--- linux-nvidia-7.0.0.orig/Changes.md +++ linux-nvidia-7.0.0/Changes.md @@ -0,0 +1,73 @@ +Driver-related patches (dropped at every major release if they are not yet upstream): + +Ubuntu-specific features not supported anymore: + +Others: +- UBUNTU: SAUCE: selftests/bpf: avoid conflicting data types in profiler.inc.h +- UBUNTU: SAUCE: Revert "arm64/fpsimd: Make kernel_neon_ API _GPL" +- UBUNTU: SAUCE: net: wwan: t7xx: PCIe reset rescan +- UBUNTU: SAUCE: PCI/ASPM: Introduce a new helper to report ASPM capability +- UBUNTU: SAUCE: Revert "mm: remove follow_pfn" + +6.14: + - UBUNTU: SAUCE: modpost: support arbitrary symbol length in modversion + - UBUNTU: SAUCE: allows to enable Rust with modversions + - UBUNTU: SAUCE: modpost: Replace 0-length array with flex-array member + +6.15: + - UBUNTU: SAUCE: objtool: Make objtool check actually fatal upon fatal errors + - UBUNTU: SAUCE: r8169: Fix compile warning + +6.16: + - UBUNTU: SAUCE: binder: turn into module - lock_vma_under_rcu() + - UBUNTU: SAUCE: arm64: dts: qcom: x1e78100-t14s: mark l12b and l15b always-on + - UBUNTU: SAUCE: arm64: dts: qcom: x1e78100-t14s: fix missing HID supplies + - UBUNTU: SAUCE: arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes + - UBUNTU: SAUCE: arm64: dts: qcom: x1e80100-t14s: Describe the Parade PS8830 retimers + - UBUNTU: SAUCE: arm64: dts: qcom: x1e80100-t14s: Enable HBR3 on external DPs + - UBUNTU: SAUCE: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + - UBUNTU: SAUCE: arm64: dts: qcom: Add EC to Lenovo Yoga Slim 7x + - UBUNTU: SAUCE: arm64: dts: qcom: x1e80100-vivobook-s15: Add bluetooth + - UBUNTU: SAUCE: arm64: dts: qcom: x1p64100-acer-swift-sf14-11 dt for Acer Swift 14 SF14-11 (touchpad fix) + - UBUNTU: SAUCE: dt-bindings: arm: qcom: Add Acer Swift 14 AI + - UBUNTU: SAUCE: arm64: dts: qcom: x1e78100-t14s: Add display brightness control support + - UBUNTU: SAUCE: gpio: aggregator: add aggr_alloc()/aggr_free() + - UBUNTU: SAUCE: gpio: aggregator: introduce basic configfs interface + - UBUNTU: SAUCE: gpio: aggregator: rename 'name' to 'key' in aggr_parse() + - UBUNTU: SAUCE: gpio: aggregator: expose aggregator created via legacy sysfs to configfs + - UBUNTU: SAUCE: drm/msm/dp: Fix support of LTTPR handling + - UBUNTU: SAUCE: drm/msm/dp: Introduce link training per-segment for LTTPRs + - UBUNTU: SAUCE: gpio: aggregator: Fix gpio_aggregator_line_alloc() checking + - UBUNTU: SAUCE: gpio: aggregator: Fix error code in gpio_aggregator_activate() + - UBUNTU: SAUCE: Revert "gcc-15: acpi: sprinkle random '__nonstring' crumbles around" + - UBUNTU: SAUCE: arm: Fix instruction set selection for GCC 11 + +6.18: + - UBUNTU: SAUCE: isapnp_init: make isa PNP scans occur async + - UBUNTU: SAUCE: sstep.c: #include + - UBUNTU: SAUCE: ptp: free ptp clock properly + - UBUNTU: SAUCE: Documentation: import error c_funcptr_sig_re, c_sig_re (sphinx-doc/sphinx@0f49e30c) + - UBUNTU: SAUCE: riscv: dts: microchip: Disable PCIe on the Icicle Kit + - UBUNTU: SAUCE: audit: fix skb leak when audit rate limit is exceeded + - UBUNTU: SAUCE: (no-up) mei_me: Add module parameter to disable MSI + +6.19: + - UBUNTU: SAUCE: media: Support ov05c10 camera sensor + - UBUNTU: SAUCE: drm/dp: clamp PWM bit count to advertised MIN and MAX capabilities + - UBUNTU: SAUCE: arm64: dts: qcom: x1e80100-asus-zenbook-a14: Enable WiFi, Bluetooth + - UBUNTU: SAUCE: leds: lp55xx -- do not force use of the fallback loader + - UBUNTU: SAUCE: phy: qcom-qmp-combo: drop regulator loads + - UBUNTU: SAUCE: phy: qcom: qmp-combo: get default qmpphy_mode from DT + - UBUNTU: SAUCE: dt-bindings: arm: qcom: Add Asus Zenbook A14 UX3407QA LCD/OLED variants + - UBUNTU: SAUCE: arm64: dts: qcom: Rework X1-based Asus Zenbook A14's displays + - Dropped lsm reverts due to fixing lockdown + +7.0: + - UBUNTU: SAUCE: arm64: dts: qcom: x1e80100-asus-vivobook: Introduce retimers, external DP + - UBUNTU: SAUCE: net: qrtr: mhi: synchronize qrtr and mhi preparation + - UBUNTU: SAUCE: wip: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + - UBUNTU: SAUCE: arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes + - UBUNTU: SAUCE: arm64: dts: qcom: x1e80100: move remaining dp0/1/2 data-lanes to SoC dtsi + - UBUNTU: SAUCE: PCI: Disable RRS polling for Intel SSDPE2KX020T8 nvme + - UBUNTU: SAUCE: Reapply "serial: 8250: Switch to nbcon console" + - UBUNTU: SAUCE: Reapply "serial: 8250: Revert "drop lockdep annotation from serial8250_clear_IER()" --- linux-nvidia-7.0.0.orig/Documentation/ABI/testing/sysfs-devices-system-cpu +++ linux-nvidia-7.0.0/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -327,6 +327,52 @@ This file is only present if the cppc-cpufreq driver is in use. +What: /sys/devices/system/cpu/cpuX/cpufreq/min_perf +Date: December 2025 +Contact: linux-pm@vger.kernel.org +Description: Minimum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file conveys the minimum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must correspond to a + performance level in the range [Lowest Performance, Highest + Performance], inclusive. The minimum must be less than or equal + to the maximum performance. The performance range can be checked + from nodes: + /sys/devices/system/cpu/cpuX/acpi_cppc/highest_perf + /sys/devices/system/cpu/cpuX/acpi_cppc/lowest_perf + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/max_perf +Date: December 2025 +Contact: linux-pm@vger.kernel.org +Description: Maximum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file conveys the maximum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must correspond to a + performance level in the range [Lowest Performance, Highest + Performance], inclusive. The performance range can be checked + from nodes: + /sys/devices/system/cpu/cpuX/acpi_cppc/highest_perf + /sys/devices/system/cpu/cpuX/acpi_cppc/lowest_perf + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/perf_limited +Date: December 2025 +Contact: linux-pm@vger.kernel.org +Description: Performance Limited + + Read/write a 32 bits value from/to this file. This file indicates + to OSPM that an unpredictable event has limited processor + performance, and the delivered performance may be less than + desired/minimum performance. + + This file is only present if the cppc-cpufreq driver is in use. What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 --- linux-nvidia-7.0.0.orig/Documentation/admin-guide/kernel-parameters.txt +++ linux-nvidia-7.0.0/Documentation/admin-guide/kernel-parameters.txt @@ -1038,6 +1038,18 @@ Format: ,,,[,] + cppc_cpufreq.auto_sel_mode= + [CPU_FREQ] Enable ACPI CPPC autonomous performance selection. + When enabled, hardware automatically adjusts CPU frequency + on all CPUs based on workload demands. In Autonomous mode, + Energy Performance Preference(EPP) hints guide hardware + toward performance(0x0) or energy efficiency (0xff). + Requires ACPI CPPC autonomous selection register support. + Format: + Default: 0 (disabled) + 0: use cpufreq governors + 1: enable if supoorted by hardware + cpuidle.off=1 [CPU_IDLE] disable the cpuidle sub-system @@ -5114,6 +5126,12 @@ nomsi [MSI] If the PCI_MSI kernel config parameter is enabled, this kernel boot option can be used to disable the use of MSI interrupts system-wide. + clearmsi [X86] Clears MSI/MSI-X enable bits early in boot + time in order to avoid issues like adapters + screaming irqs and preventing boot progress. + Also, it enforces the PCI Local Bus spec + rule that those bits should be 0 in system reset + events (useful for kexec/kdump cases). noioapicquirk [APIC] Disable all boot interrupt quirks. Safety option to keep boot IRQs enabled. This should never be necessary. --- linux-nvidia-7.0.0.orig/Documentation/admin-guide/media/amdisp4-1.rst +++ linux-nvidia-7.0.0/Documentation/admin-guide/media/amdisp4-1.rst @@ -0,0 +1,63 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: + +==================================== +AMD Image Signal Processor (amdisp4) +==================================== + +Introduction +============ + +This file documents the driver for the AMD ISP4 that is part of +AMD Ryzen AI Max 300 Series. + +The driver is located under drivers/media/platform/amd/isp4 and uses +the Media-Controller API. + +The driver exposes one video capture device to userspace and provide +web camera like interface. Internally the video device is connected +to the isp4 sub-device responsible for communication with the CCPU FW. + +Topology +======== + +.. _amdisp4_topology_graph: + +.. kernel-figure:: amdisp4.dot + :alt: Diagram of the media pipeline topology + :align: center + + + +The driver has 1 sub-device: Representing isp4 image signal processor. +The driver has 1 video device: Capture device for retrieving images. + +- ISP4 Image Signal Processing Subdevice Node + +--------------------------------------------- + +The isp4 is represented as a single V4L2 subdev, the sub-device does not +provide interface to the user space. The sub-device is connected to one video node +(isp4_capture) with immutable active link. The sub-device represents ISP with +connected sensor similar to smart cameras (sensors with integrated ISP). +sub-device has only one link to the video device for capturing the frames. +The sub-device communicates with CCPU FW for streaming configuration and +buffer management. + + +- isp4_capture - Frames Capture Video Node + +------------------------------------------ + +Isp4_capture is a capture device to capture frames to memory. +The entity is connected to isp4 sub-device. The video device +provides web camera like interface to userspace. It supports +mmap and dma buf types of memory. + +Capturing Video Frames Example +============================== + +.. code-block:: bash + + v4l2-ctl "-d" "/dev/video0" "--set-fmt-video=width=1920,height=1080,pixelformat=NV12" "--stream-mmap" "--stream-count=10" --- linux-nvidia-7.0.0.orig/Documentation/admin-guide/media/amdisp4.dot +++ linux-nvidia-7.0.0/Documentation/admin-guide/media/amdisp4.dot @@ -0,0 +1,6 @@ +digraph board { + rankdir=TB + n00000001 [label="{{} | amd isp4\n | { 0}}", shape=Mrecord, style=filled, fillcolor=green] + n00000001:port0 -> n00000003 [style=bold] + n00000003 [label="Preview\n/dev/video0", shape=box, style=filled, fillcolor=yellow] +} --- linux-nvidia-7.0.0.orig/Documentation/admin-guide/media/v4l-drivers.rst +++ linux-nvidia-7.0.0/Documentation/admin-guide/media/v4l-drivers.rst @@ -9,6 +9,7 @@ .. toctree:: :maxdepth: 2 + amdisp4-1 bttv c3-isp cafe_ccic --- linux-nvidia-7.0.0.orig/Documentation/arch/arm64/silicon-errata.rst +++ linux-nvidia-7.0.0/Documentation/arch/arm64/silicon-errata.rst @@ -214,6 +214,9 @@ +----------------+-----------------+-----------------+-----------------------------+ | ARM | SI L1 | #4311569 | ARM64_ERRATUM_4311569 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | CMN-650 | #3642720 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ ++----------------+-----------------+-----------------+-----------------------------+ | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 | +----------------+-----------------+-----------------+-----------------------------+ | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 | @@ -247,6 +250,12 @@ +----------------+-----------------+-----------------+-----------------------------+ | NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| NVIDIA | T241 MPAM | T241-MPAM-1 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ +| NVIDIA | T241 MPAM | T241-MPAM-4 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ +| NVIDIA | T241 MPAM | T241-MPAM-6 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +----------------+-----------------+-----------------+-----------------------------+ --- linux-nvidia-7.0.0.orig/Documentation/cgroups/namespace.txt +++ linux-nvidia-7.0.0/Documentation/cgroups/namespace.txt @@ -0,0 +1,142 @@ + CGroup Namespaces + +CGroup Namespace provides a mechanism to virtualize the view of the +/proc//cgroup file. The CLONE_NEWCGROUP clone-flag can be used with +clone() and unshare() syscalls to create a new cgroup namespace. +The process running inside the cgroup namespace will have its /proc//cgroup +output restricted to cgroupns-root. cgroupns-root is the cgroup of the process +at the time of creation of the cgroup namespace. + +Prior to CGroup Namespace, the /proc//cgroup file used to show complete +path of the cgroup of a process. In a container setup (where a set of cgroups +and namespaces are intended to isolate processes), the /proc//cgroup file +may leak potential system level information to the isolated processes. + +For Example: + $ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1 + +The path '/batchjobs/container_id1' can generally be considered as system-data +and its desirable to not expose it to the isolated process. + +CGroup Namespaces can be used to restrict visibility of this path. +For Example: + # Before creating cgroup namespace + $ ls -l /proc/self/ns/cgroup + lrwxrwxrwx 1 root root 0 2014-07-15 10:37 /proc/self/ns/cgroup -> cgroup:[4026531835] + $ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1 + + # unshare(CLONE_NEWCGROUP) and exec /bin/bash + $ ~/unshare -c + [ns]$ ls -l /proc/self/ns/cgroup + lrwxrwxrwx 1 root root 0 2014-07-15 10:35 /proc/self/ns/cgroup -> cgroup:[4026532183] + # From within new cgroupns, process sees that its in the root cgroup + [ns]$ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/ + + # From global cgroupns: + $ cat /proc//cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1 + + # Unshare cgroupns along with userns and mountns + # Following calls unshare(CLONE_NEWCGROUP|CLONE_NEWUSER|CLONE_NEWNS), then + # sets up uid/gid map and execs /bin/bash + $ ~/unshare -c -u -m + # Originally, we were in /batchjobs/container_id1 cgroup. Mount our own cgroup + # hierarchy. + [ns]$ mount -t cgroup cgroup /tmp/cgroup + [ns]$ ls -l /tmp/cgroup + total 0 + -r--r--r-- 1 root root 0 2014-10-13 09:32 cgroup.controllers + -r--r--r-- 1 root root 0 2014-10-13 09:32 cgroup.populated + -rw-r--r-- 1 root root 0 2014-10-13 09:25 cgroup.procs + -rw-r--r-- 1 root root 0 2014-10-13 09:32 cgroup.subtree_control + +The cgroupns-root (/batchjobs/container_id1 in above example) becomes the +filesystem root for the namespace specific cgroupfs mount. + +The virtualization of /proc/self/cgroup file combined with restricting +the view of cgroup hierarchy by namespace-private cgroupfs mount +should provide a completely isolated cgroup view inside the container. + +In its current form, the cgroup namespaces patcheset provides following +behavior: + +(1) The 'cgroupns-root' for a cgroup namespace is the cgroup in which + the process calling unshare is running. + For ex. if a process in /batchjobs/container_id1 cgroup calls unshare, + cgroup /batchjobs/container_id1 becomes the cgroupns-root. + For the init_cgroup_ns, this is the real root ('/') cgroup + (identified in code as cgrp_dfl_root.cgrp). + +(2) The cgroupns-root cgroup does not change even if the namespace + creator process later moves to a different cgroup. + $ ~/unshare -c # unshare cgroupns in some cgroup + [ns]$ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/ + [ns]$ mkdir sub_cgrp_1 + [ns]$ echo 0 > sub_cgrp_1/cgroup.procs + [ns]$ cat /proc/self/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/sub_cgrp_1 + +(3) Each process gets its CGROUPNS specific view of /proc//cgroup +(a) Processes running inside the cgroup namespace will be able to see + cgroup paths (in /proc/self/cgroup) only inside their root cgroup + [ns]$ sleep 100000 & # From within unshared cgroupns + [1] 7353 + [ns]$ echo 7353 > sub_cgrp_1/cgroup.procs + [ns]$ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/sub_cgrp_1 + +(b) From global cgroupns, the real cgroup path will be visible: + $ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/batchjobs/container_id1/sub_cgrp_1 + +(c) From a sibling cgroupns (cgroupns root-ed at a different cgroup), cgroup + path relative to its own cgroupns-root will be shown: + # ns2's cgroupns-root is at '/batchjobs/container_id2' + [ns2]$ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/../container_id2/sub_cgrp_1 + + Note that the relative path always starts with '/' to indicate that its + relative to the cgroupns-root of the caller. + +(4) Processes inside a cgroupns can move in-and-out of the cgroupns-root + (if they have proper access to external cgroups). + # From inside cgroupns (with cgroupns-root at /batchjobs/container_id1), and + # assuming that the global hierarchy is still accessible inside cgroupns: + $ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/sub_cgrp_1 + $ echo 7353 > batchjobs/container_id2/cgroup.procs + $ cat /proc/7353/cgroup + 0:cpuset,cpu,cpuacct,memory,devices,freezer,hugetlb:/../container_id2 + + Note that this kind of setup is not encouraged. A task inside cgroupns + should only be exposed to its own cgroupns hierarchy. Otherwise it makes + the virtualization of /proc//cgroup less useful. + +(5) Setns to another cgroup namespace is allowed when: + (a) the process has CAP_SYS_ADMIN in its current userns + (b) the process has CAP_SYS_ADMIN in the target cgroupns' userns + No implicit cgroup changes happen with attaching to another cgroupns. It + is expected that the somone moves the attaching process under the target + cgroupns-root. + +(6) When some thread from a multi-threaded process unshares its + cgroup-namespace, the new cgroupns gets applied to the entire process (all + the threads). For the unified-hierarchy this is expected as it only allows + process-level containerization. For the legacy hierarchies this may be + unexpected. So all the threads in the process will have the same cgroup. + +(7) The cgroup namespace is alive as long as there is atleast 1 + process inside it. When the last process exits, the cgroup + namespace is destroyed. The cgroupns-root and the actual cgroups + remain though. + +(8) Namespace specific cgroup hierarchy can be mounted by a process running + inside cgroupns: + $ mount -t cgroup -o __DEVEL__sane_behavior cgroup $MOUNT_POINT + + This will mount the unified cgroup hierarchy with cgroupns-root as the + filesystem root. The process needs CAP_SYS_ADMIN in its userns and mntns. --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,mpam-msc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Memory System Resource Partitioning and Monitoring (MPAM) + +description: | + The Arm MPAM specification can be found here: + + https://developer.arm.com/documentation/ddi0598/latest + +maintainers: + - Rob Herring + +properties: + compatible: + items: + - const: arm,mpam-msc # Further details are discoverable + - const: arm,mpam-memory-controller-msc + + reg: + maxItems: 1 + description: A memory region containing registers as defined in the MPAM + specification. + + interrupts: + minItems: 1 + items: + - description: error (optional) + - description: overflow (optional, only for monitoring) + + interrupt-names: + oneOf: + - items: + - enum: [ error, overflow ] + - items: + - const: error + - const: overflow + + arm,not-ready-us: + description: The maximum time in microseconds for monitoring data to be + accurate after a settings change. For more information, see the + Not-Ready (NRDY) bit description in the MPAM specification. + + numa-node-id: true # see NUMA binding + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^ris@[0-9a-f]+$': + type: object + additionalProperties: false + description: + RIS nodes for each resource instance in an MSC. These nodes are required + for each resource instance implementing known MPAM controls + + properties: + compatible: + enum: + - arm,mpam-cache + # Memory bandwidth + - arm,mpam-memory + + reg: + minimum: 0 + maximum: 0xf + + cpus: + description: + Phandle(s) to the CPU node(s) this RIS belongs to. By default, the parent + device's affinity is used. + + arm,mpam-device: + $ref: /schemas/types.yaml#/definitions/phandle + description: + By default, the MPAM enabled device associated with a RIS is the MSC's + parent node. It is possible for each RIS to be associated with different + devices in which case 'arm,mpam-device' should be used. + + required: + - compatible + - reg + +required: + - compatible + - reg + +dependencies: + interrupts: [ interrupt-names ] + +additionalProperties: false + +examples: + - | + L3: cache-controller@30000000 { + compatible = "arm,dsu-l3-cache", "cache"; + cache-level = <3>; + cache-unified; + + ranges = <0x0 0x30000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + msc@10000 { + compatible = "arm,mpam-msc"; + + reg = <0x10000 0x2000>; + interrupts = <1>, <2>; + interrupt-names = "error", "overflow"; + arm,not-ready-us = <1>; + /* CPU affinity implied by parent cache node */ + }; + }; + + mem: memory-controller@20000 { + compatible = "foo,a-memory-controller"; + reg = <0x20000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + msc@21000 { + compatible = "arm,mpam-memory-controller-msc", "arm,mpam-msc"; + reg = <0x21000 0x1000>; + interrupts = <3>; + interrupt-names = "error"; + arm,not-ready-us = <1>; + numa-node-id = <1>; + }; + }; + + iommu@40000 { + reg = <0x40000 0x1000>; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + msc@41000 { + compatible = "arm,mpam-msc"; + reg = <0 0x1000>; + interrupts = <5>, <6>; + interrupt-names = "error", "overflow"; + arm,not-ready-us = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + ris@2 { + compatible = "arm,mpam-cache"; + reg = <0>; + // TODO: How to map to device(s)? + }; + }; + }; + + msc@80000 { + compatible = "foo,a-standalone-msc"; + reg = <0x80000 0x1000>; + + clocks = <&clks 123>; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + msc@10000 { + compatible = "arm,mpam-msc"; + + reg = <0x10000 0x2000>; + interrupts = <7>; + interrupt-names = "overflow"; + arm,not-ready-us = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + ris@0 { + compatible = "arm,mpam-cache"; + reg = <0>; + arm,mpam-device = <&L2_0>; + }; + + ris@1 { + compatible = "arm,mpam-memory"; + reg = <1>; + arm,mpam-device = <&mem>; + }; + }; + }; + +... --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/arm/qcom.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1102,6 +1102,7 @@ - dell,inspiron-14-plus-7441 - dell,latitude-7455 - dell,xps13-9345 + - hp,elitebook-6-g1q - hp,elitebook-ultra-g1q - hp,omnibook-x14 - lenovo,yoga-slim7x @@ -1131,6 +1132,13 @@ - items: - enum: + - acer,swift-sf14-11 + - const: qcom,x1p64100 + - const: qcom,x1e80100 + + - items: + - enum: + - asus,vivobook-s15-x1p4 - hp,omnibook-x14-fe1 - lenovo,thinkbook-16 - qcom,x1p42100-crd --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-slim7x-ec.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-slim7x-ec.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/platform/lenovo,yoga-slim7x-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lenovo Yoga Slim 7x Embedded Controller. + +maintainers: + - Maya Matuszczyk + +description: + The Lenovo Yoga Slim 7x has an EC which handles some minor functions, like + power LED or some special keys on the keyboard. This bindings describes + how it is connected + +properties: + compatible: + const: lenovo,yoga-slim7x-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - |+ + #include + i2c5 { + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "lenovo,yoga-slim7x-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8350-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Venus video encode and decode accelerators + +maintainers: + - Konrad Dybcio + +description: | + The Venus Iris2 IP is a video encode and decode accelerator present + on Qualcomm platforms + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + enum: + - qcom,sc8280xp-venus + - qcom,sm8350-venus + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + resets: + maxItems: 1 + + reset-names: + items: + - const: core + + power-domains: + maxItems: 3 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mx + + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + - const: video-llcc + + operating-points-v2: true + opp-table: + type: object + + iommus: + maxItems: 1 + + video-decoder: + type: object + + properties: + compatible: + const: venus-decoder + + required: + - compatible + + additionalProperties: false + + video-encoder: + type: object + + properties: + compatible: + const: venus-encoder + + required: + - compatible + + additionalProperties: false + +required: + - compatible + - power-domain-names + - iommus + - video-decoder + - video-encoder + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + venus: video-codec@aa00000 { + compatible = "qcom,sm8350-venus"; + reg = <0x0aa00000 0x100000>; + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "core"; + + power-domains = <&videocc MVS0C_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SM8350_MX>; + power-domain-names = "venus", + "vcodec0", + "mx"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "cpu-cfg", + "video-mem", + "video-llcc"; + + operating-points-v2 = <&venus_opp_table>; + iommus = <&apps_smmu 0x2100 0x400>; + memory-region = <&pil_video_mem>; + + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + }; --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -14,7 +14,11 @@ properties: compatible: - const: qcom,x1e80100-camss + oneOf: + - const: qcom,x1e80100-camss + - items: + - const: qcom,x1e80100-camss + - const: simple-mfd reg: maxItems: 17 @@ -39,6 +43,14 @@ - const: vfe_lite0 - const: vfe_lite1 + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + ranges: true + clocks: maxItems: 29 @@ -104,7 +116,22 @@ - const: sf_icp_mnoc iommus: - maxItems: 8 + oneOf: + - items: + - description: S1 HLOS IFE and IFE_LITE non-protected read + - description: S1 HLOS IFE and IFE_LITE non-protected write + - description: S1 HLOS SFE non-protected read + - description: S1 HLOS SFE non-protected write + - description: S1 HLOS CDM IFE non-protected + - description: Legacy slot 0 - do not use + - description: Legacy slot 1 - do not use + - description: Legacy slot 2 - do not use + - items: + - description: S1 HLOS IFE and IFE_LITE non-protected read + - description: S1 HLOS IFE and IFE_LITE non-protected write + - description: S1 HLOS SFE non-protected read + - description: S1 HLOS SFE non-protected write + - description: S1 HLOS CDM IFE non-protected power-domains: items: @@ -126,11 +153,22 @@ description: 1.2V supply to a PHY. + phys: + maxItems: 4 + + phy-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + ports: $ref: /schemas/graph.yaml#/properties/ports description: - CSI input ports. + CSI input ports. Supports either standard single sensor mode or + Qualcomm's combo mode with one sensor in 2x1 + 1x1 data-lane, clock-lane mode. patternProperties: "^port@[0-3]$": @@ -138,26 +176,94 @@ unevaluatedProperties: false description: - Input port for receiving CSI data from a CSIPHY. + Input port for receiving CSI data. properties: - endpoint: + endpoint@0: $ref: video-interfaces.yaml# unevaluatedProperties: false + description: + Endpoint for receiving a single sensor input (or first leg of combo). + properties: data-lanes: minItems: 1 - maxItems: 4 + maxItems: 4 # Base max allows 4 (for D-PHY) + + clock-lanes: + maxItems: 1 bus-type: enum: - 1 # MEDIA_BUS_TYPE_CSI2_CPHY - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + endpoint@1: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + description: + Endpoint for receiving the second leg of a combo sensor input. + + properties: + data-lanes: + maxItems: 1 + + clock-lanes: + maxItems: 1 + + bus-type: + const: 4 # Combo is D-PHY specific + required: - data-lanes + allOf: + # Case 1: Combo Mode (endpoint@1 is present) + # If endpoint@1 exists, we restrict endpoint@0 to 2 lanes (D-PHY split) + - if: + required: + - endpoint@1 + then: + properties: + endpoint@0: + properties: + data-lanes: + minItems: 2 + maxItems: 2 + bus-type: + const: 4 + endpoint@1: + properties: + data-lanes: + minItems: 1 + maxItems: 1 + bus-type: + const: 4 + + # Case 2: Single Mode (endpoint@1 is missing) + # We explicitly allow up to 4 lanes here to cover the D-PHY use case. + - if: + not: + required: + - endpoint@1 + then: + properties: + endpoint@0: + properties: + data-lanes: + minItems: 1 + maxItems: 4 + +patternProperties: + "^phy@[0-9a-f]+$": + $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml + unevaluatedProperties: false + + "^opp-table(-.*)?$": + type: object + required: - compatible - reg @@ -171,8 +277,6 @@ - iommus - power-domains - power-domain-names - - vdd-csiphy-0p8-supply - - vdd-csiphy-1p2-supply - ports additionalProperties: false @@ -184,6 +288,7 @@ #include #include #include + #include #include soc { @@ -191,7 +296,7 @@ #size-cells = <2>; camss: isp@acb7000 { - compatible = "qcom,x1e80100-camss"; + compatible = "qcom,x1e80100-camss", "simple-mfd"; reg = <0 0x0acb7000 0 0x2000>, <0 0x0acb9000 0 0x2000>, @@ -229,6 +334,10 @@ "vfe_lite0", "vfe_lite1"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, <&camcc CAM_CC_CORE_AHB_CLK>, @@ -332,13 +441,10 @@ "sf_icp_mnoc"; iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x820 0x60>, + <&apps_smmu 0x840 0x60>, <&apps_smmu 0x860 0x60>, - <&apps_smmu 0x1800 0x60>, - <&apps_smmu 0x1860 0x60>, - <&apps_smmu 0x18e0 0x00>, - <&apps_smmu 0x1980 0x20>, - <&apps_smmu 0x1900 0x00>, - <&apps_smmu 0x19a0 0x20>; + <&apps_smmu 0x18a0 0x0>; power-domains = <&camcc CAM_CC_IFE_0_GDSC>, <&camcc CAM_CC_IFE_1_GDSC>, --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -84,6 +84,19 @@ mode-switch: true orientation-switch: true + qcom,combo-initial-mode: + description: + Describe the initial mode of the Combo PHY configuration. + The Combo PHY is a wrapper on top of a DP PHY and an USB3 PHY, + sharing the same SuperSpeed lanes with either DisplayPort over + the 4 lanes (dp), USB3 on a pair of lanes (usb3) or both + technologies in a 2+2 configuration (usb3+dp) as default. + default: usb3+dp + enum: + - usb3+dp + - usb3 + - dp + ports: $ref: /schemas/graph.yaml#/properties/ports --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CSI2 PHY + +maintainers: + - Bryan O'Donoghue + +description: + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY + modes. + +properties: + compatible: + const: qcom,x1e80100-csi2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: csiphy + - const: csiphy_timer + - const: camnoc_axi + - const: cpas_ahb + + interrupts: + maxItems: 1 + + operating-points-v2: + maxItems: 1 + + power-domains: + items: + - description: TITAN TOP GDSC + - description: MXC or MXA voltage rail + - description: MMCX voltage rail + + power-domain-names: + items: + - const: top + - const: mx + - const: mmcx + + vdda-0p8-supply: + description: Phandle to a 0.8V regulator supply to a PHY. + + vdda-1p2-supply: + description: Phandle to 1.2V regulator supply to a PHY. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - interrupts + - operating-points-v2 + - power-domains + - power-domain-names + - vdda-0p8-supply + - vdda-1p2-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + csiphy@ace4000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0x0ace4000 0x2000>; + #phy-cells = <1>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 = <&csiphy_opp_table>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "top", + "mx", + "mmcx"; + + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + }; + + csiphy_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; --- linux-nvidia-7.0.0.orig/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml +++ linux-nvidia-7.0.0/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml @@ -16,6 +16,8 @@ DAC for headphone output, two integrated Class D amplifiers for loudspeakers, and two ADCs for wired headset microphone input or stereo line input. PDM inputs are provided for digital microphones. + CS42L43B variant adds dedicated PDM interface, SoundWire Clock Gearing + support and more decimators to ISRCs. allOf: - $ref: dai-common.yaml# @@ -24,6 +26,7 @@ compatible: enum: - cirrus,cs42l43 + - cirrus,cs42l43b reg: maxItems: 1 --- linux-nvidia-7.0.0.orig/Documentation/filesystems/resctrl.rst +++ linux-nvidia-7.0.0/Documentation/filesystems/resctrl.rst @@ -228,12 +228,11 @@ user can request. "bandwidth_gran": - The granularity in which the memory bandwidth + The approximate granularity in which the memory bandwidth percentage is allocated. The allocated b/w percentage is rounded off to the next - control step available on the hardware. The - available bandwidth control steps are: - min_bandwidth + N * bandwidth_gran. + control step available on the hardware. The available + steps are at least as small as this value. "delay_linear": Indicates if the delay scale is linear or --- linux-nvidia-7.0.0.orig/Kbuild +++ linux-nvidia-7.0.0/Kbuild @@ -109,3 +109,4 @@ obj-y += virt/ obj-y += $(ARCH_DRIVERS) obj-$(CONFIG_DRM_HEADER_TEST) += include/ +obj-y += ubuntu/ --- linux-nvidia-7.0.0.orig/Kconfig +++ linux-nvidia-7.0.0/Kconfig @@ -19,6 +19,8 @@ source "drivers/Kconfig" +source "ubuntu/Kconfig" + source "fs/Kconfig" source "security/Kconfig" --- linux-nvidia-7.0.0.orig/MAINTAINERS +++ linux-nvidia-7.0.0/MAINTAINERS @@ -199,6 +199,18 @@ F: Documentation/devicetree/bindings/power/supply/*ab8500* F: drivers/power/supply/*ab8500* +AAEON DEVICE DRIVER WITH WMI INTERFACE +M: Edward Lin +M: Kunyang Fan +M: Frank Hsieh +M: Jacob Wu +S: Supported +F: drivers/gpio/gpio-aaeon.c +F: drivers/hwmon/hwmon-aaeon.c +F: drivers/leds/leds-aaeon.c +F: drivers/mfd/mfd-aaeon.c +F: drivers/watchdog/wdt_aaeon.c + ABI/API L: linux-api@vger.kernel.org F: include/linux/syscalls.h @@ -1160,6 +1172,31 @@ F: drivers/iommu/amd/ F: include/linux/amd-iommu.h +AMD ISP4 DRIVER +M: Bin Du +M: Nirujogi Pratap +L: linux-media@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media.git +F: Documentation/admin-guide/media/amdisp4-1.rst +F: Documentation/admin-guide/media/amdisp4.dot +F: drivers/media/platform/amd/Kconfig +F: drivers/media/platform/amd/Makefile +F: drivers/media/platform/amd/isp4/Kconfig +F: drivers/media/platform/amd/isp4/Makefile +F: drivers/media/platform/amd/isp4/isp4.c +F: drivers/media/platform/amd/isp4/isp4.h +F: drivers/media/platform/amd/isp4/isp4_debug.c +F: drivers/media/platform/amd/isp4/isp4_debug.h +F: drivers/media/platform/amd/isp4/isp4_fw_cmd_resp.h +F: drivers/media/platform/amd/isp4/isp4_hw_reg.h +F: drivers/media/platform/amd/isp4/isp4_interface.c +F: drivers/media/platform/amd/isp4/isp4_interface.h +F: drivers/media/platform/amd/isp4/isp4_subdev.c +F: drivers/media/platform/amd/isp4/isp4_subdev.h +F: drivers/media/platform/amd/isp4/isp4_video.c +F: drivers/media/platform/amd/isp4/isp4_video.h + AMD KFD M: Felix Kuehling L: amd-gfx@lists.freedesktop.org @@ -14479,6 +14516,12 @@ S: Maintained F: drivers/platform/x86/lenovo/wmi-hotkey-utilities.c +LENOVO YOGA SLIM 7X EC DRIVER +M: Maya Matuszczyk +S: Maintained +F: Documentation/devicetree/bindings/platform/lenovo,yoga-slim7x-ec.yaml +F: drivers/platform/arm64/lenovo-yoga-slim7x.c + LETSKETCH HID TABLET DRIVER M: Hans de Goede L: linux-input@vger.kernel.org @@ -21797,6 +21840,17 @@ F: Documentation/devicetree/bindings/media/qcom,*-iris.yaml F: drivers/media/platform/qcom/iris/ +QUALCOMM MIPI CSI2 PHY DRIVER +M: Bryan O'Donoghue +L: linux-phy@lists.infradead.org +L: linux-media@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/phy/qcom,*-csi2-phy.yaml +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.c +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.h +F: include/dt-bindings/phy/phy-qcom-mipi-csi2* + QUALCOMM NAND CONTROLLER DRIVER M: Manivannan Sadhasivam L: linux-mtd@lists.infradead.org --- linux-nvidia-7.0.0.orig/Makefile +++ linux-nvidia-7.0.0/Makefile @@ -585,6 +585,9 @@ -I$(objtree)/include \ $(USERINCLUDE) +# UBUNTU: Include our third party driver stuff too +LINUXINCLUDE += -I$(srctree)/ubuntu/include + KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE KBUILD_CFLAGS := @@ -1416,8 +1419,9 @@ quiet_cmd_headers_install = INSTALL $(INSTALL_HDR_PATH)/include cmd_headers_install = \ mkdir -p $(INSTALL_HDR_PATH); \ - rsync -mrl --include='*/' --include='*\.h' --exclude='*' \ - usr/include $(INSTALL_HDR_PATH) + find usr/include -type f -name '*.h' -print0 | \ + tar -czf - --null --no-recursion --no-wildcards-match-slash -T- | \ + tar -xzf - --strip-components=1 -C $(INSTALL_HDR_PATH) PHONY += headers_install headers_install: headers @@ -1434,6 +1438,7 @@ else $(Q)$(MAKE) $(hdr-inst)=include/uapi $(Q)$(MAKE) $(hdr-inst)=arch/$(SRCARCH)/include/uapi + $(Q)$(MAKE) $(hdr-inst)=ubuntu/include dst=include oldheaders= endif ifdef CONFIG_HEADERS_INSTALL @@ -1659,7 +1664,7 @@ # Directories & files removed with 'make mrproper' MRPROPER_FILES += include/config include/generated \ arch/$(SRCARCH)/include/generated .objdiff \ - debian snap tar-install PKGBUILD pacman \ + snap tar-install PKGBUILD pacman \ .config .config.old .version \ Module.symvers \ certs/signing_key.pem \ --- linux-nvidia-7.0.0.orig/Ubuntu.md +++ linux-nvidia-7.0.0/Ubuntu.md @@ -0,0 +1,8 @@ +Name: linux-nvidia +Version: 7.0.0 +Series: 26.04 (resolute) +Description: + This is the source code for the NVIDIA linux kernel for the 26.04 series. This + source tree is used to produce the flavours: nvidia, nvidia-64k. + This kernel is configured to support the widest range of desktop, laptop and + server configurations. --- linux-nvidia-7.0.0.orig/arch/arm64/Kconfig +++ linux-nvidia-7.0.0/arch/arm64/Kconfig @@ -1660,7 +1660,7 @@ # 64K | 29 | 16 | 13 | 13 | config ARCH_FORCE_MAX_ORDER int - default "13" if ARM64_64K_PAGES + default "13" if ARM64_64K_PAGES || (ARCH_THUNDER && ARM64_4K_PAGES) default "11" if ARM64_16K_PAGES default "10" help @@ -2017,8 +2017,8 @@ config ARM64_MPAM bool "Enable support for MPAM" - select ARM64_MPAM_DRIVER if EXPERT # does nothing yet - select ACPI_MPAM if ACPI + select ARM64_MPAM_DRIVER + select ARCH_HAS_CPU_RESCTRL help Memory System Resource Partitioning and Monitoring (MPAM) is an optional extension to the Arm architecture that allows each @@ -2040,6 +2040,8 @@ MPAM is exposed to user-space via the resctrl pseudo filesystem. + This option enables the extra context switch code. + endmenu # "ARMv8.4 architectural features" menu "ARMv8.5 architectural features" --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/Makefile +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/Makefile @@ -374,21 +374,31 @@ dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-medion-sprchrgd-14-s1.dtb x1e80100-medion-sprchrgd-14-s1-el2.dtb +x1e80100-microsoft-denali-oled-el2-dtbs := x1e80100-microsoft-denali-oled.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-denali-oled.dtb x1e80100-microsoft-denali-oled-el2.dtb x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb x1e80100-qcp-el2-dtbs := x1e80100-qcp.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb x1e80100-qcp-el2.dtb +x1p42100-acer-swift-go14-01-el2-dtbs := x1p42100-acer-swift-go14-01.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-acer-swift-go14-01.dtb x1p42100-acer-swift-go14-01-el2.dtb +x1p42100-asus-vivobook-s15-el2-dtbs := x1p42100-asus-vivobook-s15.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-vivobook-s15.dtb x1p42100-asus-vivobook-s15-el2.dtb x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb x1p42100-asus-zenbook-a14-lcd-el2-dtbs := x1p42100-asus-zenbook-a14-lcd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14-lcd.dtb x1p42100-asus-zenbook-a14-lcd-el2.dtb x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb +x1p42100-hp-elitebook-6-g1q-el2-dtbs := x1p42100-hp-elitebook-6-g1q.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-elitebook-6-g1q.dtb x1p42100-hp-elitebook-6-g1q-el2.dtb x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb +x1p64100-acer-swift-sf14-11-el2-dtbs := x1p64100-acer-swift-sf14-11.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p64100-acer-swift-sf14-11.dtb x1p64100-acer-swift-sf14-11-el2.dtb --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -5464,6 +5466,466 @@ #power-domain-cells = <1>; }; + cci0: cci@ac15000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac15000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac16000 0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: isp@acb7000 { + compatible = "qcom,x1e80100-camss", "simple-mfd"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x820 0x60>, + <&apps_smmu 0x840 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x18a0 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + phys = <&csiphy0 PHY_TYPE_DPHY>, <&csiphy1 PHY_TYPE_DPHY>, + <&csiphy2 PHY_TYPE_DPHY>, <&csiphy4 PHY_TYPE_DPHY>; + phy-names = "csiphy0", "csiphy1", + "csiphy2", "csiphy4"; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy0_inep0: endpoint@0 { + reg = <0>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy1_inep0: endpoint@0 { + reg = <0>; + }; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy2_inep0: endpoint@0 { + reg = <0>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + camss_csiphy4_inep0: endpoint@0 { + reg = <0>; + }; + }; + }; + + csiphy0: phy@ace4000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace4000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "top", + "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy1: phy@ace6000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace6000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "top", + "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy2: phy@ace8000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0ace8000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "top", + "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy4: phy@acec000 { + compatible = "qcom,x1e80100-csi2-phy"; + reg = <0 0x0acec000 0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names = "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 = <&csiphy_mxa_opp_table>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "top", + "mx", + "mmcx"; + + #phy-cells = <1>; + + status = "disabled"; + }; + + csiphy_mxc_opp_table: opp-table-mxc { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; + + csiphy_mxa_opp_table: opp-table-mxa { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,x1e80100-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; @@ -6098,6 +6560,78 @@ gpio-ranges = <&tlmm 0 0 239>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105", "gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235", "gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105", "gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235", "gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-down; + }; + }; + edp0_hpd_default: edp0-hpd-default-state { pins = "gpio119"; function = "edp0_hot"; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -490,18 +490,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -581,18 +581,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -703,18 +703,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; @@ -1474,6 +1462,11 @@ status = "okay"; }; +&venus { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcvss8280.mbn"; + status = "okay"; +}; + &wsamacro { status = "okay"; }; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -443,18 +443,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -560,18 +560,6 @@ status = "okay"; }; -&gpi_dma0 { - status = "okay"; -}; - -&gpi_dma1 { - status = "okay"; -}; - -&gpi_dma2 { - status = "okay"; -}; - &gpu { status = "okay"; }; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -696,6 +697,11 @@ no-map; }; + pil_video_mem: pil_video_region@86700000 { + reg = <0 0x86700000 0 0x500000>; + no-map; + }; + pil_adsp_mem: adsp-region@86c00000 { reg = <0 0x86c00000 0 0x2000000>; no-map; @@ -4181,6 +4187,86 @@ }; }; + venus: video-codec@aa00000 { + compatible = "qcom,sm8350-venus"; + reg = <0 0x0aa00000 0 0x100000>; + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + power-domains = <&videocc MVS0C_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SC8280XP_MX>; + power-domain-names = "venus", + "vcodec0", + "mx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "cpu-cfg", + "video-mem", + "video-llcc"; + + operating-points-v2 = <&venus_opp_table>; + iommus = <&apps_smmu 0x2e00 0x400>; + memory-region = <&pil_video_mem>; + + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1098000000 { + opp-hz = /bits/ 64 <1098000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-1332000000 { + opp-hz = /bits/ 64 <1332000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + videocc: clock-controller@abf0000 { + compatible = "qcom,sc8280xp-videocc"; + reg = <0 0x0abf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + cci0: cci@ac4a000 { compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg = <0 0x0ac4a000 0 0x1000>; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1-acer-swift-14.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1-acer-swift-14.dtsi @@ -0,0 +1,1473 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* +* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +* Copyright (c) 2024, Linaro Limited +* Copyright (c) 2024, Victorien Alric - vickdu31 +*/ + +#include +#include +#include +#include +#include + +/ { + model = "Acer Swift AI"; + compatible = "acer,swift-14", "qcom,x1e80100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-ACER-SWIFT-14"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_1p15_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_1p8_reg_en>; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_3p3_reg_en>; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + + //vdd-supply = <&vreg_misc_3p3>; + //vddl-supply = <&vreg_l12b_1p2>; + + //pinctrl-0 = <&tpad_default>; + //pinctrl-names = "default"; + }; + + /* ELAN06F1 or SYNA06F2 */ + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "xo"; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + clock-names = "xo"; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* ILIT2911 or GTCH1563 */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c20 { + clock-frequency = <400000>; + + status = "okay"; + +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + backlight = <&backlight>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + bias-disable; + }; +}; + +&pm8550ve_9_gpios { + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + bias-disable; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; + +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&pmc8380_5_gpios { + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + bias-disable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <72 2>, /* Secure EC I2C connection (?) */ + <238 1>; /* UFS Reset */ + + edp_hpd_default: edp-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts0_default: ts0-default-state { + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + bt_en_default: bt-en-sleep { + pins = "gpio116"; + function = "gpio"; + output-low; + bias-disable; + qcom,drive-strength = <16>; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart14 { + status = "okay"; + bluetooth: bt_wcn7850 { + compatible = "qcom,wcn7850-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_default>; + enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + max-speed = <3200000>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi @@ -0,0 +1,1362 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu + */ + +#include +#include +#include +#include + +#include "hamoa-pmics.dtsi" + +/ { + chassis-type = "laptop"; + + aliases { + serial1 = &uart14; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Left-side port, closer to the screen */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side port, farther from the screen */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; + + /* EC @ 0x76 */ +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna56ac03", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + bias-pull-down; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio116"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -69,14 +70,11 @@ pinctrl-0 = <&cam_indicator_en>; pinctrl-names = "default"; - led-camera-indicator { - label = "white:camera-indicator"; + privacy_led: privacy-led { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; - /* Reuse as a panic indicator until we get a "camera on" trigger */ panic-indicator; }; }; @@ -507,6 +505,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -757,6 +762,86 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; +}; + +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + csiphy4_ep: endpoint@4 { + reg = <4>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02c10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam_rgb_default>; + pinctrl-names = "default"; + + leds = <&privacy_led>; + led-names = "privacy"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02c10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + phy-type = ; + + status = "okay"; }; &i2c0 { @@ -1236,6 +1321,22 @@ bias-disable; }; + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -17,6 +18,7 @@ aliases { serial0 = &uart21; + serial1 = &uart14; }; wcd938x: audio-codec { @@ -498,6 +500,48 @@ regulator-boot-on; }; + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -513,6 +557,65 @@ regulator-boot-on; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -865,12 +968,101 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vreg_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1808000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + }; }; &gpu { status = "okay"; }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + camss_csiphy4_inep0: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&ov08x40_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov08x40"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam_rgb_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov08x40_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&camss_csiphy4_inep0>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; @@ -1234,6 +1426,23 @@ status = "okay"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie5 { vddpe-3v3-supply = <&vreg_wwan>; @@ -1491,6 +1700,22 @@ <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; @@ -1679,6 +1904,20 @@ output-low; }; + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wwan_sw_en: wwan-sw-en-state { pins = "gpio221"; function = "gpio"; @@ -1687,6 +1926,23 @@ }; }; +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "hamoa-pmics.dtsi" @@ -792,6 +793,66 @@ }; }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + camss_csiphy4_inep0: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02e10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@10 { + compatible = "ovti,ov02e10"; + reg = <0x10>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_cam_1p8>; + + port { + ov02e10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <360000000>; + remote-endpoint = <&camss_csiphy4_inep0>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include @@ -20,6 +22,10 @@ compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100"; chassis-type = "laptop"; + aliases { + serial1 = &uart14; + }; + wcd938x: audio-codec { compatible = "qcom,wcd9385-codec"; @@ -62,6 +68,21 @@ }; }; + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + privacy_led: privacy-led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + hdmi-bridge { compatible = "realtek,rtd2171"; @@ -360,6 +381,48 @@ regulator-boot-on; }; + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -502,6 +565,65 @@ }; }; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -562,6 +684,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -805,6 +934,121 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p2: ldo1 { + regulator-name = "vreg_l1m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l2m_1p2: ldo2 { + regulator-name = "vreg_l2m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vreg_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l5m_2p8: ldo5 { + regulator-name = "vreg_l5m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; + +}; + +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + camss_csiphy4_inep0: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02c10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + leds = <&privacy_led>; + led-names = "privacy"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7m_2p8>; + dvdd-supply = <&vreg_l2m_1p2>; + dovdd-supply = <&vreg_l4m_1p8>; + + port { + ov02c10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&camss_csiphy4_inep0>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; }; &gpu { @@ -1176,6 +1420,21 @@ &pcie4_port0 { reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; }; &pcie5 { @@ -1388,12 +1647,35 @@ <72 2>, /* Secure EC I2C connection (?) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + ec_int_n_default: ec-int-n-state { pins = "gpio66"; function = "gpio"; bias-disable; }; + cam_indicator_en: cam-indicator-en-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + eusb3_reset_n: eusb3-reset-n-state { pins = "gpio6"; function = "gpio"; @@ -1583,6 +1865,20 @@ output-low; }; + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wwan_sw_en: wwan-sw-en-state { pins = "gpio221"; function = "gpio"; @@ -1591,6 +1887,23 @@ }; }; +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &usb_1_ss0_hsphy { vdd-supply = <&vreg_l3j_0p8>; vdda12-supply = <&vreg_l2j_1p2>; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -6,1024 +6,22 @@ /dts-v1/; -#include -#include -#include -#include - #include "hamoa.dtsi" -#include "hamoa-pmics.dtsi" +#include "x1-asus-vivobook-s15.dtsi" / { model = "ASUS Vivobook S 15"; compatible = "asus,vivobook-s15", "qcom,x1e80100"; chassis-type = "laptop"; - - aliases { - serial1 = &uart14; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&hall_int_n_default>; - pinctrl-names = "default"; - - switch-lid { - gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - wakeup-event-action = ; - }; - }; - - hdmi-bridge { - compatible = "parade,ps185hdm"; - - pinctrl-0 = <&hdmi_hpd_default>; - pinctrl-names = "default"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_bridge_dp_in: endpoint { - remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_bridge_tmds_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&hdmi_bridge_tmds_out>; - }; - }; - }; - - pmic-glink { - compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", - "qcom,pmic-glink"; - orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, - <&tlmm 123 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - /* Left-side port, closer to the screen */ - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss0_hs_in: endpoint { - remote-endpoint = <&usb_1_ss0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&retimer_ss0_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss0_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss0_con_sbu_out>; - }; - }; - }; - }; - - /* Left-side port, farther from the screen */ - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss1_hs_in: endpoint { - remote-endpoint = <&usb_1_ss1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&retimer_ss1_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss1_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss1_con_sbu_out>; - }; - }; - }; - }; - }; - - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-always-on; - regulator-boot-on; - }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p15: regulator-rtmr0-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p8: regulator-rtmr0-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_3p3: regulator-rtmr0-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_1p15: regulator-rtmr1-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_1p8: regulator-rtmr1-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_3p3: regulator-rtmr1-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vph_pwr: regulator-vph-pwr { - compatible = "regulator-fixed"; - - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - - regulator-always-on; - regulator-boot-on; - }; - - /* - * TODO: These two regulators are actually part of the removable M.2 - * card and not the CRD mainboard. Need to describe this differently. - * Functionally it works correctly, because all we need to do is to - * turn on the actual 3.3V supply above. - */ - vreg_wcn_0p95: regulator-wcn-0p95 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_0P95"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_1p9: regulator-wcn-1p9 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_1P9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_3p3: regulator-wcn-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wcn_sw_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - wcn7850-pmu { - compatible = "qcom,wcn7850-pmu"; - - vdd-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_l15b_1p8>; - vddaon-supply = <&vreg_wcn_0p95>; - vdddig-supply = <&vreg_wcn_0p95>; - vddrfa1p2-supply = <&vreg_wcn_1p9>; - vddrfa1p8-supply = <&vreg_wcn_1p9>; - - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; - pinctrl-names = "default"; - - regulators { - vreg_pmu_rfa_cmn: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn"; - }; - - vreg_pmu_aon_0p59: ldo1 { - regulator-name = "vreg_pmu_aon_0p59"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p85: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p85"; - }; - - vreg_pmu_btcmx_0p85: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p85"; - }; - - vreg_pmu_rfa_0p8: ldo5 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo6 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p8: ldo7 { - regulator-name = "vreg_pmu_rfa_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo8 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_pcie_1p8: ldo9 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - }; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8550-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob1-supply = <&vph_pwr>; - vdd-bob2-supply = <&vph_pwr>; - vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; - vdd-l2-l13-l14-supply = <&vreg_bob1>; - vdd-l5-l16-supply = <&vreg_bob1>; - vdd-l6-l7-supply = <&vreg_bob2>; - vdd-l8-l9-supply = <&vreg_bob1>; - vdd-l12-supply = <&vreg_s5j_1p2>; - vdd-l15-supply = <&vreg_s4c_1p8>; - vdd-l17-supply = <&vreg_bob2>; - - vreg_bob1: bob1 { - regulator-name = "vreg_bob1"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - - vreg_bob2: bob2 { - regulator-name = "vreg_bob2"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l2b_3p0: ldo2 { - regulator-name = "vreg_l2b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = ; - }; - - vreg_l4b_1p8: ldo4 { - regulator-name = "vreg_l4b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13b_3p0: ldo13 { - regulator-name = "vreg_l13b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l14b_3p0: ldo14 { - regulator-name = "vreg_l14b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l15b_1p8: ldo15 { - regulator-name = "vreg_l15b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s4-supply = <&vph_pwr>; - - vreg_l3c_0p8: ldo3 { - regulator-name = "vreg_l3c_0p8"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - - vreg_s4c_1p8: smps4 { - regulator-name = "vreg_s4c_1p8"; - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "d"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s4c_1p8>; - vdd-s1-supply = <&vph_pwr>; - - vreg_l1d_0p8: ldo1 { - regulator-name = "vreg_l1d_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2d_0p9: ldo2 { - regulator-name = "vreg_l2d_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3d_1p8: ldo3 { - regulator-name = "vreg_l3d_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-3 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s5j_1p2>; - - vreg_l2e_0p8: ldo2 { - regulator-name = "vreg_l2e_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3e_1p2: ldo3 { - regulator-name = "vreg_l3e_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-4 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s5j_1p2>; - vdd-s1-supply = <&vph_pwr>; - - vreg_s1f_0p7: smps1 { - regulator-name = "vreg_s1f_0p7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - }; - - regulators-6 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "i"; - - vdd-l1-supply = <&vreg_s4c_1p8>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - - vreg_l3i_0p8: ldo3 { - regulator-name = "vreg_l3i_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; - - regulators-7 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "j"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s5-supply = <&vph_pwr>; - - vreg_s5j_1p2: smps5 { - regulator-name = "vreg_s5j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l1j_0p8: ldo1 { - regulator-name = "vreg_l1j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2j_1p2: ldo2 { - regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1256000>; - regulator-initial-mode = ; - }; - - vreg_l3j_0p8: ldo3 { - regulator-name = "vreg_l3j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; -}; - -&gpu { - status = "okay"; }; &gpu_zap_shader { firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn"; }; -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-0 = <&tpad_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x08>; - - clocks = <&rpmhcc RPMH_RF_CLK3>; - - vdd-supply = <&vreg_rtmr0_1p15>; - vdd33-supply = <&vreg_rtmr0_3p3>; - vdd33-cap-supply = <&vreg_rtmr0_3p3>; - vddar-supply = <&vreg_rtmr0_1p15>; - vddat-supply = <&vreg_rtmr0_1p15>; - vddio-supply = <&vreg_rtmr0_1p8>; - - reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr0_default>; - pinctrl-names = "default"; - - orientation-switch; - retimer-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss0_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss0_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; - - eusb5_repeater: redriver@43 { - compatible = "nxp,ptn3222"; - reg = <0x43>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb5_reset_n>; - pinctrl-names = "default"; - }; - - eusb3_repeater: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb3_reset_n>; - pinctrl-names = "default"; - }; - - eusb6_repeater: redriver@4f { - compatible = "nxp,ptn3222"; - reg = <0x4f>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb6_reset_n>; - pinctrl-names = "default"; - }; - - /* EC @ 0x76 */ -}; - -&i2c7 { - clock-frequency = <400000>; - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x8>; - - clocks = <&rpmhcc RPMH_RF_CLK4>; - - vdd-supply = <&vreg_rtmr1_1p15>; - vdd33-supply = <&vreg_rtmr1_3p3>; - vdd33-cap-supply = <&vreg_rtmr1_3p3>; - vddar-supply = <&vreg_rtmr1_1p15>; - vddat-supply = <&vreg_rtmr1_1p15>; - vddio-supply = <&vreg_rtmr1_1p8>; - - reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr1_default>; - pinctrl-names = "default"; - - retimer-switch; - orientation-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss1_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss1_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss1_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; - }; - }; - }; - }; -}; - &iris { firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; - status = "okay"; -}; -&mdss { - status = "okay"; -}; - -&mdss_dp0 { - status = "okay"; -}; - -&mdss_dp0_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp1 { - status = "okay"; -}; - -&mdss_dp1_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp2 { - status = "okay"; -}; - -&mdss_dp2_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp3 { - /delete-property/ #sound-dai-cells; - - pinctrl-0 = <&edp0_hpd_default>; - pinctrl-names = "default"; - - status = "okay"; - - aux-bus { - panel { - compatible = "samsung,atna56ac03", "samsung,atna33xc20"; - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_3p3>; - - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; -}; - -&mdss_dp3_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie4 { - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l3i_0p8>; - vdda-pll-supply = <&vreg_l3e_1p2>; - - status = "okay"; -}; - -&pcie4_port0 { - reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - wifi@0 { - compatible = "pci17cb,1107"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - }; -}; - -&pcie6a { - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-0 = <&pcie6a_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie6a_phy { - vdda-phy-supply = <&vreg_l1d_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie6a_port0 { - reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; -}; - -&pm8550_gpios { - rtmr0_default: rtmr0-reset-n-active-state { - pins = "gpio10"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; - - usb0_3p3_reg_en: usb0-3p3-reg-en-state { - pins = "gpio11"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pm8550ve_9_gpios { - usb0_1p8_reg_en: usb0-1p8-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pmc8380_3_gpios { - edp_bl_en: edp-bl-en-state { - pins = "gpio4"; - function = "normal"; - power-source = <1>; /* 1.8 V */ - qcom,drive-strength = ; - bias-pull-down; - input-disable; - output-enable; - }; -}; - -&pmc8380_5_gpios { - usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&qupv3_0 { - status = "okay"; -}; - -&qupv3_1 { - status = "okay"; -}; - -&qupv3_2 { status = "okay"; }; @@ -1041,345 +39,3 @@ status = "okay"; }; -&smb2360_0 { - status = "okay"; -}; - -&smb2360_0_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l2b_3p0>; -}; - -&smb2360_1 { - status = "okay"; -}; - -&smb2360_1_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l14b_3p0>; -}; - -&tlmm { - gpio-reserved-ranges = <34 2>, /* Unused */ - <44 4>, /* SPI (TPM) */ - <238 1>; /* UFS Reset */ - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - eusb3_reset_n: eusb3-reset-n-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-low; - }; - - eusb5_reset_n: eusb5-reset-n-state { - pins = "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-low; - }; - - eusb6_reset_n: eusb6-reset-n-state { - pins = "gpio184"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-low; - }; - - hall_int_n_default: hall-int-n-state { - pins = "gpio92"; - function = "gpio"; - bias-disable; - }; - - hdmi_hpd_default: hdmi-hpd-default-state { - pins = "gpio126"; - function = "usb2_dp"; - bias-disable; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-disable; - }; - - nvme_reg_en: nvme-reg-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6a_default: pcie6a-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie6a_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - rtmr1_default: rtmr1-reset-n-active-state { - pins = "gpio176"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-disable; - }; - - usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { - pins = "gpio188"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { - pins = "gpio175"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { - pins = "gpio186"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - wcn_bt_en: wcn-bt-en-state { - pins = "gpio116"; - function = "gpio"; - drive-strength = <16>; - bias-pull-down; - }; - - wcn_sw_en: wcn-sw-en-state { - pins = "gpio214"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - wcn_wlan_en: wcn-wlan-en-state { - pins = "gpio117"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; -}; - -&uart14 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn7850-bt"; - max-speed = <3200000>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - }; -}; - -&usb_1_ss0_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_0_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; - - status = "okay"; -}; - -&usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss0_dwc3_hs { - remote-endpoint = <&pmic_glink_ss0_hs_in>; -}; - -&usb_1_ss0_qmpphy_out { - remote-endpoint = <&retimer_ss0_ss_in>; -}; - -&usb_1_ss1_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_1_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - status = "okay"; -}; - -&usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss1_dwc3_hs { - remote-endpoint = <&pmic_glink_ss1_hs_in>; -}; - -&usb_1_ss1_qmpphy_out { - remote-endpoint = <&retimer_ss1_ss_in>; -}; - -&usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - /delete-property/ mode-switch; - /delete-property/ orientation-switch; - - status = "okay"; - - ports { - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - /delete-node/ endpoint; - - usb_1_ss2_qmpphy_out_dp: endpoint@0 { - reg = <0>; - - data-lanes = <3 2 1 0>; - remote-endpoint = <&hdmi_bridge_dp_in>; - }; - - /* No USB3 lanes connected */ - }; - }; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb5_repeater>; - - status = "okay"; -}; - -&usb_mp { - status = "okay"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb3_repeater>; - - status = "okay"; -}; - -&usb_mp_hsphy1 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb6_repeater>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - - status = "okay"; -}; - -&usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - - status = "okay"; -}; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "hamoa.dtsi" @@ -43,17 +44,14 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; - led-camera-indicator { - label = "white:camera-indicator"; + privacy_led: privacy-led { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; - /* Reuse as a panic indicator until we get a "camera on" trigger */ panic-indicator; }; }; @@ -151,6 +149,67 @@ }; }; + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-Dell-XPS-13-9345"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + channels-swapped; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_cam_1p8: regulator-cam-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_CAM_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_ldo_en>; + pinctrl-names = "default"; + }; + vreg_edp_3p3: regulator-edp-3p3 { compatible = "regulator-fixed"; @@ -415,6 +474,13 @@ regulator-initial-mode = ; }; + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + vreg_l2b_3p0: ldo2 { regulator-name = "vreg_l2b_3p0"; regulator-min-microvolt = <3072000>; @@ -436,6 +502,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -682,6 +755,71 @@ firmware-name = "qcom/x1e80100/dell/xps13-9345/qcdxkmsuc8380.mbn"; }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + camss_csiphy4_inep0: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02e10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + leds = <&privacy_led>; + led-names = "privacy"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + rotation = <180>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_2p8>; + dovdd-supply = <&vreg_cam_1p8>; + + port { + ov02e10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&camss_csiphy4_inep0>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -880,6 +1018,32 @@ status = "okay"; }; +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + &mdss { status = "okay"; }; @@ -1069,16 +1233,102 @@ vdd3-supply = <&vreg_l14b_3p0>; }; +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + &tlmm { gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ <76 4>, /* SPI19 (TZ Protected) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + /* cam_aon_mclk4 */ + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + cam_indicator_en: cam-indicator-en-state { pins = "gpio110"; function = "gpio"; drive-strength = <2>; bias-disable; + }; + + cam_ldo_en: cam-ldo-en-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; edp_bl_en: edp-bl-en-state { --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include #include "hamoa.dtsi" @@ -40,6 +42,21 @@ }; }; + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + privacy_led: privacy-led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -552,6 +569,13 @@ regulator-initial-mode = ; }; + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + vreg_l8b_3p0: ldo8 { regulator-name = "vreg_l8b_3p0"; regulator-min-microvolt = <3072000>; @@ -795,6 +819,57 @@ regulator-initial-mode = ; }; }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-l4-supply = <&vreg_s4c_1p8>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p2: ldo1 { + regulator-name = "vreg_l1m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l2m_1p2: ldo2 { + regulator-name = "vreg_l2m_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l3m_1p8: ldo3 { + regulator-name = "vreg_l3m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l4m_1p8: ldo4 { + regulator-name = "vreg_l4m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l5m_2p8: ldo5 { + regulator-name = "vreg_l5m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; }; &gpu { @@ -805,6 +880,69 @@ firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn"; }; +&camss { + status = "okay"; + + ports { + /* + * port0 => csiphy0 + * port1 => csiphy1 + * port2 => csiphy2 + * port3 => csiphy4 + */ + port@3 { + camss_csiphy4_inep0: endpoint@0 { + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&ov02c10_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_default>; + + leds = <&privacy_led>; + led-names = "privacy"; + + clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>; + assigned-clock-rates = <19200000>; + + orientation = <0>; /* front facing */ + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l1m_1p2>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02c10_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + remote-endpoint = <&camss_csiphy4_inep0>; + }; + }; + }; +}; + +&csiphy4 { + vdda-0p8-supply = <&vreg_l2c_0p8>; + vdda-1p2-supply = <&vreg_l1c_1p2>; + + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; @@ -1352,6 +1490,29 @@ <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1p42100-acer-swift-go14-01.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1p42100-acer-swift-go14-01.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* +* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +* Copyright (c) 2024, Linaro Limited +*/ + +/dts-v1/; + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" +#include "x1-acer-swift-14.dtsi" +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Acer Swift Go 14 AI (SFG14-01)"; + compatible = "acer,swift-go14-01","lenovo,thinkpad-t14s", "qcom,x1p42100", "qcom,x1e80100"; + chassis-type = "laptop"; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/ACER/SFG14-01/qcdxkmsuc8380.mbn"; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/ACER/SFG14-01/qcadsp8380.mbn", + "qcom/x1e80100/ACER/SFG14-01/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/ACER/SFG14-01/qccdsp8380.mbn", + "qcom/x1e80100/ACER/SFG14-01/cdsp_dtbs.elf"; + + status = "okay"; +}; + + + --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu + */ + +/dts-v1/; + +#include "purwa.dtsi" +#include "x1-asus-vivobook-s15.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "ASUS Vivobook S 15 X1P-42-100"; + compatible = "asus,vivobook-s15-x1p4", "qcom,x1p42100"; + chassis-type = "laptop"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcdxkmsucpurwa.mbn"; +}; + +&iris { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcadsp8380.mbn", + "qcom/x1p42100/ASUSTeK/vivobook-s15/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qccdsp8380.mbn", + "qcom/x1p42100/ASUSTeK/vivobook-s15/cdsp_dtbs.elf"; + + status = "okay"; +}; + --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1p42100-hp-elitebook-6-g1q.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1p42100-hp-elitebook-6-g1q.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" +#include "x1-hp-omnibook-x14.dtsi" +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "HP EliteBook 6 G1q 14 inch Notebook Next Gen AI PC"; + compatible = "hp,elitebook-6-g1q", "qcom,x1p42100"; + chassis-type = "laptop"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/hp/elitebook-6-g1q/qcdxkmsucpurwa.mbn"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/hp/elitebook-6-g1q/qcadsp8380.mbn", + "qcom/x1p42100/hp/elitebook-6-g1q/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/hp/elitebook-6-g1q/qccdsp8380.mbn", + "qcom/x1p42100/hp/elitebook-6-g1q/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&i2c0 { + /* The touchpad in the EliteBook is on a different I2C address */ + /delete-node/ touchpad@15; + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; --- linux-nvidia-7.0.0.orig/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts +++ linux-nvidia-7.0.0/arch/arm64/boot/dts/qcom/x1p64100-acer-swift-sf14-11.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* +* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +* Copyright (c) 2024, Linaro Limited +*/ + +/dts-v1/; + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" +#include "x1-acer-swift-14.dtsi" + +/ { + model = "Acer Swift 14 AI (SF14-11)"; + compatible = "acer,swift-sf14-11","lenovo,thinkpad-t14s", "qcom,x1p64100", "qcom,x1e80100"; + chassis-type = "laptop"; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/ACER/SF14-11/qcdxkmsuc8380.mbn"; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/ACER/SF14-11/qcadsp8380.mbn", + "qcom/x1e80100/ACER/SF14-11/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/ACER/SF14-11/qccdsp8380.mbn", + "qcom/x1e80100/ACER/SF14-11/cdsp_dtbs.elf"; + + status = "okay"; +}; --- linux-nvidia-7.0.0.orig/arch/arm64/configs/defconfig +++ linux-nvidia-7.0.0/arch/arm64/configs/defconfig @@ -1957,3 +1957,10 @@ CONFIG_CORESIGHT_CPU_DEBUG=m CONFIG_CORESIGHT_CTI=m CONFIG_MEMTEST=y +CONFIG_NVGRACE_GPU_VFIO_PCI=m +CONFIG_NVGRACE_EGM=m +CONFIG_VFIO_DEVICE_CDEV=y +CONFIG_FAULT_INJECTION=y +CONFIG_IOMMUFD_DRIVER=y +CONFIG_IOMMUFD=y +CONFIG_IOMMUFD_TEST=y --- linux-nvidia-7.0.0.orig/arch/arm64/include/asm/mpam.h +++ linux-nvidia-7.0.0/arch/arm64/include/asm/mpam.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2025 Arm Ltd. */ + +#ifndef __ASM__MPAM_H +#define __ASM__MPAM_H + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_STATIC_KEY_FALSE(mpam_enabled); +DECLARE_PER_CPU(u64, arm64_mpam_default); +DECLARE_PER_CPU(u64, arm64_mpam_current); + +/* + * The value of the MPAM0_EL1 sysreg when a task is in the default group. + * This is used by the context switch code to use the resctrl CPU property + * instead. The value is modified when CDP is enabled/disabled by mounting + * the resctrl filesystem. + */ +extern u64 arm64_mpam_global_default; + +/* + * The resctrl filesystem writes to the partid/pmg values for threads and CPUs, + * which may race with reads in __mpam_sched_in(). Ensure only one of the old + * or new values are used. Particular care should be taken with the pmg field + * as __mpam_sched_in() may read a partid and pmg that don't match, causing + * this value to be stored with cache allocations, despite being considered + * 'free' by resctrl. + * + * A value in struct thread_info is used instead of struct task_struct as the + * cpu's u64 register format is used, but struct task_struct has two u32'. + */ +static inline void mpam_set_cpu_defaults(int cpu, u16 partid_d, u16 partid_i, + u8 pmg_d, u8 pmg_i) +{ + u64 default_val; + + default_val = FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d); + default_val |= FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i); + default_val |= FIELD_PREP(MPAM0_EL1_PMG_D, pmg_d); + default_val |= FIELD_PREP(MPAM0_EL1_PMG_I, pmg_i); + + WRITE_ONCE(per_cpu(arm64_mpam_default, cpu), default_val); +} + +static inline void mpam_set_task_partid_pmg(struct task_struct *tsk, + u16 partid_d, u16 partid_i, + u8 pmg_d, u8 pmg_i) +{ +#ifdef CONFIG_ARM64_MPAM + u64 regval; + + regval = FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d); + regval |= FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i); + regval |= FIELD_PREP(MPAM0_EL1_PMG_D, pmg_d); + regval |= FIELD_PREP(MPAM0_EL1_PMG_I, pmg_i); + + WRITE_ONCE(task_thread_info(tsk)->mpam_partid_pmg, regval); +#endif +} + +static inline u64 mpam_get_regval(struct task_struct *tsk) +{ +#ifdef CONFIG_ARM64_MPAM + return READ_ONCE(task_thread_info(tsk)->mpam_partid_pmg); +#else + return 0; +#endif +} + +static inline void mpam_thread_switch(struct task_struct *tsk) +{ + u64 oldregval; + int cpu = smp_processor_id(); + u64 regval = mpam_get_regval(tsk); + + if (!IS_ENABLED(CONFIG_ARM64_MPAM) || + !static_branch_likely(&mpam_enabled)) + return; + + if (regval == READ_ONCE(arm64_mpam_global_default)) + regval = READ_ONCE(per_cpu(arm64_mpam_default, cpu)); + + oldregval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); + if (oldregval == regval) + return; + + /* Synchronising this write is left until the ERET to EL0 */ + write_sysreg_s(regval, SYS_MPAM0_EL1); + WRITE_ONCE(per_cpu(arm64_mpam_current, cpu), regval); +} +#endif /* __ASM__MPAM_H */ --- linux-nvidia-7.0.0.orig/arch/arm64/include/asm/resctrl.h +++ linux-nvidia-7.0.0/arch/arm64/include/asm/resctrl.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include --- linux-nvidia-7.0.0.orig/arch/arm64/include/asm/thread_info.h +++ linux-nvidia-7.0.0/arch/arm64/include/asm/thread_info.h @@ -42,6 +42,9 @@ void *scs_base; void *scs_sp; #endif +#ifdef CONFIG_ARM64_MPAM + u64 mpam_partid_pmg; +#endif u32 cpu; }; --- linux-nvidia-7.0.0.orig/arch/arm64/kernel/Makefile +++ linux-nvidia-7.0.0/arch/arm64/kernel/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_VMCORE_INFO) += vmcore_info.o obj-$(CONFIG_ARM_SDE_INTERFACE) += sdei.o obj-$(CONFIG_ARM64_PTR_AUTH) += pointer_auth.o +obj-$(CONFIG_ARM64_MPAM) += mpam.o obj-$(CONFIG_ARM64_MTE) += mte.o obj-y += vdso-wrap.o obj-$(CONFIG_COMPAT_VDSO) += vdso32-wrap.o --- linux-nvidia-7.0.0.orig/arch/arm64/kernel/cpufeature.c +++ linux-nvidia-7.0.0/arch/arm64/kernel/cpufeature.c @@ -86,6 +86,7 @@ #include #include #include +#include #include #include #include @@ -2501,6 +2502,12 @@ static void cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) { + int cpu = smp_processor_id(); + u64 regval = 0; + + if (IS_ENABLED(CONFIG_MPAM)) + regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); + /* * Access by the kernel (at EL1) should use the reserved PARTID * which is configured unrestricted. This avoids priority-inversion @@ -2508,6 +2515,8 @@ * been throttled to release the lock. */ write_sysreg_s(0, SYS_MPAM1_EL1); + + write_sysreg_s(regval, SYS_MPAM0_EL1); } static bool --- linux-nvidia-7.0.0.orig/arch/arm64/kernel/mpam.c +++ linux-nvidia-7.0.0/arch/arm64/kernel/mpam.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2025 Arm Ltd. */ + +#include + +#include +#include +#include +#include + +DEFINE_STATIC_KEY_FALSE(mpam_enabled); +DEFINE_PER_CPU(u64, arm64_mpam_default); +DEFINE_PER_CPU(u64, arm64_mpam_current); + +u64 arm64_mpam_global_default; + +static int mpam_pm_notifier(struct notifier_block *self, + unsigned long cmd, void *v) +{ + u64 regval; + int cpu = smp_processor_id(); + + switch (cmd) { + case CPU_PM_EXIT: + /* + * Don't use mpam_thread_switch() as the system register + * value has changed under our feet. + */ + regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); + write_sysreg_s(0, SYS_MPAM1_EL1); + write_sysreg_s(regval, SYS_MPAM0_EL1); + + return NOTIFY_OK; + default: + return NOTIFY_DONE; + } +} + +static struct notifier_block mpam_pm_nb = { + .notifier_call = mpam_pm_notifier, +}; + +static int __init arm64_mpam_register_cpus(void) +{ + u64 mpamidr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); + u16 partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, mpamidr); + u8 pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, mpamidr); + + cpu_pm_register_notifier(&mpam_pm_nb); + return mpam_register_requestor(partid_max, pmg_max); +} +/* Must occur before mpam_msc_driver_init() from subsys_initcall() */ +arch_initcall(arm64_mpam_register_cpus) --- linux-nvidia-7.0.0.orig/arch/arm64/kernel/process.c +++ linux-nvidia-7.0.0/arch/arm64/kernel/process.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -738,6 +739,12 @@ if (prev->thread.sctlr_user != next->thread.sctlr_user) update_sctlr_el1(next->thread.sctlr_user); + /* + * MPAM thread switch happens after the DSB to ensure prev's accesses + * use prev's MPAM settings. + */ + mpam_thread_switch(next); + /* the actual thread switch */ last = cpu_switch_to(prev, next); --- linux-nvidia-7.0.0.orig/arch/powerpc/Makefile +++ linux-nvidia-7.0.0/arch/powerpc/Makefile @@ -225,7 +225,7 @@ all: zImage # With make 3.82 we cannot mix normal and wildcard targets -BOOT_TARGETS1 := zImage zImage.initrd uImage +BOOT_TARGETS1 := zImage zImage.initrd uImage vmlinux.strip BOOT_TARGETS2 := zImage% dtbImage% treeImage.% cuImage.% simpleImage.% uImage.% PHONY += $(BOOT_TARGETS1) $(BOOT_TARGETS2) --- linux-nvidia-7.0.0.orig/arch/powerpc/kernel/pci-common.c +++ linux-nvidia-7.0.0/arch/powerpc/kernel/pci-common.c @@ -360,6 +360,7 @@ } return NULL; } +EXPORT_SYMBOL(pci_find_hose_for_OF_device); struct pci_controller *pci_find_controller_for_domain(int domain_nr) { @@ -1630,6 +1631,7 @@ { return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); } +EXPORT_SYMBOL_GPL(early_find_capability); struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) { --- linux-nvidia-7.0.0.orig/arch/powerpc/kernel/setup-common.c +++ linux-nvidia-7.0.0/arch/powerpc/kernel/setup-common.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,7 @@ #include #include #include +#include #include "setup.h" @@ -922,6 +924,16 @@ */ initialize_cache_info(); + /* + * Lock down the kernel if booted in secure mode. This is required to + * maintain kernel integrity. + */ + if (IS_ENABLED(CONFIG_LOCK_DOWN_IN_SECURE_BOOT)) { + if (is_ppc_secureboot_enabled()) + security_lock_kernel_down("PowerNV Secure Boot mode", + LOCKDOWN_INTEGRITY_MAX); + } + /* Initialize RTAS if available. */ rtas_initialize(); --- linux-nvidia-7.0.0.orig/arch/powerpc/platforms/pseries/vio.c +++ linux-nvidia-7.0.0/arch/powerpc/platforms/pseries/vio.c @@ -39,7 +39,6 @@ .name = "vio", .type = "", .dev.init_name = "vio", - .dev.bus = &vio_bus_type, }; #ifdef CONFIG_PPC_SMLPAR --- linux-nvidia-7.0.0.orig/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ linux-nvidia-7.0.0/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -42,7 +42,7 @@ }; }; cpu1: cpu@1 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -69,7 +69,7 @@ }; }; cpu2: cpu@2 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -96,7 +96,7 @@ }; }; cpu3: cpu@3 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; @@ -123,7 +123,7 @@ }; }; cpu4: cpu@4 { - compatible = "sifive,bullet0", "riscv"; + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <32768>; --- linux-nvidia-7.0.0.orig/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts +++ linux-nvidia-7.0.0/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "hifive-unleashed-a00.dts" + +/ { + soc { + pcie: pcie@2030000000 { + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + compatible = "microsemi,ms-pf-axi-pcie-host"; + device_type = "pci"; + bus-range = <0x01 0x7f>; + interrupt-map = <0 0 0 1 &ms_pcie_intc 0 0 0 0 2 &ms_pcie_intc 1 0 0 0 3 &ms_pcie_intc 2 0 0 0 4 &ms_pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&plic0>; + interrupts = <32>; + ranges = <0x3000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; + reg-names = "control", "apb"; + ms_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; +}; --- linux-nvidia-7.0.0.orig/arch/riscv/mm/init.c +++ linux-nvidia-7.0.0/arch/riscv/mm/init.c @@ -909,6 +909,10 @@ disable_pgtable_l4(); } + /* UBUNTU: Force disable sv57 and fallback to sv48 */ + if (pgtable_l5_enabled) + disable_pgtable_l5(); + memset(early_pg_dir, 0, PAGE_SIZE); memset(early_p4d, 0, PAGE_SIZE); memset(early_pud, 0, PAGE_SIZE); --- linux-nvidia-7.0.0.orig/arch/s390/include/asm/ipl.h +++ linux-nvidia-7.0.0/arch/s390/include/asm/ipl.h @@ -139,6 +139,7 @@ unsigned char flags, unsigned short cert); int ipl_report_add_certificate(struct ipl_report *report, void *key, unsigned long addr, unsigned long len); +bool ipl_get_secureboot(void); /* * DIAG 308 support --- linux-nvidia-7.0.0.orig/arch/s390/kernel/ipl.c +++ linux-nvidia-7.0.0/arch/s390/kernel/ipl.c @@ -2521,3 +2521,8 @@ } #endif + +bool ipl_get_secureboot(void) +{ + return !!ipl_secure_flag; +} --- linux-nvidia-7.0.0.orig/arch/s390/kernel/setup.c +++ linux-nvidia-7.0.0/arch/s390/kernel/setup.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -917,6 +918,9 @@ log_component_list(); + if (ipl_get_secureboot()) + security_lock_kernel_down("Secure IPL mode", LOCKDOWN_INTEGRITY_MAX); + /* Have one command line that is parsed and saved in /proc/cmdline */ /* boot_command_line has been already set up in early.c */ *cmdline_p = boot_command_line; --- linux-nvidia-7.0.0.orig/arch/x86/include/asm/pci-direct.h +++ linux-nvidia-7.0.0/arch/x86/include/asm/pci-direct.h @@ -10,9 +10,11 @@ extern u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset); extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset); extern u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset); +extern u32 pci_early_find_cap(int bus, int slot, int func, int cap); extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val); extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val); extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val); +extern unsigned int pci_early_clear_msi; extern int early_pci_allowed(void); #endif /* _ASM_X86_PCI_DIRECT_H */ --- linux-nvidia-7.0.0.orig/arch/x86/include/asm/resctrl.h +++ linux-nvidia-7.0.0/arch/x86/include/asm/resctrl.h @@ -191,8 +191,22 @@ enum resctrl_event_id evtid, void *ctx) { } +static inline bool resctrl_arch_mon_can_overflow(void) +{ + return true; +} + void resctrl_cpu_detect(struct cpuinfo_x86 *c); +static inline bool resctrl_arch_get_mb_uses_numa_nid(void) +{ + return false; +} + +static inline int resctrl_arch_set_mb_uses_numa_nid(bool enabled) +{ + return -EOPNOTSUPP; +} #else static inline void resctrl_arch_sched_in(struct task_struct *tsk) {} --- linux-nvidia-7.0.0.orig/arch/x86/kernel/aperture_64.c +++ linux-nvidia-7.0.0/arch/x86/kernel/aperture_64.c @@ -136,32 +136,6 @@ } -/* Find a PCI capability */ -static u32 __init find_cap(int bus, int slot, int func, int cap) -{ - int bytes; - u8 pos; - - if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & - PCI_STATUS_CAP_LIST)) - return 0; - - pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); - for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { - u8 id; - - pos &= ~3; - id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); - if (id == 0xff) - break; - if (id == cap) - return pos; - pos = read_pci_config_byte(bus, slot, func, - pos+PCI_CAP_LIST_NEXT); - } - return 0; -} - /* Read a standard AGPv3 bridge header */ static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) { @@ -250,8 +224,8 @@ case PCI_CLASS_BRIDGE_HOST: case PCI_CLASS_BRIDGE_OTHER: /* needed? */ /* AGP bridge? */ - cap = find_cap(bus, slot, func, - PCI_CAP_ID_AGP); + cap = pci_early_find_cap(bus, slot, + func, PCI_CAP_ID_AGP); if (!cap) break; *valid_agp = 1; --- linux-nvidia-7.0.0.orig/arch/x86/kernel/cpu/resctrl/core.c +++ linux-nvidia-7.0.0/arch/x86/kernel/cpu/resctrl/core.c @@ -88,7 +88,6 @@ .name = "MB", .ctrl_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA), - .schema_fmt = RESCTRL_SCHEMA_RANGE, }, }, [RDT_RESOURCE_SMBA] = @@ -97,7 +96,6 @@ .name = "SMBA", .ctrl_scope = RESCTRL_L3_CACHE, .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA), - .schema_fmt = RESCTRL_SCHEMA_RANGE, }, }, [RDT_RESOURCE_PERF_PKG] = @@ -211,22 +209,23 @@ cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid = edx.split.cos_max + 1; max_delay = eax.split.max_delay + 1; + r->schema_fmt = RESCTRL_SCHEMA_PERCENT; r->membw.max_bw = MAX_MBA_BW; - r->membw.arch_needs_linear = true; + r->mba.arch_needs_linear = true; if (ecx & MBA_IS_LINEAR) { - r->membw.delay_linear = true; + r->mba.delay_linear = true; r->membw.min_bw = MAX_MBA_BW - max_delay; r->membw.bw_gran = MAX_MBA_BW - max_delay; } else { if (!rdt_get_mb_table(r)) return false; - r->membw.arch_needs_linear = false; + r->mba.arch_needs_linear = false; } if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) - r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; + r->mba.throttle_mode = THREAD_THROTTLE_PER_THREAD; else - r->membw.throttle_mode = THREAD_THROTTLE_MAX; + r->mba.throttle_mode = THREAD_THROTTLE_MAX; r->alloc_capable = true; @@ -246,17 +245,18 @@ cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); hw_res->num_closid = edx + 1; + r->schema_fmt = RESCTRL_SCHEMA__AMD_MBA; r->membw.max_bw = 1 << eax; /* AMD does not use delay */ - r->membw.delay_linear = false; - r->membw.arch_needs_linear = false; + r->mba.delay_linear = false; + r->mba.arch_needs_linear = false; /* * AMD does not use memory delay throttle model to control * the allocation like Intel does. */ - r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; + r->mba.throttle_mode = THREAD_THROTTLE_UNDEFINED; r->membw.min_bw = 0; r->membw.bw_gran = 1; @@ -325,7 +325,7 @@ */ static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) { - if (r->membw.delay_linear) + if (r->mba.delay_linear) return MAX_MBA_BW - bw; pr_warn_once("Non Linear delay-bw map not supported but queried\n"); @@ -378,7 +378,7 @@ * For Memory Allocation: Set b/w requested to 100% */ for (i = 0; i < hw_res->num_closid; i++, dc++) - *dc = resctrl_get_default_ctrl(r); + *dc = resctrl_get_resource_default_ctrl(r); } static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom) --- linux-nvidia-7.0.0.orig/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ linux-nvidia-7.0.0/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -16,9 +16,15 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include "internal.h" +u32 resctrl_arch_round_bw(u32 val, const struct resctrl_schema *s) +{ + return roundup(val, (unsigned long)s->membw.bw_gran); +} + int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain *d, u32 closid, enum resctrl_conf_type t, u32 cfg_val) { --- linux-nvidia-7.0.0.orig/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ linux-nvidia-7.0.0/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -253,7 +253,7 @@ hw_dom = resctrl_to_arch_ctrl_dom(d); for (i = 0; i < hw_res->num_closid; i++) - hw_dom->ctrl_val[i] = resctrl_get_default_ctrl(r); + hw_dom->ctrl_val[i] = resctrl_get_resource_default_ctrl(r); msr_param.dom = d; smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &msr_param, 1); } --- linux-nvidia-7.0.0.orig/arch/x86/kernel/early-quirks.c +++ linux-nvidia-7.0.0/arch/x86/kernel/early-quirks.c @@ -29,6 +29,37 @@ #include #include +static void __init early_pci_clear_msi(int bus, int slot, int func) +{ + int pos; + u16 ctrl; + + if (likely(!pci_early_clear_msi)) + return; + + pr_info_once("Clearing MSI/MSI-X enable bits early in boot (quirk)\n"); + + pos = pci_early_find_cap(bus, slot, func, PCI_CAP_ID_MSI); + if (pos) { + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS); + ctrl &= ~PCI_MSI_FLAGS_ENABLE; + write_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS, ctrl); + + /* Read again to flush previous write */ + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS); + } + + pos = pci_early_find_cap(bus, slot, func, PCI_CAP_ID_MSIX); + if (pos) { + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS); + ctrl &= ~PCI_MSIX_FLAGS_ENABLE; + write_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS, ctrl); + + /* Read again to flush previous write */ + ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS); + } +} + static void __init fix_hypertransport_config(int num, int slot, int func) { u32 htcfg; @@ -727,6 +758,7 @@ PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, { PCI_VENDOR_ID_BROADCOM, 0x4331, PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, + { PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, early_pci_clear_msi}, {} }; @@ -779,6 +811,10 @@ PCI_HEADER_TYPE); if ((type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { + /* pci_early_clear_msi scans the buses differently. */ + if (pci_early_clear_msi) + return -1; + sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS); if (sec > num) early_pci_scan_bus(sec); @@ -805,8 +841,13 @@ void __init early_quirks(void) { + int bus; + if (!early_pci_allowed()) return; early_pci_scan_bus(0); + /* pci_early_clear_msi scans more buses. */ + for (bus = 1; pci_early_clear_msi && bus < 256; bus++) + early_pci_scan_bus(bus); } --- linux-nvidia-7.0.0.orig/arch/x86/kernel/reboot.c +++ linux-nvidia-7.0.0/arch/x86/kernel/reboot.c @@ -489,7 +489,46 @@ DMI_MATCH(DMI_PRODUCT_NAME, "VGN-Z540N"), }, }, - + { /* Handle problems with rebooting on the Latitude E6520. */ + .callback = set_pci_reboot, + .ident = "Dell Latitude E6520", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6520"), + }, + }, + { /* Handle problems with rebooting on the OptiPlex 790. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 790", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 790"), + }, + }, + { /* Handle problems with rebooting on the OptiPlex 990. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 990", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 990"), + }, + }, + { /* Handle problems with rebooting on the Latitude E6220. */ + .callback = set_pci_reboot, + .ident = "Dell Latitude E6220", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6220"), + }, + }, + { /* Handle problems with rebooting on the OptiPlex 390. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 390", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 390"), + }, + }, { } }; --- linux-nvidia-7.0.0.orig/arch/x86/kernel/setup.c +++ linux-nvidia-7.0.0/arch/x86/kernel/setup.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -998,6 +999,13 @@ reserve_ibft_region(); x86_init.resources.dmi_setup(); + efi_set_secure_boot(boot_params.secure_boot); + +#ifdef CONFIG_LOCK_DOWN_IN_SECURE_BOOT + if (efi_enabled(EFI_SECURE_BOOT)) + security_lock_kernel_down("EFI Secure Boot mode", LOCKDOWN_INTEGRITY_MAX); +#endif + /* * VMware detection requires dmi to be available, so this * needs to be done after dmi_setup(), for the boot CPU. @@ -1156,19 +1164,7 @@ /* Allocate bigger log buffer */ setup_log_buf(1); - if (efi_enabled(EFI_BOOT)) { - switch (boot_params.secure_boot) { - case efi_secureboot_mode_disabled: - pr_info("Secure boot disabled\n"); - break; - case efi_secureboot_mode_enabled: - pr_info("Secure boot enabled\n"); - break; - default: - pr_info("Secure boot could not be determined\n"); - break; - } - } + efi_set_secure_boot(boot_params.secure_boot); reserve_initrd(); --- linux-nvidia-7.0.0.orig/arch/x86/pci/common.c +++ linux-nvidia-7.0.0/arch/x86/pci/common.c @@ -34,6 +34,7 @@ #endif int pcibios_last_bus = -1; unsigned long pirq_table_addr; +unsigned int pci_early_clear_msi; const struct pci_raw_ops *__read_mostly raw_pci_ops; const struct pci_raw_ops *__read_mostly raw_pci_ext_ops; @@ -614,6 +615,9 @@ } else if (!strcmp(str, "skip_isa_align")) { pci_probe |= PCI_CAN_SKIP_ISA_ALIGN; return NULL; + } else if (!strcmp(str, "clearmsi")) { + pci_early_clear_msi = 1; + return NULL; } else if (!strcmp(str, "noioapicquirk")) { noioapicquirk = 1; return NULL; --- linux-nvidia-7.0.0.orig/arch/x86/pci/early.c +++ linux-nvidia-7.0.0/arch/x86/pci/early.c @@ -51,6 +51,31 @@ outw(val, 0xcfc + (offset&2)); } +u32 pci_early_find_cap(int bus, int slot, int func, int cap) +{ + int bytes; + u8 pos; + + if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & + PCI_STATUS_CAP_LIST)) + return 0; + + pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); + for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { + u8 id; + + pos &= ~3; + id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); + if (id == 0xff) + break; + if (id == cap) + return pos; + pos = read_pci_config_byte(bus, slot, func, + pos+PCI_CAP_LIST_NEXT); + } + return 0; +} + int early_pci_allowed(void) { return (pci_probe & (PCI_PROBE_CONF1|PCI_PROBE_NOEARLY)) == --- linux-nvidia-7.0.0.orig/certs/blacklist.c +++ linux-nvidia-7.0.0/certs/blacklist.c @@ -277,6 +277,9 @@ if (IS_ERR(key)) { pr_err("Problem with revocation key (%ld)\n", PTR_ERR(key)); return PTR_ERR(key); + } else { + pr_notice("Revoked X.509 cert '%s'\n", + key_ref_to_ptr(key)->description); } return 0; --- linux-nvidia-7.0.0.orig/crypto/aegis128-neon-inner.c +++ linux-nvidia-7.0.0/crypto/aegis128-neon-inner.c @@ -148,8 +148,8 @@ kiv, vld1q_u8(const1), vld1q_u8(const0), - k ^ vld1q_u8(const0), - k ^ vld1q_u8(const1), + (uint8x16_t) (k ^ vld1q_u8(const0)), + (uint8x16_t) (k ^ vld1q_u8(const1)), }}; int i; --- linux-nvidia-7.0.0.orig/crypto/asymmetric_keys/x509_loader.c +++ linux-nvidia-7.0.0/crypto/asymmetric_keys/x509_loader.c @@ -41,6 +41,7 @@ if (IS_ERR(key)) { pr_err("Problem loading in-kernel X.509 certificate (%ld)\n", PTR_ERR(key)); + WARN_ON_ONCE(1); } else { pr_notice("Loaded X.509 cert '%s'\n", key_ref_to_ptr(key)->description); --- linux-nvidia-7.0.0.orig/crypto/fips.c +++ linux-nvidia-7.0.0/crypto/fips.c @@ -15,7 +15,8 @@ #include #include -int fips_enabled; +/* LP: #2049082 UBUNTU: SAUCE: FIPS kernels default to FIPS mode */ +int fips_enabled = 1; EXPORT_SYMBOL_GPL(fips_enabled); ATOMIC_NOTIFIER_HEAD(fips_fail_notif_chain); --- linux-nvidia-7.0.0.orig/debian.master/changelog +++ linux-nvidia-7.0.0/debian.master/changelog @@ -0,0 +1,8370 @@ +linux (7.0.0-14.14) resolute; urgency=medium + + * resolute/linux: 7.0.0-14.14 -proposed tracker (LP: #2148159) + + * support vflip/hflip for Sony IMX471 camera sensor (LP: #2138841) + - SAUCE: media: ipu-bridge: add TBE20A0 ACPI id for Sony IMX471 + + * AA: disable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED (LP: #2147533) + - [Config] disable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED + + * System doesn't response with mt76 call trace (LP: #2137448) + - wifi: mt76: mt792x: Fix a potential deadlock in high-load situations + + * The second tbt storage plugged on the dock will not be recognized + (LP: #2139572) + - SAUCE: thunderbolt: Fix PCIe device enumeration with delayed rescan + + * dma-buf filesystem flags fix (LP: #2139656) + - SAUCE: dma-buf: set SB_I_NOEXEC and SB_I_NODEV on dmabuf filesystem + + * Bluetooth device (MT7925) not detected on USB bus with linux-oem-6.17 + (LP: #2145164) + - SAUCE: USB: hub: call ACPI _PRR reset during port power-cycle on + enumeration failure + + * drm/i915/lnl+/tc: Fix false disconnect of active DP-alt TC port during + long HPD pulse (LP: #2143879) + - SAUCE: drm/i915/lnl+/tc: Fix false disconnect of active DP-alt TC port + during long HPD pulse + + * i915 WARN_ON call trace during CB/WB on MTL/ARL platforms (LP: #2144537) + - SAUCE: drm/i915/xelpdp/tc: Convert TCSS power check WARN to a debug + message + + * Miscellaneous Ubuntu changes + - [Packaging] Add support for per-flavour depends + - [Packaging] Don't hard-code lmm zfs dependency + - [Config] updateconfigs following v7.0 release + + -- Paolo Pisati Mon, 13 Apr 2026 10:12:22 +0200 + +linux (7.0.0-13.13) resolute; urgency=medium + + * resolute/linux: 7.0.0-13.13 -proposed tracker (LP: #2147403) + + * ubuntu_kselftests:_net/net:gre_gso.sh failing (LP: #2136820) + - SAUCE increase socat timeout in gre_gso.sh + + * Canonical Kmod 2025 key rotation (LP: #2147447) + - [Packaging] ubuntu-compatible-signing -- make Ubuntu-Compatible-Signing + extensible + - [Packaging] ubuntu-compatible-signing -- allow consumption of positive + certs + - [Packaging] ubuntu-compatible-signing -- report the livepatch:2025 key + - [Config] prepare for Canonical Kmod key rotation + - [Packaging] ubuntu-compatible-signing -- report the kmod:2025 key + - [Packaging] ensure our cert rollups are always fresh + + * On Dell system, the internal OLED display drops to a visibly low FPS after + suspend/resume (LP: #2144712) + - drm/i915/psr: Disable Panel Replay on Dell XPS 14 DA14260 as a quirk + - drm/i915/psr: Fixes for Dell XPS DA14260 quirk + + * Realtek RTL8116AF SFP option module fails to get connected (LP: #2116144) + - SAUCE: r8169: add quirk for RTL8116af SerDes + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v7.0-rc7 rebase + + -- Paolo Pisati Wed, 08 Apr 2026 06:56:37 +0200 + +linux (7.0.0-12.12) resolute; urgency=medium + + * resolute/linux: 7.0.0-12.12 -proposed tracker (LP: #2146778) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + + * linux-generic does not run scripts in /usr/share/kernel/*.d (LP: #2147005) + - [Packaging] templates: Use consistent indentation + - [Packaging] templates: Run scripts in /usr/share/kernel/*.d too + + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] riscv64: Enable COUNTER=m + - [Config] riscv64: Use GENDWARFKSYMS like other architectures + + * unconfined profile denies userns_create for chromium based processes + (LP: #1990064) + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * FFe: add network interface mediation to 26.04 (LP: #2144679) + - SAUCE: apparmor5.0.0 [57/57]: apparmor: add the ability to use interface + in network mediation. + + * Jellyfin Desktop Flatpak doesn't work with the current AppArmor profile + (LP: #2142956) + - SAUCE: apparmor5.0.0 [29/57]: apparmor: fix fine grained inet mediation + sock_file_perm + - SAUCE: apparmor5.0.0 [30/57]: apparmor-next 7.1: aapparmor: use target + task's context in apparmor_getprocattr() + - SAUCE: apparmor5.0.0 [31/57]: apparmor-next 7.1: apparmor: return error + on namespace mismatch in verify_header + - SAUCE: apparmor5.0.0 [32/57]: apparmor-next 7.1: apparmor: enable + differential encoding + - SAUCE: apparmor5.0.0 [33/57]: apparmor-next 7.1: apparmor: propagate + -ENOMEM correctly in unpack_table + - SAUCE: apparmor5.0.0 [34/57]: apparmor-next 7.1: apparmor: Replace + memcpy + NUL termination with kmemdup_nul in do_setattr + - SAUCE: apparmor5.0.0 [35/57]: apparmor-next 7.1: apparmor: Remove + redundant if check in sk_peer_get_label + - SAUCE: apparmor5.0.0 [36/57]: apparmor-next 7.1: apparmor: use + __label_make_stale in __aa_proxy_redirect + - SAUCE: apparmor5.0.0 [37/57]: apparmor-next 7.1: apparmor: fix net.h and + policy.h circular include pattern + - SAUCE: apparmor5.0.0 [39/57]: apparmor-next 7.1: apparmor: make include + headers self-contained + - SAUCE: apparmor5.0.0 [40/57]: apparmor-next 7.1: apparmor: Use + sysfs_emit in param_get_{audit,mode} + - SAUCE: apparmor5.0.0 [41/57]: apparmor-next 7.1: apparmor: fix + rawdata_f_data implicit flex array + - SAUCE: apparmor5.0.0 [42/57]: apparmor-next 7.1: apparmor: free rawdata + as soon as possible + - SAUCE: apparmor5.0.0 [43/57]: apparmor-next 7.1: apparmor: Initial + support for compressed policies + - SAUCE: apparmor5.0.0 [44/57]: apparmor-next 7.1: apparmor: fix potential + UAF in aa_replace_profiles + - SAUCE: apparmor5.0.0 [45/57]: apparmor-next 7.1: apparmor: hide unused + get_loaddata_common_ref() function + - SAUCE: apparmor5.0.0 [46/57]: apparmor-next 7.1: apparmor: Fix string + overrun due to missing termination + - SAUCE: apparmor5.0.0 [47/57]: apparmor: fix packed tag on v5 header + struct + - SAUCE: apparmor5.0.0 [48/57]: apparmor: add temporal caching to audit + responses. + - SAUCE: apparmor5.0.0 [49/57]: apparmor: change fn_label_build() call to + not return NULL + - SAUCE: apparmor5.0.0 [50/57]: apparmor: make fn_label_build() capable of + handling not supported + - SAUCE: apparmor5.0.0 [51/57]: apparmor: move netfilter functions next to + the LSM network operations + - SAUCE: apparmor5.0.0 [52/57]: apparmor: move sock_rvc_skb() next to + inet_conn_request + - SAUCE: apparmor5.0.0 [53/57]: apparmor: fix af_unix local addr mediation + binding + - SAUCE: apparmor5.0.0 [54/57]: cleanups of apparmor af_unix mediation + - SAUCE: apparmor5.0.0 [55/57]: apparmor: fix apparmor_secmark_check() + when !inet and secmark defined. + - SAUCE: apparmor5.0.0 [56/57]: apparmor: fix auditing of non-mediation + falures + + * snap service cannot change apparmor hat (LP: #2139664) // Jellyfin Desktop + Flatpak doesn't work with the current AppArmor profile (LP: #2142956) + - SAUCE: apparmor5.0.0 [38/57]: apparmor-next 7.1: apparmor: grab ns lock + and refresh when looking up changehat child profiles + + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor5.0.0 [28/57]: apparmor: fix aa_label_sk_perm to check + for RULE_MEDIATES_NET + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/57]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/57]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/57]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [4/57]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [5/57]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [6/57]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [7/57]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [8/57]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [9/57]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [10/57]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [12/57]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [13/57]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [14/57]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [15/57]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [16/57]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [19/57]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [20/57]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [21/57]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [22/57]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [23/57]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [24/57]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [25/57]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [26/57]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [27/57]: apparmor: prevent profile->disconnected + double free in aa_free_profile + + * update apparmor and LSM stacking patch set (LP: #2028253) // Installation + of AppArmor on a 6.14 kernel produces error message "Illegal number: yes" + (LP: #2102680) + - SAUCE: apparmor5.0.0 [17/57]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [18/57]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [11/57]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + + * Enable new Intel WCL soundwire support (LP: #2143301) + - ASoC: sdw_utils: Add CS42L43B codec info + - ASoC: dt-bindings: cirrus, cs42l43: Add CS42L43B variant + - mfd: cs42l43: Add support for the B variant + - ASoC: cs42l43: Add support for the B variant + + * Enable audio functions on Dell Huracan/Renegade platforms w/o built-in + microphone (LP: #2143902) + - ASoC: SDCA: Add default value for mipi-sdca-function-reset-max-delay + - ASoC: SDCA: Update counting of SU/GE DAPM routes + - ASoC: SDCA: Improve mapping of Q7.8 SDCA volumes + - ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops + - ASoC: add snd_soc_lookup_component_by_name helper + - ASoC: soc_sdw_utils: partial match the codec name + - ASoC: soc_sdw_utils: remove index from sdca codec name + + * [SRU] MIPI camera is not working after upgrading to 6.17-oem + (LP: #2145171) + - SAUCE: ACPI: respect items already in honor_dep before skipping + + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Actually enable llvm for perf + + * Pull patch in qla2xxx to Resolute (LP: #2144856) + - scsi: qla2xxx: Add support to report MPI FW state + + * Ubuntu Resolute Desktop image arm64 - Boot on SC8280XP stalls with gpi-dma + errors (LP: #2142403) + - Revert "arm64: dts: qcom: sc8280xp: Enable GPI DMA" + + * 26.04 Snapdragon X Elite: Sync concept kernel changes (LP: #2144643) + - SAUCE: arm64: dts: add missing denali-oled.dtb to Makefile + - SAUCE: dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema + - SAUCE: phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add simple-mfd + compatible + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add optional PHY handle + definitions + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add support for combo- + mode endpoints + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Describe iommu entries + - SAUCE: media: qcom: camss: Add legacy_phy flag to SoC definition + structures + - SAUCE: media: qcom: camss: Add support for PHY API devices + - SAUCE: media: qcom: camss: Drop legacy PHY descriptions from x1e + - SAUCE: arm64: dts: qcom: x1e80100: Add CAMCC block definition + - SAUCE: arm64: dts: qcom: x1e80100: Add CCI definitions + - SAUCE: arm64: dts: qcom: x1e80100: Add CAMSS block definition + - SAUCE: arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m + regulators + - SAUCE: arm64: dts: qcom: x1e80100-crd: Add ov08x40 RGB sensor on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Add pm8010 camera PMIC with + voltage levels for IR and RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Add on ov02c10 RGB sensor on + CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add pm8010 camera + PMIC with voltage levels for IR and RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add l7b_2p8 + voltage regulator for RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add ov02c10 RGB + sensor on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-dell-inspiron14-7441: Switch on CAMSS + RGB sensor + - SAUCE: arm64: dts: qcom: x1-asus-zenbook-a14: Add on OV02C10 RGB sensor + on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: add camera support + - SAUCE: arm64: dts: qcom: x1e78100-t14s: enable camera privacy indicator + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: enable camera + privacy indicator + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: enable camera privacy + indicator + - SAUCE: dt-bindings: arm: qcom: Add ASUS Vivobook X1P42100 variant + - SAUCE: arm64: dts: qcom: x1-vivobook-s15: create a common dtsi for Hamoa + and Purwa variants + - SAUCE: arm64: dts: qcom: x1-vivobook-s15: add Purwa-compatible device + tree + - SAUCE: firmware: qcom: scm: allow QSEECOM on ASUS Vivobook X1P42100 + variant + - SAUCE: arm64: dts: qcom: hamoa: Move PCIe PERST and Wake GPIOs to port + nodes + - SAUCE: arm64: dts: qcom: x1e-acer-swift-14: Move PCIe PERST and Wake + GPIOs to port nodes + + * 25.10 Snapdragon X Elite: Sync concept kernel changes (LP: #2121477) + - SAUCE: wip: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + + * Miscellaneous Ubuntu changes + - SAUCE: dt-bindings: arm: qcom: Document HP EliteBook 6 G1q + - SAUCE: firmware: qcom: scm: Allow QSEECOM for HP EliteBook 6 G1q + - SAUCE: arm64: dts: qcom: x1p42100-hp-elitebook-6-g1q: DT for HP + EliteBook 6 G1q + - [Config] PHY_QCOM_MIPI_CSI2=m + - SAUCE: arm64: dts: x1e80100-lenovo-yoga-slim7x: Fix RGB camera supplies + - [Config] toolchain version update + - Update Changes.md after v7.0-rc5 rebase + - [Packaging] update Ubuntu.md + - [Config] enable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED + - [Packaging] Add linux-main-modules-zfs to linux-modules depends + + * Miscellaneous upstream changes + - Revert "UBUNTU: SAUCE: Add Bluetooth support for the Lenovo Yoga Slim + 7x" + + -- Timo Aaltonen Thu, 02 Apr 2026 11:50:22 +0300 + +linux (7.0.0-10.10) resolute; urgency=medium + + * resolute/linux: 7.0.0-10.10 -proposed tracker (LP: #2144865) + + * Miscellaneous upstream changes + - Revert "powerpc: fix KUAP warning in VMX usercopy path" + + -- Paolo Pisati Thu, 19 Mar 2026 09:44:11 +0100 + +linux (7.0.0-9.9) resolute; urgency=medium + + * resolute/linux: 7.0.0-9.9 -proposed tracker (LP: #2144735) + + * Please make dracut the default initrd generator (LP: #2142775) + - [Packaging] recommends dracut instead of initramfs-tools + + * Miscellaneous Ubuntu changes + - SAUCE: Change RISC-V target to RVA23 (riscv64a23-unknown-linux-gnu) + + -- Paolo Pisati Wed, 18 Mar 2026 13:11:06 +0100 + +linux (7.0.0-8.8) resolute; urgency=medium + + * resolute/linux: 7.0.0-8.8 -proposed tracker (LP: #2144652) + + * UBUNTU: SAUCE: igc: Increase Thunderbolt MAC passthrough delay to 1000ms + (LP: #2143197) + - SAUCE: igc: Increase Thunderbolt MAC passthrough delay to 1000ms + + * [usrmerge] evaluate kernel owned packages for DEP17 compliance + (LP: #2139276) + - [Packaging] Install modules in /usr/lib/modules + + * Miscellaneous Ubuntu changes + - [Config] hardening: enable LIST_HARDENED + - [Config] hardening: disable LDISC_AUTOLOAD + - [Config] hardening: disable LEGACY_PTYS + - [Config] updateconfigs following v7.0-rc4 rebase + + -- Paolo Pisati Tue, 17 Mar 2026 18:01:36 +0100 + +linux (7.0.0-7.7) resolute; urgency=medium + + * resolute/linux: 7.0.0-7.7 -proposed tracker (LP: #2143974) + + * unconfined profile denies userns_create for chromium based processes + (LP: #1990064) + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * Jellyfin Desktop Flatpak doesn't work with the current AppArmor profile + (LP: #2142956) + - SAUCE: apparmor5.0.0 [29/29]: apparmor: fix fine grained inet mediation + sock_file_perm + + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor5.0.0 [28/29]: apparmor: fix aa_label_sk_perm to check + for RULE_MEDIATES_NET + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/29]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/29]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/29]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [4/29]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [5/29]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [6/29]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [7/29]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [8/29]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [9/29]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [10/29]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [12/29]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [13/29]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [14/29]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [15/29]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [16/29]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [19/29]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [20/29]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [21/29]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [22/29]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [23/29]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [24/29]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [25/29]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [26/29]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [27/29]: apparmor: prevent profile->disconnected + double free in aa_free_profile + + * update apparmor and LSM stacking patch set (LP: #2028253) // Installation + of AppArmor on a 6.14 kernel produces error message "Illegal number: yes" + (LP: #2102680) + - SAUCE: apparmor5.0.0 [17/29]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [18/29]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [11/29]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + + * NPU utilization on amdxdna is missing (LP: #2143243) + - SAUCE: accel/amdxdna: Add IOCTL to retrieve realtime NPU power estimate + - SAUCE: accel/amdxdna: Support sensors for column utilization + - SAUCE: accel/amdxdna: Import AMD_PMF namespace + + * Adopting dark mode by default for OLED panel (LP: #2143203) + - SAUCE: drm/connector: Add a new 'panel_type' property + - SAUCE: drm/amd/display: Attach OLED property to eDP panels + + * Support AMD Image Signal Processing (ISP) unit V4.0 (LP: #2110092) + - SAUCE: media: platform: amd: Introduce amd isp4 capture driver + - SAUCE: media: platform: amd: low level support for isp4 firmware + - SAUCE: media: platform: amd: Add isp4 fw and hw interface + - SAUCE: media: platform: amd: isp4 subdev and firmware loading handling + added + - SAUCE: media: platform: amd: isp4 video node and buffers handling added + - SAUCE: Documentation: add documentation of AMD isp 4 driver + - SAUCE: media: platform: amd: isp4 debug fs logging and more descriptive + errors + - [Config] Enable VIDEO_AMD_ISP4_CAPTURE + + * Miscellaneous Ubuntu changes + - [Config] temporarily disable OBJTOOL_WERROR + + -- Paolo Pisati Thu, 12 Mar 2026 10:49:34 +0100 + +linux (7.0.0-6.6) resolute; urgency=medium + + * resolute/linux: 7.0.0-6.6 -proposed tracker (LP: #2143745) + + * Miscellaneous Ubuntu changes + - [Packaging] drop unstable suffix + + -- Paolo Pisati Mon, 09 Mar 2026 17:20:26 +0100 + +linux (7.0.0-5.5) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-5.5 -proposed tracker (LP: #2143700) + + * Resolute real-time patchset: 7.0-rc1-rt1 (LP: #2143181) + - SAUCE: Reapply "serial: 8250: Switch to nbcon console" + - SAUCE: Reapply "serial: 8250: Revert "drop lockdep annotation from + serial8250_clear_IER()"" + - SAUCE: drm/i915: Use preempt_disable/enable_rt() where recommended + - SAUCE: drm/i915: Don't disable interrupts on PREEMPT_RT during atomic + updates + - SAUCE: drm/i915: Disable tracing points on PREEMPT_RT + - SAUCE: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + + spin_lock() + - SAUCE: drm/i915: Drop the irqs_disabled() check + - SAUCE: drm/i915/guc: Consider also RCU depth in busy loop. + - SAUCE: drm/i915: Consider RCU read section as atomic. + - SAUCE: Revert "drm/i915: Depend on !PREEMPT_RT." + - SAUCE: sysfs: Add /sys/kernel/realtime entry + - Real-time patchset 7.0-rc1-rt1 + + * Miscellaneous Ubuntu changes + - [Config] rust toolchain version update + + -- Paolo Pisati Mon, 09 Mar 2026 08:10:31 +0100 + +linux-unstable (7.0.0-4.4) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-4.4 -proposed tracker (LP: #2143123) + + * efi: Fix swapped arguments to bsearch() in efi_status_to_*() SAUCE patch + (LP: #2141276) + - SAUCE efi: Fix swapped arguments to bsearch() in efi_status_to_*() + + * Plucky preinstalled server fails to boot on rb3gen2 (LP: #2106681) // + Questing preinstalled server fails to boot on sa8775p boards + (LP: #2121347) + - [Config] move more qcom interconnect/pinctrl/gcc options to builtin + + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Add llvm-21-dev to build-depends for perf + + * Miscellaneous Ubuntu changes + - [Packaging] Add intel-speed-select to linux-tools + - [Packaging] remove stale debian/dkms-versions + - [Packaging] remove stale debian/dkms-versions scripting + + -- Paolo Pisati Wed, 04 Mar 2026 13:59:02 +0100 + +linux-unstable (7.0.0-3.3) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-3.3 -proposed tracker (LP: #2143020) + + * Miscellaneous Ubuntu changes + - [Config] updateconfig after rebase to v7.0-rc2 + - [Config] switch to PREEMPT_LAZY + + -- Paolo Pisati Mon, 02 Mar 2026 09:26:45 +0100 + +linux-unstable (7.0.0-2.2) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-2.2 -proposed tracker (LP: #2142764) + + -- Paolo Pisati Fri, 27 Feb 2026 10:25:35 +0100 + +linux-unstable (7.0.0-1.1) resolute; urgency=medium + + * resolute/linux-unstable: 7.0.0-1.1 -proposed tracker (LP: #2142402) + + * Miscellaneous Ubuntu changes + - [packaging] rename to linux-unstable + - [Config] updateconfig after rebase to v7.0-rc1 + - Update Changes.md + - [Packaging] add libbpf-dev to Build-Depends + - [Config] disable AMD_ISP4, FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove zfs FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove evdi FTBFS + - [Config] updateconfig after rebase to v7.0-rc1 + - [Config] update toolchain version + + -- Paolo Pisati Mon, 23 Feb 2026 08:32:17 +0100 + +linux-unstable (6.19.0-6.6) resolute; urgency=medium + + * resolute/linux: 6.19.0-6.6 -proposed tracker (LP: #2142114) + + * Resolute update: v6.19.2 upstream stable release (LP: #2142112) + - Revert "driver core: enforce device_lock for driver_match_device()" + - Linux 6.19.2 + + * Resolute update: v6.19.1 upstream stable release (LP: #2142111) + - io_uring/io-wq: add exit-on-idle state + - io_uring: allow io-wq workers to exit when unused + - smb: client: split cached_fid bitfields to avoid shared-byte RMW races + - ksmbd: fix infinite loop caused by next_smb2_rcv_hdr_off reset in error + paths + - ksmbd: add chann_lock to protect ksmbd_chann_list xarray + - smb: server: fix leak of active_num_conn in ksmbd_tcp_new_connection() + - smb: smbdirect: introduce smbdirect_socket.recv_io.credits.available + - smb: smbdirect: introduce smbdirect_socket.send_io.bcredits.* + - smb: server: make use of smbdirect_socket.recv_io.credits.available + - smb: server: let recv_done() queue a refill when the peer is low on + credits + - smb: server: make use of smbdirect_socket.send_io.bcredits + - smb: server: fix last send credit problem causing disconnects + - smb: server: let send_done handle a completion without IB_SEND_SIGNALED + - smb: client: make use of smbdirect_socket.recv_io.credits.available + - smb: client: let recv_done() queue a refill when the peer is low on + credits + - smb: client: let smbd_post_send() make use of request->wr + - smb: client: remove pointless sc->recv_io.credits.count rollback + - smb: client: remove pointless sc->send_io.pending handling in + smbd_post_send_iter() + - smb: client: port and use the wait_for_credits logic used by server + - smb: client: split out smbd_ib_post_send() + - smb: client: introduce and use smbd_{alloc, free}_send_io() + - smb: client: use smbdirect_send_batch processing + - smb: client: make use of smbdirect_socket.send_io.bcredits + - smb: client: fix last send credit problem causing disconnects + - smb: client: let smbd_post_send_negotiate_req() use smbd_post_send() + - smb: client: let send_done handle a completion without IB_SEND_SIGNALED + - driver core: enforce device_lock for driver_match_device() + - Bluetooth: btusb: Add USB ID 7392:e611 for Edimax EW-7611UXB + - ALSA: hda/conexant: Add quirk for HP ZBook Studio G4 + - crypto: iaa - Fix out-of-bounds index in find_empty_iaa_compression_mode + - crypto: octeontx - Fix length check to avoid truncation in + ucode_load_store + - crypto: omap - Allocate OMAP_CRYPTO_FORCE_COPY scatterlists correctly + - crypto: virtio - Add spinlock protection with virtqueue notification + - crypto: virtio - Remove duplicated virtqueue_kick in + virtio_crypto_skcipher_crypt_req + - nilfs2: Fix potential block overflow that cause system hang + - hfs: ensure sb->s_fs_info is always cleaned up + - wifi: rtw88: Fix alignment fault in rtw_core_enable_beacon() + - scsi: qla2xxx: Validate sp before freeing associated memory + - scsi: qla2xxx: Allow recovery for tape devices + - scsi: qla2xxx: Delay module unload while fabric scan in progress + - scsi: qla2xxx: Free sp in error path to fix system crash + - scsi: qla2xxx: Query FW again before proceeding with login + - sched/mmcid: Don't assume CID is CPU owned on mode switch + - bus: fsl-mc: fix use-after-free in driver_override_show() + - erofs: fix UAF issue for file-backed mounts w/ directio option + - xfs: fix UAF in xchk_btree_check_block_owner + - drm/exynos: vidi: use ctx->lock to protect struct vidi_context member + variables related to memory alloc/free + - PCI: endpoint: Avoid creating sub-groups asynchronously + - wifi: rtl8xxxu: fix slab-out-of-bounds in rtl8xxxu_sta_add + - Linux 6.19.1 + + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor: fix aa_label_sk_perm to check for RULE_MEDIATES_NET + + -- Timo Aaltonen Wed, 18 Feb 2026 14:31:48 +0200 + +linux (6.19.0-5.5) resolute; urgency=medium + + * resolute/linux: 6.19.0-5.5 -proposed tracker (LP: #2141736) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2026.02.09) + + * Blacklisted sbsa_gwdt module makes machines reboot (LP: #2138924) + - [Packaging] fix watchdog blacklist exceptions adding kmod extension + + * Miscellaneous Ubuntu changes + - [Packaging] debian/scripts/dkms-build--nvidia-N -- fix module.lds option + - [Packaging] fix a typo in Ubuntu.md + - [Config] updateconfig after rebase to v6.19-rc8 + - [Packaging] Drop changelog entries older than noble + + -- Timo Aaltonen Fri, 13 Feb 2026 19:04:04 +0200 + +linux (6.19.0-3.3) resolute; urgency=medium + + * resolute/linux: 6.19.0-3.3 -proposed tracker (LP: #2138935) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2026.01.12) + - [Packaging] update variants + + * [26.04] Please test secureboot and lock-down with 6.18 kernel (s390x) on + Resolute Raccoon (LP: #2131805) + - SAUCE: s390/boot/vmlinux.lds.S: Ensure bzImage ends with SecureBoot + trailer + + * unconfined profile denies userns_create for chromium based processes + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set + - SAUCE: apparmor5.0.0 [1/53]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/53]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/53]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor5.0.0 [4/53]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [5/53]: apparmor-next 7.0: apparmor: replace + sprintf with snprintf in aa_new_learning_profile + - SAUCE: apparmor5.0.0 [6/53]: apparmor-next 7.0: apparmor: Replace + sprintf/strcpy with scnprintf/strscpy in aa_policy_init + - SAUCE: apparmor5.0.0 [7/53]: apparmor-next 7.0: apparmor: Replace + deprecated strcpy in d_namespace_path + - SAUCE: apparmor5.0.0 [8/53]: apparmor-next 7.0: apparmor: fix NULL + pointer dereference in __unix_needs_revalidation + - SAUCE: apparmor5.0.0 [9/53]: apparmor-next 7.0: apparmor: fix NULL sock + in aa_sock_file_perm + - SAUCE: apparmor5.0.0 [10/53]: apparmor-next 7.0: apparmor: Replace + deprecated strcpy with memcpy in gen_symlink_name + - SAUCE: apparmor5.0.0 [11/53]: apparmor-next 7.0: AppArmor: Allow + apparmor to handle unaligned dfa tables + - SAUCE: apparmor5.0.0 [12/53]: apparmor-next 7.0: apparmor: Fix & + Optimize table creation from possibly unaligned memory + - SAUCE: apparmor5.0.0 [13/53]: apparmor-next 7.0: apparmor: make str + table more generic and be able to have multiple entries + - SAUCE: apparmor5.0.0 [14/53]: apparmor-next 7.0: apparmor: add support + loading per permission tagging + - SAUCE: apparmor5.0.0 [15/53]: apparmor-next 7.0: aoparmor: userns: Add + support for execpath in userns + - SAUCE: apparmor5.0.0 [16/53]: apparmor-next 7.0: apparmor: fix boolean + argument in apparmor_mmap_file + - SAUCE: apparmor5.0.0 [17/53]: apparmor-next 7.0: apparmor: drop + in_atomic flag in common_mmap, and common_file_perm + - SAUCE: apparmor5.0.0 [18/53]: apparmor-next 7.0: apparmor: account for + in_atomic removal in common_file_perm + - SAUCE: apparmor5.0.0 [19/53]: apparmor-next 7.0: apparmor: return + -ENOMEM in unpack_perms_table upon alloc failure + - SAUCE: apparmor5.0.0 [20/53]: apparmor-next 7.0: apparmor: guard against + free routines being called with a NULL + - SAUCE: apparmor5.0.0 [21/53]: apparmor-next 7.0: apparmor: move check + for aa_null file to cover all cases + - SAUCE: apparmor5.0.0 [22/53]: apparmor-next 7.0: apparmor: fix label and + profile debug macros + - SAUCE: apparmor5.0.0 [23/53]: apparmor-next 7.0: apparmor: + refactor/cleanup cred helper fns. + - SAUCE: apparmor5.0.0 [24/53]: apparmor-next 7.0: apparmor: fix rlimit + for posix cpu timers + - SAUCE: apparmor5.0.0 [25/53]: apparmor-next 7.0: apparmor: fix fast path + cache check for unix sockets + - SAUCE: apparmor5.0.0 [26/53]: apparmor-next 7.0: apparmor: remove + apply_modes_to_perms from label_match + - SAUCE: apparmor5.0.0 [27/53]: apparmor-next 7.0: apparmor: make + label_match return a consistent value + - SAUCE: apparmor5.0.0 [28/53]: apparmor-next 7.0: apparmor: split + xxx_in_ns into its two separate semantic use cases + - SAUCE: apparmor5.0.0 [29/53]: apparmor-next 7.0: apparmor: avoid per-cpu + hold underflow in aa_get_buffer + - SAUCE: apparmor5.0.0 [30/53]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [31/53]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [32/53]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [33/53]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [34/53]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [35/53]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [36/53]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [37/53]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + - SAUCE: apparmor5.0.0 [38/53]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [39/53]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [40/53]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [41/53]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [42/53]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [43/53]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [44/53]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + - SAUCE: apparmor5.0.0 [45/53]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [46/53]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [47/53]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [48/53]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [49/53]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [50/53]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [51/53]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [52/53]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [53/53]: apparmor: prevent profile->disconnected + double free in aa_free_profile + + * Blacklisted sbsa_gwdt module makes machines reboot (LP: #2138924) + - [Packaging] remove sbsa_gwdt from watchdog blacklist + + * Integrate IgH EtherCAT master (LP: #2138621) + - SAUCE: ubuntu/igh-ecat: Import IgH EtherCAT master + - SAUCE: igh-ecat: Plug IgH EtherCAT master into Kbuild + - SAUCE: igh-ecat: Fix build failure with kernel 6.19 + - [Config] Enable IgH EtherCAT master + + * TBT call trace while connecting TBT4 monitor on TBT5 port (LP: #2137613) + - SAUCE: thunderbolt: log path activation failures without WARN backtraces + + * Boot up hang with ucsi call trace while plug power cord or device on tbt5 + port (LP: #2127764) + - SAUCE: usb: typec: ucsi: Fix workqueue destruction race during connector + cleanup + + * Ease the sysfs call trace which comes from ucsi firmware issue + (LP: #2127960) + - usb: typec: ucsi: Detect and skip duplicate altmodes from buggy firmware + - usb: typec: ucsi: Add duplicate detection to nvidia registration path + - usb: typec: ucsi: yoga_c630: Remove redundant duplicate altmode handling + + * Enable RTL ASPM for more new Dell platforms (LP: #2133144) + - SAUCE: r8169: Add more Dell platforms to enable ASPM + + * Enable RTL ASPM for new Dell platforms (LP: #2121200) + - SAUCE: r8169: enable ASPM on all new Dell platforms + + * Miscellaneous Ubuntu changes + - [Packaging] Bump clang build-dep to match the current default. + - [Config] updateconfig after rebase to v6.19-rc6 + - [Packaging] update Ubuntu.md + + -- Timo Aaltonen Fri, 23 Jan 2026 17:50:01 +0200 + +linux-unstable (6.19.0-1.1) resolute; urgency=medium + + * resolute/linux-unstable: 6.19.0-1.1 -proposed tracker (LP: #2138287) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.10.20) + - [Packaging] update variants + + * Miscellaneous Ubuntu changes + - SAUCE: (lockdown) efi,lockdown: fix kernel lockdown on Secure Boot + - [Config] updateconfigs following v6.19-rc4 rebase + - SAUCE: aaeon: The modules need to import ASUS_WMI now + - Update Changes.md + - SAUCE: arm64: dts: qcom: x1-acer-swift-14: Fix includes + - [Packaging] Drop failing dkms packages + + -- Timo Aaltonen Tue, 13 Jan 2026 15:36:30 +0200 + +linux-unstable (6.19.0-0.0) resolute; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Wed, 17 Dec 2025 14:08:41 +0200 + +linux-unstable (6.18.0-6.6) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-6.6 -proposed tracker (LP: #2133502) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.10.20) + + * Miscellaneous Ubuntu changes + - Update dropped.txt + - [Packaging] debian.master/dkms-versions: Drop failing dkms packages + - rename dropped.txt to Changes.md + + -- Paolo Pisati Mon, 01 Dec 2025 14:52:34 +0100 + +linux-unstable (6.18.0-5.5) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-5.5 -proposed tracker (LP: #2131673) + + * Re-enable INTEL_SKL_INT3472 for kernels >= 6.16 for Intel IPU camera + (LP: #2128792) + - Revert "UBUNTU: [Config] FTBFS: disable INTEL_SKL_INT3472" + - Revert "UBUNTU: SAUCE: platform/x86: int3472: Add handshake GPIO + function" + + * i40e driver is triggering VF resets on every link state change + (LP: #2130552) + - i40e: avoid redundant VF link state updates + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.18-rc6 rebase + + -- Paolo Pisati Tue, 18 Nov 2025 11:23:48 +0100 + +linux-unstable (6.18.0-4.4) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-4.4 -proposed tracker (LP: #2131211) + + * CAP_PERFMON insufficient to get perf data (LP: #2131046) + - SAUCE: perf/core: Allow CAP_PERFMON for paranoid level 4 + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.18-rc5 rebase + + -- Paolo Pisati Thu, 13 Nov 2025 12:55:49 +0100 + +linux-unstable (6.18.0-3.3) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-3.3 -proposed tracker (LP: #2129919) + + * [26.04 FEAT] Set Architecture Level (ALS) to z15 (LP: #2126577) + - [Config] Raise the architectural level set for s390x to z15 + + * Miscellaneous Ubuntu changes + - [Config]: Enable CONFIG_CRYPTO_BENCHMARK + - [Config] updateconfigs after v6.18-rc3 rebase + + -- Paolo Pisati Mon, 27 Oct 2025 11:07:35 +0100 + +linux-unstable (6.18.0-2.2) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-2.2 -proposed tracker (LP: #2129552) + + * Miscellaneous Ubuntu changes + - [Config] update rustc version + + -- Paolo Pisati Wed, 22 Oct 2025 15:42:17 +0200 + +linux-unstable (6.18.0-1.1) resolute; urgency=medium + + * resolute/linux-unstable: 6.18.0-1.1 -proposed tracker (LP: #2129038) + + * Packaging resync (LP: #1786013) + - [Packaging] update Ubuntu.md + + * Miscellaneous Ubuntu changes + - [Packaging] Rename to linux-unstable and move to 6.18 + - [Config] updateconfigs following v6.18-rc1 rebase + - [Config] apparmor: remove SECURITY_APPARMOR_RESTRICT_USERNS + - [Packaging] debian.master/dkms-versions: Drop failing dkms packages + - [Config] updateconfigs following v6.18-rc2 rebase + - move to resolute + + * Miscellaneous upstream changes + - Revert "audit: fix skb leak when audit rate limit is exceeded" + - Revert "audit: init ab->skb_list earlier in audit_buffer_alloc()" + - Revert "audit: add record for multiple object contexts" + - Revert "audit: add record for multiple task security contexts" + - Revert "lsm: security_lsmblob_to_secctx module selection" + - audit: fix skb leak when audit rate limit is exceeded + + -- Paolo Pisati Tue, 21 Oct 2025 16:26:01 +0200 + +linux-unstable (6.18.0-0.0) resolute; urgency=medium + + * questing/linux: 6.17.0-6.6 -proposed tracker (LP: #2126040) + + * Questing update: v6.17.1 upstream stable release (LP: #2126948) + - blk-mq: fix blk_mq_tags double free while nr_requests grown + - gcc-plugins: Remove TODO_verify_il for GCC >= 16 + - scsi: target: target_core_configfs: Add length check to avoid buffer + overflow + - ALSA: usb-audio: fix race condition to UAF in snd_usbmidi_free + - wifi: rtw89: fix use-after-free in rtw89_core_tx_kick_off_and_wait() + - media: b2c2: Fix use-after-free causing by irq_check_work in + flexcop_pci_remove + - media: i2c: tc358743: Fix use-after-free bugs caused by orphan timer in + probe + - media: tuner: xc5000: Fix use-after-free in xc5000_release + - media: rc: fix races with imon_disconnect() + - media: uvcvideo: Mark invalid entities with id UVC_INVALID_ENTITY_ID + - mm: swap: check for stable address space before operating on the VMA + - wifi: ath11k: fix NULL dereference in ath11k_qmi_m3_load() + - media: iris: Fix memory leak by freeing untracked persist buffer + - media: stm32-csi: Fix dereference before NULL check + - ASoC: qcom: audioreach: fix potential null pointer dereference + - Linux 6.17.1 + + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] riscv64: Update EFI_SBAT_FILE + - [Config] riscv64: Enable EFI_ZBOOT + - [Config] riscv64: Disable support for non-RVA23 SoCs + - [Config] riscv64: Disable RISCV_ISA_FALLBACK + - [Config] riscv64: Sync config with other architectures + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs after rebase to 6.17 + + -- Timo Aaltonen Tue, 07 Oct 2025 14:15:18 +0300 + +linux (6.17.0-5.5) questing; urgency=medium + + * questing/linux: 6.17.0-5.5 -proposed tracker (LP: #2125319) + + * Packaging resync (LP: #1786013) + - [Packaging] resync git-ubuntu-log + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.09.22) + + * [SRU] Failed to create source package: Unmet build dependencies: + bpftool:native (LP: #2122310) + - [Packaging] fix build profile spec for bpftool + + * UBUNTU: fan: fail to check kmalloc() return could cause a NULL pointer + dereference (LP: #2125053) + - SAUCE: fan: vxlan: check memory allocation for map + + * iproute2 breaking netplan DEP-8 tests in Questing, unexpected "fan-map" in + JSON output (LP: #2124257) + - SAUCE: fan: don't enforce a specific enum value for IFLA_VXLAN_FAN_MAP + + * memory leaks when configuring a small rate limit in audit (LP: #2122554) + - SAUCE: audit: fix skb leak when audit rate limit is exceeded + + * Support AMD Image Signal Processing (ISP) unit V4.0 (LP: #2110092) + - SAUCE: media: platform: amd: Introduce amd isp4 capture driver + - SAUCE: media: platform: amd: low level support for isp4 firmware + - SAUCE: media: platform: amd: Add isp4 fw and hw interface + - SAUCE: media: platform: amd: isp4 subdev and firmware loading handling + added + - SAUCE: media: platform: amd: isp4 video node and buffers handling added + - SAUCE: media: platform: amd: isp4 debug fs logging and more descriptive + errors + - SAUCE: Documentation: add documentation of AMD isp 4 driver + - [Config] Enable AMD_ISP4 + + * 25.10 Snapdragon X Elite: Sync concept kernel changes (LP: #2121477) + - phy: qcom: qmp-combo: Rename 'mode' to 'phy_mode' + - phy: qcom: qmp-combo: store DP phy power state + - phy: qcom: qmp-combo: introduce QMPPHY_MODE + - phy: qcom: qmp-combo: register a typec mux to change the QMPPHY_MODE + - arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint reader + - dt-bindings: arm: qcom: Add Dell Latitude 7455 + - dt-bindings: display: panel: samsung,atna40cu11: document ATNA40CU11 + - dt-bindings: display: panel: samsung,atna40ct06: document ATNA40CT06 + - drm/panel-edp: Add BOE NV140WUM-N64 + - arm64: dts: qcom: x1-crd: Enable HBR3 on external DPs + - SAUCE: drm/dp: drm_edp_backlight_set_level: do not always send 3-byte + commands + - SAUCE: drm/edp-panel: Add touchscreen panel used by Lenovo X13s + - SAUCE: net: qrtr: mhi: synchronize qrtr and mhi preparation + - SAUCE: arm64: dts: qcom: x1e78100-t14s-oled: add eDP panel + - SAUCE: wip: arm64: dts: qcom: x1e80100-crd: Add WiFi/BT pwrseq + - SAUCE: wip: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + - SAUCE: drm/dp: clamp PWM bit count to advertised MIN and MAX + capabilities + - SAUCE: arm64: dts: qcom: x1e80100-pmics: Disable pm8010 by default + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: Add Left/Right + Speakers and Tweeter + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: enable MICs LDO + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: Mark audio channels + as left-right swapped + - SAUCE: arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13: Set up 4-lane DP + - SAUCE: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document default + phy mode + - SAUCE: phy: qcom: qmp-combo: get default qmpphy_mode from DT + - SAUCE: arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes + - SAUCE: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Reference usb- + switch.yaml to allow mode-switch + - SAUCE: dt-bindings: arm: qcom: Add Asus Zenbook A14 UX3407QA LCD/OLED + variants + - SAUCE: arm64: dts: qcom: Rework X1-based Asus Zenbook A14's displays + - SAUCE: arm64: dts: qcom: x1e80100-asus-zenbook-a14: Enable WiFi, + Bluetooth + - SAUCE: arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude + 7455 + - SAUCE: firmware: qcom: scm: Allow QSEECOM on Dell Inspiron 7441 / + Latitude 7455 + - SAUCE: dt-bindings: arm: qcom: Add Acer Swift 14 AI + - SAUCE: arm64: dts: qcom: x1-acer-swift-14: Add support for Acer Swift 14 + - SAUCE: arm64: dts: qcom: x1e80100: allow mode-switch events to reach the + QMP Combo PHYs + - SAUCE: arm64: dts: qcom: x1e80100: move dp0/1/2 data-lanes to SoC dtsi + - SAUCE: arm64: dts: qcom: x1e80100: Set up 4-lane DP + - SAUCE: arm64: dts: qcom: x1e80100: move remaining dp0/1/2 data-lanes to + SoC dtsi + - Revert "UBUNTU: SAUCE: Change: cracking sound fix" + + * UBSAN: shift-out-of-bounds in drivers/edac/skx_common.c:452:16 + (LP: #2119713) + - EDAC/i10nm: Skip DIMM enumeration on a disabled memory controller + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs for v6.17-rc6 rebase + + -- Timo Aaltonen Mon, 22 Sep 2025 10:33:58 +0300 + +linux (6.17.0-4.4) questing; urgency=medium + + * questing/linux: 6.17.0-4.4 -proposed tracker (LP: #2122321) + + * [SRU] Do not instantiate SPD5118 sensors on i801 SMBus controllers + (LP: #2114963) + - SAUCE: i2c: i801: Do not instantiate spd5118 under SPD Write Disable + + * initramfs-tools: autopkgtest fails on arm64 with Possible missing firmware + /lib/firmware/apple/dfrmtfw-*.bin for built-in driver apple_z2 + (LP: #2115758) + - [Config] Set TOUCHSCREEN_APPLE_Z2=m (arm64) + + * Support TDX host in questing (LP: #2121873) + - SAUCE: x86/kexec: Consolidate relocate_kernel() function parameters + - SAUCE: x86/sme: Use percpu boolean to control WBINVD during kexec + - SAUCE: x86/virt/tdx: Mark memory cache state incoherent when making + SEAMCALL + - SAUCE: x86/kexec: Disable kexec/kdump on platforms with TDX partial + write erratum + - SAUCE: x86/virt/tdx: Remove the !KEXEC_CORE dependency + - SAUCE: x86/virt/tdx: Update the kexec section in the TDX documentation + - SAUCE: KVM: TDX: Explicitly do WBINVD when no more TDX SEAMCALLs + - [Config] enable TDX host support + + * minimal kernel lacks modules for blk disk in arm64 openstack environments + where config_drive is required (LP: #2118499) + - [Config] Enable SYM53C8XX_2 on arm64 + + * Miscellaneous Ubuntu changes + - [Config] Re-enable Rust support, and make sure it doesn't get disabled + by accident + - [Config] updateconfigs for v6.17-rc5 rebase + + -- Timo Aaltonen Mon, 08 Sep 2025 17:10:38 +0300 + +linux (6.17.0-3.3) questing; urgency=medium + + * questing/linux: 6.17.0-3.3 -proposed tracker (LP: #2121512) + + * Enable Xilinx PS UART configs (LP: #2121337) + - [Config] Enable Xilinx PS UART configs + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.08.25) + + * Plucky/Questing fails to boot on (older) Macs (LP: #2105402) + - SAUCE: hack: efi/libstub: enable t14s boot failure hack only on arm64 + + * Miscellaneous Ubuntu changes + - [Packaging] Fix linux-modules Description, add dependency on wireless- + regdb from old -extra + - [Packaging] Fix arch list for bpftool build-dep + + -- Timo Aaltonen Thu, 28 Aug 2025 10:37:03 +0300 + +linux (6.17.0-2.2) questing; urgency=medium + + * questing/linux: 6.17.0-2.2 -proposed tracker (LP: #2121374) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.08.25) + + * enable Mediatek media platform drivers on arm64 (LP: #2116138) + - [Config] enable mediatek media platform drivers + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/38]: Stacking: Audit: Create audit_stamp + structure + - SAUCE: apparmor5.0.0 [2/38]: Stacking: Audit: Allow multiple records in + an audit_buffer + - SAUCE: apparmor5.0.0 [3/38]: Stacking: LSM: security_lsmblob_to_secctx + module selection + - SAUCE: apparmor5.0.0 [4/38]: Stacking: Audit: Add record for multiple + task security contexts + - SAUCE: apparmor5.0.0 [5/38]: Stacking: Audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor5.0.0 [6/38]: Stacking: Audit: Add record for multiple + object contexts + - SAUCE: apparmor5.0.0 [7/38]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [8/38]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [9/38]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor5.0.0 [10/38]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [11/38]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [12/38]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [13/38]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [14/38]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [15/38]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [16/38]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [18/38]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [19/38]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [20/38]: aoparmor: userns: Add support for execpath + in userns + - SAUCE: apparmor5.0.0 [21/38]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [22/38]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [23/38]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [26/38]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [27/38]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [28/38]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [29/38]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [30/38]: apparmor: add AA_DEBUG_PROFILE to have + debug on profiles with flag set + - SAUCE: apparmor5.0.0 [31/38]: apparmor: make str table more generic and + be able to have multiple entries + - SAUCE: apparmor5.0.0 [32/38]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [33/38]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [34/38]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [35/38]: UBUNTU: SAUCE: apparmor5.0.0 [35/38]: + apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [36/38]: apparmor: mmap_file() doesn't need to be + called atomically + - SAUCE: apparmor5.0.0 [37/38]: apparmor: guard against free routines + being called with a NULL + - SAUCE: apparmor5.0.0 [38/38]: apparmor: prevent profile->disconnected + double free in aa_free_profile + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * Installation of AppArmor on a 6.14 kernel produces error message "Illegal + number: yes" (LP: #2102680) + - SAUCE: apparmor5.0.0 [24/38]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [25/38]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [17/38]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + + * nvme no longer detected on boot after upgrade to 6.8.0-60 (LP: #2111521) + - SAUCE: PCI: Disable RRS polling for Intel SSDPE2KX020T8 nvme + + * Miscellaneous Ubuntu changes + - [Packaging] Use host bpftool if doing cross-compiling + - [Packaging] Rename to linux + - [Packaging] d/t/ubuntu-regression-suite: use https to clone + - [Packaging] d/t/control: add snapd and fuse-overlayfs dependencies + - [Packaging] Drop/update some dkms packages. + + -- Timo Aaltonen Tue, 26 Aug 2025 17:15:12 +0300 + +linux-unstable (6.17.0-1.1) questing; urgency=medium + + * questing/linux-unstable: 6.17.0-1.1 -proposed tracker (LP: #2121054) + + * Enable CONFIG_IPV6_OPTIMISTIC_DAD (LP: #1728366) + - [Config] Enable CONFIG_IPV6_OPTIMISTIC_DAD + + * No IP Address assigned after hot-plugging Ethernet cable on HP Platform + (LP: #2115393) + - Revert "e1000e: change k1 configuration on MTP and later platforms" + + * sources list generation using dwarfdump takes up to 0.5hr in build process + (LP: #2104911) + - [Packaging] Don't generate list of source files + + * Miscellaneous Ubuntu changes + - [Config] updateconfig following rebase to v6.17-rc2 + - [Packaging] Renane to linux-unstable + - SAUCE: gpio: aaeon: use new GPIO line value setter callbacks + - [Packaging] debian.master/dkms-versions: Drop failing dkms packages + - [Packaging] Don't suggest linux-modules-extra + + -- Timo Aaltonen Thu, 21 Aug 2025 11:22:12 +0300 + +linux-unstable (6.17.0-0.0) questing; urgency=medium + + * dummy entry + + -- Timo Aaltonen Mon, 18 Aug 2025 18:27:35 +0300 + +linux (6.16.0-16.16) questing; urgency=medium + + * questing/linux: 6.16.0-16.16 -proposed tracker (LP: #2120720) + + -- Paolo Pisati Sat, 16 Aug 2025 17:31:00 +0200 + +linux (6.16.0-14.14) questing; urgency=medium + + * questing/linux: 6.16.0-14.14 -proposed tracker (LP: #2120657) + + * BPF header file in wrong location (LP: #2118965) + - [Packaging] Install bpf header to correct location + + * enlarge the number of the serial port for sh-sci serial driver + (LP: #2116140) + - [Config] enlarge CONFIG_SERIAL_SH_SCI_NR_UARTS + + * Ubuntu 24.04+ arm64: screen resolution fixed to 1024x768 with last kernel + update (LP: #2115068) + - [Config] Replace FB_HYPERV with DRM_HYPERV + + * Miscellaneous Ubuntu changes + - [Packaging] move to unversioned gcc by default + - [Config] bump toolchain version to gcc-15 + + -- Paolo Pisati Fri, 15 Aug 2025 08:24:39 +0200 + +linux (6.16.0-13.13) questing; urgency=medium + + * questing/linux: 6.16.0-13.13 -proposed tracker (LP: #2119951) + + * Miscellaneous Ubuntu changes + - [Packaging] debian.master/dkms-versions -- remove ipu6 since it's + upstream + + -- Paolo Pisati Thu, 07 Aug 2025 16:32:32 +0200 + +linux (6.16.0-12.12) questing; urgency=medium + + * questing/linux: 6.16.0-12.12 -proposed tracker (LP: #2119711) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.07.28) + - [Packaging] resync git-ubuntu-log + - [Packaging] update variants + - [Packaging] update annotations scripts + + -- Paolo Pisati Thu, 07 Aug 2025 09:59:27 +0200 + +linux (6.16.0-11.11) questing; urgency=medium + + * questing/linux: 6.16.0-11.11 -proposed tracker (LP: #2119360) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/93]: Stacking: Audit: Create audit_stamp + structure + - SAUCE: apparmor5.0.0 [2/93]: Stacking: Audit: Allow multiple records in + an audit_buffer + - SAUCE: apparmor5.0.0 [3/93]: Stacking: LSM: security_lsmblob_to_secctx + module selection + - SAUCE: apparmor5.0.0 [4/93]: Stacking: Audit: Add record for multiple + task security contexts + - SAUCE: apparmor5.0.0 [5/93]: Stacking: Audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor5.0.0 [6/93]: Stacking: Audit: Add record for multiple + object contexts + - SAUCE: apparmor5.0.0 [7/93]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [8/93]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [9/93]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor5.0.0 [10/93]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [11/93]: 6.17 apparmor-next: apparmor: Use + str_yes_no() helper function + - SAUCE: apparmor5.0.0 [12/93]: 6.17 apparmor-next: apparmor: Improve + debug print infrastructure + - SAUCE: apparmor5.0.0 [13/93]: 6.17 apparmor-next: apparmor: cleanup: + attachment perm lookup to use lookup_perms() + - SAUCE: apparmor5.0.0 [14/93]: 6.17 apparmor-next: apparmor: remove + redundant unconfined check. + - SAUCE: apparmor5.0.0 [15/93]: 6.17 apparmor-next: apparmor: switch + signal mediation to use RULE_MEDIATES + - SAUCE: apparmor5.0.0 [16/93]: 6.17 apparmor-next: apparmor: ensure + labels with more than one entry have correct flags + - SAUCE: apparmor5.0.0 [17/93]: 6.17 apparmor-next: apparmor: remove + explicit restriction that unconfined cannot use change_hat + - SAUCE: apparmor5.0.0 [18/93]: 6.17 apparmor-next: apparmor: cleanup: + refactor file_perm() to doc semantics of some checks + - SAUCE: apparmor5.0.0 [19/93]: 6.17 apparmor-next: apparmor: carry + mediation check on label + - SAUCE: apparmor5.0.0 [20/93]: 6.17 apparmor-next: apparmor: add + additional flags to extended permission. + - SAUCE: apparmor5.0.0 [21/93]: 6.17 apparmor-next: apparmor: add support + for profiles to define the kill signal + - SAUCE: apparmor5.0.0 [22/93]: 6.17 apparmor-next: apparmor: fix + x_table_lookup when stacking is not the first entry + - SAUCE: apparmor5.0.0 [23/93]: 6.17 apparmor-next: apparmor: add ability + to mediate caps with policy state machine + - SAUCE: apparmor5.0.0 [24/93]: 6.17 apparmor-next: apparmor: remove + af_select macro + - SAUCE: apparmor5.0.0 [25/93]: 6.17 apparmor-next: apparmor: lift kernel + socket check out of critical section + - SAUCE: apparmor5.0.0 [26/93]: 6.17 apparmor-next: apparmor: in + preparation for finer networking rules rework match_prot + - SAUCE: apparmor5.0.0 [27/93]: 6.17 apparmor-next: apparmor: add fine + grained af_unix mediation + - SAUCE: apparmor5.0.0 [28/93]: 6.17 apparmor-next: apparmor: gate make + fine grained unix mediation behind v9 abi + - SAUCE: apparmor5.0.0 [29/93]: 6.17 apparmor-next: apparmor: fix dbus + permission queries to v9 ABI + - SAUCE: apparmor5.0.0 [30/93]: 6.17 apparmor-next: apparmor: Fix checking + address of an array in accum_label_info() + - SAUCE: apparmor5.0.0 [31/93]: 6.17 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor5.0.0 [32/93]: 6.17 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor5.0.0 [33/93]: 6.17 apparmor-next: apparmor: fix typos + and spelling errors + - SAUCE: apparmor5.0.0 [34/93]: 6.17 apparmor-next: apparmor: use the + condition in AA_BUG_FMT even with debug disabled + - SAUCE: apparmor5.0.0 [35/93]: 6.17 apparmor-next: apparmor: Remove + unused variable 'sock' in __file_sock_perm() + - SAUCE: apparmor5.0.0 [68/93]: Revert "6.17 apparmor-next: apparmor: fix + dbus permission queries to v9 ABI" + - SAUCE: apparmor5.0.0 [69/93]: Revert "6.17 apparmor-next: apparmor: gate + make fine grained unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [70/93]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [71/93]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [72/93]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [73/93]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [75/93]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [76/93]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [80/93]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [83/93]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [84/93]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [85/93]: apparmor: prompt: enable userspace upcall + for mediation + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * Installation of AppArmor on a 6.14 kernel produces error message "Illegal + number: yes" (LP: #2102680) + - SAUCE: apparmor5.0.0 [81/93]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [82/93]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [74/93]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor5.0.0 [36/93]: 6.17 apparmor-next: security/apparmor: use + kfree_sensitive() in unpack_secmark() + - SAUCE: apparmor5.0.0 [37/93]: 6.17 apparmor-next: apparmor: Fix + incorrect profile->signal range check + - SAUCE: apparmor5.0.0 [38/93]: 6.17 apparmor-next: apparmor: fix some + kernel-doc issues in header files + - SAUCE: apparmor5.0.0 [39/93]: 6.17 apparmor-next: apparmor: ensure + WB_HISTORY_SIZE value is a power of 2 + - SAUCE: apparmor5.0.0 [40/93]: 6.17 apparmor-next: apparmor: fix loop + detection used in conflicting attachment resolution + - SAUCE: apparmor5.0.0 [41/93]: 6.17 apparmor-next: apparmor: make all + generated string array headers const char *const + - SAUCE: apparmor5.0.0 [42/93]: 6.17 apparmor-next: apparmor: force audit + on unconfined exec if info is set by find_attach + - SAUCE: apparmor5.0.0 [43/93]: 6.17 apparmor-next: apparmor: move the + "conflicting profile attachments" infostr to a const declaration + - SAUCE: apparmor5.0.0 [44/93]: 6.17 apparmor-next: apparmor: include + conflicting attachment info for confined ix/ux fallback + - SAUCE: apparmor5.0.0 [45/93]: 6.17 apparmor-next: apparmor: force + auditing of conflicting attachment execs from confined + - SAUCE: apparmor5.0.0 [46/93]: 6.17 apparmor-next: apparmor: make + debug_values_table static + - SAUCE: apparmor5.0.0 [47/93]: 6.17 apparmor-next: apparmor: Document + that label must be last member in struct aa_profile + - SAUCE: apparmor5.0.0 [48/93]: 6.17 apparmor-next: apparmor: mitigate + parser generating large xtables + - SAUCE: apparmor5.0.0 [49/93]: 6.17 apparmor-next: apparmor: make + __begin_current_label_crit_section() indicate whether put is needed + - SAUCE: apparmor5.0.0 [50/93]: 6.17 apparmor-next: apparmor: update + kernel doc comments for xxx_label_crit_section + - SAUCE: apparmor5.0.0 [51/93]: 6.17 apparmor-next: apparmor: Remove use + of the double lock + - SAUCE: apparmor5.0.0 [52/93]: 6.17 apparmor-next: apparmor: fix af_unix + auditing to include all address information + - SAUCE: apparmor5.0.0 [53/93]: 6.17 apparmor-next: apparmor: fix + AA_DEBUG_LABEL() + - SAUCE: apparmor5.0.0 [54/93]: 6.17 apparmor-next: apparmor: fix + regression in fs based unix sockets when using old abi + - SAUCE: apparmor5.0.0 [55/93]: 6.17 apparmor-next: apparmor: make sure + unix socket labeling is correctly updated. + - SAUCE: apparmor5.0.0 [56/93]: 6.17 apparmor-next: apparmor: shift ouid + when mediating hard links in userns + - SAUCE: apparmor5.0.0 [57/93]: 6.17 apparmor-next: apparmor: shift uid + when mediating af_unix in userns + - SAUCE: apparmor5.0.0 [58/93]: 6.17 apparmor-next: apparmor: Fix 8-byte + alignment for initial dfa blob streams + - SAUCE: apparmor5.0.0 [59/93]: 6.17 apparmor-next: apparmor: Fix + unaligned memory accesses in KUnit test + - SAUCE: apparmor5.0.0 [60/93]: 6.17 apparmor-next: apparmor: fix kernel + doc warnings for kernel test robot + - SAUCE: apparmor5.0.0 [61/93]: 6.17 apparmor-next: apparmor: remove + redundant perms.allow MAY_EXEC bitflag set + - SAUCE: apparmor5.0.0 [62/93]: 6.17 apparmor-next: apparmor: fix + documentation mismatches in val_mask_to_str and socket functions + - SAUCE: apparmor5.0.0 [63/93]: 6.17 apparmor-next: apparmor: transition + from a list of rules to a vector of rules + - SAUCE: apparmor5.0.0 [64/93]: 6.17 apparmor-next: apparmor: fix: accept2 + being specifie even when permission table is presnt + - SAUCE: apparmor5.0.0 [65/93]: 6.17 apparmor-next: apparmor: Remove the + unused variable rules + - SAUCE: apparmor5.0.0 [66/93]: 6.17 apparmor-next: apparmor: fix test + error: WARNING in apparmor_unix_stream_connect + - SAUCE: apparmor5.0.0 [67/93]: 6.17 apparmor-next: apparmor: fix + Regression on linux-next (next-20250721) + - SAUCE: apparmor5.0.0 [77/93]: aoparmor: userns: Add support for execpath + in userns + - SAUCE: apparmor5.0.0 [78/93]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [79/93]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [86/93]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [87/93]: apparmor: add AA_DEBUG_PROFILE to have + debug on profiles with flag set + - SAUCE: apparmor5.0.0 [88/93]: apparmor: make str table more generic and + be able to have multiple entries + - SAUCE: apparmor5.0.0 [89/93]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [90/93]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [91/93]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [92/93]: UBUNTU: SAUCE: apparmor5.0.0 [92/93]: + apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [93/93]: apparmor: mmap_file() doesn't need to be + called atomically + + -- Paolo Pisati Sat, 02 Aug 2025 11:25:12 +0200 + +linux (6.16.0-10.10) questing; urgency=medium + + * questing/linux: 6.16.0-10.10 -proposed tracker (LP: #2118882) + + * Miscellaneous Ubuntu changes + - Update dropped.txt + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] disable signing for s390x" + + -- Paolo Pisati Mon, 28 Jul 2025 08:23:12 +0200 + +linux (6.16.0-9.9) questing; urgency=medium + + * questing/linux: 6.16.0-9.9 -proposed tracker (LP: #2117331) + + -- Paolo Pisati Mon, 21 Jul 2025 09:06:33 +0200 + +linux (6.16.0-8.8) questing; urgency=medium + + * questing/linux: 6.16.0-8.8 -proposed tracker (LP: #2117156) + + * Miscellaneous Ubuntu changes + - [Packaging] rename to linux + - [Packaging] disable signing for s390x + + -- Paolo Pisati Thu, 17 Jul 2025 15:11:36 +0200 + +linux-unstable (6.16.0-7.7) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-7.7 -proposed tracker (LP: #2116881) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.16-rc6 rebase + + -- Paolo Pisati Tue, 15 Jul 2025 09:13:15 +0200 + +linux-unstable (6.16.0-6.6) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-6.6 -proposed tracker (LP: #2116265) + + * [UBUNTU 25.04] lszcrypt output shows no cards because ap module has to be + loaded manually (LP: #2116061) + - [Config] s390: Build ap driver into the kernel + + * Miscellaneous Ubuntu changes + - [Packaging] debian.master/control.stub.in: fix dpkg-checkbuilddeps + - [Config] RUSTC_VERSION = 108501 + + -- Paolo Pisati Sun, 13 Jul 2025 10:16:39 +0200 + +linux-unstable (6.16.0-5.5) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-5.5 -proposed tracker (LP: #2115966) + + * Miscellaneous Ubuntu changes + - [Packaging] debian.master/control.stub.in: prepare for cross-compiling + - [Packaging] debian/rules.d/0-common-vars.mk: avoid infinite loop + - [Packaging] debian/rules.d/0-common-vars.mk: use native GCC + - [Packaging] debian/rules.d/0-common-vars.mk: enable linux-tools cross- + compilation + - [Packaging] debian/rules.d/0-common-vars.mk: fix linux-tools cross-build + - [Config] updateconfigs following v6.16-rc5 rebase + + -- Paolo Pisati Tue, 08 Jul 2025 15:09:17 +0200 + +linux-unstable (6.16.0-4.4) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-4.4 -proposed tracker (LP: #2115628) + + -- Paolo Pisati Mon, 30 Jun 2025 13:34:49 +0200 + +linux-unstable (6.16.0-3.3) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-3.3 -proposed tracker (LP: #2115254) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.06.03) + + * arm64: kernel image cannot be booted in UEFI despite EFI stub and ZBOOT + (LP: #2098111) + - [Packaging] Install compressed vmlinuz.efi on arm64 + + * Creating a VXLAN interface with a Fan mapping causes a NULL pointer + dereference caught by ubuntu_fan_smoke_test:sut-scan (LP: #2113992) + - SAUCE: fan: vxlan: parse fan-map from IFLA_VXLAN_FAN_MAP attribute ID + + * Dell AIO backlight is not working, dell_uart_backlight module is missing + (LP: #2083800) + - [Config] enable CONFIG_DELL_UART_BACKLIGHT + + * Miscellaneous Ubuntu changes + - [Packaging] Update debian/signature-inclusion + + -- Paolo Pisati Wed, 25 Jun 2025 13:07:01 +0200 + +linux-unstable (6.16.0-2.2) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-2.2 -proposed tracker (LP: #2114841) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.06.03) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.16-rc2 + + -- Paolo Pisati Wed, 18 Jun 2025 15:33:41 +0200 + +linux-unstable (6.16.0-1.1) questing; urgency=medium + + * questing/linux-unstable: 6.16.0-1.1 -proposed tracker (LP: #2114165) + + * Support Sony IMX471 camera sensor for Intel IPU7 platforms (LP: #2107320) + - SAUCE: media: ipu-bridge: Support imx471 sensor + + * Rotate the Canonical Livepatch key (LP: #2111244) + - [config] prepare for Canonical Livepatch key rotation + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.05.26) + + * Miscellaneous Ubuntu changes + - Update dropped.txt + - Update dropped.txt wrt v6.16-rc1 rebase + - [Config] updateconfigs following v6.16-rc1 + - [Config] FTBFS: disable INTEL_SKL_INT3472 + - SAUCE: binder: turn into module - lock_vma_under_rcu() + - [Packaging] debian.master/dkms-versions -- temporarily remove zfs FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove + v4l2loopback FTBFS + + -- Paolo Pisati Thu, 12 Jun 2025 12:58:18 +0200 + +linux-unstable (6.15.0-2.2) questing; urgency=medium + + * questing/linux-unstable: 6.15.0-2.2 -proposed tracker (LP: #2111721) + + * Miscellaneous Ubuntu changes + - [Config] Updateconfigs for v6.15-rc7 rebase + + -- Paolo Pisati Mon, 26 May 2025 15:24:31 +0200 + +linux-unstable (6.15.0-1.1) questing; urgency=medium + + * questing/linux-unstable: 6.15.0-1.1 -proposed tracker (LP: #2110148) + + * Drop support for modules-extra (LP: #2042831) + - [Packaging] Drop support for modules-extra + + * Miscellaneous Ubuntu changes + - [Packaging] Rename to linux-unstable, bump version + - [Packaging] Re-enable tools build on cross-builds + - [Packaging] debian.master/dkms-versions -- temporarily remove all dkms + - [Packaging] Introduce do_sources_list build flag + - [Config] Updateconfigs for v6.15-rc5 rebase + - SAUCE: Revert "gcc-15: acpi: sprinkle random '__nonstring' crumbles around" + + -- Timo Aaltonen Thu, 08 May 2025 22:29:23 +0300 + +linux-unstable (6.15.0-0.0) questing; urgency=medium + + * Dummy entry + + -- Timo Aaltonen Wed, 07 May 2025 18:41:33 +0300 + +linux (6.14.0-17.17) plucky; urgency=medium + + * plucky/linux: 6.14.0-17.17 -proposed tracker (LP: #2109741) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/2025.04.14) + + * Plucky update: v6.14.4 upstream stable release (LP: #2109367) + - scsi: hisi_sas: Enable force phy when SATA disk directly connected + - wifi: at76c50x: fix use after free access in at76_disconnect + - wifi: mac80211: Update skb's control block key in ieee80211_tx_dequeue() + - wifi: mac80211: Purge vif txq in ieee80211_do_stop() + - wifi: brcmfmac: fix memory leak in brcmf_get_module_param + - wifi: wl1251: fix memory leak in wl1251_tx_work + - scsi: iscsi: Fix missing scsi_host_put() in error path + - scsi: smartpqi: Use is_kdump_kernel() to check for kdump + - md/raid10: fix missing discard IO accounting + - md/md-bitmap: fix stats collection for external bitmaps + - ASoC: dwc: always enable/disable i2s irqs + - ASoC: Intel: avs: Fix null-ptr-deref in avs_component_probe() + - crypto: tegra - Fix IV usage for AES ECB + - ovl: remove unused forward declaration + - RDMA/bnxt_re: Fix budget handling of notification queue + - RDMA/usnic: Fix passing zero to PTR_ERR in usnic_ib_pci_probe() + - RDMA/hns: Fix wrong maximum DMA segment size + - ALSA: hda/cirrus_scodec_test: Don't select dependencies + - ALSA: hda/realtek - Fixed ASUS platform headset Mic issue + - ASoC: cs42l43: Reset clamp override on jack removal + - RDMA/core: Silence oversized kvmalloc() warning + - firmware: cs_dsp: test_bin_error: Fix uninitialized data used as fw version + - Bluetooth: hci_event: Fix sending MGMT_EV_DEVICE_FOUND for invalid address + - Bluetooth: btrtl: Prevent potential NULL dereference + - Bluetooth: qca: fix NV variant for one of WCN3950 SoCs + - Bluetooth: l2cap: Check encryption key size on incoming connection + - RDMA/bnxt_re: Remove unusable nq variable + - ipv6: add exception routes to GC list in rt6_insert_exception + - xen: fix multicall debug feature + - mlxbf-bootctl: use sysfs_emit_at() in secure_boot_fuse_state_show() + - wifi: iwlwifi: pcie: set state to no-FW before reset handshake + - Revert "wifi: mac80211: Update skb's control block key in + ieee80211_tx_dequeue()" + - igc: fix PTM cycle trigger logic + - igc: increase wait time before retrying PTM + - igc: move ktime snapshot into PTM retry loop + - igc: handle the IGC_PTP_ENABLED flag correctly + - igc: cleanup PTP module if probe fails + - igc: add lock preventing multiple simultaneous PTM transactions + - perf tools: Remove evsel__handle_error_quirks() + - dt-bindings: soc: fsl: fsl,ls1028a-reset: Fix maintainer entry + - smc: Fix lockdep false-positive for IPPROTO_SMC. + - test suite: use %zu to print size_t + - selftests: mincore: fix tmpfs mincore test failure + - pds_core: fix memory leak in pdsc_debugfs_add_qcq() + - ethtool: cmis_cdb: use correct rpl size in ethtool_cmis_module_poll() + - net: mctp: Set SOCK_RCU_FREE + - net: hibmcge: fix incorrect pause frame statistics issue + - net: hibmcge: fix incorrect multicast filtering issue + - net: hibmcge: fix wrong mtu log issue + - net: hibmcge: fix not restore rx pause mac addr after reset issue + - block: fix resource leak in blk_register_queue() error path + - netlink: specs: ovs_vport: align with C codegen capabilities + - net: openvswitch: fix nested key length validation in the set() action + - can: rockchip_canfd: fix broken quirks checks + - net: ngbe: fix memory leak in ngbe_probe() error path + - octeontx2-pf: handle otx2_mbox_get_rsp errors + - net: ethernet: ti: am65-cpsw: fix port_np reference counting + - eth: bnxt: fix missing ring index trim on error path + - loop: aio inherit the ioprio of original request + - loop: stop using vfs_iter_{read,write} for buffered I/O + - nvmet: pci-epf: always fully initialize completion entries + - nvmet: pci-epf: clear CC and CSTS when disabling the controller + - ata: libata-sata: Save all fields from sense data descriptor + - cxgb4: fix memory leak in cxgb4_init_ethtool_filters() error path + - netlink: specs: rt-link: add an attr layer around alt-ifname + - netlink: specs: rtnetlink: attribute naming corrections + - netlink: specs: rt-link: adjust mctp attribute naming + - netlink: specs: rt-neigh: prefix struct nfmsg members with ndm + - net: b53: enable BPDU reception for management port + - net: bridge: switchdev: do not notify new brentries as changed + - net: txgbe: fix memory leak in txgbe_probe() error path + - net: dsa: mv88e6xxx: avoid unregistering devlink regions which were never + registered + - net: dsa: mv88e6xxx: fix -ENOENT when deleting VLANs and MST is unsupported + - net: dsa: clean up FDB, MDB, VLAN entries on unbind + - net: dsa: free routing table on probe failure + - net: dsa: avoid refcount warnings when ds->ops->tag_8021q_vlan_del() fails + - ptp: ocp: fix start time alignment in ptp_ocp_signal_set + - netfilter: conntrack: fix erronous removal of offload bit + - net: ti: icss-iep: Add pwidth configuration for perout signal + - net: ti: icss-iep: Add phase offset configuration for perout signal + - net: ti: icss-iep: Fix possible NULL pointer dereference for perout request + - net: ethernet: mtk_eth_soc: reapply mdc divider on reset + - net: ethernet: mtk_eth_soc: correct the max weight of the queue limit for + 100Mbps + - net: ethernet: mtk_eth_soc: revise QDMA packet scheduler settings + - riscv: Use kvmalloc_array on relocation_hashtable + - riscv: Properly export reserved regions in /proc/iomem + - riscv: module: Fix out-of-bounds relocation access + - riscv: module: Allocate PLT entries for R_RISCV_PLT32 + - kunit: qemu_configs: SH: Respect kunit cmdline + - thermal: intel: int340x: Fix Panther Lake DLVR support + - riscv: KGDB: Do not inline arch_kgdb_breakpoint() + - riscv: KGDB: Remove ".option norvc/.option rvc" for kgdb_compiled_break + - cpufreq/sched: Fix the usage of CPUFREQ_NEED_UPDATE_LIMITS + - objtool/rust: add one more `noreturn` Rust function for Rust 1.86.0 + - rust: helpers: Remove volatile qualifier from io helpers + - rust: kasan/kbuild: fix missing flags on first build + - rust: disable `clippy::needless_continue` + - rust: kbuild: Don't export __pfx symbols + - rust: kbuild: use `pound` to support GNU Make < 4.3 + - writeback: fix false warning in inode_to_wb() + - Revert "PCI: Avoid reset when disabled via sysfs" + - ASoC: fsl: fsl_qmc_audio: Reset audio data pointers on TRIGGER_START event + - ASoC: codecs:lpass-wsa-macro: Fix vi feedback rate + - ASoC: codecs:lpass-wsa-macro: Fix logic of enabling vi channels + - ASoC: Intel: sof_sdw: Add quirk for Asus Zenbook S16 + - ASoC: qcom: Fix sc7280 lpass potential buffer overflow + - accel/ivpu: Fix the NPU's DPU frequency calculation + - alloc_tag: handle incomplete bulk allocations in vm_module_tags_populate + - asus-laptop: Fix an uninitialized variable + - block: integrity: Do not call set_page_dirty_lock() + - drm/v3d: Fix Indirect Dispatch configuration for V3D 7.1.6 and later + - drm/msm/dpu: Fix error pointers in dpu_plane_virtual_atomic_check + - drm/msm/dpu: drop rogue intr_tear_rd_ptr values + - dma-buf/sw_sync: Decrement refcount on error in sw_sync_ioctl_get_deadline() + - nfs: add missing selections of CONFIG_CRC32 + - nfsd: decrease sc_count directly if fail to queue dl_recall + - i2c: atr: Fix wrong include + - eventpoll: abstract out ep_try_send_events() helper + - eventpoll: Set epoll timeout if it's in the future + - ftrace: fix incorrect hash size in register_ftrace_direct() + - drm/msm/a6xx+: Don't let IB_SIZE overflow + - Bluetooth: l2cap: Process valid commands in too long frame + - Bluetooth: vhci: Avoid needless snprintf() calls + - btrfs: ioctl: don't free iov when btrfs_encoded_read() returns -EAGAIN + - btrfs: correctly escape subvol in btrfs_show_options() + - cpufreq/sched: Explicitly synchronize limits_changed flag handling + - crypto: caam/qi - Fix drv_ctx refcount bug + - hfs/hfsplus: fix slab-out-of-bounds in hfs_bnode_read_key + - i2c: cros-ec-tunnel: defer probe if parent EC is not present + - isofs: Prevent the use of too small fid + - lib/iov_iter: fix to increase non slab folio refcount + - loop: properly send KOBJ_CHANGED uevent for disk device + - loop: LOOP_SET_FD: send uevents for partitions + - mm/compaction: fix bug in hugetlb handling pathway + - mm/gup: fix wrongly calculated returned value in fault_in_safe_writeable() + - mm: fix filemap_get_folios_contig returning batches of identical folios + - mm: fix apply_to_existing_page_range() + - ovl: don't allow datadir only + - ksmbd: Fix dangling pointer in krb_authenticate + - ksmbd: fix use-after-free in __smb2_lease_break_noti() + - ksmbd: fix use-after-free in smb_break_all_levII_oplock() + - ksmbd: Prevent integer overflow in calculation of deadtime + - ksmbd: fix the warning from __kernel_write_iter + - Revert "smb: client: Fix netns refcount imbalance causing leaks and use- + after-free" + - Revert "smb: client: fix TCP timers deadlock after rmmod" + - riscv: Avoid fortify warning in syscall_get_arguments() + - selftests/mm: generate a temporary mountpoint for cgroup filesystem + - slab: ensure slab->obj_exts is clear in a newly allocated slab page + - smb3 client: fix open hardlink on deferred close file error + - string: Add load_unaligned_zeropad() code path to sized_strscpy() + - tracing: Fix filter string testing + - virtiofs: add filesystem context source name check + - x86/microcode/AMD: Extend the SHA check to Zen5, block loading of any + unreleased standalone Zen5 microcode patches + - x86/cpu/amd: Fix workaround for erratum 1054 + - x86/boot/sev: Avoid shared GHCB page for early memory acceptance + - scsi: megaraid_sas: Block zero-length ATA VPD inquiry + - scsi: ufs: exynos: Move UFS shareability value to drvdata + - scsi: ufs: exynos: Disable iocc if dma-coherent property isn't set + - scsi: ufs: exynos: Ensure consistent phy reference counts + - RDMA/cma: Fix workqueue crash in cma_netevent_work_handler + - RAS/AMD/ATL: Include row[13] bit in row retirement + - RAS/AMD/FMPM: Get masked address + - platform/x86: amd: pmf: Fix STT limits + - perf/x86/intel: Allow to update user space GPRs from PEBS records + - perf/x86/intel/uncore: Fix the scale of IIO free running counters on SNR + - perf/x86/intel/uncore: Fix the scale of IIO free running counters on ICX + - perf/x86/intel/uncore: Fix the scale of IIO free running counters on SPR + - drm/repaper: fix integer overflows in repeat functions + - drm/ast: Fix ast_dp connection status + - drm/msm/dsi: Add check for devm_kstrdup() + - drm/msm/a6xx: Fix stale rpmh votes from GPU + - drm/amdgpu: Prefer shadow rom when available + - drm/amd/display: prevent hang on link training fail + - drm/amd: Handle being compiled without SI or CIK support better + - drm/amd/display: Actually do immediate vblank disable + - drm/amd/display: Increase vblank offdelay for PSR panels + - drm/amd/pm: Prevent division by zero + - drm/amd/pm/powerplay: Prevent division by zero + - drm/amd/pm: Add zero RPM enabled OD setting support for SMU14.0.2 + - drm/amd/pm/smu11: Prevent division by zero + - drm/amd/pm/powerplay/hwmgr/smu7_thermal: Prevent division by zero + - drm/amd/pm/swsmu/smu13/smu_v13_0: Prevent division by zero + - drm/amd/pm/powerplay/hwmgr/vega20_thermal: Prevent division by zero + - drm/amdgpu/mes12: optimize MES pipe FW version fetching + - drm/i915/vrr: Add vrr.vsync_{start, end} in vrr_params_changed + - drm/xe: Use local fence in error path of xe_migrate_clear + - drm/virtio: Don't attach GEM to a non-created context in gem_object_open() + - drm/amd/display: Add HP Elitebook 645 to the quirk list for eDP on DP1 + - drm/amd/display: Protect FPU in dml2_validate()/dml21_validate() + - drm/amd/display: Protect FPU in dml21_copy() + - drm/amdgpu/mes11: optimize MES pipe FW version fetching + - drm/amdgpu/dma_buf: fix page_link check + - drm/nouveau: prime: fix ttm_bo_delayed_delete oops + - drm/imagination: fix firmware memory leaks + - drm/imagination: take paired job reference + - drm/virtio: Fix missed dmabuf unpinning in error path of prepare_fb() + - drm/sti: remove duplicate object names + - drm/i915: Fix scanline_offset for LNL+ and BMG+ + - drm/xe: Fix an out-of-bounds shift when invalidating TLB + - Revert "UBUNTU: SAUCE: drm/xe/bmg: Add one additional PCI ID" + - drm/xe/bmg: Add one additional PCI ID + - drm/i915/gvt: fix unterminated-string-initialization warning + - drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC + - drm/i915/dp: Reject HBR3 when sink doesn't support TPS4 + - drm/amdgpu: immediately use GTT for new allocations + - drm/amd/display: Do not enable Replay and PSR while VRR is on in + amdgpu_dm_commit_planes() + - drm/amd/display: Protect FPU in dml2_init()/dml21_init() + - drm/amd/display: Add HP Probook 445 and 465 to the quirk list for eDP on DP1 + - drm/xe/dma_buf: stop relying on placement in unmap + - drm/xe/userptr: fix notifier vs folio deadlock + - drm/xe: Set LRC addresses before guc load + - drm/i915/display: Add macro for checking 3 DSC engines + - drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices + - drm/amd/display/dml2: use vzalloc rather than kzalloc + - drm/amdgpu: fix warning of drm_mm_clean + - drm/mgag200: Fix value in register + - io_uring: don't post tag CQEs on file/buffer registration failure + - arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 + - arm64/sysreg: Add register fields for HDFGRTR2_EL2 + - arm64/sysreg: Add register fields for HDFGWTR2_EL2 + - arm64/sysreg: Add register fields for HFGITR2_EL2 + - arm64/sysreg: Add register fields for HFGRTR2_EL2 + - arm64/sysreg: Add register fields for HFGWTR2_EL2 + - arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 + - cpufreq: Reference count policy in cpufreq_update_limits() + - scripts: generate_rust_analyzer: Add ffi crate + - platform/x86: alienware-wmi-wmax: Add G-Mode support to Alienware m16 R1 + - platform/x86: alienware-wmi-wmax: Extend support to more laptops + - platform/x86: msi-wmi-platform: Rename "data" variable + - platform/x86: msi-wmi-platform: Workaround a ACPI firmware bug + - drm/amd/display: Temporarily disable hostvm on DCN31 + - nvmet-fc: Remove unused functions + - mm/vma: add give_up_on_oom option on modify/merge, use in uffd release + - Revert "wifi: ath12k: Fix invalid entry fetch in ath12k_dp_mon_srng_process" + - MIPS: dec: Declare which_prom() as static + - MIPS: cevt-ds1287: Add missing ds1287.h include + - MIPS: ds1287: Match ds1287_set_base_clock() function types + - wifi: ath12k: Fix invalid entry fetch in ath12k_dp_mon_srng_process + - Linux 6.14.4 + + * Plucky update: v6.14.3 upstream stable release (LP: #2108854) + - ASoC: Intel: adl: add 2xrt1316 audio configuration + - cgroup/cpuset: Fix incorrect isolated_cpus update in + update_parent_effective_cpumask() + - cgroup/cpuset: Fix error handling in remote_partition_disable() + - cgroup/cpuset: Fix race between newly created partition and dying one + - tracing: fprobe: Cleanup fprobe hash when module unloading + - gpiolib: of: Fix the choice for Ingenic NAND quirk + - selftests/futex: futex_waitv wouldblock test should fail + - ublk: fix handling recovery & reissue in ublk_abort_queue() + - drm/virtio: Fix flickering issue seen with imported dmabufs + - drm/i915: Disable RPG during live selftest + - x86/acpi: Don't limit CPUs to 1 for Xen PV guests due to disabled ACPI + - net: ethtool: fix ethtool_ringparam_get_cfg() returns a hds_thresh value + always as 0. + - drm/xe/hw_engine: define sysfs_ops on all directories + - drm/xe: Restore EIO errno return when GuC PC start fails + - ata: pata_pxa: Fix potential NULL pointer dereference in pxa_ata_probe() + - objtool: Fix INSN_CONTEXT_SWITCH handling in validate_unret() + - tipc: fix memory leak in tipc_link_xmit + - codel: remove sch->q.qlen check before qdisc_tree_reduce_backlog() + - net: tls: explicitly disallow disconnect + - octeontx2-pf: qos: fix VF root node parent queue index + - tc: Ensure we have enough buffer space when sending filter netlink + notifications + - net: ethtool: Don't call .cleanup_data when prepare_data fails + - drm/tests: modeset: Fix drm_display_mode memory leak + - drm/tests: helpers: Create kunit helper to destroy a drm_display_mode + - drm/tests: cmdline: Fix drm_display_mode memory leak + - drm/tests: modes: Fix drm_display_mode memory leak + - drm/tests: probe-helper: Fix drm_display_mode memory leak + - net: libwx: handle page_pool_dev_alloc_pages error + - cifs: Fix support for WSL-style symlinks + - ata: sata_sx4: Add error handling in pdc20621_i2c_read() + - drm/i915/huc: Fix fence not released on early probe errors + - s390/cpumf: Fix double free on error in cpumf_pmu_event_init() + - nvmet-fcloop: swap list_add_tail arguments + - net_sched: sch_sfq: use a temporary work area for validating configuration + - net_sched: sch_sfq: move the limit validation + - x86/cpu: Avoid running off the end of an AMD erratum table + - smb: client: fix UAF in decryption with multichannel + - net: phy: move phy_link_change() prior to mdio_bus_phy_may_suspend() + - net: phy: allow MDIO bus PM ops to start/stop state machine for phylink- + controlled PHY + - ipv6: Align behavior across nexthops during path selection + - net: ppp: Add bound checking for skb data on ppp_sync_txmung + - nft_set_pipapo: fix incorrect avx2 match of 5th field octet + - ethtool: cmis_cdb: Fix incorrect read / write length extension + - iommu/exynos: Fix suspend/resume with IDENTITY domain + - iommu/mediatek: Fix NULL pointer deference in mtk_iommu_device_group + - net: libwx: Fix the wrong Rx descriptor field + - perf/core: Simplify the perf_event_alloc() error path + - perf: Fix hang while freeing sigtrap event + - fs: consistently deref the files table with rcu_dereference_raw() + - umount: Allow superblock owners to force umount + - srcu: Force synchronization for srcu_get_delay() + - pm: cpupower: bench: Prevent NULL dereference on malloc failure + - irqchip/gic-v3: Add Rockchip 3568002 erratum workaround + - [Config] updateconfigs for ROCKCHIP_ERRATUM_3568002 + - x86/mm: Clear _PAGE_DIRTY for kernel mappings when we clear _PAGE_RW + - x86/percpu: Disable named address spaces for UBSAN_BOOL with KASAN for GCC < + 14.2 + - x86/ia32: Leave NULL selector values 0~3 unchanged + - x86/cpu: Don't clear X86_FEATURE_LAHF_LM flag in init_amd_k8() on AMD when + running in a virtual machine + - perf: arm_pmu: Don't disable counter in armpmu_add() + - perf/dwc_pcie: fix some unreleased resources + - perf/dwc_pcie: fix duplicate pci_dev devices + - PM: hibernate: Avoid deadlock in hibernate_compressor_param_set() + - Flush console log from kernel_power_off() + - cpufreq/amd-pstate: Invalidate cppc_req_cached during suspend + - arm64: cputype: Add QCOM_CPU_PART_KRYO_3XX_GOLD + - xen/mcelog: Add __nonstring annotations for unterminated strings + - zstd: Increase DYNAMIC_BMI2 GCC version cutoff from 4.8 to 11.0 to work + around compiler segfault + - tracing: Disable branch profiling in noinstr code + - platform/chrome: cros_ec_lpc: Match on Framework ACPI device + - ASoC: SOF: topology: Use krealloc_array() to replace krealloc() + - HID: pidff: Convert infinite length from Linux API to PID standard + - HID: pidff: Do not send effect envelope if it's empty + - HID: pidff: Add MISSING_DELAY quirk and its detection + - HID: pidff: Add MISSING_PBO quirk and its detection + - HID: pidff: Add PERMISSIVE_CONTROL quirk + - HID: pidff: Add hid_pidff_init_with_quirks and export as GPL symbol + - HID: pidff: Add FIX_WHEEL_DIRECTION quirk + - HID: Add hid-universal-pidff driver and supported device ids + - [Config] enable new hid-universal-pidff driver module + - HID: pidff: Add PERIODIC_SINE_ONLY quirk + - HID: pidff: Fix null pointer dereference in pidff_find_fields + - ASoC: amd: ps: use macro for ACP6.3 pci revision id + - ASoC: amd: amd_sdw: Add quirks for Dell SKU's + - ALSA: hda: intel: Fix Optimus when GPU has no sound + - ALSA: hda: intel: Add Lenovo IdeaPad Z570 to probe denylist + - ASoC: fsl_audmix: register card device depends on 'dais' property + - media: uvcvideo: Add quirk for Actions UVC05 + - HID: lenovo: Fix to ensure the data as __le32 instead of u32 + - media: s5p-mfc: Corrected NV12M/NV21M plane-sizes + - mmc: dw_mmc: add a quirk for accessing 64-bit FIFOs in two halves + - ALSA: usb-audio: Fix CME quirk for UF series keyboards + - ASoC: amd: Add DMI quirk for ACP6X mic support + - ALSA: hda/realtek: fix micmute LEDs on HP Laptops with ALC3315 + - ALSA: hda/realtek: fix micmute LEDs on HP Laptops with ALC3247 + - ASoC: amd: yc: update quirk data for new Lenovo model + - platform/x86: x86-android-tablets: Add select POWER_SUPPLY to Kconfig + - wifi: ath9k: use unsigned long for activity check timestamp + - wifi: ath11k: Fix DMA buffer allocation to resolve SWIOTLB issues + - wifi: ath11k: fix memory leak in ath11k_xxx_remove() + - wifi: ath12k: fix memory leak in ath12k_pci_remove() + - wifi: ath12k: Fix invalid entry fetch in ath12k_dp_mon_srng_process + - wifi: ath12k: Avoid memory leak while enabling statistics + - ata: libata-core: Add 'external' to the libata.force kernel parameter + - scsi: mpi3mr: Avoid reply queue full condition + - scsi: mpi3mr: Synchronous access b/w reset and tm thread for reply queue + - net: page_pool: don't cast mp param to devmem + - f2fs: don't retry IO for corrupted data scenario + - wifi: mac80211: add strict mode disabling workarounds + - wifi: mac80211: ensure sdata->work is canceled before initialized. + - scsi: target: spc: Fix RSOC parameter data header size + - net: usb: asix_devices: add FiberGecko DeviceID + - page_pool: avoid infinite loop to schedule delayed worker + - can: flexcan: Add quirk to handle separate interrupt lines for mailboxes + - can: flexcan: add NXP S32G2/S32G3 SoC support + - jfs: Fix uninit-value access of imap allocated in the diMount() function + - fs/jfs: cast inactags to s64 to prevent potential overflow + - fs/jfs: Prevent integer overflow in AG size calculation + - jfs: Prevent copying of nlink with value 0 from disk inode + - jfs: add sanity check for agwidth in dbMount + - wifi: rtw88: Add support for Mercusys MA30N and D-Link DWA-T185 rev. A1 + - ata: libata-eh: Do not use ATAPI DMA for a device limited to PIO mode + - net: sfp: add quirk for 2.5G OEM BX SFP + - wifi: ath12k: Fix invalid data access in ath12k_dp_rx_h_undecap_nwifi + - f2fs: fix to avoid out-of-bounds access in f2fs_truncate_inode_blocks() + - net: sfp: add quirk for FS SFP-10GM-T copper SFP+ module + - ahci: add PCI ID for Marvell 88SE9215 SATA Controller + - ext4: protect ext4_release_dquot against freezing + - Revert "f2fs: rebuild nat_bits during umount" + - wifi: mac80211: fix userspace_selectors corruption + - ext4: ignore xattrs past end + - cdc_ether|r8152: ThinkPad Hybrid USB-C/A Dock quirk + - scsi: st: Fix array overflow in st_setup() + - ahci: Marvell 88SE9215 controllers prefer DMA for ATAPI + - btrfs: harden block_group::bg_list against list_del() races + - wifi: mt76: mt76x2u: add TP-Link TL-WDN6200 ID to device table + - net: vlan: don't propagate flags on open + - tracing: fix return value in __ftrace_event_enable_disable for + TRACE_REG_UNREGISTER + - Bluetooth: btusb: Add new VID/PID for WCN785x + - Bluetooth: btintel_pcie: Add device id of Whale Peak + - Bluetooth: btusb: Add 13 USB device IDs for Qualcomm WCN785x + - Bluetooth: hci_uart: fix race during initialization + - Bluetooth: btusb: Add 2 HWIDs for MT7922 + - Bluetooth: hci_qca: use the power sequencer for wcn6750 + - Bluetooth: qca: simplify WCN399x NVM loading + - Bluetooth: qca: add WCN3950 support + - drm: allow encoder mode_set even when connectors change for crtc + - drm/virtio: Set missing bo->attached flag + - drm/rockchip: Don't change hdmi reference clock rate + - drm/xe/ptl: Update the PTL pci id table + - drm/xe/pf: Don't send BEGIN_ID if VF has no context/doorbells + - drm/xe/vf: Don't try to trigger a full GT reset if VF + - drm/amd/display: Update Cursor request mode to the beginning prefetch always + - drm/amd/display: Guard Possible Null Pointer Dereference + - drm/amd/display: add workaround flag to link to force FFE preset + - drm/amdgpu: Unlocked unmap only clear page table leaves + - drm: panel-orientation-quirks: Add support for AYANEO 2S + - drm: panel-orientation-quirks: Add quirks for AYA NEO Flip DS and KB + - drm: panel-orientation-quirks: Add quirk for AYA NEO Slide + - drm: panel-orientation-quirks: Add new quirk for GPD Win 2 + - drm: panel-orientation-quirks: Add quirk for OneXPlayer Mini (Intel) + - drm/debugfs: fix printk format for bridge index + - drm/bridge: panel: forbid initializing a panel with unknown connector type + - drm/amd/display: Update FIXED_VS Link Rate Toggle Workaround Usage + - drm/amd/display: stop DML2 from removing pipes based on planes + - drivers: base: devres: Allow to release group on device release + - drm/amdkfd: clamp queue size to minimum + - drm/amdkfd: Fix mode1 reset crash issue + - drm/amdkfd: Fix pqm_destroy_queue race with GPU reset + - drm/amdkfd: debugfs hang_hws skip GPU with MES + - drm/xe/xelp: Move Wa_16011163337 from tunings to workarounds + - drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data + - drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off + - drm/rockchip: stop passing non struct drm_device to drm_err() and friends + - PCI: Add Rockchip Vendor ID + - drm/amdgpu: handle amdgpu_cgs_create_device() errors in + amd_powerplay_create() + - drm/amd/display: Prevent VStartup Overflow + - PCI: Enable Configuration RRS SV early + - drm/amdgpu: Fix the race condition for draining retry fault + - PCI: Check BAR index for validity + - PCI: vmd: Make vmd_dev::cfg_lock a raw_spinlock_t type + - drm/amdgpu: grab an additional reference on the gang fence v2 + - fbdev: omapfb: Add 'plane' value check + - tracing: probe-events: Log error for exceeding the number of arguments + - tracing: probe-events: Add comments about entry data storing code + - ktest: Fix Test Failures Due to Missing LOG_FILE Directories + - tpm, tpm_tis: Workaround failed command reception on Infineon devices + - tpm: End any active auth session before shutdown + - pwm: mediatek: Prevent divide-by-zero in pwm_mediatek_config() + - pwm: rcar: Improve register calculation + - pwm: fsl-ftm: Handle clk_get_rate() returning 0 + - pwm: stm32: Search an appropriate duty_cycle if period cannot be modified + - erofs: set error to bio if file-backed IO fails + - bpf: support SKF_NET_OFF and SKF_LL_OFF on skb frags + - ext4: don't treat fhandle lookup of ea_inode as FS corruption + - s390/pci: Fix s390_mmio_read/write syscall page fault handling + - HID: pidff: Clamp PERIODIC effect period to device's logical range + - HID: pidff: Stop all effects before enabling actuators + - HID: pidff: Completely rework and fix pidff_reset function + - HID: pidff: Simplify pidff_upload_effect function + - HID: pidff: Define values used in pidff_find_special_fields + - HID: pidff: Rescale time values to match field units + - HID: pidff: Factor out code for setting gain + - HID: pidff: Move all hid-pidff definitions to a dedicated header + - HID: pidff: Simplify pidff_rescale_signed + - HID: pidff: Use macros instead of hardcoded min/max values for shorts + - HID: pidff: Factor out pool report fetch and remove excess declaration + - HID: pidff: Make sure to fetch pool before checking SIMULTANEOUS_MAX + - HID: hid-universal-pidff: Add Asetek wheelbases support + - HID: pidff: Comment and code style update + - HID: pidff: Support device error response from PID_BLOCK_LOAD + - HID: pidff: Remove redundant call to pidff_find_special_keys + - HID: pidff: Rename two functions to align them with naming convention + - HID: pidff: Clamp effect playback LOOP_COUNT value + - HID: pidff: Compute INFINITE value instead of using hardcoded 0xffff + - HID: pidff: Fix 90 degrees direction name North -> East + - HID: pidff: Fix set_device_control() + - auxdisplay: hd44780: Fix an API misuse in hd44780.c + - dt-bindings: media: st,stmipid02: correct lane-polarities maxItems + - media: mediatek: vcodec: Fix a resource leak related to the scp device in FW + initialization + - media: mtk-vcodec: venc: avoid -Wenum-compare-conditional warning + - media: uapi: rkisp1-config: Fix typo in extensible params example + - media: mgb4: Fix CMT registers update logic + - media: i2c: adv748x: Fix test pattern selection mask + - media: mgb4: Fix switched CMT frequency range "magic values" sets + - media: intel/ipu6: set the dev_parent of video device to pdev + - media: venus: hfi: add a check to handle OOB in sfr region + - media: venus: hfi: add check to handle incorrect queue size + - media: vim2m: print device name after registering device + - media: siano: Fix error handling in smsdvb_module_init() + - media: rockchip: rga: fix rga offset lookup + - xenfs/xensyms: respect hypervisor's "next" indication + - KVM: arm64: PMU: Set raw values from user to PM{C,I}NTEN{SET,CLR}, + PMOVS{SET,CLR} + - arm64: cputype: Add MIDR_CORTEX_A76AE + - arm64: errata: Add QCOM_KRYO_4XX_GOLD to the spectre_bhb_k24_list + - arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB + - arm64: errata: Add KRYO 2XX/3XX/4XX silver cores to Spectre BHB safe list + - KVM: arm64: Tear down vGIC on failed vCPU creation + - KVM: arm64: Set HCR_EL2.TID1 unconditionally + - spi: cadence-qspi: Fix probe on AM62A LP SK + - mtd: rawnand: brcmnand: fix PM resume warning + - tpm, tpm_tis: Fix timeout handling when waiting for TPM status + - accel/ivpu: Fix PM related deadlocks in MS IOCTLs + - media: ov08x40: Properly turn sensor on/off when runtime-suspended + - media: streamzap: prevent processing IR data on URB failure + - media: hi556: Fix memory leak (on error) in hi556_check_hwcfg() + - media: visl: Fix ERANGE error when setting enum controls + - media: platform: stm32: Add check for clk_enable() + - media: xilinx-tpg: fix double put in xtpg_parse_of() + - media: imx219: Adjust PLL settings based on the number of MIPI lanes + - media: v4l2-dv-timings: prevent possible overflow in v4l2_detect_gtf() + - Revert "media: imx214: Fix the error handling in imx214_probe()" + - media: i2c: ccs: Set the device's runtime PM status correctly in remove + - media: i2c: ccs: Set the device's runtime PM status correctly in probe + - media: i2c: ov7251: Set enable GPIO low in probe + - media: i2c: ov7251: Introduce 1 ms delay between regulators and en GPIO + - media: nuvoton: Fix reference handling of ece_node + - media: nuvoton: Fix reference handling of ece_pdev + - media: venus: hfi_parser: add check to avoid out of bound access + - media: venus: hfi_parser: refactor hfi packet parsing logic + - media: i2c: imx319: Rectify runtime PM handling probe and remove + - media: i2c: imx219: Rectify runtime PM handling in probe and remove + - media: i2c: imx214: Rectify probe error handling related to runtime PM + - media: chips-media: wave5: Fix gray color on screen + - media: chips-media: wave5: Avoid race condition in the interrupt handler + - media: chips-media: wave5: Fix a hang after seeking + - media: chips-media: wave5: Fix timeout while testing 10bit hevc fluster + - irqchip/renesas-rzv2h: Fix wrong variable usage in rzv2h_tint_set_type() + - mptcp: sockopt: fix getting IPV6_V6ONLY + - mptcp: sockopt: fix getting freebind & transparent + - block: make sure ->nr_integrity_segments is cloned in blk_rq_prep_clone + - mtd: Add check for devm_kcalloc() + - net: dsa: mv88e6xxx: workaround RGMII transmit delay erratum for 6320 family + - net: dsa: mv88e6xxx: fix internal PHYs for 6320 family + - mtd: Replace kcalloc() with devm_kcalloc() + - clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup + - Revert "wifi: mt76: mt7925: Update mt7925_mcu_uni_[tx,rx]_ba for MLO" + - wifi: mt76: Add check for devm_kstrdup() + - wifi: mt76: mt792x: re-register CHANCTX_STA_CSA only for the mt7921 series + - wifi: mac80211: fix integer overflow in hwmp_route_info_get() + - wifi: mt76: mt7925: ensure wow pattern command align fw format + - wifi: mt76: mt7925: fix country count limitation for CLC + - wifi: mt76: mt7925: fix the wrong link_idx when a p2p_device is present + - wifi: mt76: mt7925: fix the wrong simultaneous cap for MLO + - wifi: mt76: mt7925: adjust rm BSS flow to prevent next connection failure + - wifi: mt76: mt7925: integrate *mlo_sta_cmd and *sta_cmd + - wifi: mt76: mt7925: update the power-saving flow + - scsi: lpfc: Restore clearing of NLP_UNREG_INP in ndlp->nlp_flag + - net: stmmac: Fix accessing freed irq affinity_hint + - io_uring/net: fix accept multishot handling + - io_uring/net: fix io_req_post_cqe abuse by send bundle + - io_uring/kbuf: reject zero sized provided buffers + - ASoC: codecs: wcd937x: fix a potential memory leak in + wcd937x_soc_codec_probe() + - ASoC: q6apm: add q6apm_get_hw_pointer helper + - ASoC: q6apm-dai: schedule all available frames to avoid dsp under-runs + - ASoC: q6apm-dai: make use of q6apm_get_hw_pointer + - ASoC: qdsp6: q6apm-dai: set 10 ms period and buffer alignment. + - ASoC: qdsp6: q6apm-dai: fix capture pipeline overruns. + - ASoC: qdsp6: q6asm-dai: fix q6asm_dai_compr_set_params error path + - ALSA: hda/realtek: Enable Mute LED on HP OMEN 16 Laptop xd000xx + - accel/ivpu: Fix warning in ivpu_ipc_send_receive_internal() + - accel/ivpu: Fix deadlock in ivpu_ms_cleanup() + - arm/crc-t10dif: fix use of out-of-scope array in crc_t10dif_arch() + - arm64/crc-t10dif: fix use of out-of-scope array in crc_t10dif_arch() + - bus: mhi: host: Fix race between unprepare and queue_buf + - ext4: fix off-by-one error in do_split + - f2fs: fix the missing write pointer correction + - f2fs: fix to avoid atomicity corruption of atomic file + - vdpa/mlx5: Fix oversized null mkey longer than 32bit + - udf: Fix inode_getblk() return value + - tpm: do not start chip while suspended + - svcrdma: do not unregister device for listeners + - soc: samsung: exynos-chipid: Add NULL pointer check in exynos_chipid_probe() + - smb311 client: fix missing tcon check when mounting with linux/posix + extensions + - ima: limit the number of open-writers integrity violations + - ima: limit the number of ToMToU integrity violations + - igc: Fix XSK queue NAPI ID mapping + - i3c: master: svc: Use readsb helper for reading MDB + - i3c: Add NULL pointer check in i3c_master_queue_ibi() + - jbd2: remove wrong sb->s_sequence check + - kbuild: exclude .rodata.(cst|str)* when building ranges + - kbuild: Add '-fno-builtin-wcslen' + - leds: rgb: leds-qcom-lpg: Fix pwm resolution max for Hi-Res PWMs + - leds: rgb: leds-qcom-lpg: Fix calculation of best period Hi-Res PWMs + - mfd: ene-kb3930: Fix a potential NULL pointer dereference + - mailbox: tegra-hsp: Define dimensioning masks in SoC data + - locking/lockdep: Decrease nr_unused_locks if lock unused in zap_class() + - lib: scatterlist: fix sg_split_phys to preserve original scatterlist offsets + - mptcp: fix NULL pointer in can_accept_new_subflow + - mptcp: only inc MPJoinAckHMacFailure for HMAC failures + - mtd: inftlcore: Add error check for inftl_read_oob() + - mtd: rawnand: Add status chack in r852_ready() + - mtd: spinand: Fix build with gcc < 7.5 + - arm64: mops: Do not dereference src reg for a set operation + - arm64: tegra: Remove the Orin NX/Nano suspend key + - arm64: mm: Correct the update of max_pfn + - arm64: dts: ti: k3-j784s4-j742s2-main-common: Correct the GICD size + - arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks + - arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang + - arm64: dts: mediatek: mt8173: Fix disp-pwm compatible string + - arm64: dts: exynos: gs101: disable pinctrl_gsacore node + - backlight: led_bl: Hold led_access lock when calling led_sysfs_disable() + - btrfs: fix non-empty delayed iputs list on unmount due to compressed write + workers + - btrfs: tests: fix chunk map leak after failure to add it to the tree + - btrfs: zoned: fix zone activation with missing devices + - btrfs: zoned: fix zone finishing with missing devices + - iommufd: Fix uninitialized rc in iommufd_access_rw() + - iommu/tegra241-cmdqv: Fix warnings due to dmam_free_coherent() + - iommu/vt-d: Put IRTE back into posted MSI mode if vCPU posting is disabled + - iommu/vt-d: Don't clobber posted vCPU IRTE when host IRQ affinity changes + - iommu/vt-d: Fix possible circular locking dependency + - iommu/vt-d: Wire up irq_ack() to irq_move_irq() for posted MSIs + - sparc/mm: disable preemption in lazy mmu mode + - sparc/mm: avoid calling arch_enter/leave_lazy_mmu() in set_ptes + - net: Fix null-ptr-deref by sock_lock_init_class_and_name() and rmmod. + - mm/damon/ops: have damon_get_folio return folio even for tail pages + - mm/damon: avoid applying DAMOS action to same entity multiple times + - mm/rmap: reject hugetlb folios in folio_make_device_exclusive() + - mm: make page_mapped_in_vma() hugetlb walk aware + - mm: fix lazy mmu docs and usage + - mm/mremap: correctly handle partial mremap() of VMA starting at 0 + - mm: add missing release barrier on PGDAT_RECLAIM_LOCKED unlock + - mm/userfaultfd: fix release hang over concurrent GUP + - mm/hwpoison: do not send SIGBUS to processes with recovered clean pages + - mm/hugetlb: move hugetlb_sysctl_init() to the __init section + - mm/hwpoison: introduce folio_contain_hwpoisoned_page() helper + - sctp: detect and prevent references to a freed transport in sendmsg + - x86/xen: fix balloon target initialization for PVH dom0 + - uprobes: Avoid false-positive lockdep splat on CONFIG_PREEMPT_RT=y in the + ri_timer() uprobe timer callback, use raw_write_seqcount_*() + - tracing: fprobe: Fix to lock module while registering fprobe + - tracing: fprobe events: Fix possible UAF on modules + - tracing: Do not add length to print format in synthetic events + - thermal/drivers/rockchip: Add missing rk3328 mapping entry + - CIFS: Propagate min offload along with other parameters from primary to + secondary channels. + - cifs: avoid NULL pointer dereference in dbg call + - cifs: fix integer overflow in match_server() + - cifs: Ensure that all non-client-specific reparse points are processed by + the server + - clk: renesas: r9a07g043: Fix HP clock source for RZ/Five + - clk: qcom: clk-branch: Fix invert halt status bit check for votable clocks + - clk: qcom: gdsc: Release pm subdomains in reverse add order + - clk: qcom: gdsc: Capture pm_genpd_add_subdomain result code + - clk: qcom: gdsc: Set retain_ff before moving to HW CTRL + - crypto: ccp - Fix check for the primary ASP device + - crypto: ccp - Fix uAPI definitions of PSP errors + - dlm: fix error if inactive rsb is not hashed + - dlm: fix error if active rsb is not hashed + - dm-ebs: fix prefetch-vs-suspend race + - dm-integrity: set ti->error on memory allocation failure + - dm-integrity: fix non-constant-time tag verification + - dm-verity: fix prefetch-vs-suspend race + - dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg' + - dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg' + - firmware: cs_dsp: test_control_parse: null-terminate test strings + - ftrace: Add cond_resched() to ftrace_graph_set_hash() + - ftrace: Properly merge notrace hashes + - fuse: {io-uring} Fix a possible req cancellation race + - gpio: mpc8xxx: Fix wakeup source leaks on device unbind + - gpio: tegra186: fix resource handling in ACPI probe path + - gpio: zynq: Fix wakeup source leaks on device unbind + - gve: handle overflow when reporting TX consumed descriptors + - KVM: Allow building irqbypass.ko as as module when kvm.ko is a module + - [Config] updateconfigs for HAVE_KVM_IRQ_BYPASS + - KVM: x86: Explicitly zero-initialize on-stack CPUID unions + - KVM: x86: Acquire SRCU in KVM_GET_MP_STATE to protect guest memory accesses + - landlock: Move code to ease future backports + - landlock: Add the errata interface + - landlock: Add erratum for TCP fix + - landlock: Always allow signals between threads of the same process + - landlock: Prepare to add second errata + - selftests/landlock: Split signal_scoping_threads tests + - selftests/landlock: Add a new test for setuid() + - misc: pci_endpoint_test: Avoid issue of interrupts remaining after + request_irq error + - misc: pci_endpoint_test: Fix displaying 'irq_type' after 'request_irq' error + - misc: pci_endpoint_test: Fix 'irq_type' to convey the correct type + - net: mana: Switch to page pool for jumbo frames + - ntb: use 64-bit arithmetic for the MSI doorbell mask + - of/irq: Fix device node refcount leakage in API of_irq_parse_one() + - of/irq: Fix device node refcount leakage in API of_irq_parse_raw() + - of/irq: Fix device node refcount leakages in of_irq_count() + - of/irq: Fix device node refcount leakage in API irq_of_parse_and_map() + - of/irq: Fix device node refcount leakages in of_irq_init() + - PCI: brcmstb: Fix missing of_node_put() in brcm_pcie_probe() + - PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4 + - PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args() + - PCI: pciehp: Avoid unnecessary device replacement check + - PCI: Fix reference leak in pci_alloc_child_bus() + - PCI: Fix reference leak in pci_register_host_bridge() + - PCI: Fix wrong length of devres array + - phy: freescale: imx8m-pcie: assert phy reset and perst in power off + - pinctrl: qcom: Clear latched interrupt status when changing IRQ type + - pinctrl: samsung: add support for eint_fltcon_offset + - ring-buffer: Use flush_kernel_vmap_range() over flush_dcache_folio() + - s390/pci: Fix zpci_bus_is_isolated_vf() for non-VFs + - s390/virtio_ccw: Don't allocate/assign airqs for non-existing queues + - s390: Fix linker error when -no-pie option is unavailable + - sched_ext: create_dsq: Return -EEXIST on duplicate request + - selftests: mptcp: close fd_in before returning in main_loop + - selftests: mptcp: fix incorrect fd checks in main_loop + - spi: fsl-qspi: use devm function instead of driver remove + - spi: fsl-qspi: Fix double cleanup in probe error path + - thermal/drivers/mediatek/lvts: Disable monitor mode during suspend + - thermal/drivers/mediatek/lvts: Disable Stage 3 thermal threshold + - wifi: ath11k: update channel list in worker when wait flag is set + - arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists + - iommufd: Make attach_handle generic than fault specific + - iommufd: Fail replace if device has not been attached + - x86/e820: Fix handling of subpage regions when calculating nosave ranges in + e820__register_nosave_regions() + - Bluetooth: hci_uart: Fix another race during initialization + - Linux 6.14.3 + + * Plucky update: v6.14.3 upstream stable release (LP: #2108854) // + CVE-2025-37838 + - HSI: ssi_protocol: Fix use after free vulnerability in ssi_protocol Driver + Due to Race Condition + + * Introduce configfs-based interface for gpio-aggregator (LP: #2103496) + - SAUCE: gpio: aggregator: fix "_sysfs" prefix check in + gpio_aggregator_make_group() + - SAUCE: gpio: aggregator: Fix gpio_aggregator_line_alloc() checking + - SAUCE: gpio: aggregator: Return an error if there are no GPIOs in + gpio_aggregator_parse() + - SAUCE: gpio: aggregator: Fix error code in gpio_aggregator_activate() + - SAUCE: gpio: aggregator: Fix leak in gpio_aggregator_parse() + - SAUCE: selftests: gpio: gpio-aggregator: add a test case for _sysfs prefix + reservation + + * [SRU] Fix screen flickering in inverted display mode (LP: #2103617) + - drm/xe/display: Fix fbdev GGTT mapping handling. + + * System could not hit hardware sleep state with specific panel with AMD + KRK/STX under DC mode (LP: #2103480) + - drm/amd/display: Add and use new dm_prepare_suspend() callback + + * WARNING: CPU: 18 PID: 3683 at arch/powerpc/kvm/../../../virt/kvm/vfio.c Call + Traces seen when pci device is detached from the kvm guest (LP: #2104893) + - KVM: PPC: Enable CAP_SPAPR_TCE_VFIO on pSeries KVM guests + + * [SRU] Enable speaker/mic mute LEDs on Lenovo ideapad and thinkbook + (LP: #2106449) + - platform/x86:lenovo-wmi-hotkey-utilities.c: Support for mic and audio mute + LEDs + - [Config] Enable Lenovo wmi hotkey driver + + * OLED panel screen backlight brightness does not change with brightness + hotkey(F6&F7 Key) (LP: #2097818) + - drm/dp: Add eDP 1.5 bit definition + - drm/dp: Increase eDP display control capability size + - drm/i915/backlight: Use proper interface based on eDP version + - drm/i915/backlight: Check Luminance based brightness control for VESA + - drm/i915/backlight: Modify function to get VESA brightness in Nits + - drm/i915/backlight: Add function to change brightness in nits for VESA + - drm/i915/backlight: Setup nits based luminance via VESA + - drm/i915/backlight: Enable nits based luminance + + * Plucky update: v6.14.2 upstream stable release (LP: #2107212) + - fs: support O_PATH fds with FSCONFIG_SET_FD + - watch_queue: fix pipe accounting mismatch + - x86/mm/pat: cpa-test: fix length for CPA_ARRAY test + - m68k: sun3: Use str_read_write() helper in mmu_emu_handle_fault() + - m68k: sun3: Fix DEBUG_MMU_EMU build + - cpufreq: scpi: compare kHz instead of Hz + - seccomp: fix the __secure_computing() stub for !HAVE_ARCH_SECCOMP_FILTER + - smack: dont compile ipv6 code unless ipv6 is configured + - smack: ipv4/ipv6: tcp/dccp/sctp: fix incorrect child socket label + - sched: Cancel the slice protection of the idle entity + - sched/eevdf: Force propagating min_slice of cfs_rq when {en,de}queue tasks + - cpufreq: governor: Fix negative 'idle_time' handling in dbs_update() + - EDAC/igen6: Fix the flood of invalid error reports + - EDAC/{skx_common,i10nm}: Fix some missing error reports on Emerald Rapids + - x86/vdso: Fix latent bug in vclock_pages calculation + - x86/fpu: Fix guest FPU state buffer allocation size + - cpufreq/amd-pstate: Modify the min_perf calculation in adjust_perf callback + - cpufreq/amd-pstate: Pass min/max_limit_perf as min/max_perf to + amd_pstate_update + - cpufreq/amd-pstate: Convert all perf values to u8 + - cpufreq/amd-pstate: Add missing NULL ptr check in amd_pstate_update + - x86/fpu: Avoid copying dynamic FP state from init_task in + arch_dup_task_struct() + - rseq: Update kernel fields in lockstep with CONFIG_DEBUG_RSEQ=y + - x86/platform: Only allow CONFIG_EISA for 32-bit + - [Config] updateconfigs for HAVE_EISA + - x86/sev: Add missing RIP_REL_REF() invocations during sme_enable() + - lockdep/mm: Fix might_fault() lockdep check of current->mm->mmap_lock + - PM: sleep: Adjust check before setting power.must_resume + - cpufreq: tegra194: Allow building for Tegra234 + - RISC-V: KVM: Disable the kernel perf counter during configure + - kunit/stackinit: Use fill byte different from Clang i386 pattern + - watchdog/hardlockup/perf: Fix perf_event memory leak + - x86/split_lock: Fix the delayed detection logic + - selinux: Chain up tool resolving errors in install_policy.sh + - EDAC/ie31200: Fix the size of EDAC_MC_LAYER_CHIP_SELECT layer + - EDAC/ie31200: Fix the DIMM size mask for several SoCs + - EDAC/ie31200: Fix the error path order of ie31200_init() + - dma: Fix encryption bit clearing for dma_to_phys + - dma: Introduce generic dma_addr_*crypted helpers + - arm64: realm: Use aliased addresses for device DMA to shared buffers + - x86/resctrl: Fix allocation of cleanest CLOSID on platforms with no monitors + - cpuidle: Init cpuidle only for present CPUs + - thermal: int340x: Add NULL check for adev + - PM: sleep: Fix handling devices with direct_complete set on errors + - lockdep: Don't disable interrupts on RT in disable_irq_nosync_lockdep.*() + - cpufreq: Init cpufreq only for present CPUs + - perf/ring_buffer: Allow the EPOLLRDNORM flag for poll + - perf: Save PMU specific data in task_struct + - perf: Supply task information to sched_task() + - perf/x86/lbr: Fix shorter LBRs call stacks for the system-wide mode + - sched/deadline: Ignore special tasks when rebuilding domains + - sched/topology: Wrappers for sched_domains_mutex + - sched/deadline: Generalize unique visiting of root domains + - sched/deadline: Rebuild root domain accounting after every update + - x86/traps: Make exc_double_fault() consistently noreturn + - x86/fpu/xstate: Fix inconsistencies in guest FPU xfeatures + - x86/entry: Add __init to ia32_emulation_override_cmdline() + - RISC-V: KVM: Teardown riscv specific bits after kvm_exit + - regulator: pca9450: Fix enable register for LDO5 + - auxdisplay: MAX6959 should select BITREVERSE + - media: verisilicon: HEVC: Initialize start_bit field + - media: platform: allgro-dvt: unregister v4l2_device on the error path + - auxdisplay: panel: Fix an API misuse in panel.c + - platform/x86: lenovo-yoga-tab2-pro-1380-fastcharger: Make symbol static + - platform/x86: dell-uart-backlight: Make dell_uart_bl_serdev_driver static + - platform/x86: dell-ddv: Fix temperature calculation + - ASoC: cs35l41: check the return value from spi_setup() + - ASoC: amd: acp: Fix for enabling DMIC on acp platforms via _DSD entry + - HID: remove superfluous (and wrong) Makefile entry for + CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER + - ASoC: simple-card-utils: Don't use __free(device_node) at + graph_util_parse_dai() + - dt-bindings: vendor-prefixes: add GOcontroll + - ALSA: hda/realtek: Always honor no_shutup_pins + - ASoC: tegra: Use non-atomic timeout for ADX status register + - ASoC: ti: j721e-evm: Fix clock configuration for ti,j7200-cpb-audio + compatible + - ALSA: usb-audio: separate DJM-A9 cap lvl options + - ALSA: timer: Don't take register_mutex with copy_from/to_user() + - ALSA: hda/realtek: Fix built-in mic assignment on ASUS VivoBook X515UA + - wifi: rtw89: Correct immediate cfg_len calculation for scan_offload_be + - wifi: ath12k: fix skb_ext_desc leak in ath12k_dp_tx() error path + - wifi: ath12k: encode max Tx power in scan channel list command + - wifi: ath12k: Fix pdev lookup in WBM error processing + - wifi: ath9k: do not submit zero bytes to the entropy pool + - wifi: ath11k: fix wrong overriding for VHT Beamformee STS Capability + - arm64: dts: mediatek: mt8173-elm: Drop pmic's #address-cells and #size-cells + - arm64: dts: mediatek: mt8173: Fix some node names + - wifi: ath11k: update channel list in reg notifier instead reg worker + - ARM: dts: omap4-panda-a4: Add missing model and compatible properties + - f2fs: quota: fix to avoid warning in dquot_writeback_dquots() + - dlm: prevent NPD when writing a positive value to event_done + - wifi: ath11k: fix RCU stall while reaping monitor destination ring + - wifi: ath11k: add srng->lock for ath11k_hal_srng_* in monitor mode + - wifi: ath12k: Fix locking in "QMI firmware ready" error paths + - f2fs: fix to avoid panic once fallocation fails for pinfile + - scsi: mpt3sas: Reduce log level of ignore_delay_remove message to KERN_INFO + - md: ensure resync is prioritized over recovery + - md/raid1: fix memory leak in raid1_run() if no active rdev + - coredump: Fixes core_pipe_limit sysctl proc_handler + - io_uring/io-wq: eliminate redundant io_work_get_acct() calls + - io_uring/io-wq: cache work->flags in variable + - io_uring/io-wq: do not use bogus hash value + - io_uring: check for iowq alloc_workqueue failure + - io_uring/net: improve recv bundles + - firmware: arm_ffa: Refactor addition of partition information into XArray + - firmware: arm_ffa: Unregister the FF-A devices when cleaning up the + partitions + - arm64: dts: mediatek: mt6359: fix dtbs_check error for audio-codec + - scsi: mpi3mr: Fix locking in an error path + - scsi: mpt3sas: Fix a locking bug in an error path + - can: rockchip_canfd: rkcanfd_chip_fifo_setup(): remove duplicated setup of + RX FIFO + - jfs: reject on-disk inodes of an unsupported type + - jfs: add check read-only before txBeginAnon() call + - jfs: add check read-only before truncation in jfs_truncate_nolock() + - wifi: ath12k: Add missing htt_metadata flag in ath12k_dp_tx() + - wifi: rtw89: rtw8852b{t}: fix TSSI debug timestamps + - xfrm: delay initialization of offload path till its actually requested + - iommu/io-pgtable-dart: Only set subpage protection disable for DART 1 + - firmware: arm_ffa: Explicitly cast return value from FFA_VERSION before + comparison + - firmware: arm_ffa: Explicitly cast return value from NOTIFICATION_INFO_GET + - arm64: dts: renesas: r8a774c0: Re-add voltages to OPP table + - arm64: dts: renesas: r8a77990: Re-add voltages to OPP table + - firmware: arm_ffa: Skip the first/partition ID when parsing vCPU list + - arm64: dts: ti: k3-j722s-evm: Fix USB2.0_MUX_SEL to select Type-C + - wifi: ath12k: use link specific bss_conf as well in + ath12k_mac_vif_cache_flush() + - arm64: dts: imx8mp-skov: correct PMIC board limits + - arm64: dts: imx8mp-skov: operate CPU at 850 mV by default + - arm64: dts: mediatek: mt8390-genio-700-evk: Move common parts to dtsi + - arm64: dts: mediatek: mt8390-genio-common: Fix duplicated regulator name + - wifi: ath11k: Clear affinity hint before calling ath11k_pcic_free_irq() in + error path + - wifi: ath12k: Clear affinity hint before calling ath12k_pci_free_irq() in + error path + - f2fs: fix to set .discard_granularity correctly + - f2fs: add check for deleted inode + - arm64: dts: ti: k3-am62-verdin-dahlia: add Microphone Jack to sound card + - f2fs: fix potential deadloop in prepare_compress_overwrite() + - f2fs: fix to call f2fs_recover_quota_end() correctly + - md: fix mddev uaf while iterating all_mddevs list + - md/raid1,raid10: don't ignore IO flags + - md/md-bitmap: fix wrong bitmap_limit for clustermd when write sb + - tracing: Fix DECLARE_TRACE_CONDITION + - tools/rv: Keep user LDFLAGS in build + - arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx + - arm64: dts: ti: k3-am62p: fix pinctrl settings + - arm64: dts: ti: k3-j722s: fix pinctrl settings + - wifi: rtw89: fw: correct debug message format in + rtw89_build_txpwr_trk_tbl_from_elm() + - wifi: rtw89: pci: correct ISR RDU bit for 8922AE + - blk-throttle: fix lower bps rate by throtl_trim_slice() + - soc: mediatek: mtk-mmsys: Fix MT8188 VDO1 DPI1 output selection + - soc: mediatek: mt8167-mmsys: Fix missing regval in all entries + - soc: mediatek: mt8365-mmsys: Fix routing table masks and values + - md/raid10: wait barrier before returning discard request with REQ_NOWAIT + - block: ensure correct integrity capability propagation in stacked devices + - block: Correctly initialize BLK_INTEGRITY_NOGENERATE and + BLK_INTEGRITY_NOVERIFY + - badblocks: Fix error shitf ops + - badblocks: factor out a helper try_adjacent_combine + - badblocks: attempt to merge adjacent badblocks during ack_all_badblocks + - badblocks: return error directly when setting badblocks exceeds 512 + - badblocks: return error if any badblock set fails + - badblocks: fix the using of MAX_BADBLOCKS + - badblocks: fix merge issue when new badblocks align with pre+1 + - badblocks: fix missing bad blocks on retry in _badblocks_check() + - badblocks: return boolean from badblocks_set() and badblocks_clear() + - badblocks: use sector_t instead of int to avoid truncation of badblocks + length + - firmware: arm_scmi: use ioread64() instead of ioread64_hi_lo() + - net: airoha: Fix lan4 support in airoha_qdma_get_gdm_port() + - iommu/amd: Fix header file + - iommu/vt-d: Fix system hang on reboot -f + - memory: mtk-smi: Add ostd setting for mt8192 + - gfs2: minor evict fix + - gfs2: skip if we cannot defer delete + - ARM: dts: imx6ul-tqma6ul1: Change include order to disable fec2 node + - arm64: dts: imx8mp: add AUDIO_AXI_CLK_ROOT to AUDIOMIX block + - arm64: dts: imx8mp: change AUDIO_AXI_CLK_ROOT freq. to 800MHz + - f2fs: fix to avoid accessing uninitialized curseg + - iommu: Handle race with default domain setup + - wifi: mac80211: remove SSID from ML reconf + - f2fs: fix to avoid running out of free segments + - block: fix adding folio to bio + - ext4: fix potential null dereference in ext4 kunit test + - ext4: convert EXT4_FLAGS_* defines to enum + - ext4: add EXT4_FLAGS_EMERGENCY_RO bit + - ext4: correct behavior under errors=remount-ro mode + - ext4: show 'emergency_ro' when EXT4_FLAGS_EMERGENCY_RO is set + - arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory + - arm64: dts: rockchip: Remove bluetooth node from rock-3a + - bus: qcom-ssc-block-bus: Remove some duplicated iounmap() calls + - bus: qcom-ssc-block-bus: Fix the error handling path of + qcom_ssc_block_bus_probe() + - arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max + - arm64: dts: rockchip: Fix PWM pinctrl names + - arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 + - erofs: allow 16-byte volume name again + - ext4: add missing brelse() for bh2 in ext4_dx_add_entry() + - ext4: verify fast symlink length + - f2fs: fix missing discard for active segments + - scsi: hisi_sas: Fixed failure to issue vendor specific commands + - scsi: target: tcm_loop: Fix wrong abort tag + - ext4: introduce ITAIL helper + - ext4: fix out-of-bound read in ext4_xattr_inode_dec_ref_all() + - ext4: goto right label 'out_mmap_sem' in ext4_setattr() + - jbd2: fix off-by-one while erasing journal + - ata: libata: Fix NCQ Non-Data log not supported print + - wifi: nl80211: store chandef on the correct link when starting CAC + - wifi: mac80211: check basic rates validity in sta_link_apply_parameters + - wifi: cfg80211: init wiphy_work before allocating rfkill fails + - wifi: mwifiex: Fix premature release of RF calibration data. + - wifi: mwifiex: Fix RF calibration data download from file + - ice: health.c: fix compilation on gcc 7.5 + - ice: ensure periodic output start time is in the future + - ice: fix reservation of resources for RDMA when disabled + - virtchnl: make proto and filter action count unsigned + - ice: stop truncating queue ids when checking + - ice: validate queue quanta parameters to prevent OOB access + - ice: fix input validation for virtchnl BW + - ice: fix using untrusted value of pkt_len in ice_vc_fdir_parse_raw() + - idpf: check error for register_netdev() on init + - btrfs: get used bytes while holding lock at btrfs_reclaim_bgs_work() + - btrfs: fix reclaimed bytes accounting after automatic block group reclaim + - btrfs: fix block group refcount race in btrfs_create_pending_block_groups() + - btrfs: don't clobber ret in btrfs_validate_super() + - wifi: mt76: mt7915: fix possible integer overflows in + mt7915_muru_stats_show() + - igb: reject invalid external timestamp requests for 82580-based HW + - renesas: reject PTP_STRICT_FLAGS as unsupported + - net: lan743x: reject unsupported external timestamp requests + - broadcom: fix supported flag check in periodic output function + - ptp: ocp: reject unsupported periodic output flags + - nvmet: pci-epf: Always configure BAR0 as 64-bit + - jbd2: add a missing data flush during file and fs synchronization + - ext4: define ext4_journal_destroy wrapper + - ext4: avoid journaling sb update on error if journal is destroying + - eth: bnxt: fix out-of-range access of vnic_info array + - net: Remove RTNL dance for SIOCBRADDIF and SIOCBRDELIF. + - netfilter: nfnetlink_queue: Initialize ctx to avoid memory allocation error + - netfilter: nf_tables: Only use nf_skip_indirect_calls() when + MITIGATION_RETPOLINE + - ax25: Remove broken autobind + - net/mlx5e: Fix ethtool -N flow-type ip4 to RSS context + - bnxt_en: Mask the bd_cnt field in the TX BD properly + - bnxt_en: Linearize TX SKB if the fragments exceed the max + - net: dsa: mv88e6xxx: fix atu_move_port_mask for 6341 family + - net: dsa: mv88e6xxx: enable PVT for 6321 switch + - net: dsa: mv88e6xxx: enable .port_set_policy() for 6320 family + - net: dsa: mv88e6xxx: fix VTU methods for 6320 family + - net: dsa: mv88e6xxx: enable STU methods for 6320 family + - mlxsw: spectrum_acl_bloom_filter: Workaround for some LLVM versions + - net: dsa: sja1105: fix displaced ethtool statistics counters + - net: dsa: sja1105: reject other RX filters than + HWTSTAMP_FILTER_PTP_V2_L2_EVENT + - net: dsa: sja1105: fix kasan out-of-bounds warning in + sja1105_table_delete_entry() + - net/mlx5: LAG, reload representors on LAG creation failure + - net/mlx5: Start health poll after enable hca + - vmxnet3: unregister xdp rxq info in the reset path + - bonding: check xdp prog when set bond mode + - ibmvnic: Use kernel helpers for hex dumps + - net: fix NULL pointer dereference in l3mdev_l3_rcv + - virtio_net: Fix endian with virtio_net_ctrl_rss + - Bluetooth: Add quirk for broken READ_VOICE_SETTING + - Bluetooth: Add quirk for broken READ_PAGE_SCAN_TYPE + - Bluetooth: btusb: Fix regression in the initialization of fake Bluetooth + controllers + - Bluetooth: hci_core: Enable buffer flow control for SCO/eSCO + - Bluetooth: HCI: Add definition of hci_rp_remote_name_req_cancel + - rwonce: handle KCSAN like KASAN in read_word_at_a_time() + - net: dsa: microchip: fix DCB apptrust configuration on KSZ88x3 + - Bluetooth: btnxpuart: Fix kernel panic during FW release + - Bluetooth: hci_event: Fix handling of HCI_EV_LE_DIRECT_ADV_REPORT + - net: Fix the devmem sock opts and msgs for parisc + - net: libwx: fix Tx descriptor content for some tunnel packets + - net: libwx: fix Tx L4 checksum + - rwonce: fix crash by removing READ_ONCE() for unaligned read + - drm/bridge: ti-sn65dsi86: Fix multiple instances + - drm/ssd130x: Set SPI .id_table to prevent an SPI core warning + - accel/amdxdna: Return error when setting clock failed for npu1 + - drm/panthor: Fix a race between the reset and suspend path + - drm/ssd130x: fix ssd132x encoding + - drm/ssd130x: ensure ssd132x pitch is correct + - drm/dp_mst: Fix drm RAD print + - drm/bridge: it6505: fix HDCP V match check is not performed correctly + - drm/panthor: Fix race condition when gathering fdinfo group samples + - drm: xlnx: zynqmp: Fix max dma segment size + - drm: xlnx: zynqmp_dpsub: Add NULL check in zynqmp_audio_init + - drm: zynqmp_dp: Fix a deadlock in zynqmp_dp_ignore_hpd_set() + - drm/vkms: Fix use after free and double free on init error + - gpu: cdns-mhdp8546: fix call balance of mhdp->clk handling routines + - drm/amdgpu: refine smu send msg debug log format + - drm/amdgpu/umsch: remove vpe test from umsch + - drm/amdgpu/umsch: declare umsch firmware + - drm/amdgpu/umsch: fix ucode check + - drm/amdgpu/vcn5.0.1: use correct dpm helper + - PCI: Use downstream bridges for distributing resources + - PCI: Remove add_align overwrite unrelated to size0 + - PCI: Simplify size1 assignment logic + - PCI: Allow relaxed bridge window tail sizing for optional resources + - drm/mediatek: mtk_hdmi: Unregister audio platform device on failure + - drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member + - drm/amdgpu: Replace Mutex with Spinlock for RLCG register access to avoid + Priority Inversion in SRIOV + - PCI/ASPM: Fix link state exit during switch upstream function removal + - drm/panel: ilitek-ili9882t: fix GPIO name in error message + - PCI/ACS: Fix 'pci=config_acs=' parameter + - drm/amd/display: fix an indent issue in DML21 + - drm/msm/dpu: don't use active in atomic_check() + - drm/msm/dsi/phy: Program clock inverters in correct register + - drm/msm/dsi: Use existing per-interface slice count in DSC timing + - drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host + - drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs + - drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topology + - drm/msm/gem: Fix error code msm_parse_deps() + - drm/amdkfd: Fix Circular Locking Dependency in + 'svm_range_cpu_invalidate_pagetables' + - PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC + - PCI: cadence-ep: Fix the driver to send MSG TLP for INTx without data + payload + - PCI: brcmstb: Set generation limit before PCIe link up + - PCI: brcmstb: Use internal register to change link capability + - PCI: brcmstb: Fix error path after a call to regulator_bulk_get() + - PCI: brcmstb: Fix potential premature regulator disabling + - selftests/pcie_bwctrl: Add 'set_pcie_speed.sh' to TEST_PROGS + - PCI/portdrv: Only disable pciehp interrupts early when needed + - PCI: Avoid reset when disabled via sysfs + - drm/msm/dpu: move needs_cdm setting to dpu_encoder_get_topology() + - drm/msm/dpu: simplify dpu_encoder_get_topology() interface + - drm/msm/dpu: don't set crtc_state->mode_changed from atomic_check() + - drm/panthor: Update CS_STATUS_ defines to correct values + - drm/file: Add fdinfo helper for printing regions with prefix + - drm/panthor: Expose size of driver internal BO's over fdinfo + - drm/panthor: Replace sleep locks with spinlocks in fdinfo path + - drm/panthor: Avoid sleep locking in the internal BO size path + - drm/panthor: Clean up FW version information display + - drm/amd/display: fix type mismatch in CalculateDynamicMetadataParameters() + - drm/msm/a6xx: Fix a6xx indexed-regs in devcoreduump + - powerpc/perf: Fix ref-counting on the PMU 'vpa_pmu' + - misc: pci_endpoint_test: Fix pci_endpoint_test_bars_read_bar() error + handling + - misc: pci_endpoint_test: Handle BAR sizes larger than INT_MAX + - PCI: endpoint: pci-epf-test: Handle endianness properly + - crypto: powerpc: Mark ghashp8-ppc.o as an OBJECT_FILES_NON_STANDARD + - powerpc/kexec: fix physical address calculation in clear_utlb_entry() + - PCI: Remove stray put_device() in pci_register_host_bridge() + - PCI: xilinx-cpm: Fix IRQ domain leak in error path of probe + - drm/mediatek: Fix config_updating flag never false when no mbox channel + - drm/mediatek: dp: drm_err => dev_err in HPD path to avoid NULL ptr + - drm/mediatek: dsi: fix error codes in mtk_dsi_host_transfer() + - drm/amd/display: avoid NPD when ASIC does not support DMUB + - PCI: dwc: ep: Return -ENOMEM for allocation failures + - PCI: histb: Fix an error handling path in histb_pcie_probe() + - PCI: Fix BAR resizing when VF BARs are assigned + - drm/amdgpu/mes: optimize compute loop handling + - drm/amdgpu/mes: enable compute pipes across all MEC + - PCI: pciehp: Don't enable HPIE when resuming in poll mode + - PCI/bwctrl: Fix pcie_bwctrl_select_speed() return type + - io_uring/net: only import send_zc buffer once + - PCI: Fix NULL dereference in SR-IOV VF creation error path + - io_uring: use lockless_cq flag in io_req_complete_post() + - io_uring: fix retry handling off iowq + - fbdev: au1100fb: Move a variable assignment behind a null pointer check + - dummycon: fix default rows/cols + - mdacon: rework dependency list + - fbdev: sm501fb: Add some geometry checks. + - crypto: iaa - Test the correct request flag + - crypto: qat - set parity error mask for qat_420xx + - crypto: tegra - Use separate buffer for setkey + - crypto: tegra - Do not use fixed size buffers + - crypto: tegra - check return value for hash do_one_req + - crypto: tegra - Transfer HASH init function to crypto engine + - crypto: tegra - Fix HASH intermediate result handling + - crypto: bpf - Add MODULE_DESCRIPTION for skcipher + - crypto: tegra - Use HMAC fallback when keyslots are full + - clk: amlogic: gxbb: drop incorrect flag on 32k clock + - crypto: hisilicon/sec2 - fix for aead authsize alignment + - crypto: hisilicon/sec2 - fix for sec spec check + - RDMA/mlx5: Fix page_size variable overflow + - remoteproc: core: Clear table_sz when rproc_shutdown + - of: property: Increase NR_FWNODE_REFERENCE_ARGS + - pinctrl: renesas: rzg2l: Suppress binding attributes + - remoteproc: qcom_q6v5_pas: Make single-PD handling more robust + - libbpf: Fix hypothetical STT_SECTION extern NULL deref case + - drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock + - selftests/bpf: Fix string read in strncmp benchmark + - x86/mm/pat: Fix VM_PAT handling when fork() fails in copy_page_range() + - clk: renesas: r8a08g045: Check the source of the CPU PLL settings + - remoteproc: qcom: pas: add minidump_id to SC7280 WPSS + - clk: samsung: Fix UBSAN panic in samsung_clk_init() + - pinctrl: nuvoton: npcm8xx: Fix error handling in npcm8xx_gpio_fw() + - crypto: tegra - Fix CMAC intermediate result handling + - clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock + - selftests/bpf: Fix runqslower cross-endian build + - s390: Remove ioremap_wt() and pgprot_writethrough() + - RDMA/mana_ib: Ensure variable err is initialized + - crypto: tegra - Set IV to NULL explicitly for AES ECB + - remoteproc: qcom_q6v5_pas: Use resource with CX PD for MSM8226 + - crypto: tegra - finalize crypto req on error + - crypto: tegra - Reserve keyslots to allocate dynamically + - bpf: Use preempt_count() directly in bpf_send_signal_common() + - lib: 842: Improve error handling in sw842_compress() + - pinctrl: renesas: rza2: Fix missing of_node_put() call + - pinctrl: renesas: rzg2l: Fix missing of_node_put() call + - RDMA/mlx5: Fix MR cache initialization error flow + - selftests/bpf: Fix freplace_link segfault in tailcalls prog test + - clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent + - RDMA/core: Don't expose hw_counters outside of init net namespace + - RDMA/mlx5: Fix calculation of total invalidated pages + - RDMA/erdma: Prevent use-after-free in erdma_accept_newconn() + - remoteproc: qcom_q6v5_mss: Handle platforms with one power domain + - power: supply: bq27xxx_battery: do not update cached flags prematurely + - leds: st1202: Check for error code from devm_mutex_init() call + - crypto: api - Fix larval relookup type and mask + - IB/mad: Check available slots before posting receive WRs + - pinctrl: tegra: Set SFIO mode to Mux Register + - clk: amlogic: g12b: fix cluster A parent data + - clk: amlogic: gxbb: drop non existing 32k clock parent + - selftests/bpf: Select NUMA_NO_NODE to create map + - rust: fix signature of rust_fmt_argument + - crypto: tegra - Fix format specifier in tegra_sha_prep_cmd() + - libbpf: Add namespace for errstr making it libbpf_errstr + - clk: mmp: Fix NULL vs IS_ERR() check + - pinctrl: npcm8xx: Fix incorrect struct npcm8xx_pincfg assignment + - samples/bpf: Fix broken vmlinux path for VMLINUX_BTF + - crypto: qat - remove access to parity register for QAT GEN4 + - clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents + - clk: amlogic: g12a: fix mmc A peripheral clock + - pinctrl: bcm2835: don't -EINVAL on alternate funcs from get_direction() + - x86/entry: Fix ORC unwinder for PUSH_REGS with save_ret=1 + - power: supply: max77693: Fix wrong conversion of charge input threshold + value + - crypto: api - Call crypto_alg_put in crypto_unregister_alg + - clk: stm32f4: fix an uninitialized variable + - crypto: nx - Fix uninitialised hv_nxc on error + - clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable() + - bpf: Fix array bounds error with may_goto + - RDMA/mlx5: Fix mlx5_poll_one() cur_qp update flow + - pinctrl: renesas: rzv2m: Fix missing of_node_put() call + - clk: qcom: ipq5424: fix software and hardware flow control error of UART + - mfd: sm501: Switch to BIT() to mitigate integer overflows + - leds: Fix LED_OFF brightness race + - x86/dumpstack: Fix inaccurate unwinding from exception stacks due to + misplaced assignment + - RDMA/core: Fix use-after-free when rename device name + - crypto: hisilicon/sec2 - fix for aead auth key length + - pinctrl: intel: Fix wrong bypass assignment in intel_pinctrl_probe_pwm() + - clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock + - libbpf: Fix accessing BTF.ext core_relo header + - perf stat: Fix find_stat for mixed legacy/non-legacy events + - perf: Always feature test reallocarray + - w1: fix NULL pointer dereference in probe + - staging: gpib: Add missing interface entry point + - staging: gpib: Fix pr_err format warning + - usb: typec: thunderbolt: Fix loops that iterate TYPEC_PLUG_SOP_P and + TYPEC_PLUG_SOP_PP + - usb: typec: thunderbolt: Remove IS_ERR check for plug + - iio: dac: adi-axi-dac: modify stream enable + - perf test: Fix Hwmon PMU test endianess issue + - perf stat: Don't merge counters purely on name + - fs/ntfs3: Factor out ntfs_{create/remove}_procdir() + - fs/ntfs3: Factor out ntfs_{create/remove}_proc_root() + - fs/ntfs3: Fix 'proc_info_root' leak when init ntfs failed + - fs/ntfs3: Update inode->i_mapping->a_ops on compression state + - iio: light: veml6030: extend regmap to support regfields + - iio: gts-helper: export iio_gts_get_total_gain() + - iio: light: veml6030: fix scale to conform to ABI + - iio: adc: ad7124: Micro-optimize channel disabling + - iio: adc: ad7124: Really disable all channels at probe time + - phy: phy-rockchip-samsung-hdptx: Don't use dt aliases to determine phy-id + - perf tools: Add skip check in tool_pmu__event_to_str() + - isofs: fix KMSAN uninit-value bug in do_isofs_readdir() + - perf tests: Fix Tool PMU test segfault + - soundwire: slave: fix an OF node reference leak in soundwire slave device + - staging: gpib: Fix cb7210 pcmcia Oops + - perf report: Switch data file correctly in TUI + - perf report: Fix input reload/switch with symbol sort key + - greybus: gb-beagleplay: Add error handling for gb_greybus_init + - coresight: catu: Fix number of pages while using 64k pages + - vhost-scsi: Fix handling of multiple calls to vhost_scsi_set_endpoint + - coresight-etm4x: add isb() before reading the TRCSTATR + - perf pmus: Restructure pmu_read_sysfs to scan fewer PMUs + - perf pmu: Dynamically allocate tool PMU + - perf pmu: Don't double count common sysfs and json events + - tools/x86: Fix linux/unaligned.h include path in lib/insn.c + - perf build: Fix in-tree build due to symbolic link + - ucsi_ccg: Don't show failed to get FW build information error + - iio: accel: mma8452: Ensure error return on failure to matching oversampling + ratio + - iio: accel: msa311: Fix failure to release runtime pm if direct mode claim + fails. + - iio: backend: make sure to NULL terminate stack buffer + - iio: core: Rework claim and release of direct mode to work with sparse. + - iio: adc: ad7173: Grab direct mode for calibration + - iio: adc: ad7192: Grab direct mode for calibration + - perf arm-spe: Fix load-store operation checking + - perf bench: Fix perf bench syscall loop count + - perf machine: Fixup kernel maps ends after adding extra maps + - usb: xhci: correct debug message page size calculation + - fs/ntfs3: Fix a couple integer overflows on 32bit systems + - fs/ntfs3: Prevent integer overflow in hdr_first_de() + - perf test: Add timeout to datasym workload + - perf tests: Fix data symbol test with LTO builds + - NFSD: Fix callback decoder status codes + - soundwire: take in count the bandwidth of a prepared stream + - dmaengine: fsl-edma: cleanup chan after dma_async_device_unregister + - dmaengine: fsl-edma: free irq correctly in remove path + - dmaengine: ae4dma: Use the MSI count and its corresponding IRQ number + - dmaengine: ptdma: Utilize the AE4DMA engine's multi-queue functionality + - iio: adc: ad_sigma_delta: Disable channel after calibration + - iio: adc: ad4130: Fix comparison of channel setups + - iio: adc: ad7124: Fix comparison of channel configs + - iio: adc: ad7173: Fix comparison of channel configs + - iio: adc: ad7768-1: set MOSI idle state to prevent accidental reset + - iio: light: Add check for array bounds in veml6075_read_int_time_ms + - perf debug: Avoid stack overflow in recursive error message + - perf evlist: Add success path to evlist__create_syswide_maps + - perf evsel: tp_format accessing improvements + - perf x86/topdown: Fix topdown leader sampling test error on hybrid + - perf units: Fix insufficient array space + - perf test stat_all_pmu.sh: Correctly check 'perf stat' result + - kernel/events/uprobes: handle device-exclusive entries correctly in + __replace_page() + - kexec: initialize ELF lowest address to ULONG_MAX + - ocfs2: validate l_tree_depth to avoid out-of-bounds access + - reboot: replace __hw_protection_shutdown bool action parameter with an enum + - reboot: reboot, not shutdown, on hw_protection_reboot timeout + - arch/powerpc: drop GENERIC_PTDUMP from mpc885_ads_defconfig + - writeback: let trace_balance_dirty_pages() take struct dtc as parameter + - writeback: fix calculations in trace_balance_dirty_pages() for cgwb + - scripts/gdb/linux/symbols.py: address changes to module_sect_attrs + - NFSv4: Don't trigger uneccessary scans for return-on-close delegations + - NFSv4: Avoid unnecessary scans of filesystems for returning delegations + - NFSv4: Avoid unnecessary scans of filesystems for expired delegations + - NFSv4: Avoid unnecessary scans of filesystems for delayed delegations + - NFS: fix open_owner_id_maxsz and related fields. + - fuse: fix dax truncate/punch_hole fault path + - selftests/mm/cow: fix the incorrect error handling + - um: Pass the correct Rust target and options with gcc + - um: remove copy_from_kernel_nofault_allowed + - um: hostfs: avoid issues on inode number reuse by host + - i3c: master: svc: Fix missing the IBI rules + - perf python: Fixup description of sample.id event member + - perf python: Decrement the refcount of just created event on failure + - perf python: Don't keep a raw_data pointer to consumed ring buffer space + - perf python: Check if there is space to copy all the event + - perf dso: fix dso__is_kallsyms() check + - perf: intel-tpebs: Fix incorrect usage of zfree() + - perf pmu: Handle memory failure in tool_pmu__new() + - staging: rtl8723bs: select CONFIG_CRYPTO_LIB_AES + - staging: vchiq_arm: Register debugfs after cdev + - staging: vchiq_arm: Fix possible NPR of keep-alive thread + - staging: vchiq_arm: Stop kthreads if vchiq cdev register fails + - tty: n_tty: use uint for space returned by tty_write_room() + - perf vendor events arm64 AmpereOneX: Fix frontend_bound calculation + - fs/procfs: fix the comment above proc_pid_wchan() + - perf tools: Fix is_compat_mode build break in ppc64 + - perf tools: annotate asm_pure_loop.S + - perf bpf-filter: Fix a parsing error with comma + - objtool: Handle various symbol types of rodata + - objtool: Handle different entry size of rodata + - objtool: Handle PC relative relocation type + - objtool: Fix detection of consecutive jump tables on Clang 20 + - thermal: core: Remove duplicate struct declaration + - objtool, spi: amd: Fix out-of-bounds stack access in amd_set_spi_freq() + - objtool, nvmet: Fix out-of-bounds stack access in nvmet_ctrl_state_show() + - objtool, media: dib8000: Prevent divide-by-zero in dib8000_set_dds() + - NFS: Shut down the nfs_client only after all the superblocks + - smb: client: Fix netns refcount imbalance causing leaks and use-after-free + - exfat: fix the infinite loop in exfat_find_last_cluster() + - exfat: fix missing shutdown check + - rtnetlink: Allocate vfinfo size for VF GUIDs when supported + - rndis_host: Flag RNDIS modems as WWAN devices + - ksmbd: use aead_request_free to match aead_request_alloc + - ksmbd: fix multichannel connection failure + - ksmbd: fix r_count dec/increment mismatch + - net/mlx5e: SHAMPO, Make reserved size independent of page size + - ring-buffer: Fix bytes_dropped calculation issue + - objtool: Fix segfault in ignore_unreachable_insn() + - LoongArch: Fix help text of CMDLINE_EXTEND in Kconfig + - LoongArch: Fix device node refcount leak in fdt_cpu_clk_init() + - LoongArch: Rework the arch_kgdb_breakpoint() implementation + - ACPI: processor: idle: Return an error if both P_LVL{2,3} idle states are + invalid + - net: phy: broadcom: Correct BCM5221 PHY model detection + - octeontx2-af: Fix mbox INTR handler when num VFs > 64 + - octeontx2-af: Free NIX_AF_INT_VEC_GEN irq + - objtool: Fix verbose disassembly if CROSS_COMPILE isn't set + - sched/smt: Always inline sched_smt_active() + - context_tracking: Always inline ct_{nmi,irq}_{enter,exit}() + - rcu-tasks: Always inline rcu_irq_work_resched() + - objtool/loongarch: Add unwind hints in prepare_frametrace() + - nfs: Add missing release on error in nfs_lock_and_join_requests() + - rtc: renesas-rtca3: Disable interrupts only if the RTC is enabled + - spufs: fix a leak on spufs_new_file() failure + - spufs: fix gang directory lifetimes + - spufs: fix a leak in spufs_create_context() + - fs/9p: fix NULL pointer dereference on mkdir + - riscv: ftrace: Add parentheses in macro definitions of make_call_t0 and + make_call_ra + - riscv: Fix the __riscv_copy_vec_words_unaligned implementation + - riscv: Fix missing __free_pages() in check_vector_unaligned_access() + - riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on + HAVE_DYNAMIC_FTRACE_WITH_ARGS + - ntb_hw_switchtec: Fix shift-out-of-bounds in switchtec_ntb_mw_set_trans + - ntb: intel: Fix using link status DB's + - riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of + ftrace_return_to_handler + - riscv: Annotate unaligned access init functions + - riscv: Fix riscv_online_cpu_vec + - riscv: Fix check_unaligned_access_all_cpus + - riscv: Change check_unaligned_access_speed_all_cpus to void + - riscv: Fix set up of cpu hotplug callbacks + - riscv: Fix set up of vector cpu hotplug callback + - firmware: cs_dsp: Ensure cs_dsp_load[_coeff]() returns 0 on success + - ALSA: hda/realtek: Fix built-in mic breakage on ASUS VivoBook X515JA + - RISC-V: errata: Use medany for relocatable builds + - x86/uaccess: Improve performance by aligning writes to 8 bytes in + copy_user_generic(), on non-FSRM/ERMS CPUs + - ublk: make sure ubq->canceling is set when queue is frozen + - s390/entry: Fix setting _CIF_MCCK_GUEST with lowcore relocation + - ASoC: codecs: rt5665: Fix some error handling paths in rt5665_probe() + - spi: cadence: Fix out-of-bounds array access in cdns_mrvl_xspi_setup_clock() + - riscv: Fix hugetlb retrieval of number of ptes in case of !present pte + - riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator + - riscv/purgatory: 4B align purgatory_start + - nvme/ioctl: don't warn on vectorized uring_cmd with fixed buffer + - nvme-pci: skip nvme_write_sq_db on empty rqlist + - ASoC: imx-card: Add NULL check in imx_card_probe() + - spi: bcm2835: Do not call gpiod_put() on invalid descriptor + - ALSA: hda/realtek: Fix built-in mic on another ASUS VivoBook model + - spi: bcm2835: Restore native CS probing when pinctrl-bcm2835 is absent + - xsk: Add launch time hardware offload support to XDP Tx metadata + - igc: Refactor empty frame insertion for launch time support + - igc: Add launch time support to XDP ZC + - igc: Fix TX drops in XDP ZC + - e1000e: change k1 configuration on MTP and later platforms + - ixgbe: fix media type detection for E610 device + - idpf: fix adapter NULL pointer dereference on reboot + - netfilter: nft_set_hash: GC reaps elements with conncount for dynamic sets + only + - netfilter: nf_tables: don't unregister hook when table is dormant + - netlabel: Fix NULL pointer exception caused by CALIPSO on IPv4 sockets + - net_sched: skbprio: Remove overly strict queue assertions + - sctp: add mutual exclusion in proc_sctp_do_udp_port() + - net: airoha: Fix qid report in airoha_tc_get_htb_get_leaf_queue() + - net: airoha: Fix ETS priomap validation + - net: mvpp2: Prevent parser TCAM memory corruption + - rtnetlink: Use register_pernet_subsys() in rtnl_net_debug_init(). + - udp: Fix multiple wraparounds of sk->sk_rmem_alloc. + - udp: Fix memory accounting leak. + - vsock: avoid timeout during connect() if the socket is closing + - tunnels: Accept PACKET_HOST in skb_tunnel_check_pmtu(). + - xsk: Fix __xsk_generic_xmit() error code when cq is full + - net: decrease cached dst counters in dst_release + - netfilter: nft_tunnel: fix geneve_opt type confusion addition + - sfc: rip out MDIO support + - sfc: fix NULL dereferences in ef100_process_design_param() + - ipv6: fix omitted netlink attributes when using RTEXT_FILTER_SKIP_STATS + - net: dsa: mv88e6xxx: propperly shutdown PPU re-enable timer on destroy + - net: fix geneve_opt length integer overflow + - ipv6: Start path selection from the first nexthop + - ipv6: Do not consider link down nexthops in path selection + - arcnet: Add NULL check in com20020pci_probe() + - net: ibmveth: make veth_pool_store stop hanging + - netlink: specs: rt_route: pull the ifa- prefix out of the names + - tools/power turbostat: Allow Zero return value for some RAPL registers + - kbuild: deb-pkg: don't set KBUILD_BUILD_VERSION unconditionally + - drm/xe: Fix unmet direct dependencies warning + - drm/amdgpu/gfx11: fix num_mec + - drm/amdgpu/gfx12: fix num_mec + - perf/core: Fix child_total_time_enabled accounting bug at task exit + - tools/power turbostat: report CoreThr per measurement interval + - tools/power turbostat: Restore GFX sysfs fflush() call + - staging: gpib: ni_usb console messaging cleanup + - staging: gpib: Fix Oops after disconnect in ni_usb + - staging: gpib: agilent usb console messaging cleanup + - staging: gpib: Fix Oops after disconnect in agilent usb + - tty: serial: fsl_lpuart: Use u32 and u8 for register variables + - tty: serial: fsl_lpuart: use port struct directly to simply code + - tty: serial: fsl_lpuart: Fix unused variable 'sport' build warning + - tty: serial: lpuart: only disable CTS instead of overwriting the whole + UARTMODIR register + - usbnet:fix NPE during rx_complete + - rust: Fix enabling Rust and building with GCC for LoongArch + - LoongArch: Increase ARCH_DMA_MINALIGN up to 16 + - LoongArch: Increase MAX_IO_PICS up to 8 + - LoongArch: BPF: Fix off-by-one error in build_prologue() + - LoongArch: BPF: Don't override subprog's return value + - LoongArch: BPF: Use move_addr() for BPF_PSEUDO_FUNC + - x86/hyperv: Fix check of return value from snp_set_vmsa() + - KVM: x86: block KVM_CAP_SYNC_REGS if guest state is protected + - x86/microcode/AMD: Fix __apply_microcode_amd()'s return value + - x86/mce: use is_copy_from_user() to determine copy-from-user context + - x86/paravirt: Move halt paravirt calls under CONFIG_PARAVIRT + - x86/tdx: Fix arch_safe_halt() execution for TDX VMs + - ACPI: x86: Extend Lenovo Yoga Tab 3 quirk with skip GPIO event-handlers + - platform/x86: thinkpad_acpi: disable ACPI fan access for T495* and E560 + - platform/x86: ISST: Correct command storage data length + - ntb_perf: Delete duplicate dmaengine_unmap_put() call in perf_copy_chunk() + - perf/x86/intel: Apply static call for drain_pebs + - perf/x86/intel: Avoid disable PMU if !cpuc->enabled in sample read + - uprobes/x86: Harden uretprobe syscall trampoline check + - bcachefs: bch2_ioctl_subvolume_destroy() fixes + - x86/Kconfig: Add cmpxchg8b support back to Geode CPUs + - x86/tsc: Always save/restore TSC sched_clock() on suspend/resume + - x86/mm: Fix flush_tlb_range() when used for zapping normal PMDs + - ACPI: platform-profile: Fix CFI violation when accessing sysfs files + - wifi: mt76: mt7925: remove unused acpi function for clc + - acpi: nfit: fix narrowing conversion in acpi_nfit_ctl + - ACPI: resource: Skip IRQ override on ASUS Vivobook 14 X1404VAP + - ACPI: video: Handle fetching EDID as ACPI_TYPE_PACKAGE + - ARM: 9443/1: Require linker to support KEEP within OVERLAY for DCE + - [Config] updateconfigs for LD_CAN_USE_KEEP_IN_OVERLAY + - ARM: 9444/1: add KEEP() keyword to ARM_VECTORS + - media: omap3isp: Handle ARM dma_iommu_mapping + - Remove unnecessary firmware version check for gc v9_4_2 + - mmc: omap: Fix memory leak in mmc_omap_new_slot + - mmc: sdhci-pxav3: set NEED_RSP_BUSY capability + - mmc: sdhci-omap: Disable MMC_CAP_AGGRESSIVE_PM for eMMC/SD + - KVM: SVM: Don't change target vCPU state on AP Creation VMGEXIT error + - ksmbd: add bounds check for durable handle context + - ksmbd: add bounds check for create lease context + - ksmbd: fix use-after-free in ksmbd_sessions_deregister() + - ksmbd: fix session use-after-free in multichannel connection + - ksmbd: fix overflow in dacloffset bounds check + - ksmbd: validate zero num_subauth before sub_auth is accessed + - ksmbd: fix null pointer dereference in alloc_preauth_hash() + - exfat: fix random stack corruption after get_block + - exfat: fix potential wrong error return from get_block + - tracing: Fix use-after-free in print_graph_function_flags during tracer + switching + - tracing: Ensure module defining synth event cannot be unloaded while tracing + - tracing: Fix synth event printk format for str fields + - tracing/osnoise: Fix possible recursive locking for cpus_read_lock() + - tracing: Verify event formats that have "%*p.." + - mm/gup: reject FOLL_SPLIT_PMD with hugetlb VMAs + - arm64: Don't call NULL in do_compat_alignment_fixup() + - wifi: mt76: mt7921: fix kernel panic due to null pointer dereference + - ext4: don't over-report free space or inodes in statvfs + - ext4: fix OOB read when checking dotdot dir + - PCI/bwctrl: Fix NULL pointer dereference on bus number exhaustion + - jfs: fix slab-out-of-bounds read in ea_get() + - jfs: add index corruption check to DT_GETPAGE() + - mm: zswap: fix crypto_free_acomp() deadlock in zswap_cpu_comp_dead() + - exec: fix the racy usage of fs_struct->in_exec + - media: vimc: skip .s_stream() for stopped entities + - media: streamzap: fix race between device disconnection and urb callback + - nfsd: don't ignore the return code of svc_proc_register() + - nfsd: allow SC_STATUS_FREEABLE when searching via nfs4_lookup_stateid() + - nfsd: put dl_stid if fail to queue dl_recall + - NFSD: Add a Kconfig setting to enable delegated timestamps + - [Config] disable new feature NFSD_V4_DELEG_TIMESTAMPS + - nfsd: fix management of listener transports + - NFSD: nfsd_unlink() clobbers non-zero status returned from + fh_fill_pre_attrs() + - NFSD: Never return NFS4ERR_FILE_OPEN when removing a directory + - NFSD: Skip sending CB_RECALL_ANY when the backchannel isn't up + - perf pmu: Rename name matching for no suffix or wildcard variants + - include/{topology,cpuset}: Move dl_rebuild_rd_accounting to cpuset.h + - tracing: Do not use PERF enums when perf is not defined + - ASoC: mediatek: mt6359: Fix DT parse error due to wrong child node name + - Linux 6.14.2 + + * Plucky update: v6.14.1 upstream stable release (LP: #2106661) + - ALSA: usb-audio: Add quirk for Plantronics headsets to fix control names + - HID: hid-plantronics: Add mic mute mapping and generalize quirks + - atm: Fix NULL pointer dereference + - cgroup/rstat: Fix forceidle time in cpu.stat + - netfilter: socket: Lookup orig tuple for IPv6 SNAT + - ALSA: hda/realtek: Support mute LED on HP Laptop 15s-du3xxx + - ALSA: hda/realtek: Bass speaker fixup for ASUS UM5606KA + - counter: stm32-lptimer-cnt: fix error handling when enabling + - counter: microchip-tcb-capture: Fix undefined counter channel state on probe + - tty: serial: 8250: Add some more device IDs + - tty: serial: 8250: Add Brainboxes XC devices + - tty: serial: fsl_lpuart: disable transmitter before changing RS485 related + registers + - net: usb: qmi_wwan: add Telit Cinterion FN990B composition + - net: usb: qmi_wwan: add Telit Cinterion FE990B composition + - net: usb: usbnet: restore usb%d name exception for local mac addresses + - usb: xhci: Don't skip on Stopped - Length Invalid + - usb: xhci: Apply the link chain quirk on NEC isoc endpoints + - memstick: rtsx_usb_ms: Fix slab-use-after-free in rtsx_usb_ms_drv_remove + - perf tools: Fix up some comments and code to properly use the event_source + bus + - serial: stm32: do not deassert RS485 RTS GPIO prematurely + - serial: 8250_dma: terminate correct DMA in tx_dma_flush() + - Linux 6.14.1 + + * Null pointer dereference in gVNIC driver (LP: #2106281) + - gve: unlink old napi only if page pool exists + + * Miscellaneous upstream changes + - Revert "net: stmmac: dwmac-socfpga: Set RX watchdog interrupt as broken" + - Revert "drm: fsl-dcu: enable PIXCLK on LS1021A" + - Revert "m68k: mvme147: Reinstate early console" + - Revert "MAINTAINERS: appoint myself the XFS maintainer for 6.12 LTS" + + -- Mehmet Basaran Thu, 01 May 2025 10:39:35 +0300 + +linux (6.14.0-15.15) plucky; urgency=medium + + * plucky/linux: 6.14.0-15.15 -proposed tracker (LP: #2106239) + + * Enabling GENDWARFKSYMS breaks loading modules (LP: #2103771) + - [Packaging] Bump pahole build-dep + + * BMG: support additional PCI ID (LP: #2105768) + - SAUCE: drm/xe/bmg: Add one additional PCI ID + + * Missing bpftool binary on riscv64 (LP: #2106091) + - [Packaging] Build bpftool and linux-perf on riscv64 + - [Packaging] Allow binary-debs target without enabling + do_flavour_image_package + - [Packaging] Fix bpftool, linux-perf packaging in binary-perarch + + -- Paolo Pisati Sun, 06 Apr 2025 14:36:36 +0200 + +linux (6.14.0-14.14) plucky; urgency=medium + + * plucky/linux: 6.14.0-14.14 -proposed tracker (LP: #2106234) + + * Expose IFLA_VXLAN_FAN_MAP version via sysctl/proc (LP: #2106115) + - SAUCE: fan: expose IFLA_VXLAN_FAN_MAP version via sysctl/proc + + * not able to install a Power9 bare metal with Ubuntu 25.04 Plucky + (LP: #2104297) + - SAUCE: powerpc64/ftrace: fix module loading without patchable function + entries + + * bluetooth/detect-output failed due to the lack of USB device id in btusb.c + (LP: #2094969) + - SAUCE: Bluetooth: btusb: Add new VID/PID 0489/e14e for MT7925 + + * Don't suggests fdutils package anymore (LP: #2104355) + - [Packaging] Drop fdutils from linux-image Suggests + + * Miscellaneous Ubuntu changes + - [Packaging] Add bpftool, linux-perf to linux-image Suggests + + -- Paolo Pisati Fri, 04 Apr 2025 15:12:05 +0200 + +linux (6.14.0-13.13) plucky; urgency=medium + + * plucky/linux: 6.14.0-13.13 -proposed tracker (LP: #2104293) + + * Miscellaneous Ubuntu changes + - [Packaging] Fix invoking of control-create + + -- Paolo Pisati Wed, 26 Mar 2025 20:26:51 +0100 + +linux (6.14.0-12.12) plucky; urgency=medium + + * plucky/linux: 6.14.0-12.12 -proposed tracker (LP: #2104021) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.03.24) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.03.24) + + * Disconnected paths for mqueues show a TODO in the kernel logs (LP: #2102237) + - SAUCE: apparmor4.0.0 [58/53]: apparmor: add mediation of disconnected paths + in mqueues + + * Installation of AppArmor on a 6.14 kernel produces error message "Illegal + number: yes" (LP: #2102680) + - SAUCE: apparmor4.0.0 [56/53]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor4.0.0 [57/53]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT for + userns and io_uring sysctls + + * QRT AppArmorUnixDomainConnect test failures on Plucky 6.14 kernel + (LP: #2103460) + - SAUCE: apparmor4.0.0 [54/53]: AppArmor: Fix af_unix backwards compat + - SAUCE: apparmor4.0.0 [55/53]: apparmor: Fix inet mediation + + * Mouse cursor flashes using the 'xe' DRM driver (LP: #2103981) + - drm/xe/display: Re-use display vmas when possible + + * Snapdragon X Elite: Sync concept kernel changes (LP: #2100858) + - SAUCE: drm/msm/dp: Fix support of LTTPR handling + - SAUCE: drm/msm/dp: Introduce link training per-segment for LTTPRs + - SAUCE: wifi: ath12k: fix ring-buffer corruption + - SAUCE: wifi: ath11k: fix ring-buffer corruption + - SAUCE: arm64: dts: qcom: x1e80100-hp-omnibook-x14: Enable SMB2360 0 and 1 + - SAUCE: Revert "usb: typec: ps883x: fix missing accessibility check" + + * drm/xe: improve behavior under memory pressure (LP: #2102659) + - drm/xe: Reject BO eviction if BO is bound to current VM + + * Introduce configfs-based interface for gpio-aggregator (LP: #2103496) + - gpio: introduce utilities for synchronous fake device creation + - gpio: sim: convert to use dev-sync-probe utilities + - gpio: virtuser: convert to use dev-sync-probe utilities + - [Config] updateconfigs for DEV_SYNC_PROBE + - SAUCE: gpio: aggregator: reorder functions to prepare for configfs + introduction + - SAUCE: gpio: aggregator: add aggr_alloc()/aggr_free() + - SAUCE: gpio: aggregator: introduce basic configfs interface + - SAUCE: gpio: aggregator: rename 'name' to 'key' in aggr_parse() + - SAUCE: gpio: aggregator: expose aggregator created via legacy sysfs to + configfs + - SAUCE: gpio: aggregator: cancel deferred probe for devices created via + configfs + - SAUCE: Documentation: gpio: document configfs interface for gpio-aggregator + - SAUCE: selftests: gpio: add test cases for gpio-aggregator + + * python perf module missing in plucky's kernel (LP: #2103653) + - [Packaging] linux-perf: Fix python perf library location + + * Miscellaneous Ubuntu changes + - [packaging] mv debian.master/copyright debian + - [Config] Disable CONFIG_MODULE_COMPRESS_ALL + - Revert "SAUCE: Support but do not require compressed modules" + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Config] Revert back to GENKSYMS on amd64/arm64 too, drop + rust support" + + -- Paolo Pisati Wed, 26 Mar 2025 10:50:08 +0100 + +linux (6.14.0-11.11) plucky; urgency=medium + + * plucky/linux: 6.14.0-11.11 -proposed tracker (LP: #2103404) + + * Snapdragon X Elite: Sync concept kernel changes (LP: #2100858) + - firmware: qcom: uefisecapp: fix efivars registration race + - soc: qcom: pdr: Fix the potential deadlock + - clk: qcom: gcc-x1e80100: Unregister GCC_GPU_CFG_AHB_CLK/GCC_DISP_XO_CLK + - arm64: dts: qcom: x1e80100: Set CPU interconnect paths as ACTIVE_ONLY + - dt-bindings: usb: Add Parade PS8830 Type-C retimer bindings + - usb: typec: Add support for Parade PS8830 Type-C Retimer + - usb: typec: ps883x: fix probe error handling + - usb: typec: ps883x: fix registration race + - usb: typec: ps883x: fix missing accessibility check + - usb: typec: ps883x: fix configuration error handling + - drm/dp: Add helper to set LTTPRs in transparent mode + - drm/msm/dp: Add support for LTTPR handling + - arm64: dts: qcom: x1e80100: Add the watchdog device + - arm64: dts: qcom: x1e80100: Mark usb_2 as dma-coherent + - arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets + - arm64: dts: qcom: Commonize X1 CRD DTSI + - arm64: dts: qcom: Add X1P42100 SoC and CRD + - arm64: dts: qcom: x1e80100: Fix video thermal zone + - arm64: dts: qcom: x1e80100: Apply consistent critical thermal shutdown + - arm64: dts: qcom: x1e80100: Add GPU cooling + - arm64: dts: qcom: x1e80100: Drop unused passive thermal trip points for CPU + - arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable external DP support + - arm64: dts: qcom: x1e001de-devkit: Enable HBR3 on external DPs + - arm64: dts: qcom: x1e80100-hp-x14: Enable HBR3 on external DPs + - arm64: dts: qcom: x1e80100-qcp: Enable HBR3 on external DPs + - drm/edp-panel: Add panel used by T14s Gen6 Snapdragon + - arm64: dts: qcom: x1e80100-slim7x: Drop incorrect qcom,ath12k-calibration- + variant + - SAUCE: arm64: dts: qcom: x1e80100-crd: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e78100-t14s: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e001de-devkit: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: mark l12b and l15b + always-on + - SAUCE: arm64: dts: qcom: x1e80100-hp-x14: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e80100-yoga-slim7x: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e80100-qcp: mark l12b and l15b always-on + - SAUCE: arm64: dts: qcom: x1e78100-t14s: fix missing HID supplies + - SAUCE: arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes + - SAUCE: arm64: dts: qcom: x1e80100: Enable cpufreq + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Describe the Parade PS8830 retimers + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Enable external DisplayPort support + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Enable HBR3 on external DPs + - SAUCE: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + - SAUCE: Add Bluetooth support for the Lenovo Yoga Slim 7x + - SAUCE: dt-bindings: platform: Add bindings for Lenovo Yoga Slim 7x EC + - SAUCE: platform: arm64: Add driver for Lenovo Yoga Slim 7x's EC + - SAUCE: arm64: dts: qcom: Add EC to Lenovo Yoga Slim 7x + - SAUCE: arm64: dts: qcom: x1e80100-vivobook-s15: Add bluetooth + - SAUCE: arm64: dts: qcom: x1e80100-vivobook-s15: Enable USB-A ports + - SAUCE: arm64: dts: qcom: x1e80100-vivobook-s15: Enable micro-sd card reader + - SAUCE: arm64: dts: qcom: x1p64100-acer-swift-sf14-11 dt for Acer Swift 14 + SF14-11 (touchpad fix) + - SAUCE: dt-bindings: arm: qcom: Add Acer Swift 14 AI + - SAUCE: arm64: dts: qcom: x1e80100-acer-swift-sf14-11: Enable HBR3 on + external DPs + - SAUCE: firmware: qcom: scm: Allow QSEECOM on Acer Swift 14 models + - SAUCE: arm64: dts: qcom: x1e001de-devkit: Set ps8830 reset-gpios active low + - SAUCE: Change: cracking sound fix + - SAUCE: rtc: pm8xxx: add support for uefi offset + - SAUCE: rtc: pm8xxx: mitigate flash wear + - SAUCE: arm64: dts: qcom: sc8280xp-x13s: switch to uefi rtc offset + - SAUCE: dt-bindings: rtc: qcom-pm8xxx: document qcom,no-alarm flag + - SAUCE: rtc: pm8xxx: implement qcom,no-alarm flag for non-HLOS owned alarm + - SAUCE: arm64: dts: qcom: x1e80100: enable rtc + - SAUCE: arm64: dts: qcom: x1e80100-microsoft-romulus: Enable external DP + support + - SAUCE: arm64: dts: qcom: x1e80100-asus-vivobook: Introduce retimers, + external DP + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps-9345: Add WiFi/BT pwrseq + - SAUCE: arm64: dts: qcom: x1e78100-t14s: Add display brightness control + support + - SAUCE: hack: efi/libstub: mitigate t14s exit_boot_services() failure + - [Config] Enable X Elite modules on arm64 + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.14-rc7 rebase + + -- Paolo Pisati Mon, 17 Mar 2025 11:29:48 +0100 + +linux (6.14.0-10.10) plucky; urgency=medium + + * plucky/linux: 6.14.0-10.10 -proposed tracker (LP: #2102106) + + * Miscellaneous Ubuntu changes + - [Config] Revert back to GENKSYMS on amd64/arm64 too, drop rust support + + -- Paolo Pisati Wed, 12 Mar 2025 15:20:52 +0100 + +linux (6.14.0-9.9) plucky; urgency=medium + + * plucky/linux: 6.14.0-9.9 -proposed tracker (LP: #2101943) + + * Miscellaneous Ubuntu changes + - [Config] Revert back to GENKSYMS on non-rust-enabled archs + + -- Paolo Pisati Tue, 11 Mar 2025 12:38:22 +0100 + +linux (6.14.0-8.8) plucky; urgency=medium + + * plucky/linux: 6.14.0-8.8 -proposed tracker (LP: #2101833) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.02.26) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.03.10) + + * wdat_wdt.ko should be pulled in by linux-image-virtual (LP: #2098554) + - [Packaging]: wdat_wdt.ko is moved from "linux-modules-extra-*-generic" to + "linux-modules-*-generic" + + * Add additional PCI ids for BMG support (LP: #2098969) + - drm/xe/bmg: Add new PCI IDs + + * Provide linux-perf package (LP: #1613393) + - [Packaging] Split linux-perf from linux-tools-common + + * linux-tools-common: bpftool wrapper causes build failure for xdp-tools + (LP: #2007308) + - [Packaging] bpftool: move to separate unversioned and unflavored binary + package + + * Miscellaneous Ubuntu changes + - [Packaging] templates/image.postrm.in: Add modules.weakdep to the remove- + list + - [Config] Re-enable rust support, switch from genksyms to gendwarfksyms + - [packaging] check-in copyright directly in debian/ + - [Packaging] remove intermediate $(DEBIAN)/control.stub + - [Config] updateconfigs following v6.14-rc6 rebase + + -- Paolo Pisati Mon, 10 Mar 2025 16:46:27 +0100 + +linux (6.14.0-7.7) plucky; urgency=medium + + * plucky/linux: 6.14.0-7.7 -proposed tracker (LP: #2100581) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Sync riscv64.mk with linux-riscv tree" + + -- Paolo Pisati Fri, 28 Feb 2025 10:46:05 +0100 + +linux (6.14.0-6.6) plucky; urgency=medium + + * plucky/linux: 6.14.0-6.6 -proposed tracker (LP: #2100481) + + * Miscellaneous Ubuntu changes + - [Packaging] riscv64.mk: fix a typo + - [Packaging] enable signing for s390x + - [Packaging] riscv64.mk: disable building as part of linux-generic + + -- Paolo Pisati Fri, 28 Feb 2025 09:44:27 +0100 + +linux (6.14.0-5.5) plucky; urgency=medium + + * plucky/linux: 6.14.0-5.5 -proposed tracker (LP: #2100254) + + * Miscellaneous Ubuntu changes + - [Packaging] Sync riscv64.mk with linux-riscv tree + - [Packaging] clean up the distclean rule + - [Config] updateconfigs following v6.14-rc4 rebase + + -- Paolo Pisati Wed, 26 Feb 2025 11:23:13 +0100 + +linux (6.14.0-4.4) plucky; urgency=medium + + * plucky/linux: 6.14.0-4.4 -proposed tracker (LP: #2098875) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2025.02.11) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [1/53]: Stacking: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [2/53]: Stacking: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [3/53]: Stacking: LSM: security_lsmblob_to_secctx + module selection + - SAUCE: apparmor4.0.0 [4/53]: Stacking: Audit: Add record for multiple task + security contexts + - SAUCE: apparmor4.0.0 [5/53]: Stacking: Audit: multiple subject lsm values + for netlabel + - SAUCE: apparmor4.0.0 [6/53]: Stacking: Audit: Add record for multiple object + contexts + - SAUCE: apparmor4.0.0 [7/53]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor4.0.0 [8/53]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [9/53]: Stacking: Audit: Call only the first of the + audit rule hooks + - SAUCE: apparmor4.0.0 [10/53]: Stacking: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [11/53]: 6.15 apparmor-next: apparmor: Use str_yes_no() + helper function + - SAUCE: apparmor4.0.0 [12/53]: 6.15 apparmor-next: apparmor: Improve debug + print infrastructure + - SAUCE: apparmor4.0.0 [13/53]: 6.15 apparmor-next: apparmor: cleanup: + attachment perm lookup to use lookup_perms() + - SAUCE: apparmor4.0.0 [14/53]: 6.15 apparmor-next: apparmor: remove redundant + unconfined check. + - SAUCE: apparmor4.0.0 [15/53]: 6.15 apparmor-next: apparmor: switch signal + mediation to use RULE_MEDIATES + - SAUCE: apparmor4.0.0 [16/53]: 6.15 apparmor-next: apparmor: ensure labels + with more than one entry have correct flags + - SAUCE: apparmor4.0.0 [17/53]: 6.15 apparmor-next: apparmor: remove explicit + restriction that unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [18/53]: 6.15 apparmor-next: apparmor: cleanup: + refactor file_perm() to doc semantics of some checks + - SAUCE: apparmor4.0.0 [19/53]: 6.15 apparmor-next: apparmor: carry mediation + check on label + - SAUCE: apparmor4.0.0 [20/53]: 6.15 apparmor-next: apparmor: add additional + flags to extended permission. + - SAUCE: apparmor4.0.0 [21/53]: 6.15 apparmor-next: apparmor: add support for + profiles to define the kill signal + - SAUCE: apparmor4.0.0 [22/53]: 6.15 apparmor-next: apparmor: fix + x_table_lookup when stacking is not the first entry + - SAUCE: apparmor4.0.0 [23/53]: 6.15 apparmor-next: apparmor: add ability to + mediate caps with policy state machine + - SAUCE: apparmor4.0.0 [24/53]: 6.15 apparmor-next: apparmor: remove af_select + macro + - SAUCE: apparmor4.0.0 [25/53]: 6.15 apparmor-next: apparmor: lift kernel + socket check out of critical section + - SAUCE: apparmor4.0.0 [26/53]: 6.15 apparmor-next: apparmor: in preparation + for finer networking rules rework match_prot + - SAUCE: apparmor4.0.0 [27/53]: 6.15 apparmor-next: apparmor: add fine grained + af_unix mediation + - SAUCE: apparmor4.0.0 [28/53]: 6.15 apparmor-next: apparmor: gate make fine + grained unix mediation behind v9 abi + - SAUCE: apparmor4.0.0 [29/53]: 6.15 apparmor-next: apparmor: fix dbus + permission queries to v9 ABI + - SAUCE: apparmor4.0.0 [30/53]: 6.15 apparmor-next: apparmor: Fix checking + address of an array in accum_label_info() + - SAUCE: apparmor4.0.0 [31/53]: 6.15 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor4.0.0 [32/53]: 6.15 apparmor-next: apparmor: Modify + mismatched function name + - SAUCE: apparmor4.0.0 [33/53]: 6.15 apparmor-next: apparmor: fix typos and + spelling errors + - SAUCE: apparmor4.0.0 [34/53]: 6.15 apparmor-next: apparmor: use the + condition in AA_BUG_FMT even with debug disabled + - SAUCE: apparmor4.0.0 [35/53]: 6.15 apparmor-next: apparmor: Remove unused + variable 'sock' in __file_sock_perm() + - SAUCE: apparmor4.0.0 [36/53]: Revert "6.15 apparmor-next: apparmor: fix dbus + permission queries to v9 ABI" + - SAUCE: apparmor4.0.0 [37/53]: Revert "6.15 apparmor-next: apparmor: gate + make fine grained unix mediation behind v9 abi" + - SAUCE: apparmor4.0.0 [38/53]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [39/53]: apparmor: make debug_values_table static + - SAUCE: apparmor4.0.0 [40/53]: apparmor: Document that label must be last + member in struct aa_profile + - SAUCE: apparmor4.0.0 [41/53]: apparmor: transition from a list of rules to a + vector of rules + - SAUCE: apparmor4.0.0 [42/53]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [43/53]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [44/53]: add unprivileged user ns mediation + - SAUCE: apparmor4.0.0 [45/53]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/53]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [48/53]: apparmor: allow profile to be transitioned + when a userns is created + - SAUCE: apparmor4.0.0 [49/53]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [51/53]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [52/53]: add io_uring mediation + - SAUCE: apparmor4.0.0 [53/53]: enable userspace upcall for mediation + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [46/53]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - [Packaging] disable signing for ppc64el + - [Packaging] disable signing for s390x + - [packaging] rename to linux + - [Config] update RUSTC version + - [packaging] remove $(wildcard $(DEBIAN)/control.d/*) dependency + - [packaging] avoid piping control-create for error detection + - [packaging] split flavour-control.stub + - [packaging] generate debian/control with correct signed/unsigned + - [packaging] remove DESC and =HUMAN= substitution + - [Packaging] remove unnecessary dependency on control.stub + - [Packaging] add .gitignore and clean more files + - SAUCE: apparmor4.0.0 [50/53]: apparmor: audit mqueue-via-path access as + getattr instead of unlink + - [Packaging] debian.master/dkms-versions -- remove ipu6-drivers, + ipu7-drivers, backport-iwlwifi-dkms and mofed-modules-24.10 FTBFS + + -- Paolo Pisati Thu, 20 Feb 2025 14:20:53 +0100 + +linux-unstable (6.14.0-3.3) plucky; urgency=medium + + * plucky/linux-unstable: 6.14.0-3.3 -proposed tracker (LP: #2098836) + + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] riscv64: Sync config with other architectures + + * Miscellaneous Ubuntu changes + - SAUCE: platform/x86: int3472: fixup s/polarity/gpio_flags/ + - [Config] riscv64: Disable CONFIG_ARCH_RENESAS + - [Config] riscv64: Disable Andes vendor extensions + - [Config] riscv64: Set CONFIG_MMC_SPI=m like other architectures + - [Config] riscv64: Enable Svpbmt support + - [Config] riscv64: Disable kernel compression + - [packaging] enable ppc64el signing + - [Config] updateconfigs + + -- Paolo Pisati Wed, 19 Feb 2025 16:38:27 +0100 + +linux-unstable (6.14.0-2.2) plucky; urgency=medium + + * plucky/linux-unstable: 6.14.0-2.2 -proposed tracker (LP: #2097828) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.14-rc2 rebase + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Build all packages for linux-unstable" + + -- Paolo Pisati Tue, 11 Feb 2025 10:11:13 +0100 + +linux-unstable (6.14.0-1.1) plucky; urgency=medium + + * [25.04 FEAT] In-kernel crypto support MSA 11 HMAC (LP: #2096812) + - [Config] Change CONFIG_CRYPTO_HMAC_S390 to m for s390x + + * Miscellaneous Ubuntu changes + - Update dropped.txt (MODVERSION patches for Rust) + - [Config] updateconfigs following v6.14-rc1 rebase + - SAUCE: binder: turn into module - list_lru_add()/list_lru_del() + - SAUCE: binder: turn into module - lock_vma_under_rcu() + - [Config] temporarily disable DRM_HISI_HIBMC, FTBFS + - dkms: remove zfs, FTBFS + - [Config] armhf: disable TEGRA210_ADMA, FTBFS + + -- Paolo Pisati Fri, 07 Feb 2025 09:41:02 +0100 + +linux-unstable (6.13.0-2.2) plucky; urgency=medium + + * plucky/linux-unstable: 6.13.0-2.2 -proposed tracker (LP: #2096822) + + * Failed to probe for OVTI02C1: chip id mismatch: 560243!=0 (LP: #2090932) + - SAUCE: ACPI: scan: Update HID for new platform + + * Miscellaneous Ubuntu changes + - [Packaging]: Fix linux-bpf-dev build error for non-main kernels + - [Packaging] perf: enable debuginfod support + - [Config] toolchain version update + + -- Timo Aaltonen Tue, 28 Jan 2025 11:15:49 +0200 + +linux-unstable (6.13.0-1.1) plucky; urgency=medium + + * plucky/linux-unstable: 6.13.0-1.1 -proposed tracker (LP: #2096776) + + * Miscellaneous Ubuntu changes + - [Packaging] Rename to linux-unstable, bump version + - [Config] updateconfigs following v6.13 rebase + - [Config] toolchain version update + + -- Timo Aaltonen Mon, 27 Jan 2025 17:54:43 +0200 + +linux-unstable (6.13.0-0.0) plucky; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Mon, 20 Jan 2025 13:35:31 +0200 + +linux (6.12.0-10.10) plucky; urgency=medium + + * plucky/linux: 6.12.0-10.10 -proposed tracker (LP: #2092288) + + * Miscellaneous Ubuntu changes + - [Config] toolchain version update + - [Packaging] Update to clang-19 and newer rustc + - [Config] Re-enable rust support + + -- Paolo Pisati Sun, 29 Dec 2024 11:25:01 +0100 + +linux (6.12.0-9.9) plucky; urgency=medium + + * plucky/linux: 6.12.0-9.9 -proposed tracker (LP: #2092219) + + * Miscellaneous Ubuntu changes + - [Packaging] rules: Fix raw_kernelversion + + -- Paolo Pisati Fri, 20 Dec 2024 10:17:18 +0100 + +linux (6.12.0-8.8) plucky; urgency=medium + + * plucky/linux: 6.12.0-8.8 -proposed tracker (LP: #2092077) + + * Intel AX211 wireless module [8086:7740] subsys [8086:4090] wrongly + recognized as BE201 (LP: #2091546) + - SAUCE: wifi: iwlwifi: fix CRF name for Bz + + * When /dev/vmbus/hv_kvp is not present, disable hv-kvp-daemon (LP: #2091744) + - [Packaging] disable hv-kvp-daemon if needed + + * Miscellaneous Ubuntu changes + - [Packaging] linux-bpf-dev: Restructure packaging + - [Packaging] linux-bpf-dev: Skip packaging for additional kernel flavors + - [Packaging] rules: Convert install-arch-headers to a stamped target + - [Packaging] rules: Fold config check into stamp-prepare-% target + - [Packaging] rules: Fold module signature check into stamp-install-% target + - [Packaging] rules: Remove inclusion of 4-checks.mk + - [Packaging] rules: Remove build tests + - [Packaging] rules: Clean up install-perarch target + - [Packaging] rules: Move the ABI build directory to debian/build + - [Packaging] rules: Introduce global abi_dir variable + - [Packaging] rules: Introduce global build_dir variable + - [Packaging] rules: Remove target_flavour variable + - [Packaging] rules: Remove unused confdir variables + - [Packaging] rules: Remove undefined variables prev_{abinum, revisions} + - [Packaging] rules: Remove explicit kernel compression + - [Packaging] rules: Remove ship_extras_package feature + - [Packaging] rules: Remove stamps/stamp-prepare-indep target + - [Packaging] rules: Explicitly set do_*tools* variables to false + - [Packaging] rules: Wrap do_linux_tools around bpftool install/usage + + -- Paolo Pisati Thu, 19 Dec 2024 15:10:50 +0100 + +linux (6.12.0-7.7) plucky; urgency=medium + + * plucky/linux: 6.12.0-7.7 -proposed tracker (LP: #2091852) + + * Miscellaneous Ubuntu changes + - remove the AA stack + + * Remove the entire AA stack (FTBFS) + + -- Paolo Pisati Wed, 18 Dec 2024 14:55:25 +0100 + +linux (6.12.0-6.6) plucky; urgency=medium + + * plucky/linux: 6.12.0-6.6 -proposed tracker (LP: #2091721) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [29/84]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [30/84]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [31/84]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [32/84]: af_unix mediation + - SAUCE: apparmor4.0.0 [33/84]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [35/84]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [36/84]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [37/84]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [38/84]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [39/84]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [40/84]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [41/84]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [42/84]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [43/84]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [44/84]: prompt - fix caching + - SAUCE: apparmor4.0.0 [45/84]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [46/84]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [47/84]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [48/84]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [49/84]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [50/84]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/93] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [55/84]: add io_uring mediation + - SAUCE: apparmor4.0.0 [56/84]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [57/84]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [58/84]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [59/84]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [60/84]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [61/84]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [62/84]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [63/84]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [64/84]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [65/84]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [66/84]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [67/84]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [68/84]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [69/84]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [70/84]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [71/84]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [72/84]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [73/84]: fixup notify + - SAUCE: apparmor4.0.0 [74/84]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [75/84]: apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [76/84]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0 [77/84]: fix reserved mem for when we save ipv6 + addresses + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * linux-gcp 6.8.0-1005.5 (+ others) Noble kernel regression with new apparmor + profiles/features (LP: #2061851) + - SAUCE: apparmor4.0.0 [78/84]: fix address mapping for recvfrom + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [52/84]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [53/84]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [54/84]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - [packaging] rename to linux + - SAUCE: apparmor4.0.0 [1/84]: LSM: Add the lsm_prop data structure. + - SAUCE: apparmor4.0.0 [2/84]: LSM: Use lsm_prop in security_audit_rule_match + - SAUCE: apparmor4.0.0 [3/84]: LSM: Add lsmprop_to_secctx hook + - SAUCE: apparmor4.0.0 [4/84]: Audit: maintain an lsm_prop in audit_context + - SAUCE: apparmor4.0.0 [5/84]: LSM: Use lsm_prop in security_ipc_getsecid + - SAUCE: apparmor4.0.0 [6/84]: Audit: Update shutdown LSM data + - SAUCE: apparmor4.0.0 [7/84]: LSM: Use lsm_prop in security_current_getsecid + - SAUCE: apparmor4.0.0 [8/84]: LSM: Use lsm_prop in security_inode_getsecid + - SAUCE: apparmor4.0.0 [9/84]: Audit: use an lsm_prop in audit_names + - SAUCE: apparmor4.0.0 [10/84]: LSM: Create new security_cred_getlsmprop LSM + hook + - SAUCE: apparmor4.0.0 [11/84]: Audit: Change context data from secid to + lsm_prop + - SAUCE: apparmor4.0.0 [12/84]: Use lsm_prop for audit data + - SAUCE: apparmor4.0.0 [13/84]: LSM: Remove lsm_prop scaffolding + - SAUCE: apparmor4.0.0 [14/84]: LSM: Ensure the correct LSM context releaser + - SAUCE: apparmor4.0.0 [15/84]: LSM: Replace context+len with lsm_context + - SAUCE: apparmor4.0.0 [16/84]: LSM: Use lsm_context in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [17/84]: LSM: lsm_context in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [18/84]: LSM: secctx provider check on release + - SAUCE: apparmor4.0.0 [19/84]: LSM: Use lsm_context in + security_inode_notifysecctx + - SAUCE: apparmor4.0.0 [20/84]: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [21/84]: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [22/84]: LSM: security_lsmblob_to_secctx module + selection + - SAUCE: apparmor4.0.0 [23/84]: Audit: Add record for multiple task security + contexts + - SAUCE: apparmor4.0.0 [24/84]: Audit: multiple subject lsm values for + netlabel + - SAUCE: apparmor4.0.0 [25/84]: Audit: Add record for multiple object contexts + - SAUCE: apparmor4.0.0 [26/84]: LSM: Single calls in secid hooks + - SAUCE: apparmor4.0.0 [27/84]: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [28/84]: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [34/84]: fixup inode_set_attr + - SAUCE: apparmor4.0.0 [79/84]: apparmor: add support for 2^24 states to the + dfa state machine. + - SAUCE: apparmor4.0.0 [80/84]: apparmor: advertise to userspace support of + user upcall for file rules. + - SAUCE: apparmor4.0.0 [81/84]: apparmor: allocate xmatch for nullpdf inside + aa_alloc_null + - SAUCE: apparmor4.0.0 [82/84]: apparmor: properly handle cx/px lookup failure + for complain + - SAUCE: apparmor4.0.0 [83/84]: apparmor: fix prompt failing during large down + loads + - SAUCE: apparmor4.0.0 [84/84]: apparmor: fix allow field in notification + + -- Paolo Pisati Fri, 13 Dec 2024 16:35:21 +0100 + +linux (6.12.0-5.5) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-5.5 -proposed tracker (LP: #2091628) + + * Plucky update: v6.12.4 upstream stable release (LP: #2091627) + - xfs: remove unknown compat feature check in superblock write validation + - quota: flush quota_release_work upon quota writeback + - btrfs: drop unused parameter file_offset from + btrfs_encoded_read_regular_fill_pages() + - btrfs: change btrfs_encoded_read() so that reading of extent is done by + caller + - btrfs: move priv off stack in btrfs_encoded_read_regular_fill_pages() + - btrfs: fix use-after-free in btrfs_encoded_read_endio() + - btrfs: don't loop for nowait writes when checking for cross references + - btrfs: add a sanity check for btrfs root in btrfs_search_slot() + - btrfs: ref-verify: fix use-after-free after invalid ref action + - iommu/tegra241-cmdqv: Fix unused variable warning + - netkit: Add option for scrubbing skb meta data + - md/raid5: Wait sync io to finish before changing group cnt + - md/md-bitmap: Add missing destroy_work_on_stack() + - arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer + - arm64: dts: mediatek: mt8186-corsola: Fix GPU supply coupling max-spread + - arm64: dts: freescale: imx8mm-verdin: Fix SD regulator startup delay + - arm64: dts: ti: k3-am62-verdin: Fix SD regulator startup delay + - arm64: dts: mediatek: mt8186-corsola: Fix IT6505 reset line polarity + - media: qcom: camss: fix error path on configuration of power domains + - media: amphion: Set video drvdata before register video device + - media: imx-jpeg: Set video drvdata before register video device + - media: mtk-jpeg: Fix null-ptr-deref during unload module + - media: i2c: dw9768: Fix pm_runtime_set_suspended() with runtime pm enabled + - arm64: dts: freescale: imx8mp-verdin: Fix SD regulator startup delay + - media: i2c: tc358743: Fix crash in the probe error path when using polling + - media: imx-jpeg: Ensure power suppliers be suspended before detach them + - media: platform: rga: fix 32-bit DMA limitation + - media: verisilicon: av1: Fix reference video buffer pointer assignment + - media: ts2020: fix null-ptr-deref in ts2020_probe() + - media: platform: exynos4-is: Fix an OF node reference leak in + fimc_md_is_isp_available + - efi/libstub: Free correct pointer on failure + - net: phy: dp83869: fix status reporting for 1000base-x autonegotiation + - media: amphion: Fix pm_runtime_set_suspended() with runtime pm enabled + - media: venus: Fix pm_runtime_set_suspended() with runtime pm enabled + - media: gspca: ov534-ov772x: Fix off-by-one error in set_frame_rate() + - media: ov08x40: Fix burst write sequence + - media: platform: allegro-dvt: Fix possible memory leak in + allocate_buffers_internal() + - media: uvcvideo: Stop stream during unregister + - media: uvcvideo: Require entities to have a non-zero unique ID + - tracing: Fix function timing profiler to initialize hashtable + - kunit: Fix potential null dereference in kunit_device_driver_test() + - kunit: string-stream: Fix a UAF bug in kunit_init_suite() + - ovl: Filter invalid inodes with missing lookup function + - maple_tree: refine mas_store_root() on storing NULL + - ftrace: Fix regression with module command in stack_trace_filter + - vmstat: call fold_vm_zone_numa_events() before show per zone NUMA event + - zram: clear IDLE flag after recompression + - iommu/io-pgtable-arm: Fix stage-2 map/unmap for concatenated tables + - iommu/arm-smmu: Defer probe of clients after smmu device bound + - leds: lp55xx: Remove redundant test for invalid channel number + - mm/damon/vaddr: fix issue in damon_va_evenly_split_region() + - powerpc/vdso: Drop -mstack-protector-guard flags in 32-bit files with clang + - cpufreq: scmi: Fix cleanup path when boost enablement fails + - clk: qcom: gcc-qcs404: fix initial rate of GPLL3 + - ad7780: fix division by zero in ad7780_write_raw() + - nvmem: core: Check read_only flag for force_ro in bin_attr_nvmem_write() + - driver core: fw_devlink: Stop trying to optimize cycle detection logic + - spmi: pmic-arb: fix return path in for_each_available_child_of_node() + - ARM: 9429/1: ioremap: Sync PGDs for VMALLOC shadow + - s390/entry: Mark IRQ entries to fix stack depot warnings + - ARM: 9430/1: entry: Do a dummy read from VMAP shadow + - ARM: 9431/1: mm: Pair atomic_set_release() with _read_acquire() + - net: stmmac: set initial EEE policy configuration + - vfio/qat: fix overflow check in qat_vf_resume_write() + - PCI: qcom: Disable ASPM L0s for X1E80100 + - perf jevents: fix breakage when do perf stat on system metric + - remoteproc: qcom_q6v5_pas: disable auto boot for wpss + - PCI: imx6: Fix suspend/resume support on i.MX6QDL + - mm/slub: Avoid list corruption when removing a slab from the full list + - f2fs: fix to drop all discards after creating snapshot on lvm device + - ceph: extract entity name from device id + - ceph: pass cred pointer to ceph_mds_auth_match() + - ceph: fix cred leak in ceph_mds_check_access() + - mtd: spinand: winbond: Fix 512GW and 02JW OOB layout + - mtd: spinand: winbond: Fix 512GW, 01GW, 01JW and 02JW ECC information + - util_macros.h: fix/rework find_closest() macros + - s390/stacktrace: Use break instead of return statement + - scsi: ufs: exynos: Add check inside exynos_ufs_config_smu() + - scsi: ufs: exynos: Fix hibern8 notify callbacks + - i3c: master: svc: Fix pm_runtime_set_suspended() with runtime pm enabled + - i3c: master: Fix miss free init_dyn_addr at i3c_master_put_i3c_addrs() + - i3c: master: svc: fix possible assignment of the same address to two devices + - i3c: master: svc: Modify enabled_events bit 7:0 to act as IBI enable counter + - PCI: keystone: Set mode as Root Complex for "ti,keystone-pcie" compatible + - PCI: keystone: Add link up check to ks_pcie_other_map_bus() + - PCI: endpoint: Fix PCI domain ID release in pci_epc_destroy() + - PCI: endpoint: Clear secondary (not primary) EPC in pci_epc_remove_epf() + - slab: Fix too strict alignment check in create_cache() + - fs/proc/kcore.c: Clear ret value in read_kcore_iter after successful + iov_iter_zero + - thermal: int3400: Fix reading of current_uuid for active policy + - leds: flash: mt6360: Fix device_for_each_child_node() refcounting in error + paths + - ovl: properly handle large files in ovl_security_fileattr + - mm/vmalloc: combine all TLB flush operations of KASAN shadow virtual address + into one operation + - dm: Fix typo in error message + - dm thin: Add missing destroy_work_on_stack() + - PCI: dwc: ep: Fix advertised resizable BAR size regression + - PCI: of_property: Assign PCI instead of CPU bus address to dynamic PCI nodes + - PCI: rockchip-ep: Fix address translation unit programming + - nfsd: make sure exp active before svc_export_show + - nfsd: fix nfs4_openowner leak when concurrent nfsd4_open occur + - iio: accel: kx022a: Fix raw read format + - iio: invensense: fix multiple odr switch when FIFO is off + - iio: Fix fwnode_handle in __fwnode_iio_channel_get_by_name() + - iio: adc: ad7923: Fix buffer overflow for tx_buf and ring_xfer + - iio: gts: fix infinite loop for gain_to_scaletables() + - powerpc: Fix stack protector Kconfig test for clang + - powerpc: Adjust adding stack protector flags to KBUILD_CLAGS for clang + - binder: fix node UAF in binder_add_freeze_work() + - binder: fix OOB in binder_add_freeze_work() + - binder: fix freeze UAF in binder_release_work() + - binder: fix BINDER_WORK_FROZEN_BINDER debug logs + - binder: fix BINDER_WORK_CLEAR_FREEZE_NOTIFICATION debug logs + - binder: allow freeze notification for dead nodes + - binder: fix memleak of proc->delivered_freeze + - binder: add delivered_freeze to debugfs output + - dt-bindings: net: fec: add pps channel property + - net: fec: refactor PPS channel configuration + - net: fec: make PPS channel configurable + - drm/panic: Fix uninitialized spinlock acquisition with CONFIG_DRM_PANIC=n + - drm/sti: avoid potential dereference of error pointers in + sti_hqvdp_atomic_check + - drm/sti: avoid potential dereference of error pointers in + sti_gdp_atomic_check + - drm: panel: jd9365da-h3: Remove unused num_init_cmds structure member + - drm/sti: avoid potential dereference of error pointers + - drm/fbdev-dma: Select FB_DEFERRED_IO + - drm/mediatek: Fix child node refcount handling in early exit + - drm/bridge: it6505: Fix inverted reset polarity + - drm/etnaviv: flush shader L1 cache after user commandstream + - drm: xlnx: zynqmp_dpsub: fix hotplug detection + - drm/xe/xe_guc_ads: save/restore OA registers and allowlist regs + - drm/xe/migrate: fix pat index usage + - Revert "drm/radeon: Delay Connector detecting when HPD singals is unstable" + - drm/xe/migrate: use XE_BO_FLAG_PAGETABLE + - drm/xe/guc_submit: fix race around suspend_pending + - drm/amdkfd: Use the correct wptr size + - drm/amdgpu/pm: add gen5 display to the user on smu v14.0.2/3 + - drm/amd: Add some missing straps from NBIO 7.11.0 + - drm/amdgpu: fix usage slab after free + - drm/amd/pm: skip setting the power source on smu v14.0.2/3 + - drm/amd: Fix initialization mistake for NBIO 7.11 devices + - drm/amd/pm: update current_socclk and current_uclk in gpu_metrics on smu + v13.0.7 + - drm/amd/pm: disable pcie speed switching on Intel platform for smu v14.0.2/3 + - drm/amd/pm: Remove arcturus min power limit + - drm/amd/display: Fix handling of plane refcount + - drm/amd/display: update pipe selection policy to check head pipe + - drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto + - posix-timers: Target group sigqueue to current task only if not exiting + - Revert "drm/xe/xe_guc_ads: save/restore OA registers and allowlist regs" + - Linux 6.12.4 + + * Plucky update: v6.12.3 upstream stable release (LP: #2091626) + - sched: Initialize idle tasks only once + - Linux 6.12.3 + + * Plucky update: v6.12.2 upstream stable release (LP: #2091625) + - MAINTAINERS: appoint myself the XFS maintainer for 6.12 LTS + - drm/amd/display: Skip Invalid Streams from DSC Policy + - drm/amd/display: Fix incorrect DSC recompute trigger + - s390/facilities: Fix warning about shadow of global variable + - s390/virtio_ccw: Fix dma_parm pointer not set up + - efs: fix the efs new mount api implementation + - arm64: probes: Disable kprobes/uprobes on MOPS instructions + - kselftest/arm64: hwcap: fix f8dp2 cpuinfo name + - kselftest/arm64: mte: fix printf type warnings about __u64 + - kselftest/arm64: mte: fix printf type warnings about longs + - block/fs: Pass an iocb to generic_atomic_write_valid() + - fs/block: Check for IOCB_DIRECT in generic_atomic_write_valid() + - s390/cio: Do not unregister the subchannel based on DNV + - s390/pageattr: Implement missing kernel_page_present() + - x86/pvh: Call C code via the kernel virtual mapping + - brd: defer automatic disk creation until module initialization succeeds + - ext4: avoid remount errors with 'abort' mount option + - mips: asm: fix warning when disabling MIPS_FP_SUPPORT + - s390/cpum_sf: Fix and protect memory allocation of SDBs with mutex + - initramfs: avoid filename buffer overrun + - arm64: Expose ID_AA64ISAR1_EL1.XS to sanitised feature consumers + - kselftest/arm64: Fix encoding for SVE B16B16 test + - nvme-pci: fix freeing of the HMB descriptor table + - m68k: mvme147: Fix SCSI controller IRQ numbers + - m68k: mvme147: Reinstate early console + - arm64: fix .data.rel.ro size assertion when CONFIG_LTO_CLANG + - acpi/arm64: Adjust error handling procedure in gtdt_parse_timer_block() + - loop: fix type of block size + - cachefiles: Fix incorrect length return value in + cachefiles_ondemand_fd_write_iter() + - cachefiles: Fix missing pos updates in cachefiles_ondemand_fd_write_iter() + - cachefiles: Fix NULL pointer dereference in object->file + - netfs/fscache: Add a memory barrier for FSCACHE_VOLUME_CREATING + - block: take chunk_sectors into account in bio_split_write_zeroes + - block: fix bio_split_rw_at to take zone_write_granularity into account + - s390/syscalls: Avoid creation of arch/arch/ directory + - hfsplus: don't query the device logical block size multiple times + - ext4: fix race in buffer_head read fault injection + - nvme-pci: reverse request order in nvme_queue_rqs + - virtio_blk: reverse request order in virtio_queue_rqs + - crypto: mxs-dcp - Fix AES-CBC with hardware-bound keys + - crypto: caam - Fix the pointer passed to caam_qi_shutdown() + - crypto: qat - remove check after debugfs_create_dir() + - crypto: qat/qat_420xx - fix off by one in uof_get_name() + - crypto: qat/qat_4xxx - fix off by one in uof_get_name() + - firmware: google: Unregister driver_info on failure + - EDAC/bluefield: Fix potential integer overflow + - crypto: qat - remove faulty arbiter config reset + - thermal: core: Initialize thermal zones before registering them + - thermal: core: Rearrange PM notification code + - thermal: core: Represent suspend-related thermal zone flags as bits + - thermal: core: Mark thermal zones as initializing to start with + - thermal: core: Fix race between zone registration and system suspend + - EDAC/fsl_ddr: Fix bad bit shift operations + - EDAC/skx_common: Differentiate memory error sources + - EDAC/{skx_common,i10nm}: Fix incorrect far-memory error source indicator + - crypto: pcrypt - Call crypto layer directly when padata_do_parallel() return + -EBUSY + - crypto: cavium - Fix the if condition to exit loop after timeout + - cpufreq/amd-pstate: Don't update CPPC request in + amd_pstate_cpu_boost_update() + - amd-pstate: Set min_perf to nominal_perf for active mode performance gov + - crypto: hisilicon/qm - disable same error report before resetting + - EDAC/igen6: Avoid segmentation fault on module unload + - crypto: qat - Fix missing destroy_workqueue in adf_init_aer() + - crypto: inside-secure - Fix the return value of safexcel_xcbcmac_cra_init() + - sched/cpufreq: Ensure sd is rebuilt for EAS check + - doc: rcu: update printed dynticks counter bits + - rcu/srcutiny: don't return before reenabling preemption + - rcu/kvfree: Fix data-race in __mod_timer / kvfree_call_rcu + - rcu/nocb: Fix missed RCU barrier on deoffloading + - hwmon: (pmbus/core) clear faults after setting smbalert mask + - hwmon: (nct6775-core) Fix overflows seen when writing limit attributes + - ACPI: CPPC: Fix _CPC register setting issue + - thermal: testing: Use DEFINE_FREE() and __free() to simplify code + - thermal: testing: Initialize some variables annoteded with _free() + - crypto: caam - add error check to caam_rsa_set_priv_key_form + - crypto: bcm - add error check in the ahash_hmac_init function + - crypto: cavium - Fix an error handling path in cpt_ucode_load_fw() + - rcuscale: Do a proper cleanup if kfree_scale_init() fails + - tools/lib/thermal: Make more generic the command encoding function + - thermal/lib: Fix memory leak on error in thermal_genl_auto() + - x86/unwind/orc: Fix unwind for newly forked tasks + - Revert "scripts/faddr2line: Check only two symbols when calculating symbol + size" + - cleanup: Remove address space of returned pointer + - time: Partially revert cleanup on msecs_to_jiffies() documentation + - time: Fix references to _msecs_to_jiffies() handling of values + - timers: Add missing READ_ONCE() in __run_timer_base() + - locking/atomic/x86: Use ALT_OUTPUT_SP() for __alternative_atomic64() + - locking/atomic/x86: Use ALT_OUTPUT_SP() for __arch_{,try_}cmpxchg64_emu() + - kcsan, seqlock: Support seqcount_latch_t + - kcsan, seqlock: Fix incorrect assumption in read_seqbegin() + - sched/ext: Remove sched_fork() hack + - locking/rt: Add sparse annotation PREEMPT_RT's sleeping locks. + - rust: helpers: Avoid raw_spin_lock initialization for PREEMPT_RT + - clocksource/drivers:sp804: Make user selectable + - clocksource/drivers/timer-ti-dm: Fix child node refcount handling + - irqchip/riscv-aplic: Prevent crash when MSI domain is missing + - regulator: qcom-smd: make smd_vreg_rpm static + - spi: spi-fsl-lpspi: Use IRQF_NO_AUTOEN flag in request_irq() + - arm64: dts: qcom: qcs6390-rb3gen2: use modem.mbn for modem DSP + - ARM: dts: renesas: genmai: Fix partition size for QSPI NOR Flash + - drivers: soc: xilinx: add the missing kfree in xlnx_add_cb_for_suspend() + - microblaze: Export xmb_manager functions + - arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain + - arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phy + - arm64: dts: mt8195: Fix dtbs_check error for mutex node + - arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node + - arm64: dts: mediatek: mt8183-kukui: Disable DPI display interface + - arm64: dts: mt8183: Add port node to dpi node + - soc: ti: smartreflex: Use IRQF_NO_AUTOEN flag in request_irq() + - soc: qcom: geni-se: fix array underflow in geni_se_clk_tbl_get() + - arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbins + - arm64: dts: qcom: sda660-ifc6560: fix l10a voltage ranges + - ARM: dts: microchip: sam9x60: Add missing property atmel,usart-mode + - mmc: mmc_spi: drop buggy snprintf() + - scripts/kernel-doc: Do not track section counter across processed files + - arm64: dts: qcom: x1e80100-slim7x: Drop orientation-switch from USB SS[0-1] + QMP PHYs + - arm64: dts: qcom: x1e80100-vivobook-s15: Drop orientation-switch from USB + SS[0-1] QMP PHYs + - openrisc: Implement fixmap to fix earlycon + - efi/libstub: fix efi_parse_options() ignoring the default command line + - tpm: fix signed/unsigned bug when checking event logs + - media: i2c: max96717: clean up on error in max96717_subdev_init() + - media: i2c: vgxy61: Fix an error handling path in vgxy61_detect() + - media: i2c: ds90ub960: Fix missing return check on ub960_rxport_read call + - arm64: dts: mt8183: krane: Fix the address of eeprom at i2c4 + - arm64: dts: mt8183: kukui: Fix the address of eeprom at i2c4 + - arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region + - kernel-doc: allow object-like macros in ReST output + - arm64: dts: ti: k3-am62x-phyboard-lyra: Drop unnecessary McASP AFIFOs + - gpio: sloppy-logic-analyzer remove reference to rcu_momentary_dyntick_idle() + - arm64: dts: mediatek: mt8173-elm-hana: Add vdd-supply to second source + trackpad + - arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status + - arm64: dts: mediatek: mt8195-cherry: Use correct audio codec DAI + - Revert "cgroup: Fix memory leak caused by missing cgroup_bpf_offline" + - cgroup/bpf: only cgroup v2 can be attached by bpf programs + - regulator: rk808: Restrict DVS GPIOs to the RK808 variant only + - power: sequencing: make the QCom PMU pwrseq driver depend on CONFIG_OF + - arm64: tegra: p2180: Add mandatory compatible for WiFi node + - arm64: dts: rockchip: Remove 'enable-active-low' from two boards + - arm64: dts: mt8183: fennel: add i2c2's i2c-scl-internal-delay-ns + - arm64: dts: mt8183: burnet: add i2c2's i2c-scl-internal-delay-ns + - arm64: dts: mt8183: cozmo: add i2c2's i2c-scl-internal-delay-ns + - arm64: dts: mt8183: Damu: add i2c2's i2c-scl-internal-delay-ns + - pwm: imx27: Workaround of the pwm output bug when decrease the duty cycle + - ARM: dts: cubieboard4: Fix DCDC5 regulator constraints + - arm64: dts: ti: k3-j7200: Fix register map for main domain pmx + - arm64: dts: ti: k3-j7200: Fix clock ids for MCSPI instances + - arm64: dts: ti: k3-j721e: Fix clock IDs for MCSPI instances + - arm64: dts: ti: k3-j721s2: Fix clock IDs for MCSPI instances + - watchdog: Add HAS_IOPORT dependency for SBC8360 and SBC7240 + - arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers + - dt-bindings: cache: qcom,llcc: Fix X1E80100 reg entries + - of/fdt: add dt_phys arg to early_init_dt_scan and early_init_dt_verify + - pmdomain: ti-sci: Add missing of_node_put() for args.np + - spi: tegra210-quad: Avoid shift-out-of-bounds + - spi: zynqmp-gqspi: Undo runtime PM changes at driver exit time​ + - regmap: irq: Set lockdep class for hierarchical IRQ domains + - arm64: dts: renesas: hihope: Drop #sound-dai-cells + - arm64: dts: imx8mn-tqma8mqnl-mba8mx-usbot: fix coexistence of output-low and + output-high in GPIO + - arm64: dts: mediatek: mt6358: fix dtbs_check error + - arm64: dts: mediatek: mt8183-kukui-jacuzzi: Fix DP bridge supply names + - arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add supplies for fixed + regulators + - selftests/resctrl: Print accurate buffer size as part of MBM results + - selftests/resctrl: Fix memory overflow due to unhandled wraparound + - selftests/resctrl: Protect against array overrun during iMC config parsing + - firmware: arm_scpi: Check the DVFS OPP count returned by the firmware + - media: ipu6: Fix DMA and physical address debugging messages for 32-bit + - media: ipu6: not override the dma_ops of device in driver + - media: ipu6: remove architecture DMA ops dependency in Kconfig + - pwm: Assume a disabled PWM to emit a constant inactive output + - media: atomisp: Add check for rgby_data memory allocation failure + - arm64: dts: rockchip: correct analog audio name on Indiedroid Nova + - sched_ext: scx_bpf_dispatch_from_dsq_set_*() are allowed from unlocked + context + - HID: hyperv: streamline driver probe to avoid devres issues + - platform/x86: asus-wmi: Fix inconsistent use of thermal policies + - platform/x86/intel/pmt: allow user offset for PMT callbacks + - platform/x86: panasonic-laptop: Return errno correctly in show callback + - drm/imagination: Convert to use time_before macro + - drm/imagination: Use pvr_vm_context_get() + - drm/mm: Mark drm_mm_interval_tree*() functions with __maybe_unused + - drm/vc4: hvs: Don't write gamma luts on 2711 + - drm/vc4: hdmi: Avoid hang with debug registers when suspended + - drm/vc4: hvs: Fix dlist debug not resetting the next entry pointer + - drm/vc4: hvs: Remove incorrect limit from hvs_dlist debugfs function + - drm/vc4: hvs: Correct logic on stopping an HVS channel + - wifi: ath9k: add range check for conn_rsp_epid in htc_connect_service() + - drm/omap: Fix possible NULL dereference + - drm/omap: Fix locking in omap_gem_new_dmabuf() + - drm/v3d: Appease lockdep while updating GPU stats + - wifi: p54: Use IRQF_NO_AUTOEN flag in request_irq() + - wifi: mwifiex: Use IRQF_NO_AUTOEN flag in request_irq() + - udmabuf: change folios array from kmalloc to kvmalloc + - udmabuf: fix vmap_udmabuf error page set + - drm/imx/dcss: Use IRQF_NO_AUTOEN flag in request_irq() + - drm/imx/ipuv3: Use IRQF_NO_AUTOEN flag in request_irq() + - drm/panel: nt35510: Make new commands optional + - drm/v3d: Address race-condition in MMU flush + - drm/v3d: Flush the MMU before we supply more memory to the binner + - drm/amdgpu: Fix JPEG v4.0.3 register write + - wifi: ath10k: fix invalid VHT parameters in supported_vht_mcs_rate_nss1 + - wifi: ath10k: fix invalid VHT parameters in supported_vht_mcs_rate_nss2 + - wifi: ath12k: Skip Rx TID cleanup for self peer + - dt-bindings: vendor-prefixes: Add NeoFidelity, Inc + - ASoC: fsl_micfil: fix regmap_write_bits usage + - ASoC: dt-bindings: mt6359: Update generic node name and dmic-mode + - drm/amdgpu/gfx9: Add Cleaner Shader Deinitialization in gfx_v9_0 Module + - ASoC: fsl-asoc-card: Add missing handling of {hp,mic}-dt-gpios + - drm/bridge: anx7625: Drop EDID cache on bridge power off + - drm/bridge: it6505: Drop EDID cache on bridge power off + - libbpf: Fix expected_attach_type set handling in program load callback + - libbpf: Fix output .symtab byte-order during linking + - selftests/bpf: Fix uprobe_multi compilation error + - dlm: fix swapped args sb_flags vs sb_status + - wifi: rtl8xxxu: Perform update_beacon_work when beaconing is enabled + - ASoC: amd: acp: fix for inconsistent indenting + - ASoC: amd: acp: fix for cpu dai index logic + - drm/amd/display: fix a memleak issue when driver is removed + - wifi: ath12k: fix use-after-free in ath12k_dp_cc_cleanup() + - wifi: ath12k: fix one more memcpy size error + - libbpf: Add missing per-arch include path + - selftests: bpf: Add missing per-arch include path + - bpf: Fix the xdp_adjust_tail sample prog issue + - selftests/bpf: Fix backtrace printing for selftests crashes + - wifi: ath11k: Fix CE offset address calculation for WCN6750 in SSR + - selftests/bpf: add missing header include for htons + - wifi: cfg80211: check radio iface combination for multi radio per wiphy + - ice: consistently use q_idx in ice_vc_cfg_qs_msg() + - drm/vc4: hdmi: Increase audio MAI fifo dreq threshold + - drm/vc4: Introduce generation number enum + - drm/vc4: Match drm_dev_enter and exit calls in vc4_hvs_lut_load + - drm/vc4: Match drm_dev_enter and exit calls in vc4_hvs_atomic_flush + - drm/vc4: Correct generation check in vc4_hvs_lut_load + - libbpf: fix sym_is_subprog() logic for weak global subprogs + - accel/ivpu: Prevent recovery invocation during probe and resume + - ASoC: rt722-sdca: Remove logically deadcode in rt722-sdca.c + - libbpf: never interpret subprogs in .text as entry programs + - netdevsim: copy addresses for both in and out paths + - drm/bridge: tc358767: Fix link properties discovery + - drm/panic: Select ZLIB_DEFLATE for DRM_PANIC_SCREEN_QR_CODE + - selftests/bpf: Fix msg_verify_data in test_sockmap + - selftests/bpf: Fix txmsg_redir of test_txmsg_pull in test_sockmap + - wifi: mwifiex: add missing locking for cfg80211 calls + - wifi: wilc1000: Set MAC after operation mode + - wifi: mwifiex: Fix memcpy() field-spanning write warning in + mwifiex_config_scan() + - drm: fsl-dcu: enable PIXCLK on LS1021A + - drm: panel: nv3052c: correct spi_device_id for RG35XX panel + - drm/msm/dpu: on SDM845 move DSPP_3 to LM_5 block + - drm/msm/dpu: drop LM_3 / LM_4 on SDM845 + - drm/msm/dpu: drop LM_3 / LM_4 on MSM8998 + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_common.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_ethtool.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_flows.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in cn10k.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_dmac_flt.c + - octeontx2-pf: handle otx2_mbox_get_rsp errors in otx2_dcbnl.c + - selftests/bpf: fix test_spin_lock_fail.c's global vars usage + - libbpf: move global data mmap()'ing into bpf_object__load() + - wifi: rtw89: rename rtw89_vif to rtw89_vif_link ahead for MLO + - wifi: rtw89: rename rtw89_sta to rtw89_sta_link ahead for MLO + - wifi: rtw89: read bss_conf corresponding to the link + - wifi: rtw89: read link_sta corresponding to the link + - wifi: rtw89: refactor VIF related func ahead for MLO + - wifi: rtw89: refactor STA related func ahead for MLO + - wifi: rtw89: tweak driver architecture for impending MLO support + - wifi: rtw89: Fix TX fail with A2DP after scanning + - wifi: rtw89: unlock on error path in rtw89_ops_unassign_vif_chanctx() + - drm/panfrost: Remove unused id_mask from struct panfrost_model + - bpf, arm64: Remove garbage frame for struct_ops trampoline + - drm/msm/adreno: Use IRQF_NO_AUTOEN flag in request_irq() + - drm/msm/gpu: Check the status of registration to PM QoS + - drm/xe/hdcp: Fix gsc structure check in fw check status + - drm/etnaviv: Request pages from DMA32 zone on addressing_limited + - drm/etnaviv: hold GPU lock across perfmon sampling + - drm/amd/display: Increase idle worker HPD detection time + - drm/amd/display: Reduce HPD Detection Interval for IPS + - drm/nouveau/gr/gf100: Fix missing unlock in gf100_gr_chan_new() + - drm: zynqmp_kms: Unplug DRM device before removal + - drm: xlnx: zynqmp_disp: layer may be null while releasing + - wifi: wfx: Fix error handling in wfx_core_init() + - wifi: cw1200: Fix potential NULL dereference + - drm/msm/dpu: cast crtc_clk calculation to u64 in _dpu_core_perf_calc_clk() + - bpf, bpftool: Fix incorrect disasm pc + - bpf: Tighten tail call checks for lingering locks, RCU, preempt_disable + - drm/vkms: Drop unnecessary call to drm_crtc_cleanup() + - drm/amdgpu: Fix the memory allocation issue in + amdgpu_discovery_get_nps_info() + - drm/amdkfd: Use dynamic allocation for CU occupancy array in + 'kfd_get_cu_occupancy()' + - bpf: Mark raw_tp arguments with PTR_MAYBE_NULL + - drm: use ATOMIC64_INIT() for atomic64_t + - netfilter: nf_tables: avoid false-positive lockdep splat on rule deletion + - netfilter: nf_tables: must hold rcu read lock while iterating expression + type list + - netfilter: nf_tables: must hold rcu read lock while iterating object type + list + - netlink: typographical error in nlmsg_type constants definition + - wifi: rtw89: coex: check NULL return of kmalloc in btc_fw_set_monreg() + - drm/panfrost: Add missing OPP table refcnt decremental + - drm/panthor: introduce job cycle and timestamp accounting + - drm/panthor: record current and maximum device clock frequencies + - drm/panthor: Fix OPP refcnt leaks in devfreq initialisation + - isofs: avoid memory leak in iocharset + - selftests/bpf: Add txmsg_pass to pull/push/pop in test_sockmap + - selftests/bpf: Fix SENDPAGE data logic in test_sockmap + - selftests/bpf: Fix total_bytes in msg_loop_rx in test_sockmap + - selftests/bpf: Add push/pop checking for msg_verify_data in test_sockmap + - bpf, sockmap: Several fixes to bpf_msg_push_data + - bpf, sockmap: Several fixes to bpf_msg_pop_data + - bpf, sockmap: Fix sk_msg_reset_curr + - ipv6: release nexthop on device removal + - selftests: net: really check for bg process completion + - wifi: cfg80211: Remove the Medium Synchronization Delay validity check + - wifi: iwlwifi: allow fast resume on ax200 + - wifi: iwlwifi: mvm: tell iwlmei when we finished suspending + - drm/amdgpu: fix ACA bank count boundary check error + - drm/amdgpu: Fix map/unmap queue logic + - drm/amdkfd: Fix wrong usage of INIT_WORK() + - bpf: Allow return values 0 and 1 for kprobe session + - bpf: Force uprobe bpf program to always return 0 + - selftests/bpf: skip the timer_lockup test for single-CPU nodes + - ipv6: Fix soft lockups in fib6_select_path under high next hop churn + - net: rfkill: gpio: Add check for clk_enable() + - Revert "wifi: iwlegacy: do not skip frames with bad FCS" + - bpf: Use function pointers count as struct_ops links count + - bpf: Add kernel symbol for struct_ops trampoline + - ALSA: usx2y: Use snd_card_free_when_closed() at disconnection + - ALSA: us122l: Use snd_card_free_when_closed() at disconnection + - ALSA: caiaq: Use snd_card_free_when_closed() at disconnection + - ALSA: 6fire: Release resources at card release + - i2c: dev: Fix memory leak when underlying adapter does not support I2C + - selftests: netfilter: Fix missing return values in conntrack_dump_flush + - Bluetooth: btintel_pcie: Add handshake between driver and firmware + - Bluetooth: btintel: Do no pass vendor events to stack + - Bluetooth: btmtk: adjust the position to init iso data anchor + - Bluetooth: btbcm: fix missing of_node_put() in btbcm_get_board_name() + - Bluetooth: ISO: Use kref to track lifetime of iso_conn + - Bluetooth: ISO: Do not emit LE PA Create Sync if previous is pending + - Bluetooth: ISO: Do not emit LE BIG Create Sync if previous is pending + - Bluetooth: ISO: Send BIG Create Sync via hci_sync + - Bluetooth: fix use-after-free in device_for_each_child() + - xsk: Free skb when TX metadata options are invalid + - erofs: fix file-backed mounts over FUSE + - erofs: fix blksize < PAGE_SIZE for file-backed mounts + - erofs: handle NONHEAD !delta[1] lclusters gracefully + - dlm: fix dlm_recover_members refcount on error + - eth: fbnic: don't disable the PCI device twice + - net: txgbe: remove GPIO interrupt controller + - net: txgbe: fix null pointer to pcs + - netpoll: Use rcu_access_pointer() in netpoll_poll_lock + - wireguard: selftests: load nf_conntrack if not present + - bpf: fix recursive lock when verdict program return SK_PASS + - unicode: Fix utf8_load() error path + - cppc_cpufreq: Use desired perf if feedback ctrs are 0 or unchanged + - RDMA/core: Provide rdma_user_mmap_disassociate() to disassociate mmap pages + - RDMA/hns: Disassociate mmap pages for all uctx when HW is being reset + - pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() + - clk: mediatek: drop two dead config options + - trace/trace_event_perf: remove duplicate samples on the first tracepoint + event + - pinctrl: zynqmp: drop excess struct member description + - pinctrl: renesas: Select PINCTRL_RZG2L for RZ/V2H(P) SoC + - clk: qcom: videocc-sm8550: depend on either gcc-sm8550 or gcc-sm8650 + - iommu/s390: Implement blocking domain + - scsi: hisi_sas: Enable all PHYs that are not disabled by user during + controller reset + - powerpc/vdso: Flag VDSO64 entry points as functions + - mfd: tps65010: Use IRQF_NO_AUTOEN flag in request_irq() to fix race + - mfd: da9052-spi: Change read-mask to write-mask + - mfd: intel_soc_pmic_bxtwc: Use IRQ domain for USB Type-C device + - mfd: intel_soc_pmic_bxtwc: Use IRQ domain for TMU device + - mfd: intel_soc_pmic_bxtwc: Use IRQ domain for PMIC devices + - mfd: intel_soc_pmic_bxtwc: Fix IRQ domain names duplication + - cpufreq: loongson2: Unregister platform_driver on failure + - powerpc/fadump: Refactor and prepare fadump_cma_init for late init + - powerpc/fadump: Move fadump_cma_init to setup_arch() after initmem_init() + - mtd: hyperbus: rpc-if: Add missing MODULE_DEVICE_TABLE + - mtd: rawnand: atmel: Fix possible memory leak + - clk: Allow kunit tests to run without OF_OVERLAY enabled + - powerpc/mm/fault: Fix kfence page fault reporting + - iommu/tegra241-cmdqv: Staticize cmdqv_debugfs_dir + - clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate() + - mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in + RD_ANY_REG_OP + - powerpc/pseries: Fix dtl_access_lock to be a rw_semaphore + - cpufreq: CPPC: Fix possible null-ptr-deref for cpufreq_cpu_get_raw() + - cpufreq: CPPC: Fix possible null-ptr-deref for cppc_get_cpu_cost() + - iommu/amd/pgtbl_v2: Take protection domain lock before invalidating TLB + - RDMA/hns: Fix an AEQE overflow error caused by untimely update of eq_db_ci + - RDMA/hns: Fix flush cqe error when racing with destroy qp + - RDMA/hns: Modify debugfs name + - RDMA/hns: Use dev_* printings in hem code instead of ibdev_* + - RDMA/hns: Fix cpu stuck caused by printings during reset + - RDMA/rxe: Fix the qp flush warnings in req + - RDMA/bnxt_re: Check cqe flags to know imm_data vs inv_irkey + - clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset + - clk: renesas: rzg2l: Fix FOUTPOSTDIV clk + - RDMA/rxe: Set queue pair cur_qp_state when being queried + - RDMA/mlx5: Call dev_put() after the blocking notifier + - RDMA/core: Implement RoCE GID port rescan and export delete function + - RDMA/mlx5: Ensure active slave attachment to the bond IB device + - RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation + - riscv: kvm: Fix out-of-bounds array access + - clk: imx: lpcg-scu: SW workaround for errata (e10858) + - clk: imx: fracn-gppll: correct PLL initialization flow + - clk: imx: fracn-gppll: fix pll power up + - clk: imx: clk-scu: fix clk enable state save and restore + - clk: imx: imx8-acm: Fix return value check in + clk_imx_acm_attach_pm_domains() + - iommu/vt-d: Fix checks and print in dmar_fault_dump_ptes() + - iommu/vt-d: Fix checks and print in pgtable_walk() + - checkpatch: always parse orig_commit in fixes tag + - mfd: rt5033: Fix missing regmap_del_irq_chip() + - leds: max5970: Fix unreleased fwnode_handle in probe function + - leds: ktd2692: Set missing timing properties + - fs/proc/kcore.c: fix coccinelle reported ERROR instances + - scsi: target: Fix incorrect function name in pscsi_create_type_disk() + - scsi: bfa: Fix use-after-free in bfad_im_module_exit() + - scsi: fusion: Remove unused variable 'rc' + - scsi: qedf: Fix a possible memory leak in qedf_alloc_and_init_sb() + - scsi: qedi: Fix a possible memory leak in qedi_alloc_and_init_sb() + - scsi: sg: Enable runtime power management + - x86/tdx: Introduce wrappers to read and write TD metadata + - x86/tdx: Rename tdx_parse_tdinfo() to tdx_setup() + - x86/tdx: Dynamically disable SEPT violations from causing #VEs + - powerpc/fadump: allocate memory for additional parameters early + - fadump: reserve param area if below boot_mem_top + - RDMA/hns: Fix out-of-order issue of requester when setting FENCE + - RDMA/hns: Fix NULL pointer derefernce in hns_roce_map_mr_sg() + - cpufreq: loongson3: Check for error code from devm_mutex_init() call + - cpufreq: CPPC: Fix wrong return value in cppc_get_cpu_cost() + - cpufreq: CPPC: Fix wrong return value in cppc_get_cpu_power() + - kasan: move checks to do_strncpy_from_user + - kunit: skb: use "gfp" variable instead of hardcoding GFP_KERNEL + - ocfs2: fix uninitialized value in ocfs2_file_read_iter() + - zram: ZRAM_DEF_COMP should depend on ZRAM + - iommu/tegra241-cmdqv: Fix alignment failure at max_n_shift + - dax: delete a stale directory pmem + - KVM: PPC: Book3S HV: Stop using vc->dpdes for nested KVM guests + - KVM: PPC: Book3S HV: Avoid returning to nested hypervisor on pending + doorbells + - powerpc/sstep: make emulate_vsx_load and emulate_vsx_store static + - RDMA/hns: Fix different dgids mapping to the same dip_idx + - KVM: PPC: Book3S HV: Fix kmv -> kvm typo + - powerpc/kexec: Fix return of uninitialized variable + - fbdev: sh7760fb: Fix a possible memory leak in sh7760fb_alloc_mem() + - RDMA/mlx5: Move events notifier registration to be after device registration + - clk: clk-apple-nco: Add NULL check in applnco_probe + - clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883 + - clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs + - clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK} configuration + - clk: en7523: move clock_register in hw_init callback + - clk: en7523: introduce chip_scu regmap + - clk: en7523: fix estimation of fixed rate for EN7581 + - dt-bindings: clock: axi-clkgen: include AXI clk + - clk: clk-axi-clkgen: make sure to enable the AXI bus clock + - zram: permit only one post-processing operation at a time + - zram: fix NULL pointer in comp_algorithm_show() + - RDMA/bnxt_re: Correct the sequence of device suspend + - arm64: dts: qcom: sc8180x: Add a SoC-specific compatible to cpufreq-hw + - pinctrl: k210: Undef K210_PC_DEFAULT + - rtla/timerlat: Do not set params->user_workload with -U + - smb: cached directories can be more than root file handle + - mailbox: mtk-cmdq: fix wrong use of sizeof in cmdq_get_clocks() + - mailbox: arm_mhuv2: clean up loop in get_irq_chan_comb() + - x86: fix off-by-one in access_ok() + - perf cs-etm: Don't flush when packet_queue fills up + - gfs2: Rename GLF_VERIFY_EVICT to GLF_VERIFY_DELETE + - gfs2: Allow immediate GLF_VERIFY_DELETE work + - gfs2: Fix unlinked inode cleanup + - perf mem: Fix printing PERF_MEM_LVLNUM_{L2_MHB|MSC} + - dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only + - PCI: Fix reset_method_store() memory leak + - perf jevents: Don't stop at the first matched pmu when searching a events + table + - perf stat: Close cork_fd when create_perf_stat_counter() failed + - perf stat: Fix affinity memory leaks on error path + - perf trace: Keep exited threads for summary + - perf test attr: Add back missing topdown events + - rust: rbtree: fix `SAFETY` comments that should be `# Safety` sections + - f2fs: compress: fix inconsistent update of i_blocks in + release_compress_blocks and reserve_compress_blocks + - f2fs: fix null-ptr-deref in f2fs_submit_page_bio() + - mailbox, remoteproc: k3-m4+: fix compile testing + - f2fs: fix to account dirty data in __get_secs_required() + - perf dso: Fix symtab_type for kmod compression + - perf disasm: Fix capstone memory leak + - perf probe: Fix libdw memory leak + - perf probe: Correct demangled symbols in C++ program + - rust: kernel: fix THIS_MODULE header path in ThisModule doc comment + - rust: macros: fix documentation of the paste! macro + - PCI: cpqphp: Fix PCIBIOS_* return value confusion + - rust: block: fix formatting of `kernel::block::mq::request` module + - perf disasm: Use disasm_line__free() to properly free disasm_line + - perf disasm: Fix not cleaning up disasm_line in symbol__disassemble_raw() + - virtiofs: use pages instead of pointer for kernel direct IO + - perf ftrace latency: Fix unit on histogram first entry when using --use-nsec + - i3c: master: Remove i3c_dev_disable_ibi_locked(olddev) on device hotjoin + - f2fs: fix the wrong f2fs_bug_on condition in f2fs_do_replace_block + - f2fs: check curseg->inited before write_sum_page in change_curseg + - f2fs: Fix not used variable 'index' + - f2fs: fix to avoid potential deadlock in f2fs_record_stop_reason() + - f2fs: fix to avoid use GC_AT when setting gc_mode as GC_URGENT_LOW or + GC_URGENT_MID + - PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is + supported + - PCI: qcom-ep: Move controller cleanups to qcom_pcie_perst_deassert() + - PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert() + - PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds + - perf build: Add missing cflags when building with custom libtraceevent + - f2fs: fix race in concurrent f2fs_stop_gc_thread + - f2fs: fix to map blocks correctly for direct write + - f2fs: fix to avoid forcing direct write to use buffered IO on inline_data + inode + - perf trace: avoid garbage when not printing a trace event's arguments + - m68k: mcfgpio: Fix incorrect register offset for CONFIG_M5441x + - m68k: coldfire/device.c: only build FEC when HW macros are defined + - svcrdma: Address an integer overflow + - nfsd: drop inode parameter from nfsd4_change_attribute() + - perf list: Fix topic and pmu_name argument order + - perf trace: Fix tracing itself, creating feedback loops + - perf trace: Do not lose last events in a race + - perf trace: Avoid garbage when not printing a syscall's arguments + - remoteproc: qcom: pas: Remove subdevs on the error path of adsp_probe() + - remoteproc: qcom: adsp: Remove subdevs on the error path of adsp_probe() + - remoteproc: qcom: pas: add minidump_id to SM8350 resources + - rpmsg: glink: use only lower 16-bits of param2 for CMD_OPEN name length + - remoteproc: qcom_q6v5_mss: Re-order writes to the IMEM region + - PCI: endpoint: epf-mhi: Avoid NULL dereference if DT lacks 'mmio' + - NFSD: Prevent NULL dereference in nfsd4_process_cb_update() + - NFSD: Cap the number of bytes copied by nfs4_reset_recoverydir() + - nfsd: release svc_expkey/svc_export with rcu_work + - svcrdma: fix miss destroy percpu_counter in svc_rdma_proc_init() + - NFSD: Fix nfsd4_shutdown_copy() + - nfs_common: must not hold RCU while calling nfsd_file_put_local + - f2fs: fix to do cast in F2FS_{BLK_TO_BYTES, BTYES_TO_BLK} to avoid overflow + - perf bpf-filter: Return -ENOMEM directly when pfi allocation fails + - hwmon: (tps23861) Fix reporting of negative temperatures + - hwmon: (aquacomputer_d5next) Fix length of speed_input array + - phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in + airoha_pcie_phy_init_clk_out() + - phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in + airoha_pcie_phy_init_csr_2l() + - phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in + airoha_pcie_phy_init_ssc_jcpll() + - phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions + - vdpa/mlx5: Fix suboptimal range on iotlb iteration + - vfio/mlx5: Fix an unwind issue in mlx5vf_add_migration_pages() + - vfio/mlx5: Fix unwind flows in mlx5vf_pci_save/resume_device_data() + - selftests/mount_setattr: Fix failures on 64K PAGE_SIZE kernels + - gpio: zevio: Add missed label initialisation + - vfio/pci: Properly hide first-in-list PCIe extended capability + - fs_parser: update mount_api doc to match function signature + - LoongArch: Fix build failure with GCC 15 (-std=gnu23) + - LoongArch: BPF: Sign-extend return values + - power: supply: core: Remove might_sleep() from power_supply_put() + - power: supply: bq27xxx: Fix registers of bq27426 + - power: supply: rt9471: Fix wrong WDT function regfield declaration + - power: supply: rt9471: Use IC status regfield to report real charger status + - fs/ntfs3: Equivalent transition from page to folio + - power: reset: ep93xx: add AUXILIARY_BUS dependency + - net: usb: lan78xx: Fix double free issue with interrupt buffer allocation + - net: usb: lan78xx: Fix memory leak on device unplug by freeing PHY device + - tg3: Set coherent DMA mask bits to 31 for BCM57766 chipsets + - net: usb: lan78xx: Fix refcounting and autosuspend on invalid WoL + configuration + - net: microchip: vcap: Add typegroup table terminators in kunit tests + - netlink: fix false positive warning in extack during dumps + - exfat: fix file being changed by unaligned direct write + - net/l2tp: fix warning in l2tp_exit_net found by syzbot + - s390/iucv: MSG_PEEK causes memory leak in iucv_sock_destruct() + - rtase: Refactor the rtase_check_mac_version_valid() function + - rtase: Correct the speed for RTL907XD-V1 + - rtase: Corrects error handling of the rtase_check_mac_version_valid() + - net/ipv6: delete temporary address if mngtmpaddr is removed or unmanaged + - net: mdio-ipq4019: add missing error check + - marvell: pxa168_eth: fix call balance of pep->clk handling routines + - net: stmmac: dwmac-socfpga: Set RX watchdog interrupt as broken + - octeontx2-af: RPM: Fix mismatch in lmac type + - octeontx2-af: RPM: Fix low network performance + - octeontx2-af: RPM: fix stale RSFEC counters + - octeontx2-af: RPM: fix stale FCFEC counters + - octeontx2-af: Quiesce traffic before NIX block reset + - spi: atmel-quadspi: Fix register name in verbose logging function + - net: hsr: fix hsr_init_sk() vs network/transport headers. + - bnxt_en: Reserve rings after PCIe AER recovery if NIC interface is down + - bnxt_en: Set backplane link modes correctly for ethtool + - bnxt_en: Fix queue start to update vnic RSS table + - bnxt_en: Fix receive ring space parameters when XDP is active + - bnxt_en: Refactor bnxt_ptp_init() + - bnxt_en: Unregister PTP during PCI shutdown and suspend + - Bluetooth: MGMT: Fix slab-use-after-free Read in set_powered_sync + - Bluetooth: MGMT: Fix possible deadlocks + - llc: Improve setsockopt() handling of malformed user input + - rxrpc: Improve setsockopt() handling of malformed user input + - tcp: Fix use-after-free of nreq in reqsk_timer_handler(). + - ip6mr: fix tables suspicious RCU usage + - ipmr: fix tables suspicious RCU usage + - iio: light: al3010: Fix an error handling path in al3010_probe() + - usb: using mutex lock and supporting O_NONBLOCK flag in iowarrior_read() + - usb: yurex: make waiting on yurex_write interruptible + - USB: chaoskey: fail open after removal + - USB: chaoskey: Fix possible deadlock chaoskey_list_lock + - misc: apds990x: Fix missing pm_runtime_disable() + - devres: Fix page faults when tracing devres from unloaded modules + - usb: gadget: uvc: wake pump everytime we update the free list + - interconnect: qcom: icc-rpmh: probe defer incase of missing QoS clock + dependency + - iio: backend: fix wrong pointer passed to IS_ERR() + - iio: adc: ad4000: fix reading unsigned data + - iio: adc: ad4000: Check for error code from devm_mutex_init() call + - iio: adc: pac1921: Check for error code from devm_mutex_init() call + - iio: accel: adxl380: fix raw sample read + - phy: realtek: usb: fix NULL deref in rtk_usb2phy_probe + - phy: realtek: usb: fix NULL deref in rtk_usb3phy_probe + - counter: stm32-timer-cnt: Add check for clk_enable() + - counter: ti-ecap-capture: Add check for clk_enable() + - bus: mhi: host: Switch trace_mhi_gen_tre fields to native endian + - usb: typec: fix potential array underflow in ucsi_ccg_sync_control() + - firmware_loader: Fix possible resource leak in fw_log_firmware_info() + - ALSA: hda/realtek: Update ALC256 depop procedure + - drm/radeon: Fix spurious unplug event on radeon HDMI + - drm/amd/display: Fix null check for pipe_ctx->plane_state in + dcn20_program_pipe + - drm/amd/display: Fix null check for pipe_ctx->plane_state in hwss_setup_dpp + - ASoC: imx-audmix: Add NULL check in imx_audmix_probe + - drm/xe/ufence: Wake up waiters after setting ufence->signalled + - apparmor: fix 'Do simple duplicate message elimination' + - ALSA: core: Fix possible NULL dereference caused by kunit_kzalloc() + - ASoC: amd: yc: Fix for enabling DMIC on acp6x via _DSD entry + - ASoC: mediatek: Check num_codecs is not zero to avoid panic during probe + - s390/pci: Fix potential double remove of hotplug slot + - f2fs: fix fiemap failure issue when page size is 16KB + - net_sched: sch_fq: don't follow the fast path if Tx is behind now + - xen: Fix the issue of resource not being properly released in + xenbus_dev_probe() + - ALSA: usb-audio: Fix potential out-of-bound accesses for Extigy and Mbox + devices + - ALSA: usb-audio: Fix out of bounds reads when finding clock sources + - usb: ehci-spear: fix call balance of sehci clk handling routines + - usb: typec: ucsi: glink: fix off-by-one in connector_status + - xfs: fix simplify extent lookup in xfs_can_free_eofblocks + - ext4: supress data-race warnings in ext4_free_inodes_{count,set}() + - ext4: fix FS_IOC_GETFSMAP handling + - MAINTAINERS: update location of media main tree + - docs: media: update location of the media patches + - jfs: xattr: check invalid xattr size more strictly + - ASoC: amd: yc: Add a quirk for microfone on Lenovo ThinkPad P14s Gen 5 + 21MES00B00 + - ASoC: codecs: Fix atomicity violation in snd_soc_component_get_drvdata() + - ASoC: da7213: Populate max_register to regmap_config + - perf/x86/intel/pt: Fix buffer full but size is 0 case + - crypto: x86/aegis128 - access 32-bit arguments as 32-bit + - KVM: x86: switch hugepage recovery thread to vhost_task + - KVM: x86/mmu: Skip the "try unsync" path iff the old SPTE was a leaf SPTE + - KVM: x86: add back X86_LOCAL_APIC dependency + - KVM: x86: Break CONFIG_KVM_X86's direct dependency on KVM_INTEL || KVM_AMD + - powerpc/pseries: Fix KVM guest detection for disabling hardlockup detector + - KVM: arm64: vgic-v3: Sanitise guest writes to GICR_INVLPIR + - KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status + - Revert "KVM: VMX: Move LOAD_IA32_PERF_GLOBAL_CTRL errata handling out of + setup_vmcs_config()" + - KVM: arm64: Don't retire aborted MMIO instruction + - KVM: arm64: vgic-its: Clear ITE when DISCARD frees an ITE + - KVM: arm64: Get rid of userspace_irqchip_in_use + - KVM: arm64: vgic-its: Add a data length check in vgic_its_save_* + - KVM: arm64: vgic-its: Clear DTE when MAPD unmaps a device + - Compiler Attributes: disable __counted_by for clang < 19.1.3 + - PCI: Fix use-after-free of slot->bus on hot remove + - LoongArch: Explicitly specify code model in Makefile + - clk: clk-loongson2: Fix memory corruption bug in struct + loongson2_clk_provider + - clk: clk-loongson2: Fix potential buffer overflow in flexible-array member + access + - fsnotify: fix sending inotify event with unexpected filename + - fsnotify: Fix ordering of iput() and watched_objects decrement + - comedi: Flush partial mappings in error case + - apparmor: test: Fix memory leak for aa_unpack_strdup() + - iio: dac: adi-axi-dac: fix wrong register bitfield + - tty: ldsic: fix tty_ldisc_autoload sysctl's proc_handler + - locking/lockdep: Avoid creating new name string literals in + lockdep_set_subclass() + - tools/nolibc: s390: include std.h + - fcntl: make F_DUPFD_QUERY associative + - pinctrl: qcom: spmi: fix debugfs drive strength + - dt-bindings: pinctrl: samsung: Fix interrupt constraint for variants with + fallbacks + - dt-bindings: iio: dac: ad3552r: fix maximum spi speed + - exfat: fix uninit-value in __exfat_get_dentry_set + - exfat: fix out-of-bounds access of directory entries + - xhci: Fix control transfer error on Etron xHCI host + - xhci: Combine two if statements for Etron xHCI host + - xhci: Don't perform Soft Retry for Etron xHCI host + - xhci: Don't issue Reset Device command to Etron xHCI host + - Bluetooth: Fix type of len in rfcomm_sock_getsockopt{,_old}() + - usb: xhci: Limit Stop Endpoint retries + - usb: xhci: Fix TD invalidation under pending Set TR Dequeue + - usb: xhci: Avoid queuing redundant Stop Endpoint commands + - ARM: dts: omap36xx: declare 1GHz OPP as turbo again + - wifi: ath12k: fix warning when unbinding + - wifi: rtlwifi: Drastically reduce the attempts to read efuse in case of + failures + - wifi: nl80211: fix bounds checker error in nl80211_parse_sched_scan + - wifi: ath12k: fix crash when unbinding + - wifi: brcmfmac: release 'root' node in all execution paths + - Revert "fs: don't block i_writecount during exec" + - Revert "f2fs: remove unreachable lazytime mount option parsing" + - Revert "usb: gadget: composite: fix OS descriptors w_value logic" + - serial: sh-sci: Clean sci_ports[0] after at earlycon exit + - Revert "serial: sh-sci: Clean sci_ports[0] after at earlycon exit" + - io_uring: fix corner case forgetting to vunmap + - io_uring: check for overflows in io_pin_pages + - blk-settings: round down io_opt to physical_block_size + - gpio: exar: set value when external pull-up or pull-down is present + - netfilter: ipset: add missing range check in bitmap_ip_uadt + - spi: Fix acpi deferred irq probe + - mtd: spi-nor: core: replace dummy buswidth from addr to data + - cpufreq: mediatek-hw: Fix wrong return value in mtk_cpufreq_get_cpu_power() + - cifs: support mounting with alternate password to allow password rotation + - parisc/ftrace: Fix function graph tracing disablement + - RISC-V: Scalar unaligned access emulated on hotplug CPUs + - RISC-V: Check scalar unaligned access on all CPUs + - ksmbd: fix use-after-free in SMB request handling + - smb: client: fix NULL ptr deref in crypto_aead_setkey() + - platform/chrome: cros_ec_typec: fix missing fwnode reference decrement + - irqchip/irq-mvebu-sei: Move misplaced select() callback to SEI CP domain + - x86/CPU/AMD: Terminate the erratum_1386_microcode array + - ubi: wl: Put source PEB into correct list if trying locking LEB failed + - um: ubd: Do not use drvdata in release + - um: net: Do not use drvdata in release + - dt-bindings: serial: rs485: Fix rs485-rts-delay property + - serial: 8250_fintek: Add support for F81216E + - serial: 8250: omap: Move pm_runtime_get_sync + - serial: amba-pl011: Fix RX stall when DMA is used + - serial: amba-pl011: fix build regression + - Revert "block, bfq: merge bfq_release_process_ref() into + bfq_put_cooperator()" + - mtd: ubi: fix unreleased fwnode_handle in find_volume_fwnode() + - block: Prevent potential deadlock in blk_revalidate_disk_zones() + - um: vector: Do not use drvdata in release + - sh: cpuinfo: Fix a warning for CONFIG_CPUMASK_OFFSTACK + - iio: gts: Fix uninitialized symbol 'ret' + - ublk: fix ublk_ch_mmap() for 64K page size + - arm64: tls: Fix context-switching of tpidrro_el0 when kpti is enabled + - block: fix missing dispatching request when queue is started or unquiesced + - block: fix ordering between checking QUEUE_FLAG_QUIESCED request adding + - block: fix ordering between checking BLK_MQ_S_STOPPED request adding + - blk-mq: Make blk_mq_quiesce_tagset() hold the tag list mutex less long + - gve: Flow steering trigger reset only for timeout error + - HID: wacom: Interpret tilt data from Intuos Pro BT as signed values + - i40e: Fix handling changed priv flags + - media: wl128x: Fix atomicity violation in fmc_send_cmd() + - media: intel/ipu6: do not handle interrupts when device is disabled + - arm64: dts: mediatek: mt8186-corsola-voltorb: Merge speaker codec nodes + - netdev-genl: Hold rcu_read_lock in napi_get + - soc: fsl: cpm1: qmc: Set the ret error code on platform_get_irq() failure + - soc: fsl: rcpm: fix missing of_node_put() in copy_ippdexpcr1_setting() + - media: v4l2-core: v4l2-dv-timings: check cvt/gtf result + - x86/mm: Carve out INVLPG inline asm for use by others + - x86/microcode/AMD: Flush patch buffer mapping after application + - ALSA: rawmidi: Fix kvfree() call in spinlock + - ALSA: ump: Fix evaluation of MIDI 1.0 FB info + - ALSA: pcm: Add sanity NULL check for the default mmap fault handler + - ALSA: hda/realtek: Update ALC225 depop procedure + - ALSA: hda/realtek: Enable speaker pins for Medion E15443 platform + - ALSA: hda/realtek: Set PCBeep to default value for ALC274 + - ALSA: hda/realtek: Fix Internal Speaker and Mic boost of Infinix Y4 Max + - ALSA: hda/realtek: fix mute/micmute LEDs don't work for EliteBook X G1i + - ALSA: hda/realtek: Apply quirk for Medion E15433 + - fs/smb/client: implement chmod() for SMB3 POSIX Extensions + - smb: client: fix use-after-free of signing key + - smb3: request handle caching when caching directories + - smb: client: handle max length for SMB symlinks + - smb: Don't leak cfid when reconnect races with open_cached_dir + - smb: prevent use-after-free due to open_cached_dir error paths + - smb: During unmount, ensure all cached dir instances drop their dentry + - usb: misc: ljca: set small runtime autosuspend delay + - usb: misc: ljca: move usb_autopm_put_interface() after wait for response + - usb: dwc3: ep0: Don't clear ep0 DWC3_EP_TRANSFER_STARTED + - usb: musb: Fix hardware lockup on first Rx endpoint request + - usb: dwc3: gadget: Add missing check for single port RAM in TxFIFO resizing + logic + - usb: dwc3: gadget: Fix checking for number of TRBs left + - usb: dwc3: gadget: Fix looping of queued SG entries + - staging: vchiq_arm: Fix missing refcount decrement in error path for fw_node + - counter: stm32-timer-cnt: fix device_node handling in probe_encoder() + - ublk: fix error code for unsupported command + - lib: string_helpers: silence snprintf() output truncation warning + - f2fs: fix to do sanity check on node blkaddr in truncate_node() + - ipc: fix memleak if msg_init_ns failed in create_ipc_ns + - Input: cs40l50 - fix wrong usage of INIT_WORK() + - NFSD: Prevent a potential integer overflow + - SUNRPC: make sure cache entry active before cache_show + - um: Fix potential integer overflow during physmem setup + - um: Fix the return value of elf_core_copy_task_fpregs + - kfifo: don't include dma-mapping.h in kfifo.h + - um: ubd: Initialize ubd's disk pointer in ubd_add + - um: Always dump trace for specified task in show_stack + - NFSv4.0: Fix a use-after-free problem in the asynchronous open() + - nfs/localio: must clear res.replen in nfs_local_read_done + - rtc: st-lpc: Use IRQF_NO_AUTOEN flag in request_irq() + - rtc: abx80x: Fix WDT bit position of the status register + - rtc: check if __rtc_read_time was successful in rtc_timer_do_work() + - ubi: fastmap: wl: Schedule fm_work if wear-leveling pool is empty + - ubifs: Correct the total block count by deducting journal reservation + - ubi: fastmap: Fix duplicate slab cache names while attaching + - ubifs: authentication: Fix use-after-free in ubifs_tnc_end_commit + - jffs2: fix use of uninitialized variable + - hostfs: Fix the NULL vs IS_ERR() bug for __filemap_get_folio() + - net/9p/usbg: fix handling of the failed kzalloc() memory allocation + - rtc: rzn1: fix BCD to rtc_time conversion errors + - Revert "nfs: don't reuse partially completed requests in + nfs_lock_and_join_requests" + - nvme/multipath: Fix RCU list traversal to use SRCU primitive + - blk-mq: add non_owner variant of start_freeze/unfreeze queue APIs + - block: model freeze & enter queue as lock for supporting lockdep + - block: fix uaf for flush rq while iterating tags + - block: return unsigned int from bdev_io_min + - nvme-fabrics: fix kernel crash while shutting down controller + - 9p/xen: fix init sequence + - 9p/xen: fix release of IRQ + - perf/arm-smmuv3: Fix lockdep assert in ->event_init() + - perf/arm-cmn: Ensure port and device id bits are set properly + - smb: client: disable directory caching when dir_cache_timeout is zero + - x86/Documentation: Update algo in init_size description of boot protocol + - cifs: Fix parsing native symlinks relative to the export + - cifs: Fix parsing reparse point with native symlink in SMB1 non-UNICODE + session + - rtc: ab-eoz9: don't fail temperature reads on undervoltage notification + - Rename .data.unlikely to .data..unlikely + - Rename .data.once to .data..once to fix resetting WARN*_ONCE + - kbuild: deb-pkg: Don't fail if modules.order is missing + - smb: Initialize cfid->tcon before performing network ops + - block: Don't allow an atomic write be truncated in blkdev_write_iter() + - modpost: remove incorrect code in do_eisa_entry() + - cifs: during remount, make sure passwords are in sync + - cifs: unlock on error in smb3_reconfigure() + - nfs: ignore SB_RDONLY when mounting nfs + - sunrpc: clear XPRT_SOCK_UPD_TIMEOUT when reset transport + - SUNRPC: timeout and cancel TLS handshake with -ETIMEDOUT + - sunrpc: fix one UAF issue caused by sunrpc kernel tcp socket + - nfs/blocklayout: Don't attempt unregister for invalid block device + - nfs/blocklayout: Limit repeat device registration on failure + - block, bfq: fix bfqq uaf in bfq_limit_depth() + - brd: decrease the number of allocated pages which discarded + - sh: intc: Fix use-after-free bug in register_intc_controller() + - tools/power turbostat: Fix trailing '\n' parsing + - tools/power turbostat: Fix child's argument forwarding + - block: always verify unfreeze lock on the owner task + - block: don't verify IO lock for freeze/unfreeze in elevator_init_mq() + - Linux 6.12.2 + + * Plucky update: v6.12.1 upstream stable release (LP: #2091624) + - hv_sock: Initializing vsk->trans to NULL to prevent a dangling pointer + - media: uvcvideo: Skip parsing frames of type UVC_VS_UNDEFINED in + uvc_parse_format + - mm/mmap: fix __mmap_region() error handling in rare merge failure case + - Linux 6.12.1 + + * Fix compile warnings (LP: #2089676) + - SAUCE: Revert "UBUNTU: SAUCE: (no-up) Allow filtering of cpufreq drivers" + - SAUCE: r8169: Fix compile warning + + * Intel Be201 Bluetooth hardware error 0x0f on Arrow Lake (LP: #2088151) + - Bluetooth: btintel: Add DSBR support for BlazarIW, BlazarU and GaP + + * python perf module missing in realtime kernel (LP: #2089411) + - [Packaging] linux-tools: Link directories rather than individual files + - [Packaging] linux-tools: Fix python perf library packaging + + * Miscellaneous Ubuntu changes + - [Packaging] Fix source file collection + - [Packaging] Build all packages for linux-unstable + - [Packaging] linux-lib-rust: Fix incorrect package name + - [Packaging] linux-tools: Put libperf-jvmti.so into lib/ + - [Packaging] linux-bpf-dev: Restructure packaging + - [Packaging] linux-bpf-dev: Skip packaging for additional kernel flavors + - [Config] updateconfigs following v6.12.2 stable import + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] linux-bpf-dev: Skip packaging for additional + kernel flavors" + - Revert "UBUNTU: [Packaging] linux-bpf-dev: Restructure packaging" + + -- Paolo Pisati Thu, 12 Dec 2024 17:17:27 +0100 + +linux-unstable (6.12.0-4.4) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-4.4 -proposed tracker (LP: #2089753) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.11.12) + + * Random flickering with Intel i915 (Comet Lake and Kaby Lake) on Linux 6.8+ + (LP: #2086587) + - SAUCE: iommu/intel: disable DMAR for KBL and CML integrated gfx + + * Miscellaneous Ubuntu changes + - [Packaging] avoid arch-specific certificate creation + + * Miscellaneous upstream changes + - Revert "lsm: remove LSM_COUNT and LSM_CONFIG_COUNT" + - Revert "lsm: replace indirect LSM hook calls with static calls" + - Revert "init/main.c: Initialize early LSMs after arch code, static keys and + calls." + + -- Paolo Pisati Wed, 27 Nov 2024 11:50:01 +0100 + +linux-unstable (6.12.0-3.3) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-3.3 -proposed tracker (LP: #2088427) + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.12 rebase + + -- Paolo Pisati Mon, 18 Nov 2024 09:57:30 +0100 + +linux-unstable (6.12.0-2.2) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-2.2 -proposed tracker (LP: #2088046) + + * Miscellaneous Ubuntu changes + - debian.master/dkms-versions: temporarily remove dkmses + + -- Paolo Pisati Wed, 13 Nov 2024 10:59:36 +0100 + +linux-unstable (6.12.0-1.1) plucky; urgency=medium + + * plucky/linux-unstable: 6.12.0-1.1 -proposed tracker (LP: #2087956) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.11.12) + + * OVTI08F4:00: number of CSI2 data lanes 2 is not supported (LP: #2084059) + - SAUCE: media: ipu-bridge: Add support for additional link frequencies + + * [Oracular] Allow overriding Rust tools (LP: #2084693) + - [Packaging] Allow rust overrides + + * Support ov05c10 camera sensor in Intel ipu-bridge (LP: #2081866) + - SAUCE: media: Support ov05c10 camera sensor + + * Lack of UART boot output on rb3gen2 even with earlycon (LP: #2083559) + - [Config] move qcom clk and serial options as builtin + + * Missing Bluetooth device IDs for new Mediatek MT7920/MT7925 (LP: #2078878) + - SAUCE: Bluetooth: btusb: Add USB HW IDs for MT7920/MT7925 + + * Support Qualcomm WCN7851 Dual Bluetooth Adapter 0489:E0F3 (LP: #2081796) + - SAUCE: Bluetooth: btusb: Add one more ID 0x0489:0xe0f3 for Qualcomm WCN785x + + * re-enable Ubuntu FAN in the Noble kernel (LP: #2064508) + - SAUCE: fan: add VXLAN implementation + - SAUCE: fan: Fix NULL pointer dereference + - SAUCE: fan: support vxlan strict length validation + + * update for V3 kernel bits and improved multiple fan slice support + (LP: #1470091) // re-enable Ubuntu FAN in the Noble kernel (LP: #2064508) + - SAUCE: fan: tunnel multiple mapping mode (v3) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.12 and rename to linux-unstable + - [Config] Update annotations after rebase to v6.12-rc4 + - [Packaging] use DEB_ prefix for some variables + - debian.master/dkms-versions: temporarily remove most dkms packages + - [Packaging] Sort build dependencies alphabetically + - [Packaging] Add list of used source files to buildinfo package + - [Packaging] replace $(DROOT) with debian + - [Config] updateconfigs following v6.12-rc7 rebase + - [packaging] garbage collect some invalid/unnecessary flags + + -- Paolo Pisati Tue, 12 Nov 2024 14:56:47 +0100 + +linux-unstable (6.12.0-0.0) plucky; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Thu, 03 Oct 2024 15:00:32 +0300 + +linux (6.11.0-8.8) oracular; urgency=medium + + * oracular/linux: 6.11.0-8.8 -proposed tracker (LP: #2080825) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.08.12) + + * [SRU] Disable CONFIG_TCG_TPM2_HMAC to avoid performance loss after v6.10 + (LP: #2080322) + - [Config] disable CONFIG_TCG_TPM2_HMAC by default + + * Integrated Sensor Hub (ISH) support for Intel Lunar Lake platform + (LP: #2071698) + - Documentation: hid: intel-ish-hid: Add vendor custom firmware loading + - HID: intel-ish-hid: Use CPU generation string in driver_data + - hid: intel-ish-hid: Add support for vendor customized firmware loading + + * Miscellaneous Ubuntu changes + - [Packaging] Purge obsolete upstart files + - [Packaging] tools/hv: don't build/install hv_fcopy_uio_daemon on arm64 + - [Config] Update toolchain versions + - SAUCE: rust: Fix rustc source path for the new rustc packaging + - [Packaging] Don't force bindgen version + - [Config] Re-enable rust support for amd64 + + -- Timo Aaltonen Mon, 16 Sep 2024 15:04:18 +0300 + +linux (6.11.0-7.7) oracular; urgency=medium + + * oracular/linux: 6.11.0-7.7 -proposed tracker (LP: #2079949) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [1/99]: LSM: Infrastructure management of the sock + security + - SAUCE: apparmor4.0.0 [2/99]: LSM: Add the lsmblob data structure. + - SAUCE: apparmor4.0.0 [3/99]: LSM: Use lsmblob in security_audit_rule_match + - SAUCE: apparmor4.0.0 [4/99]: LSM: Call only one hook for audit rules + - SAUCE: apparmor4.0.0 [5/99]: LSM: Add lsmblob_to_secctx hook + - SAUCE: apparmor4.0.0 [6/99]: Audit: maintain an lsmblob in audit_context + - SAUCE: apparmor4.0.0 [7/99]: LSM: Use lsmblob in security_ipc_getsecid + - SAUCE: apparmor4.0.0 [8/99]: Audit: Update shutdown LSM data + - SAUCE: apparmor4.0.0 [9/99]: LSM: Use lsmblob in security_current_getsecid + - SAUCE: apparmor4.0.0 [10/99]: LSM: Use lsmblob in security_inode_getsecid + - SAUCE: apparmor4.0.0 [11/99]: Audit: use an lsmblob in audit_names + - SAUCE: apparmor4.0.0 [12/99]: LSM: Create new security_cred_getlsmblob LSM + hook + - SAUCE: apparmor4.0.0 [13/99]: Audit: Change context data from secid to + lsmblob + - SAUCE: apparmor4.0.0 [14/99]: Netlabel: Use lsmblob for audit data + - SAUCE: apparmor4.0.0 [15/99]: LSM: Ensure the correct LSM context releaser + - SAUCE: apparmor4.0.0 [16/99]: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [17/99]: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [18/99]: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [19/99]: LSM: lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [20/99]: LSM: security_lsmblob_to_secctx module + selection + - SAUCE: apparmor4.0.0 [21/99]: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [22/99]: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [23/99]: Audit: Add record for multiple task security + contexts + - SAUCE: apparmor4.0.0 [24/99]: audit: multiple subject lsm values for + netlabel + - SAUCE: apparmor4.0.0 [25/99]: Audit: Add record for multiple object contexts + - SAUCE: apparmor4.0.0 [26/99]: LSM: Remove unused lsmcontext_init() + - SAUCE: apparmor4.0.0 [27/99]: LSM: Improve logic in security_getprocattr + - SAUCE: apparmor4.0.0 [28/99]: LSM: secctx provider check on release + - SAUCE: apparmor4.0.0 [29/99]: LSM: Single calls in socket_getpeersec hooks + - SAUCE: apparmor4.0.0 [30/99]: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [31/99]: LSM: Identify which LSM handles the context + string + - SAUCE: apparmor4.0.0 [32/99]: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [33/99]: LSM: Add mount opts blob size tracking + - SAUCE: apparmor4.0.0 [34/99]: LSM: allocate mnt_opts blobs instead of module + specific data + - SAUCE: apparmor4.0.0 [35/99]: LSM: Infrastructure management of the key + security blob + - SAUCE: apparmor4.0.0 [36/99]: LSM: Infrastructure management of the mnt_opts + security blob + - SAUCE: apparmor4.0.0 [37/99]: LSM: Remove lsmblob scaffolding + - SAUCE: apparmor4.0.0 [38/99]: LSM: Allow reservation of netlabel + - SAUCE: apparmor4.0.0 [39/99]: LSM: restrict security_cred_getsecid() to a + single LSM + - SAUCE: apparmor4.0.0 [40/99]: Smack: Remove LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [41/99]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [41/99]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [42/99]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [43/99]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [44/99]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [45/99]: af_unix mediation + - SAUCE: apparmor4.0.0 [46/99]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [47/99] fixup inode_set_attr + - SAUCE: apparmor4.0.0 [48/99]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [49/99]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [50/99]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [51/99]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [52/99]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [53/99]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [54/99]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [55/99]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [56/99]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [57/99]: prompt - fix caching + - SAUCE: apparmor4.0.0 [58/99]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [59/99]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [60/99]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [61/99]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [62/99]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [63/99]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [64/93] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [65/99]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [66/99]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [67/99]: userns - make it so special unconfined + profiles can mediate user namespaces + - SAUCE: apparmor4.0.0 [68/99]: add io_uring mediation + - SAUCE: apparmor4.0.0 [69/99]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [70/99]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [71/99]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [72/99]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [73/99]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [74/99]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [75/99]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [76/99]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [77/99]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [78/99]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [79/99]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [80/99]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [81/99]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [82/99]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [83/99]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [84/99]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [85/99]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [86/99]: fixup notify + - SAUCE: apparmor4.0.0 [87/99]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [88/99]: apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [89/99]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0 [90/99]: fix reserved mem for when we save ipv6 + addresses + - SAUCE: apparmor4.0.0 [91/99]: fix address mapping for recvfrom + - SAUCE: apparmor4.0.0 [92/99]: apparmor: add support for 2^24 states to the + dfa state machine. + - SAUCE: apparmor4.0.0 [93/99]: apparmor: advertise to userspace support of + user upcall for file rules. + - SAUCE: apparmor4.0.0 [94/99]: apparmor: allocate xmatch for nullpdf inside + aa_alloc_null + - SAUCE: apparmor4.0.0 [95/99]: apparmor: properly handle cx/px lookup failure + for complain + - SAUCE: apparmor4.0.0 [96/99]: apparmor: fix prompt failing during large down + loads + - SAUCE: apparmor4.0.0 [97/99]: apparmor: fix allow field in notification + - SAUCE: apparmor4.0.0 [98/99]: fix build error with !CONFIG_SECURITY + - SAUCE: apparmor4.0.0 [99/99]: fix build error with in nfs4xdr + + * Intel Lunar Lake / Battlemage enablement (LP: #2076209) + - drm/xe/lnl: Drop force_probe requirement + - drm/xe: Support 'nomodeset' kernel command-line option + - drm/i915/display: Plane capability for 64k phys alignment + - drm/xe: Align all VRAM scanout buffers to 64k physical pages when needed. + - drm/xe: Use separate rpm lockdep map for non-d3cold-capable devices + - drm/xe: Fix NPD in ggtt_node_remove() + - drm/xe/bmg: Drop force_probe requirement + - drm/xe/gsc: Fix FW status if the firmware is already loaded + - drm/xe/gsc: Track the platform in the compatibility version + - drm/xe/gsc: Wedge the device if the GSCCS reset fails + - drm/i915/bios: Update new entries in VBT BDB block definitions + - drm/xe/hwmon: Treat hwmon as a per-device concept + - drm/xe: s/xe_tile_migrate_engine/xe_tile_migrate_exec_queue + - drm/xe: Add xe_vm_pgtable_update_op to xe_vma_ops + - drm/xe: Add xe_exec_queue_last_fence_test_dep + - drm/xe: Add timeout to preempt fences + - drm/xe: Convert multiple bind ops into single job + - drm/xe: Update VM trace events + - drm/xe: Update PT layer with better error handling + - drm/xe: Add VM bind IOCTL error injection + - dma-buf: Split out dma fence array create into alloc and arm functions + - drm/xe: Invalidate media_gt TLBs in PT code + - drm/i915/display: Fix BMG CCS modifiers + - drm/xe: Use xe_pm_runtime_get in xe_bo_move() if reclaim-safe. + - drm/xe: Remove extra dma_fence_put on xe_sync_entry_add_deps failure + + * [24.10 FEAT] [KRN1911] Vertical CPU Polarization Support Stage 2 + (LP: #2072760) + - s390/wti: Introduce infrastructure for warning track interrupt + - s390/wti: Prepare graceful CPU pre-emption on wti reception + - s390/wti: Add wti accounting for missed grace periods + - s390/wti: Add debugfs file to display missed grace periods per cpu + - s390/topology: Add sysctl handler for polarization + - s390/topology: Add config option to switch to vertical during boot + - s390/smp: Add cpu capacities + - s390/hiperdispatch: Introduce hiperdispatch + - s390/hiperdispatch: Add steal time averaging + - s390/hiperdispatch: Add trace events + - s390/hiperdispatch: Add hiperdispatch sysctl interface + - s390/hiperdispatch: Add hiperdispatch debug attributes + - s390/hiperdispatch: Add hiperdispatch debug counters + - [Config] Initial set of new options HIPERDISPATCH_ON and + SCHED_TOPOLOGY_VERTICAL to yes for s390x + + * Remove non-LPAE kernel flavor (LP: #2025265) + - [Packaging] Drop control.d/vars.generic-lpae + + * generate and ship vmlinux.h to allow packages to build BPF CO-RE + (LP: #2050083) + - [Packaging] Don't call dh_all on linux-bpf-dev unless on master kernel + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.11-rc7 rebase + + -- Timo Aaltonen Mon, 09 Sep 2024 13:38:09 +0300 + +linux (6.11.0-6.6) oracular; urgency=medium + + * oracular/linux: 6.11.0-6.6 -proposed tracker (LP: #2077949) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.08.12) + - [Packaging] update Ubuntu.md + + * Pull in latest X13s commits (LP: #2078929) + - arm64: dts: qcom: sc8280xp-x13s: disable PCIe perst pull downs + - arm64: dts: qcom: sc8280xp-x13s: clean up PCIe2a pinctrl node + - media: qcom: camss: Remove use_count guard in stop_streaming + - media: qcom: camss: Fix ordering of pm_runtime_enable + - arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor + - wifi: ath11k: fix NULL pointer dereference in ath11k_mac_get_eirp_power() + - Revert "wifi: ath11k: restore country code during resume" + - Revert "wifi: ath11k: support hibernation" + - SAUCE: media: ov5675: Fix power on/off delay timings + - SAUCE: media: dt-bindings: Document SC8280XP/SM8350 Venus + - SAUCE: media: venus: core: Remove trailing commas from of match entries + - SAUCE: media: venus: hfi_venus: Support only updating certain bits with + presets + - SAUCE: media: platform: venus: Add optional LLCC path + - SAUCE: media: venus: core: Add SM8350 resource struct + - SAUCE: media: venus: core: Add SC8280XP resource struct + - SAUCE: arm64: dts: qcom: sc8280xp: Add Venus + - SAUCE: arm64: dts: qcom: sc8280xp-x13s: Enable Venus + - SAUCE: phy: qcom-qmp-combo: drop regulator loads + - SAUCE: phy: qcom-edp: drop regulator loads + - SAUCE: i2c: qcom-cci: Stop complaining about DT set clock rate + - SAUCE: clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs + + * Intel Lunar Lake / Battlemage enablement (LP: #2076209) + - drm/i915: Skip programming FIA link enable bits for MTL+ + - drm/i915: disable fbc due to Wa_16023588340 + - drm/xe/xe2lpm: Extend Wa_16021639441 + - drm/i915/display: Cache adpative sync caps to use it later + - drm/xe: Generate oob before compiling anything + - drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock + - drm/xe/gsc: add Battlemage support + - drm/xe/migrate: Handle clear ccs logic for xe2 dgfx + - drm/xe/migrate: Add helper function to program identity map + - drm/xe/xe2: Introduce identity map for compressed pat for vram + - drm/xe/xe_migrate: Handle migration logic for xe2+ dgfx + - drm/xe/fbdev: Limit the usage of stolen for LNL+ + - drm/xe/uapi: Expose SIMD16 EU mask in topology query + - drm/xe: Fix warning on unreachable statement + - drm/i915/hdcp: Add encoder check in intel_hdcp_get_capability + - drm/i915/hdcp: Add encoder check in hdcp2_get_capability + - drm/xe/hdcp: Check GSC structure validity + - drm/i915/dp: Clear VSC SDP during post ddi disable routine + - drm/xe/huc: Define HuC binary for LNL + - drm/xe/gsc: Define GSC binary for LNL + - drm/xe/huc: Define HuC binary for BMG + - drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG + - drm/i915/display/dp: Compute AS SDP when vrr is also enabled + - drm/xe: Move and export xe_hw_engine lookup. + - drm/xe/xe2: Enable Priority Mem Read + - drm/xe/xe2: Introduce performance changes + - drm/xe/xe2: Add performance turning changes + - drm/xe/guc: Bump minimum required GuC version to v70.29.2 + - drm/xe/guc: Define GuC version v70.29.2 for BMG + - drm/xe/guc: Enable w/a 14022293748 and 22019794406 + - drm/xe: Move enable host l2 VRAM post MCR init + - drm/xe: Write all slices if its mcr register + - drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register + - drm/i915/pps: Disable DPLS_GATING around pps sequence + - drm/xe: fix engine_class bounds check again + - drm/xe/uc: Use managed bo for HuC and GSC objects + - drm/xe: Use reserved copy engine for user binds on faulting devices + - drm/xe/display: Match i915 driver suspend/resume sequences better + - drm/i915: move rawclk from runtime to display runtime info + - drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO() + - drm/i915/psr: Prevent Panel Replay if CRC calculation is enabled + - drm/i915/display: Don't enable decompression on Xe2 with Tile4 + - drm/fourcc: define Intel Xe2 related tile4 ccs modifiers + - drm/i915/display: allow creation of Xe2 ccs framebuffers + - drm/xe/display: fix compat IS_DISPLAY_STEP() range end + - drm/xe/display: remove intel_display_step_name() to simplify + - drm/xe/display: remove the unused compat HAS_GMD_ID() + - drm/xe/step: define more steppings E-J + - drm/i915/display: rename IS_DISPLAY_IP_RANGE() to IS_DISPLAY_VER_FULL() + - drm/i915/display: rename IS_DISPLAY_IP_STEP() to IS_DISPLAY_VER_STEP() + - drm/i915/display: identify display steppings in display probe + - drm/i915/display: switch to display detected steppings + - drm/i915: remove display stepping handling + - drm/xe: remove display stepping handling + - drm/xe: Removed unused xe_ggtt_printk + - drm/xe: Introduce GGTT documentation + - drm/xe: Remove unnecessary drm_mm.h includes + - drm/{i915, xe}: Avoid direct inspection of dpt_vma from outside dpt + - drm/xe: Encapsulate drm_mm_node inside xe_ggtt_node + - drm/xe: Rename xe_ggtt_node related functions + - drm/xe: Limit drm_mm_node_allocated access to xe_ggtt_node + - drm/xe: Introduce xe_ggtt_largest_hole + - drm/xe: Introduce xe_ggtt_print_holes + - drm/xe: Refactor xe_ggtt balloon functions to make the node clear + - drm/xe: Make xe_ggtt_node struct independent + - drm/xe: Fix missing runtime outer protection for ggtt_remove_node + - drm/xe: Move ggtt_fini to devm managed + - drm/xe: Set firmware state to loadable before registering guc_fini_hw + - drm/xe: Drop warn on xe_guc_pc_gucrc_disable in guc pc fini + - drm/xe: Move hw_engine_fini to devm managed + - drm/xe: Update xe_sa to use xe_managed_bo_create_pin_map + - drm/xe: Suspend/resume user access only during system s/r + - drm/xe: Handle polling only for system s/r in xe_display_pm_suspend/resume() + - drm/xe/display: handle HPD polling in display runtime suspend/resume + - drm/xe: Fix total initialization in xe_ggtt_print_holes() + + * Missing device ID for amd_atl for AMD platforms Kraken and Strix-Halo + (LP: #2077922) + - x86/amd_nb: Add new PCI IDs for AMD family 1Ah model 60h + - x86/amd_nb: Add new PCI IDs for AMD family 1Ah model 60h-70h + + * generate and ship vmlinux.h to allow packages to build BPF CO-RE + (LP: #2050083) + - [Packaging] add linux-bpf-dev package + - [Packaging] do not attempt to generate BTF header on armhf + + * Fix ethernet performance on JSL and EHL (LP: #2077858) + - intel_idle: Disable promotion to C1E on Jasper Lake and Elkhart Lake + + * Regression: unable to reach low idle states on Tiger Lake (LP: #2072679) + - SAUCE: PCI: ASPM: Allow OS to configure ASPM where BIOS is incapable of + - SAUCE: PCI: vmd: Let OS control ASPM for devices under VMD domain + + * Random flickering with Intel i915 (Gen9 GPUs in 6th-8th gen CPUs) on Linux + 6.8 (LP: #2062951) + - SAUCE: iommu/intel: disable DMAR for SKL integrated gfx + + * Make linux-tools-common Provide linux-cpupower (LP: #1960841) + - [Packaging] Add linux-cpupower to linux-tools-common Provides + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0: fix build error with !CONFIG_SECURITY + - [Config] updateconfigs following v6.11-rc6 rebase + - SAUCE: apparmor4.0.0: fix build after rebase to v6.11-rc6 + - [Packaging] perf: reenable libtraceevent + + -- Timo Aaltonen Wed, 04 Sep 2024 17:12:57 +0300 + +linux (6.11.0-5.5) oracular; urgency=medium + + * oracular/linux: 6.11.0-5.5 -proposed tracker (LP: #2077454) + + * GDS force mitigation re-enabled in 6.10 (and 6.11) causing crashes + (LP: #2077145) + - [Config] Force disable CONFIG_MITIGATION_GDS_FORCE again + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.11-rc5 rebase + + -- Timo Aaltonen Mon, 26 Aug 2024 17:11:19 +0300 + +linux (6.11.0-4.4) oracular; urgency=medium + + * oracular/linux: 6.11.0-4.4 -proposed tracker (LP: #2077394) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + + * Miscellaneous Ubuntu changes + - [Config] Disable CONFIG_DRM_I915_REPLAY_GPU_HANGS_API + - [Packaging] carry ELF_PACKAGE_METADATA into relinking + - [Packaging] Rename to linux + + -- Timo Aaltonen Tue, 20 Aug 2024 12:07:08 +0300 + +linux (6.11.0-3.3) oracular; urgency=medium + + * dummy entry + + -- Timo Aaltonen Tue, 20 Aug 2024 10:30:29 +0300 + +linux-unstable (6.11.0-3.3) oracular; urgency=medium + + * oracular/linux-unstable: 6.11.0-3.3 -proposed tracker (LP: #2077292) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.08.12) + + * Disable PCI_DYNAMIC_OF_NODES in Ubuntu (LP: #2074376) + - [Config] Disable PCI_DYNAMIC_OF_NODES + + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v6.11-rc3 rebase + + -- Timo Aaltonen Mon, 19 Aug 2024 11:49:32 +0300 + +linux-unstable (6.11.0-2.2) oracular; urgency=medium + + * oracular/linux-unstable: 6.11.0-2.2 -proposed tracker (LP: #2076564) + + * please help enable more EROFS compression algorithms (LP: #2074049) + - [Config] enable LZMA and ZSTD file compressions in EROFS + + * Enable CONFIG_EXFAT_FS in s390x too (LP: #2076428) + - [Config] Enable EXFAT_FS on s390x too + + * Miscellaneous Ubuntu changes + - [Packaging] Disable tools/perf on armhf (FTBFS) + - [Config] toolchain version update + + * Miscellaneous Ubuntu changes + - UBUNTU: Rebase on v6.11-rc3 + + -- Timo Aaltonen Mon, 12 Aug 2024 14:07:05 +0300 + +linux-unstable (6.11.0-1.1) oracular; urgency=medium + + * oracular/linux-unstable: 6.11.0-1.1 -proposed tracker (LP: #2076116) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.11 and rename to linux-unstable + - [Config] updateconfigs following v6.11-rc2 rebase + - SAUCE: hwmon: Fix aaeon driver for 6.11. + - debian.master/dkms-versions: temporarily remove all dkms + + -- Timo Aaltonen Mon, 05 Aug 2024 20:10:11 +0300 + +linux-unstable (6.11.0-0.0) oracular; urgency=medium + + * Dummy entry. + + -- Timo Aaltonen Wed, 31 Jul 2024 16:41:50 +0300 + +linux (6.10.0-18.18) oracular; urgency=medium + + * oracular/linux: 6.10.0-18.18 -proposed tracker (LP: #2073754) + + * net:fib_rule_tests.sh in ubuntu_kselftests_net fails on Noble (LP: #2066332) + - Revert "UBUNTU: SAUCE: selftests: net: fix "from" match test in + fib_rule_tests.sh" + + * Pull-request to address TPM bypass issue (LP: #2037688) + - [Config]: Configure TPM drivers as builtins for arm64 in annotations + + * kdump doesn't work with UEFI secure boot and kernel lockdown enabled on + ARM64 (LP: #2033007) + - [Config]: Enable CONFIG_KEXEC_IMAGE_VERIFY_SIG on arm64 + + * Miscellaneous Ubuntu changes + - SAUCE: s390/setup: Fix __pa/__va for modules under non-GPL licenses + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] debian.master/dkms-versions -- disable zfs for + s390x" + + -- Paolo Pisati Mon, 22 Jul 2024 13:43:47 +0200 + +linux (6.10.0-17.17) oracular; urgency=medium + + * oracular/linux: 6.10.0-17.17 -proposed tracker (LP: #2073091) + + * Miscellaneous Ubuntu changes + - rebase on v6.10 + + -- Paolo Pisati Mon, 15 Jul 2024 10:29:49 +0200 + +linux (6.10.0-16.16) oracular; urgency=medium + + * oracular/linux: 6.10.0-16.16 -proposed tracker (LP: #2072507) + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc7 + + -- Paolo Pisati Mon, 08 Jul 2024 17:52:01 +0200 + +linux (6.10.0-15.15) oracular; urgency=medium + + * oracular/linux: 6.10.0-15.15 -proposed tracker (LP: #2071915) + + * [UBUNTU 24.04] IOMMU DMA mode changed in kernel config causes massive + throughput degradation for PCI-related network workloads (LP: #2071471) + - [Config] Set IOMMU_DEFAULT_DMA_STRICT=n and IOMMU_DEFAULT_DMA_LAZY=yes for + s390x + + * Miscellaneous Ubuntu changes + - rename to linux + + -- Paolo Pisati Thu, 04 Jul 2024 12:12:06 +0200 + +linux-unstable (6.10.0-14.14) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-14.14 -proposed tracker (LP: #2071786) + + * zfs-dkms FTBFS on Linux 6.10/s390x (LP: #2071774) + - [Packaging] debian.master/dkms-versions -- disable zfs for s390x + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.06.11) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [42/92]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [42/92]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [43/92]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [44/92]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [45/92]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [46/92]: af_unix mediation + - SAUCE: apparmor4.0.0 [47/92]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/92]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/92]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/92]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/92]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/92]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/92]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/92]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/92]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/92]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/92]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/92]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/92]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/92]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/92]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/92]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/92]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/93] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/92]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/92]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/92]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/92]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/92]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/92]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/92]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/92]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/92]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/92]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/92]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/92]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/92]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/92]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/92]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/92]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/92]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/92]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/92]: fixup notify + - SAUCE: apparmor4.0.0 [88/92]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [89/92]: apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [90/92]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0 [91/92]: fix reserved mem for when we save ipv6 + addresses + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * linux-gcp 6.8.0-1005.5 (+ others) Noble kernel regression with new apparmor + profiles/features (LP: #2061851) + - SAUCE: apparmor4.0.0 [92/92]: fix address mapping for recvfrom + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/92]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/92]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/92]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0 [1/92]: LSM: Infrastructure management of the sock + security + - SAUCE: apparmor4.0.0 [2/92]: LSM: Add the lsmblob data structure. + - SAUCE: apparmor4.0.0 [3/92]: LSM: Use lsmblob in security_audit_rule_match + - SAUCE: apparmor4.0.0 [4/92]: LSM: Call only one hook for audit rules + - SAUCE: apparmor4.0.0 [5/92]: LSM: Add lsmblob_to_secctx hook + - SAUCE: apparmor4.0.0 [6/92]: Audit: maintain an lsmblob in audit_context + - SAUCE: apparmor4.0.0 [7/92]: LSM: Use lsmblob in security_ipc_getsecid + - SAUCE: apparmor4.0.0 [8/92]: Audit: Update shutdown LSM data + - SAUCE: apparmor4.0.0 [9/92]: LSM: Use lsmblob in security_current_getsecid + - SAUCE: apparmor4.0.0 [10/92]: LSM: Use lsmblob in security_inode_getsecid + - SAUCE: apparmor4.0.0 [11/92]: Audit: use an lsmblob in audit_names + - SAUCE: apparmor4.0.0 [12/92]: LSM: Create new security_cred_getlsmblob LSM + hook + - SAUCE: apparmor4.0.0 [13/92]: Audit: Change context data from secid to + lsmblob + - SAUCE: apparmor4.0.0 [14/92]: Netlabel: Use lsmblob for audit data + - SAUCE: apparmor4.0.0 [15/92]: LSM: Ensure the correct LSM context releaser + - SAUCE: apparmor4.0.0 [16/92]: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [17/92]: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [18/92]: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [19/92]: LSM: lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [20/92]: LSM: security_lsmblob_to_secctx module + selection + - SAUCE: apparmor4.0.0 [21/92]: Audit: Create audit_stamp structure + - SAUCE: apparmor4.0.0 [22/92]: Audit: Allow multiple records in an + audit_buffer + - SAUCE: apparmor4.0.0 [23/92]: Audit: Add record for multiple task security + contexts + - SAUCE: apparmor4.0.0 [24/92]: audit: multiple subject lsm values for + netlabel + - SAUCE: apparmor4.0.0 [25/92]: Audit: Add record for multiple object contexts + - SAUCE: apparmor4.0.0 [26/92]: LSM: Remove unused lsmcontext_init() + - SAUCE: apparmor4.0.0 [27/92]: LSM: Improve logic in security_getprocattr + - SAUCE: apparmor4.0.0 [28/92]: LSM: secctx provider check on release + - SAUCE: apparmor4.0.0 [29/92]: LSM: Single calls in socket_getpeersec hooks + - SAUCE: apparmor4.0.0 [30/92]: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [31/92]: LSM: Identify which LSM handles the context + string + - SAUCE: apparmor4.0.0 [32/92]: AppArmor: Remove the exclusive flag + - SAUCE: apparmor4.0.0 [33/92]: LSM: Add mount opts blob size tracking + - SAUCE: apparmor4.0.0 [34/92]: LSM: allocate mnt_opts blobs instead of module + specific data + - SAUCE: apparmor4.0.0 [35/92]: LSM: Infrastructure management of the key + security blob + - SAUCE: apparmor4.0.0 [36/92]: LSM: Infrastructure management of the mnt_opts + security blob + - SAUCE: apparmor4.0.0 [37/92]: LSM: Remove lsmblob scaffolding + - SAUCE: apparmor4.0.0 [38/92]: LSM: Allow reservation of netlabel + - SAUCE: apparmor4.0.0 [39/92]: LSM: Correct handling of ENOSYS in + inode_setxattr + - SAUCE: apparmor4.0.0 [40/92]: LSM: restrict security_cred_getsecid() to a + single LSM + - SAUCE: apparmor4.0.0 [41/92]: Smack: Remove LSM_FLAG_EXCLUSIVE + + * Miscellaneous upstream changes + - fixup inode_set_attr + + -- Paolo Pisati Wed, 03 Jul 2024 11:23:40 +0200 + +linux-unstable (6.10.0-13.13) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-13.13 -proposed tracker (LP: #2071598) + + * Miscellaneous Ubuntu changes + - zfs FTBFS on s390x - temporarily disable it + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc6 + + -- Paolo Pisati Mon, 01 Jul 2024 11:57:44 +0200 + +linux-unstable (6.10.0-12.12) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-12.12 -proposed tracker (LP: #2071461) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.06.11) + + * noble:linux: ADT ubuntu-regression-suite misses fakeroot dependency + (LP: #2070042) + - [DEP-8] Add missing fakeroot dependency + + * Add Real-time Linux Analysis tool (rtla) to linux-tools (LP: #2059080) + - [Packaging] add Real-time Linux Analysis tool (rtla) to linux-tools + - [Packaging] update dependencies for rtla + + * failed to enable IPU6 camera sensor on kernel >= 6.8: ivsc_ace + intel_vsc-5db76cf6-0a68-4ed6-9b78-0361635e2447: switch camera to host + failed: -110 (LP: #2067364) + - SAUCE: media: ivsc: csi: don't count privacy on as error + - SAUCE: media: ivsc: csi: add separate lock for v4l2 control handler + - SAUCE: media: ivsc: csi: remove privacy status in struct mei_csi + - SAUCE: mei: vsc: Enhance IVSC chipset stability during warm reboot + - SAUCE: mei: vsc: Enhance SPI transfer of IVSC rom + - SAUCE: mei: vsc: Utilize the appropriate byte order swap function + - SAUCE: mei: vsc: Prevent timeout error with added delay post-firmware + download + + * Miscellaneous Ubuntu changes + - SAUCE: nvme-tcp: Do not terminate commands when in RESETTING + - SAUCE: nvme-tcp: make 'err_work' a delayed work + - SAUCE: nvme-tcp: delay error recovery until the next KATO interval + - SAUCE: nvme-tcp: add recovery_delay to sysfs + - [Packaging] rtla: workaround the empty LD variable + - [Packaging] Check do_lib_rust before linking Rust lib files + - [Config] toolchain version update + + -- Paolo Pisati Fri, 28 Jun 2024 15:37:27 +0200 + +linux-unstable (6.10.0-11.11) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-11.11 -proposed tracker (LP: #2070368) + + * Provide python perf module (LP: #2051560) + - [Packaging] enable perf python module + - [Packaging] provide a wrapper module for python-perf + + * Miscellaneous Ubuntu changes + - [Config] toolchain version update + - [Packaging] Fix python3-setuptools build-dep for tools/perf + + -- Paolo Pisati Tue, 25 Jun 2024 14:53:52 +0200 + +linux-unstable (6.10.0-10.10) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-10.10 -proposed tracker (LP: #2070030) + + * Miscellaneous Ubuntu changes + - [Config] arm64: disable RELR + - [Config] updateconfigs following v6.10-rc5 rebase + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc5 + + -- Paolo Pisati Mon, 24 Jun 2024 10:57:14 +0200 + +linux-unstable (6.10.0-7.7) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-7.7 -proposed tracker (LP: #2069713) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.06.11) + + * Miscellaneous Ubuntu changes + - SAUCE: Revert "mm: remove follow_pfn" + - [Packaging] debian.master/dkms-versions -- remove zfs-linux + + -- Paolo Pisati Tue, 18 Jun 2024 12:13:02 +0200 + +linux-unstable (6.10.0-6.6) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-6.6 -proposed tracker (LP: #2069590) + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc4 + - [Config] updateconfigs following v6.10-rc4 rebase + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc4 + + -- Paolo Pisati Mon, 17 Jun 2024 11:02:49 +0200 + +linux-unstable (6.10.0-5.5) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-5.5 -proposed tracker (LP: #2069031) + + * Miscellaneous Ubuntu changes + - [packaging] remove the kernel configuration for perf + - [Packaging] dkms-build: Support DEB822 sources + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc3 + + -- Paolo Pisati Tue, 11 Jun 2024 12:42:10 +0200 + +linux-unstable (6.10.0-4.4) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-4.4 -proposed tracker (LP: #2067887) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc2 + + -- Paolo Pisati Mon, 03 Jun 2024 11:52:09 +0200 + +linux-unstable (6.10.0-3.3) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-3.3 -proposed tracker (LP: #2067718) + + * Miscellaneous Ubuntu changes + - SAUCE: [packaging] `make scripts_gdb` target is broken upstream, to avoid a + FTBFS, do not try to install GDB_SCRIPTS + + -- Paolo Pisati Fri, 31 May 2024 13:17:14 +0200 + +linux-unstable (6.10.0-2.2) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-2.2 -proposed tracker (LP: #2067473) + + * Miscellaneous Ubuntu changes + - SAUCE: update hv_fcopy_daemon target to hv_fcopy_uio_daemon (following + upstream rename) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] update dependencies for rtla" + - Revert "UBUNTU: [Packaging] add Real-time Linux Analysis tool (rtla) to + linux-tools" + - Revert "UBUNTU: [Packaging] provide a wrapper module for python-perf" + - Revert "UBUNTU: [Packaging] enable perf python module" + + -- Paolo Pisati Wed, 29 May 2024 14:08:53 +0200 + +linux-unstable (6.10.0-1.1) oracular; urgency=medium + + * oracular/linux-unstable: 6.10.0-1.1 -proposed tracker (LP: #2067390) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.10 and rename to linux-unstable + - [Config] updateconfigs following v6.10-rc1 rebase + - SAUCE: (lockdown) security: use default hook return value + - debian.master/dkms-versions: temporarily remove all dkms + + * Miscellaneous Ubuntu changes + - rebase on v6.10-rc1 + + -- Paolo Pisati Tue, 28 May 2024 17:57:38 +0200 + +linux-unstable (6.10.0-0.0) oracular; urgency=medium + + * noble/linux: 6.8.0-34.34 -proposed tracker (LP: #2065167) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/2024.04.29) + + -- Roxana Nicolescu Wed, 08 May 2024 13:14:41 +0200 + +linux (6.8.0-32.32) noble; urgency=medium + + * noble/linux: 6.8.0-32.32 -proposed tracker (LP: #2064344) + + * Packaging resync (LP: #1786013) + - [Packaging] drop getabis data + - [Packaging] update variants + - [Packaging] update annotations scripts + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/2024.04.29) + + * Enable Nezha board (LP: #1975592) + - [Config] Enable CONFIG_REGULATOR_FIXED_VOLTAGE on riscv64 + + * Enable Nezha board (LP: #1975592) // Enable StarFive VisionFive 2 board + (LP: #2013232) + - [Config] Enable CONFIG_SERIAL_8250_DW on riscv64 + + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] Sync riscv64 config with other architectures + + * obsolete out-of-tree ivsc dkms in favor of in-tree one (LP: #2061747) + - ACPI: scan: Defer enumeration of devices with a _DEP pointing to IVSC device + - Revert "mei: vsc: Call wake_up() in the threaded IRQ handler" + - mei: vsc: Unregister interrupt handler for system suspend + - media: ipu-bridge: Add ov01a10 in Dell XPS 9315 + - SAUCE: media: ipu-bridge: Support more sensors + + * Fix after-suspend-mediacard/sdhc-insert test failed (LP: #2042500) + - PCI/ASPM: Move pci_configure_ltr() to aspm.c + - PCI/ASPM: Always build aspm.c + - PCI/ASPM: Move pci_save_ltr_state() to aspm.c + - PCI/ASPM: Save L1 PM Substates Capability for suspend/resume + - PCI/ASPM: Call pci_save_ltr_state() from pci_save_pcie_state() + - PCI/ASPM: Disable L1 before configuring L1 Substates + - PCI/ASPM: Update save_state when configuration changes + + * RTL8852BE fw security fail then lost WIFI function during suspend/resume + cycle (LP: #2063096) + - wifi: rtw89: download firmware with five times retry + + * intel_rapl_common: Add support for ARL and LNL (LP: #2061953) + - powercap: intel_rapl: Add support for Lunar Lake-M paltform + - powercap: intel_rapl: Add support for Arrow Lake + + * Kernel panic during checkbox stress_ng_test on Grace running noble 6.8 + (arm64+largemem) kernel (LP: #2058557) + - aio: Fix null ptr deref in aio_complete() wakeup + + * Avoid creating non-working backlight sysfs knob from ASUS board + (LP: #2060422) + - platform/x86: asus-wmi: Consider device is absent when the read is ~0 + + * Include cifs.ko in linux-modules package (LP: #2042546) + - [Packaging] Replace fs/cifs with fs/smb/client in inclusion list + + * Add Real-time Linux Analysis tool (rtla) to linux-tools (LP: #2059080) + - SAUCE: rtla: fix deb build + - [Packaging] add Real-time Linux Analysis tool (rtla) to linux-tools + - [Packaging] update dependencies for rtla + + * Noble update: v6.8.4 upstream stable release (LP: #2060533) + - Revert "workqueue: Shorten events_freezable_power_efficient name" + - Revert "workqueue: Don't call cpumask_test_cpu() with -1 CPU in + wq_update_node_max_active()" + - Revert "workqueue: Implement system-wide nr_active enforcement for unbound + workqueues" + - Revert "workqueue: Introduce struct wq_node_nr_active" + - Revert "workqueue: RCU protect wq->dfl_pwq and implement accessors for it" + - Revert "workqueue: Make wq_adjust_max_active() round-robin pwqs while + activating" + - Revert "workqueue: Move nr_active handling into helpers" + - Revert "workqueue: Replace pwq_activate_inactive_work() with + [__]pwq_activate_work()" + - Revert "workqueue: Factor out pwq_is_empty()" + - Revert "workqueue: Move pwq->max_active to wq->max_active" + - Revert "workqueue.c: Increase workqueue name length" + - Linux 6.8.4 + + * Noble update: v6.8.3 upstream stable release (LP: #2060531) + - drm/vmwgfx: Unmap the surface before resetting it on a plane state + - wifi: brcmfmac: Fix use-after-free bug in brcmf_cfg80211_detach + - wifi: brcmfmac: avoid invalid list operation when vendor attach fails + - media: staging: ipu3-imgu: Set fields before media_entity_pads_init() + - arm64: dts: qcom: sc7280: Add additional MSI interrupts + - remoteproc: virtio: Fix wdg cannot recovery remote processor + - clk: qcom: gcc-sdm845: Add soft dependency on rpmhpd + - smack: Set SMACK64TRANSMUTE only for dirs in smack_inode_setxattr() + - smack: Handle SMACK64TRANSMUTE in smack_inode_setsecurity() + - arm: dts: marvell: Fix maxium->maxim typo in brownstone dts + - drm/vmwgfx: Fix possible null pointer derefence with invalid contexts + - arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphones + - serial: max310x: fix NULL pointer dereference in I2C instantiation + - drm/vmwgfx: Fix the lifetime of the bo cursor memory + - pci_iounmap(): Fix MMIO mapping leak + - media: xc4000: Fix atomicity violation in xc4000_get_frequency + - media: mc: Add local pad to pipeline regardless of the link state + - media: mc: Fix flags handling when creating pad links + - media: nxp: imx8-isi: Check whether crossbar pad is non-NULL before access + - media: mc: Add num_links flag to media_pad + - media: mc: Rename pad variable to clarify intent + - media: mc: Expand MUST_CONNECT flag to always require an enabled link + - media: nxp: imx8-isi: Mark all crossbar sink pads as MUST_CONNECT + - md: use RCU lock to protect traversal in md_spares_need_change() + - KVM: Always flush async #PF workqueue when vCPU is being destroyed + - arm64: dts: qcom: sm8550-qrd: correct WCD9385 TX port mapping + - arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mapping + - cpufreq: amd-pstate: Fix min_perf assignment in amd_pstate_adjust_perf() + - thermal/intel: Fix intel_tcc_get_temp() to support negative CPU temperature + - powercap: intel_rapl: Fix a NULL pointer dereference + - powercap: intel_rapl: Fix locking in TPMI RAPL + - powercap: intel_rapl_tpmi: Fix a register bug + - powercap: intel_rapl_tpmi: Fix System Domain probing + - powerpc/smp: Adjust nr_cpu_ids to cover all threads of a core + - powerpc/smp: Increase nr_cpu_ids to include the boot CPU + - sparc64: NMI watchdog: fix return value of __setup handler + - sparc: vDSO: fix return value of __setup handler + - selftests/mqueue: Set timeout to 180 seconds + - pinctrl: qcom: sm8650-lpass-lpi: correct Kconfig name + - ext4: correct best extent lstart adjustment logic + - drm/amdgpu/display: Address kdoc for 'is_psr_su' in 'fill_dc_dirty_rects' + - block: Clear zone limits for a non-zoned stacked queue + - kasan/test: avoid gcc warning for intentional overflow + - bounds: support non-power-of-two CONFIG_NR_CPUS + - fat: fix uninitialized field in nostale filehandles + - fuse: fix VM_MAYSHARE and direct_io_allow_mmap + - mfd: twl: Select MFD_CORE + - ubifs: Set page uptodate in the correct place + - ubi: Check for too small LEB size in VTBL code + - ubi: correct the calculation of fastmap size + - ubifs: ubifs_symlink: Fix memleak of inode->i_link in error path + - mtd: rawnand: meson: fix scrambling mode value in command macro + - md/md-bitmap: fix incorrect usage for sb_index + - x86/nmi: Fix the inverse "in NMI handler" check + - parisc/unaligned: Rewrite 64-bit inline assembly of emulate_ldd() + - parisc: Avoid clobbering the C/B bits in the PSW with tophys and tovirt + macros + - parisc: Fix ip_fast_csum + - parisc: Fix csum_ipv6_magic on 32-bit systems + - parisc: Fix csum_ipv6_magic on 64-bit systems + - parisc: Strip upper 32 bit of sum in csum_ipv6_magic for 64-bit builds + - md/raid5: fix atomicity violation in raid5_cache_count + - iio: adc: rockchip_saradc: fix bitmask for channels on SARADCv2 + - iio: adc: rockchip_saradc: use mask for write_enable bitfield + - docs: Restore "smart quotes" for quotes + - cpufreq: Limit resolving a frequency to policy min/max + - PM: suspend: Set mem_sleep_current during kernel command line setup + - vfio/pds: Always clear the save/restore FDs on reset + - clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays + - clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays + - clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays + - clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays + - clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays + - clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays + - clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays + - usb: xhci: Add error handling in xhci_map_urb_for_dma + - powerpc/fsl: Fix mfpmr build errors with newer binutils + - USB: serial: ftdi_sio: add support for GMC Z216C Adapter IR-USB + - USB: serial: add device ID for VeriFone adapter + - USB: serial: cp210x: add ID for MGP Instruments PDS100 + - wifi: mac80211: track capability/opmode NSS separately + - USB: serial: option: add MeiG Smart SLM320 product + - KVM: x86/xen: inject vCPU upcall vector when local APIC is enabled + - USB: serial: cp210x: add pid/vid for TDK NC0110013M and MM0110113M + - PM: sleep: wakeirq: fix wake irq warning in system suspend + - mmc: tmio: avoid concurrent runs of mmc_request_done() + - fuse: replace remaining make_bad_inode() with fuse_make_bad() + - fuse: fix root lookup with nonzero generation + - fuse: don't unhash root + - usb: typec: ucsi: Clean up UCSI_CABLE_PROP macros + - usb: dwc3-am62: fix module unload/reload behavior + - usb: dwc3-am62: Disable wakeup at remove + - serial: core: only stop transmit when HW fifo is empty + - serial: Lock console when calling into driver before registration + - btrfs: qgroup: always free reserved space for extent records + - btrfs: fix off-by-one chunk length calculation at contains_pending_extent() + - wifi: rtw88: Add missing VID/PIDs for 8811CU and 8821CU + - docs: Makefile: Add dependency to $(YNL_INDEX) for targets other than + htmldocs + - PCI/PM: Drain runtime-idle callbacks before driver removal + - PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root Ports + - Revert "Revert "md/raid5: Wait for MD_SB_CHANGE_PENDING in raid5d"" + - md: don't clear MD_RECOVERY_FROZEN for new dm-raid until resume + - md: export helpers to stop sync_thread + - md: export helper md_is_rdwr() + - md: add a new helper reshape_interrupted() + - dm-raid: really frozen sync_thread during suspend + - md/dm-raid: don't call md_reap_sync_thread() directly + - dm-raid: add a new helper prepare_suspend() in md_personality + - dm-raid456, md/raid456: fix a deadlock for dm-raid456 while io concurrent + with reshape + - dm-raid: fix lockdep waring in "pers->hot_add_disk" + - powerpc: xor_vmx: Add '-mhard-float' to CFLAGS + - mac802154: fix llsec key resources release in mac802154_llsec_key_del + - mm: swap: fix race between free_swap_and_cache() and swapoff() + - mmc: core: Fix switch on gp3 partition + - Bluetooth: btnxpuart: Fix btnxpuart_close + - leds: trigger: netdev: Fix kernel panic on interface rename trig notify + - drm/etnaviv: Restore some id values + - landlock: Warn once if a Landlock action is requested while disabled + - io_uring: fix mshot read defer taskrun cqe posting + - hwmon: (amc6821) add of_match table + - io_uring: fix io_queue_proc modifying req->flags + - ext4: fix corruption during on-line resize + - nvmem: meson-efuse: fix function pointer type mismatch + - slimbus: core: Remove usage of the deprecated ida_simple_xx() API + - phy: tegra: xusb: Add API to retrieve the port number of phy + - usb: gadget: tegra-xudc: Fix USB3 PHY retrieval logic + - speakup: Fix 8bit characters from direct synth + - debugfs: fix wait/cancellation handling during remove + - PCI/AER: Block runtime suspend when handling errors + - io_uring/net: correctly handle multishot recvmsg retry setup + - io_uring: fix mshot io-wq checks + - PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p + - sparc32: Fix parport build with sparc32 + - nfs: fix UAF in direct writes + - NFS: Read unlock folio on nfs_page_create_from_folio() error + - kbuild: Move -Wenum-{compare-conditional,enum-conversion} into W=1 + - PCI: qcom: Enable BDF to SID translation properly + - PCI: dwc: endpoint: Fix advertised resizable BAR size + - PCI: hv: Fix ring buffer size calculation + - cifs: prevent updating file size from server if we have a read/write lease + - cifs: allow changing password during remount + - thermal/drivers/mediatek: Fix control buffer enablement on MT7896 + - vfio/pci: Disable auto-enable of exclusive INTx IRQ + - vfio/pci: Lock external INTx masking ops + - vfio/platform: Disable virqfds on cleanup + - vfio/platform: Create persistent IRQ handlers + - vfio/fsl-mc: Block calling interrupt handler without trigger + - tpm,tpm_tis: Avoid warning splat at shutdown + - ksmbd: replace generic_fillattr with vfs_getattr + - ksmbd: retrieve number of blocks using vfs_getattr in + set_file_allocation_info + - platform/x86/intel/tpmi: Change vsec offset to u64 + - io_uring/rw: return IOU_ISSUE_SKIP_COMPLETE for multishot retry + - io_uring: clean rings on NO_MMAP alloc fail + - ring-buffer: Do not set shortest_full when full target is hit + - ring-buffer: Fix full_waiters_pending in poll + - ring-buffer: Use wait_event_interruptible() in ring_buffer_wait() + - tracing/ring-buffer: Fix wait_on_pipe() race + - dlm: fix user space lkb refcounting + - soc: fsl: qbman: Always disable interrupts when taking cgr_lock + - soc: fsl: qbman: Use raw spinlock for cgr_lock + - s390/zcrypt: fix reference counting on zcrypt card objects + - drm/probe-helper: warn about negative .get_modes() + - drm/panel: do not return negative error codes from drm_panel_get_modes() + - drm/exynos: do not return negative values from .get_modes() + - drm/imx/ipuv3: do not return negative values from .get_modes() + - drm/vc4: hdmi: do not return negative values from .get_modes() + - clocksource/drivers/timer-riscv: Clear timer interrupt on timer + initialization + - memtest: use {READ,WRITE}_ONCE in memory scanning + - Revert "block/mq-deadline: use correct way to throttling write requests" + - lsm: use 32-bit compatible data types in LSM syscalls + - lsm: handle the NULL buffer case in lsm_fill_user_ctx() + - f2fs: mark inode dirty for FI_ATOMIC_COMMITTED flag + - f2fs: truncate page cache before clearing flags when aborting atomic write + - nilfs2: fix failure to detect DAT corruption in btree and direct mappings + - nilfs2: prevent kernel bug at submit_bh_wbc() + - cifs: make sure server interfaces are requested only for SMB3+ + - cifs: reduce warning log level for server not advertising interfaces + - cifs: open_cached_dir(): add FILE_READ_EA to desired access + - mtd: rawnand: Fix and simplify again the continuous read derivations + - mtd: rawnand: Add a helper for calculating a page index + - mtd: rawnand: Ensure all continuous terms are always in sync + - mtd: rawnand: Constrain even more when continuous reads are enabled + - cpufreq: dt: always allocate zeroed cpumask + - io_uring/futex: always remove futex entry for cancel all + - io_uring/waitid: always remove waitid entry for cancel all + - x86/CPU/AMD: Update the Zenbleed microcode revisions + - ksmbd: fix slab-out-of-bounds in smb_strndup_from_utf16() + - net: esp: fix bad handling of pages from page_pool + - NFSD: Fix nfsd_clid_class use of __string_len() macro + - drm/i915: Add missing ; to __assign_str() macros in tracepoint code + - net: hns3: tracing: fix hclgevf trace event strings + - cxl/trace: Properly initialize cxl_poison region name + - ksmbd: fix potencial out-of-bounds when buffer offset is invalid + - virtio: reenable config if freezing device failed + - LoongArch: Change __my_cpu_offset definition to avoid mis-optimization + - LoongArch: Define the __io_aw() hook as mmiowb() + - LoongArch/crypto: Clean up useless assignment operations + - wireguard: netlink: check for dangling peer via is_dead instead of empty + list + - wireguard: netlink: access device through ctx instead of peer + - wireguard: selftests: set RISCV_ISA_FALLBACK on riscv{32,64} + - ahci: asm1064: asm1166: don't limit reported ports + - drm/amd/display: Change default size for dummy plane in DML2 + - drm/amdgpu: amdgpu_ttm_gart_bind set gtt bound flag + - drm/amdgpu/pm: Fix NULL pointer dereference when get power limit + - drm/amdgpu/pm: Check the validity of overdiver power limit + - drm/amd/display: Override min required DCFCLK in dml1_validate + - drm/amd/display: Allow dirty rects to be sent to dmub when abm is active + - drm/amd/display: Init DPPCLK from SMU on dcn32 + - drm/amd/display: Update odm when ODM combine is changed on an otg master + pipe with no plane + - drm/amd/display: Fix idle check for shared firmware state + - drm/amd/display: Amend coasting vtotal for replay low hz + - drm/amd/display: Lock all enabled otg pipes even with no planes + - drm/amd/display: Implement wait_for_odm_update_pending_complete + - drm/amd/display: Return the correct HDCP error code + - drm/amd/display: Add a dc_state NULL check in dc_state_release + - drm/amd/display: Fix noise issue on HDMI AV mute + - dm snapshot: fix lockup in dm_exception_table_exit + - x86/pm: Work around false positive kmemleak report in msr_build_context() + - wifi: brcmfmac: add per-vendor feature detection callback + - wifi: brcmfmac: cfg80211: Use WSEC to set SAE password + - wifi: brcmfmac: Demote vendor-specific attach/detach messages to info + - drm/ttm: Make sure the mapped tt pages are decrypted when needed + - drm/amd/display: Unify optimize_required flags and VRR adjustments + - drm/amd/display: Add more checks for exiting idle in DC + - btrfs: add set_folio_extent_mapped() helper + - btrfs: replace sb::s_blocksize by fs_info::sectorsize + - btrfs: add helpers to get inode from page/folio pointers + - btrfs: add helpers to get fs_info from page/folio pointers + - btrfs: add helper to get fs_info from struct inode pointer + - btrfs: qgroup: validate btrfs_qgroup_inherit parameter + - vfio: Introduce interface to flush virqfd inject workqueue + - vfio/pci: Create persistent INTx handler + - drm/bridge: add ->edid_read hook and drm_bridge_edid_read() + - drm/bridge: lt8912b: use drm_bridge_edid_read() + - drm/bridge: lt8912b: clear the EDID property on failures + - drm/bridge: lt8912b: do not return negative values from .get_modes() + - drm/amd/display: Remove pixle rate limit for subvp + - drm/amd/display: Revert Remove pixle rate limit for subvp + - workqueue: Shorten events_freezable_power_efficient name + - drm/amd/display: Use freesync when `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found + - netfilter: nf_tables: reject constant set with timeout + - Revert "crypto: pkcs7 - remove sha1 support" + - x86/efistub: Call mixed mode boot services on the firmware's stack + - ASoC: amd: yc: Revert "Fix non-functional mic on Lenovo 21J2" + - ASoC: amd: yc: Revert "add new YC platform variant (0x63) support" + - Fix memory leak in posix_clock_open() + - wifi: rtw88: 8821cu: Fix connection failure + - x86/Kconfig: Remove CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT + - x86/sev: Fix position dependent variable references in startup code + - clocksource/drivers/arm_global_timer: Fix maximum prescaler value + - ARM: 9352/1: iwmmxt: Remove support for PJ4/PJ4B cores + - ARM: 9359/1: flush: check if the folio is reserved for no-mapping addresses + - entry: Respect changes to system call number by trace_sys_enter() + - swiotlb: Fix double-allocation of slots due to broken alignment handling + - swiotlb: Honour dma_alloc_coherent() alignment in swiotlb_alloc() + - swiotlb: Fix alignment checks when both allocation and DMA masks are present + - iommu/dma: Force swiotlb_max_mapping_size on an untrusted device + - printk: Update @console_may_schedule in console_trylock_spinning() + - irqchip/renesas-rzg2l: Flush posted write in irq_eoi() + - irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() + - irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi() + - irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type + - kprobes/x86: Use copy_from_kernel_nofault() to read from unsafe address + - efi/libstub: fix efi_random_alloc() to allocate memory at alloc_min or + higher address + - x86/mpparse: Register APIC address only once + - x86/fpu: Keep xfd_state in sync with MSR_IA32_XFD + - efi: fix panic in kdump kernel + - pwm: img: fix pwm clock lookup + - selftests/mm: Fix build with _FORTIFY_SOURCE + - btrfs: handle errors returned from unpin_extent_cache() + - btrfs: fix warning messages not printing interval at unpin_extent_range() + - btrfs: do not skip re-registration for the mounted device + - mfd: intel-lpss: Switch to generalized quirk table + - mfd: intel-lpss: Introduce QUIRK_CLOCK_DIVIDER_UNITY for XPS 9530 + - drm/i915: Replace a memset() with zero initialization + - drm/i915: Try to preserve the current shared_dpll for fastset on type-c + ports + - drm/i915: Include the PLL name in the debug messages + - drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs + - crypto: iaa - Fix nr_cpus < nr_iaa case + - drm/amd/display: Prevent crash when disable stream + - ALSA: hda/tas2781: remove digital gain kcontrol + - ALSA: hda/tas2781: add locks to kcontrols + - mm: zswap: fix writeback shinker GFP_NOIO/GFP_NOFS recursion + - init: open /initrd.image with O_LARGEFILE + - x86/efistub: Add missing boot_params for mixed mode compat entry + - efi/libstub: Cast away type warning in use of max() + - x86/efistub: Reinstate soft limit for initrd loading + - prctl: generalize PR_SET_MDWE support check to be per-arch + - ARM: prctl: reject PR_SET_MDWE on pre-ARMv6 + - tmpfs: fix race on handling dquot rbtree + - btrfs: validate device maj:min during open + - btrfs: fix race in read_extent_buffer_pages() + - btrfs: zoned: don't skip block groups with 100% zone unusable + - btrfs: zoned: use zone aware sb location for scrub + - btrfs: zoned: fix use-after-free in do_zone_finish() + - wifi: mac80211: check/clear fast rx for non-4addr sta VLAN changes + - wifi: cfg80211: add a flag to disable wireless extensions + - wifi: iwlwifi: mvm: disable MLO for the time being + - wifi: iwlwifi: fw: don't always use FW dump trig + - wifi: iwlwifi: mvm: handle debugfs names more carefully + - Revert "drm/amd/display: Fix sending VSC (+ colorimetry) packets for DP/eDP + displays without PSR" + - fbdev: Select I/O-memory framebuffer ops for SBus + - exec: Fix NOMMU linux_binprm::exec in transfer_args_to_stack() + - hexagon: vmlinux.lds.S: handle attributes section + - mm: cachestat: fix two shmem bugs + - selftests/mm: sigbus-wp test requires UFFD_FEATURE_WP_HUGETLBFS_SHMEM + - selftests/mm: fix ARM related issue with fork after pthread_create + - mmc: sdhci-omap: re-tuning is needed after a pm transition to support emmc + HS200 mode + - mmc: core: Initialize mmc_blk_ioc_data + - mmc: core: Avoid negative index with array access + - sdhci-of-dwcmshc: disable PM runtime in dwcmshc_remove() + - block: Do not force full zone append completion in req_bio_endio() + - thermal: devfreq_cooling: Fix perf state when calculate dfc res_util + - Revert "thermal: core: Don't update trip points inside the hysteresis range" + - nouveau/dmem: handle kcalloc() allocation failure + - net: ll_temac: platform_get_resource replaced by wrong function + - net: wan: framer: Add missing static inline qualifiers + - net: phy: qcom: at803x: fix kernel panic with at8031_probe + - drm/xe/query: fix gt_id bounds check + - drm/dp: Fix divide-by-zero regression on DP MST unplug with nouveau + - drm/vmwgfx: Create debugfs ttm_resource_manager entry only if needed + - drm/amdkfd: fix TLB flush after unmap for GFX9.4.2 + - drm/amdgpu: fix deadlock while reading mqd from debugfs + - drm/amd/display: Remove MPC rate control logic from DCN30 and above + - drm/amd/display: Set DCN351 BB and IP the same as DCN35 + - drm/i915/hwmon: Fix locking inversion in sysfs getter + - drm/i915/vma: Fix UAF on destroy against retire race + - drm/i915/bios: Tolerate devdata==NULL in + intel_bios_encoder_supports_dp_dual_mode() + - drm/i915/vrr: Generate VRR "safe window" for DSB + - drm/i915/dsi: Go back to the previous INIT_OTP/DISPLAY_ON order, mostly + - drm/i915/dsb: Fix DSB vblank waits when using VRR + - drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed() + - drm/i915: Pre-populate the cursor physical dma address + - drm/i915/gt: Reset queue_priority_hint on parking + - drm/amd/display: Fix bounds check for dcn35 DcfClocks + - Bluetooth: hci_sync: Fix not checking error on hci_cmd_sync_cancel_sync + - mtd: spinand: Add support for 5-byte IDs + - Revert "usb: phy: generic: Get the vbus supply" + - usb: cdc-wdm: close race between read and workqueue + - usb: misc: ljca: Fix double free in error handling path + - USB: UAS: return ENODEV when submit urbs fail with device not attached + - vfio/pds: Make sure migration file isn't accessed after reset + - ring-buffer: Make wake once of ring_buffer_wait() more robust + - btrfs: fix extent map leak in unexpected scenario at unpin_extent_cache() + - ALSA: sh: aica: reorder cleanup operations to avoid UAF bugs + - scsi: ufs: qcom: Provide default cycles_in_1us value + - scsi: sd: Fix TCG OPAL unlock on system resume + - scsi: core: Fix unremoved procfs host directory regression + - staging: vc04_services: changen strncpy() to strscpy_pad() + - staging: vc04_services: fix information leak in create_component() + - genirq: Introduce IRQF_COND_ONESHOT and use it in pinctrl-amd + - usb: dwc3: Properly set system wakeup + - USB: core: Fix deadlock in usb_deauthorize_interface() + - USB: core: Add hub_get() and hub_put() routines + - USB: core: Fix deadlock in port "disable" sysfs attribute + - usb: dwc2: host: Fix remote wakeup from hibernation + - usb: dwc2: host: Fix hibernation flow + - usb: dwc2: host: Fix ISOC flow in DDMA mode + - usb: dwc2: gadget: Fix exiting from clock gating + - usb: dwc2: gadget: LPM flow fix + - usb: udc: remove warning when queue disabled ep + - usb: typec: ucsi: Fix race between typec_switch and role_switch + - usb: typec: tcpm: fix double-free issue in tcpm_port_unregister_pd() + - usb: typec: tcpm: Correct port source pdo array in pd_set callback + - usb: typec: tcpm: Update PD of Type-C port upon pd_set + - usb: typec: Return size of buffer if pd_set operation succeeds + - usb: typec: ucsi: Clear EVENT_PENDING under PPM lock + - usb: typec: ucsi: Ack unsupported commands + - usb: typec: ucsi_acpi: Refactor and fix DELL quirk + - usb: typec: ucsi: Clear UCSI_CCI_RESET_COMPLETE before reset + - scsi: qla2xxx: Prevent command send on chip reset + - scsi: qla2xxx: Fix N2N stuck connection + - scsi: qla2xxx: Split FCE|EFT trace control + - scsi: qla2xxx: Update manufacturer detail + - scsi: qla2xxx: NVME|FCP prefer flag not being honored + - scsi: qla2xxx: Fix command flush on cable pull + - scsi: qla2xxx: Fix double free of the ha->vp_map pointer + - scsi: qla2xxx: Fix double free of fcport + - scsi: qla2xxx: Change debug message during driver unload + - scsi: qla2xxx: Delay I/O Abort on PCI error + - x86/bugs: Fix the SRSO mitigation on Zen3/4 + - crash: use macro to add crashk_res into iomem early for specific arch + - drm/amd/display: fix IPX enablement + - x86/bugs: Use fixed addressing for VERW operand + - Revert "x86/bugs: Use fixed addressing for VERW operand" + - usb: dwc3: pci: Drop duplicate ID + - scsi: lpfc: Correct size for cmdwqe/rspwqe for memset() + - scsi: lpfc: Correct size for wqe for memset() + - scsi: libsas: Add a helper sas_get_sas_addr_and_dev_type() + - scsi: libsas: Fix disk not being scanned in after being removed + - perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and + later + - x86/sev: Skip ROM range scans and validation for SEV-SNP guests + - tools/resolve_btfids: fix build with musl libc + - drm/amdgpu: fix use-after-free bug + - drm/sched: fix null-ptr-deref in init entity + - Linux 6.8.3 + - [Config] updateconfigs following v6.8.3 import + + * Noble update: v6.8.3 upstream stable release (LP: #2060531) // + [Ubuntu-24.04] Hugepage memory is not getting released even after destroying + the guest! (LP: #2062556) + - block: Fix page refcounts for unaligned buffers in __bio_release_pages() + + * [SPR][EMR][GNR] TDX: efi: TD Measurement support for kernel cmdline/initrd + sections from EFI stub (LP: #2060130) + - efi/libstub: Use TPM event typedefs from the TCG PC Client spec + - efi/tpm: Use symbolic GUID name from spec for final events table + - efi/libstub: Add Confidential Computing (CC) measurement typedefs + - efi/libstub: Measure into CC protocol if TCG2 protocol is absent + - efi/libstub: Add get_event_log() support for CC platforms + - x86/efistub: Remap kernel text read-only before dropping NX attribute + + * Fix acpi_power_meter accessing IPMI region before it's ready (LP: #2059263) + - ACPI: IPMI: Add helper to wait for when SMI is selected + - hwmon: (acpi_power_meter) Ensure IPMI space handler is ready on Dell systems + + * Drop fips-checks script from trees (LP: #2055083) + - [Packaging] Remove fips-checks script + + * alsa/realtek: adjust max output valume for headphone on 2 LG machines + (LP: #2058573) + - ALSA: hda/realtek: fix the hp playback volume issue for LG machines + + * Noble update: v6.8.2 upstream stable release (LP: #2060097) + - do_sys_name_to_handle(): use kzalloc() to fix kernel-infoleak + - workqueue.c: Increase workqueue name length + - workqueue: Move pwq->max_active to wq->max_active + - workqueue: Factor out pwq_is_empty() + - workqueue: Replace pwq_activate_inactive_work() with [__]pwq_activate_work() + - workqueue: Move nr_active handling into helpers + - workqueue: Make wq_adjust_max_active() round-robin pwqs while activating + - workqueue: RCU protect wq->dfl_pwq and implement accessors for it + - workqueue: Introduce struct wq_node_nr_active + - workqueue: Implement system-wide nr_active enforcement for unbound + workqueues + - workqueue: Don't call cpumask_test_cpu() with -1 CPU in + wq_update_node_max_active() + - iomap: clear the per-folio dirty bits on all writeback failures + - fs: Fix rw_hint validation + - io_uring: remove looping around handling traditional task_work + - io_uring: remove unconditional looping in local task_work handling + - s390/dasd: Use dev_*() for device log messages + - s390/dasd: fix double module refcount decrement + - fs/hfsplus: use better @opf description + - md: fix kmemleak of rdev->serial + - rcu/exp: Fix RCU expedited parallel grace period kworker allocation failure + recovery + - rcu/exp: Handle RCU expedited grace period kworker allocation failure + - fs/select: rework stack allocation hack for clang + - block: fix deadlock between bd_link_disk_holder and partition scan + - md: Don't clear MD_CLOSING when the raid is about to stop + - kunit: Setup DMA masks on the kunit device + - ovl: Always reject mounting over case-insensitive directories + - kunit: test: Log the correct filter string in executor_test + - lib/cmdline: Fix an invalid format specifier in an assertion msg + - lib: memcpy_kunit: Fix an invalid format specifier in an assertion msg + - time: test: Fix incorrect format specifier + - rtc: test: Fix invalid format specifier. + - net: test: Fix printf format specifier in skb_segment kunit test + - drm/xe/tests: Fix printf format specifiers in xe_migrate test + - drm: tests: Fix invalid printf format specifiers in KUnit tests + - md/raid1: factor out helpers to add rdev to conf + - md/raid1: record nonrot rdevs while adding/removing rdevs to conf + - md/raid1: fix choose next idle in read_balance() + - io_uring/net: unify how recvmsg and sendmsg copy in the msghdr + - io_uring/net: move receive multishot out of the generic msghdr path + - io_uring/net: fix overflow check in io_recvmsg_mshot_prep() + - nvme: host: fix double-free of struct nvme_id_ns in ns_update_nuse() + - aoe: fix the potential use-after-free problem in aoecmd_cfg_pkts + - x86/mm: Ensure input to pfn_to_kaddr() is treated as a 64-bit type + - x86/resctrl: Remove hard-coded memory bandwidth limit + - x86/resctrl: Read supported bandwidth sources from CPUID + - x86/resctrl: Implement new mba_MBps throttling heuristic + - x86/sme: Fix memory encryption setting if enabled by default and not + overridden + - timekeeping: Fix cross-timestamp interpolation on counter wrap + - timekeeping: Fix cross-timestamp interpolation corner case decision + - timekeeping: Fix cross-timestamp interpolation for non-x86 + - x86/asm: Remove the __iomem annotation of movdir64b()'s dst argument + - sched/fair: Take the scheduling domain into account in select_idle_smt() + - sched/fair: Take the scheduling domain into account in select_idle_core() + - wifi: ath10k: fix NULL pointer dereference in + ath10k_wmi_tlv_op_pull_mgmt_tx_compl_ev() + - wifi: b43: Stop/wake correct queue in DMA Tx path when QoS is disabled + - wifi: b43: Stop/wake correct queue in PIO Tx path when QoS is disabled + - wifi: b43: Stop correct queue in DMA worker when QoS is disabled + - wifi: b43: Disable QoS for bcm4331 + - wifi: wilc1000: fix declarations ordering + - wifi: wilc1000: fix RCU usage in connect path + - wifi: ath11k: add support to select 6 GHz regulatory type + - wifi: ath11k: store cur_regulatory_info for each radio + - wifi: ath11k: fix a possible dead lock caused by ab->base_lock + - wifi: rtl8xxxu: add cancel_work_sync() for c2hcmd_work + - wifi: wilc1000: do not realloc workqueue everytime an interface is added + - wifi: wilc1000: fix multi-vif management when deleting a vif + - wifi: mwifiex: debugfs: Drop unnecessary error check for + debugfs_create_dir() + - ARM: dts: renesas: r8a73a4: Fix external clocks and clock rate + - arm64: dts: qcom: x1e80100: drop qcom,drv-count + - arm64: dts: qcom: sc8180x: Hook up VDD_CX as GCC parent domain + - arm64: dts: qcom: sc8180x: Fix up big CPU idle state entry latency + - arm64: dts: qcom: sc8180x: Add missing CPU off state + - arm64: dts: qcom: sc8180x: Fix eDP PHY power-domains + - arm64: dts: qcom: sc8180x: Don't hold MDP core clock at FMAX + - arm64: dts: qcom: sc8180x: Require LOW_SVS vote for MMCX if DISPCC is on + - arm64: dts: qcom: sc8180x: Add missing CPU<->MDP_CFG path + - arm64: dts: qcom: sc8180x: Shrink aoss_qmp register space size + - cpufreq: brcmstb-avs-cpufreq: add check for cpufreq_cpu_get's return value + - cpufreq: mediatek-hw: Wait for CPU supplies before probing + - sock_diag: annotate data-races around sock_diag_handlers[family] + - inet_diag: annotate data-races around inet_diag_table[] + - bpftool: Silence build warning about calloc() + - selftests/bpf: Fix potential premature unload in bpf_testmod + - libbpf: Apply map_set_def_max_entries() for inner_maps on creation + - selftest/bpf: Add map_in_maps with BPF_MAP_TYPE_PERF_EVENT_ARRAY values + - bpftool: Fix wrong free call in do_show_link + - wifi: ath12k: Fix issues in channel list update + - selftests/bpf: Fix the flaky tc_redirect_dtime test + - selftests/bpf: Wait for the netstamp_needed_key static key to be turned on + - wifi: cfg80211: add RNR with reporting AP information + - wifi: mac80211: use deflink and fix typo in link ID check + - wifi: iwlwifi: change link id in time event to s8 + - af_unix: Annotate data-race of gc_in_progress in wait_for_unix_gc(). + - arm64: dts: qcom: sm8450: Add missing interconnects to serial + - soc: qcom: socinfo: rename PM2250 to PM4125 + - arm64: dts: qcom: sc7280: Add static properties to cryptobam + - arm64: dts: qcom: qcm6490-fairphone-fp5: Add missing reserved-memory + - arm64: dts: qcom: sdm845-oneplus-common: improve DAI node naming + - arm64: dts: qcom: rename PM2250 to PM4125 + - cpufreq: mediatek-hw: Don't error out if supply is not found + - libbpf: Fix faccessat() usage on Android + - libbpf: fix __arg_ctx type enforcement for perf_event programs + - pmdomain: qcom: rpmhpd: Drop SA8540P gfx.lvl + - arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc + - arm64: dts: renesas: r8a779g0: Restore sort order + - arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2 + - selftests/bpf: Disable IPv6 for lwt_redirect test + - arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on OSM-S i.MX8MM + - arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on SL/BL i.MX8MM + - arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL + OSM-S board + - arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL + board + - arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL + OSM-S board + - arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL + board + - arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module + - arm64: dts: imx8qm: Align edma3 power-domains resources indentation + - arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers + - libbpf: Add missing LIBBPF_API annotation to libbpf_set_memlock_rlim API + - wifi: ath9k: delay all of ath9k_wmi_event_tasklet() until init is complete + - wifi: ath11k: change to move WMI_VDEV_PARAM_SET_HEMU_MODE before + WMI_PEER_ASSOC_CMDID + - wifi: ath12k: fix fetching MCBC flag for QCN9274 + - wifi: iwlwifi: mvm: report beacon protection failures + - wifi: iwlwifi: dbg-tlv: ensure NUL termination + - wifi: iwlwifi: acpi: fix WPFC reading + - wifi: iwlwifi: mvm: initialize rates in FW earlier + - wifi: iwlwifi: fix EWRD table validity check + - wifi: iwlwifi: mvm: d3: fix IPN byte order + - wifi: iwlwifi: always have 'uats_enabled' + - wifi: iwlwifi: mvm: fix the TLC command after ADD_STA + - wifi: iwlwifi: read BIOS PNVM only for non-Intel SKU + - gpio: vf610: allow disabling the vf610 driver + - selftests/bpf: trace_helpers.c: do not use poisoned type + - bpf: make sure scalar args don't accept __arg_nonnull tag + - bpf: don't emit warnings intended for global subprogs for static subprogs + - arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS + - pwm: atmel-hlcdc: Fix clock imbalance related to suspend support + - net: blackhole_dev: fix build warning for ethh set but not used + - spi: consolidate setting message->spi + - spi: move split xfers for CS_WORD emulation + - arm64: dts: ti: k3-am62p5-sk: Enable CPSW MDIO node + - arm64: dts: ti: k3-j721s2: Fix power domain for VTM node + - arm64: dts: ti: k3-j784s4: Fix power domain for VTM node + - wifi: ath11k: initialize rx_mcs_80 and rx_mcs_160 before use + - wifi: libertas: fix some memleaks in lbs_allocate_cmd_buffer() + - arm64: dts: ti: k3-am69-sk: remove assigned-clock-parents for unused VP + - libbpf: fix return value for PERF_EVENT __arg_ctx type fix up check + - arm64: dts: ti: k3-am62p-mcu/wakeup: Disable MCU and wakeup R5FSS nodes + - arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J + - libbpf: Use OPTS_SET() macro in bpf_xdp_query() + - wifi: wfx: fix memory leak when starting AP + - arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY + - arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY + - arm64: dts: qcom: sm8650: Fix UFS PHY clocks + - wifi: ath12k: fix incorrect logic of calculating vdev_stats_id + - printk: nbcon: Relocate 32bit seq macros + - printk: ringbuffer: Do not skip non-finalized records with prb_next_seq() + - printk: Wait for all reserved records with pr_flush() + - printk: Add this_cpu_in_panic() + - printk: ringbuffer: Cleanup reader terminology + - printk: ringbuffer: Skip non-finalized records in panic + - printk: Disable passing console lock owner completely during panic() + - pwm: sti: Fix capture for st,pwm-num-chan < st,capture-num-chan + - tools/resolve_btfids: Refactor set sorting with types from btf_ids.h + - tools/resolve_btfids: Fix cross-compilation to non-host endianness + - wifi: iwlwifi: support EHT for WH + - wifi: iwlwifi: properly check if link is active + - wifi: iwlwifi: mvm: fix erroneous queue index mask + - wifi: iwlwifi: mvm: don't set the MFP flag for the GTK + - wifi: iwlwifi: mvm: don't set replay counters to 0xff + - s390/pai: fix attr_event_free upper limit for pai device drivers + - s390/vdso: drop '-fPIC' from LDFLAGS + - arm64: dts: qcom: qcm6490-idp: Correct the voltage setting for vph_pwr + - arm64: dts: qcom: qcs6490-rb3gen2: Correct the voltage setting for vph_pwr + - selftests: forwarding: Add missing config entries + - selftests: forwarding: Add missing multicast routing config entries + - arm64: dts: qcom: sm6115: drop pipe clock selection + - ipv6: mcast: remove one synchronize_net() barrier in ipv6_mc_down() + - arm64: dts: mt8183: Move CrosEC base detection node to kukui-based DTs + - arm64: dts: mediatek: mt7986: fix reference to PWM in fan node + - arm64: dts: mediatek: mt7986: drop crypto's unneeded/invalid clock name + - arm64: dts: mediatek: mt7986: fix SPI bus width properties + - arm64: dts: mediatek: mt7986: fix SPI nodename + - arm64: dts: mediatek: mt7986: drop "#clock-cells" from PWM + - arm64: dts: mediatek: mt7986: add "#reset-cells" to infracfg + - arm64: dts: mediatek: mt8192-asurada: Remove CrosEC base detection node + - arm64: dts: mediatek: mt8192: fix vencoder clock name + - arm64: dts: mediatek: mt8186: fix VENC power domain clocks + - arm64: dts: mediatek: mt7622: add missing "device_type" to memory nodes + - can: m_can: Start/Cancel polling timer together with interrupts + - wifi: iwlwifi: mvm: Fix the listener MAC filter flags + - bpf: Mark bpf_spin_{lock,unlock}() helpers with notrace correctly + - arm64: dts: qcom: sdm845: Use the Low Power Island CX/MX for SLPI + - soc: qcom: llcc: Check return value on Broadcast_OR reg read + - ARM: dts: qcom: msm8974: correct qfprom node size + - arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains + - arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers + - arm64: dts: ti: am65x: Fix dtbs_install for Rocktech OLDI overlay + - cpufreq: qcom-hw: add CONFIG_COMMON_CLK dependency + - wifi: wilc1000: prevent use-after-free on vif when cleaning up all + interfaces + - pwm: dwc: use pm_sleep_ptr() macro + - arm64: dts: ti: k3-am69-sk: fix PMIC interrupt number + - arm64: dts: ti: k3-j721e-sk: fix PMIC interrupt number + - arm64: dts: ti: k3-am62-main: disable usb lpm + - ACPI: processor_idle: Fix memory leak in acpi_processor_power_exit() + - bus: tegra-aconnect: Update dependency to ARCH_TEGRA + - iommu/amd: Mark interrupt as managed + - wifi: brcmsmac: avoid function pointer casts + - arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios + - arm64: dts: qcom: sm8150: correct PCIe wake-gpios + - powercap: dtpm_cpu: Fix error check against freq_qos_add_request() + - net: ena: Remove ena_select_queue + - arm64: dts: ti: k3-j7200-common-proc-board: Modify Pinmux for wkup_uart0 and + mcu_uart0 + - arm64: dts: ti: k3-j7200-common-proc-board: Remove clock-frequency from + mcu_uart0 + - arm64: dts: ti: k3-j721s2-common-proc-board: Remove Pinmux for CTS and RTS + in wkup_uart0 + - arm64: dts: ti: k3-j784s4-evm: Remove Pinmux for CTS and RTS in wkup_uart0 + - arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC + - arm64: dts: mt8195-cherry-tomato: change watchdog reset boot flow + - arm64: dts: ti: Add common1 register space for AM65x SoC + - arm64: dts: ti: Add common1 register space for AM62x SoC + - firmware: arm_scmi: Fix double free in SMC transport cleanup path + - wifi: cfg80211: set correct param change count in ML element + - arm64: dts: ti: k3-j721e: Fix mux-reg-masks in hbmc_mux + - arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl + - arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS + - wifi: wilc1000: revert reset line logic flip + - ARM: dts: arm: realview: Fix development chip ROM compatible value + - memory: tegra: Correct DLA client names + - wifi: mt76: mt7996: fix fw loading timeout + - wifi: mt76: mt7925: fix connect to 80211b mode fail in 2Ghz band + - wifi: mt76: mt7925: fix SAP no beacon issue in 5Ghz and 6Ghz band + - wifi: mt76: mt7925: fix mcu query command fail + - wifi: mt76: mt7925: fix wmm queue mapping + - wifi: mt76: mt7925: fix fw download fail + - wifi: mt76: mt7925: fix WoW failed in encrypted mode + - wifi: mt76: mt7925: fix the wrong header translation config + - wifi: mt76: mt7925: add flow to avoid chip bt function fail + - wifi: mt76: mt7925: add support to set ifs time by mcu command + - wifi: mt76: mt7925: update PCIe DMA settings + - wifi: mt76: mt7996: check txs format before getting skb by pid + - wifi: mt76: mt7996: fix TWT issues + - wifi: mt76: mt7996: fix incorrect interpretation of EHT MCS caps + - wifi: mt76: mt7996: fix HE beamformer phy cap for station vif + - wifi: mt76: mt7996: fix efuse reading issue + - wifi: mt76: mt7996: fix HIF_TXD_V2_1 value + - wifi: mt76: mt792x: fix ethtool warning + - wifi: mt76: mt7921e: fix use-after-free in free_irq() + - wifi: mt76: mt7925e: fix use-after-free in free_irq() + - wifi: mt76: mt7921: fix incorrect type conversion for CLC command + - wifi: mt76: mt792x: fix a potential loading failure of the 6Ghz channel + config from ACPI + - wifi: mt76: fix the issue of missing txpwr settings from ch153 to ch177 + - arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes + - arm64: dts: renesas: r9a08g045: Add missing interrupts to IRQC node + - arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs + - arm64: dts: renesas: r8a779a0: Correct avb[01] reg sizes + - arm64: dts: renesas: r8a779g0: Correct avb[01] reg sizes + - net: mctp: copy skb ext data when fragmenting + - pstore: inode: Only d_invalidate() is needed + - arm64: dts: allwinner: h6: Add RX DMA channel for SPDIF + - ARM: dts: imx6dl-yapp4: Fix typo in the QCA switch register address + - ARM: dts: imx6dl-yapp4: Move the internal switch PHYs under the switch node + - arm64: dts: imx8mp: Set SPI NOR to max 40 MHz on Data Modul i.MX8M Plus eDM + SBC + - arm64: dts: imx8mp-evk: Fix hdmi@3d node + - regulator: userspace-consumer: add module device table + - gpiolib: Pass consumer device through to core in + devm_fwnode_gpiod_get_index() + - arm64: dts: marvell: reorder crypto interrupts on Armada SoCs + - ACPI: resource: Do IRQ override on Lunnen Ground laptops + - ACPI: resource: Add MAIBENBEN X577 to irq1_edge_low_force_override + - ACPI: scan: Fix device check notification handling + - arm64: dts: rockchip: add missing interrupt-names for rk356x vdpu + - arm64: dts: rockchip: fix reset-names for rk356x i2s2 controller + - arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s + - objtool: Fix UNWIND_HINT_{SAVE,RESTORE} across basic blocks + - x86, relocs: Ignore relocations in .notes section + - SUNRPC: fix a memleak in gss_import_v2_context + - SUNRPC: fix some memleaks in gssx_dec_option_array + - arm64: dts: qcom: sm8550: Fix SPMI channels size + - arm64: dts: qcom: sm8650: Fix SPMI channels size + - mmc: wmt-sdmmc: remove an incorrect release_mem_region() call in the .remove + function + - ACPI: CPPC: enable AMD CPPC V2 support for family 17h processors + - btrfs: fix race when detecting delalloc ranges during fiemap + - wifi: rtw88: 8821cu: Fix firmware upload fail + - wifi: rtw88: 8821c: Fix beacon loss and disconnect + - wifi: rtw88: 8821c: Fix false alarm count + - wifi: brcm80211: handle pmk_op allocation failure + - riscv: dts: starfive: jh7100: fix root clock names + - PCI: Make pci_dev_is_disconnected() helper public for other drivers + - iommu/vt-d: Don't issue ATS Invalidation request when device is disconnected + - iommu/vt-d: Use rbtree to track iommu probed devices + - iommu/vt-d: Improve ITE fault handling if target device isn't present + - iommu/vt-d: Use device rbtree in iopf reporting path + - iommu: Add static iommu_ops->release_domain + - iommu/vt-d: Fix NULL domain on device release + - igc: Fix missing time sync events + - igb: Fix missing time sync events + - ice: fix stats being updated by way too large values + - Bluetooth: Remove HCI_POWER_OFF_TIMEOUT + - Bluetooth: mgmt: Remove leftover queuing of power_off work + - Bluetooth: Remove superfluous call to hci_conn_check_pending() + - Bluetooth: Remove BT_HS + - Bluetooth: hci_event: Fix not indicating new connection for BIG Sync + - Bluetooth: hci_qca: don't use IS_ERR_OR_NULL() with gpiod_get_optional() + - Bluetooth: hci_core: Cancel request on command timeout + - Bluetooth: hci_sync: Fix overwriting request callback + - Bluetooth: hci_h5: Add ability to allocate memory for private data + - Bluetooth: btrtl: fix out of bounds memory access + - Bluetooth: hci_core: Fix possible buffer overflow + - Bluetooth: msft: Fix memory leak + - Bluetooth: btusb: Fix memory leak + - Bluetooth: af_bluetooth: Fix deadlock + - Bluetooth: fix use-after-free in accessing skb after sending it + - sr9800: Add check for usbnet_get_endpoints + - s390/cache: prevent rebuild of shared_cpu_list + - bpf: Fix DEVMAP_HASH overflow check on 32-bit arches + - bpf: Fix hashtab overflow check on 32-bit arches + - bpf: Fix stackmap overflow check on 32-bit arches + - net: dsa: microchip: make sure drive strength configuration is not lost by + soft reset + - dpll: spec: use proper enum for pin capabilities attribute + - iommu: Fix compilation without CONFIG_IOMMU_INTEL + - ipv6: fib6_rules: flush route cache when rule is changed + - net: ip_tunnel: make sure to pull inner header in ip_tunnel_rcv() + - octeontx2-af: Fix devlink params + - net: phy: fix phy_get_internal_delay accessing an empty array + - dpll: fix dpll_xa_ref_*_del() for multiple registrations + - net: hns3: fix wrong judgment condition issue + - net: hns3: fix kernel crash when 1588 is received on HIP08 devices + - net: hns3: fix port duplex configure error in IMP reset + - Bluetooth: Fix eir name length + - net: phy: dp83822: Fix RGMII TX delay configuration + - erofs: fix lockdep false positives on initializing erofs_pseudo_mnt + - OPP: debugfs: Fix warning around icc_get_name() + - tcp: fix incorrect parameter validation in the do_tcp_getsockopt() function + - ipmr: fix incorrect parameter validation in the ip_mroute_getsockopt() + function + - l2tp: fix incorrect parameter validation in the pppol2tp_getsockopt() + function + - udp: fix incorrect parameter validation in the udp_lib_getsockopt() function + - net: kcm: fix incorrect parameter validation in the kcm_getsockopt) function + - net/x25: fix incorrect parameter validation in the x25_getsockopt() function + - devlink: Fix length of eswitch inline-mode + - r8152: fix unknown device for choose_configuration + - nfp: flower: handle acti_netdevs allocation failure + - bpf: hardcode BPF_PROG_PACK_SIZE to 2MB * num_possible_nodes() + - dm raid: fix false positive for requeue needed during reshape + - dm: call the resume method on internal suspend + - fbdev/simplefb: change loglevel when the power domains cannot be parsed + - drm/tegra: dsi: Add missing check for of_find_device_by_node + - drm/tegra: dpaux: Fix PM disable depth imbalance in tegra_dpaux_probe + - drm/tegra: dsi: Fix some error handling paths in tegra_dsi_probe() + - drm/tegra: dsi: Fix missing pm_runtime_disable() in the error handling path + of tegra_dsi_probe() + - drm/tegra: hdmi: Fix some error handling paths in tegra_hdmi_probe() + - drm/tegra: rgb: Fix some error handling paths in tegra_dc_rgb_probe() + - drm/tegra: rgb: Fix missing clk_put() in the error handling paths of + tegra_dc_rgb_probe() + - drm/tegra: output: Fix missing i2c_put_adapter() in the error handling paths + of tegra_output_probe() + - drm/rockchip: inno_hdmi: Fix video timing + - drm: Don't treat 0 as -1 in drm_fixp2int_ceil + - drm/vkms: Avoid reading beyond LUT array + - drm/vmwgfx: fix a memleak in vmw_gmrid_man_get_node + - drm/rockchip: lvds: do not overwrite error code + - drm/rockchip: lvds: do not print scary message when probing defer + - drm/panel-edp: use put_sync in unprepare + - drm/lima: fix a memleak in lima_heap_alloc + - ASoC: amd: acp: Add missing error handling in sof-mach + - ASoC: SOF: amd: Fix memory leak in amd_sof_acp_probe() + - ASoC: SOF: core: Skip firmware test for custom loaders + - ASoC: SOF: amd: Compute file paths on firmware load + - soundwire: stream: add missing const to Documentation + - dmaengine: tegra210-adma: Update dependency to ARCH_TEGRA + - media: tc358743: register v4l2 async device only after successful setup + - media: cadence: csi2rx: use match fwnode for media link + - PCI/DPC: Print all TLP Prefixes, not just the first + - perf record: Fix possible incorrect free in record__switch_output() + - perf record: Check conflict between '--timestamp-filename' option and pipe + mode before recording + - HID: lenovo: Add middleclick_workaround sysfs knob for cptkbd + - drm/amd/display: Fix a potential buffer overflow in 'dp_dsc_clock_en_read()' + - perf pmu: Treat the msr pmu as software + - crypto: qat - avoid memcpy() overflow warning + - ALSA: hda: cs35l41: Set Channel Index correctly when system is missing _DSD + - drm/amd/display: Fix potential NULL pointer dereferences in + 'dcn10_set_output_transfer_func()' + - ASoC: sh: rz-ssi: Fix error message print + - drm/vmwgfx: Fix vmw_du_get_cursor_mob fencing of newly-created MOBs + - clk: renesas: r8a779g0: Fix PCIe clock name + - pinctrl: renesas: rzg2l: Fix locking in rzg2l_dt_subnode_to_map() + - pinctrl: renesas: r8a779g0: Add missing SCIF_CLK2 pin group/function + - clk: samsung: exynos850: Propagate SPI IPCLK rate change + - media: v4l2: cci: print leading 0 on error + - perf evsel: Fix duplicate initialization of data->id in + evsel__parse_sample() + - perf bpf: Clean up the generated/copied vmlinux.h + - clk: meson: Add missing clocks to axg_clk_regmaps + - media: em28xx: annotate unchecked call to media_device_register() + - media: v4l2-tpg: fix some memleaks in tpg_alloc + - media: v4l2-mem2mem: fix a memleak in v4l2_m2m_register_entity + - media: dt-bindings: techwell,tw9900: Fix port schema ref + - mtd: spinand: esmt: Extend IDs to 5 bytes + - media: edia: dvbdev: fix a use-after-free + - pinctrl: mediatek: Drop bogus slew rate register range for MT8186 + - pinctrl: mediatek: Drop bogus slew rate register range for MT8192 + - drm/amdgpu: Fix potential out-of-bounds access in + 'amdgpu_discovery_reg_base_init()' + - clk: qcom: reset: Commonize the de/assert functions + - clk: qcom: reset: Ensure write completion on reset de/assertion + - quota: Fix potential NULL pointer dereference + - quota: Fix rcu annotations of inode dquot pointers + - quota: Properly annotate i_dquot arrays with __rcu + - ASoC: Intel: ssp-common: Add stub for sof_ssp_get_codec_name + - PCI/P2PDMA: Fix a sleeping issue in a RCU read section + - PCI: switchtec: Fix an error handling path in switchtec_pci_probe() + - crypto: xilinx - call finalize with bh disabled + - drivers/ps3: select VIDEO to provide cmdline functions + - perf thread_map: Free strlist on normal path in thread_map__new_by_tid_str() + - perf srcline: Add missed addr2line closes + - dt-bindings: msm: qcom, mdss: Include ommited fam-b compatible + - drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL_EN + - drm/msm/dpu: Only enable DSC_MODE_MULTIPLEX if dsc_merge is enabled + - drm/radeon/ni: Fix wrong firmware size logging in ni_init_microcode() + - drm/amd/display: fix NULL checks for adev->dm.dc in amdgpu_dm_fini() + - clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks + - clk: renesas: r8a779f0: Correct PFC/GPIO parent clock + - clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 + mux + - ALSA: seq: fix function cast warnings + - perf expr: Fix "has_event" function for metric style events + - perf stat: Avoid metric-only segv + - perf metric: Don't remove scale from counts + - ASoC: meson: aiu: fix function pointer type mismatch + - ASoC: meson: t9015: fix function pointer type mismatch + - powerpc: Force inlining of arch_vmap_p{u/m}d_supported() + - ASoC: SOF: Add some bounds checking to firmware data + - drm: ci: use clk_ignore_unused for apq8016 + - NTB: fix possible name leak in ntb_register_device() + - media: cedrus: h265: Fix configuring bitstream size + - media: sun8i-di: Fix coefficient writes + - media: sun8i-di: Fix power on/off sequences + - media: sun8i-di: Fix chroma difference threshold + - staging: media: starfive: Set 16 bpp for capture_raw device + - media: imx: csc/scaler: fix v4l2_ctrl_handler memory leak + - media: go7007: add check of return value of go7007_read_addr() + - media: pvrusb2: remove redundant NULL check + - media: videobuf2: Add missing doc comment for waiting_in_dqbuf + - media: pvrusb2: fix pvr2_stream_callback casts + - clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times + - drm/amd/display: Add 'replay' NULL check in 'edp_set_replay_allow_active()' + - drm/panel: boe-tv101wum-nl6: make use of prepare_prev_first + - drm/msm/dpu: finalise global state object + - drm/mediatek: dsi: Fix DSI RGB666 formats and definitions + - PCI: Mark 3ware-9650SE Root Port Extended Tags as broken + - drm/bridge: adv7511: fix crash on irq during probe + - pinctrl: renesas: Allow the compiler to optimize away sh_pfc_pm + - clk: hisilicon: hi3519: Release the correct number of gates in + hi3519_clk_unregister() + - clk: hisilicon: hi3559a: Fix an erroneous devm_kfree() + - clk: mediatek: mt8135: Fix an error handling path in + clk_mt8135_apmixed_probe() + - clk: mediatek: mt7622-apmixedsys: Fix an error handling path in + clk_mt8135_apmixed_probe() + - clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF + - clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical + - drm/tegra: put drm_gem_object ref on error in tegra_fb_create + - tty: mips_ejtag_fdc: Fix passing incompatible pointer type warning + - media: ivsc: csi: Swap SINK and SOURCE pads + - media: i2c: imx290: Fix IMX920 typo + - mfd: syscon: Call of_node_put() only when of_parse_phandle() takes a ref + - mfd: altera-sysmgr: Call of_node_put() only when of_parse_phandle() takes a + ref + - perf print-events: make is_event_supported() more robust + - crypto: arm/sha - fix function cast warnings + - crypto: ccp - Avoid discarding errors in psp_send_platform_access_msg() + - crypto: qat - remove unused macros in qat_comp_alg.c + - crypto: qat - removed unused macro in adf_cnv_dbgfs.c + - crypto: qat - avoid division by zero + - crypto: qat - remove double initialization of value + - crypto: qat - fix ring to service map for dcc in 4xxx + - crypto: qat - fix ring to service map for dcc in 420xx + - crypto: jitter - fix CRYPTO_JITTERENTROPY help text + - drm/tidss: Fix initial plane zpos values + - drm/tidss: Fix sync-lost issue with two displays + - clk: imx: imx8mp: Fix SAI_MCLK_SEL definition + - mtd: maps: physmap-core: fix flash size larger than 32-bit + - mtd: rawnand: lpc32xx_mlc: fix irq handler prototype + - mtd: rawnand: brcmnand: exec_op helper functions return type fixes + - ASoC: meson: axg-tdm-interface: fix mclk setup without mclk-fs + - ASoC: meson: axg-tdm-interface: add frame rate constraint + - drm/msm/a6xx: specify UBWC config for sc7180 + - drm/msm/a7xx: Fix LLC typo + - dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition + - perf pmu: Fix a potential memory leak in perf_pmu__lookup() + - HID: amd_sfh: Update HPD sensor structure elements + - HID: amd_sfh: Avoid disabling the interrupt + - drm/amdgpu: Fix missing break in ATOM_ARG_IMM Case of atom_get_src_int() + - media: pvrusb2: fix uaf in pvr2_context_set_notify + - media: dvb-frontends: avoid stack overflow warnings with clang + - media: go7007: fix a memleak in go7007_load_encoder + - media: ttpci: fix two memleaks in budget_av_attach + - media: mediatek: vcodec: avoid -Wcast-function-type-strict warning + - arm64: ftrace: Don't forbid CALL_OPS+CC_OPTIMIZE_FOR_SIZE with Clang + - drm/tests: helpers: Include missing drm_drv header + - drm/amd/pm: Fix esm reg mask use to get pcie speed + - gpio: nomadik: fix offset bug in nmk_pmx_set() + - drm/mediatek: Fix a null pointer crash in mtk_drm_crtc_finish_page_flip + - mfd: cs42l43: Fix wrong register defaults + - powerpc/32: fix ADB_CUDA kconfig warning + - powerpc/pseries: Fix potential memleak in papr_get_attr() + - powerpc/hv-gpci: Fix the H_GET_PERF_COUNTER_INFO hcall return value checks + - clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk' + - clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' + - clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset + - perf vendor events amd: Fix Zen 4 cache latency events + - drm/msm/dpu: allow certain formats for CDM for DP + - drm/msm/dpu: add division of drm_display_mode's hskew parameter + - media: usbtv: Remove useless locks in usbtv_video_free() + - drm/xe: Fix ref counting leak on page fault + - drm/xe: Replace 'grouped target' in Makefile with pattern rule + - lib/stackdepot: fix first entry having a 0-handle + - lib/stackdepot: off by one in depot_fetch_stack() + - modules: wait do_free_init correctly + - mfd: cs42l43: Fix wrong GPIO_FN_SEL and SPI_CLK_CONFIG1 defaults + - power: supply: mm8013: fix "not charging" detection + - powerpc/embedded6xx: Fix no previous prototype for avr_uart_send() etc. + - powerpc/4xx: Fix warp_gpio_leds build failure + - RISC-V: KVM: Forward SEED CSR access to user space + - leds: aw2013: Unlock mutex before destroying it + - leds: sgm3140: Add missing timer cleanup and flash gpio control + - backlight: hx8357: Fix potential NULL pointer dereference + - backlight: ktz8866: Correct the check for of_property_read_u32 + - backlight: lm3630a: Initialize backlight_properties on init + - backlight: lm3630a: Don't set bl->props.brightness in get_brightness + - backlight: da9052: Fully initialize backlight_properties during probe + - backlight: lm3639: Fully initialize backlight_properties during probe + - backlight: lp8788: Fully initialize backlight_properties during probe + - sparc32: Use generic cmpdi2/ucmpdi2 variants + - mtd: maps: sun_uflash: Declare uflash_devinit static + - sparc32: Do not select GENERIC_ISA_DMA + - sparc32: Fix section mismatch in leon_pci_grpci + - clk: Fix clk_core_get NULL dereference + - clk: zynq: Prevent null pointer dereference caused by kmalloc failure + - PCI: brcmstb: Fix broken brcm_pcie_mdio_write() polling + - cifs: Fix writeback data corruption + - ALSA: hda/realtek: fix ALC285 issues on HP Envy x360 laptops + - ALSA: hda/tas2781: use dev_dbg in system_resume + - ALSA: hda/tas2781: add lock to system_suspend + - ALSA: hda/tas2781: do not reset cur_* values in runtime_suspend + - ALSA: hda/tas2781: do not call pm_runtime_force_* in system_resume/suspend + - ALSA: hda/tas2781: restore power state after system_resume + - ALSA: scarlett2: Fix Scarlett 4th Gen 4i4 low-voltage detection + - ALSA: scarlett2: Fix Scarlett 4th Gen autogain status values + - ALSA: scarlett2: Fix Scarlett 4th Gen input gain range + - ALSA: scarlett2: Fix Scarlett 4th Gen input gain range again + - mips: cm: Convert __mips_cm_l2sync_phys_base() to weak function + - platform/x86/intel/pmc/lnl: Remove SSRAM support + - platform/x86/intel/pmc/arl: Put GNA device in D3 + - platform/x86/amd/pmf: Do not use readl() for policy buffer access + - ALSA: usb-audio: Stop parsing channels bits when all channels are found. + - phy: qcom: qmp-usb: split USB-C PHY driver + - phy: qcom: qmp-usbc: add support for the Type-C handling + - phy: qcom: qmp-usbc: handle CLAMP register in a correct way + - scsi: hisi_sas: Fix a deadlock issue related to automatic dump + - RDMA/irdma: Remove duplicate assignment + - RDMA/srpt: Do not register event handler until srpt device is fully setup + - f2fs: compress: fix to guarantee persisting compressed blocks by CP + - f2fs: compress: fix to cover normal cluster write with cp_rwsem + - f2fs: compress: fix to check unreleased compressed cluster + - f2fs: compress: fix to avoid inconsistence bewteen i_blocks and dnode + - f2fs: fix to remove unnecessary f2fs_bug_on() to avoid panic + - f2fs: zone: fix to wait completion of last bio in zone correctly + - f2fs: fix NULL pointer dereference in f2fs_submit_page_write() + - f2fs: compress: fix to cover f2fs_disable_compressed_file() w/ i_sem + - f2fs: fix to avoid potential panic during recovery + - scsi: csiostor: Avoid function pointer casts + - i3c: dw: Disable IBI IRQ depends on hot-join and SIR enabling + - RDMA/hns: Fix mis-modifying default congestion control algorithm + - RDMA/device: Fix a race between mad_client and cm_client init + - RDMA/rtrs-clt: Check strnlen return len in sysfs mpath_policy_store() + - scsi: bfa: Fix function pointer type mismatch for hcb_qe->cbfn + - f2fs: fix to create selinux label during whiteout initialization + - f2fs: compress: fix to check zstd compress level correctly in mount option + - net: sunrpc: Fix an off by one in rpc_sockaddr2uaddr() + - NFSv4.2: fix nfs4_listxattr kernel BUG at mm/usercopy.c:102 + - NFSv4.2: fix listxattr maximum XDR buffer size + - f2fs: compress: fix to check compress flag w/ .i_sem lock + - f2fs: check number of blocks in a current section + - watchdog: starfive: Check pm_runtime_enabled() before decrementing usage + counter + - watchdog: stm32_iwdg: initialize default timeout + - f2fs: fix to use correct segment type in f2fs_allocate_data_block() + - f2fs: ro: compress: fix to avoid caching unaligned extent + - RDMA/mana_ib: Fix bug in creation of dma regions + - RDMA/mana_ib: Introduce mdev_to_gc helper function + - RDMA/mana_ib: Introduce mana_ib_get_netdev helper function + - RDMA/mana_ib: Introduce mana_ib_install_cq_cb helper function + - RDMA/mana_ib: Use virtual address in dma regions for MRs + - Input: iqs7222 - add support for IQS7222D v1.1 and v1.2 + - NFS: Fix nfs_netfs_issue_read() xarray locking for writeback interrupt + - NFS: Fix an off by one in root_nfs_cat() + - NFSv4.1/pnfs: fix NFS with TLS in pnfs + - ACPI: HMAT: Remove register of memory node for generic target + - f2fs: compress: relocate some judgments in f2fs_reserve_compress_blocks + - f2fs: compress: fix reserve_cblocks counting error when out of space + - f2fs: fix to truncate meta inode pages forcely + - f2fs: zone: fix to remove pow2 check condition for zoned block device + - cxl: Fix the incorrect assignment of SSLBIS entry pointer initial location + - perf/x86/amd/core: Avoid register reset when CPU is dead + - afs: Revert "afs: Hide silly-rename files from userspace" + - afs: Don't cache preferred address + - afs: Fix occasional rmdir-then-VNOVNODE with generic/011 + - f2fs: fix to avoid use-after-free issue in f2fs_filemap_fault + - nfs: fix panic when nfs4_ff_layout_prepare_ds() fails + - ovl: relax WARN_ON in ovl_verify_area() + - io_uring/net: correct the type of variable + - remoteproc: stm32: Fix incorrect type in assignment for va + - remoteproc: stm32: Fix incorrect type assignment returned by + stm32_rproc_get_loaded_rsc_tablef + - iio: pressure: mprls0025pa fix off-by-one enum + - usb: phy: generic: Get the vbus supply + - tty: vt: fix 20 vs 0x20 typo in EScsiignore + - serial: max310x: fix syntax error in IRQ error message + - tty: serial: samsung: fix tx_empty() to return TIOCSER_TEMT + - arm64: dts: broadcom: bcmbca: bcm4908: drop invalid switch cells + - coresight: Fix issue where a source device's helpers aren't disabled + - coresight: etm4x: Set skip_power_up in etm4_init_arch_data function + - xhci: Add interrupt pending autoclear flag to each interrupter + - xhci: make isoc_bei_interval variable interrupter specific. + - xhci: remove unnecessary event_ring_deq parameter from xhci_handle_event() + - xhci: update event ring dequeue pointer position to controller correctly + - coccinelle: device_attr_show: Remove useless expression STR + - kconfig: fix infinite loop when expanding a macro at the end of file + - iio: gts-helper: Fix division loop + - bus: mhi: ep: check the correct variable in mhi_ep_register_controller() + - hwtracing: hisi_ptt: Move type check to the beginning of + hisi_ptt_pmu_event_init() + - rtc: mt6397: select IRQ_DOMAIN instead of depending on it + - rtc: max31335: fix interrupt status reg + - serial: 8250_exar: Don't remove GPIO device on suspend + - staging: greybus: fix get_channel_from_mode() failure path + - mei: vsc: Call wake_up() in the threaded IRQ handler + - mei: vsc: Don't use sleeping condition in wait_event_timeout() + - usb: gadget: net2272: Use irqflags in the call to net2272_probe_fin + - char: xilinx_hwicap: Fix NULL vs IS_ERR() bug + - x86/hyperv: Use per cpu initial stack for vtl context + - ASoC: tlv320adc3xxx: Don't strip remove function when driver is builtin + - thermal/drivers/mediatek/lvts_thermal: Fix a memory leak in an error + handling path + - thermal/drivers/qoriq: Fix getting tmu range + - io_uring: don't save/restore iowait state + - spi: lpspi: Avoid potential use-after-free in probe() + - spi: Restore delays for non-GPIO chip select + - ASoC: rockchip: i2s-tdm: Fix inaccurate sampling rates + - nouveau: reset the bo resource bus info after an eviction + - tcp: Fix NEW_SYN_RECV handling in inet_twsk_purge() + - rds: tcp: Fix use-after-free of net in reqsk_timer_handler(). + - octeontx2-af: Use matching wake_up API variant in CGX command interface + - s390/vtime: fix average steal time calculation + - net/sched: taprio: proper TCA_TAPRIO_TC_ENTRY_INDEX check + - devlink: Fix devlink parallel commands processing + - riscv: Only check online cpus for emulated accesses + - soc: fsl: dpio: fix kcalloc() argument order + - cpufreq: Fix per-policy boost behavior on SoCs using cpufreq_boost_set_sw() + - io_uring: Fix release of pinned pages when __io_uaddr_map fails + - tcp: Fix refcnt handling in __inet_hash_connect(). + - vmxnet3: Fix missing reserved tailroom + - hsr: Fix uninit-value access in hsr_get_node() + - net: txgbe: fix clk_name exceed MAX_DEV_ID limits + - spi: spi-mem: add statistics support to ->exec_op() calls + - spi: Fix error code checking in spi_mem_exec_op() + - nvme: fix reconnection fail due to reserved tag allocation + - drm/xe: Invalidate userptr VMA on page pin fault + - drm/xe: Skip VMAs pin when requesting signal to the last XE_EXEC + - net: mediatek: mtk_eth_soc: clear MAC_MCR_FORCE_LINK only when MAC is up + - net: ethernet: mtk_eth_soc: fix PPE hanging issue + - io_uring: fix poll_remove stalled req completion + - ASoC: SOF: amd: Move signed_fw_image to struct acp_quirk_entry + - ASoC: SOF: amd: Skip IRAM/DRAM size modification for Steam Deck OLED + - riscv: Fix compilation error with FAST_GUP and rv32 + - xen/evtchn: avoid WARN() when unbinding an event channel + - xen/events: increment refcnt only if event channel is refcounted + - packet: annotate data-races around ignore_outgoing + - xfrm: Allow UDP encapsulation only in offload modes + - net: veth: do not manipulate GRO when using XDP + - net: dsa: mt7530: prevent possible incorrect XTAL frequency selection + - spi: spi-imx: fix off-by-one in mx51 CPU mode burst length + - drm: Fix drm_fixp2int_round() making it add 0.5 + - virtio: uapi: Drop __packed attribute in linux/virtio_pci.h + - vdpa_sim: reset must not run + - vdpa/mlx5: Allow CVQ size changes + - virtio: packed: fix unmap leak for indirect desc table + - net: move dev->state into net_device_read_txrx group + - wireguard: receive: annotate data-race around receiving_counter.counter + - rds: introduce acquire/release ordering in acquire/release_in_xmit() + - hsr: Handle failures in module init + - ipv4: raw: Fix sending packets from raw sockets via IPsec tunnels + - nouveau/gsp: don't check devinit disable on GSP. + - ceph: stop copying to iter at EOF on sync reads + - net: phy: fix phy_read_poll_timeout argument type in genphy_loopback + - dm-integrity: fix a memory leak when rechecking the data + - net/bnx2x: Prevent access to a freed page in page_pool + - devlink: fix port new reply cmd type + - octeontx2: Detect the mbox up or down message via register + - octeontx2-pf: Wait till detach_resources msg is complete + - octeontx2-pf: Use default max_active works instead of one + - octeontx2-pf: Send UP messages to VF only when VF is up. + - octeontx2-af: Use separate handlers for interrupts + - drm/amdgpu: add MMHUB 3.3.1 support + - drm/amdgpu: fix mmhub client id out-of-bounds access + - drm/amdgpu: drop setting buffer funcs in sdma442 + - netfilter: nft_set_pipapo: release elements in clone only from destroy path + - netfilter: nf_tables: do not compare internal table flags on updates + - rcu: add a helper to report consolidated flavor QS + - net: report RCU QS on threaded NAPI repolling + - bpf: report RCU QS in cpumap kthread + - net: dsa: mt7530: fix link-local frames that ingress vlan filtering ports + - net: dsa: mt7530: fix handling of all link-local frames + - netfilter: nf_tables: Fix a memory leak in nf_tables_updchain + - spi: spi-mt65xx: Fix NULL pointer access in interrupt handler + - selftests: forwarding: Fix ping failure due to short timeout + - dm io: Support IO priority + - dm-integrity: align the outgoing bio in integrity_recheck + - x86/efistub: Clear decompressor BSS in native EFI entrypoint + - x86/efistub: Don't clear BSS twice in mixed mode + - printk: Adjust mapping for 32bit seq macros + - printk: Use prb_first_seq() as base for 32bit seq macros + - Linux 6.8.2 + - [Config] updateconfig following v6.8.2 import + + * Provide python perf module (LP: #2051560) + - [Packaging] enable perf python module + - [Packaging] provide a wrapper module for python-perf + + * To support AMD Adaptive Backlight Management (ABM) for power profiles daemon + >= 2.0 (LP: #2056716) + - drm/amd/display: add panel_power_savings sysfs entry to eDP connectors + - drm/amdgpu: respect the abmlevel module parameter value if it is set + + * Miscellaneous Ubuntu changes + - [Config] Disable StarFive JH7100 support + - [Config] Disable Renesas RZ/Five support + - [Config] Disable BINFMT_FLAT for riscv64 + + -- Roxana Nicolescu Wed, 01 May 2024 16:02:05 +0200 + +linux (6.8.0-31.31) noble; urgency=medium + + * noble/linux: 6.8.0-31.31 -proposed tracker (LP: #2062933) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.04.04) + + -- Andrea Righi Fri, 19 Apr 2024 23:46:38 +0200 + +linux (6.8.0-30.30) noble; urgency=medium + + * noble/linux: 6.8.0-30.30 -proposed tracker (LP: #2061893) + + * System unstable, kernel ring buffer flooded with "BUG: Bad page state in + process swapper/0" (LP: #2056706) + - xen-netfront: Add missing skb_mark_for_recycle + + -- Andrea Righi Tue, 16 Apr 2024 21:17:11 +0200 + +linux (6.8.0-29.29) noble; urgency=medium + + * noble/linux: 6.8.0-29.29 -proposed tracker (LP: #2061888) + + * [24.04 FEAT] [SEC2353] zcrypt: extend error recovery to deal with device + scans (LP: #2050019) + - s390/zcrypt: harmonize debug feature calls and defines + - s390/zcrypt: introduce dynamic debugging for AP and zcrypt code + - s390/pkey: harmonize pkey s390 debug feature calls + - s390/pkey: introduce dynamic debugging for pkey + - s390/ap: add debug possibility for AP messages + - s390/zcrypt: add debug possibility for CCA and EP11 messages + - s390/ap: rearm APQNs bindings complete completion + - s390/ap: clarify AP scan bus related functions and variables + - s390/ap: rework ap_scan_bus() to return true on config change + - s390/ap: introduce mutex to lock the AP bus scan + - s390/zcrypt: introduce retries on in-kernel send CPRB functions + - s390/zcrypt: improve zcrypt retry behavior + - s390/pkey: improve pkey retry behavior + + * [24.04 FEAT] Memory hotplug vmem pages (s390x) (LP: #2051835) + - mm/memory_hotplug: introduce MEM_PREPARE_ONLINE/MEM_FINISH_OFFLINE notifiers + - s390/mm: allocate vmemmap pages from self-contained memory range + - s390/sclp: remove unhandled memory notifier type + - s390/mm: implement MEM_PREPARE_ONLINE/MEM_FINISH_OFFLINE notifiers + - s390: enable MHP_MEMMAP_ON_MEMORY + - [Config] enable CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE and + CONFIG_MHP_MEMMAP_ON_MEMORY for s390x + + -- Paolo Pisati Tue, 16 Apr 2024 20:32:09 +0200 + +linux (6.8.0-28.28) noble; urgency=medium + + * noble/linux: 6.8.0-28.28 -proposed tracker (LP: #2061867) + + * linux-gcp 6.8.0-1005.5 (+ others) Noble kernel regression iwth new apparmor + profiles/features (LP: #2061851) + - SAUCE: apparmor4.0.0 [92/90]: fix address mapping for recvfrom + + -- Paolo Pisati Tue, 16 Apr 2024 18:29:17 +0200 + +linux (6.8.0-25.25) noble; urgency=medium + + * noble/linux: 6.8.0-25.25 -proposed tracker (LP: #2061083) + + * Packaging resync (LP: #1786013) + - [Packaging] debian.master/dkms-versions -- update from kernel-versions + (main/d2024.04.04) + + * Apply mitigations for the native BHI hardware vulnerabilty (LP: #2060909) + - x86/cpufeatures: Add new word for scattered features + - x86/bugs: Change commas to semicolons in 'spectre_v2' sysfs file + - x86/syscall: Don't force use of indirect calls for system calls + - x86/bhi: Add support for clearing branch history at syscall entry + - x86/bhi: Define SPEC_CTRL_BHI_DIS_S + - x86/bhi: Enumerate Branch History Injection (BHI) bug + - x86/bhi: Add BHI mitigation knob + - x86/bhi: Mitigate KVM by default + - KVM: x86: Add BHI_NO + - x86: set SPECTRE_BHI_ON as default + - [Config] enable spectre_bhi=auto by default + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [01/90]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/90]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/90]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/90]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/90]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/90]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/90]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/90]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/90]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/90]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/90]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/90]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/90]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/90]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/90]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/90]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/90]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/90]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/90]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/90]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/90]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/90]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/90]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/90]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/90]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/90]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/90]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/90]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/90]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [31/90]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/90]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/90]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/90]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/90]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/90]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/90]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/90]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/90]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/90]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/90]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/90]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [43/90]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/90]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/90]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/90]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/90]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/90]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/90]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/90]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/90]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/90]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/90]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/90]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/90]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/90]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/90]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/90]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/90]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/90]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/90]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/90]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/90]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/90]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/90] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/90]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/90]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/90]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/90]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/90]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/90]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/90]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/90]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/90]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/90]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/90]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/90]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/90]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/90]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/90]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/90]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/90]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/90]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/90]: fixup notify + - SAUCE: apparmor4.0.0 [88/90]: apparmor: add fine grained ipv4/ipv6 mediation + - SAUCE: apparmor4.0.0 [89/90]:apparmor: disable tailglob responses for now + - SAUCE: apparmor4.0.0 [90/90]: apparmor: Fix notify build warnings + - SAUCE: apparmor4.0.0: fix reserved mem for when we save ipv6 addresses + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/90]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/90]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/90]: userns - make it so special unconfined + profiles can mediate user namespaces + + * [MTL] x86: Fix Cache info sysfs is not populated (LP: #2049793) + - SAUCE: cacheinfo: Check for null last-level cache info + - SAUCE: cacheinfo: Allocate memory for memory if not done from the primary + CPU + - SAUCE: x86/cacheinfo: Delete global num_cache_leaves + - SAUCE: x86/cacheinfo: Clean out init_cache_level() + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0: LSM stacking v39: fix build error with + CONFIG_SECURITY=n + - [Config] toolchain version update + + -- Paolo Pisati Fri, 12 Apr 2024 10:42:33 +0200 + +linux (6.8.0-22.22) noble; urgency=medium + + * noble/linux: 6.8.0-22.22 -proposed tracker (LP: #2060238) + + -- Andrea Righi Thu, 04 Apr 2024 23:00:49 +0200 + +linux (6.8.0-21.21) noble; urgency=medium + + * noble/linux: 6.8.0-21.21 -proposed tracker (LP: #2060225) + + * Miscellaneous Ubuntu changes + - [Config] update toolchain version in annotations + + -- Andrea Righi Thu, 04 Apr 2024 22:20:27 +0200 + +linux (6.8.0-20.20) noble; urgency=medium + + * noble/linux: 6.8.0-20.20 -proposed tracker (LP: #2058221) + + * Noble update: v6.8.1 upstream stable release (LP: #2058224) + - x86/mmio: Disable KVM mitigation when X86_FEATURE_CLEAR_CPU_BUF is set + - Documentation/hw-vuln: Add documentation for RFDS + - x86/rfds: Mitigate Register File Data Sampling (RFDS) + - KVM/x86: Export RFDS_NO and RFDS_CLEAR to guests + - Linux 6.8.1 + + * Autopkgtest failures on amd64 (LP: #2048768) + - [Packaging] update to clang-18 + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0: LSM stacking v39: fix build error with + CONFIG_SECURITY=n + - [Config] amd64: MITIGATION_RFDS=y + + -- Paolo Pisati Mon, 18 Mar 2024 11:08:14 +0100 + +linux (6.8.0-19.19) noble; urgency=medium + + * noble/linux: 6.8.0-19.19 -proposed tracker (LP: #2057910) + + * Miscellaneous Ubuntu changes + - [Packaging] re-introduce linux-doc as an empty package + + -- Paolo Pisati Thu, 14 Mar 2024 14:36:14 +0100 + +linux (6.8.0-18.18) noble; urgency=medium + + * noble/linux: 6.8.0-18.18 -proposed tracker (LP: #2057456) + + * Miscellaneous Ubuntu changes + - [Packaging] drop dependency on libclang-17 + + -- Paolo Pisati Tue, 12 Mar 2024 14:44:13 +0100 + +linux (6.8.0-17.17) noble; urgency=medium + + * noble/linux: 6.8.0-17.17 -proposed tracker (LP: #2056745) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Add debian/control sanity check" + + -- Paolo Pisati Mon, 11 Mar 2024 12:46:38 +0100 + +linux (6.8.0-16.16) noble; urgency=medium + + * noble/linux: 6.8.0-16.16 -proposed tracker (LP: #2056738) + + * left-over ceph debugging printks (LP: #2056616) + - Revert "UBUNTU: SAUCE: ceph: make sure all the files successfully put before + unmounting" + + * qat: Improve error recovery flows (LP: #2056354) + - crypto: qat - add heartbeat error simulator + - crypto: qat - disable arbitration before reset + - crypto: qat - update PFVF protocol for recovery + - crypto: qat - re-enable sriov after pf reset + - crypto: qat - add fatal error notification + - crypto: qat - add auto reset on error + - crypto: qat - limit heartbeat notifications + - crypto: qat - improve aer error reset handling + - crypto: qat - change SLAs cleanup flow at shutdown + - crypto: qat - resolve race condition during AER recovery + - Documentation: qat: fix auto_reset section + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [01/87]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/87]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/87]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/87]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/87]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/87]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/87]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/87]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/87]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/87]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/87]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/87]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/87]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/87]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/87]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/87]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/87]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/87]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/87]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/87]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/87]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/87]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/87]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/87]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/87]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/87]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/87]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/87]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/87]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [31/87]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/87]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/87]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/87]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/87]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/87]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/87]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/87]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/87]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/87]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/87]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/87]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [43/87]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/87]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/87]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/87]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/87]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/87]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/87]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/87]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/87]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/87]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/87]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/87]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/87]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/87]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/87]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/87]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/87]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/87]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/87]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/87]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/87]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/87]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/87] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/87]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/87]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/87]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/87]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/87]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/87]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/87]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/87]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/87]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/87]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/87]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/87]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/87]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/87]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/87]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/87]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/87]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/87]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/87]: fixup notify + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/87]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/87]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/87]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Enable lowlatency settings in the generic kernel (LP: #2051342) + - [Config] enable low-latency settings + + * hwmon: (coretemp) Fix core count limitation (LP: #2056126) + - hwmon: (coretemp) Introduce enum for attr index + - hwmon: (coretemp) Remove unnecessary dependency of array index + - hwmon: (coretemp) Replace sensor_device_attribute with device_attribute + - hwmon: (coretemp) Remove redundant pdata->cpu_map[] + - hwmon: (coretemp) Abstract core_temp helpers + - hwmon: (coretemp) Split package temp_data and core temp_data + - hwmon: (coretemp) Remove redundant temp_data->is_pkg_data + - hwmon: (coretemp) Use dynamic allocated memory for core temp_data + + * Miscellaneous Ubuntu changes + - [Config] Disable CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION + - [Packaging] remove debian/scripts/misc/arch-has-odm-enabled.sh + - rebase on v6.8 + - [Config] toolchain version update + + * Miscellaneous upstream changes + - crypto: qat - add fatal error notify method + + * Rebase on v6.8 + + -- Paolo Pisati Mon, 11 Mar 2024 10:14:10 +0100 + +linux (6.8.0-15.15) noble; urgency=medium + + * noble/linux: 6.8.0-15.15 -proposed tracker (LP: #2055871) + + * Miscellaneous Ubuntu changes + - rebase on v6.8-rc7 + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] Transition laptop-23.10 to generic" + + * Rebase on v6.8-rc7 + + -- Paolo Pisati Mon, 04 Mar 2024 11:50:51 +0100 + +linux (6.8.0-14.14) noble; urgency=medium + + * noble/linux: 6.8.0-14.14 -proposed tracker (LP: #2055551) + + * Please change CONFIG_CONSOLE_LOGLEVEL_QUIET to 3 (LP: #2049390) + - [Config] reduce verbosity when booting in quiet mode + + * linux: please move erofs.ko (CONFIG_EROFS for EROFS support) from linux- + modules-extra to linux-modules (LP: #2054809) + - UBUNTU [Packaging]: Include erofs in linux-modules instead of linux-modules- + extra + + * linux: please move dmi-sysfs.ko (CONFIG_DMI_SYSFS for SMBIOS support) from + linux-modules-extra to linux-modules (LP: #2045561) + - [Packaging] Move dmi-sysfs.ko into linux-modules + + * Enable CONFIG_INTEL_IOMMU_DEFAULT_ON and + CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON (LP: #1951440) + - [Config] enable Intel DMA remapping by default + + * disable Intel DMA remapping by default (LP: #1971699) + - [Config] update tracking bug for CONFIG_INTEL_IOMMU_DEFAULT_ON + + * Packaging resync (LP: #1786013) + - debian.master/dkms-versions -- update from kernel-versions + (main/d2024.02.29) + + * Miscellaneous Ubuntu changes + - SAUCE: modpost: Replace 0-length array with flex-array member + - [packaging] do not include debian/ directory in a binary package + - [packaging] remove debian/stamps/keep-dir + + -- Paolo Pisati Fri, 01 Mar 2024 11:45:12 +0100 + +linux (6.8.0-13.13) noble; urgency=medium + + * noble/linux: 6.8.0-13.13 -proposed tracker (LP: #2055421) + + * Packaging resync (LP: #1786013) + - debian.master/dkms-versions -- update from kernel-versions + (main/d2024.02.29) + + * Miscellaneous Ubuntu changes + - rebase on v6.8-rc6 + - [Config] updateconfifs following v6.8-rc6 rebase + + * Rebase on v6.8-rc6 + + -- Paolo Pisati Thu, 29 Feb 2024 15:02:24 +0100 + +linux (6.8.0-12.12) noble; urgency=medium + + * linux-tools-common: man page of usbip[d] is misplaced (LP: #2054094) + - [Packaging] rules: Put usbip manpages in the correct directory + + * Validate connection interval to pass Bluetooth Test Suite (LP: #2052005) + - Bluetooth: Enforce validation on max value of connection interval + + * Turning COMPAT_32BIT_TIME off on s390x (LP: #2038583) + - [Config] Turn off 31-bit COMPAT on s390x + + * Don't produce linux-source binary package (LP: #2043994) + - [Packaging] Add debian/control sanity check + + * Don't produce linux-*-source- package (LP: #2052439) + - [Packaging] Move linux-source package stub to debian/control.d + - [Packaging] Build linux-source package only for the main kernel + + * Don't produce linux-*-cloud-tools-common, linux-*-tools-common and + linux-*-tools-host binary packages (LP: #2048183) + - [Packaging] Move indep tools package stubs to debian/control.d + - [Packaging] Build indep tools packages only for the main kernel + + * Enable CONFIG_INTEL_IOMMU_DEFAULT_ON and + CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON (LP: #1951440) + - [Config] enable Intel DMA remapping by default + + * disable Intel DMA remapping by default (LP: #1971699) + - [Config] update tracking bug for CONFIG_INTEL_IOMMU_DEFAULT_ON + + * Miscellaneous Ubuntu changes + - [Packaging] Transition laptop-23.10 to generic + + -- Paolo Pisati Thu, 22 Feb 2024 14:31:00 +0100 + +linux (6.8.0-11.11) noble; urgency=medium + + * noble/linux: 6.8.0-11.11 -proposed tracker (LP: #2053094) + + * Miscellaneous Ubuntu changes + - [Packaging] riscv64: disable building unnecessary binary debs + + -- Paolo Pisati Wed, 14 Feb 2024 00:04:31 +0100 + +linux (6.8.0-10.10) noble; urgency=medium + + * noble/linux: 6.8.0-10.10 -proposed tracker (LP: #2053015) + + * Miscellaneous Ubuntu changes + - [Packaging] add Rust build-deps for riscv64 + + * Miscellaneous upstream changes + - Revert "Revert "UBUNTU: [Packaging] temporarily disable Rust dependencies on + riscv64"" + + -- Paolo Pisati Tue, 13 Feb 2024 13:23:47 +0100 + +linux (6.8.0-9.9) noble; urgency=medium + + * noble/linux: 6.8.0-9.9 -proposed tracker (LP: #2052945) + + * Miscellaneous upstream changes + - Revert "UBUNTU: [Packaging] temporarily disable Rust dependencies on + riscv64" + + -- Paolo Pisati Mon, 12 Feb 2024 15:49:20 +0100 + +linux (6.8.0-8.8) noble; urgency=medium + + * noble/linux: 6.8.0-8.8 -proposed tracker (LP: #2052918) + + * Miscellaneous Ubuntu changes + - [Packaging] riscv64: enable linux-libc-dev build + - v6.8-rc4 rebase + + * Rebase on v6.8-rc4 + + -- Paolo Pisati Mon, 12 Feb 2024 10:13:34 +0100 + +linux (6.8.0-7.7) noble; urgency=medium + + * noble/linux: 6.8.0-7.7 -proposed tracker (LP: #2052691) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [01/87]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/87]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/87]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/87]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/87]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/87]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/87]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/87]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/87]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/87]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/87]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/87]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/87]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/87]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/87]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/87]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/87]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/87]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/87]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/87]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/87]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/87]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/87]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/87]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/87]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/87]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/87]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/87]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/87]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [31/87]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/87]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/87]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/87]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/87]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/87]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/87]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/87]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/87]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/87]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/87]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/87]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [43/87]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/87]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/87]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/87]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/87]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/87]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/87]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/87]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/87]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/87]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/87]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/87]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/87]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/87]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/87]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/87]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/87]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/87]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/87]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/87]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/87]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/87]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [65/87] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [69/87]: add io_uring mediation + - SAUCE: apparmor4.0.0 [70/87]: apparmor: fix oops when racing to retrieve + notification + - SAUCE: apparmor4.0.0 [71/87]: apparmor: fix notification header size + - SAUCE: apparmor4.0.0 [72/87]: apparmor: fix request field from a prompt + reply that denies all access + - SAUCE: apparmor4.0.0 [73/87]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + - SAUCE: apparmor4.0.0 [74/87]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/87]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/87]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/87]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/87]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/87]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/87]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/87]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/87]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/87]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/87]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/87]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/87]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/87]: fixup notify + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/87]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/87]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/87]: userns - make it so special unconfined + profiles can mediate user namespaces + + -- Paolo Pisati Thu, 08 Feb 2024 12:05:44 +0100 + +linux (6.8.0-6.6) noble; urgency=medium + + * noble/linux: 6.8.0-6.6 -proposed tracker (LP: #2052592) + + * Packaging resync (LP: #1786013) + - debian.master/dkms-versions -- update from kernel-versions + (main/d2024.02.07) + - [Packaging] update variants + + * FIPS kernels should default to fips mode (LP: #2049082) + - SAUCE: Enable fips mode by default, in FIPS kernels only + + * Fix snapcraftyaml.yaml for jammy:linux-raspi (LP: #2051468) + - [Packaging] Remove old snapcraft.yaml + + * Azure: Fix regression introduced in LP: #2045069 (LP: #2052453) + - hv_netvsc: Register VF in netvsc_probe if NET_DEVICE_REGISTER missed + + * Miscellaneous Ubuntu changes + - [Packaging] Remove in-tree abi checks + - [Packaging] drop abi files with clean + - [Packaging] Remove do_full_source variable (fixup) + - [Packaging] Remove update-dkms-versions and move dkms-versions + - [Config] updateconfigs following v6.8-rc3 rebase + - [packaging] rename to linux + - [packaging] rebase on v6.8-rc3 + - [packaging] disable signing for ppc64el + + * Rebase on v6.8-rc3 + + -- Paolo Pisati Wed, 07 Feb 2024 15:13:52 +0100 + +linux (6.8.0-5.5) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-5.5 -proposed tracker (LP: #2052136) + + * Miscellaneous upstream changes + - Revert "mm/sparsemem: fix race in accessing memory_section->usage" + + -- Paolo Pisati Fri, 02 Feb 2024 12:59:09 +0100 + +linux-unstable (6.8.0-4.4) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-4.4 -proposed tracker (LP: #2051502) + + * Migrate from fbdev drivers to simpledrm and DRM fbdev emulation layer + (LP: #1965303) + - [Config] enable simpledrm and DRM fbdev emulation layer + + * Miscellaneous Ubuntu changes + - [Config] toolchain update + + * Miscellaneous upstream changes + - rust: upgrade to Rust 1.75.0 + + -- Paolo Pisati Mon, 29 Jan 2024 14:49:49 +0100 + +linux-unstable (6.8.0-3.3) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-3.3 -proposed tracker (LP: #2051488) + + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor4.0.0 [43/87]: LSM stacking v39: UBUNTU: SAUCE: apparmor4.0.0 + [12/95]: add/use fns to print hash string hex value + - SAUCE: apparmor4.0.0 [44/87]: patch to provide compatibility with v2.x net + rules + - SAUCE: apparmor4.0.0 [45/87]: add unpriviled user ns mediation + - SAUCE: apparmor4.0.0 [46/87]: Add sysctls for additional controls of unpriv + userns restrictions + - SAUCE: apparmor4.0.0 [47/87]: af_unix mediation + - SAUCE: apparmor4.0.0 [48/87]: Add fine grained mediation of posix mqueues + - SAUCE: apparmor4.0.0 [49/87]: setup slab cache for audit data + - SAUCE: apparmor4.0.0 [50/87]: Improve debug print infrastructure + - SAUCE: apparmor4.0.0 [51/87]: add the ability for profiles to have a + learning cache + - SAUCE: apparmor4.0.0 [52/87]: enable userspace upcall for mediation + - SAUCE: apparmor4.0.0 [53/87]: prompt - lock down prompt interface + - SAUCE: apparmor4.0.0 [54/87]: prompt - allow controlling of caching of a + prompt response + - SAUCE: apparmor4.0.0 [55/87]: prompt - add refcount to audit_node in prep or + reuse and delete + - SAUCE: apparmor4.0.0 [56/87]: prompt - refactor to moving caching to + uresponse + - SAUCE: apparmor4.0.0 [57/87]: prompt - Improve debug statements + - SAUCE: apparmor4.0.0 [58/87]: prompt - fix caching + - SAUCE: apparmor4.0.0 [59/87]: prompt - rework build to use append fn, to + simplify adding strings + - SAUCE: apparmor4.0.0 [60/87]: prompt - refcount notifications + - SAUCE: apparmor4.0.0 [61/87]: prompt - add the ability to reply with a + profile name + - SAUCE: apparmor4.0.0 [62/87]: prompt - fix notification cache when updating + - SAUCE: apparmor4.0.0 [63/87]: prompt - add tailglob on name for cache + support + - SAUCE: apparmor4.0.0 [64/87]: prompt - allow profiles to set prompts as + interruptible + - SAUCE: apparmor4.0.0 [69/87]: add io_uring mediation + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + + * apparmor restricts read access of user namespace mediation sysctls to root + (LP: #2040194) + - SAUCE: apparmor4.0.0 [73/87]: apparmor: open userns related sysctl so lxc + can check if restriction are in place + + * AppArmor spams kernel log with assert when auditing (LP: #2040192) + - SAUCE: apparmor4.0.0 [72/87]: apparmor: fix request field from a prompt + reply that denies all access + + * apparmor notification files verification (LP: #2040250) + - SAUCE: apparmor4.0.0 [71/87]: apparmor: fix notification header size + + * apparmor oops when racing to retrieve a notification (LP: #2040245) + - SAUCE: apparmor4.0.0 [70/87]: apparmor: fix oops when racing to retrieve + notification + + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in mantic + (LP: #2032602) + - SAUCE: apparmor4.0.0 [66/87]: prompt - add support for advanced filtering of + notifications + - SAUCE: apparmor4.0.0 [67/87]: userns - add the ability to reference a global + variable for a feature value + - SAUCE: apparmor4.0.0 [68/87]: userns - make it so special unconfined + profiles can mediate user namespaces + + * Miscellaneous Ubuntu changes + - SAUCE: apparmor4.0.0 [01/87]: LSM stacking v39: integrity: disassociate + ima_filter_rule from security_audit_rule + - SAUCE: apparmor4.0.0 [02/87]: LSM stacking v39: SM: Infrastructure + management of the sock security + - SAUCE: apparmor4.0.0 [03/87]: LSM stacking v39: LSM: Add the lsmblob data + structure. + - SAUCE: apparmor4.0.0 [04/87]: LSM stacking v39: IMA: avoid label collisions + with stacked LSMs + - SAUCE: apparmor4.0.0 [05/87]: LSM stacking v39: LSM: Use lsmblob in + security_audit_rule_match + - SAUCE: apparmor4.0.0 [06/87]: LSM stacking v39: LSM: Add lsmblob_to_secctx + hook + - SAUCE: apparmor4.0.0 [07/87]: LSM stacking v39: Audit: maintain an lsmblob + in audit_context + - SAUCE: apparmor4.0.0 [08/87]: LSM stacking v39: LSM: Use lsmblob in + security_ipc_getsecid + - SAUCE: apparmor4.0.0 [09/87]: LSM stacking v39: Audit: Update shutdown LSM + data + - SAUCE: apparmor4.0.0 [10/87]: LSM stacking v39: LSM: Use lsmblob in + security_current_getsecid + - SAUCE: apparmor4.0.0 [11/87]: LSM stacking v39: LSM: Use lsmblob in + security_inode_getsecid + - SAUCE: apparmor4.0.0 [12/87]: LSM stacking v39: Audit: use an lsmblob in + audit_names + - SAUCE: apparmor4.0.0 [13/87]: LSM stacking v39: LSM: Create new + security_cred_getlsmblob LSM hook + - SAUCE: apparmor4.0.0 [14/87]: LSM stacking v39: Audit: Change context data + from secid to lsmblob + - SAUCE: apparmor4.0.0 [15/87]: LSM stacking v39: Netlabel: Use lsmblob for + audit data + - SAUCE: apparmor4.0.0 [16/87]: LSM stacking v39: LSM: Ensure the correct LSM + context releaser + - SAUCE: apparmor4.0.0 [17/87]: LSM stacking v39: LSM: Use lsmcontext in + security_secid_to_secctx + - SAUCE: apparmor4.0.0 [18/87]: LSM stacking v39: LSM: Use lsmcontext in + security_lsmblob_to_secctx + - SAUCE: apparmor4.0.0 [19/87]: LSM stacking v39: LSM: Use lsmcontext in + security_inode_getsecctx + - SAUCE: apparmor4.0.0 [20/87]: LSM stacking v39: LSM: Use lsmcontext in + security_dentry_init_security + - SAUCE: apparmor4.0.0 [21/87]: LSM stacking v39: LSM: + security_lsmblob_to_secctx module selection + - SAUCE: apparmor4.0.0 [22/87]: LSM stacking v39: Audit: Create audit_stamp + structure + - SAUCE: apparmor4.0.0 [23/87]: LSM stacking v39: Audit: Allow multiple + records in an audit_buffer + - SAUCE: apparmor4.0.0 [24/87]: LSM stacking v39: Audit: Add record for + multiple task security contexts + - SAUCE: apparmor4.0.0 [25/87]: LSM stacking v39: audit: multiple subject lsm + values for netlabel + - SAUCE: apparmor4.0.0 [26/87]: LSM stacking v39: Audit: Add record for + multiple object contexts + - SAUCE: apparmor4.0.0 [27/87]: LSM stacking v39: LSM: Remove unused + lsmcontext_init() + - SAUCE: apparmor4.0.0 [28/87]: LSM stacking v39: LSM: Improve logic in + security_getprocattr + - SAUCE: apparmor4.0.0 [29/87]: LSM stacking v39: LSM: secctx provider check + on release + - SAUCE: apparmor4.0.0 [30/87]: LSM stacking v39: LSM: Single calls in + socket_getpeersec hooks + - SAUCE: apparmor4.0.0 [31/87]: LSM stacking v39: LSM: Exclusive secmark usage + - SAUCE: apparmor4.0.0 [32/87]: LSM stacking v39: LSM: Identify which LSM + handles the context string + - SAUCE: apparmor4.0.0 [33/87]: LSM stacking v39: AppArmor: Remove the + exclusive flag + - SAUCE: apparmor4.0.0 [34/87]: LSM stacking v39: LSM: Add mount opts blob + size tracking + - SAUCE: apparmor4.0.0 [35/87]: LSM stacking v39: LSM: allocate mnt_opts blobs + instead of module specific data + - SAUCE: apparmor4.0.0 [36/87]: LSM stacking v39: LSM: Infrastructure + management of the key security blob + - SAUCE: apparmor4.0.0 [37/87]: LSM stacking v39: LSM: Infrastructure + management of the mnt_opts security blob + - SAUCE: apparmor4.0.0 [38/87]: LSM stacking v39: LSM: Correct handling of + ENOSYS in inode_setxattr + - SAUCE: apparmor4.0.0 [39/87]: LSM stacking v39: LSM: Remove lsmblob + scaffolding + - SAUCE: apparmor4.0.0 [40/87]: LSM stacking v39: LSM: Allow reservation of + netlabel + - SAUCE: apparmor4.0.0 [41/87]: LSM stacking v39: LSM: restrict + security_cred_getsecid() to a single LSM + - SAUCE: apparmor4.0.0 [42/87]: LSM stacking v39: Smack: Remove + LSM_FLAG_EXCLUSIVE + - SAUCE: apparmor4.0.0 [65/87] v6.8 prompt:fixup interruptible + - SAUCE: apparmor4.0.0 [74/87]: apparmor: cleanup attachment perm lookup to + use lookup_perms() + - SAUCE: apparmor4.0.0 [75/87]: apparmor: remove redundant unconfined check. + - SAUCE: apparmor4.0.0 [76/87]: apparmor: switch signal mediation to using + RULE_MEDIATES + - SAUCE: apparmor4.0.0 [77/87]: apparmor: ensure labels with more than one + entry have correct flags + - SAUCE: apparmor4.0.0 [78/87]: apparmor: remove explicit restriction that + unconfined cannot use change_hat + - SAUCE: apparmor4.0.0 [79/87]: apparmor: cleanup: refactor file_perm() to + provide semantics of some checks + - SAUCE: apparmor4.0.0 [80/87]: apparmor: carry mediation check on label + - SAUCE: apparmor4.0.0 [81/87]: apparmor: convert easy uses of unconfined() to + label_mediates() + - SAUCE: apparmor4.0.0 [82/87]: apparmor: add additional flags to extended + permission. + - SAUCE: apparmor4.0.0 [83/87]: apparmor: add support for profiles to define + the kill signal + - SAUCE: apparmor4.0.0 [84/87]: apparmor: fix x_table_lookup when stacking is + not the first entry + - SAUCE: apparmor4.0.0 [85/87]: apparmor: allow profile to be transitioned + when a user ns is created + - SAUCE: apparmor4.0.0 [86/87]: apparmor: add ability to mediate caps with + policy state machine + - SAUCE: apparmor4.0.0 [87/87]: fixup notify + - [Config] updateconfigs following v6.8-rc2 rebase + + -- Paolo Pisati Mon, 29 Jan 2024 08:59:32 +0100 + +linux-unstable (6.8.0-2.2) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-2.2 -proposed tracker (LP: #2051110) + + * Miscellaneous Ubuntu changes + - [Config] toolchain update + - [Config] enable Rust + + -- Paolo Pisati Wed, 24 Jan 2024 13:10:07 +0100 + +linux-unstable (6.8.0-1.1) noble; urgency=medium + + * noble/linux-unstable: 6.8.0-1.1 -proposed tracker (LP: #2051102) + + * Miscellaneous Ubuntu changes + - [packaging] move to v6.8-rc1 + - [Config] updateconfigs following v6.8-rc1 rebase + - SAUCE: export file_close_fd() instead of close_fd_get_file() + - SAUCE: cpufreq: s/strlcpy/strscpy/ + - debian/dkms-versions -- temporarily disable zfs dkms + - debian/dkms-versions -- temporarily disable ipu6 and isvsc dkms + - debian/dkms-versions -- temporarily disable v4l2loopback + + -- Paolo Pisati Wed, 24 Jan 2024 10:48:37 +0100 + +linux-unstable (6.8.0-0.0) noble; urgency=medium + + * Empty entry. + + -- Paolo Pisati Tue, 23 Jan 2024 11:36:40 +0100 --- linux-nvidia-7.0.0.orig/debian.master/config/README.rst +++ linux-nvidia-7.0.0/debian.master/config/README.rst @@ -0,0 +1,185 @@ +================== +Config Annotations +================== + +:Author: Andrea Righi + +Overview +======== + +Each Ubuntu kernel needs to maintain its own .config for each supported +architecture and each flavour. + +Every time a new patch is applied or a kernel is rebased on top of a new +one, we need to update the .config's accordingly (config options can be +added, removed and also renamed). + +So, we need to make sure that some critical config options are always +matching the desired value in order to have a functional kernel. + +State of the art +================ + +At the moment configs are maintained as a set of Kconfig chunks (inside +`debian./config/`): a global one, plus per-arch / per-flavour +chunks. + +In addition to that, we need to maintain also a file called +'annotations'; the purpose of this file is to make sure that some +critical config options are not silently removed or changed when the +real .config is re-generated (for example after a rebase or after +applying a new set of patches). + +The main problem with this approach is that, often, we have duplicate +information that is stored both in the Kconfig chunks *and* in the +annotations files and, at the same time, the whole .config's information +is distributed between Kconfig chunks and annotations, making it hard to +maintain, review and manage in general. + +Proposed solution +================= + +The proposed solution is to store all the config information into the +"annotations" format and get rid of the config chunks (basically the +real .config's can be produced "compiling" annotations). + +Implementation +============== + +To help the management of the annotations an helper script is provided +(`debian/scripts/misc/annotations`): + +``` +usage: annotations [-h] [--version] [--file FILE] [--arch ARCH] [--flavour FLAVOUR] [--config CONFIG] + (--query | --export | --import FILE | --update FILE | --check FILE) + +Manage Ubuntu kernel .config and annotations + +options: + -h, --help show this help message and exit + --version, -v show program's version number and exit + --file FILE, -f FILE Pass annotations or .config file to be parsed + --arch ARCH, -a ARCH Select architecture + --flavour FLAVOUR, -l FLAVOUR + Select flavour (default is "generic") + --config CONFIG, -c CONFIG + Select a specific config option + +Action: + --query, -q Query annotations + --export, -e Convert annotations to .config format + --import FILE, -i FILE + Import a full .config for a specific arch and flavour into annotations + --update FILE, -u FILE + Import a partial .config into annotations (only resync configs specified in FILE) + --check FILE, -k FILE + Validate kernel .config with annotations +``` + +This script allows to query config settings (per arch/flavour/config), +export them into the Kconfig format (generating the real .config files) +and check if the final .config matches the rules defined in the +annotations. + +Examples (annotations is defined as an alias to `debian/scripts/annotations`): + + - Show settings for `CONFIG_DEBUG_INFO_BTF` for master kernel across all the + supported architectures and flavours: + +``` +$ annotations --query --config CONFIG_DEBUG_INFO_BTF +{ + "policy": { + "amd64": "y", + "arm64": "y", + "armhf": "n", + "ppc64el": "y", + "riscv64": "y", + "s390x": "y" + }, + "note": "'Needs newer pahole for armhf'" +} +``` + + - Dump kernel .config for arm64 and flavour generic-64k: + +``` +$ annotations --arch arm64 --flavour generic-64k --export +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_COMPAT=y +... +``` + + - Update annotations file with a new kernel .config for amd64 flavour + generic: + +``` +$ annotations --arch amd64 --flavour generic --import build/.config +``` + +Moreover, an additional kernelconfig commands are provided +(via debian/rules targets): + - `migrateconfigs`: automatically merge all the previous configs into + annotations (local changes still need to be committed) + +Annotations headers +=================== + +The main annotations file should contain a header to define the architectures +and flavours that are supported. + +Here is the format of the header for the generic kernel: +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 armhf ppc64el riscv64 s390x +# FLAVOUR: amd64-generic arm64-generic arm64-generic-64k armhf-generic armhf-generic-lpae ppc64el-generic riscv64-generic s390x-generic + +``` + +Example header of a derivative (linux-aws): +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 +# FLAVOUR: amd64-aws arm64-aws +# FLAVOUR_DEP: {'amd64-aws': 'amd64-generic', 'arm64-aws': 'arm64-generic'} + +include "../../debian.master/config/annotations" + +# Below you can define only the specific linux-aws configs that differ from linux generic + +``` + +Pros and Cons +============= + + Pros: + - avoid duplicate information in .config's and annotations + - allow to easily define groups of config settings (for a specific + environment or feature, such as annotations.clouds, annotations.ubuntu, + annotations.snapd, etc.) + - config options are more accessible, easy to change and review + - we can easily document how config options are managed (and external + contributors won't be discouraged anymore when they need to to change a + config option) + + Cons: + - potential regressions: the new tool/scripts can have potential bugs, + so we could experience regressions due to some missed config changes + - kernel team need to understand the new process (even if everything + is transparent, kernel cranking process is the same, there might be + corner cases that need to be addressed and resolved manually) + +TODO +==== + + - Migrate all flavour and arch definitions into annotations (rather + than having this information defined in multiple places inside + debian/scripts); right now this information is "partially" migrated, + meaning that we need to define arches and flavours in the headers + section of annotations (so that the annotations tool can figure out + the list of supported arches and flavours), but arches and flavours + are still defined elsewhere, ideally we would like to have arches and + flavours defined only in one place: annotations. --- linux-nvidia-7.0.0.orig/debian.master/config/annotations +++ linux-nvidia-7.0.0/debian.master/config/annotations @@ -0,0 +1,16840 @@ +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 armhf ppc64el riscv64 s390x +# FLAVOUR: amd64-generic arm64-generic arm64-generic-64k armhf-generic ppc64el-generic riscv64-generic s390x-generic + +CONFIG_ACCESSIBILITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_ACCESSIBILITY note<'LP: #1967702'> + +CONFIG_AGP policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_AGP note<'not autoloadable'> + +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE note<'LP: #2051835'> + +CONFIG_ARCH_MMAP_RND_BITS policy<{'amd64': '32', 'arm64': '33', 'arm64-generic-64k': '29', 'armhf': '16', 'ppc64el': '29', 'riscv64': '24'}> +CONFIG_ARCH_MMAP_RND_BITS note<'LP: #1983357'> + +CONFIG_ARCH_MMAP_RND_COMPAT_BITS policy<{'amd64': '16', 'arm64': '16', 'arm64-generic-64k': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS note<'LP: #1983357'> + +CONFIG_ARCH_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_ROCKCHIP note<'LP: #1825222'> + +CONFIG_ARM64_ERRATUM_843419 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_843419 note<'LP: #1647793'> + +CONFIG_ARM64_ERRATUM_858921 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_858921 note<'LP: #1675509'> + +CONFIG_ARM64_VA_BITS_48 policy<{'arm64': 'y'}> +CONFIG_ARM64_VA_BITS_48 note<'Cavium ThunderX 2-socket needs a minimum of 41 bits of VA'> + +CONFIG_ARMV8_DEPRECATED policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARMV8_DEPRECATED note<'LP: #1545542'> + +CONFIG_ARM_HIGHBANK_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_HIGHBANK_CPUIDLE note<'broken on ecx-1000'> + +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT note<'LP: #1845820'> + +CONFIG_ASYMMETRIC_KEY_TYPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASYMMETRIC_KEY_TYPE note<'module signing'> + +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE note<'module signing'> + +CONFIG_ATA_PIIX policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATA_PIIX note<'LP: #1627324'> + +CONFIG_BINFMT_SCRIPT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BINFMT_SCRIPT note<'required if init is a shell script such as in initramfs-tools'> + +CONFIG_BLK_DEV_DM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_DM note<'LP: #560717'> + +CONFIG_BLK_DEV_NVME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_NVME note<'LP: #1759893'> + +CONFIG_BLK_DEV_RAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_RAM note<'LP: #1593293'> + +CONFIG_BLK_DEV_RAM_SIZE policy<{'amd64': '65536', 'arm64': '65536', 'armhf': '65536', 'ppc64el': '65536', 'riscv64': '65536', 's390x': '65536'}> +CONFIG_BLK_DEV_RAM_SIZE note<'Ramdisk size should be a minimum of 64M'> + +CONFIG_BLK_DEV_SD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_SD note<'LP: #1627330'> + +CONFIG_BLK_DEV_SR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_SR note<'LP: #1627330'> + +CONFIG_BLK_DEV_THROTTLING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_THROTTLING note<'CGROUP disk consumption control'> + +CONFIG_BPF_UNPRIV_DEFAULT_OFF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_UNPRIV_DEFAULT_OFF note<'security reason'> + +CONFIG_CHR_DEV_SG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CHR_DEV_SG note<'not autoloadable'> + +CONFIG_CMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CMA note<'LP: #1803206'> + +CONFIG_CMA_SIZE_MBYTES policy<{'amd64': '0', 'arm64': '32', 'armhf': '32', 'riscv64': '32'}> +CONFIG_CMA_SIZE_MBYTES note<'LP: #1823753'> + +CONFIG_COMPAT_BRK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_COMPAT_BRK note<'disables brk ASLR'> + +CONFIG_CONSOLE_LOGLEVEL_QUIET policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3', 's390x': '3'}> +CONFIG_CONSOLE_LOGLEVEL_QUIET note<'LP: #2049390'> + +CONFIG_CP15_BARRIER_EMULATION policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_CP15_BARRIER_EMULATION note<'LP: #1545542'> + +CONFIG_CPUFREQ_DT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPUFREQ_DT note<'not autoloadable'> + +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE note<'for bootspeed'> + +CONFIG_CPU_FREQ_GOV_CONSERVATIVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_ONDEMAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_ONDEMAND note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_PERFORMANCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_PERFORMANCE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_POWERSAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_POWERSAVE note<'not autoloadable'> + +CONFIG_CPU_FREQ_GOV_USERSPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_USERSPACE note<'not autoloadable'> + +CONFIG_CPU_FREQ_STAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_STAT note<'dependancy of boot essential'> + +CONFIG_CRASH_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRASH_DUMP note<'LP: #1363180'> + +CONFIG_CRYPTO_HMAC_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_HMAC_S390 note<'LP: #2096812'> + +CONFIG_CRYPTO_LIB_SHA512_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA512_ARCH note<'LP: #2034061'> + +CONFIG_CRYPTO_SHA512 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SHA512 note<'module signing'> + +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE note<'Obsolete w/ no known userspace dependencies'> + +CONFIG_DEBUG_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_FS note<'required debug option'> + +CONFIG_DEBUG_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO note<'required for debug packages'> + +CONFIG_DEBUG_INFO_BTF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_BTF note<'Needs newer pahole for armhf'> + +CONFIG_DEBUG_INFO_SPLIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_SPLIT note<'LP: #1413664'> + +CONFIG_DEBUG_KERNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_KERNEL note<'required debug option'> + +CONFIG_DEFAULT_MMAP_MIN_ADDR policy<{'amd64': '65536', 'arm64': '32768', 'armhf': '32768', 'ppc64el': '65536', 'riscv64': '65536', 's390x': '65536'}> +CONFIG_DEFAULT_MMAP_MIN_ADDR note<'LP: #1531327'> + +CONFIG_DEVTMPFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVTMPFS note<'upstart requirement'> + +CONFIG_DEVTMPFS_MOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVTMPFS_MOUNT note<'upstart requirement'> + +CONFIG_DMA_CMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DMA_CMA note<'LP: #1803206'> + +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING note<'LP: #2019040'> + +CONFIG_DRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM note<'LP: #1965303'> + +CONFIG_DRM_AMDGPU_CIK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMDGPU_CIK note<'for zesty'> + +CONFIG_DRM_I915_REPLAY_GPU_HANGS_API policy<{'amd64': 'n'}> +CONFIG_DRM_I915_REPLAY_GPU_HANGS_API note<'Only useful for upstream developers'> + +CONFIG_DRM_MGAG200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_MGAG200 note<'LP: #1693337'> + +CONFIG_DRM_SIMPLEDRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DRM_SIMPLEDRM note<'LP: #1965303'> + +CONFIG_DRM_VBOXVIDEO policy<{'amd64': 'm'}> +CONFIG_DRM_VBOXVIDEO note<'LP: #1718679'> + +CONFIG_DVB_DUMMY_FE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DUMMY_FE note<'expert use only'> + +CONFIG_ECRYPT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ECRYPT_FS note<'not autoloadable'> + +CONFIG_EFIVAR_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFIVAR_FS note<'needed for variable EFI update'> + +CONFIG_EFI_HANDOVER_PROTOCOL policy<{'amd64': 'y'}> +CONFIG_EFI_HANDOVER_PROTOCOL note<'{GRUB may include some downstream patches that may rely on the handover protocol, so make sure this is enabled}'> + +CONFIG_EFI_ZBOOT policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_ZBOOT note<'LP: #2002226'> + +CONFIG_EVM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM note<'LP: #1643652'> + +CONFIG_EVM_ATTR_FSUUID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM_ATTR_FSUUID note<'LP: #1643652'> + +CONFIG_EVM_LOAD_X509 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EVM_LOAD_X509 note<'LP: #1643652'> + +CONFIG_EVM_X509_PATH policy<{'ppc64el': '"/etc/keys/x509_evm.der"'}> +CONFIG_EVM_X509_PATH note<'LP: #1643652'> + +CONFIG_EXT2_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EXT2_FS note<'ext4 handling via EXT4_USE_FOR_EXT23'> + +CONFIG_FA_DUMP policy<{'ppc64el': 'y'}> +CONFIG_FA_DUMP note<'LP: #1415562'> + +CONFIG_FB_EFI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_FB_EFI note<'LP: #1965303'> + +CONFIG_FB_VESA policy<{'amd64': 'n'}> +CONFIG_FB_VESA note<'LP: #1965303'> + +CONFIG_FHANDLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FHANDLE note<'LP: #1412543'> + +CONFIG_FUSE_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSE_FS note<'not autoloadable'> + +CONFIG_FW_LOADER_USER_HELPER_FALLBACK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FW_LOADER_USER_HELPER_FALLBACK note<'LP: #1398458'> + +CONFIG_GPIO_CDEV_V1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_CDEV_V1 note<'LP: #1953613'> + +CONFIG_GPIO_EM policy<{'armhf': 'n'}> +CONFIG_GPIO_EM note<'h/w not encounted'> + +CONFIG_GPIO_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_TWL4030 note<'LP: #921934'> + +CONFIG_HIBERNATION policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_HIBERNATION note<'LP: #1867753'> + +CONFIG_HIPERDISPATCH_ON policy<{'s390x': 'y'}> +CONFIG_HIPERDISPATCH_ON note<'LP: #2072760'> + +CONFIG_HOTPLUG_PCI_PCIE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PCI_PCIE note<'LP: #1374440'> + +CONFIG_HOTPLUG_PCI_SHPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HOTPLUG_PCI_SHPC note<'LP: #1374440'> + +CONFIG_HSA_AMD_P2P policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSA_AMD_P2P note<'LP: #1987394'> + +CONFIG_HSU_DMA policy<{'amd64': 'y'}> +CONFIG_HSU_DMA note<'required by CONFIG_SERIAL_8250_MID (LP: #2009283)'> + +CONFIG_HVC_UDBG policy<{'ppc64el': 'n'}> +CONFIG_HVC_UDBG note<'LP: #1680888'> + +CONFIG_HZ_100 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_HZ_100 note<'LP: #2051342'> + +CONFIG_HZ_1000 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HZ_1000 note<'LP: #2051342'> + +CONFIG_HZ_250 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HZ_250 note<'LP: #2051342'> + +CONFIG_I2C_CHARDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_I2C_CHARDEV note<'LP: #1417032'> + +CONFIG_IBMVNIC policy<{'ppc64el': 'm'}> +CONFIG_IBMVNIC note<'LP: #1628187'> + +CONFIG_IDLE_PAGE_TRACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IDLE_PAGE_TRACKING note<'is there a cost associated with this?'> + +CONFIG_IGH_ECAT policy<{'amd64': 'm', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IGH_ECAT note<'{LP: #2138621}'> + +CONFIG_IIO_SIMPLE_DUMMY_BUFFER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IIO_SIMPLE_DUMMY_BUFFER note<'dummy driver'> + +CONFIG_IIO_SIMPLE_DUMMY_EVENTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IIO_SIMPLE_DUMMY_EVENTS note<'dummy driver'> + +CONFIG_IMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA note<'LP: #1643652'> + +CONFIG_IMA_APPRAISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_APPRAISE note<'LP: #1643652'> + +CONFIG_IMA_ARCH_POLICY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_ARCH_POLICY note<'LP: #1866909'> + +CONFIG_IMA_DEFAULT_HASH_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_DEFAULT_HASH_SHA256 note<'LP: #2041735'> + +CONFIG_IMA_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IMA_KEXEC note<'LP: #1643652'> + +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY note<'LP: #1667490'> + +CONFIG_IMA_READ_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_READ_POLICY note<'LP: #1866909'> + +CONFIG_IMA_SIG_TEMPLATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_SIG_TEMPLATE note<'LP: #1643652'> + +CONFIG_IMA_WRITE_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_WRITE_POLICY note<'LP: #1667490'> + +CONFIG_INPUT_UINPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INPUT_UINPUT note<'LP: #584812'> + +CONFIG_INTEGRITY_PLATFORM_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_PLATFORM_KEYRING note<'Required for lockdown'> + +CONFIG_INTEL_ATOMISP policy<{'amd64': 'n'}> +CONFIG_INTEL_ATOMISP note<'LP: #2017444'> + +CONFIG_INTEL_ATOMISP2_PM policy<{'amd64': 'm'}> +CONFIG_INTEL_ATOMISP2_PM note<'LP: #2017444'> + +CONFIG_INTEL_IOMMU_DEFAULT_ON policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_DEFAULT_ON note<'LP: #1951440'> + +CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON note<'LP: #1951440'> + +CONFIG_IOMMU_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IOMMU_DEBUGFS note<'LP: #1861057'> + +CONFIG_IOMMU_DEFAULT_DMA_LAZY policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_IOMMU_DEFAULT_DMA_LAZY note<'LP: #2071471'> + +CONFIG_IOMMU_DEFAULT_DMA_STRICT policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_IOMMU_DEFAULT_DMA_STRICT note<'LP: #2071471'> + +CONFIG_IPMMU_VMSA policy<{'arm64': 'n', 'armhf': 'n', 'riscv64': '-'}> +CONFIG_IPMMU_VMSA note<'LP: #1718734'> + +CONFIG_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6 note<'if this is a module we get a module load for every ipv6 packet'> + +CONFIG_IP_PNP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IP_PNP note<'LP: #1259861'> + +CONFIG_KERNEL_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KERNEL_ZSTD note<'LP: #193172'> + +CONFIG_KEXEC_BZIMAGE_VERIFY_SIG policy<{'amd64': 'y'}> +CONFIG_KEXEC_BZIMAGE_VERIFY_SIG note<'Q: check this is in sync with the kexec/kdump userspace'> + +CONFIG_KFENCE_STATIC_KEYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KFENCE_STATIC_KEYS note<'LP: #1948038'> + +CONFIG_KGDB_SERIAL_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_SERIAL_CONSOLE note<'early debugging support'> + +CONFIG_KVM policy<{'amd64': 'm', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'y'}> +CONFIG_KVM note<'LP: #1532886'> + +CONFIG_LATENCYTOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LATENCYTOP note<'LP: #2051342'> + +CONFIG_LEGACY_TIOCSTI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LEGACY_TIOCSTI note<'LP:#2046192'> + +CONFIG_LOAD_PPC_KEYS policy<{'ppc64el': 'y'}> +CONFIG_LOAD_PPC_KEYS note<'LP: #1866909'> + +CONFIG_LOCALVERSION_AUTO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCALVERSION_AUTO note<'triggers packaging failures'> + +CONFIG_LRU_GEN policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LRU_GEN note<'{Enable multi-gen LRU by default - LP: #2023629}'> + +CONFIG_LRU_GEN_ENABLED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LRU_GEN_ENABLED note<'{Enable multi-gen LRU by default - LP: #2023629}'> + +CONFIG_MFD_SM501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SM501 note<'boot essential on OMAP4'> + +CONFIG_MFD_TPS65217 policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_MFD_TPS65217 note<'boot essential on AM335x'> + +CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE note<'LP: #1848492'> + +CONFIG_MHP_MEMMAP_ON_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MHP_MEMMAP_ON_MEMORY note<'LP: #2051835'> + +CONFIG_MMC_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_BLOCK note<'boot essential on armhf/arm64'> + +CONFIG_MMC_OMAP_HS policy<{'armhf': 'y'}> +CONFIG_MMC_OMAP_HS note<'boot essential on arm'> + +CONFIG_MMC_SDHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_SDHCI note<'installation essential on omap/highbank'> + +CONFIG_MMC_SDHCI_PLTFM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_PLTFM note<'boot essential on highbank'> + +CONFIG_MODIFY_LDT_SYSCALL policy<{'amd64': 'y'}> +CONFIG_MODIFY_LDT_SYSCALL note<'Q: check this with security'> + +CONFIG_MODULE_COMPRESS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_COMPRESS_ZSTD note<'LP: #2028568'> + +CONFIG_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODVERSIONS note<'required as we have a livepatch/drivers modules signing key'> + +CONFIG_MTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MTD note<'boot essential on arm'> + +CONFIG_MTD_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MTD_BLOCK note<'boot essential on arm'> + +CONFIG_MTD_DOCG3 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_DOCG3 note<'LP: #1792205'> + +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE note<'can be enabled at runtime'> + +CONFIG_MTD_OF_PARTS policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_OF_PARTS note<'boot essential on arm'> + +CONFIG_MTD_ONENAND_VERIFY_WRITE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_ONENAND_VERIFY_WRITE note<'writes here are not checked in full without'> + +CONFIG_MTD_RAW_NAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MTD_RAW_NAND note<'boot essential on arm'> + +CONFIG_NETWORK_PHY_TIMESTAMPING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETWORK_PHY_TIMESTAMPING note<'LP: #1785816'> + +CONFIG_NET_9P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P note<'LP: #1557994'> + +CONFIG_NET_DROP_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DROP_MONITOR note<'LP: #1660634'> + +CONFIG_NET_SWITCHDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SWITCHDEV note<'updated to y for s390x starting with focal'> + +CONFIG_NET_VENDOR_EMULEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_EMULEX note<'LP: #1543165'> + +CONFIG_NLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NLS note<'dependancy of boot essential'> + +CONFIG_NOP_USB_XCEIV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NOP_USB_XCEIV note<'boot essential on omap/highbank'> + +CONFIG_NO_HZ_FULL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_NO_HZ_FULL note<'LP: #2051342'> + +CONFIG_NO_HZ_IDLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NO_HZ_IDLE note<'LP: #2051342'> + +CONFIG_NR_CPUS policy<{'amd64': '8192', 'arm64': '512', 'armhf': '4', 'ppc64el': '2048', 'riscv64': '512', 's390x': '512'}> +CONFIG_NR_CPUS note<'LP: #2042897 (arm64), LP: #1864198 (s390x)'> + +CONFIG_NUMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NUMA note<'LP: #1557690'> + +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED note<'LP: #1557690'> + +CONFIG_NUMA_EMU policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_NUMA_EMU note<'LP: #1864198'> + +CONFIG_NVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NVMEM note<'LP: #1543165'> + +CONFIG_NVRAM policy<{'amd64': 'm', 'ppc64el': 'y'}> +CONFIG_NVRAM note<'LP: #1837726'> + +CONFIG_N_GSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_N_GSM note<'LP: #1404670'> + +CONFIG_OSNOISE_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OSNOISE_TRACER note<'This enables the osnoise tracer for the kernel. LP: #2018591'> + +CONFIG_PAGE_POISONING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_POISONING note<'LP: #1783651'> + +CONFIG_PANIC_ON_OOPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PANIC_ON_OOPS note<'keep working if at all possible'> + +CONFIG_PATA_HPT3X3_DMA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PATA_HPT3X3_DMA note<'DMA mode is documented problematic'> + +CONFIG_PCIEASPM_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEASPM_DEFAULT note<'LP: #1398544'> + +CONFIG_PCIEPORTBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEPORTBUS note<'LP: #1665404'> + +CONFIG_PCI_DYNAMIC_OF_NODES policy<{'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PCI_DYNAMIC_OF_NODES note<'LP: #2074376, ok for arm64 as MISC_RP1 needs it'> + +CONFIG_PCI_MESON policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_MESON note<'LP: #2007745'> + +CONFIG_PCI_NR_FUNCTIONS policy<{'s390x': '512'}> +CONFIG_PCI_NR_FUNCTIONS note<'LP: #1866056'> + +CONFIG_PINCTRL_CHERRYVIEW policy<{'amd64': 'y'}> +CONFIG_PINCTRL_CHERRYVIEW note<'LP: #1630238'> + +CONFIG_PM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM note<'LP: #1867753'> + +CONFIG_PPC_MEM_KEYS policy<{'ppc64el': 'n'}> +CONFIG_PPC_MEM_KEYS note<'LP: #1776967'> + +CONFIG_PPC_SECURE_BOOT policy<{'ppc64el': 'y'}> +CONFIG_PPC_SECURE_BOOT note<'LP: #1855668'> + +CONFIG_PPC_SECVAR_SYSFS policy<{'ppc64el': 'y'}> +CONFIG_PPC_SECVAR_SYSFS note<'LP: #1866909'> + +CONFIG_PREEMPT_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PREEMPT_DYNAMIC note<'LP: #2051342'> + +CONFIG_PSI_DEFAULT_DISABLED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_PSI_DEFAULT_DISABLED note<'LP: #1876044'> + +CONFIG_QCOM_QDF2400_ERRATUM_0065 policy<{'arm64': 'y'}> +CONFIG_QCOM_QDF2400_ERRATUM_0065 note<'LP: #1672486'> + +CONFIG_QETH_OSX policy<{'s390x': 'n'}> +CONFIG_QETH_OSX note<'LP: #1959890'> + +CONFIG_RCU_LAZY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_LAZY note<'LP: #2051342'> + +CONFIG_RCU_LAZY_DEFAULT_OFF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_LAZY_DEFAULT_OFF note<'LP: #2051342'> + +CONFIG_RCU_NOCB_CPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_NOCB_CPU note<'LP: #2051342'> + +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RCU_NOCB_CPU_DEFAULT_ALL note<'LP: #2051342'> + +CONFIG_REGULATOR_TPS65217 policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65217 note<'boot essential on AM335x'> + +CONFIG_REGULATOR_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TWL4030 note<'boot requisite for omap4'> + +CONFIG_RTC_DRV_CMOS policy<{'amd64': 'y', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_RTC_DRV_CMOS note<'boot essential on i386/amd64'> + +CONFIG_RTC_DRV_EFI policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'm'}> +CONFIG_RTC_DRV_EFI note<'LP: #1583738'> + +CONFIG_RTC_DRV_TWL4030 policy<{'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_TWL4030 note<'boot essential on OMAP3/OMAP4'> + +CONFIG_RT_GROUP_SCHED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RT_GROUP_SCHED note<'LP: #1875665'> + +CONFIG_RUST policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_RUST note<'Make sure this remains enabled'> + +CONFIG_S390_UV_UAPI policy<{'s390x': 'y'}> +CONFIG_S390_UV_UAPI note<'LP: #2048919'> + +CONFIG_SAMPLE_TRACE_PRINTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SAMPLE_TRACE_PRINTK note<'Required for ftrace selftests'> + +CONFIG_SATA_AHCI_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_AHCI_PLATFORM note<'boot essential on highbank'> + +CONFIG_SATA_HIGHBANK policy<{'armhf': 'y'}> +CONFIG_SATA_HIGHBANK note<'LP: #1703430'> + +CONFIG_SCHED_TOPOLOGY_VERTICAL policy<{'s390x': 'y'}> +CONFIG_SCHED_TOPOLOGY_VERTICAL note<'LP: #2072760'> + +CONFIG_SCLP_OFB policy<{'s390x': 'y'}> +CONFIG_SCLP_OFB note<'LP: #1787898'> + +CONFIG_SCSI_IPR_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_IPR_DUMP note<'LP: #1343109'> + +CONFIG_SCSI_IPR_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_IPR_TRACE note<'LP: #1343109'> + +CONFIG_SCSI_SYM53C8XX_2 policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SYM53C8XX_2 note<'{LP: #2118499}'> + +CONFIG_SCSI_VIRTIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_VIRTIO note<'enable initrdless boot in VMs for ease of use, cloud-kernel parity and disaster recovery, LP: #1685291'> + +CONFIG_SECURITY_SAFESETID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SAFESETID note<'LP: #1845391'> + +CONFIG_SERIAL_8250_DW policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_DW note<'several RISC-V boards needs this for console output'> + +CONFIG_SERIAL_8250_MID policy<{'amd64': 'y'}> +CONFIG_SERIAL_8250_MID note<'required to provide console on some Intel SoC platforms (LP: #2009283)'> + +CONFIG_SERIAL_DEV_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SERIAL_DEV_BUS note<'LP: #1739939'> + +CONFIG_SERIAL_DEV_CTRL_TTYPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SERIAL_DEV_CTRL_TTYPORT note<'LP: #1739939'> + +CONFIG_SERIAL_SH_SCI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI note<'LP: #2022361'> + +CONFIG_SERIAL_SH_SCI_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI_CONSOLE note<'LP: #2022361'> + +CONFIG_SERIAL_SH_SCI_EARLYCON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI_EARLYCON note<'LP: #2022361'> + +CONFIG_SETEND_EMULATION policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_SETEND_EMULATION note<'LP: #1545542'> + +CONFIG_SMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMC note<'LP: #1789934'> + +CONFIG_SMC_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMC_DIAG note<'LP: #1789934'> + +CONFIG_SND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND note<'not autoloadable on omap'> + +CONFIG_SND_HDA_POWER_SAVE_DEFAULT policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SND_HDA_POWER_SAVE_DEFAULT note<'LP: #1804265'> + +CONFIG_SND_HDA_RECONFIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_RECONFIG note<'allows fixes to be tested live'> + +CONFIG_SND_PCM_OSS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_PCM_OSS note<'deprecated in favour of pulseaudio emulation'> + +CONFIG_SND_SOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC note<'not autoloadable on omap'> + +CONFIG_SND_SOC_AMD_RENOIR policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_RENOIR note<'LP: #1881046'> + +CONFIG_SND_SOC_AMD_RENOIR_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_RENOIR_MACH note<'LP: #1881046'> + +CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH note<'LP: #1921632'> + +CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES policy<{'amd64': 'y'}> +CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES note<'LP: #1921632'> + +CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC note<'LP: #1848490'> + +CONFIG_SND_SOC_SOF_HDA_LINK policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_HDA_LINK note<'LP: #1848490'> + +CONFIG_SOUND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SOUND note<'not autoloadable on omap'> + +CONFIG_SOUNDWIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE note<'LP: #1855685'> + +CONFIG_SOUND_OSS_CORE_PRECLAIM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SOUND_OSS_CORE_PRECLAIM note<'LP: #1385510'> + +CONFIG_SQUASHFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS note<'LP: #1593134'> + +CONFIG_SQUASHFS_4K_DEVBLK_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_4K_DEVBLK_SIZE note<'non-default block size'> + +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU note<'LP: #1980861'> + +CONFIG_STACK_VALIDATION policy<{'amd64': 'y'}> +CONFIG_STACK_VALIDATION note<'needed for livepatch'> + +CONFIG_SWP_EMULATION policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_SWP_EMULATION note<'LP: #1545542'> + +CONFIG_SYSFB_SIMPLEFB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SYSFB_SIMPLEFB note<'LP: #1965303'> + +CONFIG_TCG_TIS_I2C_ATMEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_ATMEL note<'LP: #1643652'> + +CONFIG_TCG_TIS_I2C_INFINEON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_INFINEON note<'LP: #1643652'> + +CONFIG_TCG_TIS_I2C_NUVOTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_NUVOTON note<'LP: #1643652'> + +CONFIG_TCG_TPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCG_TPM note<'needed for early validation'> + +CONFIG_TIMERLAT_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIMERLAT_TRACER note<'This enables the osnoise tracer for the kernel. LP: #2018591'> + +CONFIG_TMPFS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_POSIX_ACL note<'some /dev nodes require POSIX ACLs, like /dev/dsp'> + +CONFIG_TOUCHSCREEN_APPLE_Z2 policy<{'arm64': 'm'}> +CONFIG_TOUCHSCREEN_APPLE_Z2 note<'LP: #2115758'> + +CONFIG_TOUCHSCREEN_ELAN policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ELAN note<'LP: #1630238'> + +CONFIG_TUNE_Z16 policy<{'s390x': 'y'}> +CONFIG_TUNE_Z16 note<'LP: #1982833 in general, always pick the newest tune available'> + +CONFIG_UBSAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_UBSAN note<'LP: #1942215'> + +CONFIG_UNWINDER_FRAME_POINTER policy<{'amd64': 'y', 'armhf': 'y'}> +CONFIG_UNWINDER_FRAME_POINTER note<'needed for livepatch'> + +CONFIG_USB_EHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_USB_EHCI_HCD_PLATFORM policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EHCI_HCD_PLATFORM note<'Dont use the generic ehci/ohci code on omap, it doesnt work'> + +CONFIG_USB_HCD_BCMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HCD_BCMA note<'USB_{O,E}HCI_HCD_PLATFORM must be off on omap'> + +CONFIG_USB_HCD_SSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HCD_SSB note<'USB_{O,E}HCI_HCD_PLATFORM must be off on omap'> + +CONFIG_USB_M66592 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_M66592 note<'gadget device'> + +CONFIG_USB_MUSB_HDRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MUSB_HDRC note<'not autoloadable on omap'> + +CONFIG_USB_OTG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_USB_OTG note<'LP: #1411295'> + +CONFIG_USB_SERIAL_DEBUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_DEBUG note<'not actually debug'> + +CONFIG_USB_UHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_UHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_USB_XHCI_DBGCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_DBGCAP note<'LP: #1730832'> + +CONFIG_USB_XHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_HCD note<'ensures USB 2.0/1.1 probe ordering'> + +CONFIG_VFAT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFAT_FS note<'needed on arm to ensure we can write the kernel when replacing'> + +CONFIG_VFIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VFIO note<'LP: #1636733'> + +CONFIG_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VFIO_PCI note<'LP: #1636733'> + +CONFIG_VFIO_PCI_ZDEV_KVM policy<{'s390x': 'y'}> +CONFIG_VFIO_PCI_ZDEV_KVM note<'LP: #2042853'> + +CONFIG_VIDEO_VIMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIMC note<'LP: #1831482'> + +CONFIG_VIRTIO_BLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_BLK note<'LP: #2030745'> + +CONFIG_VIRTIO_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_VIRTIO_MMIO note<'LP: #1557689'> + +CONFIG_VIRTIO_NET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_NET note<'KVM paravirt support -- cloud-init currently racy with this as a module (LP: #2036968)'> + +CONFIG_WWAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_WWAN note<'LP: #2033406'> + +CONFIG_X509_CERTIFICATE_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_X509_CERTIFICATE_PARSER note<'module signing'> + +CONFIG_X86_ACPI_CPUFREQ policy<{'amd64': 'y'}> +CONFIG_X86_ACPI_CPUFREQ note<'not autoloadable'> + +CONFIG_X86_KERNEL_IBT policy<{'amd64': 'n'}> +CONFIG_X86_KERNEL_IBT note<'LP: #1980484'> + +CONFIG_X86_PCC_CPUFREQ policy<{'amd64': 'y'}> +CONFIG_X86_PCC_CPUFREQ note<'not autoloadable'> + +CONFIG_X86_POWERNOW_K8 policy<{'amd64': 'y'}> +CONFIG_X86_POWERNOW_K8 note<'not autoloadable'> + +CONFIG_X86_SPEEDSTEP_CENTRINO policy<{'amd64': 'y'}> +CONFIG_X86_SPEEDSTEP_CENTRINO note<'not autoloadable'> + +CONFIG_X86_UV policy<{'amd64': 'y'}> +CONFIG_X86_UV note<'LP: #1863810'> + +CONFIG_X86_X32_ABI policy<{'amd64': 'n'}> +CONFIG_X86_X32_ABI note<'LP: #1994516'> + +CONFIG_XEN_512GB policy<{'amd64': 'y'}> +CONFIG_XEN_512GB note<'Q: is this related to the utlemming questions on memory size?'> + +CONFIG_XEN_ACPI_PROCESSOR policy<{'amd64': 'y'}> +CONFIG_XEN_ACPI_PROCESSOR note<'boot essential on XEN host'> + +CONFIG_XEN_BLKDEV_FRONTEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_BLKDEV_FRONTEND note<'not autoloadable -- XEN paravirt support'> + +CONFIG_XEN_NETDEV_FRONTEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_NETDEV_FRONTEND note<'not autoloadable -- XEN paravirt support'> + +CONFIG_XZ_DEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC note<'boot essential -- initramfs decompressor'> + +CONFIG_ZLIB_DFLTCC policy<{'s390x': 'y'}> +CONFIG_ZLIB_DFLTCC note<'LP: #1830208'> + +CONFIG_ZONE_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_ZONE_DMA note<'LP: #1628523'> + + +# ---- Annotations without notes ---- + +CONFIG_104_QUAD_8 policy<{'amd64': 'm'}> +CONFIG_60XX_WDT policy<{'amd64': 'm'}> +CONFIG_64BIT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_6LOWPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_6LOWPAN_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_ICMPV6 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_GHC_UDP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_6LOWPAN_NHC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_DEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_FRAGMENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_HOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_MOBILITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_ROUTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6LOWPAN_NHC_UDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_6PACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_8139CP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_8139TOO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_8139TOO_8129 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_8139TOO_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_8139TOO_TUNE_TWISTER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_8139_OLD_RX_RESET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_842_COMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_842_DECOMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_88PM886_GPADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_9P_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_9P_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_9P_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_9P_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_A11Y_BRAILLE_CONSOLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_A64FX_DIAG policy<{'arm64': 'y'}> +CONFIG_ABP060MG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ABP2030PA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ABP2030PA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ABP2030PA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AC97_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ACENIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ACENIC_OMIT_TIGON_I policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ACERHDF policy<{'amd64': 'm'}> +CONFIG_ACER_WIRELESS policy<{'amd64': 'm'}> +CONFIG_ACER_WMI policy<{'amd64': 'm'}> +CONFIG_ACLINT_SSWI policy<{'riscv64': 'n'}> +CONFIG_ACORN_PARTITION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_AC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_ADXL policy<{'amd64': 'y'}> +CONFIG_ACPI_AGDI policy<{'arm64': 'y'}> +CONFIG_ACPI_ALS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_APEI policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_EINJ policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_ACPI_APEI_EINJ_CXL policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_ERST_DEBUG policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_ACPI_APEI_GHES policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_MEMORY_FAILURE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_PCIEAER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_APEI_SEA policy<{'arm64': 'y'}> +CONFIG_ACPI_APMT policy<{'arm64': 'y'}> +CONFIG_ACPI_BATTERY policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_BGRT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_BUTTON policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CCA_REQUIRED policy<{'arm64': 'y'}> +CONFIG_ACPI_CMPC policy<{'amd64': 'm'}> +CONFIG_ACPI_CONFIGFS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_CONTAINER policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CPPC_CPUFREQ policy<{'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_CPPC_CPUFREQ_FIE policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CPPC_LIB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_CPU_FREQ_PSS policy<{'amd64': 'y'}> +CONFIG_ACPI_CUSTOM_DSDT_FILE policy<{'amd64': '""'}> +CONFIG_ACPI_DEBUG policy<{'amd64': 'y', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_ACPI_DEBUGGER policy<{'amd64': 'y', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_ACPI_DEBUGGER_USER policy<{'amd64': 'y'}> +CONFIG_ACPI_DOCK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_DPTF policy<{'amd64': 'y'}> +CONFIG_ACPI_EC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_EC_DEBUGFS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_EXTLOG policy<{'amd64': 'm'}> +CONFIG_ACPI_FAN policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_FFH policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_FPDT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_GENERIC_GSI policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_GTDT policy<{'arm64': 'y'}> +CONFIG_ACPI_HED policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_HMAT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_HOTPLUG_CPU policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_HOTPLUG_IOAPIC policy<{'amd64': 'y'}> +CONFIG_ACPI_HOTPLUG_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_I2C_OPREGION policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_IORT policy<{'arm64': 'y'}> +CONFIG_ACPI_IPMI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_LEGACY_TABLES_LOOKUP policy<{'amd64': 'y'}> +CONFIG_ACPI_LPIT policy<{'amd64': 'y'}> +CONFIG_ACPI_MADT_WAKEUP policy<{'amd64': 'y'}> +CONFIG_ACPI_MCFG policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_MDIO policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_MPAM policy<{'arm64': 'y'}> +CONFIG_ACPI_MRRM policy<{'amd64': 'y'}> +CONFIG_ACPI_NFIT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_NHLT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_NUMA policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PCC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PCI_SLOT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PFRUT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_PLATFORM_PROFILE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': '-'}> +CONFIG_ACPI_PPTT policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PRMT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_PROCESSOR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_PROCESSOR_AGGREGATOR policy<{'amd64': 'm'}> +CONFIG_ACPI_PROCESSOR_CSTATE policy<{'amd64': 'y'}> +CONFIG_ACPI_PROCESSOR_IDLE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_QUICKSTART policy<{'amd64': 'm'}> +CONFIG_ACPI_REDUCED_HARDWARE_ONLY policy<{'amd64': 'n', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE policy<{'amd64': 'y'}> +CONFIG_ACPI_RIMT policy<{'riscv64': 'y'}> +CONFIG_ACPI_SBS policy<{'amd64': 'm'}> +CONFIG_ACPI_SLEEP policy<{'amd64': 'y'}> +CONFIG_ACPI_SPCR_TABLE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT policy<{'amd64': 'y'}> +CONFIG_ACPI_TABLE_LIB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_TABLE_UPGRADE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_TAD policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_THERMAL_LIB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_THERMAL_REL policy<{'amd64': 'm'}> +CONFIG_ACPI_TOSHIBA policy<{'amd64': 'm'}> +CONFIG_ACPI_VIDEO policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ACPI_VIOT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ACPI_WATCHDOG policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ACPI_WMI policy<{'amd64': 'm'}> +CONFIG_ACPI_WMI_LEGACY_DEVICE_NAMES policy<{'amd64': 'y'}> +CONFIG_ACQUIRE_WDT policy<{'amd64': 'm'}> +CONFIG_ACRN_GUEST policy<{'amd64': 'y'}> +CONFIG_ACRN_HSM policy<{'amd64': 'm'}> +CONFIG_AD2S1200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD2S1210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD2S90 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3530R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3552R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3552R_HS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD3552R_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4170_4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4695 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD4851 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD525X_DPOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AD525X_DPOT_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD525X_DPOT_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5272 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5380 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5421 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5446 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5446_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5446_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5449 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5504 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5592R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5592R_BASE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5593R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5624R_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5686 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5686_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5696_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5755 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5758 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5764 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5766 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5770R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5791 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD5933 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7091R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7091R5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7091R8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7124 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7173 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7191 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7192 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7266 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7291 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7292 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7293 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7298 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7380 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7405 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD74115 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD74413R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7476 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7606 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7606_IFACE_PARALLEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7606_IFACE_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7625 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7746 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7766 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7768_1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7779 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7791 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7793 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7816 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7887 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7923 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7944 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD7949 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD799X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD8366 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD8460 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD8801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9467 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9739A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD9834 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADA4250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADAPTEC_STARFIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ADC_BATTERY_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADE9000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADF4350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADF4371 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADF4377 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ADFS_FS_RW policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ADIN1100_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ADIN1110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIN_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ADIS16080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16136 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16203 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16209 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16460 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16475 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16480 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADIS16550 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADI_AXI_ADC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ADI_AXI_DAC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ADI_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADJD_S311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADL8113 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADM8211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMFM2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV1013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV1014 policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV4420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADMV8818 policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADP810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADRF6780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADT7316 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADT7316_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADT7316_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADUX1020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADVANTECH_EC_WDT policy<{'amd64': 'm'}> +CONFIG_ADVANTECH_WDT policy<{'amd64': 'm'}> +CONFIG_ADVISE_SYSCALLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ADV_SWBUTTON policy<{'amd64': 'm'}> +CONFIG_ADXL313 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL313_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL313_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL345 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL345_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL345_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL355 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL355_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL355_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL367 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL367_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL367_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL372 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL372_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL372_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL380 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL380_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXL380_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXRS290 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ADXRS450 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AD_SIGMA_DELTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AEABI policy<{'armhf': 'y'}> +CONFIG_AF8133J policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AFE4403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AFE4404 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AFFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AFIUCV policy<{'s390x': 'm'}> +CONFIG_AFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AFS_DEBUG_CURSOR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AFS_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AF_KCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AF_RXRPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AF_RXRPC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AF_RXRPC_INJECT_LOSS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AF_RXRPC_INJECT_RX_DELAY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AF_RXRPC_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AF_UNIX_OOB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AGP_AMD64 policy<{'amd64': 'y'}> +CONFIG_AGP_INTEL policy<{'amd64': 'y'}> +CONFIG_AGP_SIS policy<{'amd64': 'm'}> +CONFIG_AGP_VIA policy<{'amd64': 'y'}> +CONFIG_AHCI_CEVA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AHCI_DM816 policy<{'armhf': 'm'}> +CONFIG_AHCI_DWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AHCI_IMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_AHCI_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AHCI_MVEBU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AHCI_QORIQ policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_AHCI_SUNXI policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_AHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AHCI_XGENE policy<{'arm64': 'm'}> +CONFIG_AIC79XX_CMDS_PER_DEVICE policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_AIC79XX_DEBUG_ENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_AIC79XX_DEBUG_MASK policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_AIC79XX_REG_PRETTY_PRINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AIC79XX_RESET_DELAY_MS policy<{'amd64': '5000', 'arm64': '5000', 'armhf': '5000', 'ppc64el': '5000', 'riscv64': '5000'}> +CONFIG_AIC7XXX_CMDS_PER_DEVICE policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_AIC7XXX_DEBUG_ENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_AIC7XXX_DEBUG_MASK policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_AIC7XXX_REG_PRETTY_PRINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AIC7XXX_RESET_DELAY_MS policy<{'amd64': '5000', 'arm64': '5000', 'armhf': '5000', 'ppc64el': '5000', 'riscv64': '5000'}> +CONFIG_AIC94XX_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_AIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AIROHA_CPU_PM_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AIROHA_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AIROHA_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AIR_EN8811H_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AIX_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_AK09911 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AK8974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AK8975 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AL3000A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AL3010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AL3320A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALIBABA_ENI_VDPA policy<{'amd64': 'm'}> +CONFIG_ALIBABA_UNCORE_DRW_PMU policy<{'arm64': 'm'}> +CONFIG_ALIENWARE_WMI policy<{'amd64': 'm'}> +CONFIG_ALIENWARE_WMI_LEGACY policy<{'amd64': 'y'}> +CONFIG_ALIENWARE_WMI_WMAX policy<{'amd64': 'y'}> +CONFIG_ALIGNMENT_TRAP policy<{'armhf': 'y'}> +CONFIG_ALIM1535_WDT policy<{'amd64': 'm'}> +CONFIG_ALIM7101_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ALLOW_DEV_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ALS31300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALTERA_FREEZE_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALTERA_MBOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ALTERA_MSGDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ALTERA_PR_IP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ALTERA_PR_IP_CORE_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ALTERA_STAPL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ALTERA_TSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ALTERNATE_USER_ADDRESS_SPACE policy<{'s390x': 'y'}> +CONFIG_ALTIVEC policy<{'ppc64el': 'y'}> +CONFIG_ALX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_AL_FIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AM2315 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AM335X_CONTROL_USB policy<{'armhf': 'm'}> +CONFIG_AM335X_PHY_USB policy<{'armhf': 'm'}> +CONFIG_AMBA_PL08X policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_AMCC_QT2025_PHY policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_AMD8111_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_AMDTEE policy<{'amd64': 'm'}> +CONFIG_AMD_3D_VCACHE policy<{'amd64': 'm'}> +CONFIG_AMD_AE4DMA policy<{'amd64': 'm'}> +CONFIG_AMD_ATL policy<{'amd64': 'm'}> +CONFIG_AMD_ATL_PRM policy<{'amd64': 'y'}> +CONFIG_AMD_HFI policy<{'amd64': 'y'}> +CONFIG_AMD_HSMP policy<{'amd64': 'm'}> +CONFIG_AMD_HSMP_ACPI policy<{'amd64': 'm'}> +CONFIG_AMD_HSMP_PLAT policy<{'amd64': 'm'}> +CONFIG_AMD_IOMMU policy<{'amd64': 'y'}> +CONFIG_AMD_IOMMU_IOMMUFD policy<{'amd64': 'n'}> +CONFIG_AMD_ISP_PLATFORM policy<{'amd64': 'm'}> +CONFIG_AMD_MEM_ENCRYPT policy<{'amd64': 'y'}> +CONFIG_AMD_MP2_STB policy<{'amd64': 'y'}> +CONFIG_AMD_NB policy<{'amd64': 'y'}> +CONFIG_AMD_NODE policy<{'amd64': 'y'}> +CONFIG_AMD_NUMA policy<{'amd64': 'y'}> +CONFIG_AMD_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AMD_PMC policy<{'amd64': 'm'}> +CONFIG_AMD_PMF policy<{'amd64': 'm'}> +CONFIG_AMD_PMF_DEBUG policy<{'amd64': 'y'}> +CONFIG_AMD_PTDMA policy<{'amd64': 'm'}> +CONFIG_AMD_QDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AMD_SBRMI_HWMON policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_AMD_SBRMI_I2C policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_AMD_SECURE_AVIC policy<{'amd64': 'y'}> +CONFIG_AMD_SFH_HID policy<{'amd64': 'm'}> +CONFIG_AMD_WBRF policy<{'amd64': 'y'}> +CONFIG_AMD_XGBE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_AMD_XGBE_DCB policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_AMD_XGBE_HAVE_ECC policy<{'amd64': 'y'}> +CONFIG_AMIGA_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_AMILO_RFKILL policy<{'amd64': 'm'}> +CONFIG_AMLOGIC_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_AMPERE_ERRATUM_AC03_CPU_38 policy<{'arm64': 'y'}> +CONFIG_AMPERE_ERRATUM_AC04_CPU_23 policy<{'arm64': 'y'}> +CONFIG_AMT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ANDROID_BINDERFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ANDROID_BINDER_DEVICES policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""'}> +CONFIG_ANDROID_BINDER_IPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ANDROID_BINDER_IPC_RUST policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_ANON_VMA_NAME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AOSONG_AGS02MA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AP policy<{'s390x': 'y'}> +CONFIG_APDS9160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APDS9300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APDS9306 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APDS9802ALS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_APDS9960 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_APERTURE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_APM_EMULATION policy<{'armhf': 'n'}> +CONFIG_APPLDATA_BASE policy<{'s390x': 'y'}> +CONFIG_APPLDATA_MEM policy<{'s390x': 'm'}> +CONFIG_APPLDATA_NET_SUM policy<{'s390x': 'm'}> +CONFIG_APPLDATA_OS policy<{'s390x': 'm'}> +CONFIG_APPLE_ADMAC policy<{'arm64': 'm'}> +CONFIG_APPLE_AIC policy<{'arm64': 'y'}> +CONFIG_APPLE_DART policy<{'arm64': 'm'}> +CONFIG_APPLE_GMUX policy<{'amd64': 'm'}> +CONFIG_APPLE_M1_CPU_PMU policy<{'arm64': 'y'}> +CONFIG_APPLE_MAILBOX policy<{'arm64': 'm'}> +CONFIG_APPLE_MFI_FASTCHARGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_APPLE_PMGR_PWRSTATE policy<{'arm64': 'y'}> +CONFIG_APPLE_PROPERTIES policy<{'amd64': 'y'}> +CONFIG_APPLE_RTKIT policy<{'arm64': 'm'}> +CONFIG_APPLE_SART policy<{'arm64': 'm'}> +CONFIG_APPLE_TUNABLE policy<{'arm64': 'm'}> +CONFIG_APPLE_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_APPLICOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_APQ_GCC_8084 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_APQ_MMCC_8084 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_AP_DEBUG policy<{'s390x': 'n'}> +CONFIG_AQTION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AQUANTIA_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AR5523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCH_32BIT_OFF_T policy<{'armhf': 'y'}> +CONFIG_ARCH_32BIT_USTAT_F_TINODE policy<{'s390x': 'y'}> +CONFIG_ARCH_ACTIONS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_AIROHA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_ALPINE policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARCH_ANDES policy<{'riscv64': 'n'}> +CONFIG_ARCH_ANLOGIC policy<{'riscv64': 'n'}> +CONFIG_ARCH_APPLE policy<{'arm64': 'y'}> +CONFIG_ARCH_ARTPEC policy<{'armhf': 'y'}> +CONFIG_ARCH_ASPEED policy<{'armhf': 'y'}> +CONFIG_ARCH_AT91 policy<{'armhf': 'n'}> +CONFIG_ARCH_AXIADO policy<{'arm64': 'y'}> +CONFIG_ARCH_AXXIA policy<{'armhf': 'y'}> +CONFIG_ARCH_BCM policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARCH_BERLIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS policy<{'arm64': 'y'}> +CONFIG_ARCH_BINFMT_ELF_STATE policy<{'arm64': 'y', 's390x': '-'}> +CONFIG_ARCH_BITMAIN policy<{'arm64': 'y'}> +CONFIG_ARCH_BLAIZE policy<{'arm64': 'y'}> +CONFIG_ARCH_BST policy<{'arm64': 'y'}> +CONFIG_ARCH_CANAAN policy<{'riscv64': 'n'}> +CONFIG_ARCH_CC_CAN_LINK policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_CIX policy<{'arm64': 'y'}> +CONFIG_ARCH_CLOCKSOURCE_INIT policy<{'amd64': 'y', 'riscv64': '-'}> +CONFIG_ARCH_CONFIGURES_CPU_MITIGATIONS policy<{'amd64': 'y'}> +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_CPUIDLE_HALTPOLL policy<{'amd64': 'y'}> +CONFIG_ARCH_CPU_PROBE_RELEASE policy<{'ppc64el': 'y'}> +CONFIG_ARCH_DEFAULT_CRASH_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_ARCH_DIGICOLOR policy<{'armhf': 'n'}> +CONFIG_ARCH_DISABLE_KASAN_INLINE policy<{'ppc64el': 'y'}> +CONFIG_ARCH_DMA_ADDR_T_64BIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_DMA_DEFAULT_COHERENT policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_DOVE policy<{'armhf': 'n'}> +CONFIG_ARCH_EMEV2 policy<{'armhf': 'y'}> +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_ENABLE_THP_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_ESWIN policy<{'riscv64': 'n'}> +CONFIG_ARCH_EXYNOS policy<{'arm64': 'n', 'armhf': 'y'}> +CONFIG_ARCH_EXYNOS3 policy<{'armhf': 'n'}> +CONFIG_ARCH_EXYNOS4 policy<{'armhf': 'n'}> +CONFIG_ARCH_EXYNOS5 policy<{'armhf': 'n'}> +CONFIG_ARCH_FLATMEM_ENABLE policy<{'armhf': 'y'}> +CONFIG_ARCH_FORCE_MAX_ORDER policy<{'arm64': '13', 'armhf': '11', 'ppc64el': '8'}> +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_ADD_PAGES policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_BANDGAP policy<{'armhf': 'y'}> +CONFIG_ARCH_HAS_BINFMT_FLAT policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_CACHE_LINE_SIZE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HAS_CC_CAN_LINK policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_CC_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_COPY_MC policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_CPU_ATTACK_VECTORS policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_CPU_CACHE_ALIASING policy<{'armhf': 'y'}> +CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_CPU_FINALIZE_INIT policy<{'amd64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_CPU_PASID policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_CPU_RELAX policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_CPU_RESCTRL policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEBUG_VIRTUAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEBUG_WX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DMA_ALLOC policy<{'armhf': 'y'}> +CONFIG_ARCH_HAS_DMA_MAP_DIRECT policy<{'ppc64el': 'y'}> +CONFIG_ARCH_HAS_DMA_OPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_DMA_PREP_COHERENT policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_EARLY_DEBUG policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_ELFCORE_COMPAT policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_ELF_CORE_EFLAGS policy<{'riscv64': 'y'}> +CONFIG_ARCH_HAS_ELF_RANDOMIZE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_EXECMEM_ROX policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_FAST_MULTIPLIER policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_FORTIFY_SOURCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_GIGANTIC_PAGE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_HW_PTE_YOUNG policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_KCOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_KEEPINITRD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_LAZY_MMU_MODE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_MEMREMAP_COMPAT_ALIGN policy<{'ppc64el': 'y'}> +CONFIG_ARCH_HAS_MEM_ENCRYPT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_MMIOWB policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH policy<{'amd64': 'y'}> +CONFIG_ARCH_HAS_PHYS_TO_DMA policy<{'ppc64el': 'y'}> +CONFIG_ARCH_HAS_PKEYS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_PMEM_API policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_PREEMPT_LAZY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD policy<{'riscv64': 'y'}> +CONFIG_ARCH_HAS_PTDUMP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_PTE_SPECIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_RELR policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_RESET_CONTROLLER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HAS_SCALED_CPUTIME policy<{'s390x': 'y'}> +CONFIG_ARCH_HAS_SETUP_DMA_OPS policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SET_DIRECT_MAP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_SET_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_STRICT_MODULE_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_SUBPAGE_FAULTS policy<{'arm64': 'y'}> +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_SYSCALL_WRAPPER policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS policy<{'arm64': '-', 'armhf': 'y'}> +CONFIG_ARCH_HAS_TICK_BROADCAST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_HAS_UBSAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAS_USER_SHADOW_STACK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_VDSO_ARCH_DATA policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HAS_VDSO_TIME_DATA policy<{'riscv64': '-', 's390x': 'y'}> +CONFIG_ARCH_HAS_ZONE_DMA_SET policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAVE_ELF_PROT policy<{'arm64': 'y'}> +CONFIG_ARCH_HAVE_EXTRA_ELF_NOTES policy<{'amd64': 'y'}> +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS policy<{'arm64': 'y', 's390x': 'y'}> +CONFIG_ARCH_HI3xxx policy<{'armhf': 'y'}> +CONFIG_ARCH_HIBERNATION_HEADER policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HIBERNATION_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_HIGHBANK policy<{'armhf': 'y'}> +CONFIG_ARCH_HIP01 policy<{'armhf': 'n'}> +CONFIG_ARCH_HIP04 policy<{'armhf': 'y'}> +CONFIG_ARCH_HISI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_HIX5HD2 policy<{'armhf': 'y'}> +CONFIG_ARCH_HPE policy<{'armhf': 'y'}> +CONFIG_ARCH_HPE_GXP policy<{'armhf': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ policy<{'s390x': 'y'}> +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_ARCH_INTEL_SOCFPGA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_K3 policy<{'arm64': 'y'}> +CONFIG_ARCH_KEEMBAY policy<{'arm64': 'y'}> +CONFIG_ARCH_KEEP_MEMBLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_KEYSTONE policy<{'armhf': 'n'}> +CONFIG_ARCH_LAN969X policy<{'arm64': 'y'}> +CONFIG_ARCH_LAYERSCAPE policy<{'arm64': 'y'}> +CONFIG_ARCH_LG1K policy<{'arm64': 'y'}> +CONFIG_ARCH_MA35 policy<{'arm64': 'y'}> +CONFIG_ARCH_MAY_HAVE_PC_FDC policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MEDIATEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MEMORY_PROBE policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MICROCHIP policy<{'arm64': 'y', 'riscv64': 'n'}> +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC policy<{'amd64': 'y'}> +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_MILBEAUT policy<{'armhf': 'y'}> +CONFIG_ARCH_MILBEAUT_M10V policy<{'armhf': 'y'}> +CONFIG_ARCH_MMAP_RND_BITS_MAX policy<{'amd64': '32', 'arm64': '33', 'arm64-generic-64k': '29', 'armhf': '16', 'ppc64el': '29', 'riscv64': '24'}> +CONFIG_ARCH_MMAP_RND_BITS_MIN policy<{'amd64': '28', 'arm64': '18', 'arm64-generic-64k': '14', 'armhf': '8', 'ppc64el': '14', 'riscv64': '18'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX policy<{'amd64': '16', 'arm64': '16', 'ppc64el': '13', 'riscv64': '17'}> +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN policy<{'amd64': '8', 'arm64': '11', 'arm64-generic-64k': '7', 'ppc64el': '7', 'riscv64': '8'}> +CONFIG_ARCH_MMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MSTARV7 policy<{'armhf': 'y'}> +CONFIG_ARCH_MULTIPLATFORM policy<{'armhf': 'y'}> +CONFIG_ARCH_MULTI_V6 policy<{'armhf': 'n'}> +CONFIG_ARCH_MULTI_V6_V7 policy<{'armhf': 'y'}> +CONFIG_ARCH_MULTI_V7 policy<{'armhf': 'y'}> +CONFIG_ARCH_MVEBU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_MXC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED policy<{'armhf': 'y'}> +CONFIG_ARCH_NEEDS_DEFER_KASAN policy<{'ppc64el': 'y'}> +CONFIG_ARCH_NPCM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_NPCM7XX policy<{'armhf': 'y'}> +CONFIG_ARCH_NXP policy<{'arm64': 'y'}> +CONFIG_ARCH_OMAP policy<{'armhf': 'y'}> +CONFIG_ARCH_OMAP2PLUS policy<{'armhf': 'y'}> +CONFIG_ARCH_OMAP2PLUS_TYPICAL policy<{'armhf': 'y'}> +CONFIG_ARCH_OMAP3 policy<{'armhf': 'n'}> +CONFIG_ARCH_OMAP4 policy<{'armhf': 'n'}> +CONFIG_ARCH_OPTIONAL_KERNEL_RWX policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_PENSANDO policy<{'arm64': 'y'}> +CONFIG_ARCH_PKEY_BITS policy<{'amd64': '4', 'arm64': '3', 'ppc64el': '5'}> +CONFIG_ARCH_PROC_KCORE_TEXT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_QCOM_RESERVE_SMEM policy<{'armhf': 'y'}> +CONFIG_ARCH_R7S72100 policy<{'armhf': 'y'}> +CONFIG_ARCH_R7S9210 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A73A4 policy<{'armhf': 'n'}> +CONFIG_ARCH_R8A7740 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7742 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7743 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7744 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7745 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A77470 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A7778 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7779 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7790 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7791 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7792 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7793 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A7794 policy<{'armhf': 'y'}> +CONFIG_ARCH_R8A77951 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77960 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77961 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77965 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77970 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77980 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77990 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A77995 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_ARCH_R8A78000 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A06G032 policy<{'armhf': 'y'}> +CONFIG_ARCH_R9A07G043 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A07G044 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A07G054 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G011 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G047 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G077 policy<{'arm64': 'y'}> +CONFIG_ARCH_R9A09G087 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN1 policy<{'armhf': 'y'}> +CONFIG_ARCH_RCAR_GEN2 policy<{'armhf': 'y'}> +CONFIG_ARCH_RCAR_GEN3 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN4 policy<{'arm64': 'y'}> +CONFIG_ARCH_RCAR_GEN5 policy<{'arm64': 'y'}> +CONFIG_ARCH_RDA policy<{'armhf': 'y'}> +CONFIG_ARCH_REALTEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_REALVIEW policy<{'armhf': 'n'}> +CONFIG_ARCH_RENESAS policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'n'}> +CONFIG_ARCH_RMOBILE policy<{'armhf': 'y'}> +CONFIG_ARCH_RV64I policy<{'riscv64': 'y'}> +CONFIG_ARCH_RZG2L policy<{'arm64': 'y'}> +CONFIG_ARCH_RZN1 policy<{'armhf': 'y'}> +CONFIG_ARCH_S32 policy<{'arm64': 'y'}> +CONFIG_ARCH_S5PV210 policy<{'armhf': 'n'}> +CONFIG_ARCH_SEATTLE policy<{'arm64': 'y'}> +CONFIG_ARCH_SELECTS_CRASH_DUMP policy<{'ppc64el': 'y'}> +CONFIG_ARCH_SELECTS_KEXEC policy<{'riscv64': 'y'}> +CONFIG_ARCH_SELECTS_KEXEC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SELECT_MEMORY_MODEL policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SH73A0 policy<{'armhf': 'y'}> +CONFIG_ARCH_SIFIVE policy<{'riscv64': 'n'}> +CONFIG_ARCH_SOPHGO policy<{'arm64': 'y', 'riscv64': 'n'}> +CONFIG_ARCH_SPACEMIT policy<{'riscv64': 'n'}> +CONFIG_ARCH_SPARSEMEM_DEFAULT policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_SPARSEMEM_ENABLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SPARX5 policy<{'arm64': 'y'}> +CONFIG_ARCH_SPRD policy<{'arm64': 'y'}> +CONFIG_ARCH_STACKWALK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_STI policy<{'armhf': 'n'}> +CONFIG_ARCH_STM32 policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_ARCH_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_ARCH_SUNXI policy<{'arm64': 'y', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_ARCH_SUPPORTS_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_AUTOFDO_CLANG policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_CFI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_CRASH_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_CRASH_HOTPLUG policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_HUGETLBFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_INT128 policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_JUMP policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_SIG policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_KEXEC_SIG_FORCE policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_LTO_CLANG policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_PMD_PFNMAP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_PROPELLER_CLANG policy<{'amd64': 'y'}> +CONFIG_ARCH_SUPPORTS_PUD_PFNMAP policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_RT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_CLUSTER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_MC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_SCHED_SMT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_ARCH_SUPPORTS_UPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_SUSPEND_NONZERO_CPU policy<{'ppc64el': 'y'}> +CONFIG_ARCH_SUSPEND_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_SYNQUACER policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_TEGRA_114_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TEGRA_124_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TEGRA_132_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_186_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_194_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_210_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_234_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_241_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_264_SOC policy<{'arm64': 'y'}> +CONFIG_ARCH_TEGRA_2x_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TEGRA_3x_SOC policy<{'armhf': 'y'}> +CONFIG_ARCH_TENSTORRENT policy<{'riscv64': 'n'}> +CONFIG_ARCH_THEAD policy<{'riscv64': 'n'}> +CONFIG_ARCH_THUNDER policy<{'arm64': 'y'}> +CONFIG_ARCH_THUNDER2 policy<{'arm64': 'y'}> +CONFIG_ARCH_U8500 policy<{'armhf': 'n'}> +CONFIG_ARCH_UNIPHIER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARCH_USERFLAGS policy<{'armhf': '"-mlittle-endian"', 's390x': '"-m64"'}> +CONFIG_ARCH_USES_CFI_GENERIC_LLVM_PASS policy<{'armhf': 'y'}> +CONFIG_ARCH_USES_HIGH_VMA_FLAGS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USES_PG_ARCH_2 policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_USES_PG_ARCH_3 policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_BUILTIN_BSWAP policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_USE_CMPXCHG_LOCKREF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_USE_GNU_PROPERTY policy<{'arm64': 'y'}> +CONFIG_ARCH_USE_MEMREMAP_PROT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_MEMTEST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_QUEUED_RWLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_QUEUED_SPINLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_USE_SYM_ANNOTATIONS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_USING_PATCHABLE_FUNCTION_ENTRY policy<{'ppc64el': 'y'}> +CONFIG_ARCH_VEXPRESS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA policy<{'armhf': 'y'}> +CONFIG_ARCH_VEXPRESS_SPC policy<{'armhf': 'y'}> +CONFIG_ARCH_VEXPRESS_TC2_PM policy<{'armhf': 'y'}> +CONFIG_ARCH_VIRT policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_VISCONTI policy<{'arm64': 'y'}> +CONFIG_ARCH_VMLINUX_NEEDS_RELOCS policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT policy<{'amd64': 'y', 's390x': '-'}> +CONFIG_ARCH_WANTS_EXECMEM_LATE policy<{'arm64': 'y'}> +CONFIG_ARCH_WANTS_NO_INSTR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANTS_PRE_LINK_VMLINUX policy<{'ppc64el': 'y'}> +CONFIG_ARCH_WANTS_THP_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_FLAT_DTB_INSTALL policy<{'armhf': 'y'}> +CONFIG_ARCH_WANT_FRAME_POINTERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_GENERAL_HUGETLB policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_ARCH_WANT_HUGETLB_VMEMMAP_PREINIT policy<{'amd64': 'y'}> +CONFIG_ARCH_WANT_HUGE_PMD_SHARE policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_IPC_PARSE_VERSION policy<{'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_IRQS_OFF_ACTIVATE_MM policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_KERNEL_PMD_MKWRITE policy<{'s390x': 'y'}> +CONFIG_ARCH_WANT_LD_ORPHAN_WARN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WANT_OLD_COMPAT_IPC policy<{'amd64': 'y', 'ppc64el': '-', 's390x': '-'}> +CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP policy<{'amd64': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_ARCH_WANT_PMD_MKWRITE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ARCH_WEAK_RELEASE_ACQUIRE policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ARCH_WM8850 policy<{'armhf': 'n'}> +CONFIG_ARCH_XGENE policy<{'arm64': 'y'}> +CONFIG_ARCH_ZYNQ policy<{'armhf': 'n'}> +CONFIG_ARCH_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_ARCNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ARCNET_1051 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_1201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_CAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM20020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM20020_CS policy<{'amd64': 'm'}> +CONFIG_ARCNET_COM20020_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM90xx policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_COM90xxIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARCNET_RIM_I policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ARC_EMAC_CORE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM policy<{'armhf': 'y'}> +CONFIG_ARM64 policy<{'arm64': 'y'}> +CONFIG_ARM64_16K_PAGES policy<{'arm64': 'n'}> +CONFIG_ARM64_4K_PAGES policy<{'arm64': 'y', 'arm64-generic-64k': 'n'}> +CONFIG_ARM64_64K_PAGES policy<{'arm64': 'n', 'arm64-generic-64k': 'y'}> +CONFIG_ARM64_ACPI_PARKING_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_ARM64_AMU_EXTN policy<{'arm64': 'y'}> +CONFIG_ARM64_AS_HAS_MTE policy<{'arm64': 'y'}> +CONFIG_ARM64_BRBE policy<{'arm64': 'y'}> +CONFIG_ARM64_BTI policy<{'arm64': 'y'}> +CONFIG_ARM64_CNP policy<{'arm64': 'y'}> +CONFIG_ARM64_CONTPTE policy<{'arm64': 'y'}> +CONFIG_ARM64_CONT_PMD_SHIFT policy<{'arm64': '4', 'arm64-generic-64k': '5'}> +CONFIG_ARM64_CONT_PTE_SHIFT policy<{'arm64': '4', 'arm64-generic-64k': '5'}> +CONFIG_ARM64_DEBUG_PRIORITY_MASKING policy<{'arm64': 'n'}> +CONFIG_ARM64_E0PD policy<{'arm64': 'y'}> +CONFIG_ARM64_EPAN policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1024718 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1165522 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1286807 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1319367 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1418040 policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_ERRATUM_1463225 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1508412 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1530923 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1542419 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1742098 policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_ERRATUM_2051678 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2054223 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2067961 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2077057 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2441007 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2441009 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2457168 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2645198 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2658417 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2966298 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_3117295 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_3194386 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_4311569 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_819472 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_824069 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_826319 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_827319 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_832075 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_834220 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_845719 policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_GCS policy<{'arm64': 'y'}> +CONFIG_ARM64_HAFT policy<{'arm64': 'y'}> +CONFIG_ARM64_HW_AFDBM policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM_DRIVER policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM_DRIVER_DEBUG policy<{'arm64': 'n'}> +CONFIG_ARM64_MTE policy<{'arm64': 'y'}> +CONFIG_ARM64_PA_BITS policy<{'arm64': '48'}> +CONFIG_ARM64_PA_BITS_48 policy<{'arm64': 'y'}> +CONFIG_ARM64_PA_BITS_52 policy<{'arm64-generic-64k': 'n'}> +CONFIG_ARM64_PLATFORM_DEVICES policy<{'arm64': 'y'}> +CONFIG_ARM64_PMEM policy<{'arm64': 'y'}> +CONFIG_ARM64_POE policy<{'arm64': 'y'}> +CONFIG_ARM64_PSEUDO_NMI policy<{'arm64': 'y'}> +CONFIG_ARM64_PTR_AUTH policy<{'arm64': 'y'}> +CONFIG_ARM64_PTR_AUTH_KERNEL policy<{'arm64': 'y'}> +CONFIG_ARM64_RAS_EXTN policy<{'arm64': 'y'}> +CONFIG_ARM64_RELOC_TEST policy<{'arm64': 'n'}> +CONFIG_ARM64_SME policy<{'arm64': 'y'}> +CONFIG_ARM64_SVE policy<{'arm64': 'y'}> +CONFIG_ARM64_SW_TTBR0_PAN policy<{'arm64': 'y'}> +CONFIG_ARM64_TAGGED_ADDR_ABI policy<{'arm64': 'y'}> +CONFIG_ARM64_TLB_RANGE policy<{'arm64': 'y'}> +CONFIG_ARM64_VA_BITS policy<{'arm64': '48'}> +CONFIG_ARM64_VA_BITS_39 policy<{'arm64': 'n', 'arm64-generic-64k': '-'}> +CONFIG_ARM64_VA_BITS_42 policy<{'arm64-generic-64k': 'n'}> +CONFIG_ARM64_VA_BITS_52 policy<{'arm64': 'n'}> +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE policy<{'arm64': 'y'}> +CONFIG_ARMADA375_USBCLUSTER_PHY policy<{'armhf': 'y'}> +CONFIG_ARMADA_370_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_370_XP_IRQ policy<{'armhf': 'y'}> +CONFIG_ARMADA_370_XP_TIMER policy<{'armhf': 'y'}> +CONFIG_ARMADA_375_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_37XX_CLK policy<{'arm64': 'y'}> +CONFIG_ARMADA_37XX_RWTM_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARMADA_37XX_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARMADA_38X_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_39X_CLK policy<{'armhf': 'y'}> +CONFIG_ARMADA_AP806_SYSCON policy<{'arm64': 'y'}> +CONFIG_ARMADA_AP_CPU_CLK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARMADA_AP_CP_HELPER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARMADA_CP110_SYSCON policy<{'arm64': 'y'}> +CONFIG_ARMADA_THERMAL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARMADA_XP_CLK policy<{'armhf': 'y'}> +CONFIG_ARM_AIROHA_SOC_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_ARM_AMBA policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_ARM_APPENDED_DTB policy<{'armhf': 'y'}> +CONFIG_ARM_APPLE_SOC_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_ARCH_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_ARCH_TIMER_EVTSTREAM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND policy<{'arm64': 'y'}> +CONFIG_ARM_ARMADA_37XX_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_ARMADA_8K_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_ATAG_DTB_COMPAT policy<{'armhf': 'n'}> +CONFIG_ARM_BIG_LITTLE_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_CCA_GUEST policy<{'arm64': 'm'}> +CONFIG_ARM_CCI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI400_COMMON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI400_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI400_PORT_CTRL policy<{'armhf': 'y'}> +CONFIG_ARM_CCI5xx_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCI_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CCN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_CHARLCD policy<{'armhf': 'y'}> +CONFIG_ARM_CMN policy<{'arm64': 'm'}> +CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_CPU_SUSPEND policy<{'armhf': 'y'}> +CONFIG_ARM_CPU_TOPOLOGY policy<{'armhf': 'y'}> +CONFIG_ARM_DEBUG_WX policy<{'armhf': 'y'}> +CONFIG_ARM_DMA350 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_DMA_IOMMU_ALIGNMENT policy<{'armhf': '8'}> +CONFIG_ARM_DMA_MEM_BUFFERABLE policy<{'armhf': 'y'}> +CONFIG_ARM_DMA_USE_IOMMU policy<{'armhf': 'y'}> +CONFIG_ARM_DMC620_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_DSU_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_ERRATA_430973 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_643719 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_720789 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_754322 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_754327 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_764319 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_764369 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_773022 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_775420 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_798181 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_814220 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_818325_852422 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_821420 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_825619 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_852421 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_852423 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_857271 policy<{'armhf': 'y'}> +CONFIG_ARM_ERRATA_857272 policy<{'armhf': 'y'}> +CONFIG_ARM_EXYNOS_BUS_DEVFREQ policy<{'armhf': 'n'}> +CONFIG_ARM_EXYNOS_CPUIDLE policy<{'armhf': 'n'}> +CONFIG_ARM_FFA_SMCCC policy<{'arm64': 'y'}> +CONFIG_ARM_FFA_TRANSPORT policy<{'arm64': 'm'}> +CONFIG_ARM_GIC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_ITS_PARENT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_MAX_NR policy<{'arm64': '1', 'armhf': '1'}> +CONFIG_ARM_GIC_PM policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V2M policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_V3 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_V3_ITS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_GIC_V3_ITS_FSL_MC policy<{'arm64': 'y'}> +CONFIG_ARM_GIC_V5 policy<{'arm64': 'y'}> +CONFIG_ARM_GLOBAL_TIMER policy<{'armhf': 'y'}> +CONFIG_ARM_GT_INITIAL_PRESCALER_VAL policy<{'armhf': '1'}> +CONFIG_ARM_HAS_GROUP_RELOCS policy<{'armhf': 'y'}> +CONFIG_ARM_HEAVY_MB policy<{'armhf': 'y'}> +CONFIG_ARM_HIGHBANK_CPUFREQ policy<{'armhf': 'm'}> +CONFIG_ARM_HISI_UNCORE_DEVFREQ policy<{'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ARM_IMX6Q_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_IMX8M_DDRC_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_IMX_BUS_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_IMX_CPUFREQ_DT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_KPROBES_TEST policy<{'armhf': 'm'}> +CONFIG_ARM_L1_CACHE_SHIFT policy<{'armhf': '6'}> +CONFIG_ARM_L1_CACHE_SHIFT_6 policy<{'armhf': 'y'}> +CONFIG_ARM_LPAE policy<{'armhf': 'y'}> +CONFIG_ARM_MEDIATEK_CCI_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_MEDIATEK_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_MEDIATEK_CPUFREQ_HW policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_MHU policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_ARM_MHU_V2 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_ARM_MHU_V3 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_ARM_MODULE_PLTS policy<{'armhf': 'y'}> +CONFIG_ARM_MVEBU_V7_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_NI policy<{'arm64': 'n'}> +CONFIG_ARM_PAN policy<{'armhf': 'y'}> +CONFIG_ARM_PATCH_IDIV policy<{'armhf': 'y'}> +CONFIG_ARM_PATCH_PHYS_VIRT policy<{'armhf': 'y'}> +CONFIG_ARM_PKVM_GUEST policy<{'arm64': 'n'}> +CONFIG_ARM_PL172_MPMC policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_ARM_PMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PMUV3 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PMU_ACPI policy<{'arm64': 'y'}> +CONFIG_ARM_PSCI policy<{'armhf': 'y'}> +CONFIG_ARM_PSCI_CHECKER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARM_PSCI_CPUIDLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PSCI_FW policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_PTDUMP_CORE policy<{'armhf': 'y'}> +CONFIG_ARM_PTDUMP_DEBUGFS policy<{'armhf': 'n'}> +CONFIG_ARM_QCOM_CPUFREQ_HW policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_QCOM_CPUFREQ_NVMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_QCOM_SPM_CPUIDLE policy<{'armhf': 'y'}> +CONFIG_ARM_RK3399_DMC_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SBSA_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_ARM_SCMI_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_DEBUG_COUNTERS policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_ARM_SCMI_HAVE_MSG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_HAVE_SHMEM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_HAVE_TRANSPORT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_NEED_DEBUGFS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_PERF_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_POWERCAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_POWER_CONTROL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_POWER_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_PROTOCOL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_QUIRKS policy<{'arm64': 'y'}> +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCMI_TRANSPORT_SMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SCPI_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCPI_POWER_DOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SCPI_PROTOCOL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SDE_INTERFACE policy<{'arm64': 'y'}> +CONFIG_ARM_SMCCC_SOC_ID policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_SMC_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SMMU policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_QCOM policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_QCOM_DEBUG policy<{'arm64': 'y', 'arm64-generic-64k': 'n'}> +CONFIG_ARM_SMMU_V3 policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_V3_IOMMUFD policy<{'arm64': 'n'}> +CONFIG_ARM_SMMU_V3_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_SMMU_V3_SVA policy<{'arm64': 'y'}> +CONFIG_ARM_SP805_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_SPE_PMU policy<{'arm64': 'm'}> +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_ARM_TEGRA124_CPUFREQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TEGRA186_CPUFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_TEGRA194_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_ARM_TEGRA20_CPUFREQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TEGRA_CPUIDLE policy<{'armhf': 'n'}> +CONFIG_ARM_TEGRA_DEVFREQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ARM_THUMB policy<{'armhf': 'y'}> +CONFIG_ARM_THUMBEE policy<{'armhf': 'y'}> +CONFIG_ARM_TIMER_SP804 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TI_CPUFREQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ARM_TSTEE policy<{'arm64': 'm'}> +CONFIG_ARM_V7_PMU policy<{'armhf': 'y'}> +CONFIG_ARM_VEXPRESS_SPC_CPUFREQ policy<{'armhf': 'm'}> +CONFIG_ARM_VIC policy<{'armhf': 'y'}> +CONFIG_ARM_VIC_NR policy<{'armhf': '2'}> +CONFIG_ARM_VIRT_EXT policy<{'armhf': 'y'}> +CONFIG_AS21XXX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AS3935 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AS73211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ASM_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASN1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASN1_ENCODER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ASPEED_ADC policy<{'armhf': 'm'}> +CONFIG_ASPEED_BT_IPMI_BMC policy<{'armhf': 'm'}> +CONFIG_ASPEED_KCS_IPMI_BMC policy<{'armhf': 'm'}> +CONFIG_ASPEED_LPC_CTRL policy<{'armhf': 'm'}> +CONFIG_ASPEED_LPC_SNOOP policy<{'armhf': 'm'}> +CONFIG_ASPEED_P2A_CTRL policy<{'armhf': 'm'}> +CONFIG_ASPEED_SOCINFO policy<{'armhf': 'y'}> +CONFIG_ASPEED_UART_ROUTING policy<{'armhf': 'm'}> +CONFIG_ASPEED_WATCHDOG policy<{'armhf': 'y'}> +CONFIG_ASSOCIATIVE_ARRAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AST2600_I3C_MASTER policy<{'armhf': 'm'}> +CONFIG_AST2700_MBOX policy<{'armhf': 'm'}> +CONFIG_ASUS_ARMOURY policy<{'amd64': 'm'}> +CONFIG_ASUS_LAPTOP policy<{'amd64': 'm'}> +CONFIG_ASUS_NB_WMI policy<{'amd64': 'm'}> +CONFIG_ASUS_TF103C_DOCK policy<{'amd64': 'm'}> +CONFIG_ASUS_WIRELESS policy<{'amd64': 'm'}> +CONFIG_ASUS_WMI policy<{'amd64': 'm'}> +CONFIG_ASUS_WMI_DEPRECATED_ATTRS policy<{'amd64': 'y'}> +CONFIG_ASYNC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_KERNEL_PGTABLE_FREE policy<{'amd64': 'y'}> +CONFIG_ASYNC_MEMCPY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_PQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_RAID6_RECOV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ASYNC_RAID6_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA policy<{'arm64': 'y'}> +CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA policy<{'arm64': 'y'}> +CONFIG_ASYNC_TX_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ASYNC_XOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_AS_HAS_ARMV8_5 policy<{'arm64': 'y'}> +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE policy<{'arm64': 'y'}> +CONFIG_AS_HAS_INSN policy<{'riscv64': 'y'}> +CONFIG_AS_HAS_MOPS policy<{'arm64': 'y'}> +CONFIG_AS_HAS_NON_CONST_ULEB128 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AS_HAS_OPTION_ARCH policy<{'riscv64': 'y'}> +CONFIG_AS_HAS_ULEB128 policy<{'riscv64': 'y'}> +CONFIG_AS_IS_GNU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AS_VERSION policy<{'amd64': '24600', 'arm64': '24600', 'armhf': '24600', 'ppc64el': '24600', 'riscv64': '24600', 's390x': '24600'}> +CONFIG_AS_WRUSS policy<{'amd64': 'y'}> +CONFIG_AT76C50X_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AT803X_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_ATAGS policy<{'armhf': 'y'}> +CONFIG_ATAGS_PROC policy<{'armhf': 'y'}> +CONFIG_ATALK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ATARI_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_ATA_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ATA_BMDMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATA_FORCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATA_GENERIC policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATA_OVER_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ATA_SFF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATA_VERBOSE_ERROR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH10K_AHB policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_CE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH10K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH10K_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH10K_SNOC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ATH10K_SPECTRAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH10K_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K_AHB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K_CFR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH11K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH11K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH11K_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH11K_SPECTRAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH11K_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH12K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_ATH12K_AHB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ATH12K_COREDUMP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_ATH12K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_ATH12K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ATH12K_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_ATH5K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH5K_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH5K_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH5K_TRACER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH6KL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH6KL_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH6KL_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH6KL_TRACING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH6KL_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_AHB policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_BTCOEX_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_CHANNEL_CONTEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_COMMON_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_COMMON_SPECTRAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_DYNACK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATH9K_HTC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_HTC_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_HW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_PCI_NO_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH9K_PCOEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_RFKILL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_STATION_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH9K_WOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATH_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATH_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ATL1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATL1C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATL1E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATL2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ATLAS_EZO_SENSOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATLAS_PH_SENSOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ATM_BR2684 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_BR2684_IPFILTER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_CLIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_CLIP_NO_ICMP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATM_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_ENI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_ENI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_ENI_TUNE_BURST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_FORE200E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_FORE200E_DEBUG policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_ATM_FORE200E_TX_RETRY policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16'}> +CONFIG_ATM_FORE200E_USE_TASKLET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_HE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_HE_USE_SUNI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATM_IA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_IA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_IDT77252 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_IDT77252_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_IDT77252_RCV_ALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_IDT77252_USE_SUNI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ATM_LANAI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_LANE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_MPOA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_NICSTAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_NICSTAR_USE_IDT77105 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_NICSTAR_USE_SUNI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ATM_SOLOS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATM_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ATOMIC64_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_AT_XDMAC policy<{'arm64': 'm'}> +CONFIG_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AUDITSYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AUDIT_ARCH policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_AUDIT_ARCH_COMPAT_GENERIC policy<{'arm64': 'y'}> +CONFIG_AUDIT_COMPAT_GENERIC policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_AUDIT_GENERIC policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_AUTOFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'y'}> +CONFIG_AUTO_ZRELADDR policy<{'armhf': 'y'}> +CONFIG_AUXDISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_AUXILIARY_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_AW96103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AX25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AX25_DAMA_SLAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_AX45MP_L2_CACHE policy<{'riscv64': 'n'}> +CONFIG_AX88796 policy<{'armhf': 'm'}> +CONFIG_AX88796B_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_AX88796B_RUST_PHY policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_AX88796_93CX6 policy<{'armhf': 'n'}> +CONFIG_AXI_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_AXP20X_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AXP20X_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AXP288_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_AXP288_CHARGER policy<{'amd64': 'm'}> +CONFIG_AXP288_FUEL_GAUGE policy<{'amd64': 'm'}> +CONFIG_AYANEO_EC policy<{'amd64': 'm'}> +CONFIG_B43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B43LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B43LEGACY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43LEGACY_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_DMA_AND_PIO_MODE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_DMA_MODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43LEGACY_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PCICORE_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PCI_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43LEGACY_PIO_MODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_BCMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_BCMA_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_BUSES_BCMA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_BUSES_BCMA_AND_SSB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_BUSES_SSB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PCICORE_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PCI_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_G policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_HT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_LP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PHY_N policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_PIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B43_SDIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_B43_SSB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B44 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_B44_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B44_PCICORE_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B44_PCI_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_B53 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_MDIO_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_MMAP_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_SERDES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_SPI_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_B53_SRAB_DRIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_AAT2870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_ADP8860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_ADP8870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_APPLE policy<{'amd64': 'm'}> +CONFIG_BACKLIGHT_APPLE_DWI policy<{'arm64': 'm'}> +CONFIG_BACKLIGHT_ARCXCNN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_AS3711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_AW99706 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_BD6107 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_CGBC policy<{'amd64': 'm'}> +CONFIG_BACKLIGHT_CLASS_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BACKLIGHT_DA903X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_KTD253 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_KTD2801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_KTZ8866 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_LED policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_LM3509 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_LM3630A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LM3639 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LP855X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_LV5207LP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_MAX8925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_MP3309C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_PANDORA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_QCOM_WLED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKLIGHT_RAVE_SP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_RT4831 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_SAHARA policy<{'amd64': 'm'}> +CONFIG_BACKLIGHT_SKY81452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_TPS65217 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_BACKLIGHT_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BACKTRACE_SELF_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BACKTRACE_VERBOSE policy<{'armhf': 'n'}> +CONFIG_BALLOON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BALLOON_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BARCO_P50_GPIO policy<{'amd64': 'm'}> +CONFIG_BAREUDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BASE_SMALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BASIC_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BATMAN_ADV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BATMAN_ADV_BATMAN_V policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATMAN_ADV_BLA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATMAN_ADV_DAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATMAN_ADV_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATMAN_ADV_MCAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATMAN_ADV_TRACING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATTERY_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_ACER_A500 policy<{'armhf': 'm'}> +CONFIG_BATTERY_ACT8945A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_BQ27XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BATTERY_BQ27XXX_HDQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_BQ27XXX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_CHAGALL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_CW2015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DA9030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DA9150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_DS2760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DS2780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DS2781 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_DS2782 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_GAUGE_LTC2941 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_GOLDFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_HUAWEI_GAOKUN policy<{'arm64': 'm'}> +CONFIG_BATTERY_INTEL_DC_TI policy<{'amd64': 'm'}> +CONFIG_BATTERY_LENOVO_YOGA_C630 policy<{'arm64-generic': 'm'}> +CONFIG_BATTERY_MAX17040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_MAX17042 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_MAX1720X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_MAX1721X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_OLPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BATTERY_PM8916_BMS_VM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BATTERY_QCOM_BATTMGR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_RX51 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_SAMSUNG_SDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BATTERY_SBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BATTERY_SURFACE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_BATTERY_TWL4030_MADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BATTERY_UG3105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BAYCOM_EPP policy<{'armhf': 'm'}> +CONFIG_BAYCOM_PAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BAYCOM_SER_FDX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BAYCOM_SER_HDX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BCACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCACHE_ASYNC_REGISTRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BCACHE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BCM54140_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM7XXX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM84881_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCM87XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCMA_BLOCKIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BCMA_DRIVER_GMAC_CMN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_DRIVER_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_DRIVER_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_HOST_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_HOST_PCI_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_HOST_SOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMA_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BCMA_SFLASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BCMGENET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BCM_KONA_USB2_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCM_NET_PHYLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM_NET_PHYPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BCM_SBA_RAID policy<{'arm64': 'm'}> +CONFIG_BCM_VK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BCM_VK_TTY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BD79703 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BD957XMUF_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BD96801_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BE2ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BE2NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BE2NET_BE2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_BE3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_LANCER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BE2NET_SKYHAWK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BEFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_BEFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BERLIN2_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BFQ_CGROUP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BFQ_GROUP_IOSCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BH1745 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BH1750 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BH1780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BHYVE_GUEST policy<{'amd64': 'y'}> +CONFIG_BIG_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BIG_LITTLE policy<{'armhf': 'y'}> +CONFIG_BINARY_PRINTF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BINDGEN_VERSION_TEXT policy<{'amd64': '"bindgen 0.72.1"', 'arm64': '"bindgen 0.72.1"'}> +CONFIG_BINFMT_ELF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BINFMT_ELF_FDPIC policy<{'armhf': 'y'}> +CONFIG_BINFMT_FLAT policy<{'armhf': 'y', 'riscv64': 'n'}> +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK policy<{'armhf': 'y'}> +CONFIG_BINFMT_FLAT_OLD policy<{'armhf': 'y'}> +CONFIG_BINFMT_MISC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BINFMT_ZFLAT policy<{'armhf': 'y'}> +CONFIG_BITREVERSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLKDEV_UBLK_LEGACY_OPCODES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BLK_CGROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_FC_APPID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_IOCOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_IOLATENCY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BLK_CGROUP_IOPRIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_PUNT_BIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_CGROUP_RWSTAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEBUG_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_3W_XXXX_RAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BLK_DEV_BSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_BSGLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_BSG_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_DM_BUILTIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_DRBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_FD policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_BLK_DEV_FD_RAWCMD policy<{'amd64': 'n', 'ppc64el': 'n'}> +CONFIG_BLK_DEV_INITRD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_INTEGRITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_IO_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_LOOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_LOOP_MIN_COUNT policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8', 's390x': '8'}> +CONFIG_BLK_DEV_MD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_NBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_NULL_BLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_PCIESSD_MTIP32XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BLK_DEV_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BLK_DEV_RAM_COUNT policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16', 's390x': '16'}> +CONFIG_BLK_DEV_RBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_RNBD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_RNBD_CLIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_RNBD_SERVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_DEV_RUST_NULL policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_BLK_DEV_UBLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_BLK_DEV_WRITE_MOUNTED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_ZONED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_DEV_ZONED_LOOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BLK_ICQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_INLINE_ENCRYPTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_MQ_STACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_PM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BLK_RQ_ALLOC_TIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_SED_OPAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_WBT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLK_WBT_MQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLOCK_HOLDER_DEPRECATED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BLOCK_LEGACY_AUTOLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BL_SWITCHER policy<{'armhf': 'y'}> +CONFIG_BL_SWITCHER_DUMMY_IF policy<{'armhf': 'm'}> +CONFIG_BMA220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA220_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA220_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA400_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMA400_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_ACCEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_ACCEL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_ACCEL_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_MAGN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_MAGN_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMC150_MAGN_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BME680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BME680_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BME680_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMG160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMG160_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMG160_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI088_ACCEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI088_ACCEL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI088_ACCEL_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI160_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI160_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI270 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI270_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI270_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI323_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMI323_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMP280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMP280_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BMP280_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BNA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BNX2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNX2X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNX2X_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_BNXT_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT_FLOWER_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BNXT_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BOARD_TPCI200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BONDING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BOOTPARAM_HUNG_TASK_PANIC policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_BOOTTIME_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BOOTX_TEXT policy<{'ppc64el': 'n'}> +CONFIG_BOOT_CONFIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BOOT_CONFIG_EMBED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BOOT_CONFIG_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BOOT_PRINTK_DELAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_BOOT_VESA_SUPPORT policy<{'amd64': 'y'}> +CONFIG_BOSCH_BNO055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BOSCH_BNO055_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BOSCH_BNO055_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_JIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_JIT_ALWAYS_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_JIT_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_KPROBE_OVERRIDE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_LSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_PRELOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BPF_STREAM_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPF_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BPQETHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BQL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRANCH_PROFILE_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRCMDBG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BRCMFMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BRCMFMAC_PCIE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_PROTO_BCDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_PROTO_MSGBUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_SDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMFMAC_USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMSMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BRCMSMAC_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRCMUTIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BRCM_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_CFM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRIDGE_EBT_802_3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_AMONG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_ARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_ARPREPLY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_BROUTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_DNAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_IP6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_LIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_MARK_T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_NFLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_PKTTYPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_REDIRECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_SNAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_STP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_T_FILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_T_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_EBT_VLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_IGMP_SNOOPING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRIDGE_MRP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BRIDGE_NETFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_NF_EBTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_NF_EBTABLES_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BRIDGE_VLAN_FILTERING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BROADCAST_TLB_FLUSH policy<{'amd64': 'y'}> +CONFIG_BROADCOM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BSD_DISKLABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_BSD_PROCESS_ACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BSD_PROCESS_ACCT_V3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BTREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BTRFS_ASSERT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTRFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTRFS_EXPERIMENTAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTRFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_BTRFS_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BTRFS_FS_RUN_SANITY_TESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BTT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_6LOWPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_AOSPEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_ATH3K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_BCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_BNEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_BNEP_MC_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_BNEP_PROTO_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_BREDR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBCM203X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBCM4377 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBFUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBLUECARD policy<{'amd64': 'm'}> +CONFIG_BT_HCIBPA10X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBT3C policy<{'amd64': 'm'}> +CONFIG_BT_HCIBTSDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBTUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIBTUSB_AUTOSUSPEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_BCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_MTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_POLL_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIBTUSB_RTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIDTL1 policy<{'amd64': 'm'}> +CONFIG_BT_HCIRSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIUART_3WIRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_AG6XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_AML policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_ATH3K policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_BCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_BCSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_H4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_INTEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_LL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_MRVL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_NOKIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HCIUART_QCA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_RTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIUART_SERDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_HCIVHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_HIDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_INTEL_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_LE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_LE_L2CAP_ECRED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_MRVL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MRVL_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MSFTEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_MTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MTKSDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_MTKUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_NXPUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_QCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_QCOMSMD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_BT_RFCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_RFCOMM_TTY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_BT_RTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BT_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_BT_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_BUFFER_HEAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUG_ON_DATA_CORRUPTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_BUILDTIME_MCOUNT_SORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_BUILDTIME_TABLE_SORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUILD_SALT policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_BUILTIN_MODULE_RANGES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC policy<{'arm64': 'y'}> +CONFIG_BXT_WC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_BYTCRC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_C2PORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_C2PORT_DURAMAR_2150 policy<{'amd64': 'm'}> +CONFIG_CACHEFILES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CACHEFILES_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CACHEFILES_ERROR_INJECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CACHEFILES_ONDEMAND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CACHEMAINT_FOR_DMA policy<{'riscv64': 'y'}> +CONFIG_CACHEMAINT_FOR_HOTPLUG policy<{'arm64': 'y'}> +CONFIG_CACHESTAT_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CACHE_FEROCEON_L2 policy<{'armhf': 'y'}> +CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH policy<{'armhf': 'n'}> +CONFIG_CACHE_L2X0 policy<{'armhf': 'y'}> +CONFIG_CACHE_L2X0_PMU policy<{'armhf': 'y'}> +CONFIG_CACHE_TAUROS2 policy<{'armhf': 'y'}> +CONFIG_CADENCE_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CAIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CAIF_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CAIF_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAIF_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAIF_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAIF_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAIF_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CALL_PADDING policy<{'amd64': 'y'}> +CONFIG_CALL_THUNKS policy<{'amd64': 'y'}> +CONFIG_CALL_THUNKS_DEBUG policy<{'amd64': 'n'}> +CONFIG_CAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CAN_8DEV_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_BCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_BXCAN policy<{'arm64': 'm'}> +CONFIG_CAN_CALC_BITTIMING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_CAN327 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CC770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CC770_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CC770_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CTUCANFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CTUCANFD_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_CTUCANFD_PLATFORM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_C_CAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_C_CAN_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_C_CAN_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_DEBUG_DEVICES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CAN_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_EMS_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_EMS_PCMCIA policy<{'amd64': 'm'}> +CONFIG_CAN_EMS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ESD_402_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ESD_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ETAS_ES58X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_F81601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_F81604 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_FLEXCAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_GRCAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_GS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_GW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_HI311X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_IFI_CANFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_ISOTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_J1939 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_JANZ_ICAN3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_KVASER_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_KVASER_PCIEFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_KVASER_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCBA_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCP251X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCP251XFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_MCP251XFD_SANITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CAN_MSCAN policy<{'ppc64el': 'm'}> +CONFIG_CAN_M_CAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_M_CAN_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_M_CAN_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_M_CAN_TCAN4X5X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_PEAK_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_PEAK_PCIEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_PEAK_PCIEFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_PEAK_PCMCIA policy<{'amd64': 'm'}> +CONFIG_CAN_PEAK_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_PLX_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CAN_RCAR_CANFD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CAN_ROCKCHIP_CANFD policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_CAN_RX_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CAN_SJA1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SJA1000_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SJA1000_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SLCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SOFTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_SOFTING_CS policy<{'amd64': 'm'}> +CONFIG_CAN_TI_HECC policy<{'armhf': 'm'}> +CONFIG_CAN_UCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_VCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_VXCAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CAN_XILINXCAN policy<{'arm64': 'm'}> +CONFIG_CARDBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_CARL9170 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CARL9170_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CARL9170_HWRNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CARL9170_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CARL9170_WPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CARMINE_DRAM_CUSTOM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CASSINI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CAVIUM_CPT policy<{'arm64': 'm'}> +CONFIG_CAVIUM_ERRATUM_22375 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_23144 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_23154 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_27456 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_ERRATUM_30115 policy<{'arm64': 'y'}> +CONFIG_CAVIUM_PTP policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CAVIUM_TX2_ERRATUM_219 policy<{'arm64': 'y'}> +CONFIG_CB710_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CB710_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CB710_DEBUG_ASSUMPTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CC10001_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CCS811 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CCW policy<{'s390x': 'y'}> +CONFIG_CCWGROUP policy<{'s390x': 'm'}> +CONFIG_CCW_CONSOLE policy<{'s390x': 'y'}> +CONFIG_CC_CAN_LINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASM_AOR_FORMAT_FLAGS policy<{'s390x': 'y'}> +CONFIG_CC_HAS_ASM_GOTO_OUTPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASM_IMMEDIATE_STRINGS policy<{'s390x': 'y'}> +CONFIG_CC_HAS_ASM_INLINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ASSUME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET policy<{'arm64': 'y'}> +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI policy<{'arm64': 'y'}> +CONFIG_CC_HAS_COUNTED_BY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ELFV2 policy<{'ppc64el': 'y'}> +CONFIG_CC_HAS_ENTRY_PADDING policy<{'amd64': 'y'}> +CONFIG_CC_HAS_IBT policy<{'amd64': 'y'}> +CONFIG_CC_HAS_INT128 policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_KASAN_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_KASAN_SW_TAGS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CC_HAS_MARCH_NATIVE policy<{'amd64': 'y'}> +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_NAMED_AS policy<{'amd64': 'y'}> +CONFIG_CC_HAS_NAMED_AS_FIXED_SANITIZERS policy<{'amd64': 'y'}> +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_PCREL policy<{'ppc64el': 'y'}> +CONFIG_CC_HAS_PREFIXED policy<{'ppc64el': 'y'}> +CONFIG_CC_HAS_RETURN_THUNK policy<{'amd64': 'y'}> +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_SLS policy<{'amd64': 'y'}> +CONFIG_CC_HAS_UBSAN_BOUNDS_STRICT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAS_ZERO_CALL_USED_REGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_HAVE_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG policy<{'arm64': 'y'}> +CONFIG_CC_HAVE_STACKPROTECTOR_TLS policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CC_IMPLICIT_FALLTHROUGH policy<{'amd64': '"-Wimplicit-fallthrough=5"', 'arm64': '"-Wimplicit-fallthrough=5"', 'armhf': '"-Wimplicit-fallthrough=5"', 'ppc64el': '"-Wimplicit-fallthrough=5"', 'riscv64': '"-Wimplicit-fallthrough=5"', 's390x': '"-Wimplicit-fallthrough=5"'}> +CONFIG_CC_IS_GCC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_NO_ARRAY_BOUNDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_NO_STRINGOP_OVERFLOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CC_OPTIMIZE_FOR_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CC_VERSION_TEXT policy<{'amd64': '"x86_64-linux-gnu-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'arm64': '"aarch64-linux-gnu-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'armhf': '"arm-linux-gnueabihf-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'ppc64el': '"powerpc64le-linux-gnu-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 'riscv64': '"riscv64-linux-gnu-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"', 's390x': '"s390x-linux-gnu-gcc (Ubuntu 15.2.0-16ubuntu1) 15.2.0"'}> +CONFIG_CDNS_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CDROM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CDX_BUS policy<{'arm64': 'y'}> +CONFIG_CDX_CONTROLLER policy<{'arm64': 'm'}> +CONFIG_CEC_CH7322 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CEC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CEC_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEC_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CEC_MESON_AO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEC_MESON_G12A_AO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEC_NOTIFIER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CEC_NXP_TDA9950 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CEC_PIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CEC_PIN_ERROR_INJ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CEC_SAMSUNG_S5P policy<{'armhf': 'n'}> +CONFIG_CEC_SECO policy<{'amd64': 'm'}> +CONFIG_CEC_SECO_RC policy<{'amd64': 'y'}> +CONFIG_CEC_STM32 policy<{'arm64': 'm'}> +CONFIG_CEC_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CEPH_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CEPH_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CEPH_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CEPH_FS_SECURITY_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CEPH_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CEPH_LIB_PRETTYDEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CEPH_LIB_USE_DNS_RESOLVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CERT_STORE policy<{'s390x': 'y'}> +CONFIG_CFAG12864B policy<{'amd64': 'm'}> +CONFIG_CFAG12864B_RATE policy<{'amd64': '20'}> +CONFIG_CFG80211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CFG80211_CERTIFICATION_ONUS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CFG80211_CRDA_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_DEFAULT_PS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_DEVELOPER_WARNINGS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFG80211_WEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CFS_BANDWIDTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGBC_WDT policy<{'amd64': 'm'}> +CONFIG_CGROUPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_CPUACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CGROUP_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_DMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_FAVOR_DYNMODS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CGROUP_FREEZER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_HUGETLB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_MISC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_NET_CLASSID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_NET_PRIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_PERF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_PIDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_RDMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CGROUP_WRITEBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CHARGER_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_ADP5061 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_BD99954 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ2415X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ24190 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ24257 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ24735 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ2515X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ256XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ257XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_BQ25890 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_BQ25980 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_CPCAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_CROS_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_CHARGER_CROS_PCHG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_CROS_USBPD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_DA9150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_DETECTOR_MAX14656 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_ISP1704 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_LP8727 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_LT3651 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_LTC4162L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MANAGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHARGER_MAX14577 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX77693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX77976 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX8903 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_MAX8971 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MAX8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MP2629 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_PF1550 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_PM8916_LBC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_QCOM_SMB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_QCOM_SMBB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHARGER_RK817 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_RT9455 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_RT9467 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_CHARGER_RT9471 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_RT9756 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_SBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_SC2731 policy<{'arm64': 'm'}> +CONFIG_CHARGER_SMB347 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_SURFACE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHARGER_TPS65090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHARGER_TPS65217 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_CHARGER_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_TWL6030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_UCS1002 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARGER_WILCO policy<{'amd64': 'm'}> +CONFIG_CHARLCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHARLCD_BL_FLASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHARLCD_BL_OFF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CHARLCD_BL_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CHECKPOINT_RESTORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CHECK_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_INLINE_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_IPSEC_INLINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHELSIO_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHELSIO_T1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T1_1G policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_T3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T4VF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CHELSIO_T4_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_T4_FCOE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CHELSIO_TLS_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CHROMEOS_ACPI policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHROMEOS_LAPTOP policy<{'amd64': 'm'}> +CONFIG_CHROMEOS_OF_HW_PROBER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CHROMEOS_PRIVACY_SCREEN policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHROMEOS_PSTORE policy<{'amd64': 'm'}> +CONFIG_CHROMEOS_TBMC policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CHROME_PLATFORMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_CHR_DEV_SCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CHR_DEV_ST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CHSC_SCH policy<{'s390x': 'm'}> +CONFIG_CHTCRC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_CHT_DC_TI_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_CHT_WC_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_CICADA_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CIFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CIFS_ALLOW_INSECURE_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_COMPRESSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_DEBUG2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_DEBUG_DUMP_KEYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_DFS_UPCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_POSIX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_SMB_DIRECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_STATS2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CIFS_SWN_UPCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_UPCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIFS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CIO_DAC policy<{'amd64': 'm'}> +CONFIG_CIO_INJECT policy<{'s390x': 'n'}> +CONFIG_CIX_MBOX policy<{'arm64': 'm'}> +CONFIG_CLANG_VERSION policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_CLKBLD_I8253 policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_CLKEVT_I8253 policy<{'amd64': 'y'}> +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK policy<{'armhf': 'y'}> +CONFIG_CLKSRC_EXYNOS_MCT policy<{'armhf': 'y'}> +CONFIG_CLKSRC_IMX_GPT policy<{'armhf': 'y'}> +CONFIG_CLKSRC_IMX_TPM policy<{'armhf': 'y'}> +CONFIG_CLKSRC_MMIO policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_CLKSRC_QCOM policy<{'armhf': 'y'}> +CONFIG_CLKSRC_STM32_LP policy<{'arm64': 'y'}> +CONFIG_CLKSRC_TI_32K policy<{'armhf': 'y'}> +CONFIG_CLKSRC_VERSATILE policy<{'armhf': 'y'}> +CONFIG_CLK_ACTIONS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_EMEV2 policy<{'armhf': 'y'}> +CONFIG_CLK_GFM_LPASS_SM8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_CLK_GLYMUR_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_GLYMUR_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_ICST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX5 policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6Q policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6SL policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6SLL policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6SX policy<{'armhf': 'y'}> +CONFIG_CLK_IMX6UL policy<{'armhf': 'y'}> +CONFIG_CLK_IMX7D policy<{'armhf': 'y'}> +CONFIG_CLK_IMX7ULP policy<{'armhf': 'y'}> +CONFIG_CLK_IMX8MM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8MN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8MP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8MQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_IMX8QXP policy<{'arm64': 'y'}> +CONFIG_CLK_IMX8ULP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CLK_IMX93 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CLK_IMX95_BLK_CTL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CLK_INTEL_SOCFPGA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_INTEL_SOCFPGA32 policy<{'armhf': 'y'}> +CONFIG_CLK_INTEL_SOCFPGA64 policy<{'arm64': 'y'}> +CONFIG_CLK_KAANAPALI_CAMCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_KAANAPALI_VIDEOCC policy<{'arm64': 'm'}> +CONFIG_CLK_LS1028A_PLLDIG policy<{'arm64': 'm'}> +CONFIG_CLK_MA35D1 policy<{'arm64': 'y'}> +CONFIG_CLK_OWL_S500 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_OWL_S700 policy<{'arm64': 'y'}> +CONFIG_CLK_OWL_S900 policy<{'arm64': 'y'}> +CONFIG_CLK_PX30 policy<{'arm64': 'y'}> +CONFIG_CLK_QCM2290_GPUCC policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'n'}> +CONFIG_CLK_QORIQ policy<{'arm64': 'y'}> +CONFIG_CLK_R7S9210 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7740 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7742 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7743 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7745 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A77470 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A7778 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7779 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7790 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7791 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7792 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7794 policy<{'armhf': 'y'}> +CONFIG_CLK_R8A7795 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77960 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77961 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77965 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77970 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77980 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77990 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A77995 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_CLK_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A06G032 policy<{'armhf': 'y'}> +CONFIG_CLK_R9A07G043 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A07G044 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A07G054 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G011 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G047 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G077 policy<{'arm64': 'y'}> +CONFIG_CLK_R9A09G087 policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_CPG_LIB policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_GEN2_CPG policy<{'armhf': 'y'}> +CONFIG_CLK_RCAR_GEN3_CPG policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_GEN4_CPG policy<{'arm64': 'y'}> +CONFIG_CLK_RCAR_USB2_CLOCK_SEL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS_CPG_MSSR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS_CPG_MSTP policy<{'armhf': 'y'}> +CONFIG_CLK_RENESAS_DIV6 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_RENESAS_VBATTB policy<{'arm64': 'm'}> +CONFIG_CLK_RK3036 policy<{'armhf': 'y'}> +CONFIG_CLK_RK312X policy<{'armhf': 'y'}> +CONFIG_CLK_RK3188 policy<{'armhf': 'y'}> +CONFIG_CLK_RK322X policy<{'armhf': 'y'}> +CONFIG_CLK_RK3288 policy<{'armhf': 'y'}> +CONFIG_CLK_RK3308 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3328 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3368 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3399 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3506 policy<{'armhf': 'y'}> +CONFIG_CLK_RK3528 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3562 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3568 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_CLK_RK3576 policy<{'arm64': 'y'}> +CONFIG_CLK_RK3588 policy<{'arm64': 'y'}> +CONFIG_CLK_RV110X policy<{'armhf': 'y'}> +CONFIG_CLK_RV1126 policy<{'armhf': 'y'}> +CONFIG_CLK_RV1126B policy<{'arm64': 'y'}> +CONFIG_CLK_RZA1 policy<{'armhf': 'y'}> +CONFIG_CLK_RZG2L policy<{'arm64': 'y'}> +CONFIG_CLK_RZV2H policy<{'arm64': 'y'}> +CONFIG_CLK_SH73A0 policy<{'armhf': 'y'}> +CONFIG_CLK_SOPHGO_CV1800 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_CLKGEN policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_PLL policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2042_RPGATE policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2044 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SOPHGO_SG2044_PLL policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CLK_SP810 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_CLK_TEGRA_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_TWL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CLK_TWL6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CLK_VEXPRESS_OSC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CLK_VF610 policy<{'armhf': 'y'}> +CONFIG_CLK_X1E80100_CAMCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_DISPCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_GCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1E80100_TCSRCC policy<{'arm64': 'm'}> +CONFIG_CLK_X1P42100_GPUCC policy<{'arm64': 'm'}> +CONFIG_CLOCKSOURCE_WATCHDOG policy<{'amd64': 'y'}> +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US policy<{'amd64': '100'}> +CONFIG_CLONE_BACKWARDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CLONE_BACKWARDS2 policy<{'s390x': 'y'}> +CONFIG_CLOSURES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CLS_U32_MARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CLS_U32_PERF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CLZ_TAB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CM32181 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM3232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM3323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM3605 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CM36651 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CMA_ALIGNMENT policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'riscv64': '8'}> +CONFIG_CMA_AREAS policy<{'amd64': '20', 'arm64': '7', 'armhf': '7', 'ppc64el': '7', 'riscv64': '7', 's390x': '7'}> +CONFIG_CMA_DEBUGFS policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CMA_SIZE_SEL_MAX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CMA_SIZE_SEL_MBYTES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CMA_SIZE_SEL_MIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CMA_SIZE_SEL_PERCENTAGE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CMA_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CMDLINE policy<{'arm64': '"console=ttyAMA0"', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""'}> +CONFIG_CMDLINE_BOOL policy<{'amd64': 'n'}> +CONFIG_CMDLINE_FORCE policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_CMDLINE_FROM_BOOTLOADER policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_CMDLINE_LOG_WRAP_IDEAL_LEN policy<{'amd64': '1021', 'arm64': '1021', 'armhf': '1021', 'ppc64el': '1021', 'riscv64': '1021', 's390x': '1021'}> +CONFIG_CMDLINE_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_CMM policy<{'ppc64el': 'm', 's390x': 'y'}> +CONFIG_CMM_IUCV policy<{'s390x': 'y'}> +CONFIG_CMODEL_MEDANY policy<{'riscv64': 'y'}> +CONFIG_CMODEL_MEDLOW policy<{'riscv64': 'n'}> +CONFIG_CNIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CODA_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CODE_PATCHING_SELFTEST policy<{'ppc64el': 'n'}> +CONFIG_COMEDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_COMEDI_8254 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_8255 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_8255_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_8255_SA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1516 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_1564 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_16XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_2032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_2200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_APCI_3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADDI_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI6208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI7250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI7X3X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI8164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI9111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADL_PCI9118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADQ12B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1710 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1723 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI1760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ADV_PCI_DIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AIO_AIO12_8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AIO_IIRO_16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_DIO200_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC236_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC263_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PC263_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PCI224 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_AMPLC_PCI230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_BOND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_C6XDIGIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_DAS16_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_CB_PCIDAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIDAS64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIDDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIMDAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CB_PCIMDDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_CONTEC_PCI_DIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAC02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAQBOARD2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS08_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_DAS08_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS08_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS16M1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS1800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS6402 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DAS800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB policy<{'amd64': '20480', 'arm64': '20480', 'armhf': '20480', 'ppc64el': '20480', 'riscv64': '20480'}> +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB policy<{'amd64': '2048', 'arm64': '2048', 'armhf': '2048', 'ppc64el': '2048', 'riscv64': '2048'}> +CONFIG_COMEDI_DMM32AT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2811 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2814 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2815 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT2817 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT282X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DT9812 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_DYNA_PCI10XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_FL512 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_GSC_HPDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ICP_MULTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_II_PCI20KC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ISADMA policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_COMEDI_ISA_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_COMEDI_JR3_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_KCOMEDILIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_KE_COUNTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ME4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_ME_DAQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MF6X4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MISC_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_COMEDI_MITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MPC624 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_MULTIQ3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_6527 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_65XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_660X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_670X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_ATMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_ATMIO16D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_AT_A2150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_AT_AO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_DAQ_700_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_DAQ_DIO24_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_LABPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_LABPC_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_LABPC_ISA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_LABPC_ISADMA policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_COMEDI_NI_LABPC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_MIO_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_NI_PCIDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_PCIMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_ROUTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_TIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_TIOCMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_NI_USB6501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCI_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL726 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL812 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL816 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCL818 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCM3724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMCIA_DRIVERS policy<{'amd64': 'm'}> +CONFIG_COMEDI_PCMDA12 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_PCMUIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_QUATECH_DAQP_CS policy<{'amd64': 'm'}> +CONFIG_COMEDI_RTD520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_RTI800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_RTI802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_S526 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_S626 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TESTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TESTS_EXAMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_TESTS_NI_ROUTES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USBDUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USBDUXFAST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USBDUXSIGMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_USB_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMEDI_VMK80XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMAND_LINE_SIZE policy<{'s390x': '4096'}> +CONFIG_COMMON_CLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_COMMON_CLK_A1_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_A1_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_APPLE_NCO policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_ASPEED policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_AST2700 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_AXG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_AXG_AUDIO policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_COMMON_CLK_AXI_CLKGEN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_BD718XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_BM1880 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_C3_PERIPHERALS policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'y'}> +CONFIG_COMMON_CLK_C3_PLL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_CDCE706 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_CDCE925 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_CS2000_CP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_EN7523 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_FIXED_MMIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_COMMON_CLK_FSL_FLEXSPI policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_FSL_SAI policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_G12A policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_GXBB policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_HI3516CV300 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_HI3519 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_HI3559A policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI3660 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI3670 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI3798CV200 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_HI6220 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_HI655X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_LAN966X policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_MAX77686 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_MAX9485 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_MEDIATEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MEDIATEK_FHCTL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON8B policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_AO_CLKC policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_CLKC_UTILS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_CPU_DYNDIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_DUALDIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_MPLL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_PHASE policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MESON_PLL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_REGMAP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MESON_SCLK_DIV policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MESON_VCLK policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MESON_VID_PLL_DIV policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MMP2 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MMP2_AUDIO policy<{'armhf': 'm'}> +CONFIG_COMMON_CLK_MT2701 policy<{'armhf': 'n'}> +CONFIG_COMMON_CLK_MT2712 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_BDPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_JPGDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT2712_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6735 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_IMGSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_MFGCFG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_VDECSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6735_VENCSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6765 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_AUDIOSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_GCESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MFGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI0ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI0BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI1ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI1BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI2ASYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MIPI2BSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6765_VCODECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_IPESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6779_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6795 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_MFGCFG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_MMSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_VDECSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6795_VENCSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT6797 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT6797_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT7622 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7622_AUDSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7622_ETHSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7622_HIFSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7629 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7629_ETHSYS policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7629_HIFSYS policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7981 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7981_ETHSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT7986 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7986_ETHSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT7988 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8135 policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_MT8167 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8167_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8173 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_COMMON_CLK_MT8173_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8173_MMSYS policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_COMMON_CLK_MT8173_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8173_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8183 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_AUDIOSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_ADL policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CONN policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE0 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_IPU_CORE1 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8183_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8186 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8186_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MCUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MDPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8186_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_ADSP_AUDIO26M policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VDOSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_VPPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8188_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8192 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_AUDSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_CAMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IMGSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_IPESYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MDPSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MFGCFG policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MMSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_MSDC policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_SCP_ADSP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_VDECSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8192_VENCSYS policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8195 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_MT8195_APUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_CAMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IMGSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_IPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_SCP_ADSP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VDOSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_VPPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8195_WPESYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196 policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MCUSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MDPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MFGCFG policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_MMSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_PEXTPSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_UFSSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_VDECSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8196_VENCSYS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_MT8365 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_APU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_CAM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_MFG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_MMSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_VDEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8365_VENC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_MT8516 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_MT8516_AUDSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_NPCM8XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_NUVOTON policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_PXA1908 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_RK808 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_COMMON_CLK_RP1 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_COMMON_CLK_RPMI policy<{'riscv64': 'm'}> +CONFIG_COMMON_CLK_RS9_PCIE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_S2MPS11 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_S4_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_S4_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_SAMSUNG policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_SCMI policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_COMMON_CLK_SCPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_CLK_SI514 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_SI521XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_SI5341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_SI5351 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_SI544 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_SI570 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_SP7021 policy<{'armhf': 'm'}> +CONFIG_COMMON_CLK_STM32MP policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_STM32MP215 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_STM32MP257 policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_T7_PERIPHERALS policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_T7_PLL policy<{'arm64': 'm'}> +CONFIG_COMMON_CLK_TI_ADPLL policy<{'armhf': 'y'}> +CONFIG_COMMON_CLK_TPS68470 policy<{'amd64': 'm'}> +CONFIG_COMMON_CLK_VC3 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_VC5 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_VC7 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_COMMON_CLK_VISCONTI policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_COMMON_CLK_XGENE policy<{'arm64': 'y'}> +CONFIG_COMMON_CLK_XLNX_CLKWZRD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_COMMON_CLK_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_COMMON_RESET_HI3660 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMMON_RESET_HI6220 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_COMPACTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_COMPACT_UNEVICTABLE_DEFAULT policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1', 's390x': '1'}> +CONFIG_COMPAL_LAPTOP policy<{'amd64': 'm'}> +CONFIG_COMPAT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_COMPAT_32 policy<{'amd64': 'y'}> +CONFIG_COMPAT_32BIT_TIME policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_COMPAT_ALIGNMENT_FIXUPS policy<{'arm64': 'n', 'arm64-generic-64k': '-'}> +CONFIG_COMPAT_BINFMT_ELF policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_COMPAT_FOR_U64_ALIGNMENT policy<{'amd64': 'y'}> +CONFIG_COMPAT_NETLINK_MESSAGES policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-'}> +CONFIG_COMPAT_OLD_SIGACTION policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_COMPAT_VDSO policy<{'amd64': 'n'}> +CONFIG_COMPILE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_COMPRESSED_INSTALL policy<{'arm64': 'n'}> +CONFIG_CONFIGFS_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONNECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONSOLE_LOGLEVEL_DEFAULT policy<{'amd64': '7', 'arm64': '7', 'armhf': '7', 'ppc64el': '7', 'riscv64': '7', 's390x': '7'}> +CONFIG_CONSOLE_POLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CONSOLE_TRANSLATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_ANALYSIS_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CONTEXT_SWITCH_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_TRACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_TRACKING_IDLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CONTEXT_TRACKING_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CONTEXT_TRACKING_USER_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CONTIG_ALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CORDIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CORESIGHT policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CORTINA_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_COUNTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CPA_DEBUG policy<{'amd64': 'n'}> +CONFIG_CPCAP_ADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CPM_TSA policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n'}> +CONFIG_CPUFREQ_ARCH_CUR_FREQ policy<{'amd64': 'y'}> +CONFIG_CPUFREQ_DT_PLATDEV policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPUFREQ_DT_RUST policy<{'arm64': 'm'}> +CONFIG_CPUFREQ_VIRT policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_CPUMASK_OFFSTACK policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CPUSETS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPUSETS_V1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CPU_32v6K policy<{'armhf': 'y'}> +CONFIG_CPU_32v7 policy<{'armhf': 'y'}> +CONFIG_CPU_ABRT_EV7 policy<{'armhf': 'y'}> +CONFIG_CPU_BIG_ENDIAN policy<{'arm64': '-', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'y'}> +CONFIG_CPU_BPREDICT_DISABLE policy<{'armhf': 'n'}> +CONFIG_CPU_CACHE_V7 policy<{'armhf': 'y'}> +CONFIG_CPU_CACHE_VIPT policy<{'armhf': 'y'}> +CONFIG_CPU_COPY_V6 policy<{'armhf': 'y'}> +CONFIG_CPU_CP15 policy<{'armhf': 'y'}> +CONFIG_CPU_CP15_MMU policy<{'armhf': 'y'}> +CONFIG_CPU_FREQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CPU_FREQ_GOV_ATTR_SET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_GOV_SCHEDUTIL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_FREQ_THERMAL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_HAS_ASID policy<{'armhf': 'y'}> +CONFIG_CPU_HOTPLUG_STATE_CONTROL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CPU_ICACHE_DISABLE policy<{'armhf': 'n'}> +CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND policy<{'armhf': 'y'}> +CONFIG_CPU_IDLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_GOV_HALTPOLL policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_CPU_IDLE_GOV_LADDER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_GOV_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_GOV_TEO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CPU_IDLE_THERMAL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_ISOLATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPU_LITTLE_ENDIAN policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_CPU_MITIGATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPU_PABRT_V7 policy<{'armhf': 'y'}> +CONFIG_CPU_PJ4 policy<{'armhf': 'y'}> +CONFIG_CPU_PJ4B policy<{'armhf': 'y'}> +CONFIG_CPU_PM policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CPU_RMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CPU_SPECTRE policy<{'armhf': 'y'}> +CONFIG_CPU_SUP_AMD policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_CENTAUR policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_HYGON policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_INTEL policy<{'amd64': 'y'}> +CONFIG_CPU_SUP_ZHAOXIN policy<{'amd64': 'y'}> +CONFIG_CPU_THERMAL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CPU_THUMB_CAPABLE policy<{'armhf': 'y'}> +CONFIG_CPU_TLB_V7 policy<{'armhf': 'y'}> +CONFIG_CPU_TTBR0_PAN policy<{'armhf': 'y'}> +CONFIG_CPU_V7 policy<{'armhf': 'y'}> +CONFIG_CRAMFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRAMFS_BLOCKDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CRAMFS_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CRASH_DM_CRYPT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRASH_DM_CRYPT_CONFIGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRASH_HOTPLUG policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_CRASH_MAX_MEMORY_RANGES policy<{'amd64': '8192', 'ppc64el': '8192'}> +CONFIG_CRASH_RESERVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC16 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC32 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC32_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC4 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CRC64 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC64_ARCH policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_CRC7 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_CRC8 policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRC_CCITT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC_ITU_T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRC_OPTIMIZATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC_T10DIF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRC_T10DIF_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CROSS_MEMORY_ATTACH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_CHARDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_DEBUGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_ISHTP policy<{'amd64': 'm'}> +CONFIG_CROS_EC_LIGHTBAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_LPC policy<{'amd64': 'm'}> +CONFIG_CROS_EC_MKBP_PROXIMITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_PROTO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_SENSORHUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_TYPEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_TYPEC_ALTMODES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_CROS_EC_UART policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CROS_EC_UCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_VBC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_EC_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_HPS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_KBD_LED_BACKLIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_TYPEC_SWITCH policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CROS_USBPD_LOGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CROS_USBPD_NOTIFY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_842 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ACOMP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ADIANTUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_AEAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AEAD2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AEGIS128 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_AEGIS128_SIMD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_AES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AES_ARM64_BS policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_CE_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_CE_CCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM64_NEON_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_AES_ARM_BS policy<{'armhf': 'm'}> +CONFIG_CRYPTO_AES_ARM_CE policy<{'armhf': 'm'}> +CONFIG_CRYPTO_AES_GCM_P10 policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_AES_NI_INTEL policy<{'amd64': 'm'}> +CONFIG_CRYPTO_AES_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_AKCIPHER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_AKCIPHER2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ALGAPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ALGAPI2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ARIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_ARIA_AESNI_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_ARIA_GFNI_AVX512_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_AUTHENC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BENCHMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLAKE2B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLOWFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLOWFISH_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_BLOWFISH_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAMELLIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAMELLIA_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAST5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CAST5_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAST6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CAST6_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_CAST_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CBC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_CCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CHACHA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CHACHA20POLY1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CRC32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CRC32C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_CRYPTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_CTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_CTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_DES3_EDE_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DES_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_DEV_ALLWINNER policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_AMLOGIC_GXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_ARTPEC6 policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ASPEED policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ASPEED_ACRY policy<{'armhf': 'y'}> +CONFIG_CRYPTO_DEV_ASPEED_DEBUG policy<{'armhf': 'n'}> +CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO policy<{'armhf': 'y'}> +CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH policy<{'armhf': 'y'}> +CONFIG_CRYPTO_DEV_ATMEL_AES policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ATMEL_ECC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_ATMEL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_ATMEL_SHA204A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_CCP policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CRYPTO_DEV_CCP_CRYPTO policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CCP_DD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_CRYPTO_DEV_CCP_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_CRYPTO_DEV_CCREE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_CHELSIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_EIP93 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_EXYNOS_RNG policy<{'armhf': 'n'}> +CONFIG_CRYPTO_DEV_FSL_CAAM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD policy<{'arm64': '255', 'armhf': '255'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD policy<{'arm64': '2048', 'armhf': '2048'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_JR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE policy<{'arm64': '9', 'armhf': '9'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_HPRE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_QM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_SEC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_SEC2 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_TRNG policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_HISI_ZIP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_IAA_CRYPTO policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_IAA_CRYPTO_STATS policy<{'amd64': 'n'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 policy<{'arm64': 'y'}> +CONFIG_CRYPTO_DEV_MARVELL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_MARVELL_CESA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_MXS_DCP policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_NITROX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_NITROX_CNN55XX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_NX policy<{'ppc64el': 'y'}> +CONFIG_CRYPTO_DEV_NX_COMPRESS policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_NX_COMPRESS_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_NX_COMPRESS_PSERIES policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_OCTEONTX2_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_OCTEONTX_CPT policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_OMAP policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_OMAP_AES policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_OMAP_DES policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_OMAP_SHAM policy<{'armhf': 'm'}> +CONFIG_CRYPTO_DEV_PADLOCK policy<{'amd64': 'y'}> +CONFIG_CRYPTO_DEV_PADLOCK_AES policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_PADLOCK_SHA policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_QAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_420XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_4XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_6XXX policy<{'amd64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C3XXXVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C62X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_C62XVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_DH895xCC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CRYPTO_DEV_QCE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_QCE_AEAD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_CRYPTO_DEV_QCE_SHA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_SKCIPHER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN policy<{'arm64': '512', 'armhf': '512'}> +CONFIG_CRYPTO_DEV_QCOM_RNG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_DEV_S5P policy<{'armhf': 'n'}> +CONFIG_CRYPTO_DEV_SA2UL policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SAFEXCEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_DEV_SAHARA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_SP_CCP policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CRYPTO_DEV_SP_PSP policy<{'amd64': 'y'}> +CONFIG_CRYPTO_DEV_STM32_CRYP policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_STM32_HASH policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_SUN4I_SS policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_CRYPTO_DEV_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_CRYPTO_DEV_TI_DTHEV2 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_DEV_VMX policy<{'ppc64el': 'y'}> +CONFIG_CRYPTO_DEV_VMX_ENCRYPT policy<{'ppc64el': 'm'}> +CONFIG_CRYPTO_DEV_XILINX_TRNG policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ZYNQMP_AES policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 policy<{'arm64': 'm'}> +CONFIG_CRYPTO_DF80090A policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DH_RFC7919_GROUPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_CTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_HMAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_DRBG_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECDH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_ECDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ECHAINIV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ECRDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ENGINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ESSIV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_FCRYPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_GCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_GENIV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_GHASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_GHASH_ARM64_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_GHASH_ARM_CE policy<{'armhf': 'm'}> +CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL policy<{'amd64': 'm'}> +CONFIG_CRYPTO_GHASH_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HASH2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HASH_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HCTR2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_HKDF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_HMAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_HW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_JITTERENTROPY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64', 's390x': '64'}> +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32', 's390x': '32'}> +CONFIG_CRYPTO_JITTERENTROPY_OSR policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1', 's390x': '1'}> +CONFIG_CRYPTO_KDF800108_CTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_KPP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_KPP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_KRB5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_KRB5ENC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_KRB5_SELFTESTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_AES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_AESGCM policy<{'amd64': 'y'}> +CONFIG_CRYPTO_LIB_AES_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_ARC4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_BLAKE2B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_BLAKE2B_ARCH policy<{'armhf': 'y'}> +CONFIG_CRYPTO_LIB_BLAKE2S_ARCH policy<{'amd64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_LIB_CHACHA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_CHACHA20POLY1305 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_CHACHA_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_CURVE25519 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_CURVE25519_ARCH policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_DES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_GF128MUL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_MD5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_MD5_ARCH policy<{'ppc64el': 'y'}> +CONFIG_CRYPTO_LIB_MLDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_NH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LIB_NH_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_POLY1305_RSIZE policy<{'amd64': '11', 'arm64': '9', 'armhf': '9', 'ppc64el': '1', 'riscv64': '2', 's390x': '1'}> +CONFIG_CRYPTO_LIB_POLYVAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_LIB_POLYVAL_ARCH policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CRYPTO_LIB_SHA1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA1_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA256_ARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA3_ARCH policy<{'arm64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SHA512 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LIB_SM3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_LIB_UTILS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_LRW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LZ4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LZ4HC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MANAGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MANAGER2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MD4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_MD5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_MICHAEL_MIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_MLDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_NULL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_PAES_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_PCBC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_PCRYPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_PHMAC_S390 policy<{'s390x': 'm'}> +CONFIG_CRYPTO_RMD160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_RNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_RNG2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_RNG_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_RSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_SEQIV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SERPENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_SERPENT_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SERPENT_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SERPENT_SSE2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SHA1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SHA3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SIG2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SIMD policy<{'amd64': '-', 'armhf': '-', 'ppc64el': 'm'}> +CONFIG_CRYPTO_SKCIPHER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SKCIPHER2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_SM3_ARM64_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM3_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SM3_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_SM3_NEON policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_CCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_CE_GCM policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_ARM64_NEON_BLK policy<{'arm64': 'm'}> +CONFIG_CRYPTO_SM4_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CRYPTO_STREEBOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_TWOFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_TWOFISH_AVX_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_TWOFISH_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_TWOFISH_X86_64 policy<{'amd64': 'm'}> +CONFIG_CRYPTO_TWOFISH_X86_64_3WAY policy<{'amd64': 'm'}> +CONFIG_CRYPTO_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_AEAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_HASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_RNG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_USER_API_RNG_CAVP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CRYPTO_USER_API_SKCIPHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_WP512 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_XCBC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_XCTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CRYPTO_XTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_CRYPTO_XXHASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CRYPTO_ZSTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CS89x0 policy<{'armhf': 'm'}> +CONFIG_CS89x0_PLATFORM policy<{'armhf': 'm'}> +CONFIG_CSD_LOCK_WAIT_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_CTCM policy<{'s390x': 'm'}> +CONFIG_CURRENT_POINTER_IN_TPIDRURO policy<{'armhf': 'y'}> +CONFIG_CUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_CV1800_MBOX policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_CW1200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CW1200_WLAN_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CW1200_WLAN_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXD2880_SPI_DRV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_CXL_ATL policy<{'amd64': 'y'}> +CONFIG_CXL_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_CXL_EDAC_MEM_FEATURES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CXL_FEATURES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CXL_MCE policy<{'amd64': 'y'}> +CONFIG_CXL_MEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_MEM_RAW_COMMANDS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_CXL_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_PMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_PORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CXL_RAS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CXL_REGION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CXL_REGION_INVALIDATION_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_CXL_SUSPEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_CX_ECAT policy<{'amd64': 'm'}> +CONFIG_CYPRESS_FIRMWARE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_CZNIC_PLATFORMS policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_D3323AA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA9052_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DA9055_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DA9062_THERMAL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA9062_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DA9063_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DA9150_GPADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DAMON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DASD policy<{'s390x': 'm'}> +CONFIG_DASD_DIAG policy<{'s390x': 'm'}> +CONFIG_DASD_ECKD policy<{'s390x': 'm'}> +CONFIG_DASD_EER policy<{'s390x': 'y'}> +CONFIG_DASD_FBA policy<{'s390x': 'm'}> +CONFIG_DASD_PROFILE policy<{'s390x': 'y'}> +CONFIG_DASHARO_ACPI policy<{'amd64': 'm'}> +CONFIG_DATA_SHIFT policy<{'ppc64el': '24'}> +CONFIG_DAVICOM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DAX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DA_MON_EVENTS_ID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DCA policy<{'amd64': 'm'}> +CONFIG_DCACHE_WORD_ACCESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DCDBAS policy<{'amd64': 'm'}> +CONFIG_DCSSBLK policy<{'s390x': 'm'}> +CONFIG_DDR policy<{'armhf': 'y'}> +CONFIG_DE2104X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DE2104X_DSL policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_DEBUGGER policy<{'ppc64el': 'y'}> +CONFIG_DEBUG_ALIGN_RODATA policy<{'armhf': 'y'}> +CONFIG_DEBUG_ATOMIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_ATOMIC_SLEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_BOOT_PARAMS policy<{'amd64': 'n'}> +CONFIG_DEBUG_BUGVERBOSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_BUGVERBOSE_DETAILED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_CGROUP_REF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_CLOSURES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_DEVRES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_DRIVER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_EFI policy<{'arm64': 'n'}> +CONFIG_DEBUG_ENTRY policy<{'amd64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_FORCE_WEAK_PER_CPU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_FS_ALLOW_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_FS_ALLOW_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_GENERIC_PT policy<{'amd64': 'n'}> +CONFIG_DEBUG_GPIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_HIGHMEM policy<{'armhf': 'n'}> +CONFIG_DEBUG_INFO_BTF_MODULES policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_COMPRESSED_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_COMPRESSED_ZLIB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_COMPRESSED_ZSTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_DWARF4 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_DWARF5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_INFO_REDUCED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_IRQFLAGS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_KERNEL_DC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DEBUG_KMAP_LOCAL policy<{'armhf': 'n'}> +CONFIG_DEBUG_KMEMLEAK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_KOBJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_LIST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_LL policy<{'armhf': 'n'}> +CONFIG_DEBUG_LL_INCLUDE policy<{'armhf': '"mach/debug-macro.S"'}> +CONFIG_DEBUG_LOCKING_API_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_LOCK_ALLOC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_MAPLE_TREE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_MEMORY_INIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_MISC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEBUG_MUTEXES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_NET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_NET_SMALL_RTNL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_NMI_SELFTEST policy<{'amd64': 'n'}> +CONFIG_DEBUG_NOTIFIERS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_OBJECTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PAGEALLOC policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PAGE_REF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PERF_USE_VMALLOC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PER_CPU_MAPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PINCTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DEBUG_PLIST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_PREEMPT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_RODATA_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_RSEQ policy<{'amd64': '-', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': '-', 's390x': '-'}> +CONFIG_DEBUG_RT_MUTEXES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_RWSEMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SECTION_MISMATCH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SHIRQ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_SPINLOCK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_STACKOVERFLOW policy<{'ppc64el': 'n'}> +CONFIG_DEBUG_STACK_USAGE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_TEST_DRIVER_REMOVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_TLBFLUSH policy<{'amd64': 'n'}> +CONFIG_DEBUG_USER policy<{'armhf': 'n'}> +CONFIG_DEBUG_VFS policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_VF_UART_PORT policy<{'armhf': '1'}> +CONFIG_DEBUG_VIRTUAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_VM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_VM_PGTABLE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_WQ_FORCE_RR_CPU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_WW_MUTEX_SLOWPATH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEBUG_WX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_BZIP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_GZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_LZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DECOMPRESS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEFAULT_CUBIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEFAULT_HOSTNAME policy<{'amd64': '"(none)"', 'arm64': '"(none)"', 'armhf': '"(none)"', 'ppc64el': '"(none)"', 'riscv64': '"(none)"', 's390x': '"(none)"'}> +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT policy<{'amd64': '120', 'arm64': '120', 'armhf': '120', 'ppc64el': '120', 'riscv64': '120', 's390x': '120'}> +CONFIG_DEFAULT_INIT policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_DEFAULT_RENO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_APPARMOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEFAULT_SECURITY_DAC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_SELINUX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_SMACK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_SECURITY_TOMOYO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFAULT_TCP_CONG policy<{'amd64': '"cubic"', 'arm64': '"cubic"', 'armhf': '"cubic"', 'ppc64el': '"cubic"', 'riscv64': '"cubic"', 's390x': '"cubic"'}> +CONFIG_DEFERRED_STRUCT_PAGE_INIT policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DEFXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DELL_LAPTOP policy<{'amd64': 'm'}> +CONFIG_DELL_PC policy<{'amd64': 'm'}> +CONFIG_DELL_RBTN policy<{'amd64': 'm'}> +CONFIG_DELL_RBU policy<{'amd64': 'm'}> +CONFIG_DELL_SMBIOS policy<{'amd64': 'm'}> +CONFIG_DELL_SMBIOS_SMM policy<{'amd64': 'y'}> +CONFIG_DELL_SMBIOS_WMI policy<{'amd64': 'y'}> +CONFIG_DELL_SMO8800 policy<{'amd64': 'm'}> +CONFIG_DELL_UART_BACKLIGHT policy<{'amd64': 'm'}> +CONFIG_DELL_WMI policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_AIO policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_DDV policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_DESCRIPTOR policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_LED policy<{'amd64': 'm'}> +CONFIG_DELL_WMI_PRIVACY policy<{'amd64': 'y'}> +CONFIG_DELL_WMI_SYSMAN policy<{'amd64': 'm'}> +CONFIG_DEPRECATED_PARAM_STRUCT policy<{'armhf': 'n'}> +CONFIG_DETECT_HUNG_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DETECT_HUNG_TASK_BLOCKER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP policy<{'armhf': 'n'}> +CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU policy<{'armhf': 'n'}> +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DEVFREQ_GOV_PASSIVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_PERFORMANCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_POWERSAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_GOV_USERSPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVFREQ_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEVICE_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVICE_PRIVATE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEVPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_DEVTMPFS_SAFE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DEV_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DEV_DAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DEV_DAX_CXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DEV_DAX_HMEM policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_DEV_DAX_HMEM_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DEV_DAX_KMEM policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DEV_DAX_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DEV_SYNC_PROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DHT11 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DIAG288_WATCHDOG policy<{'s390x': 'm'}> +CONFIG_DIBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DIBS_LO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DIMLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DL2K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DLHL60D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DLM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DLM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DLN2_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DM9000 policy<{'armhf': 'm'}> +CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL policy<{'armhf': 'n'}> +CONFIG_DM9051 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DM9102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DMABUF_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMABUF_HEAPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMABUF_HEAPS_CMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMABUF_HEAPS_SYSTEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMABUF_MOVE_NOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DMABUF_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMADEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DMADEVICES_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DMAPOOL_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMARD06 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMARD09 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMARD10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMAR_TABLE policy<{'amd64': 'y'}> +CONFIG_DMATEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DMA_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_API_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_COHERENT_POOL policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_DECLARE_COHERENT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_DIRECT_REMAP policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_ENGINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_ENGINE_RAID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_DMA_FENCE_TRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMA_MAP_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DMA_NEED_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMA_NONCOHERENT_MMAP policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMA_NUMA_CMA policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_DMA_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_OMAP policy<{'armhf': 'y'}> +CONFIG_DMA_OPS_BYPASS policy<{'ppc64el': 'y'}> +CONFIG_DMA_OPS_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_DMA_RESTRICTED_POOL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DMA_SHARED_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DMA_SUN6I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DMA_VIRTUAL_CHANNELS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMIID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK policy<{'amd64': 'y'}> +CONFIG_DMI_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_DM_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_BIO_PRISON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_BUFIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CACHE_SMQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CLONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_CRYPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DM_DELAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_DUST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DM_EBS policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_ERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_FLAKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_INIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_INTEGRITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_LOG_USERSPACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_LOG_WRITES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MIRROR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_HST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_IOA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_QL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_MULTIPATH_ST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_PCACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DM_PERSISTENT_DATA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_RAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_SNAPSHOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_SWITCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_THIN_PROVISIONING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_UEVENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_UNSTRIPED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_VDO policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_VERITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_VERITY_FEC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DM_WRITECACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_ZERO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DM_ZONED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DNOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DNS_RESOLVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DOVE_CLK policy<{'armhf': 'y'}> +CONFIG_DOVE_THERMAL policy<{'armhf': 'm'}> +CONFIG_DP83640_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83822_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83848_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83867_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83869_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83TC811_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DP83TD510_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DP83TG720_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DPAA2_CONSOLE policy<{'arm64': 'm'}> +CONFIG_DPAA_ERRATUM_A050385 policy<{'arm64': 'y'}> +CONFIG_DPLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DPLL_REFCNT_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DPM_WATCHDOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DPOT_DAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DPS310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DPTF_PCH_FIVR policy<{'amd64': 'm'}> +CONFIG_DPTF_POWER policy<{'amd64': 'm'}> +CONFIG_DQL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRAGONRISE_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRBD_FAULT_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DRM_ACCEL_AMDXDNA policy<{'amd64': 'm'}> +CONFIG_DRM_ACCEL_ARM_ETHOSU policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_ACCEL_HABANALABS policy<{'amd64': 'm'}> +CONFIG_DRM_ACCEL_IVPU policy<{'amd64': 'm'}> +CONFIG_DRM_ACCEL_IVPU_DEBUG policy<{'amd64': 'n'}> +CONFIG_DRM_ACCEL_QAIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ACCEL_ROCKET policy<{'arm64': 'm'}> +CONFIG_DRM_ADP policy<{'arm64': 'm'}> +CONFIG_DRM_AMDGPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_AMDGPU_SI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMDGPU_USERPTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMDGPU_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_DRM_AMD_ACP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_DC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_DC_FP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_DC_SI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_AMD_ISP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_AMD_SECURE_DISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_ANALOGIX_ANX6345 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ANALOGIX_ANX7625 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ANALOGIX_ANX78XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_ANALOGIX_DP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_APPLETBDRM policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_ARCPGU policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ARMADA policy<{'armhf': 'm'}> +CONFIG_DRM_ASPEED_GFX policy<{'armhf': 'm'}> +CONFIG_DRM_AST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_ATMEL_HLCDC policy<{'armhf': 'm'}> +CONFIG_DRM_AUX_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_AUX_HPD_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_BOCHS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DRM_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_BRIDGE_CONNECTOR policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_BUDDY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CDNS_DSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CDNS_DSI_J721E policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_CDNS_MHDP8546 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CDNS_MHDP8546_J721E policy<{'arm64': 'y'}> +CONFIG_DRM_CHIPONE_ICN6211 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CHRONTEL_CH7033 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_CIRRUS_QEMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_CLIENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CLIENT_DEFAULT policy<{'amd64': '"fbdev"', 'arm64': '"fbdev"', 'armhf': '"fbdev"', 'ppc64el': '"fbdev"', 'riscv64': '"fbdev"', 's390x': '"fbdev"'}> +CONFIG_DRM_CLIENT_DEFAULT_FBDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CLIENT_DEFAULT_LOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_CLIENT_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_CLIENT_LOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CLIENT_SELECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_CLIENT_SETUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_CROS_EC_ANX7688 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_DEBUG_MM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_DEBUG_MODESET_LOCK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_DISPLAY_CONNECTOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_DISPLAY_DP_AUX_BUS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_DISPLAY_DP_AUX_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DP_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DP_TUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_DSC_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDCP_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_DISPLAY_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_DRAW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_DW_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DW_HDMI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_AHB_AUDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_CEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_GP_AUDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_I2S_AUDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_DW_HDMI_QP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DW_HDMI_QP_CEC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_DW_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_DW_MIPI_DSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_ETNAVIV policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_ETNAVIV_THERMAL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_EXEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_EXYNOS policy<{'armhf': 'm'}> +CONFIG_DRM_EXYNOS5433_DECON policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS7_DECON policy<{'armhf': 'n'}> +CONFIG_DRM_EXYNOS_DSI policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_FIMC policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_FIMD policy<{'armhf': 'n'}> +CONFIG_DRM_EXYNOS_G2D policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_GSC policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_HDMI policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_IPP policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_MIC policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_MIXER policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_ROTATOR policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_SCALER policy<{'armhf': 'y'}> +CONFIG_DRM_EXYNOS_VIDI policy<{'armhf': 'n'}> +CONFIG_DRM_FBDEV_EMULATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_FBDEV_OVERALLOC policy<{'amd64': '100', 'arm64': '100', 'armhf': '100', 'ppc64el': '100', 'riscv64': '100', 's390x': '100'}> +CONFIG_DRM_FSL_DCU policy<{'armhf': 'm'}> +CONFIG_DRM_FSL_LDB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_GEM_DMA_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_GEM_SHMEM_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_GM12U320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_GMA500 policy<{'amd64': 'm'}> +CONFIG_DRM_GPUSVM policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_DRM_GPUVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_GUD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_HDLCD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_HDLCD_SHOW_UNDERRUN policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_DRM_HISI_HIBMC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_HISI_KIRIN policy<{'arm64': 'm'}> +CONFIG_DRM_HYPERV policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_DRM_I2C_ADV7511 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_I2C_ADV7511_AUDIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_I2C_ADV7511_CEC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_I2C_NXP_TDA998X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_I915 policy<{'amd64': 'm'}> +CONFIG_DRM_I915_CAPTURE_ERROR policy<{'amd64': 'y'}> +CONFIG_DRM_I915_COMPRESS_ERROR policy<{'amd64': 'y'}> +CONFIG_DRM_I915_DEBUG policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_GUC policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_MMIO policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_RUNTIME_PM policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_VBLANK_EVADE policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DEBUG_WAKEREF policy<{'amd64': 'n'}> +CONFIG_DRM_I915_DP_TUNNEL policy<{'amd64': 'y'}> +CONFIG_DRM_I915_FENCE_TIMEOUT policy<{'amd64': '10000'}> +CONFIG_DRM_I915_FORCE_PROBE policy<{'amd64': '""'}> +CONFIG_DRM_I915_GVT policy<{'amd64': 'y'}> +CONFIG_DRM_I915_GVT_KVMGT policy<{'amd64': 'm'}> +CONFIG_DRM_I915_HEARTBEAT_INTERVAL policy<{'amd64': '2500'}> +CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS policy<{'amd64': 'n'}> +CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT policy<{'amd64': '8000'}> +CONFIG_DRM_I915_PREEMPT_TIMEOUT policy<{'amd64': '640'}> +CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE policy<{'amd64': '7500'}> +CONFIG_DRM_I915_PXP policy<{'amd64': 'y'}> +CONFIG_DRM_I915_REQUEST_TIMEOUT policy<{'amd64': '20000'}> +CONFIG_DRM_I915_SELFTEST policy<{'amd64': 'n'}> +CONFIG_DRM_I915_STOP_TIMEOUT policy<{'amd64': '100'}> +CONFIG_DRM_I915_SW_FENCE_CHECK_DAG policy<{'amd64': 'n'}> +CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS policy<{'amd64': 'n'}> +CONFIG_DRM_I915_TIMESLICE_DURATION policy<{'amd64': '1'}> +CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND policy<{'amd64': '250'}> +CONFIG_DRM_I915_USERPTR policy<{'amd64': 'y'}> +CONFIG_DRM_I915_WERROR policy<{'amd64': 'n'}> +CONFIG_DRM_IMX policy<{'armhf': 'm'}> +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8MP_HDMI_PAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8MP_HDMI_PVI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QM_LDB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_LDB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_COMBINER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX8_DC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX93_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX_DCSS policy<{'arm64': 'm'}> +CONFIG_DRM_IMX_HDMI policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_LCDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX_LCDIF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_IMX_LDB policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_LDB_HELPER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_IMX_LEGACY_BRIDGE policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_PARALLEL_DISPLAY policy<{'armhf': 'm'}> +CONFIG_DRM_IMX_TVE policy<{'armhf': 'm'}> +CONFIG_DRM_INNO_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_ITE_IT6263 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ITE_IT6505 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ITE_IT66121 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_KMB_DISPLAY policy<{'arm64': 'm'}> +CONFIG_DRM_KMS_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_KOMEDA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LIMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_LOAD_EDID_FIRMWARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_LOGICVC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT8912B policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT9211 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LONTIUM_LT9611UXC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_LVDS_CODEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_MALI_DISPLAY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MCDE policy<{'armhf': 'm'}> +CONFIG_DRM_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEDIATEK_HDMI_V2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MESON_DW_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MESON_DW_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER policy<{'armhf': 'm'}> +CONFIG_DRM_MIPI_DBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_MIPI_DSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_MSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_MSM_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DPU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_10NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_14NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_20NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_28NM_8960_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_28NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_DSI_7NM_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_GPU_STATE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_GPU_SUDO policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_DRM_MSM_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_HDMI_HDCP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_KMS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_KMS_FBDEV policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_MDP4 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_MDP5 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MSM_MDSS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_MXS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_MXSFB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_DRM_NOUVEAU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_NOUVEAU_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_NOUVEAU_CH7006 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_NOUVEAU_SIL164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_NOUVEAU_SVM policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DRM_NOVA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_DRM_NWL_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_NXP_PTN3460 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_OFDRM policy<{'ppc64el': 'm'}> +CONFIG_DRM_OMAP policy<{'armhf': 'n'}> +CONFIG_DRM_PANEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_PANEL_ABT_Y030XX067A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ARM_VERSATILE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_AUO_A030JTN01 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BACKLIGHT_QUIRKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_HIMAX8279D policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_TD4320 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_PANEL_DSI_CM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_EBBG_FT8719 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_EDP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ELIDA_KD35T133 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX8279 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83102 policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83112A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX83112B policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HIMAX_HX8394 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_HYDIS_HV101HD1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_IL9322 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9805 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9806E policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9881C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ILITEK_ILI9882T policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_INNOLUX_EJ030NA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_INNOLUX_P079ZCA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JDI_LPM102A188A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JDI_LT070ME05000 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_JDI_R63452 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_KHADAS_TS050 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_LB035Q02 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_LD070WX3 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_LG4573 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LG_SW43408 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_LVDS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_MIPI_DBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NEC_NL8048HL11 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NEWVISION_NV3051D policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NEWVISION_NV3052C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35510 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35560 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT35950 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36523 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36672A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT36672E policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT37801 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_NOVATEK_NT39016 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_DRM_PANEL_ORISETECH_OTA5601A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_ORISETECH_OTM8009A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM67191 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM67200 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM68200 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM692E5 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RAYDIUM_RM69380 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RENESAS_R61307 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RENESAS_R69328 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_RONBO_RB070D30 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_DB7430 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_LD9040 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_LTL106HL02 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3FC2X01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SEIKO_43WVF1G policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LQ079L1SX01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS037V7DW01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS043T1LE01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SHARP_LS060T1SX01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SIMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7701 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7703 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SITRONIX_ST7789V policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SONY_ACX565AKM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SONY_TD4353_JDI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SUMMIT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SYNAPTICS_R63353 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_SYNAPTICS_TDDI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TDO_TL070WSH30 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TPO_TD028TTEC1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TPO_TD043MTEA1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TPO_TPG110 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_G2647FB105 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_R66451 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_RM69299 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_RM692E5 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_VISIONOX_VTDR6130 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANEL_WIDECHIPS_WS2401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_PANEL_XINPENG_XPP055C272 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PANFROST policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_PANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_DRM_PANIC_BACKGROUND_COLOR policy<{'amd64': '0x5e2750', 'arm64': '0x5e2750', 'armhf': '0x5e2750', 'ppc64el': '0x5e2750', 'riscv64': '0x5e2750'}> +CONFIG_DRM_PANIC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DRM_PANIC_FOREGROUND_COLOR policy<{'amd64': '0xffffff', 'arm64': '0xffffff', 'armhf': '0xffffff', 'ppc64el': '0xffffff', 'riscv64': '0xffffff'}> +CONFIG_DRM_PANIC_SCREEN policy<{'amd64': '"user"', 'arm64': '"user"', 'armhf': '"user"', 'ppc64el': '"user"', 'riscv64': '"user"'}> +CONFIG_DRM_PANIC_SCREEN_QR_CODE policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_DRM_PANTHOR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_PARADE_PS8622 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PARADE_PS8640 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PIXPAPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PL111 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_POWERVR policy<{'arm64': 'm', 'riscv64': 'm'}> +CONFIG_DRM_PRIVACY_SCREEN policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_DRM_QXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_RADEON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_RADEON_USERPTR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DRM_RCAR_CMM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RCAR_DU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RCAR_DW_HDMI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_LVDS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RCAR_USE_CMM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_RCAR_USE_LVDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_USE_MIPI_DSI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_DRM_RCAR_VSP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_RCAR_WRITEBACK policy<{'arm64': 'y'}> +CONFIG_DRM_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RZG2L_DU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RZG2L_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_RZG2L_USE_MIPI_DSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_SAMSUNG_DSIM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SCHED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SHMOBILE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_SII902X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SII9234 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SIL_SII8620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SIMPLE_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SOLOMON_SSD2825 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SPRD policy<{'arm64': 'm'}> +CONFIG_DRM_SSD130X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_SSD130X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SSD130X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7571 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_ST7571_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_ST7571_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7586 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7735R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_ST7920 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_STM policy<{'arm64': 'm'}> +CONFIG_DRM_STM_DSI policy<{'arm64': 'm'}> +CONFIG_DRM_STM_LVDS policy<{'arm64': 'm'}> +CONFIG_DRM_SUBALLOC_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_SUN4I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN6I_DSI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN8I_DW_HDMI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN8I_MIXER policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DRM_SUN8I_TCON_TOP policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_DRM_SYSFB_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DRM_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_TEGRA_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_DRM_TEGRA_STAGING policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DRM_THINE_THC63LVD1024 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TIDSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DRM_TILCDC policy<{'armhf': 'm'}> +CONFIG_DRM_TI_DLPC3433 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_SN65DSI83 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_SN65DSI86 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_TDP158 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_TFP410 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TI_TPD12S015 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358762 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358764 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358767 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358768 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TOSHIBA_TC358775 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_TTM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_TTM_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_TVE200 policy<{'armhf': 'm'}> +CONFIG_DRM_TYR policy<{'arm64': 'm'}> +CONFIG_DRM_UDL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DRM_VGEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_VIRTIO_GPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DRM_VIRTIO_GPU_KMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DRM_VKMS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_VMWGFX policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_DRM_VMWGFX_MKSSTATS policy<{'amd64': 'n'}> +CONFIG_DRM_VRAM_HELPER policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_DRM_WAVESHARE_BRIDGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DRM_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_DRM_XE policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DRM_XEN policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_DRM_XEN_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_DRM_XE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_MEM policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_MEMIRQ policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_SRIOV policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DEBUG_VM policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_DISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_DP_TUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_FORCE_PROBE policy<{'amd64': '""', 'arm64': '""', 'arm64-generic-64k': '-', 'armhf': '""', 'ppc64el': '-', 'riscv64': '""'}> +CONFIG_DRM_XE_GPUSVM policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MAX policy<{'amd64': '10000', 'arm64': '10000', 'arm64-generic-64k': '-', 'armhf': '10000', 'ppc64el': '-', 'riscv64': '10000'}> +CONFIG_DRM_XE_JOB_TIMEOUT_MIN policy<{'amd64': '1', 'arm64': '1', 'arm64-generic-64k': '-', 'armhf': '1', 'ppc64el': '-', 'riscv64': '1'}> +CONFIG_DRM_XE_PAGEMAP policy<{'amd64': 'y', 'arm64-generic': 'y', 'riscv64': 'y'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT policy<{'amd64': '640000', 'arm64': '640000', 'arm64-generic-64k': '-', 'armhf': '640000', 'ppc64el': '-', 'riscv64': '640000'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX policy<{'amd64': '10000000', 'arm64': '10000000', 'arm64-generic-64k': '-', 'armhf': '10000000', 'ppc64el': '-', 'riscv64': '10000000'}> +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN policy<{'amd64': '1', 'arm64': '1', 'arm64-generic-64k': '-', 'armhf': '1', 'ppc64el': '-', 'riscv64': '1'}> +CONFIG_DRM_XE_TIMESLICE_MAX policy<{'amd64': '10000000', 'arm64': '10000000', 'arm64-generic-64k': '-', 'armhf': '10000000', 'ppc64el': '-', 'riscv64': '10000000'}> +CONFIG_DRM_XE_TIMESLICE_MIN policy<{'amd64': '1', 'arm64': '1', 'arm64-generic-64k': '-', 'armhf': '1', 'ppc64el': '-', 'riscv64': '1'}> +CONFIG_DRM_XE_USERPTR_INVAL_INJECT policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_XE_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'arm64-generic-64k': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n'}> +CONFIG_DRM_ZYNQMP_DPSUB policy<{'arm64': 'm'}> +CONFIG_DRM_ZYNQMP_DPSUB_AUDIO policy<{'arm64': 'y'}> +CONFIG_DS1682 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DS1803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DS4424 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DST_CACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DTC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DTL policy<{'ppc64el': 'y'}> +CONFIG_DTPM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DTPM_CPU policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DTPM_DEVFREQ policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_DT_IDLE_GENPD policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DT_IDLE_STATES policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DUMMY_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DUMMY_CONSOLE_COLUMNS policy<{'amd64': '80', 'arm64': '80', 'armhf': '80', 'ppc64el': '80', 'riscv64': '80', 's390x': '80'}> +CONFIG_DUMMY_CONSOLE_ROWS policy<{'amd64': '25', 'arm64': '25', 'armhf': '30', 'ppc64el': '25', 'riscv64': '25', 's390x': '25'}> +CONFIG_DUMMY_IRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DVB_A8293 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AF9013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AF9033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AS102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AS102_FE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ASCOT2E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ATBM8830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AU8522 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AU8522_DTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AU8522_V4L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AV7110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_AV7110_IR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_AV7110_OSD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_B2C2_FLEXCOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_B2C2_FLEXCOP_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_BCM3510 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BT8XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET_AV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET_CI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_BUDGET_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX22700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX22702 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24116 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24117 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CX24123 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2099 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2820R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2841ER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_CXD2880 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DDBRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DDBRIDGE_MSIENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_DEMUX_SECTION_LOSS_LOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_DIB3000MB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB3000MC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB7000M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB7000P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB8000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DIB9000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DM1105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DRX39XYJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DRXD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DRXK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DS3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_DYNAMIC_MINORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_EC100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_FIREDTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_FIREDTV_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_GP8PSK_FE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_HELENE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_HOPPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_HORUS3A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ISL6405 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ISL6421 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ISL6423 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_IX2505V policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_L64781 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LG2160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGDT3305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGDT3306A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGDT330X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGS8GL5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LGS8GXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBH25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBH29 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBP21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_LNBP22 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_M88DS3103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_M88RS2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MANTIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MAX_ADAPTERS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_DVB_MB86A16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MB86A20S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MMAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_MN88443X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MN88472 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MN88473 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MT312 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MT352 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MXL5XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_MXL692 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_NETUP_UNIDVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NGENE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NXT200X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_NXT6000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_OR51132 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_OR51211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_PLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PLUTO2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PT1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_PT3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_RTL2830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_RTL2832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_RTL2832_SDR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1409 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S5H1432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_S921 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SI2165 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SI2168 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SI21XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SMIPCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SP8870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_SP887X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STB0899 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STB6000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STB6100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0288 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0297 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0299 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0367 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV090x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV0910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV6110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV6110x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_STV6111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TC90522 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10048 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA1004X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10071 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA10086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA18271C2DD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA665x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA8083 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA8261 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TDA826X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TEST_DRIVERS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_TS2020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TTUSB_BUDGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TTUSB_DEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUA6100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_CX24113 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_DIB0070 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_DIB0090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_TUNER_ITD1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ULE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_A800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9005_REMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AF9035 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_ANYSEE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AU6610 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AZ6007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_AZ6027 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CE6230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CINERGY_T2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CXUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_CXUSB_ANALOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DVB_USB_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_USB_DIB0700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIB3000MC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIBUSB_MB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIBUSB_MB_FAULTY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_DVB_USB_DIBUSB_MC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DIGITV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DTT200U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DTV5100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DVBSKY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_DW2102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_EC168 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_GL861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_GP8PSK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_LME2510 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_M920X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_MXL111SF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_NOVA_T_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_OPERA1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_PCTV452E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_RTL28XXU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_TECHNISAT_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_TTUSB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_UMT_010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_VP702X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_VP7045 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_USB_ZD1301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_VES1820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_VES1X93 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZD1301_DEMOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZL10036 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZL10039 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DVB_ZL10353 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWC_PCIE_PMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DWC_XLGMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DWC_XLGMAC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_DWMAC_DWC_QOS_ETH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_IMX8 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_INTEL policy<{'amd64': 'm'}> +CONFIG_DWMAC_INTEL_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_IPQ806X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_MOTORCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DWMAC_QCOM_ETHQOS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_RENESAS_GBETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_RZN1 policy<{'armhf': 'm'}> +CONFIG_DWMAC_S32 policy<{'arm64': 'm'}> +CONFIG_DWMAC_SOCFPGA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_SOPHGO policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_DWMAC_STM32 policy<{'arm64': 'm'}> +CONFIG_DWMAC_SUN55I policy<{'arm64': 'm'}> +CONFIG_DWMAC_SUN8I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DWMAC_SUNXI policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_DWMAC_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_DWMAC_VISCONTI policy<{'arm64': 'm'}> +CONFIG_DW_APB_ICTL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DW_APB_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DW_APB_TIMER_OF policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_DW_AXI_DMAC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DW_DMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_DMAC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DW_DMAC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_EDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_EDMA_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_DW_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_DW_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DW_XDATA_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_DYNAMIC_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_DEBUG_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_JMP policy<{'amd64': 'y'}> +CONFIG_DYNAMIC_FTRACE_WITH_REGS policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_DYNAMIC_PHYSICAL_MASK policy<{'amd64': 'y'}> +CONFIG_DYNAMIC_SIGFRAME policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_E100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_E1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_E1000E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_E1000E_HWTS policy<{'amd64': 'y'}> +CONFIG_EADM_SCH policy<{'s390x': 'm'}> +CONFIG_EARLY_PRINTK policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_EARLY_PRINTK_DBGP policy<{'amd64': 'y'}> +CONFIG_EARLY_PRINTK_USB policy<{'amd64': 'y'}> +CONFIG_EARLY_PRINTK_USB_XDBC policy<{'amd64': 'y'}> +CONFIG_EBC_C384_WDT policy<{'amd64': 'm'}> +CONFIG_ECRYPT_FS_MESSAGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EC_ACER_ASPIRE1 policy<{'arm64': 'm'}> +CONFIG_EC_HUAWEI_GAOKUN policy<{'arm64': 'm'}> +CONFIG_EC_LENOVO_THINKPAD_T14S policy<{'arm64': 'm'}> +CONFIG_EC_LENOVO_YOGA_C630 policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'n'}> +CONFIG_EC_LENOVO_YOGA_SLIM7X policy<{'arm64': 'm'}> +CONFIG_EDAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_ALTERA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_ETHERNET policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_L2C policy<{'armhf': 'y'}> +CONFIG_EDAC_ALTERA_NAND policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_OCRAM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_QSPI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_SDMMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_SDRAM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_ALTERA_USB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_EDAC_AMD64 policy<{'amd64': 'm'}> +CONFIG_EDAC_ARMADA_XP policy<{'armhf': 'y'}> +CONFIG_EDAC_ASPEED policy<{'armhf': 'm'}> +CONFIG_EDAC_ATOMIC_SCRUB policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_EDAC_BLUEFIELD policy<{'arm64': 'm'}> +CONFIG_EDAC_CORTEX_A72 policy<{'arm64': 'm'}> +CONFIG_EDAC_CPC925 policy<{'ppc64el': 'm'}> +CONFIG_EDAC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_EDAC_DECODE_MCE policy<{'amd64': 'm'}> +CONFIG_EDAC_DMC520 policy<{'arm64': 'm'}> +CONFIG_EDAC_E752X policy<{'amd64': 'm'}> +CONFIG_EDAC_ECS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_GHES policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_EDAC_HIGHBANK_L2 policy<{'armhf': 'm'}> +CONFIG_EDAC_HIGHBANK_MC policy<{'armhf': 'm'}> +CONFIG_EDAC_I10NM policy<{'amd64': 'm'}> +CONFIG_EDAC_I3000 policy<{'amd64': 'm'}> +CONFIG_EDAC_I3200 policy<{'amd64': 'm'}> +CONFIG_EDAC_I5100 policy<{'amd64': 'm'}> +CONFIG_EDAC_I5400 policy<{'amd64': 'm'}> +CONFIG_EDAC_I7300 policy<{'amd64': 'm'}> +CONFIG_EDAC_I7CORE policy<{'amd64': 'm'}> +CONFIG_EDAC_I82975X policy<{'amd64': 'm'}> +CONFIG_EDAC_IE31200 policy<{'amd64': 'm'}> +CONFIG_EDAC_IGEN6 policy<{'amd64': 'm'}> +CONFIG_EDAC_IMH policy<{'amd64': 'm'}> +CONFIG_EDAC_LAYERSCAPE policy<{'arm64': 'm'}> +CONFIG_EDAC_MEM_REPAIR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EDAC_PND2 policy<{'amd64': 'm'}> +CONFIG_EDAC_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EDAC_SBRIDGE policy<{'amd64': 'm'}> +CONFIG_EDAC_SCRUB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_SKX policy<{'amd64': 'm'}> +CONFIG_EDAC_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_EDAC_SYNOPSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EDAC_THUNDERX policy<{'arm64': 'm'}> +CONFIG_EDAC_TI policy<{'armhf': 'm'}> +CONFIG_EDAC_VERSAL policy<{'arm64': 'm'}> +CONFIG_EDAC_VERSALNET policy<{'arm64': 'm'}> +CONFIG_EDAC_X38 policy<{'amd64': 'm'}> +CONFIG_EDAC_XGENE policy<{'arm64': 'm'}> +CONFIG_EDAC_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_EDD policy<{'amd64': 'y'}> +CONFIG_EDD_OFF policy<{'amd64': 'y'}> +CONFIG_EEEPC_LAPTOP policy<{'amd64': 'm'}> +CONFIG_EEEPC_WMI policy<{'amd64': 'm'}> +CONFIG_EEH policy<{'ppc64el': 'y'}> +CONFIG_EEPROM_93CX6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_93XX46 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EEPROM_AT24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_AT25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EEPROM_EE1004 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_IDT_89HPESX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_M24LR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EEPROM_MAX6875 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EFI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_ARMSTUB_DTB_LOADER policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_EFI_BOOTLOADER_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_CAPSULE_LOADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_COCO_SECRET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_DEV_PATH_PARSER policy<{'amd64': 'y'}> +CONFIG_EFI_DISABLE_PCI_DMA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_EFI_DISABLE_RUNTIME policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_EFI_DXE_MEM_ATTRIBUTES policy<{'amd64': 'y'}> +CONFIG_EFI_EARLYCON policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_EMBEDDED_FIRMWARE policy<{'amd64': 'y'}> +CONFIG_EFI_ESRT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_GENERIC_STUB policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_MIXED policy<{'amd64': 'y'}> +CONFIG_EFI_PARAMS_FROM_FDT policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EFI_PGT_DUMP policy<{'amd64': 'n'}> +CONFIG_EFI_RCI2_TABLE policy<{'amd64': 'y'}> +CONFIG_EFI_RUNTIME_MAP policy<{'amd64': 'y'}> +CONFIG_EFI_RUNTIME_WRAPPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_SBAT_FILE policy<{'amd64': '""', 'arm64': '""', 'riscv64': '""'}> +CONFIG_EFI_SECRET policy<{'amd64': 'm', 'arm64': 'n'}> +CONFIG_EFI_SOFT_RESERVE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_EFI_STUB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_EFI_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_VARS_PSTORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_EFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_EINT_MTK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ELFCORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ELF_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EMAC_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EM_TIMER_STI policy<{'armhf': 'y'}> +CONFIG_ENA_ETHERNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENC28J60 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ENC28J60_WRITEVERIFY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ENCLOSURE_SERVICES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ENCRYPTED_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ENCX24J600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ENERGY_MODEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ENIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ENS160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENS160_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENS160_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENS210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ENVELOPE_DETECTOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EPAPR_BOOT policy<{'ppc64el': 'y'}> +CONFIG_EPAPR_PARAVIRT policy<{'ppc64el': 'y'}> +CONFIG_EPIC100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EPOLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EQUALIZER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_EROFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_EROFS_FS_BACKED_BY_FILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_ONDEMAND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_PAGE_CACHE_SHARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_PCPU_KTHREAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EROFS_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_LZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EROFS_FS_ZIP_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ERRATA_ANDES policy<{'riscv64': 'n'}> +CONFIG_ERRATA_MIPS policy<{'riscv64': 'n'}> +CONFIG_ERRATA_SIFIVE policy<{'riscv64': 'n'}> +CONFIG_ERRATA_THEAD policy<{'riscv64': 'n'}> +CONFIG_ET131X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ETHERNET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ETHOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ETHTOOL_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EUROTECH_WDT policy<{'amd64': 'm'}> +CONFIG_EVENTFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVENT_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM_ADD_XATTRS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EVM_EXTRA_SMACK_XATTRS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXAR_WDT policy<{'amd64': 'm'}> +CONFIG_EXCLUSIVE_SYSTEM_RAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXECMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXFAT_DEFAULT_IOCHARSET policy<{'amd64': '"utf8"', 'arm64': '"utf8"', 'armhf': '"utf8"', 'ppc64el': '"utf8"', 'riscv64': '"utf8"', 's390x': '"utf8"'}> +CONFIG_EXFAT_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_EXPERT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXPOLINE policy<{'s390x': 'y'}> +CONFIG_EXPOLINE_AUTO policy<{'s390x': 'y'}> +CONFIG_EXPOLINE_EXTERN policy<{'s390x': 'y'}> +CONFIG_EXPOLINE_FULL policy<{'s390x': 'n'}> +CONFIG_EXPOLINE_OFF policy<{'s390x': 'n'}> +CONFIG_EXPORTFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXPORTFS_BLOCK_OPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_EXT4_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXT4_USE_FOR_EXT2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXTCON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_EXTCON_ADC_JACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EXTCON_AXP288 policy<{'amd64': 'm'}> +CONFIG_EXTCON_FSA9480 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_INTEL_CHT_WC policy<{'amd64': 'm'}> +CONFIG_EXTCON_INTEL_INT3496 policy<{'amd64': 'm'}> +CONFIG_EXTCON_INTEL_MRFLD policy<{'amd64': 'm'}> +CONFIG_EXTCON_LC824206XA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EXTCON_MAX14526 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EXTCON_MAX14577 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX3355 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX77693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX77843 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_PTN5150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_QCOM_SPMI_MISC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EXTCON_RT8973A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_RTK_TYPE_C policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_EXTCON_SM5502 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_USBC_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_EXTCON_USBC_TUSB320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTCON_USB_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_EXTENDED_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXTRA_FIRMWARE policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_EXTRA_TARGETS policy<{'ppc64el': '""'}> +CONFIG_EXT_GROUP_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_EXYNOS5422_DMC policy<{'armhf': 'n'}> +CONFIG_EXYNOS_ACPM_CLK policy<{'armhf': 'n'}> +CONFIG_EXYNOS_ACPM_PROTOCOL policy<{'armhf': 'm'}> +CONFIG_EXYNOS_ADC policy<{'armhf': 'n'}> +CONFIG_EXYNOS_AUDSS_CLK_CON policy<{'armhf': 'n'}> +CONFIG_EXYNOS_CHIPID policy<{'armhf': 'n'}> +CONFIG_EXYNOS_CLKOUT policy<{'armhf': 'n'}> +CONFIG_EXYNOS_CPU_SUSPEND policy<{'armhf': 'y'}> +CONFIG_EXYNOS_IOMMU policy<{'armhf': 'n'}> +CONFIG_EXYNOS_IRQ_COMBINER policy<{'armhf': 'y'}> +CONFIG_EXYNOS_MBOX policy<{'armhf': 'm'}> +CONFIG_EXYNOS_PMU policy<{'armhf': 'y'}> +CONFIG_EXYNOS_PMU_ARM_DRIVERS policy<{'armhf': 'y'}> +CONFIG_EXYNOS_PM_DOMAINS policy<{'armhf': 'y'}> +CONFIG_EXYNOS_SROM policy<{'armhf': 'y'}> +CONFIG_EXYNOS_THERMAL policy<{'armhf': 'y'}> +CONFIG_EXYNOS_USI policy<{'armhf': 'n'}> +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_EZX_PCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_CHECK_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_F2FS_FAULT_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_F2FS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_F2FS_FS_COMPRESSION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZ4HC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_LZORLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_FS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_IOSTAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_F2FS_STAT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F2FS_UNFAIR_RWSEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_F71808E_WDT policy<{'amd64': 'm'}> +CONFIG_FAILOVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FAIR_GROUP_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FANOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FANOTIFY_ACCESS_PERMISSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FARSYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FAT_DEFAULT_CODEPAGE policy<{'amd64': '437', 'arm64': '437', 'armhf': '437', 'ppc64el': '437', 'riscv64': '437', 's390x': '437'}> +CONFIG_FAT_DEFAULT_IOCHARSET policy<{'amd64': '"iso8859-1"', 'arm64': '"iso8859-1"', 'armhf': '"iso8859-1"', 'ppc64el': '"iso8859-1"', 'riscv64': '"iso8859-1"', 's390x': '"iso8859-1"'}> +CONFIG_FAT_DEFAULT_UTF8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FAT_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FAULT_INJECTION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FBNIC policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_3DFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_3DFX_ACCEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_3DFX_I2C policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_ARC policy<{'amd64': 'm'}> +CONFIG_FB_ARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_ASILIANT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FB_ATY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_ATY128 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_ATY128_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_ATY_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_ATY_CT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_ATY_GENERIC_LCD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_ATY_GX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_CARMINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_CARMINE_DRAM_EVAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_CFB_COPYAREA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_CFB_FILLRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_CFB_IMAGEBLIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_CFB_REV_PIXELS_IN_BYTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_CIRRUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_CYBER2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_CYBER2000_DDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_DDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_DEFERRED_IO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_DMAMEM_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_DMAMEM_HELPERS_DEFERRED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_FOREIGN_ENDIAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB_GOLDFISH policy<{'riscv64': 'm'}> +CONFIG_FB_HECUBA policy<{'amd64': 'm'}> +CONFIG_FB_HGA policy<{'amd64': 'm'}> +CONFIG_FB_I740 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_IBM_GXT4500 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB_IMSTT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FB_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FB_IOMEM_FOPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_IOMEM_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_KYRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_MACMODES policy<{'ppc64el': 'm'}> +CONFIG_FB_MATROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_MATROX_G policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MATROX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_MATROX_MAVEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_MATROX_MILLENIUM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MATROX_MYSTIQUE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MB862XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_MB862XX_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_MB862XX_LIME policy<{'ppc64el': 'n'}> +CONFIG_FB_MB862XX_PCI_GDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_METRONOME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_MODE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FB_N411 policy<{'amd64': 'm'}> +CONFIG_FB_NEOMAGIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_NOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_NVIDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_NVIDIA_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_NVIDIA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_NVIDIA_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_OF policy<{'ppc64el': 'm'}> +CONFIG_FB_OMAP2 policy<{'armhf': 'm'}> +CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_CONNECTOR_DVI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_CONNECTOR_HDMI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DEBUG_SUPPORT policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS policy<{'armhf': 'm'}> +CONFIG_FB_OMAP2_DSS_DEBUG policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_DEBUGFS policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_DPI policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_DSI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_HDMI_COMMON policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_INIT policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK policy<{'armhf': '0'}> +CONFIG_FB_OMAP2_DSS_SDI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_DSS_VENC policy<{'armhf': 'y'}> +CONFIG_FB_OMAP2_ENCODER_OPA362 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_ENCODER_TFP410 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_ENCODER_TPD12S015 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_NUM_FBS policy<{'armhf': '3'}> +CONFIG_FB_OMAP2_PANEL_DPI policy<{'armhf': 'n'}> +CONFIG_FB_OMAP2_PANEL_LGPHILIPS_LB035Q02 policy<{'armhf': 'n'}> +CONFIG_FB_OMAP4_DSS_HDMI policy<{'armhf': 'y'}> +CONFIG_FB_OMAP5_DSS_HDMI policy<{'armhf': 'n'}> +CONFIG_FB_OPENCORES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_PM2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_PM2_FIFO_DISCONNECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_PM3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA policy<{'arm64': 'y'}> +CONFIG_FB_RADEON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_RADEON_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_RADEON_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_RADEON_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_RIVA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_RIVA_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_RIVA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_RIVA_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_S1D13XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_S3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_S3_DDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SAVAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_SAVAGE_ACCEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FB_SAVAGE_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SIMPLE policy<{'amd64': '-', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': 'n'}> +CONFIG_FB_SIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SIS_300 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SIS_315 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FB_SM501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_SM712 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SM750 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SMSCUFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SSD1307 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_SVGALIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_SYSMEM_FOPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYSMEM_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYSMEM_HELPERS_DEFERRED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYS_COPYAREA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYS_FILLRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_SYS_IMAGEBLIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FB_TFT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_TFT_AGM1264K_FL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_BD663474 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8340BN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8347D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8353D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_HX8357D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9163 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9325 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9340 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9481 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ILI9486 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_PCD8544 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_RA8875 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_S6D02A1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_S6D1121 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SEPS525 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SH1106 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1289 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1306 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_SSD1351 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ST7735R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_ST7789V policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_TINYLCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_TLS8204 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_UC1611 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_UC1701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TFT_UPD161704 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FB_TILEBLITTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FB_TRIDENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_UDL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_UVESA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_VGA16 policy<{'amd64': 'm', 'ppc64el': '-'}> +CONFIG_FB_VIA policy<{'amd64': 'm'}> +CONFIG_FB_VIA_DIRECT_PROCFS policy<{'amd64': 'n'}> +CONFIG_FB_VIA_X_COMPATIBILITY policy<{'amd64': 'y'}> +CONFIG_FB_VIRTUAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FB_VOODOO1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FB_VT8623 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FB_XILINX policy<{'arm64': 'm'}> +CONFIG_FCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FCOE_FNIC policy<{'amd64': 'm'}> +CONFIG_FDDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FDMA policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FEALNX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FEC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_FHCI_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_FIB_RULES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FILE_LOCKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FIND_BIT_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FIND_BIT_BENCHMARK_RUST policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_FIND_NORMAL_PAGE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_FIPS_SIGNATURE_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FIQ policy<{'armhf': 'y'}> +CONFIG_FIREWIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FIREWIRE_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FIREWIRE_NOSY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FIREWIRE_OHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FIREWIRE_SBP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FIRMWARE_EDID policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n', 's390x': '-'}> +CONFIG_FIRMWARE_MEMMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FIRMWARE_TABLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FIXED_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FIX_EARLYCON_MEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_FLATMEM_MANUAL policy<{'armhf': 'n'}> +CONFIG_FM10K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FONTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_10x18 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_6x10 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_6x11 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_6x8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_7x14 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_8x16 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_8x8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_ACORN_8x8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_MINI_4x6 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_PEARL_8x8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_SUN12x22 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_SUN8x16 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FONT_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_TER10x18 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FONT_TER16x32 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FORCEDETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FORCE_PCI policy<{'ppc64el': 'y'}> +CONFIG_FORCE_SMP policy<{'ppc64el': 'y'}> +CONFIG_FORTIFY_SOURCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_FPGA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FPGA_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_FPGA_DFL_AFU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_EMIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME_MGR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_FME_REGION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_DFL_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_M10_BMC_SEC_UPDATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_FPGA_MGR_ALTERA_CVP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_MGR_ALTERA_PS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FPGA_MGR_ICE40_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_MACHXO2_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FPGA_MGR_MICROCHIP_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPGA_MGR_SOCFPGA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FPGA_MGR_SOCFPGA_A10 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FPGA_MGR_STRATIX10_SOC policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_VERSAL_FPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_MGR_XILINX_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_MGR_XILINX_SELECTMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FPGA_MGR_XILINX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FPGA_MGR_ZYNQMP_FPGA policy<{'arm64': 'm'}> +CONFIG_FPGA_REGION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FPROBE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FPU policy<{'riscv64': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FRAMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FRAMER_PEF2256 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FRAME_POINTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_FRAME_WARN policy<{'amd64': '1024', 'arm64': '1024', 'armhf': '1024', 'ppc64el': '2048', 'riscv64': '1024', 's390x': '1024'}> +CONFIG_FREEZER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FSCACHE_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_ASPEED policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_AST_CF policy<{'armhf': 'm'}> +CONFIG_FSI_MASTER_GPIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_HUB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_MASTER_I2CR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_NEW_DEV_NODE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_FSI_OCC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_SBEFIFO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSI_SCOM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSL_BMAN_TEST policy<{'arm64': 'm'}> +CONFIG_FSL_BMAN_TEST_API policy<{'arm64': 'n'}> +CONFIG_FSL_DPAA policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA2_ETH policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_ETH_DCB policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA2_PTP_CLOCK policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_QDMA policy<{'arm64': 'm'}> +CONFIG_FSL_DPAA2_SWITCH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_DPAA_CHECKING policy<{'arm64': 'y'}> +CONFIG_FSL_DPAA_ETH policy<{'arm64': 'm'}> +CONFIG_FSL_EDMA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FSL_ENETC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_CORE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_IERB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_MDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_PTP_CLOCK policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ENETC_QOS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_FSL_ENETC_VF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_ERRATUM_A008585 policy<{'arm64': 'y'}> +CONFIG_FSL_FMAN policy<{'arm64': 'y'}> +CONFIG_FSL_GTM policy<{'ppc64el': 'y'}> +CONFIG_FSL_GUTS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_FSL_IFC policy<{'arm64': 'y'}> +CONFIG_FSL_IMX8_DDR_PMU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FSL_IMX9_DDR_PMU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FSL_LBC policy<{'ppc64el': 'y'}> +CONFIG_FSL_MC_BUS policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_FSL_MC_DPIO policy<{'arm64': 'm'}> +CONFIG_FSL_MC_UAPI_SUPPORT policy<{'arm64': 'y'}> +CONFIG_FSL_PQ_MDIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_QDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_FSL_QMAN_TEST policy<{'arm64': 'n'}> +CONFIG_FSL_RCPM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_FSL_UCC_HDLC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_FSL_XGMAC_MDIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_FSNOTIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_DAX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_DAX_PMD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_ENCRYPTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_ENCRYPTION_ALGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_ENCRYPTION_INLINE_CRYPT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_IOMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_MBCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_VERITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FS_VERITY_BUILTIN_SIGNATURES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FTGMAC100 policy<{'armhf': 'm'}> +CONFIG_FTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FTMAC100 policy<{'armhf': 'm'}> +CONFIG_FTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FTRACE_MCOUNT_USE_CC policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_FTRACE_RECORD_RECURSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FTRACE_SORT_STARTUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 's390x': 'n'}> +CONFIG_FTRACE_STARTUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FTRACE_SYSCALLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FTR_FIXUP_SELFTEST policy<{'ppc64el': 'n'}> +CONFIG_FTWDT010_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_FUEL_GAUGE_MM8013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUEL_GAUGE_SC27XX policy<{'arm64': 'm'}> +CONFIG_FUEL_GAUGE_STC3117 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUJITSU_ERRATUM_010001 policy<{'arm64': 'y'}> +CONFIG_FUJITSU_ES policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_FUJITSU_LAPTOP policy<{'amd64': 'm'}> +CONFIG_FUJITSU_TABLET policy<{'amd64': 'm'}> +CONFIG_FUJITSU_UNCORE_PMU policy<{'arm64': 'm'}> +CONFIG_FUNCTION_ALIGNMENT policy<{'amd64': '16', 'arm64': '8', 'armhf': '0', 'ppc64el': '4', 'riscv64': '8', 's390x': '8'}> +CONFIG_FUNCTION_ALIGNMENT_16B policy<{'amd64': 'y'}> +CONFIG_FUNCTION_ALIGNMENT_4B policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FUNCTION_ALIGNMENT_8B policy<{'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_ERROR_INJECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_GRAPH_RETADDR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_GRAPH_RETVAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_GRAPH_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_PADDING_BYTES policy<{'amd64': '16'}> +CONFIG_FUNCTION_PADDING_CFI policy<{'amd64': '11'}> +CONFIG_FUNCTION_PROFILER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_SELF_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUNCTION_TRACE_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUN_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUN_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUSE_DAX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSE_IO_URING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSE_PASSTHROUGH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUSION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_FUSION_CTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUSION_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FUSION_LAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FUSION_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FUSION_MAX_SGE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_FUSION_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FUSION_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_FUTEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUTEX_MPOL policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUTEX_PI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FUTEX_PRIVATE_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FWCTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FWCTL_MLX5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FWCTL_PDS policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FWNODE_MDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FW_ATTR_CLASS policy<{'amd64': 'm'}> +CONFIG_FW_CACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_FW_CFG_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_FW_CFG_SYSFS_CMDLINE policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_FW_CS_DSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_FW_LOADER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_COMPRESS_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_COMPRESS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_PAGED_BUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_LOADER_USER_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_FW_UPLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_FXAS21002C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXAS21002C_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXAS21002C_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXLS8962AF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXLS8962AF_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXLS8962AF_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXOS8700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXOS8700_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_FXOS8700_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GACT_PROB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GADGET_UAC1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GADGET_UAC1_LEGACY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_GAMEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GAMEPORT_EMU10K1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GAMEPORT_FM801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GART_IOMMU policy<{'amd64': 'y'}> +CONFIG_GCC10_NO_ARRAY_BOUNDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GCC_NO_STRINGOP_OVERFLOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE policy<{'riscv64': 'y'}> +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS policy<{'arm64': 'y'}> +CONFIG_GCC_VERSION policy<{'amd64': '150200', 'arm64': '150200', 'armhf': '150200', 'ppc64el': '150200', 'riscv64': '150200', 's390x': '150200'}> +CONFIG_GCOV_KERNEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GDB_SCRIPTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GEHC_PMC_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GEMINI_ETHERNET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GENDWARFKSYMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GENERIC_ADC_BATTERY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GENERIC_ADC_THERMAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GENERIC_ALLOCATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_ARCH_NUMA policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_ARCH_TOPOLOGY policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_BUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_BUG_RELATIVE_POINTERS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CALIBRATE_DELAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST_IDLE policy<{'amd64': 'y'}> +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST policy<{'amd64': 'y'}> +CONFIG_GENERIC_CMOS_UPDATE policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_GENERIC_CPU_AUTOPROBE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CPU_CACHE_MAINTENANCE policy<{'arm64': 'y'}> +CONFIG_GENERIC_CPU_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CPU_VULNERABILITIES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_CSUM policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_EARLY_IOREMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_ENTRY policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_FRAMER policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_GETTIMEOFDAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_HWEIGHT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_GENERIC_IDLE_POLL_SETUP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IOMAP policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_GENERIC_IOREMAP policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_IRQ_CHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_ENTRY policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_IRQ_IPI policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_IPI_MUX policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD policy<{'arm64': 'y'}> +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_MULTI_HANDLER policy<{'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_PROBE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_GENERIC_IRQ_RESERVATION_MODE policy<{'amd64': 'y'}> +CONFIG_GENERIC_IRQ_SHOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_IRQ_SHOW_LEVEL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_ISA_DMA policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_LOCKBREAK policy<{'ppc64el': 'y', 's390x': 'y'}> +CONFIG_GENERIC_MSI_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_NET_UTILS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_PCI_IOMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PENDING_IRQ policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GENERIC_PHY_MIPI_DPHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PINCONF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PINCTRL policy<{'arm64': 'y'}> +CONFIG_GENERIC_PINCTRL_GROUPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PINMUX_FUNCTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_PT policy<{'amd64': 'y'}> +CONFIG_GENERIC_SCHED_CLOCK policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_GENERIC_SMP_IDLE_THREAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_STRNCPY_FROM_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_STRNLEN_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_SYSCALL policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_TIME_VSYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GENERIC_VDSO_OVERFLOW_PROTECT policy<{'amd64': 'y'}> +CONFIG_GENEVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GENKSYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_GENWQE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY policy<{'amd64': '0', 'arm64': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_GEN_RTC policy<{'ppc64el': 'y'}> +CONFIG_GET_FREE_REGION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GFS2_FS_LOCKING_DLM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GIANFAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_GIGABYTE_WMI policy<{'amd64': 'm'}> +CONFIG_GLOB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GNSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GNSS_MTK_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_SIRF_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_UBX_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GNSS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GOLDFISH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GOLDFISH_PIPE policy<{'riscv64': 'm'}> +CONFIG_GOLDFISH_TTY policy<{'riscv64': 'm'}> +CONFIG_GOOGLE_FIRMWARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GP2AP002 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GP2AP020A00F policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPD_POCKET_FAN policy<{'amd64': 'm'}> +CONFIG_GPIB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GPIOLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIOLIB_FASTPATH_LIMIT policy<{'amd64': '512', 'arm64': '512', 'armhf': '512', 'ppc64el': '512', 'riscv64': '512', 's390x': '512'}> +CONFIG_GPIOLIB_IRQCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIOLIB_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_104_DIO_48E policy<{'amd64': 'm'}> +CONFIG_GPIO_104_IDIO_16 policy<{'amd64': 'm'}> +CONFIG_GPIO_104_IDI_48 policy<{'amd64': 'm'}> +CONFIG_GPIO_74X164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_74XX_MMIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_AAEON policy<{'amd64': 'm'}> +CONFIG_GPIO_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_ADNP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_AGGREGATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_ALTERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_ALTERA_A10SR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_AMD8111 policy<{'amd64': 'm'}> +CONFIG_GPIO_AMDPT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_AMD_FCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_ARIZONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_ASPEED policy<{'armhf': 'm'}> +CONFIG_GPIO_ASPEED_SGPIO policy<{'armhf': 'y'}> +CONFIG_GPIO_BD71815 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BD72720 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BD9571MWV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_BLZP1600 policy<{'arm64': 'm'}> +CONFIG_GPIO_BT8XX policy<{'s390x': 'm'}> +CONFIG_GPIO_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_CDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_CGBC policy<{'amd64': 'm'}> +CONFIG_GPIO_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_CRYSTAL_COVE policy<{'amd64': 'y'}> +CONFIG_GPIO_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_DAVINCI policy<{'arm64': 'y'}> +CONFIG_GPIO_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_DS4520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_DWAPB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_EIC_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_GPIO_EN7523 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_EXAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_F7188X policy<{'amd64': 'm'}> +CONFIG_GPIO_FTGPIO010 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_FXL6408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_GPIO_GENERIC_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_GPIO_GPIO_MM policy<{'amd64': 'm'}> +CONFIG_GPIO_GRANITERAPIDS policy<{'amd64': 'm'}> +CONFIG_GPIO_GRGPIO policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_GW_PLD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_HISI policy<{'arm64': 'm'}> +CONFIG_GPIO_HLWD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_I8255 policy<{'amd64': 'm'}> +CONFIG_GPIO_ICH policy<{'amd64': 'm'}> +CONFIG_GPIO_IDIO_16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_IMX_SCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_IT87 policy<{'amd64': 'm'}> +CONFIG_GPIO_JANZ_TTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_KEMPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LATCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_LINE_MUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LOGICVC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LP3943 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LP873X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_LP87565 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MACSMC policy<{'arm64': 'm'}> +CONFIG_GPIO_MADERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX3191X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_MAX7300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_MAX7301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_MAX730X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX732X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX77620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MAX77759 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MB86S7X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_MC33880 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_MENZ127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MLXBF policy<{'arm64': 'm'}> +CONFIG_GPIO_MLXBF2 policy<{'arm64': 'm'}> +CONFIG_GPIO_MLXBF3 policy<{'arm64': 'm'}> +CONFIG_GPIO_ML_IOH policy<{'amd64': 'm'}> +CONFIG_GPIO_MOCKUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GPIO_MOXTET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MPC8XXX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_MPSSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_MSC313 policy<{'armhf': 'y'}> +CONFIG_GPIO_MVEBU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_MXC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_NPCM_SGPIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_OMAP policy<{'armhf': 'y'}> +CONFIG_GPIO_PALMAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_PCA953X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_PCA953X_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_PCA9570 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_PCF857X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_PCIE_IDIO_24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_PCI_IDIO_16 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_PISOSR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_PL061 policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_GPIO_PMIC_EIC_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_POLARFIRE_SOC policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GPIO_PXA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_QIXIS_FPGA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_RC5T583 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_RDA policy<{'armhf': 'y'}> +CONFIG_GPIO_RDC321X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_REGMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_RTD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_SCH policy<{'amd64': 'm'}> +CONFIG_GPIO_SCH311X policy<{'amd64': 'm'}> +CONFIG_GPIO_SHARED policy<{'arm64': 'y'}> +CONFIG_GPIO_SHARED_PROXY policy<{'arm64': 'm'}> +CONFIG_GPIO_SIFIVE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_SIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GPIO_SIOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_SPRD policy<{'arm64': 'm'}> +CONFIG_GPIO_STMPE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_SWNODE_UNDEFINED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_SYSCON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_SYSFS_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GPIO_TANGIER policy<{'amd64': 'm'}> +CONFIG_GPIO_TC3589X policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_TEGRA186 policy<{'arm64': 'y'}> +CONFIG_GPIO_THUNDERX policy<{'arm64': 'm'}> +CONFIG_GPIO_TN48M_CPLD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_GPIO_TPIC2810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_TPS65086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TPS65218 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TPS65219 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TPS6586X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_TPS65910 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GPIO_TPS65912 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_TPS68470 policy<{'amd64': 'm'}> +CONFIG_GPIO_TQMX86 policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_TS4800 policy<{'armhf': 'm'}> +CONFIG_GPIO_TS4900 policy<{'armhf': 'm'}> +CONFIG_GPIO_TWL6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_USBIO policy<{'amd64': 'm', 'arm64': '-', 'riscv64': '-'}> +CONFIG_GPIO_VF610 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_GPIO_VIPERBOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_VIRTUSER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GPIO_VISCONTI policy<{'arm64': 'm'}> +CONFIG_GPIO_VX855 policy<{'amd64': 'm'}> +CONFIG_GPIO_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_WCD934X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_WHISKEY_COVE policy<{'amd64': 'm'}> +CONFIG_GPIO_WINBOND policy<{'amd64': 'm'}> +CONFIG_GPIO_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_WM8994 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GPIO_WS16C48 policy<{'amd64': 'm'}> +CONFIG_GPIO_XGENE policy<{'arm64': 'y'}> +CONFIG_GPIO_XGENE_SB policy<{'arm64': 'm'}> +CONFIG_GPIO_XILINX policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_GPIO_XLP policy<{'arm64': 'm'}> +CONFIG_GPIO_XRA1403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GPIO_ZEVIO policy<{'armhf': 'y'}> +CONFIG_GPIO_ZYNQ policy<{'arm64': 'm'}> +CONFIG_GPIO_ZYNQMP_MODEPIN policy<{'arm64': 'm'}> +CONFIG_GP_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_GRACE_PERIOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GREENASIA_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_GREYBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_GREYBUS_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_AUDIO_APB_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_BEAGLEPLAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_BOOTROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_BRIDGED_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_ES2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_FIRMWARE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_LIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_LOOPBACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GREYBUS_VIBRATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_GROUP_SCHED_BANDWIDTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GROUP_SCHED_WEIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GRO_CELLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_GTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_GUEST_PERF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_GUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_GVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_GXP_TIMER policy<{'armhf': 'y'}> +CONFIG_GXP_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_HALTPOLL_CPUIDLE policy<{'amd64': 'm'}> +CONFIG_HAMACHI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HAMRADIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HANGCHECK_TIMER policy<{'amd64': 'm', 'ppc64el': 'm', 's390x': 'm'}> +CONFIG_HAPPYMEAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HARDENED_USERCOPY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HARDENED_USERCOPY_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HARDEN_BRANCH_HISTORY policy<{'armhf': 'y'}> +CONFIG_HARDEN_BRANCH_PREDICTOR policy<{'armhf': 'y'}> +CONFIG_HARDIRQS_SW_RESEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP policy<{'amd64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_ARCH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_HARDLOCKUP_DETECTOR_BUDDY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_COUNTS_HRTIMER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HARDLOCKUP_DETECTOR_PERF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_HAS_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAS_IOMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAS_IOPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAS_IOPORT_MAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAS_SECURITY_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_64BIT_ALIGNED_ACCESS policy<{'riscv64': 'y'}> +CONFIG_HAVE_ACPI_APEI policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_HAVE_ACPI_APEI_NMI policy<{'amd64': 'y'}> +CONFIG_HAVE_ALIGNED_STRUCT_PAGE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_AUDITSYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_BITREVERSE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES policy<{'amd64': 'y'}> +CONFIG_HAVE_ARCH_COMPILER_H policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_HUGE_VMALLOC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_HUGE_VMAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_JUMP_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KASAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KASAN_HW_TAGS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN_SW_TAGS policy<{'arm64': 'y'}> +CONFIG_HAVE_ARCH_KASAN_VMALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KCSAN policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KFENCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KGDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT policy<{'riscv64': 'y'}> +CONFIG_HAVE_ARCH_KMSAN policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_KSTACK_ERASE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_MMAP_RND_BITS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-'}> +CONFIG_HAVE_ARCH_NODE_DEV_GROUP policy<{'amd64': 'y'}> +CONFIG_HAVE_ARCH_NVRAM_OPS policy<{'ppc64el': 'y'}> +CONFIG_HAVE_ARCH_PFN_VALID policy<{'armhf': 'y'}> +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_SECCOMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_SECCOMP_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_SOFT_DIRTY policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_TLB_REMOVE_TABLE policy<{'ppc64el': 'y'}> +CONFIG_HAVE_ARCH_TRACEHOOK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_USERFAULTFD_MINOR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_USERFAULTFD_WP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_ARCH_VMAP_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_ARM_ARCH_TIMER policy<{'armhf': 'y'}> +CONFIG_HAVE_ARM_SCU policy<{'armhf': 'y'}> +CONFIG_HAVE_ARM_SMCCC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_ARM_SMCCC_DISCOVERY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_ARM_TWD policy<{'armhf': 'y'}> +CONFIG_HAVE_ASM_MODVERSIONS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_BOOTMEM_INFO_NODE policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 's390x': 'y'}> +CONFIG_HAVE_CALL_THUNKS policy<{'amd64': 'y'}> +CONFIG_HAVE_CLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_CLK_PREPARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_CMPXCHG_DOUBLE policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_HAVE_CMPXCHG_LOCAL policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_HAVE_CONTEXT_TRACKING_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_CONTEXT_TRACKING_USER_OFFSTACK policy<{'amd64': 'y'}> +CONFIG_HAVE_C_RECORDMCOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_DEBUG_KMEMLEAK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DEBUG_STACKOVERFLOW policy<{'ppc64el': 'y'}> +CONFIG_HAVE_DMA_CONTIGUOUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE policy<{'amd64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_JMP policy<{'amd64': 'y'}> +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_EBPF_JIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_EXIT_THREAD policy<{'amd64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_EXTRA_IPI_TRACEPOINTS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HAVE_FENTRY policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FTRACE_GRAPH_FUNC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FTRACE_REGS_HAVING_PT_REGS policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_ERROR_INJECTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_GRAPH_FREGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_GRAPH_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_FUNCTION_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GCC_PLUGINS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GENERIC_TIF_BITS policy<{'amd64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GENERIC_VDSO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GIGANTIC_FOLIOS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_GUP_FAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_ARCH policy<{'ppc64el': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_HW_BREAKPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_IMA_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_IMX_ANATOP policy<{'armhf': 'y'}> +CONFIG_HAVE_IMX_GPC policy<{'armhf': 'y'}> +CONFIG_HAVE_IMX_MMDC policy<{'armhf': 'y'}> +CONFIG_HAVE_IMX_SRC policy<{'armhf': 'y'}> +CONFIG_HAVE_INTEL_TXT policy<{'amd64': 'y'}> +CONFIG_HAVE_IOREMAP_PROT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_IRQ_TIME_ACCOUNTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_JUMP_LABEL_HACK policy<{'amd64': 'y'}> +CONFIG_HAVE_KCSAN_COMPILER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_BZIP2 policy<{'amd64': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_GZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_LZ4 policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_LZMA policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_LZO policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_UNCOMPRESSED policy<{'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_XZ policy<{'amd64': 'y', 'arm64': '-', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KERNEL_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KLP_BUILD policy<{'amd64': 'y'}> +CONFIG_HAVE_KPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KPROBES_ON_FTRACE policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_HAVE_KRETPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_ARCH_GMEM_INVALIDATE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_ARCH_GMEM_POPULATE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_ARCH_GMEM_PREPARE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_DIRTY_RING_TSO policy<{'amd64': 'y', 'arm64': '-'}> +CONFIG_HAVE_KVM_INVALID_WAKEUPS policy<{'s390x': 'y'}> +CONFIG_HAVE_KVM_IRQCHIP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_IRQ_BYPASS policy<{'amd64': 'm', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_KVM_IRQ_ROUTING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_MSI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_NO_POLL policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_HAVE_KVM_PFNCACHE policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_PM_NOTIFIER policy<{'amd64': 'y'}> +CONFIG_HAVE_KVM_READONLY_MEM policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE policy<{'arm64': 'y'}> +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_LIVEPATCH policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_MARCH_Z10_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z13_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z14_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z15_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_Z196_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MARCH_ZEC12_FEATURES policy<{'s390x': 'y'}> +CONFIG_HAVE_MEMBLOCK_PHYS_MAP policy<{'s390x': 'y'}> +CONFIG_HAVE_MEMORYLESS_NODES policy<{'ppc64el': 'y'}> +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS policy<{'amd64': 'y'}> +CONFIG_HAVE_MMIOTRACE_SUPPORT policy<{'amd64': 'y'}> +CONFIG_HAVE_MOD_ARCH_SPECIFIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_MOVE_PMD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_MOVE_PUD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_NMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_NOINSTR_HACK policy<{'amd64': 'y'}> +CONFIG_HAVE_NOINSTR_VALIDATION policy<{'amd64': 'y'}> +CONFIG_HAVE_NOP_MCOUNT policy<{'s390x': 'y'}> +CONFIG_HAVE_OBJTOOL policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_OBJTOOL_MCOUNT policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_OBJTOOL_NOP_MCOUNT policy<{'amd64': 'y'}> +CONFIG_HAVE_OPTPROBES policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PAGE_SIZE_4KB policy<{'amd64': 'y', 'arm64-generic': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PAGE_SIZE_64KB policy<{'arm64-generic-64k': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PCSPKR_PLATFORM policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PERF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PERF_EVENTS_NMI policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HAVE_PERF_REGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PERF_USER_STACK_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PNETID policy<{'s390x': 'm'}> +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC_CALL policy<{'amd64': 'y'}> +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY policy<{'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_PROC_CPU policy<{'armhf': 'y'}> +CONFIG_HAVE_PV_STEAL_CLOCK_GEN policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_PWRCTRL policy<{'arm64': 'y'}> +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_RELIABLE_STACKTRACE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_RETHOOK policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_RSEQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_RUST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_SCHED_AVG_IRQ policy<{'ppc64el': 'y'}> +CONFIG_HAVE_SETUP_PER_CPU_AREA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_SHARED_GPIOS policy<{'arm64': 'y'}> +CONFIG_HAVE_SINGLE_FTRACE_DIRECT_OPS policy<{'amd64': 'y'}> +CONFIG_HAVE_SMP policy<{'armhf': 'y'}> +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_STACKPROTECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HAVE_STACK_VALIDATION policy<{'amd64': 'y'}> +CONFIG_HAVE_STATIC_CALL policy<{'amd64': 'y'}> +CONFIG_HAVE_STATIC_CALL_INLINE policy<{'amd64': 'y'}> +CONFIG_HAVE_SYSCALL_TRACEPOINTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_TRUSTED_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_UACCESS_VALIDATION policy<{'amd64': 'y'}> +CONFIG_HAVE_UID16 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 's390x': '-'}> +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK policy<{'amd64': 'y'}> +CONFIG_HAVE_UNWIND_USER_FP policy<{'amd64': 'y'}> +CONFIG_HAVE_USER_RETURN_NOTIFIER policy<{'amd64': 'y'}> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING policy<{'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_IDLE policy<{'s390x': 'y'}> +CONFIG_HBMC_AM654 policy<{'arm64': 'm'}> +CONFIG_HCALL_STATS policy<{'ppc64el': 'n'}> +CONFIG_HD44780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HD44780_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDC100X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDC2010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDC3020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HDLC_CISCO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_FR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_PPP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_RAW_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDLC_X25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HDMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HDMI_LPE_AUDIO policy<{'amd64': 'm'}> +CONFIG_HDQ_MASTER_OMAP policy<{'armhf': 'm'}> +CONFIG_HEADERS_INSTALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HFI1_DEBUG_SDMA_ORDER policy<{'amd64': 'n'}> +CONFIG_HFSPLUS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HI13X1_GMAC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HI3660_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HI6220_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HI6421V600_IRQ policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HI8435 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HIBERNATE_CALLBACKS policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HIBERNATION_COMP_LZ4 policy<{'amd64': 'n', 'armhf': 'n', 'riscv64': 'n'}> +CONFIG_HIBERNATION_COMP_LZO policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HIBERNATION_DEF_COMP policy<{'amd64': '"lzo"', 'armhf': '"lzo"', 'riscv64': '"lzo"'}> +CONFIG_HIBERNATION_SNAPSHOT_DEV policy<{'amd64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HIBMCGE policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HIDRAW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_HID_A4TECH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ACCUTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_ACRUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ACRUX_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_ALPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_APPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_APPLEIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_APPLETB_BL policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_HID_APPLETB_KBD policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_HID_ASUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_AUREAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_BATTERY_STRENGTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_HID_BELKIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_BETOP_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_BIGBEN_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_BPF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_CHERRY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_CHICONY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_CMEDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_CORSAIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_COUGAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_CP2112 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_CREATIVE_SB0540 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_CYPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_DRAGONRISE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ELAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_ELECOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ELO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_EMS_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_EVISION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_EZKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_FT260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GEMBIRD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GFRM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GLORIOUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GOODIX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GOOGLE_HAMMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_HID_GOOGLE_STADIA_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GREENASIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_GT683R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_GYRATION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_HAPTIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_HOLTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_HYPERV_MOUSE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HID_ICADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_JABRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KENSINGTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KEYTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KYE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_KYSONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LCPOWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_LENOVO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_LETSKETCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LOGITECH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LOGITECH_DJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_LOGITECH_HIDPP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MACALLY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MAGICMOUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MALTRON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MAYFLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MCP2200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MCP2221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MEGAWORLD_FF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_MICROSOFT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MONTEREY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_MULTITOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_NINTENDO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_NTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_NTRIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_NVIDIA_SHIELD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_ORTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PANTHERLORD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PENMOUNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_PETALYNX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PICOLCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PICOLCD_BACKLIGHT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_CIR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_FB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_LCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PICOLCD_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HID_PLANTRONICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PLAYSTATION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_PRIMAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_PRODIKEYS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_PXRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_RAPOO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_RAZER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_REDRAGON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_RETRODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_RMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ROCCAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SAITEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SAMSUNG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SEMITEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SENSOR_ACCEL_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_ALS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_CUSTOM_SENSOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_DEVICE_ROTATION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_GYRO_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_HUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SENSOR_HUMIDITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_IIO_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_IIO_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_INCLINOMETER_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_MAGNETOMETER_3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_PRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_PROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SENSOR_TEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SIGMAMICRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SMARTJOYPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SONY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_SPEEDLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_STEAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_STEELSERIES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SUNPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HID_THINGM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_THRUSTMASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_TIVO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_TOPRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_TOPSEED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_TWINHAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_U2FZERO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_UCLOGIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_UDRAW_PS3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_UNIVERSAL_PIDFF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_VIEWSONIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_VIVALDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_VIVALDI_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_VRC2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_WACOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_WALTOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_WIIMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_WINWING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_XIAOMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HID_XINMO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ZEROPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HID_ZYDACRON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HIGHMEM policy<{'armhf': 'y'}> +CONFIG_HIGHPTE policy<{'armhf': 'y'}> +CONFIG_HIGH_RES_TIMERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HINIC policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HINIC3 policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HIP04_ETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HISILICON_ERRATUM_161010101 policy<{'arm64': 'y'}> +CONFIG_HISILICON_ERRATUM_161600802 policy<{'arm64': 'y'}> +CONFIG_HISILICON_ERRATUM_162100801 policy<{'arm64': 'y'}> +CONFIG_HISILICON_IRQ_MBIGEN policy<{'arm64': 'y'}> +CONFIG_HISILICON_LPC policy<{'arm64': 'y'}> +CONFIG_HISI_ACC_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_HISI_DMA policy<{'arm64': 'n', 'armhf': 'm'}> +CONFIG_HISI_FEMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HISI_HIKEY_USB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_HISI_PCIE_PMU policy<{'arm64': 'm'}> +CONFIG_HISI_PMU policy<{'arm64': 'm'}> +CONFIG_HISI_PTT policy<{'arm64': 'm'}> +CONFIG_HISI_SOC_HHA policy<{'arm64': 'm'}> +CONFIG_HISI_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HIST_TRIGGERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HIST_TRIGGERS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HIX5HD2_GMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HL_HLDIO policy<{'amd64': 'y'}> +CONFIG_HMC425 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HMC6352 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HMC_DRV policy<{'s390x': 'm'}> +CONFIG_HMEM_REPORTING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HMM_MIRROR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HNS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3_DCB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HNS3_ENET policy<{'arm64': 'm'}> +CONFIG_HNS3_HCLGE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3_HCLGEVF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS3_PMU policy<{'arm64': 'm'}> +CONFIG_HNS_DSAF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS_ENET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HNS_MDIO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HOLTEK_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC_DEAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CORE_SYNC_FULL policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_CPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PARALLEL policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PCI_ACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA policy<{'arm64': 'm'}> +CONFIG_HOTPLUG_PCI_ACPI_IBM policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_HOTPLUG_PCI_CPCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_PCI_CPCI_GENERIC policy<{'amd64': 'm'}> +CONFIG_HOTPLUG_PCI_CPCI_ZT5550 policy<{'amd64': 'm'}> +CONFIG_HOTPLUG_PCI_OCTEONEP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HOTPLUG_PCI_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_HOTPLUG_PCI_RPA policy<{'ppc64el': 'm'}> +CONFIG_HOTPLUG_PCI_RPA_DLPAR policy<{'ppc64el': 'm'}> +CONFIG_HOTPLUG_PCI_S390 policy<{'s390x': 'y'}> +CONFIG_HOTPLUG_SMT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_HOTPLUG_SPLIT_STARTUP policy<{'amd64': 'y', 'riscv64': 'y'}> +CONFIG_HP03 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HP206C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HPET policy<{'amd64': 'y'}> +CONFIG_HPET_EMULATE_RTC policy<{'amd64': 'y'}> +CONFIG_HPET_MMAP policy<{'amd64': 'y'}> +CONFIG_HPET_MMAP_DEFAULT policy<{'amd64': 'y'}> +CONFIG_HPET_TIMER policy<{'amd64': 'y'}> +CONFIG_HPFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HPWDT_NMI_DECODING policy<{'amd64': 'y'}> +CONFIG_HP_ACCEL policy<{'amd64': 'm'}> +CONFIG_HP_BIOSCFG policy<{'amd64': 'm'}> +CONFIG_HP_ILO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HP_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HP_WMI policy<{'amd64': 'm'}> +CONFIG_HSA_AMD policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSA_AMD_SVM policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSC030PA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSC030PA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSC030PA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HSI_BOARDINFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_HSI_CHAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HSR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HT16K33 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_HTC_EGPIO policy<{'armhf': 'y'}> +CONFIG_HTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HTE_TEGRA194 policy<{'arm64': 'm'}> +CONFIG_HTE_TEGRA194_TEST policy<{'arm64': 'm'}> +CONFIG_HTMDUMP policy<{'ppc64el': 'm'}> +CONFIG_HTS221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HTS221_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HTS221_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HTU21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HUAWEI_WMI policy<{'amd64': 'm'}> +CONFIG_HUGETLBFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HUGETLB_PAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP policy<{'amd64': 'y', 'arm64': '-', 'riscv64': 'y', 's390x': '-'}> +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON policy<{'amd64': 'n', 'arm64': '-', 'riscv64': 'n', 's390x': '-'}> +CONFIG_HUGETLB_PAGE_SIZE_VARIABLE policy<{'ppc64el': 'y'}> +CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING policy<{'amd64': 'y', 'arm64-generic': 'y', 'riscv64': 'y'}> +CONFIG_HVCS policy<{'ppc64el': 'm'}> +CONFIG_HVC_CONSOLE policy<{'ppc64el': 'y'}> +CONFIG_HVC_DCC policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_HVC_DRIVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HVC_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_HVC_IUCV policy<{'s390x': 'y'}> +CONFIG_HVC_OLD_HVSI policy<{'ppc64el': 'y'}> +CONFIG_HVC_OPAL policy<{'ppc64el': 'y'}> +CONFIG_HVC_RTAS policy<{'ppc64el': 'y'}> +CONFIG_HVC_XEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_HVC_XEN_FRONTEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_HV_PERF_CTRS policy<{'ppc64el': 'y'}> +CONFIG_HWLAT_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HWMON_DEBUG_CHIP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_HWMON_VID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HWPOISON_INJECT policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm'}> +CONFIG_HWSPINLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_HWSPINLOCK_OMAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HWSPINLOCK_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HWSPINLOCK_SPRD policy<{'arm64': 'm'}> +CONFIG_HWSPINLOCK_SUN6I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_HW_PERF_EVENTS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HW_RANDOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HW_RANDOM_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_AMD policy<{'amd64': 'm'}> +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_ATMEL policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_BA431 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_HW_RANDOM_CAVIUM policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_CCTRNG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_HW_RANDOM_CN10K policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_EXYNOS policy<{'armhf': 'n'}> +CONFIG_HW_RANDOM_HISI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_HISTB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_IMX_RNGC policy<{'armhf': 'm'}> +CONFIG_HW_RANDOM_INTEL policy<{'amd64': 'm'}> +CONFIG_HW_RANDOM_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_OMAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_HW_RANDOM_POLARFIRE_SOC policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_HW_RANDOM_PSERIES policy<{'ppc64el': 'm'}> +CONFIG_HW_RANDOM_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_HW_RANDOM_S390 policy<{'s390x': 'm'}> +CONFIG_HW_RANDOM_STM32 policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_TIMERIOMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HW_RANDOM_TPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_HW_RANDOM_VIA policy<{'amd64': 'm'}> +CONFIG_HW_RANDOM_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_HW_RANDOM_XGENE policy<{'arm64': 'm'}> +CONFIG_HW_RANDOM_XIPHERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_HX711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HX9023S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_HYPERV policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_HYPERVISOR_GUEST policy<{'amd64': 'y'}> +CONFIG_HYPERV_BALLOON policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_IOMMU policy<{'amd64': 'y'}> +CONFIG_HYPERV_KEYBOARD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_NET policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_STORAGE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_TESTING policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_HYPERV_TIMER policy<{'amd64': 'y'}> +CONFIG_HYPERV_UTILS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_VMBUS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_HYPERV_VTL_MODE policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_HZ policy<{'amd64': '1000', 'arm64': '1000', 'armhf': '250', 'ppc64el': '250', 'riscv64': '250', 's390x': '100'}> +CONFIG_HZ_200 policy<{'armhf': 'n'}> +CONFIG_HZ_300 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_HZ_500 policy<{'armhf': 'n'}> +CONFIG_HZ_FIXED policy<{'armhf': '0'}> +CONFIG_HZ_PERIODIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_I2CR_SCOM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ALGOBIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALGOPCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ALI1535 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALI1563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALI15X3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ALTERA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_AMD756 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_AMD8111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_AMD_ASF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_AMD_MP2 policy<{'amd64': 'm', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_I2C_APPLE policy<{'arm64': 'm'}> +CONFIG_I2C_ARB_GPIO_CHALLENGE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ASPEED policy<{'armhf': 'm'}> +CONFIG_I2C_AT91 policy<{'arm64': 'm'}> +CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL policy<{'arm64': 'n'}> +CONFIG_I2C_ATR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_AXXIA policy<{'armhf': 'm'}> +CONFIG_I2C_BOARDINFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_I2C_CADENCE policy<{'arm64': 'n', 'riscv64': 'm'}> +CONFIG_I2C_CBUS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_CCGX_UCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_CGBC policy<{'amd64': 'm'}> +CONFIG_I2C_CHT_WC policy<{'amd64': 'm'}> +CONFIG_I2C_CP2615 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_CROS_EC_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_DEBUG_ALGO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C_DEBUG_BUS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C_DEBUG_CORE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_I2C_DEMUX_PINCTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_DESIGNWARE_AMDISP policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_DESIGNWARE_BAYTRAIL policy<{'amd64': 'y'}> +CONFIG_I2C_DESIGNWARE_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_I2C_DESIGNWARE_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_DESIGNWARE_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_I2C_DIOLAN_U2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_EMEV2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_I2C_EXYNOS5 policy<{'armhf': 'n'}> +CONFIG_I2C_FSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_GPIO_FAULT_INJECTOR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_I2C_GXP policy<{'armhf': 'm'}> +CONFIG_I2C_HELPER_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_I2C_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_OF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_OF_ELAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HID_OF_GOODIX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_HISI policy<{'arm64': 'm'}> +CONFIG_I2C_HIX5HD2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_I801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_I801_MUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_I2C_IMX policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_I2C_IMX_LPI2C policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_ISCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_ISMT policy<{'amd64': 'm'}> +CONFIG_I2C_KEBA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_I2C_KEMPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_MLXBF policy<{'arm64': 'm'}> +CONFIG_I2C_MLXCPLD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_I2C_MPC policy<{'ppc64el': 'm'}> +CONFIG_I2C_MT65XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_MT7621 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_I2C_MUX_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_GPMUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MUX_LTC4306 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_MLXCPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_MULE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MUX_PCA9541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_PCA954x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MUX_PINCTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_MUX_REG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_MV64XXX policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_I2C_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_NFORCE2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_NOMADIK policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_I2C_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_NVIDIA_GPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_OCORES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_OMAP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_I2C_OPAL policy<{'ppc64el': 'y'}> +CONFIG_I2C_OWL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_PCA_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_PIIX4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_PXA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_PXA_SLAVE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_I2C_QCOM_CCI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_QCOM_GENI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_QUP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_RIIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_RK3X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_ROBOTFUZZ_OSIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_RZV2M policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_S3C2410 policy<{'armhf': 'n'}> +CONFIG_I2C_SCMI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SH_MOBILE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_SI470X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SIMTEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_SIS5595 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_SIS630 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_SIS96X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_SLAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_I2C_SLAVE_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SLAVE_TESTUNIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_SPRD policy<{'arm64': 'y'}> +CONFIG_I2C_STM32F4 policy<{'arm64': 'm'}> +CONFIG_I2C_STM32F7 policy<{'arm64': 'm'}> +CONFIG_I2C_STUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_I2C_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_I2C_TAOS_EVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_TEGRA_BPMP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_THUNDERX policy<{'arm64': 'm'}> +CONFIG_I2C_TINY_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_USBIO policy<{'amd64': 'm', 'arm64': '-', 'riscv64': '-'}> +CONFIG_I2C_VERSATILE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_I2C_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_VIAPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I2C_VIPERBOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_I2C_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_XGENE_SLIMPRO policy<{'arm64': 'm'}> +CONFIG_I2C_XILINX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I2C_XLP9XX policy<{'arm64': 'm'}> +CONFIG_I2C_ZHAOXIN policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I3C_OR_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_I40E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I40EVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_I40E_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_I6300ESB_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_I82092 policy<{'amd64': 'm'}> +CONFIG_I8253_LOCK policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_I8254 policy<{'amd64': 'm'}> +CONFIG_I8K policy<{'amd64': 'y'}> +CONFIG_IA32_EMULATION policy<{'amd64': 'y'}> +CONFIG_IA32_EMULATION_DEFAULT_DISABLED policy<{'amd64': 'n'}> +CONFIG_IA32_FEAT_CTL policy<{'amd64': 'y'}> +CONFIG_IAQCORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IAVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IB700_WDT policy<{'amd64': 'm'}> +CONFIG_IBMASR policy<{'amd64': 'm'}> +CONFIG_IBMVETH policy<{'ppc64el': 'm'}> +CONFIG_IBMVIO policy<{'ppc64el': 'y'}> +CONFIG_IBMVMC policy<{'ppc64el': 'm'}> +CONFIG_IBM_ASM policy<{'amd64': 'm'}> +CONFIG_IBM_BSR policy<{'ppc64el': 'm'}> +CONFIG_IBM_PARTITION policy<{'s390x': 'y'}> +CONFIG_IBM_RTL policy<{'amd64': 'm'}> +CONFIG_ICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ICE_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ICE_HWTS policy<{'amd64': 'y'}> +CONFIG_ICE_SWITCHDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ICP10100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ICPLUS_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ICS932S401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IDEAPAD_LAPTOP policy<{'amd64': 'm'}> +CONFIG_IDLE_INJECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IDPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IDPF_SINGLEQ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IE6XX_WDT policy<{'amd64': 'm'}> +CONFIG_IEEE802154 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IEEE802154_6LOWPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_ADF7242 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_AT86RF230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_ATUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_CA8210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_CA8210_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IEEE802154_CC2520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_FAKELB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_HWSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_MCR20A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_MRF24J40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IEEE802154_NL802154_EXPERIMENTAL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IEEE802154_SOCKET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IFB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IFCVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IGB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IGBVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IGB_DCA policy<{'amd64': 'y'}> +CONFIG_IGB_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IGC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IGC_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IGH_ECAT_ENABLE_EOE policy<{'amd64': 'y', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_IGH_ECAT_GENERIC_DEVICE policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_IIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IIO_ADC_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ADIS_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ADIS_LIB_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IIO_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IIO_BUFFER_CB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER_DMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER_DMAENGINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_BUFFER_HW_CONSUMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_CONFIGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_CONSUMERS_PER_TRIGGER policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_IIO_CROS_EC_ACCEL_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_ACTIVITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_BARO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_LIGHT_PROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_GTS_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_HRTIMER_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_INTERRUPT_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_INV_SENSORS_TIMESTAMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KFIFO_BUF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KX022A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KX022A_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_KX022A_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_MS_SENSORS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_RESCALE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IIO_SIMPLE_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SSP_SENSORHUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SSP_SENSORS_COMMONS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_STM32_LPTIMER_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_STM32_TIMER_TRIGGER policy<{'arm64': 'm'}> +CONFIG_IIO_ST_ACCEL_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_ACCEL_I2C_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_ACCEL_SPI_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_GYRO_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_GYRO_I2C_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_GYRO_SPI_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM6DSX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM9DS0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM9DS0_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_LSM9DS0_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_MAGN_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_MAGN_I2C_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_MAGN_SPI_3AXIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_PRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_PRESS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_PRESS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_SENSORS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_SENSORS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_ST_SENSORS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SW_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SW_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_SYSFS_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_TIGHTLOOP_TRIGGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_TRIGGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IIO_TRIGGERED_BUFFER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IIO_TRIGGERED_EVENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IKCONFIG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IKHEADERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ILLEGAL_POINTER_VALUE policy<{'amd64': '0xdead000000000000', 'arm64': '0xdead000000000000', 'ppc64el': '0x5deadbeef0000000', 'riscv64': '0xdead000000000000', 's390x': '0xdead000000000000'}> +CONFIG_IMA_APPRAISE_BOOTPARAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_APPRAISE_BUILD_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_APPRAISE_MODSIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_BLACKLIST_KEYRING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_DEFAULT_HASH policy<{'amd64': '"sha256"', 'arm64': '"sha256"', 'armhf': '"sha256"', 'ppc64el': '"sha256"', 'riscv64': '"sha256"', 's390x': '"sha256"'}> +CONFIG_IMA_DEFAULT_HASH_SHA1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_DEFAULT_HASH_SHA512 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_DEFAULT_TEMPLATE policy<{'amd64': '"ima-ng"', 'arm64': '"ima-ng"', 'armhf': '"ima-ng"', 'ppc64el': '"ima-sig"', 'riscv64': '"ima-ng"', 's390x': '"ima-ng"'}> +CONFIG_IMA_DISABLE_HTABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_KEXEC_EXTRA_MEMORY_KB policy<{'amd64': '0', 'arm64': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_IMA_LOAD_X509 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IMA_LSM_RULES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_MEASURE_PCR_IDX policy<{'amd64': '10', 'arm64': '10', 'armhf': '10', 'ppc64el': '10', 'riscv64': '10', 's390x': '10'}> +CONFIG_IMA_NG_TEMPLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_IMG_ASCII_LCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IMX2_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX7D_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX7ULP_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX8MM_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX8M_BLK_CTRL policy<{'arm64': 'y'}> +CONFIG_IMX8QXP_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX91_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX93_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX9_BLK_CTRL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_AIPSTZ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_DSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_DSP_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_GPCV2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_GPCV2_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_INTMUX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_IPUV3_CORE policy<{'armhf': 'm'}> +CONFIG_IMX_IRQSTEER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_MU_MSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_BBM_EXT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_SCMI_CPU_DRV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_CPU_EXT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_LMM_DRV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_LMM_EXT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCMI_MISC_DRV policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_IMX_SCMI_MISC_EXT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_SCU_PD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IMX_SC_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SC_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_SDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IMX_WEIM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INA2XX_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INDIRECT_PIO policy<{'arm64': 'y'}> +CONFIG_INET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET6_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_ESPINTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET6_ESP_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET6_XFRM_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_DIAG_DESTROY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_ESPINTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INET_ESP_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_MPTCP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_PSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INET_RAW_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_SCTP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_TABLE_PERTURB_ORDER policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16', 's390x': '16'}> +CONFIG_INET_TCP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_UDP_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INET_XFRM_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINEON_TLV493D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_ADDR_TRANS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_BNG_RE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_BNXT_RE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_CXGB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_EFA policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_ERDMA policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INFINIBAND_HFI1 policy<{'amd64': 'm'}> +CONFIG_INFINIBAND_HNS_HIP08 policy<{'arm64': 'm'}> +CONFIG_INFINIBAND_IONIC policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_IPOIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_IPOIB_CM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_IPOIB_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INFINIBAND_IRDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_ISER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_ISERT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_MTHCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_MTHCA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INFINIBAND_OCRDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INFINIBAND_ON_DEMAND_PAGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_OPA_VNIC policy<{'amd64': 'm'}> +CONFIG_INFINIBAND_QEDR policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INFINIBAND_RDMAVT policy<{'amd64': 'm'}> +CONFIG_INFINIBAND_RTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_RTRS_CLIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_RTRS_SERVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_SRP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_SRPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_USER_ACCESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_USER_MAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INFINIBAND_USER_MEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_USNIC policy<{'amd64': 'm'}> +CONFIG_INFINIBAND_VIRT_DMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INFINIBAND_VMWARE_PVRDMA policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INFTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INITRAMFS_PRESERVE_MTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INITRAMFS_SOURCE policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_INIT_ENV_ARG_LIMIT policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32', 's390x': '32'}> +CONFIG_INIT_ON_ALLOC_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INIT_ON_FREE_DEFAULT_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INIT_STACK_ALL_PATTERN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INIT_STACK_ALL_ZERO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INIT_STACK_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INLINE_READ_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK_IRQ policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_READ_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_TRYLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_SPIN_UNLOCK_IRQ policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_TRYLOCK policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK_BH policy<{'s390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK_IRQ policy<{'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': 'y'}> +CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE policy<{'s390x': 'y'}> +CONFIG_INOTIFY_USER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INPUT_88PM80X_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_88PM860X_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_88PM886_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AD714X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_AD714X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AD714X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ADXL34X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_ADXL34X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ADXL34X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_APANEL policy<{'amd64': 'm'}> +CONFIG_INPUT_ARIEL_PWRBUTTON policy<{'armhf': 'm'}> +CONFIG_INPUT_ARIZONA_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ATC260X_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_ATI_REMOTE2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_ATLAS_BTNS policy<{'amd64': 'm'}> +CONFIG_INPUT_ATMEL_CAPTOUCH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AW86927 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_AXP20X_PEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_BBNSM_PWRKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_BMA150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_CM109 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_CMA3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_CMA3000_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_CPCAP_PWRBUTTON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_CS40L50_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_DA7280_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DA9052_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DA9055_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DA9063_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DRV260X_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DRV2665_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_DRV2667_HAPTICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_E3X0_BUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_EVDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INPUT_FF_MEMLESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_GPIO_BEEPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_GPIO_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_GPIO_ROTARY_ENCODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_GPIO_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_HISI_POWERKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_IBM_PANEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_IDEAPAD_SLIDEBAR policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_INPUT_IMS_PCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_IQS269A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_IQS626A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_IQS7222 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_JOYDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_JOYSTICK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_KEYBOARD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_KEYSPAN_REMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_KXTJ9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_LEDS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MATRIXKMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_MAX7360_ROTARY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_MAX77650_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_MAX77693_HAPTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MAX8925_ONKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MAX8997_HAPTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MC13783_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_MISC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_MMA8450 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_MOUSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_MOUSEDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_MOUSEDEV_PSAUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INPUT_MOUSEDEV_SCREEN_X policy<{'amd64': '1024', 'arm64': '1024', 'armhf': '1024', 'ppc64el': '1024', 'riscv64': '1024'}> +CONFIG_INPUT_MOUSEDEV_SCREEN_Y policy<{'amd64': '768', 'arm64': '768', 'armhf': '768', 'ppc64el': '768', 'riscv64': '768'}> +CONFIG_INPUT_PALMAS_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PCF8574 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PCSPKR policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_INPUT_PF1550_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_PM8941_PWRKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_PM8XXX_VIBRATOR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INPUT_PMIC8XXX_PWRKEY policy<{'armhf': 'm'}> +CONFIG_INPUT_POWERMATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PWM_BEEPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_PWM_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_QNAP_MCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_RAVE_SP_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_REGULATOR_HAPTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_RETU_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_RK805_PWRKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_RT5120_PWRKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_SC27XX_VIBRA policy<{'arm64': 'm'}> +CONFIG_INPUT_SOC_BUTTON_ARRAY policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_SPARSEKMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_INPUT_STPMIC1_ONKEY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TABLET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_TOUCHSCREEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INPUT_TPS65218_PWRBUTTON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TPS65219_PWRBUTTON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TPS6594_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INPUT_TWL4030_PWRBUTTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_TWL4030_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_TWL6040_VIBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_VIVALDIFMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INPUT_WM831X_ON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INPUT_XEN_KBDDEV_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_INPUT_YEALINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INSPUR_PLATFORM_PROFILE policy<{'amd64': 'm'}> +CONFIG_INSTRUCTION_DECODER policy<{'amd64': 'y'}> +CONFIG_INT3406_THERMAL policy<{'amd64': 'm'}> +CONFIG_INT340X_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEGRITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_ASYMMETRIC_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_AUDIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_CA_MACHINE_KEYRING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_INTEGRITY_CA_MACHINE_KEYRING_MAX policy<{'ppc64el': 'y'}> +CONFIG_INTEGRITY_MACHINE_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INTEGRITY_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEGRITY_TRUSTED_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTEL_ATOMISP2_LED policy<{'amd64': 'm'}> +CONFIG_INTEL_ATOMISP2_PDX86 policy<{'amd64': 'y'}> +CONFIG_INTEL_BXTWC_PMIC_TMU policy<{'amd64': 'm'}> +CONFIG_INTEL_BXT_PMIC_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEL_BYTCRC_PWRSRC policy<{'amd64': 'm'}> +CONFIG_INTEL_CHTDC_TI_PWRBTN policy<{'amd64': 'm'}> +CONFIG_INTEL_CHTWC_INT33FE policy<{'amd64': 'm'}> +CONFIG_INTEL_DC_TI_ADC policy<{'amd64': 'm'}> +CONFIG_INTEL_EHL_PSE_IO policy<{'amd64': 'm'}> +CONFIG_INTEL_GTT policy<{'amd64': 'y'}> +CONFIG_INTEL_HFI_THERMAL policy<{'amd64': 'y'}> +CONFIG_INTEL_HID_EVENT policy<{'amd64': 'm'}> +CONFIG_INTEL_IDLE policy<{'amd64': 'y'}> +CONFIG_INTEL_IDMA64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INTEL_IDXD policy<{'amd64': 'm'}> +CONFIG_INTEL_IDXD_BUS policy<{'amd64': 'm'}> +CONFIG_INTEL_IDXD_COMPAT policy<{'amd64': 'n'}> +CONFIG_INTEL_IDXD_PERFMON policy<{'amd64': 'y'}> +CONFIG_INTEL_IDXD_SVM policy<{'amd64': 'y'}> +CONFIG_INTEL_IFS policy<{'amd64': 'm'}> +CONFIG_INTEL_INT0002_VGPIO policy<{'amd64': 'm'}> +CONFIG_INTEL_IOATDMA policy<{'amd64': 'm'}> +CONFIG_INTEL_IOMMU policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_FLOPPY_WA policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_PERF_EVENTS policy<{'amd64': 'y'}> +CONFIG_INTEL_IOMMU_SVM policy<{'amd64': 'y'}> +CONFIG_INTEL_IPS policy<{'amd64': 'm'}> +CONFIG_INTEL_ISHTP_ECLITE policy<{'amd64': 'm'}> +CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER policy<{'amd64': 'm'}> +CONFIG_INTEL_ISH_HID policy<{'amd64': 'm'}> +CONFIG_INTEL_LDMA policy<{'amd64': 'y'}> +CONFIG_INTEL_MEI policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm', 's390x': '-'}> +CONFIG_INTEL_MEI_GSC policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_GSC_PROXY policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_HDCP policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_LB policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_ME policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_PXP policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_TXE policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_VSC policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_VSC_HW policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'riscv64': 'm'}> +CONFIG_INTEL_MEI_WDT policy<{'amd64': 'm'}> +CONFIG_INTEL_MRFLD_ADC policy<{'amd64': 'm'}> +CONFIG_INTEL_MRFLD_PWRBTN policy<{'amd64': 'm'}> +CONFIG_INTEL_OAKTRAIL policy<{'amd64': 'm'}> +CONFIG_INTEL_OC_WATCHDOG policy<{'amd64': 'm'}> +CONFIG_INTEL_PCH_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEL_PLR_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_PMC_CORE policy<{'amd64': 'm'}> +CONFIG_INTEL_PMC_SSRAM_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_CLASS policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_CRASHLOG policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_DISCOVERY policy<{'amd64': 'm'}> +CONFIG_INTEL_PMT_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_INTEL_POWERCLAMP policy<{'amd64': 'm'}> +CONFIG_INTEL_PUNIT_IPC policy<{'amd64': 'm'}> +CONFIG_INTEL_QEP policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_INTEL_QUICKI2C policy<{'amd64': 'm'}> +CONFIG_INTEL_QUICKSPI policy<{'amd64': 'm'}> +CONFIG_INTEL_RAPL policy<{'amd64': 'm'}> +CONFIG_INTEL_RAPL_CORE policy<{'amd64': 'm'}> +CONFIG_INTEL_RAPL_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_RST policy<{'amd64': 'm'}> +CONFIG_INTEL_SAR_INT1092 policy<{'amd64': 'm'}> +CONFIG_INTEL_SCU policy<{'amd64': 'y'}> +CONFIG_INTEL_SCU_IPC policy<{'amd64': 'y'}> +CONFIG_INTEL_SCU_IPC_UTIL policy<{'amd64': 'm'}> +CONFIG_INTEL_SCU_PCI policy<{'amd64': 'y'}> +CONFIG_INTEL_SCU_PLATFORM policy<{'amd64': 'm'}> +CONFIG_INTEL_SDSI policy<{'amd64': 'm'}> +CONFIG_INTEL_SKL_INT3472 policy<{'amd64': 'm'}> +CONFIG_INTEL_SMARTCONNECT policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_DTS_IOSF_CORE policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_DTS_THERMAL policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_PMIC policy<{'amd64': 'y'}> +CONFIG_INTEL_SOC_PMIC_BXTWC policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_PMIC_CHTDC_TI policy<{'amd64': 'm'}> +CONFIG_INTEL_SOC_PMIC_CHTWC policy<{'amd64': 'y'}> +CONFIG_INTEL_SOC_PMIC_MRFLD policy<{'amd64': 'm'}> +CONFIG_INTEL_SPEED_SELECT_INTERFACE policy<{'amd64': 'm'}> +CONFIG_INTEL_SPEED_SELECT_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_STRATIX10_RSU policy<{'arm64': 'm'}> +CONFIG_INTEL_STRATIX10_SERVICE policy<{'arm64': 'm'}> +CONFIG_INTEL_TCC policy<{'amd64': 'y'}> +CONFIG_INTEL_TCC_COOLING policy<{'amd64': 'm'}> +CONFIG_INTEL_TDX_GUEST policy<{'amd64': 'y'}> +CONFIG_INTEL_TDX_HOST policy<{'amd64': 'y'}> +CONFIG_INTEL_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_INTEL_TH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_THC_HID policy<{'amd64': 'm'}> +CONFIG_INTEL_TH_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_INTEL_TH_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INTEL_TH_GTH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_MSU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_PTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TH_STH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTEL_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_TPMI_POWER_DOMAINS policy<{'amd64': 'm'}> +CONFIG_INTEL_TURBO_MAX_3 policy<{'amd64': 'y'}> +CONFIG_INTEL_TXT policy<{'amd64': 'y'}> +CONFIG_INTEL_UNCORE_FREQ_CONTROL policy<{'amd64': 'm'}> +CONFIG_INTEL_UNCORE_FREQ_CONTROL_TPMI policy<{'amd64': 'm'}> +CONFIG_INTEL_VBTN policy<{'amd64': 'm'}> +CONFIG_INTEL_VSC policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'riscv64': 'm'}> +CONFIG_INTEL_VSEC policy<{'amd64': 'm'}> +CONFIG_INTEL_WMI policy<{'amd64': 'y'}> +CONFIG_INTEL_WMI_SBL_FW_UPDATE policy<{'amd64': 'm'}> +CONFIG_INTEL_WMI_THUNDERBOLT policy<{'amd64': 'm'}> +CONFIG_INTEL_XWAY_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_INTERCONNECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_INTERCONNECT_CLK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_IMX8MQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_MTK_DVFSRC_EMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8183 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8195 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_MTK_MT8196 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_BCM_VOTER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_GLYMUR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_KAANAPALI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MILOS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_MSM8909 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8937 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8939 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8953 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8974 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8976 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_MSM8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_OSM_L3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCM2290 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS615 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QCS8300 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_QDU1000 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_RPMH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_RPMH_POSSIBLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_INTERCONNECT_QCOM_SA8775P policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SAR2130P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC7180 policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC7280 policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC8180X policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SC8280XP policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM660 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM670 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDM845 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDX55 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDX65 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SDX75 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM6115 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM6350 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM7150 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8150 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8250 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8350 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8450 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8550 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8650 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SM8750 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_QCOM_X1E80100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_INTERCONNECT_SAMSUNG policy<{'armhf': 'n'}> +CONFIG_INTERRUPT_CNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INTERRUPT_SANITIZE_REGISTERS policy<{'ppc64el': 'y'}> +CONFIG_INTERVAL_TREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_INTERVAL_TREE_SPAN_ITER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_INTERVAL_TREE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_INV_ICM42600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM42600_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM42600_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_ICM45600_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_MPU6050_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_MPU6050_IIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_INV_MPU6050_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IOMMUFD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IOMMUFD_DRIVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IOMMUFD_DRIVER_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IOMMU_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IOMMU_DEBUG policy<{'amd64': 'n'}> +CONFIG_IOMMU_DEFAULT_PASSTHROUGH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IOMMU_DMA policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_IOMMU_HELPER policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_IOMMU_IOPF policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_IOMMU_IOVA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'y'}> +CONFIG_IOMMU_IO_PGTABLE policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_IOMMU_IO_PGTABLE_ARMV7S policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST policy<{'arm64': 'n'}> +CONFIG_IOMMU_IO_PGTABLE_DART policy<{'arm64': 'y'}> +CONFIG_IOMMU_IO_PGTABLE_LPAE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IOMMU_MM_DATA policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_IOMMU_PT policy<{'amd64': 'y'}> +CONFIG_IOMMU_PT_AMDV1 policy<{'amd64': 'y'}> +CONFIG_IOMMU_PT_VTDSS policy<{'amd64': 'y'}> +CONFIG_IOMMU_PT_X86_64 policy<{'amd64': 'y'}> +CONFIG_IOMMU_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IOMMU_SVA policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_IONIC policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IOSCHED_BFQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IOSF_MBI policy<{'amd64': 'y'}> +CONFIG_IOSF_MBI_DEBUG policy<{'amd64': 'y'}> +CONFIG_IOSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IO_DELAY_0X80 policy<{'amd64': 'n'}> +CONFIG_IO_DELAY_0XED policy<{'amd64': 'y'}> +CONFIG_IO_DELAY_NONE policy<{'amd64': 'n'}> +CONFIG_IO_DELAY_UDELAY policy<{'amd64': 'n'}> +CONFIG_IO_EVENT_IRQ policy<{'ppc64el': 'y'}> +CONFIG_IO_STRICT_DEVMEM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IO_URING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IO_URING_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IO_URING_MOCK_FILE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IO_URING_ZCRX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IO_WQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP5XXX_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IP6_NF_FILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_IPTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_IPTABLES_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_EUI64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_FRAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_IPV6HEADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_MH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_OPTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_RPFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_RT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_MATCH_SRH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_SECURITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_MASQUERADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_NPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP6_NF_TARGET_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPACK_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IPC_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_BOOT_POLICY policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_IPE_POLICY_SIG_PLATFORM_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_POLICY_SIG_SECONDARY_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_DM_VERITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_DM_VERITY_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_FS_VERITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPE_PROP_FS_VERITY_BUILTIN_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPMB_DEVICE_INTERFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_DEVICE_INTERFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_DMI_DECODE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_IPMI_HANDLER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IPMI_IPMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_KCS_BMC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPMI_KCS_BMC_CDEV_IPMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPMI_KCS_BMC_SERIO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPMI_PANIC_EVENT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_IPMI_PLAT_DATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPMI_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_IPMI_POWEROFF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_SI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_SSIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPMI_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPQ_APSS_5424 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_APSS_6018 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_APSS_PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_CMN_PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_4019 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_5018 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_5332 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_5424 policy<{'arm64': 'm'}> +CONFIG_IPQ_GCC_6018 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_806X policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_IPQ_GCC_8074 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_GCC_9574 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPQ_LCC_806X policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_IPQ_NSSCC_5424 policy<{'arm64': 'm'}> +CONFIG_IPQ_NSSCC_9574 policy<{'arm64': 'm'}> +CONFIG_IPQ_NSSCC_QCA8K policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IPU_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IPV6_FOU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_FOU_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_GRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_ILA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_IOAM6_LWTUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_MIP6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_MROUTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_NDISC_NODETYPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_OPTIMISTIC_DAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_PIMSM_V2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_ROUTER_PREF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_ROUTE_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_RPL_LWTUNNEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IPV6_SEG6_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SEG6_HMAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SEG6_LWTUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_SIT_6RD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_SUBTREES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPV6_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPV6_VTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPVLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPVLAN_L3S policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IPVTAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IPW2100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPW2100_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IPW2100_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IPW2200_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IPW2200_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200_PROMISCUOUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200_QOS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPW2200_RADIOTAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IPWIRELESS policy<{'amd64': 'm'}> +CONFIG_IP_ADVANCED_ROUTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_FIB_TRIE_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MROUTE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MROUTE_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MROUTE_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MULTICAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_MULTIPLE_TABLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_NF_ARPFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_ARPTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_ARP_MANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_FILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_IPTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_IPTABLES_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MANGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_ECN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_RPFILTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_MATCH_TTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_SECURITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_ECN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_MASQUERADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_NETMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_REDIRECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_NF_TARGET_TTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_PIMSM_V1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_PIMSM_V2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_ROUTE_CLASSID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_ROUTE_MULTIPATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_ROUTE_VERBOSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_SCTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_BITMAP_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_BITMAP_IPMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_BITMAP_PORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPPORTIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_IPPORTNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_MAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETIFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_HASH_NETPORTNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_LIST_SET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_SET_MAX policy<{'amd64': '256', 'arm64': '256', 'armhf': '256', 'ppc64el': '256', 'riscv64': '256', 's390x': '256'}> +CONFIG_IP_VS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IP_VS_DH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_FO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_FTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_LBLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_LBLCR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_LC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_MH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_MH_TAB_INDEX policy<{'amd64': '12', 'arm64': '12', 'armhf': '12', 'ppc64el': '12', 'riscv64': '12', 's390x': '12'}> +CONFIG_IP_VS_NFCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_NQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_OVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_PE_SIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_PROTO_AH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_AH_ESP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_ESP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_SCTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_TCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_PROTO_UDP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IP_VS_RR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_SED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_SH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_SH_TAB_BITS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8', 's390x': '8'}> +CONFIG_IP_VS_TAB_BITS policy<{'amd64': '12', 'arm64': '12', 'armhf': '12', 'ppc64el': '12', 'riscv64': '12', 's390x': '12'}> +CONFIG_IP_VS_TWOS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_IP_VS_WLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IP_VS_WRR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IQS620AT_TEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IQS621_ALS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IQS624_POS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IRQCHIP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IRQSOFF_TRACER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_IRQSTACKS policy<{'armhf': 'y'}> +CONFIG_IRQ_ALL_CPUS policy<{'ppc64el': 'y'}> +CONFIG_IRQ_BYPASS_MANAGER policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IRQ_CROSSBAR policy<{'armhf': 'y'}> +CONFIG_IRQ_DOMAIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_DOMAIN_HIERARCHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_IRQ_FORCED_THREADING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IRQ_MSI_IOMMU policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 's390x': '-'}> +CONFIG_IRQ_MSI_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_POLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_REMAP policy<{'amd64': 'y'}> +CONFIG_IRQ_SIM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRQ_STACKS policy<{'riscv64': 'y'}> +CONFIG_IRQ_TIME_ACCOUNTING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IRQ_WORK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_IRSD200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_ENE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_FINTEK policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_GPIO_CIR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_GPIO_TX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_HIX5HD2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IGORPLUGUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IGUANA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IMON_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_IMON_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_ITE_CIR policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_JVC_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_MCEUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_MCE_KBD_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IR_MESON_TX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IR_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_IR_NEC_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_NUVOTON policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_IR_PWM_TX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_RC5_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_RC6_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_RCMM_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_REDRAT3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SANYO_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SERIAL_TRANSMITTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IR_SHARP_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SONY_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_STREAMZAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_SUNXI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_IR_TOY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_TTUSBIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IR_WINBOND_CIR policy<{'amd64': 'm'}> +CONFIG_IR_XMP_DECODER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISA_BUS policy<{'amd64': 'y'}> +CONFIG_ISA_BUS_API policy<{'amd64': 'y'}> +CONFIG_ISA_DMA_API policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_ISCSI_BOOT_SYSFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ISCSI_IBFT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_ISCSI_IBFT_FIND policy<{'amd64': 'y'}> +CONFIG_ISCSI_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ISCSI_TARGET_CXGB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISCSI_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ISDN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ISDN_CAPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ISL29003 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ISL29020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ISL29125 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISL29501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISL76682 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ISM policy<{'s390x': 'm'}> +CONFIG_ISO9660_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_IT8712F_WDT policy<{'amd64': 'm'}> +CONFIG_IT87_WDT policy<{'amd64': 'm'}> +CONFIG_ITCO_WDT policy<{'amd64': 'm'}> +CONFIG_ITG3200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IUCV policy<{'s390x': 'y'}> +CONFIG_IWL3945 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWL4965 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLDVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLEGACY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IWLEGACY_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLMLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLMVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLWIFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_IWLWIFI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_IWLWIFI_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLWIFI_DEVICE_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLWIFI_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IWLWIFI_OPMODE_MODULAR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IXGBEVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_IXGBEVF_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE_DCA policy<{'amd64': 'y'}> +CONFIG_IXGBE_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_IXGBE_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JAILHOUSE_GUEST policy<{'amd64': 'y'}> +CONFIG_JBD2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_JBD2_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_JFFS2_CMODE_FAVOURLZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_CMODE_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_CMODE_PRIORITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_CMODE_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_COMPRESSION_OPTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JFFS2_FS_DEBUG policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_JFFS2_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS_WBUF_VERIFY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_FS_WRITEBUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_RTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFFS2_RUBIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_SUMMARY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFFS2_ZLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_JFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_JFS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JFS_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_JOLIET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_JOYSTICK_A3D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_ADI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_ANALOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_AS5011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_COBRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_DB9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_FSIA6B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GAMECON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_GF2K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GRIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GRIP_MP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_GUILLEMOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_IFORCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_IFORCE_232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_IFORCE_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_INTERACT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_JOYDUMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_MAGELLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_PSXPAD_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_PSXPAD_SPI_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JOYSTICK_PXRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_QWIIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_SEESAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_SENSEHAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_SIDEWINDER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_SPACEBALL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_SPACEORB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_STINGER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_TMDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_TURBOGRAFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_TWIDJOY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_WALKERA0701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JOYSTICK_WARRIOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_XPAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JOYSTICK_XPAD_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JOYSTICK_XPAD_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_JOYSTICK_ZHENHUA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_JSA1212 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_JUMP_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_JUMP_LABEL_FEATURE_CHECKS policy<{'ppc64el': 'y'}> +CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_K3_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_K3_RTI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_K3_THERMAL policy<{'arm64': 'm'}> +CONFIG_KALLSYMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KALLSYMS_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KALLSYMS_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KARMA_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_KASAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KCMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KCOV policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KCSAN policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_KDB_CONTINUE_CATASTROPHIC policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_KDB_DEFAULT_ENABLE policy<{'amd64': '0x1', 'arm64': '0x1', 'armhf': '0x1', 'ppc64el': '0x1', 'riscv64': '0x1'}> +CONFIG_KDB_KEYBOARD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KEBA_CP500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_KEBA_LAN9252 policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_KEEMBAY_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_KEMPLD_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KERNEL_BZIP2 policy<{'amd64': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_GZIP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KERNEL_IMAGE_BASE policy<{'s390x': '0x3FFE0000000'}> +CONFIG_KERNEL_LZ4 policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_LZMA policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_LZO policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_MODE_NEON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_KERNEL_NOBP policy<{'s390x': 'n'}> +CONFIG_KERNEL_START policy<{'ppc64el': '0xc000000000000000'}> +CONFIG_KERNEL_UNCOMPRESSED policy<{'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNEL_XZ policy<{'amd64': 'n', 'arm64': '-', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': '-', 's390x': 'n'}> +CONFIG_KERNFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_ELF policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KEXEC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_HANDOVER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KEXEC_HANDOVER_DEBUG policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_KEXEC_HANDOVER_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KEXEC_HANDOVER_ENABLE_DEFAULT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KEXEC_IMAGE_VERIFY_SIG policy<{'arm64': 'y'}> +CONFIG_KEXEC_JUMP policy<{'amd64': 'y'}> +CONFIG_KEXEC_SIG policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_KEXEC_SIG_FORCE policy<{'amd64': 'n'}> +CONFIG_KEYBOARD_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_ADP5588 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_APPLESPI policy<{'amd64': 'm'}> +CONFIG_KEYBOARD_ATKBD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KEYBOARD_BCM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_CAP11XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_CYPRESS_SF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_DLINK_DIR685 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_GOLDFISH_EVENTS policy<{'riscv64': 'm'}> +CONFIG_KEYBOARD_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_GPIO_POLLED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_IMX_BBM_SCMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_KEYBOARD_IMX_SC_KEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_IQS62X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_LKKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_LM8323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_LM8333 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MATRIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MAX7359 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_MPR121 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_MT6779 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_MTK_PMIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_NEWTON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_NVEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_OMAP4 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_OPENCORES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_PINEPHONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_PMIC8XXX policy<{'armhf': 'm'}> +CONFIG_KEYBOARD_PXA27x policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_QT1050 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_QT1070 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_QT2160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_SAMSUNG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_SNVS_PWRKEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_STMPE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_STOWAWAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_SUN4I_LRADC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_KEYBOARD_SUNKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_TC3589X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KEYBOARD_TCA8418 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KEYBOARD_TM2_TOUCHKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_TWL4030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYBOARD_XTKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEYS_REQUEST_CACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEY_DH_OPERATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KEY_NOTIFICATIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KFENCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KFENCE_DEFERRABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KFENCE_NUM_OBJECTS policy<{'amd64': '255', 'arm64': '255', 'armhf': '255', 'ppc64el': '255', 'riscv64': '255', 's390x': '255'}> +CONFIG_KFENCE_SAMPLE_INTERVAL policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_KFENCE_STRESS_TEST_FAULTS policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_KGDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_HONOUR_BLOCKLIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_KDB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_KGDB_LOW_LEVEL_TRAP policy<{'amd64': 'y'}> +CONFIG_KGDB_TESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_KHADAS_MCU_FAN_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KLP_BUILD policy<{'amd64': 'y'}> +CONFIG_KMAP_LOCAL policy<{'armhf': 'y'}> +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY policy<{'armhf': 'y'}> +CONFIG_KMX61 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KPROBES_ON_FTRACE policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': '-', 's390x': 'y'}> +CONFIG_KPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KPROBE_EVENTS_ON_NOTRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KPROBE_EVENT_GEN_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KPSS_XCC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_KRAITCC policy<{'armhf': 'm'}> +CONFIG_KRAIT_CLOCKS policy<{'armhf': 'y'}> +CONFIG_KRAIT_L2_ACCESSORS policy<{'armhf': 'y'}> +CONFIG_KRETPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KRETPROBE_ON_RETHOOK policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KS0108 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KS0108_DELAY policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_KS0108_PORT policy<{'amd64': '0x378', 'arm64': '0x378', 'armhf': '0x378', 'ppc64el': '0x378', 'riscv64': '0x378'}> +CONFIG_KS8842 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KS8851 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KS8851_MLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KSZ884X_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_KUNIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_KUNPENG_HCCS policy<{'arm64': 'm'}> +CONFIG_KUSER_HELPERS policy<{'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y'}> +CONFIG_KVFREE_RCU_BATCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KVM_AMD policy<{'amd64': 'm'}> +CONFIG_KVM_AMD_SEV policy<{'amd64': 'y'}> +CONFIG_KVM_ASYNC_PF policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_KVM_ASYNC_PF_SYNC policy<{'s390x': 'y'}> +CONFIG_KVM_BOOK3S_64 policy<{'ppc64el': 'm'}> +CONFIG_KVM_BOOK3S_64_HANDLER policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_64_HV policy<{'ppc64el': 'm'}> +CONFIG_KVM_BOOK3S_HANDLER policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_EXIT_TIMING policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_NESTED_PMU_WORKAROUND policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_P9_TIMING policy<{'ppc64el': 'y'}> +CONFIG_KVM_BOOK3S_HV_PMU policy<{'ppc64el': 'm'}> +CONFIG_KVM_BOOK3S_HV_POSSIBLE policy<{'ppc64el': 'y'}> +CONFIG_KVM_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_KVM_COMPAT policy<{'amd64': 'y'}> +CONFIG_KVM_ELIDE_TLB_FLUSH_IF_YOUNG policy<{'amd64': 'y'}> +CONFIG_KVM_EXTERNAL_WRITE_TRACKING policy<{'amd64': 'y'}> +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_KVM_GENERIC_HARDWARE_ENABLING policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES policy<{'amd64': 'y'}> +CONFIG_KVM_GENERIC_PRE_FAULT_MEMORY policy<{'amd64': 'y'}> +CONFIG_KVM_GUEST policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_KVM_GUEST_MEMFD policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_KVM_HYPERV policy<{'amd64': 'y'}> +CONFIG_KVM_INTEL policy<{'amd64': 'm'}> +CONFIG_KVM_INTEL_PROVE_VE policy<{'amd64': 'y'}> +CONFIG_KVM_INTEL_TDX policy<{'amd64': 'y'}> +CONFIG_KVM_IOAPIC policy<{'amd64': 'y'}> +CONFIG_KVM_MAX_NR_VCPUS policy<{'amd64': '4096'}> +CONFIG_KVM_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_KVM_MMU_LOCKLESS_AGING policy<{'amd64': 'y', 's390x': 'y'}> +CONFIG_KVM_PROVE_MMU policy<{'amd64': 'n'}> +CONFIG_KVM_S390_UCONTROL policy<{'s390x': 'n'}> +CONFIG_KVM_SMM policy<{'amd64': 'y'}> +CONFIG_KVM_SW_PROTECTED_VM policy<{'amd64': 'y'}> +CONFIG_KVM_VFIO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_KVM_WERROR policy<{'amd64': 'y'}> +CONFIG_KVM_X86 policy<{'amd64': 'm'}> +CONFIG_KVM_XEN policy<{'amd64': 'y'}> +CONFIG_KVM_XICS policy<{'ppc64el': 'y'}> +CONFIG_KVM_XIVE policy<{'ppc64el': 'y'}> +CONFIG_KXCJK1013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KXSD9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KXSD9_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_KXSD9_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_L2TP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_DEBUGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_IP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_L2TP_V3 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LAN743X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LAN865X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LAN966X_DCB policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LAN966X_OIC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LAN966X_SWITCH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LAN969X_SWITCH policy<{'arm64': 'y'}> +CONFIG_LAPB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LAPBETHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LATTICE_ECP3_CONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LCD2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LCD_AMS369FG06 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_CLASS_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LCD_HX8357 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_ILI922X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_ILI9320 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_L4F00242T03 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_LMS283GF05 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_LMS501KF03 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_LTV350QV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_OTM3225A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_TDO24M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LCD_VGG2432A4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LDISC_AUTOLOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LDM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_LDM_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION policy<{'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LD_HEAD_STUB_CATCH policy<{'ppc64el': 'n'}> +CONFIG_LD_IS_BFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LD_ORPHAN_WARN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LD_ORPHAN_WARN_LEVEL policy<{'amd64': '"warn"', 'arm64': '"warn"', 'armhf': '"warn"', 'ppc64el': '"warn"', 'riscv64': '"warn"', 's390x': '"warn"'}> +CONFIG_LD_VERSION policy<{'amd64': '24600', 'arm64': '24600', 'armhf': '24600', 'ppc64el': '24600', 'riscv64': '24600', 's390x': '24600'}> +CONFIG_LEDS_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_AAEON policy<{'amd64': 'm'}> +CONFIG_LEDS_AAT1290 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_ACER_A500 policy<{'armhf': 'm'}> +CONFIG_LEDS_ADP5520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_AN30259A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_APU policy<{'amd64': 'm'}> +CONFIG_LEDS_ARIEL policy<{'armhf': 'm'}> +CONFIG_LEDS_AS3645A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_AW200XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_AW2013 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BCM6328 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BCM6358 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BD2606MVV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_BD2802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_BLINKM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_BLINKM_MULTICOLOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_CHT_WCOVE policy<{'amd64': 'm'}> +CONFIG_LEDS_CLASS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_CLASS_FLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_CLASS_MULTICOLOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_CR0014114 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_LEDS_DA903X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_DAC124S085 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_EL15203000 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_EXPRESSWIRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_GROUP_MULTICOLOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_INTEL_SS4200 policy<{'amd64': 'm'}> +CONFIG_LEDS_IS31FL319X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_IS31FL32XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_KTD202X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_KTD2692 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM3530 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM355x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3601X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM36274 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM3642 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LM3692X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LM3697 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP3944 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP3952 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP50XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP5521 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5523 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5562 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5569 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP55XX_COMMON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP5812 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP8501 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_LP8860 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LP8864 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_LT3593 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_MAX5970 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX77693 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_MC13783 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MENF21BMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MLXCPLD policy<{'amd64': 'm'}> +CONFIG_LEDS_MLXREG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_MT6323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MT6360 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MT6370_FLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_MT6370_RGB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_NCP5623 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_NIC78BX policy<{'amd64': 'm'}> +CONFIG_LEDS_NS2 policy<{'armhf': 'm'}> +CONFIG_LEDS_OSRAM_AMS_AS3668 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_PCA9532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PCA9532_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_PCA955X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PCA955X_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_PCA963X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PCA995X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_PM8058 policy<{'armhf': 'm'}> +CONFIG_LEDS_POWERNV policy<{'ppc64el': 'm'}> +CONFIG_LEDS_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_PWM_MULTICOLOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_QCOM_FLASH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_LEDS_QCOM_LPG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_QNAP_MCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_REGULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_RT4505 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_RT8515 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SC27XX_BLTC policy<{'arm64': 'm'}> +CONFIG_LEDS_SGM3140 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC policy<{'amd64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_APOLLOLAKE policy<{'amd64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_LEDS_SIEMENS_SIMATIC_IPC_F7188X policy<{'amd64': 'm'}> +CONFIG_LEDS_SPI_BYTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_ST1202 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SUN50I_A100 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_LEDS_SY7802 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_SYSCON policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TCA6507 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TI_LMU_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TLC591XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TPS6105X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TPS6131X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TRIGGERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_ACTIVITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_BACKLIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_CAMERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_CPU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_DEFAULT_ON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_DISK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TRIGGER_HEARTBEAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_INPUT_EVENTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LEDS_TRIGGER_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_ONESHOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_PANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEDS_TRIGGER_PATTERN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_TIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_TRANSIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TRIGGER_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_TURRIS_OMNIA policy<{'armhf': 'm'}> +CONFIG_LEDS_UPBOARD policy<{'amd64': 'm'}> +CONFIG_LEDS_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_WM831X_STATUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LEDS_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LED_TRIGGER_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LEGACY_DIRECT_IO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LEGACY_PTYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LEGACY_VSYSCALL_NONE policy<{'amd64': 'n'}> +CONFIG_LEGACY_VSYSCALL_XONLY policy<{'amd64': 'y'}> +CONFIG_LENOVO_SE10_WDT policy<{'amd64': 'm'}> +CONFIG_LENOVO_SE30_WDT policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_CAMERA policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_CAPDATA policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_EVENTS policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_GAMEZONE policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_HELPERS policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_HOTKEY_UTILITIES policy<{'amd64': 'm'}> +CONFIG_LENOVO_WMI_TUNING policy<{'amd64': 'm'}> +CONFIG_LENOVO_YMC policy<{'amd64': 'm'}> +CONFIG_LG_LAPTOP policy<{'amd64': 'm'}> +CONFIG_LIBERTAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LIBERTAS_MESH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LIBERTAS_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_THINFIRM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_THINFIRM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LIBERTAS_THINFIRM_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBERTAS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBETH_XDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LIBFCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LIBFDT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LIBIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIE_ADMINQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIE_FWLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIPW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIBIPW_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_LIBNVDIMM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_LIBWX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIDAR_LITE_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LINEAR_RANGES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LINEDISP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIQUIDIO policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LIQUIDIO_CORE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIQUIDIO_VF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LIRC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LIST_HARDENED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LITEX policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LITEX_LITEETH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LITEX_SOC_CONTROLLER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LIVEPATCH policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_LIVEPATCH_64 policy<{'ppc64el': 'y'}> +CONFIG_LIVEUPDATE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_LIVEUPDATE_MEMFD policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_LIVEUPDATE_TEST policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_LKDTM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LLC2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LLD_VERSION policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_LMK04832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_LMP91000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LOAD_IPL_KEYS policy<{'s390x': 'y'}> +CONFIG_LOAD_UEFI_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_LOCALVERSION policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_LOCKD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LOCKDEP_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCKD_V4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCKUP_DETECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOCK_DEBUGGING_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_DOWN_IN_SECURE_BOOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_EVENT_COUNTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_MM_AND_FIND_VMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_SPIN_ON_OWNER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LOCK_STAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOCK_TORTURE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOGIG940_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGIRUMBLEPAD2_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGITECH_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGIWHEELS_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_LOGO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LOG_BUF_SHIFT policy<{'amd64': '18', 'arm64': '18', 'armhf': '17', 'ppc64el': '18', 'riscv64': '18', 's390x': '18'}> +CONFIG_LOG_CPU_MAX_BUF_SHIFT policy<{'amd64': '12', 'arm64': '12', 'armhf': '12', 'ppc64el': '12', 'riscv64': '12', 's390x': '12'}> +CONFIG_LOOPBACK_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LP8788_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LPARCFG policy<{'ppc64el': 'y'}> +CONFIG_LPC_ICH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LPC_SCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_LP_CONSOLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_LRU_CACHE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LRU_GEN_STATS policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LRU_GEN_WALKS_MMU policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_LSI_ET1011C_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LSM policy<{'amd64': '"landlock,lockdown,yama,integrity,apparmor"', 'arm64': '"landlock,lockdown,yama,integrity,apparmor"', 'armhf': '"landlock,lockdown,yama,integrity,apparmor"', 'ppc64el': '"landlock,lockdown,yama,integrity,apparmor"', 'riscv64': '"landlock,lockdown,yama,integrity,apparmor"', 's390x': '"landlock,lockdown,yama,integrity,apparmor"'}> +CONFIG_LSM_MMAP_MIN_ADDR policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_LS_EXTIRQ policy<{'arm64': 'y'}> +CONFIG_LS_SCFG_MSI policy<{'arm64': 'y'}> +CONFIG_LTC1660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2309 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2471 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2485 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2496 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2497 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2632 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2664 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2688 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTC2983 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTL_MON_EVENTS_ID policy<{'armhf': 'y'}> +CONFIG_LTO_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LTR390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTR501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LTRF216A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LV0104CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_LWQ_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_LWTUNNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LWTUNNEL_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LXT_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LZ4HC_COMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LZ4_COMPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_LZ4_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LZO_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_LZO_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_M62332 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAC80211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAC80211_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_DEBUG_MENU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MAC80211_HAS_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_HWSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAC80211_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_MESH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_MESSAGE_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_RC_DEFAULT policy<{'amd64': '"minstrel_ht"', 'arm64': '"minstrel_ht"', 'armhf': '"minstrel_ht"', 'ppc64el': '"minstrel_ht"', 'riscv64': '"minstrel_ht"'}> +CONFIG_MAC80211_RC_DEFAULT_MINSTREL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_RC_MINSTREL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MAC80211_STA_HASH_MAX_SIZE policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_MAC802154 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MACB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MACB_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MACB_USE_HWSTAMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MACHZ_WDT policy<{'amd64': 'm'}> +CONFIG_MACH_ARMADA_370 policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_375 policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_38X policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_39X policy<{'armhf': 'y'}> +CONFIG_MACH_ARMADA_XP policy<{'armhf': 'y'}> +CONFIG_MACH_ARTPEC6 policy<{'armhf': 'n'}> +CONFIG_MACH_ASPEED_G6 policy<{'armhf': 'y'}> +CONFIG_MACH_BERLIN_BG2 policy<{'armhf': 'y'}> +CONFIG_MACH_BERLIN_BG2CD policy<{'armhf': 'y'}> +CONFIG_MACH_BERLIN_BG2Q policy<{'armhf': 'y'}> +CONFIG_MACH_DOVE policy<{'armhf': 'y'}> +CONFIG_MACH_INFINITY policy<{'armhf': 'y'}> +CONFIG_MACH_MESON6 policy<{'armhf': 'y'}> +CONFIG_MACH_MESON8 policy<{'armhf': 'y'}> +CONFIG_MACH_MMP2_DT policy<{'armhf': 'y'}> +CONFIG_MACH_MMP3_DT policy<{'armhf': 'y'}> +CONFIG_MACH_MT2701 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6572 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6582 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6589 policy<{'armhf': 'y'}> +CONFIG_MACH_MT6592 policy<{'armhf': 'y'}> +CONFIG_MACH_MT7623 policy<{'armhf': 'y'}> +CONFIG_MACH_MT7629 policy<{'armhf': 'y'}> +CONFIG_MACH_MT8127 policy<{'armhf': 'y'}> +CONFIG_MACH_MT8135 policy<{'armhf': 'y'}> +CONFIG_MACH_MVEBU_ANY policy<{'armhf': 'y'}> +CONFIG_MACH_MVEBU_V7 policy<{'armhf': 'y'}> +CONFIG_MACH_OMAP_GENERIC policy<{'armhf': 'y'}> +CONFIG_MACINTOSH_DRIVERS policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_MACSEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MACVLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MACVTAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MAC_EMUMOUSEBTN policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_MAC_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MADERA_IRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAG3110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAGIC_SYSRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE policy<{'amd64': '0x01b6', 'arm64': '0x01b6', 'armhf': '0x01b6', 'ppc64el': '0x01b6', 'riscv64': '0x01b6', 's390x': '0x01b6'}> +CONFIG_MAGIC_SYSRQ_SERIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_MAILBOX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MAILBOX_TEST policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MANAGER_SBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MANA_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MANTIS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAPPING_DIRTY_HELPERS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_MARCH_Z10 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z13 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z14 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z15 policy<{'s390x': 'y'}> +CONFIG_MARCH_Z16 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z16_TUNE policy<{'s390x': 'y'}> +CONFIG_MARCH_Z17 policy<{'s390x': 'n'}> +CONFIG_MARCH_Z196 policy<{'s390x': 'n'}> +CONFIG_MARCH_ZEC12 policy<{'s390x': 'n'}> +CONFIG_MARVELL_10G_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MARVELL_88Q2XXX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MARVELL_88X2222_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MARVELL_CN10K_DDR_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_CN10K_DPI policy<{'arm64': 'm'}> +CONFIG_MARVELL_CN10K_TAD_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_GTI_WDT policy<{'arm64-generic': 'm', 'arm64-generic-64k': 'y'}> +CONFIG_MARVELL_PEM_PMU policy<{'arm64': 'm'}> +CONFIG_MARVELL_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MATH_EMULATION policy<{'ppc64el': 'n'}> +CONFIG_MAX1027 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX11100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX1118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX11205 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX11410 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX1241 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX1363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX14001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX22007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX30100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX30102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX30208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX31827 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX31856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX31865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX34408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX44000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX44009 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX517 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5481 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5487 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5522 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX5821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX63XX_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MAX6959 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX77541_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX77620_THERMAL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX77620_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAX8925_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MAX9611 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAXIM_THERMOCOUPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MAXLINEAR_86110_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MAXLINEAR_GPHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MAXSMP policy<{'amd64': 'y'}> +CONFIG_MAX_PHYSMEM_BITS policy<{'s390x': '46'}> +CONFIG_MAX_SKB_FRAGS policy<{'amd64': '17', 'arm64': '17', 'armhf': '17', 'ppc64el': '17', 'riscv64': '17', 's390x': '17'}> +CONFIG_MB1232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MC3230 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MCB_LPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCB_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCHP_CLK_MPFS policy<{'arm64': 'y'}> +CONFIG_MCHP_LAN966X_PCI policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MCP320X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP3422 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP3564 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP3911 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4018 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP41010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4131 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4531 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4725 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4728 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP47FEB02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP4922 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCP9600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCPM policy<{'armhf': 'y'}> +CONFIG_MCPM_QUAD_CLUSTER policy<{'armhf': 'y'}> +CONFIG_MCTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MCTP_FLOWS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MCTP_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCTP_TRANSPORT_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCTP_TRANSPORT_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MCTP_TRANSPORT_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MDIO_ASPEED policy<{'armhf': 'm'}> +CONFIG_MDIO_BCM_UNIMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MDIO_BITBANG policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MDIO_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MDIO_BUS_MUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_BUS_MUX_GPIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_BUS_MUX_MESON_G12A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MDIO_BUS_MUX_MESON_GXL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MDIO_BUS_MUX_MMIOREG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_BUS_MUX_MULTIPLEXER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_CAVIUM policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_HISI_FEMAC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MDIO_IPQ4019 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_IPQ8064 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_MSCC_MIIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MDIO_MVUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MDIO_OCTEON policy<{'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_REGMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MDIO_SUN4I policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MDIO_THUNDER policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MDIO_XGENE policy<{'arm64': 'm'}> +CONFIG_MDM_GCC_9607 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MDM_GCC_9615 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MD_AUTODETECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MD_BITMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MD_BITMAP_FILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MD_CLUSTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_LINEAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_LLBITMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MD_RAID0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_RAID1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_RAID10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MD_RAID456 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MEDIATEK_2P5GE_PHY policy<{'arm64': 'm'}> +CONFIG_MEDIATEK_GE_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MEDIATEK_GE_SOC_PHY policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MEDIATEK_MT6359_AUXADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIATEK_MT6360_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIATEK_MT6370_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIATEK_MT6577_AUXADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MEDIATEK_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MEDIA_ALTERA_CI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_ANALOG_TV_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_ATTACH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CAMERA_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CEC_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CEC_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MEDIA_COMMON_OPTIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_CONTROLLER_DVB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_DIGITAL_TV_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_PCI_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_PLATFORM_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_RADIO_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_SDR_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_SUBDRV_AUTOSELECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MEDIA_SUPPORT_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_TEST_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEDIA_TUNER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_E4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC0011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC0012 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC0013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_FC2580 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_IT913X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_M88RS6000T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MAX2165 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MC44S803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MSI001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2063 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT20XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2131 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MT2266 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MXL301RF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MXL5005S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_MXL5007T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_QM1D1B0004 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_QM1D1C0042 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_QT1010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_R820T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_SI2157 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_SIMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18212 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18218 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA18271 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA827X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA8290 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TDA9887 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TEA5761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TEA5767 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_TUA9001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_XC2028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_XC4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_TUNER_XC5000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEDIA_USB_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEEGOPAD_ANX7428 policy<{'amd64': 'm'}> +CONFIG_MEGARAID_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MEGARAID_MAILBOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEGARAID_MM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MEGARAID_NEWGEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MEGARAID_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MELLANOX_PLATFORM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_MEMBARRIER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMBLOCK_KHO_SCRATCH policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_MEMCG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMCG_NMI_SAFETY_REQUIRES_ATOMIC policy<{'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_MEMCG_V1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MEMFD_CREATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MEMORY_FAILURE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_MEMORY_HOTPLUG policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY_HOTREMOVE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY_ISOLATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MEMORY_NOTIFIER_ERROR_INJECT policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MEMREGION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEMSTICK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MEMSTICK_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MEMSTICK_JMICRON_38X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_R592 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_REALTEK_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_TIFM_MS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEMSTICK_UNSAFE_RESUME policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MEMTEST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MEM_ALLOC_PROFILING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MEM_SOFT_DIRTY policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MENF21BMC_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MENZ069_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MEN_A21_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MEN_Z188_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MERAKI_MX100 policy<{'amd64': 'm'}> +CONFIG_MESON6_TIMER policy<{'armhf': 'y'}> +CONFIG_MESON_CANVAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_CLK_MEASURE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MESON_DDR_PMU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_EE_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MESON_GXBB_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_GXL_PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_GX_SOCINFO policy<{'arm64': 'y'}> +CONFIG_MESON_IRQ_GPIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MESON_MX_AO_ARC_REMOTEPROC policy<{'armhf': 'm'}> +CONFIG_MESON_MX_SOCINFO policy<{'armhf': 'y'}> +CONFIG_MESON_SARADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESON_SECURE_PM_DOMAINS policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_MESON_SM policy<{'arm64': 'y', 'arm64-generic-64k': '-'}> +CONFIG_MESON_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MESSAGE_LOGLEVEL_DEFAULT policy<{'amd64': '4', 'arm64': '4', 'armhf': '4', 'ppc64el': '4', 'riscv64': '4', 's390x': '4'}> +CONFIG_MFD_88PM800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_88PM805 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_88PM860X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_88PM886_PMIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_AAEON policy<{'amd64': 'm'}> +CONFIG_MFD_AAT2870_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_AC100 policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_ACER_A500_EC policy<{'armhf': 'm'}> +CONFIG_MFD_ACT8945A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ALTERA_A10SR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MFD_ALTERA_SYSMGR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MFD_ARIZONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ARIZONA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_ARIZONA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_AS3711 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_AS3722 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_AT91_USART policy<{'arm64': 'y'}> +CONFIG_MFD_ATC260X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ATC260X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_ATMEL_FLEXCOM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ATMEL_HLCDC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_AXP20X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_AXP20X_RSB policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_BCM590XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_BD9571MWV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_BQ257XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_CGBC policy<{'amd64': 'm'}> +CONFIG_MFD_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_MFD_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_CROS_EC_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_CS40L50_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS40L50_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS40L50_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS42L43_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_CS42L43_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_CS47L15 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L24 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L35 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L85 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L90 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_CS47L92 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_DA9052_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_DA9052_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_DA9055 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_DA9062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_DA9063 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_DA9150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_ENE_KB3930 policy<{'armhf': 'm'}> +CONFIG_MFD_EXYNOS_LPASS policy<{'armhf': 'n'}> +CONFIG_MFD_GATEWORKS_GSC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_HI6421_PMIC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_HI6421_SPMI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_HI655X_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_INTEL_LPSS policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_LPSS_ACPI policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_LPSS_PCI policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_PMCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_INTEL_M10_BMC_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_INTEL_PMC_BXT policy<{'amd64': 'm'}> +CONFIG_MFD_INTEL_QUARK_I2C_GPIO policy<{'amd64': 'm'}> +CONFIG_MFD_IQS62X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_JANZ_CMODIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_KEMPLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_KHADAS_MCU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_LOCHNAGAR policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_LP3943 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_LP8788 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_LS2K_BMC_CORE policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_MFD_MACSMC policy<{'arm64': 'm'}> +CONFIG_MFD_MADERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MADERA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MADERA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX14577 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_MAX5970 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX77541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77620 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77686 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_MAX77693 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX77714 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77759 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MAX77843 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MAX8907 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MAX8925 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MAX8997 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MAX8998 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_MC13XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_MC13XXX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MC13XXX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_MENF21BMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MP2629 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_MT6397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_NTXEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_NVEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_OCELOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_OMAP_USB_HOST policy<{'armhf': 'y'}> +CONFIG_MFD_PALMAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_PF1550 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_PM8XXX policy<{'armhf': 'm'}> +CONFIG_MFD_QCOM_PM8008 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_QCOM_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_QNAP_MCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_RC5T583 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_RDC321X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RETU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RK8XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RK8XX_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RK8XX_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RN5T618 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD718XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD957XMUF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_ROHM_BD96801 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RSMU_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RSMU_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_RT4831 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_RT5120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SC27XX_PMIC policy<{'arm64': 'm'}> +CONFIG_MFD_SEC_ACPM policy<{'armhf': 'm'}> +CONFIG_MFD_SEC_CORE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SEC_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SI476X_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SIMPLE_MFD_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SKY81452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_MFD_SM501_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_SMPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SPMI_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_STM32_LPTIMER policy<{'arm64': 'm'}> +CONFIG_MFD_STM32_TIMERS policy<{'arm64': 'm'}> +CONFIG_MFD_STMFX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_STMPE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_STPMIC1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_SUN4I_GPADC policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_SUN6I_PRCM policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MFD_SY7636A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_SYSCON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_TC3589X policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_TI_AM335X_TSCADC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_MFD_TI_LMU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TI_LP873X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TI_LP87565 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TN48M_CPLD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MFD_TPS65086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TPS65090 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_TPS65218 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TPS65219 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TPS6586X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_TPS65910 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_TPS65912 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_TPS65912_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MFD_TPS65912_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_TPS6594 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_TPS6594_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MFD_TPS6594_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MFD_TQMX86 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_TWL4030_AUDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_UPBOARD_FPGA policy<{'amd64': 'm'}> +CONFIG_MFD_VEXPRESS_SYSREG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MFD_VIPERBOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MFD_VX855 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_WCD934X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_WM5102 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM5110 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM831X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM831X_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_WM831X_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM8350 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM8350_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_WM8400 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_MFD_WM8994 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MFD_WM8997 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MFD_WM8998 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MHI_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MHI_BUS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MHI_BUS_EP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MHI_BUS_PCI_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHI_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHI_WWAN_CTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHI_WWAN_MBIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MHZ19B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MICREL_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCHIP_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCHIP_PHY_RDS_PTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCHIP_PIT64B policy<{'arm64': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MICROCHIP_T1S_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MICROCHIP_T1_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROCODE policy<{'amd64': 'y'}> +CONFIG_MICROCODE_DBG policy<{'amd64': 'n'}> +CONFIG_MICROCODE_LATE_LOADING policy<{'amd64': 'n'}> +CONFIG_MICROSEMI_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MICROSOFT_MANA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MIGHT_HAVE_CACHE_L2X0 policy<{'armhf': 'y'}> +CONFIG_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MII policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MILBEAUT_HDMAC policy<{'armhf': 'm'}> +CONFIG_MILBEAUT_TIMER policy<{'armhf': 'y'}> +CONFIG_MILBEAUT_XDMAC policy<{'armhf': 'm'}> +CONFIG_MINIX_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MINIX_SUBPARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MIN_HEAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MIPI_I3C_HCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MIPI_I3C_HCI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISC_ALCOR_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MISC_FILESYSTEMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MISC_RP1 policy<{'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MISC_RTSX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISC_RTSX_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MISC_RTSX_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MISDN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MISDN_AVMFRITZ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_DSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MISDN_HDLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_HFCMULTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_HFCPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MISDN_HFCUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_INFINEON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_IPAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_ISAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_L1OIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MISDN_NETJET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_SPEEDFAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MISDN_W6692 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY policy<{'arm64': 'y'}> +CONFIG_MITIGATION_CALL_DEPTH_TRACKING policy<{'amd64': 'y'}> +CONFIG_MITIGATION_GDS policy<{'amd64': 'n'}> +CONFIG_MITIGATION_IBPB_ENTRY policy<{'amd64': 'y'}> +CONFIG_MITIGATION_IBRS_ENTRY policy<{'amd64': 'y'}> +CONFIG_MITIGATION_ITS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_L1TF policy<{'amd64': 'y'}> +CONFIG_MITIGATION_MDS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_MMIO_STALE_DATA policy<{'amd64': 'y'}> +CONFIG_MITIGATION_PAGE_TABLE_ISOLATION policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RETBLEED policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RETHUNK policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RETPOLINE policy<{'amd64': 'y'}> +CONFIG_MITIGATION_RFDS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SLS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SPECTRE_BHI policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SPECTRE_V1 policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SPECTRE_V2 policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SRBDS policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SRSO policy<{'amd64': 'y'}> +CONFIG_MITIGATION_SSB policy<{'amd64': 'y'}> +CONFIG_MITIGATION_TAA policy<{'amd64': 'y'}> +CONFIG_MITIGATION_TSA policy<{'amd64': 'y'}> +CONFIG_MITIGATION_UNRET_ENTRY policy<{'amd64': 'y'}> +CONFIG_MITIGATION_VMSCAPE policy<{'amd64': 'y'}> +CONFIG_MKISS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLX4_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX4_CORE_GEN2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX4_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX4_EN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX4_EN_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX4_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX5_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CLS_ACT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX5_CORE_EN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CORE_EN_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_CORE_IPOIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_DPLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MLX5_EN_ARFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_EN_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_EN_PSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_EN_RXNFC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_EN_TLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_ESWITCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_FPGA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_HW_STEERING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLX5_MACSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_MPFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_SF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MLX5_SF_MANAGER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_SW_STEERING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_TC_CT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_TC_SAMPLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX5_VDPA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_VDPA_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLX5_VDPA_STEERING_DEBUG policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLX5_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MLX90614 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLX90632 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLX90635 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLXBF_BOOTCTL policy<{'arm64': 'm'}> +CONFIG_MLXBF_GIGE policy<{'arm64': 'm'}> +CONFIG_MLXBF_PMC policy<{'arm64': 'm'}> +CONFIG_MLXBF_TMFIFO policy<{'arm64': 'm'}> +CONFIG_MLXFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXREG_DPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXREG_HOTPLUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXREG_IO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXREG_LC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MLXSW_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXSW_CORE_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLXSW_CORE_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MLXSW_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MLXSW_MINIMAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MLXSW_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXSW_SPECTRUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MLXSW_SPECTRUM_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MLX_PLATFORM policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MLX_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMA7455 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA7455_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA7455_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA7660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA8452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA9551 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA9551_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMA9553 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_MMC35240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC5633 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMCONF_FAM10H policy<{'amd64': 'y'}> +CONFIG_MMC_ALCOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_ARMMMCI policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_MMC_BLOCK_MINORS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_MMC_CAVIUM_THUNDERX policy<{'arm64': 'm'}> +CONFIG_MMC_CB710 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_CQHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MMC_DW policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_BLUEFIELD policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_EXYNOS policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_HI3798CV200 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_HI3798MV200 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_K3 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_PCI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_PLTFM policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_MMC_DW_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_HSQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_LITEX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_MESON_GX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_MESON_MX_SDHC policy<{'armhf': 'm'}> +CONFIG_MMC_MESON_MX_SDIO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_MTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_MVSDIO policy<{'armhf': 'm'}> +CONFIG_MMC_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_OMAP policy<{'armhf': 'm'}> +CONFIG_MMC_OWL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_QCOM_DML policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MMC_REALTEK_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_REALTEK_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_RICOH_MMC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMC_SDHCI_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_AM654 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER policy<{'ppc64el': 'y'}> +CONFIG_MMC_SDHCI_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_DOVE policy<{'armhf': 'm'}> +CONFIG_MMC_SDHCI_ESDHC_IMX policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_MMC_SDHCI_EXTERNAL_DMA policy<{'arm64': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MMC_SDHCI_F_SDH30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_IO_ACCESSORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMC_SDHCI_MILBEAUT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_MSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_OF_ARASAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_OF_ASPEED policy<{'armhf': 'm'}> +CONFIG_MMC_SDHCI_OF_AT91 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_OF_DWCMSHC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_OF_ESDHC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_MMC_SDHCI_OF_HLWD policy<{'ppc64el': 'm'}> +CONFIG_MMC_SDHCI_OF_MA35D1 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OF_SPARX5 policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_OMAP policy<{'arm64': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_MMC_SDHCI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_PXAV2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_PXAV3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_S3C policy<{'armhf': 'n'}> +CONFIG_MMC_SDHCI_SPRD policy<{'arm64': 'm'}> +CONFIG_MMC_SDHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SDHCI_UHS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHCI_XENON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MMC_SDHI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_MMC_SDHI_INTERNAL_DMAC policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_MMC_SDHI_SYS_DMAC policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_MMC_SDRICOH_CS policy<{'amd64': 'm'}> +CONFIG_MMC_SH_MMCIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_STM32_SDMMC policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_MMC_SUNPLUS policy<{'armhf': 'm'}> +CONFIG_MMC_SUNXI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MMC_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MMC_TIFM_SD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_TMIO_CORE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMC_TOSHIBA_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_USDHI6ROL0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_USHC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_VIA_SDMMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_VUB300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MMC_WBSD policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_MMIOTRACE policy<{'amd64': 'y'}> +CONFIG_MMIOTRACE_TEST policy<{'amd64': 'n'}> +CONFIG_MMIOWB policy<{'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MMP_PDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMP_TDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MMU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_GATHER_MERGE_VMAS policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_MMU_GATHER_NO_GATHER policy<{'s390x': 'y'}> +CONFIG_MMU_GATHER_PAGE_SIZE policy<{'ppc64el': 'y'}> +CONFIG_MMU_GATHER_RCU_TABLE_FREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_GATHER_TABLE_FREE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_LAZY_TLB_REFCOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MMU_LAZY_TLB_SHOOTDOWN policy<{'ppc64el': 'y'}> +CONFIG_MMU_NOTIFIER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MM_ID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODPROBE_PATH policy<{'amd64': '"/sbin/modprobe"', 'arm64': '"/sbin/modprobe"', 'armhf': '"/sbin/modprobe"', 'ppc64el': '"/sbin/modprobe"', 'riscv64': '"/sbin/modprobe"', 's390x': '"/sbin/modprobe"'}> +CONFIG_MODULES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULES_TREE_LOOKUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULES_USE_ELF_REL policy<{'armhf': 'y'}> +CONFIG_MODULES_USE_ELF_RELA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_ALLOW_BTF_MISMATCH policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_COMPRESS_ALL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_COMPRESS_GZIP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_COMPRESS_XZ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_FORCE_LOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_FORCE_UNLOAD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SECTIONS policy<{'riscv64': 'y'}> +CONFIG_MODULE_SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_FORMAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_HASH policy<{'amd64': '"sha512"', 'arm64': '"sha512"', 'armhf': '"sha512"', 'ppc64el': '"sha512"', 'riscv64': '"sha512"', 's390x': '"sha512"'}> +CONFIG_MODULE_SIG_KEY policy<{'amd64': '"certs/signing_key.pem"', 'arm64': '"certs/signing_key.pem"', 'armhf': '"certs/signing_key.pem"', 'ppc64el': '"certs/signing_key.pem"', 'riscv64': '"certs/signing_key.pem"', 's390x': '"certs/signing_key.pem"'}> +CONFIG_MODULE_SIG_KEY_TYPE_ECDSA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_44 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_65 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_MLDSA_87 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_KEY_TYPE_RSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SIG_SHA256 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA384 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA3_256 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA3_384 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA3_512 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MODULE_SIG_SHA512 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_SRCVERSION_ALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_UNLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MODULE_UNLOAD_TAINT_TRACKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_MONREADER policy<{'s390x': 'm'}> +CONFIG_MONWRITER policy<{'s390x': 'm'}> +CONFIG_MOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MOST_CDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_COMPONENTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_DIM2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_SND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_USB_HDM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOST_VIDEO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MOTORCOMM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_MOUSE_APPLETOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_BCM5974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_CYAPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_ELAN_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_ELAN_I2C_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_ELAN_I2C_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_PS2_ALPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_BYD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_CYPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_ELANTECH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_ELANTECH_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_FOCALTECH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_LIFEBOOK policy<{'amd64': 'y'}> +CONFIG_MOUSE_PS2_LOGIPS2PP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SENTELIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SYNAPTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_TOUCHKIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_TRACKPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MOUSE_PS2_VMMOUSE policy<{'amd64': 'y'}> +CONFIG_MOUSE_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_SYNAPTICS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_SYNAPTICS_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOUSE_VSXXXAA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOXA_INTELLIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOXA_SMARTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MOXTET policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MP2629_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPIC policy<{'ppc64el': 'y'}> +CONFIG_MPIC_MSGR policy<{'ppc64el': 'n'}> +CONFIG_MPILIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPL115 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPL115_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPL115_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPL3115 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPLS_IPTUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MPLS_ROUTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MPRLS0025PA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPRLS0025PA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPRLS0025PA_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPROFILE_KERNEL policy<{'ppc64el': 'y'}> +CONFIG_MPTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPTCP_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MPU3050 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MPU3050_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MQ_IOSCHED_DEADLINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MQ_IOSCHED_KYBER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MRP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MS5611 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MS5611_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MS5611_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MS5637 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSA311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSC313E_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_MSCC_OCELOT_SWITCH policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSCC_OCELOT_SWITCH_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSDOS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_MSDOS_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MSE102X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSHV_ROOT policy<{'amd64': 'm', 'arm64-generic': 'm'}> +CONFIG_MSI_BITMAP_SELFTEST policy<{'ppc64el': 'n'}> +CONFIG_MSI_EC policy<{'amd64': 'm'}> +CONFIG_MSI_LAPTOP policy<{'amd64': 'm'}> +CONFIG_MSI_WMI policy<{'amd64': 'm'}> +CONFIG_MSI_WMI_PLATFORM policy<{'amd64': 'm'}> +CONFIG_MSM_GCC_8660 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8909 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8917 policy<{'arm64': 'm'}> +CONFIG_MSM_GCC_8939 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8953 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8960 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8974 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_GCC_8976 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8994 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GCC_8998 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_GPUCC_8998 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_IOMMU policy<{'armhf': 'n'}> +CONFIG_MSM_LCC_8960 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8960 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8974 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8994 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSM_MMCC_8998 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MSPRO_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MSTAR_MSC313_CPUPLL policy<{'armhf': 'y'}> +CONFIG_MSTAR_MSC313_MPLL policy<{'armhf': 'y'}> +CONFIG_MST_IRQ policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MS_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7601U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7603E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7615E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7615_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7622_WMAC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MT7663S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7663U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7663_USB_SDIO_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_CONNAC_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MT76_NPU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MT76_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x02_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x02_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x0E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x0U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x0_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x2E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x2U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT76x2_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7915E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7921_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7925E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7925U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7925_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT792x_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT792x_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT798X_WMAC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MT7996E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MT7996_NPU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTDRAM_ERASE_SIZE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_MTDRAM_TOTAL_SIZE policy<{'amd64': '4096', 'arm64': '4096', 'armhf': '4096', 'ppc64el': '4096', 'riscv64': '4096'}> +CONFIG_MTD_ABSENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_AFS_PARTS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_AMD76XROM policy<{'amd64': 'm'}> +CONFIG_MTD_BCM47XXSFLASH policy<{'armhf': 'm'}> +CONFIG_MTD_BLKDEVS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_BLOCK2MTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_BLOCK_RO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_ADV_OPTIONS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_CFI_AMDSTD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_I1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_CFI_I2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_CFI_INTELEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_STAA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CFI_UTIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_CK804XROM policy<{'amd64': 'm'}> +CONFIG_MTD_CMDLINE_PARTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MTD_COMPLEX_MAPPINGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_DATAFLASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_DATAFLASH_OTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_DATAFLASH_WRITE_VERIFY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_ESB2ROM policy<{'amd64': 'm'}> +CONFIG_MTD_GEN_PROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_HYPERBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_ICHXROM policy<{'amd64': 'm'}> +CONFIG_MTD_IMPA7 policy<{'armhf': 'm'}> +CONFIG_MTD_INTEL_DG policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_MTD_JEDECPROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_L440GX policy<{'amd64': 'm'}> +CONFIG_MTD_LPDDR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_LPDDR2_NVM policy<{'armhf': 'm'}> +CONFIG_MTD_MAP_BANK_WIDTH_1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_MAP_BANK_WIDTH_2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_MAP_BANK_WIDTH_4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_MCHP23K256 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_MCHP48L640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_MTDRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_ARASAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_BRCMNAND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BCM63XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BCMBCA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_BRCMSTB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_BRCMNAND_IPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_CAFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DENALI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DENALI_DT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DENALI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DISKONCHIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_NAND_ECC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_ECC_MXIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_BCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_HAMMING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_NAND_FSL_IFC policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_GPMI_NAND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_HISI504 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_INTEL_LGM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_MARVELL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_MXIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_NANDSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_NUVOTON_MA35 policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_OMAP2 policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_MTD_NAND_OMAP_BCH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTD_NAND_OMAP_BCH_BUILD policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_MTD_NAND_ORION policy<{'armhf': 'm'}> +CONFIG_MTD_NAND_PL35X policy<{'armhf': 'm'}> +CONFIG_MTD_NAND_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_RENESAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_RICOH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_NAND_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_STM32_FMC2 policy<{'arm64': 'm'}> +CONFIG_MTD_NAND_SUNXI policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_MTD_NAND_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_NAND_VF610_NFC policy<{'armhf': 'n'}> +CONFIG_MTD_NETtel policy<{'amd64': 'm'}> +CONFIG_MTD_ONENAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_ONENAND_2X_PROGRAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_ONENAND_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_ONENAND_OTP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_OOPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PARSER_TRX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_PARTITIONED_MASTER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PCMCIA policy<{'amd64': 'm'}> +CONFIG_MTD_PCMCIA_ANONYMOUS policy<{'amd64': 'n'}> +CONFIG_MTD_PHRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PHYSMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PHYSMAP_COMPAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_PHYSMAP_GEMINI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_PHYSMAP_GPIO_ADDR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_PHYSMAP_IXP4XX policy<{'armhf': 'y'}> +CONFIG_MTD_PHYSMAP_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_PHYSMAP_VERSATILE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_MTD_PLATRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PMC551 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_PMC551_BUGFIX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_PMC551_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_POWERNV_FLASH policy<{'ppc64el': 'm'}> +CONFIG_MTD_PSTORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_QCOMSMEM_PARTS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTD_QINFO_PROBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_RAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK policy<{'amd64': '-1', 'arm64': '-1', 'armhf': '-1', 'ppc64el': '-1', 'riscv64': '-1'}> +CONFIG_MTD_REDBOOT_PARTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_REDBOOT_PARTS_READONLY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_ROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SBC_GXX policy<{'amd64': 'm'}> +CONFIG_MTD_SCB2_FLASH policy<{'amd64': 'm'}> +CONFIG_MTD_SLRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SM_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SPI_NAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SPI_NOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SPI_NOR_SWP_DISABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_SPI_NOR_SWP_KEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_SST25L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_SWAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_TESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_MTD_UBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_UBI_BEB_LIMIT policy<{'amd64': '20', 'arm64': '20', 'armhf': '20', 'ppc64el': '20', 'riscv64': '20'}> +CONFIG_MTD_UBI_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_UBI_FASTMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MTD_UBI_GLUEBI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_UBI_NVMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTD_UBI_WL_THRESHOLD policy<{'amd64': '4096', 'arm64': '4096', 'armhf': '4096', 'ppc64el': '4096', 'riscv64': '4096'}> +CONFIG_MTK_ADSP_IPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_ADSP_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_CMDQ policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_CMDQ_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_CPUX_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_CQDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_DEVAPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_DVFSRC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_GPUEB_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_HSDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_INFRACFG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_IOMMU policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_MTK_IOMMU_V1 policy<{'armhf': 'n'}> +CONFIG_MTK_LVTS_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_LVTS_THERMAL_DEBUGFS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_MFG_PM_DOMAIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_MMSYS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_NET_PHYLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTK_PMIC_WRAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_REGULATOR_COUPLER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_SCP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_SCPSYS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_SCPSYS_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_SMI policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_MTK_SOCINFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_SOC_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_SVS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_T7XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MTK_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MTK_UART_APDMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTK_VCP_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MTRR policy<{'amd64': 'y'}> +CONFIG_MTRR_SANITIZER policy<{'amd64': 'y'}> +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT policy<{'amd64': '1'}> +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT policy<{'amd64': '1'}> +CONFIG_MULTIPLEXER policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MULTIUSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MUSB_PIO_ONLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_MUTEX_SPIN_ON_OWNER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_MUX_ADG792A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MUX_ADGS1408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MUX_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MUX_MMIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MV643XX_ETH policy<{'armhf': 'm'}> +CONFIG_MVEBU_CLK_COMMON policy<{'armhf': 'y'}> +CONFIG_MVEBU_CLK_COREDIV policy<{'armhf': 'y'}> +CONFIG_MVEBU_CLK_CPU policy<{'armhf': 'y'}> +CONFIG_MVEBU_DEVBUS policy<{'armhf': 'y'}> +CONFIG_MVEBU_GICP policy<{'arm64': 'y'}> +CONFIG_MVEBU_ICU policy<{'arm64': 'y'}> +CONFIG_MVEBU_MBUS policy<{'armhf': 'y'}> +CONFIG_MVEBU_ODMI policy<{'arm64': 'y'}> +CONFIG_MVEBU_PIC policy<{'arm64': 'y'}> +CONFIG_MVEBU_SEI policy<{'arm64': 'y'}> +CONFIG_MVMDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MVNETA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MVNETA_BM_ENABLE policy<{'armhf': 'n'}> +CONFIG_MVPP2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_MVPP2_PTP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MV_XOR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MV_XOR_V2 policy<{'arm64': 'y'}> +CONFIG_MWIFIEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWIFIEX_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWIFIEX_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWIFIEX_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MWL8K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MXC4005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MXC6255 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_MXC_CLK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MXC_CLK_SCU policy<{'arm64': 'y'}> +CONFIG_MXC_TZIC policy<{'armhf': 'y'}> +CONFIG_MXM_WMI policy<{'amd64': 'm'}> +CONFIG_MXS_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_MYRI10GE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_MYRI10GE_DCA policy<{'amd64': 'y'}> +CONFIG_NAMESPACES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NATIONAL_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NATSEMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NAU7802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NBPFAXI_DMA policy<{'armhf': 'm'}> +CONFIG_NCN26000_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NCSI_OEM_CMD_GET_MAC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NCSI_OEM_CMD_KEEP_PHY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NCT6694_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NCT7201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NDC_DIS_DYNAMIC_CACHING policy<{'arm64': 'y'}> +CONFIG_ND_BTT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ND_CLAIM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ND_PFN policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NE2K_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NEED_DMA_MAP_STATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP policy<{'arm64': 'y'}> +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NEED_PROC_VMCORE_DEVICE_RAM policy<{'s390x': 'y'}> +CONFIG_NEED_SG_DMA_FLAGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEED_SG_DMA_LENGTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_NEED_SRCU_NMI_SAFE policy<{'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_NEED_TASKS_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEON policy<{'armhf': 'y'}> +CONFIG_NET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETCONSOLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETCONSOLE_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETCONSOLE_EXTENDED_LOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NETDEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETDEVSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETDEV_NOTIFIER_ERROR_INJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NETFILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_ADVANCED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_BPF_LINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_CONNCOUNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_EGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_FAMILY_ARP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_FAMILY_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_INGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_NETLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_ACCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_GLUE_CT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_NETLINK_HOOK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_OSF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_NETLINK_QUEUE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_SKIP_EGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XTABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XTABLES_COMPAT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_NETFILTER_XTABLES_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFILTER_XT_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CGROUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CLUSTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_COMMENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNBYTES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNLABEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_CPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DCCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DEVGROUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_DSCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ECN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPRANGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_IPVS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_L2TP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_LENGTH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_LIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_NFACCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_OSF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_OWNER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_PHYSDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_PKTTYPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_POLICY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_QUOTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_RATEEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_REALM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_RECENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_SCTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_SOCKET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STATISTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_STRING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_TCPMSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_TIME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_MATCH_U32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_SET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_AUDIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CHECKSUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CLASSIFY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_CT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_DSCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_HL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_HMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_IDLETIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NETFILTER_XT_TARGET_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_MARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_MASQUERADE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NETMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NFLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NFQUEUE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_NOTRACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_RATEEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_REDIRECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_SECMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TCPMSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TEE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFILTER_XT_TARGET_TRACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETFS_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFS_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETFS_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETKIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETLABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETLINK_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NETPOLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NETWORK_FILESYSTEMS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETWORK_SECMARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NETXEN_NIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NET_9P_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_9P_FD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P_USBG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_9P_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_9P_XEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_NET_ACT_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CONNMARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CSUM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_CTINFO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_GACT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_GATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_IFE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_ACT_MIRRED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_MPLS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_PEDIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_POLICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SAMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SIMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SKBEDIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_SKBMOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_TUNNEL_KEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_ACT_VLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NET_AIROHA_FLOW_STATS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NET_AIROHA_NPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NET_CALXEDA_XGMAC policy<{'armhf': 'm'}> +CONFIG_NET_CLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_CLS_ACT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_CLS_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_CGROUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_FLOW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_FLOWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_FW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_MATCHALL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_ROUTE4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CLS_U32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_CRC32C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DEVLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DEVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_DEV_REFCNT_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_DSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NET_DSA_AR9331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_BCM_SF2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_KS8995 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_LANTIQ_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_LANTIQ_GSWIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_LOOP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MSCC_FELIX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n'}> +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MSCC_OCELOT_EXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_NET_DSA_MSCC_SEVILLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MT7530 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MT7530_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MT7530_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MV88E6060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MV88E6XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MV88E6XXX_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_MV88E6XXX_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_MXL862 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_MXL_GSW1XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_QCA8K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_REALTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_REALTEK_MDIO policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_REALTEK_RTL8365MB policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_REALTEK_RTL8366RB policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_REALTEK_SMI policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_RZN1_A5PSW policy<{'armhf': 'm'}> +CONFIG_NET_DSA_SJA1105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_SJA1105_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_SJA1105_TAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_SJA1105_VL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_DSA_SMSC_LAN9303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_SMSC_LAN9303_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_SMSC_LAN9303_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_AR9331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_BRCM_PREPEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_DSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_DSA_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_EDSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_GSWIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_HELLCREEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_KSZ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_LAN9303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_MTK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_MXL_862XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_MXL_GSW1XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_NONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_OCELOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_OCELOT_8021Q policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_QCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_RTL4_A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_RTL8_4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_RZN1_A5PSW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_SJA1105 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_TRAILER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_VSC73XX_8021Q policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_XRS700X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_TAG_YT921X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_XRS700X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_XRS700X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_XRS700X_MDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_DSA_YT921X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_EGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_EMATCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_EMATCH_CANID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NET_EMATCH_CMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_IPSET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_IPT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_META policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_NBYTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_STACK policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32', 's390x': '32'}> +CONFIG_NET_EMATCH_TEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_EMATCH_U32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_FAILOVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_FC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_FLOW_LIMIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_FOU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_FOU_IP_TUNNELS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_HANDSHAKE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_IEEE8021Q_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_IFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_INGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_IPGRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IPGRE_BROADCAST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_IPGRE_DEMUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IPIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IPVTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_IP_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_KEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_KEY_MIGRATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_L3_MASTER_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_MPLS_GSO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_NCSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_NSH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_NS_REFCNT_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_PKTGEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_POLL_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_PTP_CLASSIFY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_REDIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_RX_BUSY_POLL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCH_BPF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCH_CAKE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_CBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_CHOKE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_CODEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_DEFAULT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NET_SCH_DRR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_DUALPI2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_ETF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_ETS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_FIFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SCH_FQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_FQ_CODEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_FQ_PIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_GRED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_HFSC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_HHF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_HTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_INGRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_MQPRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_MQPRIO_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_MULTIQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_NETEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_PIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_PLUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_PRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_QFQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_RED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_SFB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_SFQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_SKBPRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_TAPRIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_TBF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SCH_TEQL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_SELFTESTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SHAPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_SOCK_MSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_TC_SKB_EXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_TEAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_BROADCAST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_LOADBALANCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_RANDOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TEAM_MODE_ROUNDROBIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_TULIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_UDP_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_VENDOR_3COM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_8390 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_ACTIONS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NET_VENDOR_ADAPTEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ADI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_AGERE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_AIROHA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NET_VENDOR_ALACRITECH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_ALLWINNER policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_NET_VENDOR_ALTEON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_AMAZON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_AMD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_AQUANTIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_ARC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ASIX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_ATHEROS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_BROADCOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_BROCADE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CADENCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_CAVIUM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CHELSIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CIRRUS policy<{'amd64': '-', 'armhf': 'y'}> +CONFIG_NET_VENDOR_CISCO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_CORTINA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_DAVICOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_DEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_DLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ENGLEDER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_EZCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_FARADAY policy<{'armhf': 'y'}> +CONFIG_NET_VENDOR_FREESCALE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_NET_VENDOR_FUJITSU policy<{'amd64': 'y'}> +CONFIG_NET_VENDOR_FUNGIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_GOOGLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_HISILICON policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_HUAWEI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_I825XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NET_VENDOR_IBM policy<{'ppc64el': 'y'}> +CONFIG_NET_VENDOR_INTEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_LITEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MARVELL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MEDIATEK policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_NET_VENDOR_MELLANOX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_META policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_MICREL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MICROCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MICROSEMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MICROSOFT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_MUCSE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_MYRI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_NATSEMI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_NETRONOME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_NI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_NVIDIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_OKI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_PACKET_ENGINES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_PENSANDO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_QLOGIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_QUALCOMM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_RDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_REALTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_RENESAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_ROCKER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SAMSUNG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SEEQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SILAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SMSC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SOCIONEXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_SOLARFLARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_STMICRO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SUN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_NET_VENDOR_SYNOPSYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_TEHUTI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_VERTEXCOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_VIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_WANGXUN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_WIZNET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NET_VENDOR_XILINX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NET_VENDOR_XIRCOM policy<{'amd64': 'y'}> +CONFIG_NET_VRF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NET_XGENE policy<{'arm64': 'm'}> +CONFIG_NET_XGENE_V2 policy<{'arm64': 'm'}> +CONFIG_NET_XGRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NEW_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_NFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NFC_DIGITAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_FDP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_FDP_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_HCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MEI_PHY policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_NFC_MICROREAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MICROREAD_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MICROREAD_MEI policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_MRVL_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NCI_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NCI_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NXP_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_NXP_NCI_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN532_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN533_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN533_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN544 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN544_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PN544_MEI policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_NFC_PORT100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_S3FWRN5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_S3FWRN5_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_S3FWRN82_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_SHDLC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFC_SIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST21NFCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST21NFCA_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST95HF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST_NCI_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_ST_NCI_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_TRF7970A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFC_VIRTUAL_NCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFIT_SECURITY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_NFP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NFP_APP_ABM_NIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFP_APP_FLOWER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NFP_NET_IPSEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFSD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFSD_BLOCKLAYOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_FLEXFILELAYOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_LEGACY_CLIENT_TRACKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFSD_PNFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_SCSILAYOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFSD_V3_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V4_2_INTER_SSC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V4_DELEG_TIMESTAMPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFSD_V4_POSIX_ACLS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFSD_V4_SECURITY_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_ACL_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_DISABLE_UDP_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_FSCACHE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_LOCALIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFS_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_USE_KERNEL_DNS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_USE_LEGACY_DNS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFS_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_V3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_V3_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFS_V4_0 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN policy<{'amd64': '"kernel.org"', 'arm64': '"kernel.org"', 'armhf': '"kernel.org"', 'ppc64el': '"kernel.org"', 'riscv64': '"kernel.org"', 's390x': '"kernel.org"'}> +CONFIG_NFS_V4_1_MIGRATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_2_READ_PLUS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFS_V4_2_SSC_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFS_V4_SECURITY_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NFTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NFTL_RW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NFT_BRIDGE_META policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_BRIDGE_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_COMPAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_COMPAT_ARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_CONNLIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_CT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_DUP_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_DUP_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_DUP_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_EXTHDR_DCCP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NFT_FIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_INET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FIB_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FLOW_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_FWD_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_HASH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_LIMIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_LOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_MASQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_NUMGEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_OSF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_QUEUE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_QUOTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REDIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_INET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_REJECT_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_SOCKET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_SYNPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_TPROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_TUNNEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NFT_XFRM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_AMANDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_BROADCAST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_FTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_H323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_IRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_LABELS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_MARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_NETBIOS_NS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_OVS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_PPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_PROCFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NF_CONNTRACK_SANE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_SECMARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_SIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_SNMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_TFTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CONNTRACK_TIMEOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_TIMESTAMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CONNTRACK_ZONES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CT_NETLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CT_NETLINK_HELPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CT_NETLINK_TIMEOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_CT_PROTO_GRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CT_PROTO_SCTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_CT_PROTO_UDPLITE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_DEFRAG_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DEFRAG_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DUP_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DUP_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_DUP_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_FLOW_TABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_FLOW_TABLE_INET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_FLOW_TABLE_PROCFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NF_LOG_ARP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_LOG_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_LOG_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_LOG_SYSLOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_AMANDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_FTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_H323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_IRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_MASQUERADE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_NAT_OVS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_NAT_PPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_REDIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_NAT_SIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_SNMP_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_NAT_TFTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_REJECT_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_REJECT_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_SOCKET_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_SOCKET_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TABLES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TABLES_ARP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_BRIDGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TABLES_INET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_IPV4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_IPV6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TABLES_NETDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NF_TPROXY_IPV4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NF_TPROXY_IPV6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NGBEVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NI903X_WDT policy<{'amd64': 'm'}> +CONFIG_NIC7018_WDT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_NILFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NINTENDO_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NITRO_ENCLAVES policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_NIU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NI_XGE_MANAGEMENT_ENET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NL80211_TESTMODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_NLATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NLMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ASCII policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_1250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_1251 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_437 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NLS_CODEPAGE_737 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_775 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_850 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_852 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_855 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_857 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_862 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_863 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_864 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_866 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_869 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_874 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_932 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_936 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_949 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_CODEPAGE_950 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_DEFAULT policy<{'amd64': '"utf8"', 'arm64': '"utf8"', 'armhf': '"utf8"', 'ppc64el': '"utf8"', 'riscv64': '"utf8"', 's390x': '"utf8"'}> +CONFIG_NLS_ISO8859_1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_13 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_14 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_15 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_7 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_ISO8859_9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_KOI8_R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_KOI8_U policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CELTIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CENTEURO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CROATIAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_CYRILLIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_GAELIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_GREEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_ICELAND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_INUIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_ROMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_ROMANIAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_MAC_TURKISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_UCS2_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NLS_UTF8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NMI_CHECK_CPU policy<{'amd64': 'y'}> +CONFIG_NMI_IPI policy<{'ppc64el': 'y'}> +CONFIG_NOA1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NODES_SHIFT policy<{'amd64': '10', 'arm64': '6', 'ppc64el': '8', 'riscv64': '2', 's390x': '1'}> +CONFIG_NONPORTABLE policy<{'riscv64': 'n'}> +CONFIG_NONSTATIC_KERNEL policy<{'ppc64el': 'y'}> +CONFIG_NOP_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NOTIFIER_ERROR_INJECTION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NOUVEAU_DEBUG policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5'}> +CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3'}> +CONFIG_NOUVEAU_DEBUG_MMU policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NOUVEAU_DEBUG_PUSH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NOVA_CORE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_NOZOMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NO_HZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NO_HZ_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NO_IOPORT_MAP policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_NO_PAGE_MAPCOUNT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NPCM7XX_KCS_IPMI_BMC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NPCM7XX_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NPCM7XX_WATCHDOG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_NPCM_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NR_CPUS_DEFAULT policy<{'amd64': '8192'}> +CONFIG_NR_CPUS_RANGE_BEGIN policy<{'amd64': '8192'}> +CONFIG_NR_CPUS_RANGE_END policy<{'amd64': '8192'}> +CONFIG_NR_IRQS policy<{'ppc64el': '512'}> +CONFIG_NS83820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NTB_AMD policy<{'amd64': 'n'}> +CONFIG_NTB_EPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_IDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_INTEL policy<{'amd64': 'm'}> +CONFIG_NTB_MSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NTB_MSI_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_NTB_NETDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_PERF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_PINGPONG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_SWITCHTEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_TOOL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTB_TRANSPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NTFS3_64BIT_CLUSTER policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NTFS3_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NTFS3_FS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NTFS3_LZX_XPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NTFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NTSYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NULL_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NUMA_BALANCING policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NUMA_KEEP_MEMINFO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NUMA_MEMBLKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_NVDIMM_DAX policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVDIMM_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVDIMM_PFN policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVDIMM_SECURITY_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_NVEC_PAZ00 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVEC_POWER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVGRACE_GPU_VFIO_PCI policy<{'arm64': 'm'}> +CONFIG_NVHE_EL2_DEBUG policy<{'arm64': 'n'}> +CONFIG_NVIDIA_CARMEL_CNP_ERRATUM policy<{'arm64': 'y'}> +CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU policy<{'arm64': 'm'}> +CONFIG_NVIDIA_SHIELD_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVIDIA_WMI_EC_BACKLIGHT policy<{'amd64': 'm'}> +CONFIG_NVMEM_APPLE_EFUSES policy<{'arm64': 'm'}> +CONFIG_NVMEM_APPLE_SPMI policy<{'arm64': 'm'}> +CONFIG_NVMEM_IMX_IIM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_IMX_OCOTP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_IMX_OCOTP_ELE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_IMX_OCOTP_SCU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_LAYERSCAPE_SFP policy<{'arm64': 'm'}> +CONFIG_NVMEM_LAYOUTS policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVMEM_LAYOUT_ONIE_TLV policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_LAYOUT_SL28_VPD policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_LAYOUT_U_BOOT_ENV policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_MAX77759 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_MESON_EFUSE policy<{'arm64': 'm', 'arm64-generic-64k': '-'}> +CONFIG_NVMEM_MESON_MX_EFUSE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_MTK_EFUSE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_QCOM_QFPROM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_QCOM_SEC_QFPROM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_QNAP_MCU_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_RAVE_SP_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_RCAR_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_REBOOT_MODE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_RMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_NVMEM_ROCKCHIP_EFUSE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_ROCKCHIP_OTP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_S32G_OCOTP policy<{'arm64': 'm'}> +CONFIG_NVMEM_SC27XX_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_SNVS_LPGPR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_NVMEM_SPMI_SDAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_SPRD_EFUSE policy<{'arm64': 'm'}> +CONFIG_NVMEM_STM32_BSEC_OPTEE_TA policy<{'arm64': 'y'}> +CONFIG_NVMEM_STM32_ROMEM policy<{'arm64': 'm'}> +CONFIG_NVMEM_SUNPLUS_OCOTP policy<{'armhf': 'm'}> +CONFIG_NVMEM_SUNXI_SID policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_NVMEM_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVMEM_U_BOOT_ENV policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_NVMEM_VF610_OCOTP policy<{'armhf': 'n'}> +CONFIG_NVMEM_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_NVME_APPLE policy<{'arm64': 'm'}> +CONFIG_NVME_AUTH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_FABRICS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_HOST_AUTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_NVME_KEYRING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_MULTIPATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_AUTH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_TARGET_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NVME_TARGET_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_FCLOOP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NVME_TARGET_LOOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_PASSTHRU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_TARGET_PCI_EPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TARGET_TCP_TLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_NVME_TCP_TLS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_NVME_VERBOSE_ERRORS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_NVSW_SN2201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_NV_TCO policy<{'amd64': 'm'}> +CONFIG_NXP_C45_TJA11XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NXP_CBTX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_NXP_ENETC4 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_ENETC_PF_COMMON policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_NETC_BLK_CTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_NETC_LIB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_NXP_NTMP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_NXP_SAR_ADC policy<{'arm64': 'm'}> +CONFIG_NXP_STM_TIMER policy<{'arm64': 'y'}> +CONFIG_NXP_TJA11XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_N_HDLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_OABI_COMPAT policy<{'armhf': 'n'}> +CONFIG_OA_TC6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OBJAGG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OBJTOOL policy<{'amd64': 'y', 'ppc64el': '-'}> +CONFIG_OBJTOOL_WERROR policy<{'amd64': 'n'}> +CONFIG_OCFS2_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OCFS2_DEBUG_MASKLOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OCFS2_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OCFS2_FS_O2CB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OCFS2_FS_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OCFS2_FS_USERSPACE_CLUSTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OCTEONEP_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OCTEONTX2_AF policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_MBOX policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_PF policy<{'arm64': 'm'}> +CONFIG_OCTEONTX2_VF policy<{'arm64': 'm'}> +CONFIG_OCTEON_EP policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OCTEON_EP_VF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OCXL policy<{'ppc64el': 'm'}> +CONFIG_OCXL_BASE policy<{'ppc64el': 'y'}> +CONFIG_OF policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_OF_ADDRESS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_DYNAMIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_EARLY_FLATTREE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_FLATTREE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_FPGA_REGION policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OF_GPIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_IOMMU policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_IRQ policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_KOBJ policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_MDIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_NUMA policy<{'arm64': 'y', 'riscv64': 'y'}> +CONFIG_OF_OVERLAY policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_PARTITION policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_PMEM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_OF_RESERVED_MEM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_RESOLVE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_OF_UNITTEST policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_OID_REGISTRY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OLD_SIGACTION policy<{'armhf': 'y', 's390x': 'y'}> +CONFIG_OLD_SIGSUSPEND policy<{'ppc64el': 'y'}> +CONFIG_OLD_SIGSUSPEND3 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 's390x': 'y'}> +CONFIG_OLPC_EC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OLPC_XO175 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OLPC_XO175_EC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OMAP2PLUS_MBOX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OMAP2PLUS_PRM policy<{'armhf': 'y'}> +CONFIG_OMAP5_ERRATA_801819 policy<{'armhf': 'y'}> +CONFIG_OMAP_CONTROL_PHY policy<{'armhf': 'm'}> +CONFIG_OMAP_DM_SYSTIMER policy<{'armhf': 'y'}> +CONFIG_OMAP_DM_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OMAP_GPMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OMAP_GPMC_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_OMAP_INTERCONNECT policy<{'armhf': 'y'}> +CONFIG_OMAP_INTERCONNECT_BARRIER policy<{'armhf': 'y'}> +CONFIG_OMAP_IOMMU policy<{'armhf': 'y'}> +CONFIG_OMAP_IOMMU_DEBUG policy<{'armhf': 'n'}> +CONFIG_OMAP_IRQCHIP policy<{'armhf': 'y'}> +CONFIG_OMAP_OCP2SCP policy<{'armhf': 'm'}> +CONFIG_OMAP_REMOTEPROC policy<{'armhf': 'm'}> +CONFIG_OMAP_REMOTEPROC_WATCHDOG policy<{'armhf': 'n'}> +CONFIG_OMAP_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OMAP_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_OMFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_OPAL_CORE policy<{'ppc64el': 'n'}> +CONFIG_OPAL_PRD policy<{'ppc64el': 'm'}> +CONFIG_OPENSSL_SUPPORTS_ML_DSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OPENVSWITCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPENVSWITCH_GENEVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPENVSWITCH_GRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPENVSWITCH_VXLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OPEN_ALLIANCE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OPEN_DICE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPT3001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPT4001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPT4060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OPTEE_INSECURE_LOAD_IMAGE policy<{'arm64': 'n'}> +CONFIG_OPTEE_STATIC_PROTMEM_POOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_OPTPROBES policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_ORANGEFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ORION_IRQCHIP policy<{'armhf': 'y'}> +CONFIG_ORION_TIMER policy<{'armhf': 'y'}> +CONFIG_ORION_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_OSF_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_OUTER_CACHE policy<{'armhf': 'y'}> +CONFIG_OUTER_CACHE_SYNC policy<{'armhf': 'y'}> +CONFIG_OUTPUT_FORMAT policy<{'amd64': '"elf64-x86-64"'}> +CONFIG_OVERLAY_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OVERLAY_FS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_INDEX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_METACOPY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OVERLAY_FS_REDIRECT_DIR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_OVERLAY_FS_XINO_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_OVMF_DEBUG_LOG policy<{'amd64': 'y', 'arm64-generic': 'n', 'arm64-generic-64k': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_OVPN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_OWL_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OWL_EMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_OWL_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OWL_PM_DOMAINS_HELPER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OWL_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_OXP_EC policy<{'amd64': 'm'}> +CONFIG_P2SB policy<{'amd64': 'y'}> +CONFIG_P54_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_P54_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_P54_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_P54_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_P54_SPI_DEFAULT_EEPROM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_P54_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PA12203001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PAC1921 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PAC1934 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PACKET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PACKET_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PADATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_BLOCK_MAX_ORDER policy<{'amd64': '10', 'arm64': '13', 'armhf': '11', 'ppc64el': '8', 'riscv64': '10', 's390x': '10'}> +CONFIG_PAGE_COUNTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_EXTENSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PAGE_IDLE_FLAG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_MAPCOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_OFFSET policy<{'armhf': '0xC0000000', 'ppc64el': '0xc000000000000000', 'riscv64': '-'}> +CONFIG_PAGE_OWNER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PAGE_POOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_POOL_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_REPORTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_SHIFT policy<{'amd64': '12', 'arm64-generic': '12', 'arm64-generic-64k': '16', 'armhf': '12', 'ppc64el': '16', 'riscv64': '12', 's390x': '12'}> +CONFIG_PAGE_SIZE_4KB policy<{'amd64': 'y', 'arm64-generic': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_SIZE_64KB policy<{'arm64-generic-64k': 'y', 'ppc64el': 'y'}> +CONFIG_PAGE_SIZE_LESS_THAN_256KB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_SIZE_LESS_THAN_64KB policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAGE_TABLE_CHECK policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_PAHOLE_HAS_LANG_EXCLUDE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PAHOLE_VERSION policy<{'amd64': '131', 'arm64': '131', 'armhf': '131', 'ppc64el': '131', 'riscv64': '131', 's390x': '131'}> +CONFIG_PALMAS_GPADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PANASONIC_LAPTOP policy<{'amd64': 'm'}> +CONFIG_PANEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PANEL_CHANGE_MESSAGE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PANEL_PARPORT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_PANEL_PROFILE policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5'}> +CONFIG_PANIC_TIMEOUT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '10', 'riscv64': '0', 's390x': '0'}> +CONFIG_PANTHERLORD_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PAPR_SCM policy<{'ppc64el': 'm'}> +CONFIG_PARAVIRT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARAVIRT_CLOCK policy<{'amd64': 'y'}> +CONFIG_PARAVIRT_SPINLOCKS policy<{'amd64': 'y'}> +CONFIG_PARAVIRT_TIME_ACCOUNTING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n'}> +CONFIG_PARAVIRT_XXL policy<{'amd64': 'y'}> +CONFIG_PARMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PARPORT_1284 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARPORT_NOT_PC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARPORT_PANEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PARPORT_PC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PARPORT_PC_FIFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PARPORT_PC_PCMCIA policy<{'amd64': 'm'}> +CONFIG_PARPORT_PC_SUPERIO policy<{'amd64': 'n', 'armhf': 'n', 'ppc64el': 'n'}> +CONFIG_PARPORT_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PARTITION_ADVANCED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PATA_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_PATA_ALI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_AMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_ARTOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_ATIIXP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_ATP867X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_CMD640_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_CMD64X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_CYPRESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_EFAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT366 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT37X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT3X2N policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_HPT3X3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PATA_IT8213 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_IT821X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_JMICRON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_MARVELL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_MPIIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NETCELL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NINJA32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NS87410 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_NS87415 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_OF_PLATFORM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PATA_OLDPIIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_OPTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_OPTIDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_ATEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_BPCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_BPCK6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_COMM policy<{'amd64': 'm', 'arm64': 'n', 'arm64-generic-64k': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_DSTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_EPAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_EPATC8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PATA_PARPORT_EPIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FIT2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FIT3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FRIQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_FRPW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_KBIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_KTTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_ON20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PARPORT_ON26 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_PATA_PCMCIA policy<{'amd64': 'm'}> +CONFIG_PATA_PDC2027X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_PDC_OLD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_PLATFORM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_RADISYS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_RDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_RZ1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SERVERWORKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SIL680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_SIS policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_TIMINGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PATA_TOSHIBA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_TRIFLEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PATA_WINBOND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PC104 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PC300TOO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PC87413_WDT policy<{'amd64': 'm'}> +CONFIG_PCC policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PCCARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCCARD_NONSTATIC policy<{'amd64': 'y'}> +CONFIG_PCENGINES_APU2 policy<{'amd64': 'm'}> +CONFIG_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI200SYN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCIEAER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEAER_INJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIEASPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIEASPM_PERFORMANCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIEASPM_POWERSAVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIEASPM_POWER_SUPERSAVE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_AL policy<{'arm64': 'y'}> +CONFIG_PCIE_ALTERA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ALTERA_MSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_AMD_MDB policy<{'arm64': 'y'}> +CONFIG_PCIE_APPLE policy<{'arm64': 'm'}> +CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR policy<{'arm64': '0xfffff000'}> +CONFIG_PCIE_ARMADA_8K policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ASPEED policy<{'armhf': 'y'}> +CONFIG_PCIE_BUS_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_BUS_PEER2PEER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_BUS_PERFORMANCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_BUS_SAFE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_BUS_TUNE_OFF policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_CADENCE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_EP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT_EP policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_CADENCE_PLAT_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_DPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_DW_EP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_PLAT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_PLAT_EP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_DW_PLAT_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_ECRC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCIE_EDR policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_HISI_ERR policy<{'arm64': 'y'}> +CONFIG_PCIE_HISI_STB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_KEEMBAY policy<{'arm64': 'y'}> +CONFIG_PCIE_KEEMBAY_EP policy<{'arm64': 'y'}> +CONFIG_PCIE_KEEMBAY_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_KIRIN policy<{'arm64': 'y'}> +CONFIG_PCIE_LAYERSCAPE_GEN4 policy<{'arm64': 'n'}> +CONFIG_PCIE_MEDIATEK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_MEDIATEK_GEN3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_MICROCHIP_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_MOBIVEIL_PLAT policy<{'arm64': 'n'}> +CONFIG_PCIE_NXP_S32G policy<{'arm64': 'y'}> +CONFIG_PCIE_PLDA_HOST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_PME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_PTM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_QCOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_QCOM_COMMON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_QCOM_EP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_RCAR_GEN4 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_GEN4_EP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_GEN4_HOST policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_RCAR_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_RENESAS_RZG3S_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_DW_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCIE_ROCKCHIP_HOST policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCIE_SG2042_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_SOPHGO_DW policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PCIE_STM32_EP policy<{'arm64': 'm'}> +CONFIG_PCIE_STM32_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194 policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194_EP policy<{'arm64': 'm'}> +CONFIG_PCIE_TEGRA194_HOST policy<{'arm64': 'm'}> +CONFIG_PCIE_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_TPH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCIE_VISCONTI_HOST policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCIE_XILINX_CPM policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX_DMA_PL policy<{'arm64': 'y'}> +CONFIG_PCIE_XILINX_NWL policy<{'arm64': 'y'}> +CONFIG_PCIPCWATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PCI_AARDVARK policy<{'arm64': 'y'}> +CONFIG_PCI_ATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_BRIDGE_EMUL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_DIRECT policy<{'amd64': 'y'}> +CONFIG_PCI_DOE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_DOMAINS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_DOMAINS_GENERIC policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCI_DRA7XX policy<{'armhf': 'm'}> +CONFIG_PCI_DRA7XX_EP policy<{'armhf': 'm'}> +CONFIG_PCI_DRA7XX_HOST policy<{'armhf': 'm'}> +CONFIG_PCI_ECAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT_CONFIGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT_MSI_DOORBELL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_ENDPOINT_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_EPF_MHI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCI_EPF_NTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PCI_EPF_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PCI_EPF_VNTB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCI_EXYNOS policy<{'armhf': 'n'}> +CONFIG_PCI_FTPCI100 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_HISI policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_HOST_GENERIC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_HOST_THUNDER_ECAM policy<{'arm64': 'y'}> +CONFIG_PCI_HOST_THUNDER_PEM policy<{'arm64': 'y'}> +CONFIG_PCI_HYPERV policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_PCI_HYPERV_INTERFACE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_PCI_IDE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_IMX6 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_IMX6_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_IMX6_HOST policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_IOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_J721E policy<{'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PCI_J721E_EP policy<{'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PCI_J721E_HOST policy<{'arm64': 'y', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PCI_KEYSTONE_EP policy<{'arm64': 'y'}> +CONFIG_PCI_KEYSTONE_HOST policy<{'arm64': 'y'}> +CONFIG_PCI_KEYSTONE_TRISTATE policy<{'arm64': 'y'}> +CONFIG_PCI_LABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_PCI_LAYERSCAPE policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_PCI_LAYERSCAPE_EP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_LOCKLESS_CONFIG policy<{'amd64': 'y'}> +CONFIG_PCI_MMCONFIG policy<{'amd64': 'y'}> +CONFIG_PCI_MSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_MSI_ARCH_FALLBACKS policy<{'ppc64el': 'y', 's390x': 'y'}> +CONFIG_PCI_MVEBU policy<{'armhf': 'm'}> +CONFIG_PCI_NPEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PCI_P2PDMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_PASID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PCI_PF_STUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_PRI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PCI_PWRCTRL policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_PWRCTRL_PWRSEQ policy<{'arm64': 'm'}> +CONFIG_PCI_PWRCTRL_SLOT policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_PWRCTRL_TC9563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_QUIRKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_RCAR_GEN2 policy<{'armhf': 'y'}> +CONFIG_PCI_REALLOC_ENABLE_AUTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCI_SKY1_HOST policy<{'arm64': 'm'}> +CONFIG_PCI_STUB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_SW_SWITCHTEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PCI_SYSCALL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_PCI_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PCI_TSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PCI_V3_SEMI policy<{'armhf': 'y'}> +CONFIG_PCI_XEN policy<{'amd64': 'y'}> +CONFIG_PCI_XGENE policy<{'arm64': 'y'}> +CONFIG_PCI_XGENE_MSI policy<{'arm64': 'y'}> +CONFIG_PCMCIA policy<{'amd64': 'm', 'arm64': 'n', 'armhf': 'n', 'ppc64el': '-'}> +CONFIG_PCMCIA_3C574 policy<{'amd64': 'm'}> +CONFIG_PCMCIA_3C589 policy<{'amd64': 'm'}> +CONFIG_PCMCIA_AHA152X policy<{'amd64': 'm'}> +CONFIG_PCMCIA_AXNET policy<{'amd64': 'm'}> +CONFIG_PCMCIA_FDOMAIN policy<{'amd64': 'm'}> +CONFIG_PCMCIA_FMVJ18X policy<{'amd64': 'm'}> +CONFIG_PCMCIA_LOAD_CIS policy<{'amd64': 'y'}> +CONFIG_PCMCIA_NMCLAN policy<{'amd64': 'm'}> +CONFIG_PCMCIA_PCNET policy<{'amd64': 'm'}> +CONFIG_PCMCIA_QLOGIC policy<{'amd64': 'm'}> +CONFIG_PCMCIA_SMC91C92 policy<{'amd64': 'm'}> +CONFIG_PCMCIA_SYM53C500 policy<{'amd64': 'm'}> +CONFIG_PCMCIA_XIRC2PS policy<{'amd64': 'm'}> +CONFIG_PCMCIA_XIRCOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_PCNET32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PCPU_DEV_REFCNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PCP_BATCH_SCALE_MAX policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5', 's390x': '5'}> +CONFIG_PCSPKR_PLATFORM policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_PCS_LYNX policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCS_MTK_LYNXI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PCS_RZN1_MIIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PCS_XPCS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PD6729 policy<{'amd64': 'm'}> +CONFIG_PDC_ADMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PDS_CORE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PDS_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PDS_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PECI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PECI_ASPEED policy<{'armhf': 'm'}> +CONFIG_PECI_CPU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PECI_NPCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PERCPU_STATS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PERCPU_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PERF_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PERF_EVENTS_AMD_BRS policy<{'amd64': 'y'}> +CONFIG_PERF_EVENTS_AMD_POWER policy<{'amd64': 'n'}> +CONFIG_PERF_EVENTS_AMD_UNCORE policy<{'amd64': 'm'}> +CONFIG_PERF_EVENTS_INTEL_CSTATE policy<{'amd64': 'm'}> +CONFIG_PERF_EVENTS_INTEL_RAPL policy<{'amd64': 'm'}> +CONFIG_PERF_EVENTS_INTEL_UNCORE policy<{'amd64': 'y'}> +CONFIG_PERF_GUEST_MEDIATED_PMU policy<{'amd64': 'y'}> +CONFIG_PERF_USE_VMALLOC policy<{'armhf': 'y'}> +CONFIG_PERSISTENT_HUGE_ZERO_FOLIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PERSISTENT_KEYRINGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PER_VMA_LOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PER_VMA_LOCK_STATS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PFAULT policy<{'s390x': 'y'}> +CONFIG_PFCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PGTABLE_HAS_HUGE_LEAVES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PGTABLE_LEVELS policy<{'amd64': '5', 'arm64': '4', 'arm64-generic-64k': '3', 'armhf': '3', 'ppc64el': '4', 'riscv64': '5', 's390x': '5'}> +CONFIG_PHANTOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHYLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PHYLIB_LEDS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PHYLINK policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PHYSICAL_ALIGN policy<{'amd64': '0x200000'}> +CONFIG_PHYSICAL_START policy<{'amd64': '0x1000000', 'ppc64el': '0x00000000'}> +CONFIG_PHYS_ADDR_T_64BIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PHY_AIROHA_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_AM654_SERDES policy<{'arm64': 'm'}> +CONFIG_PHY_APPLE_ATC policy<{'arm64': 'm'}> +CONFIG_PHY_BERLIN_SATA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_BERLIN_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_CADENCE_DPHY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_DPHY_RX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_SALVO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_SIERRA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CADENCE_TORRENT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_CAN_TRANSCEIVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHY_COMMON_PROPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PHY_CPCAP_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_DM816X_USB policy<{'armhf': 'm'}> +CONFIG_PHY_EXYNOS_DP_VIDEO policy<{'armhf': 'n'}> +CONFIG_PHY_EXYNOS_MIPI_VIDEO policy<{'armhf': 'n'}> +CONFIG_PHY_EXYNOS_PCIE policy<{'armhf': 'n'}> +CONFIG_PHY_FSL_IMX8MQ_USB policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_IMX8M_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_IMX8QM_HSIO policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_LYNX_28G policy<{'arm64': 'm'}> +CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_PHY_GOOGLE_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_HI3660_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HI3670_PCIE policy<{'arm64': 'm'}> +CONFIG_PHY_HI3670_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HI6220_USB policy<{'arm64': 'm'}> +CONFIG_PHY_HISI_INNO_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_HISTB_COMBPHY policy<{'arm64': 'm'}> +CONFIG_PHY_HIX5HD2_SATA policy<{'armhf': 'm'}> +CONFIG_PHY_INTEL_KEEMBAY_EMMC policy<{'arm64': 'm'}> +CONFIG_PHY_INTEL_KEEMBAY_USB policy<{'arm64': 'm'}> +CONFIG_PHY_INTEL_LGM_EMMC policy<{'amd64': 'm'}> +CONFIG_PHY_J721E_WIZ policy<{'arm64': 'm'}> +CONFIG_PHY_LAN966X_SERDES policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_MA35_USB policy<{'arm64': 'n'}> +CONFIG_PHY_MAPPHONE_MDM6600 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_MESON8B_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON8_HDMI_TX policy<{'armhf': 'm'}> +CONFIG_PHY_MESON_AXG_MIPI_DPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PHY_MESON_AXG_PCIE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_G12A_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_G12A_USB3_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MESON_GXL_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MIXEL_LVDS_PHY policy<{'arm64': 'm'}> +CONFIG_PHY_MIXEL_MIPI_DPHY policy<{'arm64': 'm'}> +CONFIG_PHY_MMP3_HSIC policy<{'armhf': 'm'}> +CONFIG_PHY_MMP3_USB policy<{'armhf': 'm'}> +CONFIG_PHY_MTK_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_MIPI_CSI_0_5 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_MIPI_DSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_TPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_UFS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_XFI_TPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MTK_XSPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_A3700_COMPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_A3700_UTMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_A38X_COMPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_CP110_COMPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_CP110_UTMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_MVEBU_SATA policy<{'armhf': 'y'}> +CONFIG_PHY_NXP_PTN3222 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_OCELOT_SERDES policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_PACKAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PHY_PXA_28NM_HSIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHY_PXA_28NM_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PHY_PXA_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_APQ8064_SATA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_EDP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_EUSB2_REPEATER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_IPQ4019_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_IPQ806X_SATA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_IPQ806X_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_M31_EUSB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_M31_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_MIPI_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_PCIE2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_COMBO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_PCIE_8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_UFS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QMP_USB_LEGACY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_QUSB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_SGMII_ETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PHY_QCOM_USB_HS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_QCOM_USB_HSIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_QCOM_USB_HS_28NM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_QCOM_USB_SS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_R8A779F0_ETHERNET_SERDES policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN3_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN3_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RCAR_GEN3_USB3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_DP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_DPHY_RX0 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_EMMC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_INNO_USB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_PCIE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_TYPEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_ROCKCHIP_USBDP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RTK_RTD_USB2PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RTK_RTD_USB3PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_RZ_G3E_USB3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_SAMSUNG_UFS policy<{'armhf': 'n'}> +CONFIG_PHY_SAMSUNG_USB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PHY_SNPS_EUSB2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_SOPHGO_CV1800_USB2 policy<{'arm64': 'm'}> +CONFIG_PHY_SPARX5_SERDES policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_PHY_STM32_COMBOPHY policy<{'arm64': 'm'}> +CONFIG_PHY_STM32_USBPHYC policy<{'arm64': 'm'}> +CONFIG_PHY_SUN4I_USB policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUN50I_USB3 policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUN6I_MIPI_DPHY policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUN9I_USB policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PHY_SUNPLUS_USB policy<{'armhf': 'm'}> +CONFIG_PHY_TEGRA194_P2U policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_TEGRA_XUSB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PHY_TI_GMII_SEL policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_PHY_TUSB1210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PHY_XGENE policy<{'arm64': 'y'}> +CONFIG_PHY_XILINX_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_PID_IN_CONTEXTIDR policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_PID_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PINCONF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PINCTRL_AC5 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AIROHA policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ALDERLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_AMD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_AMDISP policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': '-', 'riscv64': 'm'}> +CONFIG_PINCTRL_AMLOGIC_A4 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_AMLOGIC_C3 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_AMLOGIC_T7 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_APPLE_GPIO policy<{'arm64': 'm'}> +CONFIG_PINCTRL_APQ8064 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_APQ8084 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_ARMADA_370 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_375 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_37XX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_38X policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_39X policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ARMADA_AP806 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_CP110 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_ARMADA_XP policy<{'armhf': 'y'}> +CONFIG_PINCTRL_AS370 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_AS3722 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_ASPEED policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ASPEED_G6 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_AW9523 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_AXP209 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_BAYTRAIL policy<{'amd64': 'y'}> +CONFIG_PINCTRL_BERLIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG2 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG2CD policy<{'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG2Q policy<{'armhf': 'y'}> +CONFIG_PINCTRL_BERLIN_BG4CT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_BM1880 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_BROXTON policy<{'amd64': 'm'}> +CONFIG_PINCTRL_CANNONLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_CEDARFORK policy<{'amd64': 'm'}> +CONFIG_PINCTRL_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_CS47L15 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L35 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L85 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L90 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CS47L92 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_CY8C95X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_DA9062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_DENVERTON policy<{'amd64': 'm'}> +CONFIG_PINCTRL_DOVE policy<{'armhf': 'y'}> +CONFIG_PINCTRL_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_EMMITSBURG policy<{'amd64': 'm'}> +CONFIG_PINCTRL_EXYNOS policy<{'armhf': 'y'}> +CONFIG_PINCTRL_EXYNOS_ARM policy<{'armhf': 'y'}> +CONFIG_PINCTRL_GEMINILAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_GLYMUR policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ICELAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_IMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_IMX50 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX51 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6Q policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6SL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6SLL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6SX policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX6UL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX7D policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX7ULP policy<{'armhf': 'y'}> +CONFIG_PINCTRL_IMX8DXL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MM policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MN policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8MQ policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8QM policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8QXP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_IMX8ULP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX91 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX93 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_IMX_SCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_INTEL policy<{'amd64': 'y'}> +CONFIG_PINCTRL_INTEL_PLATFORM policy<{'amd64': 'm'}> +CONFIG_PINCTRL_IPQ4019 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_IPQ5018 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ5332 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ5424 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ6018 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ8064 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_IPQ8074 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_IPQ9574 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_JASPERLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_KAANAPALI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_PINCTRL_LAKEFIELD policy<{'amd64': 'm'}> +CONFIG_PINCTRL_LEWISBURG policy<{'amd64': 'm'}> +CONFIG_PINCTRL_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_LPASS_LPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_LYNXPOINT policy<{'amd64': 'm'}> +CONFIG_PINCTRL_MA35 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MA35D1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MADERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MAX77620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MCP23S08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PINCTRL_MCP23S08_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MCP23S08_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_MDM9607 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_MDM9615 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MESON8 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MESON8B policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MESON8_PMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MESON_A1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_AXG policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_AXG_PMX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_G12A policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_GXBB policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_GXL policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MESON_S4 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_METEORLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_METEORPOINT policy<{'amd64': 'm'}> +CONFIG_PINCTRL_MICROCHIP_SGPIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_MILOS policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MLXBF3 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MSM8226 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8660 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8909 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_MSM8917 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_MSM8953 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8960 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MSM8976 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8994 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8996 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8998 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MSM8X74 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_MT2701 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT2712 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6397 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MT6765 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6779 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_MT6795 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6797 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6878 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT6893 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7622 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7623 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT7629 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT7981 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7986 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT7988 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8127 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT8135 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_MT8167 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8173 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8183 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8186 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8188 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8189 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8192 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8195 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8196 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8365 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8516 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MTK_MOORE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MTK_PARIS policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MTK_V2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_MVEBU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_NPCM7XX policy<{'armhf': 'y'}> +CONFIG_PINCTRL_NPCM8XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_OCELOT policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_OWL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_PALMAS policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_PEF2256 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_PFC_EMEV2 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7740 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7742 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7743 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7744 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7745 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A77470 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A7778 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7779 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7790 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7791 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7792 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7793 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A7794 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PFC_R8A77951 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77960 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77961 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77965 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77970 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77980 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77990 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A77995 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_PFC_SH73A0 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_PIC64GX policy<{'arm64': 'y'}> +CONFIG_PINCTRL_POLARFIRE_SOC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_QCM2290 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCOM_SPMI_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_QCOM_SSBI_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_QCS404 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCS615 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QCS8300 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QDF2XXX policy<{'arm64': 'm'}> +CONFIG_PINCTRL_QDU1000 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_RENESAS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_RK805 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_RP1 policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_RTD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RTD1315E policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RTD1319D policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RTD1619B policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_RZA1 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_RZA2 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_RZG2L policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RZN1 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_RZT2H policy<{'arm64': 'y'}> +CONFIG_PINCTRL_RZV2M policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S32CC policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S32G2 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S500 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_S700 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_S900 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SA8775P policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SAMSUNG policy<{'armhf': 'y'}> +CONFIG_PINCTRL_SAR2130P policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC7180 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC7280 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC7280_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SC8180X policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC8280XP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SC8280XP_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PINCTRL_SDM660 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM660_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM670 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDM845 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SDX55 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_SDX65 policy<{'armhf': 'm'}> +CONFIG_PINCTRL_SDX75 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SH_PFC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_SH_PFC_GPIO policy<{'armhf': 'y'}> +CONFIG_PINCTRL_SINGLE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_SKY1 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SKY1_BASE policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM4250_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM4450 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6115 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6115_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6125 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6350 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM6375 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM7150 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8150 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8250 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8250_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8350 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8450 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8450_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8550 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8550_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8650 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8650_LPASS_LPI policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SM8750 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_SOPHGO_COMMON policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV1800B policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV1812H policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_CV18XX_OPS policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2000 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2002 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2042 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2042_OPS policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SOPHGO_SG2044 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PINCTRL_SPPCTL policy<{'armhf': 'y'}> +CONFIG_PINCTRL_SPRD policy<{'arm64': 'y'}> +CONFIG_PINCTRL_SPRD_SC9860 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32MP257 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STM32_HDP policy<{'arm64': 'y'}> +CONFIG_PINCTRL_STMFX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_SUN20I_D1 policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN4I_A10 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A100 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A100_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A64 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_A64_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H5 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H6 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H616 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H616_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN50I_H6_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN55I_A523 policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN55I_A523_R policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN5I policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN6I_A31 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN6I_A31_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A23 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A23_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A33 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A83T policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_A83T_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_H3 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_H3_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN8I_V3S policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN9I_A80 policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUN9I_A80_R policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PINCTRL_SUNRISEPOINT policy<{'amd64': 'm'}> +CONFIG_PINCTRL_SUNXI policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_PINCTRL_SX150X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PINCTRL_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA114 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA124 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA186 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA194 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA20 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA210 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA234 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TEGRA30 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TEGRA_XUSB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PINCTRL_TIGERLAKE policy<{'amd64': 'm'}> +CONFIG_PINCTRL_TI_IODELAY policy<{'armhf': 'y'}> +CONFIG_PINCTRL_TMPV7700 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_TPS6594 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINCTRL_UPBOARD policy<{'amd64': 'm'}> +CONFIG_PINCTRL_VF610 policy<{'armhf': 'y'}> +CONFIG_PINCTRL_VISCONTI policy<{'arm64': 'y'}> +CONFIG_PINCTRL_X1E80100 policy<{'arm64': 'm'}> +CONFIG_PINCTRL_ZYNQMP policy<{'arm64': 'm'}> +CONFIG_PING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PINMUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PJ4B_ERRATA_4742 policy<{'armhf': 'y'}> +CONFIG_PKCS7_MESSAGE_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PKCS7_TEST_KEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PKCS7_WAIVE_AUTHATTRS_REJECTION_FOR_MLDSA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PKCS8_PRIVATE_KEY_PARSER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PKEY policy<{'s390x': 'm'}> +CONFIG_PKEY_CCA policy<{'s390x': 'm'}> +CONFIG_PKEY_EP11 policy<{'s390x': 'm'}> +CONFIG_PKEY_PCKMO policy<{'s390x': 'm'}> +CONFIG_PKEY_UV policy<{'s390x': 'm'}> +CONFIG_PL310_ERRATA_588369 policy<{'armhf': 'y'}> +CONFIG_PL310_ERRATA_727915 policy<{'armhf': 'y'}> +CONFIG_PL310_ERRATA_753970 policy<{'armhf': 'y'}> +CONFIG_PL310_ERRATA_769419 policy<{'armhf': 'y'}> +CONFIG_PL320_MBOX policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_PL330_DMA policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_PL353_SMC policy<{'armhf': 'm'}> +CONFIG_PLATFORM_MHU policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLATFORM_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLAT_ORION policy<{'armhf': 'y'}> +CONFIG_PLAT_PXA policy<{'armhf': 'y'}> +CONFIG_PLAT_SPEAR policy<{'armhf': 'n'}> +CONFIG_PLAT_VERSATILE policy<{'armhf': 'y'}> +CONFIG_PLAYSTATION_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PLDMFW policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PLFXLC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PLX_DMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PM8916_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PMIC_ADP5520 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PMIC_DA903X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PMIC_DA9052 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PMIC_OPREGION policy<{'amd64': 'y', 'arm64': 'n', 'riscv64': 'y'}> +CONFIG_PMS7003 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PMU_SYSFS policy<{'ppc64el': 'n'}> +CONFIG_PM_ADVANCED_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_AUTOSLEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PM_CLK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_DEVFREQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PM_DEVFREQ_EVENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_GENERIC_DOMAINS_SLEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_NOTIFIER_ERROR_INJECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PM_OPP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_QOS_CPU_SYSTEM_WAKEUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP_SMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_SLEEP_SMP_NONZERO_CPU policy<{'ppc64el': 'y'}> +CONFIG_PM_STD_PARTITION policy<{'amd64': '""', 'armhf': '""', 'riscv64': '""'}> +CONFIG_PM_TEST_SUSPEND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PM_TRACE policy<{'amd64': 'y'}> +CONFIG_PM_TRACE_RTC policy<{'amd64': 'y'}> +CONFIG_PM_USERSPACE_AUTOSLEEP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PM_WAKELOCKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_WAKELOCKS_GC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PM_WAKELOCKS_LIMIT policy<{'amd64': '100', 'arm64': '100', 'armhf': '100', 'ppc64el': '100', 'riscv64': '100'}> +CONFIG_PNFS_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PNFS_FILE_LAYOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PNFS_FLEXFILE_LAYOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PNP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PNPACPI policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PNP_DEBUG_MESSAGES policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_POLARFIRE_SOC_AUTO_UPDATE policy<{'arm64': 'm'}> +CONFIG_POLARFIRE_SOC_MAILBOX policy<{'arm64': 'm'}> +CONFIG_POLARFIRE_SOC_SYSCONS policy<{'arm64': 'y'}> +CONFIG_POLARFIRE_SOC_SYS_CTRL policy<{'arm64': 'm'}> +CONFIG_POLYNOMIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PORTABLE policy<{'riscv64': 'y'}> +CONFIG_PORTWELL_EC policy<{'amd64': 'm'}> +CONFIG_POSIX_AUX_CLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_CPU_TIMERS_TASK_WORK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_MQUEUE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_MQUEUE_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POSIX_TIMERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POWER10_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWER7_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWER8_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWER9_CPU policy<{'ppc64el': 'n'}> +CONFIG_POWERCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_POWERNV_CPUFREQ policy<{'ppc64el': 'y'}> +CONFIG_POWERNV_CPUIDLE policy<{'ppc64el': 'y'}> +CONFIG_POWERNV_OP_PANEL policy<{'ppc64el': 'm'}> +CONFIG_POWERPC64_CPU policy<{'ppc64el': 'y'}> +CONFIG_POWER_MLXBF policy<{'arm64': 'm'}> +CONFIG_POWER_RESET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POWER_RESET_AS3722 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_ATC260X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_POWER_RESET_AXXIA policy<{'armhf': 'y'}> +CONFIG_POWER_RESET_BRCMKONA policy<{'armhf': 'y'}> +CONFIG_POWER_RESET_GPIO policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_GPIO_RESTART policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_HISI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_LINKSTATION policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_POWER_RESET_LTC2952 policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_MACSMC policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_MSM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_MT6323 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_OCELOT_RESET policy<{'arm64': 'y'}> +CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_QCOM_PON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_POWER_RESET_QNAP policy<{'armhf': 'n'}> +CONFIG_POWER_RESET_REGULATOR policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_RESTART policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_POWER_RESET_RMOBILE policy<{'armhf': 'm'}> +CONFIG_POWER_RESET_SC27XX policy<{'arm64': 'm'}> +CONFIG_POWER_RESET_SYSCON policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_SYSCON_POWEROFF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_TORADEX_EC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_POWER_RESET_TPS65086 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_POWER_RESET_VERSATILE policy<{'armhf': 'y'}> +CONFIG_POWER_RESET_VEXPRESS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_POWER_RESET_XGENE policy<{'arm64': 'n'}> +CONFIG_POWER_SEQUENCING policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_POWER_SEQUENCING_PCIE_M2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_POWER_SEQUENCING_QCOM_WCN policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_POWER_SUPPLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_POWER_SUPPLY_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_POWER_SUPPLY_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPC policy<{'ppc64el': 'y'}> +CONFIG_PPC64 policy<{'ppc64el': 'y'}> +CONFIG_PPC64_BOOT_WRAPPER policy<{'ppc64el': 'y'}> +CONFIG_PPC64_ELF_ABI_V2 policy<{'ppc64el': 'y'}> +CONFIG_PPC64_PROC_SYSTEMCFG policy<{'ppc64el': 'y'}> +CONFIG_PPC64_SUPPORTS_MEMORY_FAILURE policy<{'ppc64el': 'y'}> +CONFIG_PPC_4K_PAGES policy<{'ppc64el': 'n'}> +CONFIG_PPC_64K_PAGES policy<{'ppc64el': 'y'}> +CONFIG_PPC_64S_HASH_MMU policy<{'ppc64el': 'y'}> +CONFIG_PPC_BARRIER_NOSPEC policy<{'ppc64el': 'y'}> +CONFIG_PPC_BOOK3E_64 policy<{'ppc64el': 'n'}> +CONFIG_PPC_BOOK3S policy<{'ppc64el': 'y'}> +CONFIG_PPC_BOOK3S_64 policy<{'ppc64el': 'y'}> +CONFIG_PPC_BOOK3S_IDLE policy<{'ppc64el': 'y'}> +CONFIG_PPC_COPRO_BASE policy<{'ppc64el': 'y'}> +CONFIG_PPC_DAWR policy<{'ppc64el': 'y'}> +CONFIG_PPC_DENORMALISATION policy<{'ppc64el': 'y'}> +CONFIG_PPC_DISABLE_WERROR policy<{'ppc64el': 'n'}> +CONFIG_PPC_DOORBELL policy<{'ppc64el': 'y'}> +CONFIG_PPC_DT_CPU_FTRS policy<{'ppc64el': 'y'}> +CONFIG_PPC_EARLY_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_EMULATED_STATS policy<{'ppc64el': 'n'}> +CONFIG_PPC_EPAPR_HV_BYTECHAN policy<{'ppc64el': 'n'}> +CONFIG_PPC_FPU policy<{'ppc64el': 'y'}> +CONFIG_PPC_FPU_REGS policy<{'ppc64el': 'y'}> +CONFIG_PPC_FTRACE_OUT_OF_LINE policy<{'ppc64el': 'y'}> +CONFIG_PPC_FTRACE_OUT_OF_LINE_NUM_RESERVE policy<{'ppc64el': '32768'}> +CONFIG_PPC_HASH_MMU_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_HAS_LBARX_LHARX policy<{'ppc64el': 'y'}> +CONFIG_PPC_HAVE_PMU_SUPPORT policy<{'ppc64el': 'y'}> +CONFIG_PPC_I8259 policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICP_HV policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICP_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICS_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_ICS_RTAS policy<{'ppc64el': 'y'}> +CONFIG_PPC_INDIRECT_PIO policy<{'ppc64el': 'y'}> +CONFIG_PPC_IRQ_SOFT_MASK_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_KUAP policy<{'ppc64el': 'y'}> +CONFIG_PPC_KUAP_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_KUEP policy<{'ppc64el': 'y'}> +CONFIG_PPC_MEMTRACE policy<{'ppc64el': 'y'}> +CONFIG_PPC_MICROWATT policy<{'ppc64el': 'y'}> +CONFIG_PPC_MSI_BITMAP policy<{'ppc64el': 'y'}> +CONFIG_PPC_OF_BOOT_TRAMPOLINE policy<{'ppc64el': 'y'}> +CONFIG_PPC_P7_NAP policy<{'ppc64el': 'y'}> +CONFIG_PPC_PERF_CTRS policy<{'ppc64el': 'y'}> +CONFIG_PPC_PKEY policy<{'ppc64el': 'y'}> +CONFIG_PPC_POWERNV policy<{'ppc64el': 'y'}> +CONFIG_PPC_PROT_SAO_LPAR policy<{'ppc64el': 'n'}> +CONFIG_PPC_PSERIES policy<{'ppc64el': 'y'}> +CONFIG_PPC_QUEUED_SPINLOCKS policy<{'ppc64el': 'n'}> +CONFIG_PPC_RADIX_BROADCAST_TLBIE policy<{'ppc64el': 'y'}> +CONFIG_PPC_RADIX_MMU policy<{'ppc64el': 'y'}> +CONFIG_PPC_RADIX_MMU_DEFAULT policy<{'ppc64el': 'y'}> +CONFIG_PPC_RFI_SRR_DEBUG policy<{'ppc64el': 'n'}> +CONFIG_PPC_RTAS policy<{'ppc64el': 'y'}> +CONFIG_PPC_RTAS_DAEMON policy<{'ppc64el': 'y'}> +CONFIG_PPC_SMLPAR policy<{'ppc64el': 'y'}> +CONFIG_PPC_SMP_MUXED_IPI policy<{'ppc64el': 'y'}> +CONFIG_PPC_SPLPAR policy<{'ppc64el': 'y'}> +CONFIG_PPC_SUBPAGE_PROT policy<{'ppc64el': 'y'}> +CONFIG_PPC_SVM policy<{'ppc64el': 'y'}> +CONFIG_PPC_THP policy<{'ppc64el': 'y'}> +CONFIG_PPC_TRANSACTIONAL_MEM policy<{'ppc64el': 'y'}> +CONFIG_PPC_UDBG_16550 policy<{'ppc64el': 'y'}> +CONFIG_PPC_UV policy<{'ppc64el': 'y'}> +CONFIG_PPC_VAS policy<{'ppc64el': 'y'}> +CONFIG_PPC_WATCHDOG policy<{'ppc64el': 'y'}> +CONFIG_PPC_WERROR policy<{'ppc64el': 'y'}> +CONFIG_PPC_XICS policy<{'ppc64el': 'y'}> +CONFIG_PPC_XIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_XIVE_NATIVE policy<{'ppc64el': 'y'}> +CONFIG_PPC_XIVE_SPAPR policy<{'ppc64el': 'y'}> +CONFIG_PPDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PPP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PPPOATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PPPOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPPOE_HASH_BITS policy<{'amd64': '4', 'arm64': '4', 'armhf': '4', 'ppc64el': '4', 'riscv64': '4'}> +CONFIG_PPPOE_HASH_BITS_1 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PPPOE_HASH_BITS_2 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PPPOE_HASH_BITS_4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPPOE_HASH_BITS_8 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_PPPOL2TP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_ASYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_BSDCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_DEFLATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPP_MPPE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPP_MULTILINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PPP_SYNC_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PPS_CLIENT_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PPS_CLIENT_KTIMER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PPS_CLIENT_LDISC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PPS_CLIENT_PARPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PPS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PPS_GENERATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PPS_GENERATOR_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PPS_GENERATOR_TIO policy<{'amd64': 'm'}> +CONFIG_PPTP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PREEMPT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PREEMPTION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPTIRQ_DELAY_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PREEMPTIRQ_TRACEPOINTS policy<{'armhf': 'y'}> +CONFIG_PREEMPT_BUILD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_COUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_LAZY policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_NOTIFIERS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PREEMPT_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PREEMPT_RT policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_PREEMPT_TRACER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PREEMPT_VOLUNTARY policy<{'amd64': '-', 'arm64': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_PREEMPT_VOLUNTARY_BUILD policy<{'armhf': 'y', 'ppc64el': '-', 's390x': '-'}> +CONFIG_PREFIX_SYMBOLS policy<{'amd64': 'y'}> +CONFIG_PRESTERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PRESTERA_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PREVENT_FIRMWARE_BUILD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRIME_NUMBERS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PRINTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRINTK_CALLER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PRINTK_EXECUTION_CTX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRINTK_INDEX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PRINTK_TIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PRINT_STACK_DEPTH policy<{'ppc64el': '64'}> +CONFIG_PROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROBE_EVENTS_BTF_ARGS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROCESSOR_SELECT policy<{'amd64': 'y'}> +CONFIG_PROC_CHILDREN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_CPU_RESCTRL policy<{'amd64': 'y'}> +CONFIG_PROC_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_KCORE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_MEM_ALWAYS_FORCE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_MEM_FORCE_PTRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROC_MEM_NO_FORCE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROC_PAGE_MONITOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_PID_ARCH_STATUS policy<{'amd64': 'y'}> +CONFIG_PROC_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_THERMAL_MMIO_RAPL policy<{'amd64': 'm'}> +CONFIG_PROC_VMCORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_VMCORE_DEVICE_DUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROC_VMCORE_DEVICE_RAM policy<{'s390x': 'y'}> +CONFIG_PROFILE_ALL_BRANCHES policy<{'riscv64': 'n'}> +CONFIG_PROFILE_ANNOTATED_BRANCHES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROFILING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PROVE_LOCKING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_PROVIDE_OHCI1394_DMA_INIT policy<{'amd64': 'n'}> +CONFIG_PRU_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PSAMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PSERIES_CPUIDLE policy<{'ppc64el': 'y'}> +CONFIG_PSERIES_ENERGY policy<{'ppc64el': 'm'}> +CONFIG_PSERIES_PLPKS policy<{'ppc64el': 'y'}> +CONFIG_PSERIES_PLPKS_SED policy<{'ppc64el': 'y'}> +CONFIG_PSERIES_WDT policy<{'ppc64el': 'm'}> +CONFIG_PSE_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_PSE_PD692X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSE_REGULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSE_SI3474 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSE_TPS23881 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PSTORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PSTORE_BLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PSTORE_BLK_BLKDEV policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '-'}> +CONFIG_PSTORE_BLK_CONSOLE_SIZE policy<{'armhf': '64'}> +CONFIG_PSTORE_BLK_KMSG_SIZE policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_PSTORE_BLK_MAX_REASON policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2', 's390x': '-'}> +CONFIG_PSTORE_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PSTORE_CONSOLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PSTORE_DEFAULT_KMSG_BYTES policy<{'amd64': '10240', 'arm64': '10240', 'armhf': '10240', 'ppc64el': '10240', 'riscv64': '10240'}> +CONFIG_PSTORE_FTRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PSTORE_PMSG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PSTORE_RAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PSTORE_ZONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PTDUMP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PTDUMP_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'y'}> +CONFIG_PTDUMP_STAGE2_DEBUGFS policy<{'arm64': 'n'}> +CONFIG_PTE_MARKER_UFFD_WP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_PTP_1588_CLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_FC3W policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PTP_1588_CLOCK_IDT82P33 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PTP_1588_CLOCK_IDTCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_INES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_KVM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_PTP_1588_CLOCK_MOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_OCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PTP_1588_CLOCK_OPTIONAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_PTP_1588_CLOCK_QORIQ policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_PTP_1588_CLOCK_VMCLOCK policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_PTP_1588_CLOCK_VMW policy<{'amd64': 'm'}> +CONFIG_PTP_DFL_TOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PTP_NETC_V4_TIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_PTP_S390 policy<{'s390x': 'm'}> +CONFIG_PT_RECLAIM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_PUNIT_ATOM_DEBUG policy<{'amd64': 'm'}> +CONFIG_PVH policy<{'amd64': 'y'}> +CONFIG_PVPANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PVPANIC_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PVPANIC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWC_RZV2M policy<{'arm64': 'y'}> +CONFIG_PWM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_PWM_ADP5585 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_AIROHA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_APPLE policy<{'arm64': 'm'}> +CONFIG_PWM_ARGON_FAN_HAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_ATMEL_HLCDC_PWM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_ATMEL_TCB policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_AXI_PWMGEN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_BERLIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_CLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_CRC policy<{'amd64': 'y'}> +CONFIG_PWM_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_PWM_DWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_DWC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_FSL_FTM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_HIBVT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IMX1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IMX27 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IMX_TPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_IQS620A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_PWM_LP3943 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_LPSS policy<{'amd64': 'y'}> +CONFIG_PWM_LPSS_PCI policy<{'amd64': 'y'}> +CONFIG_PWM_LPSS_PLATFORM policy<{'amd64': 'y'}> +CONFIG_PWM_MAX7360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_MC33XS2410 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_MESON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_MTK_DISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_NTXEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWM_OMAP_DMTIMER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_PCA9685 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_PROVIDE_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PWM_PXA policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_PWM_RENESAS_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_RENESAS_RZG2L_GPT policy<{'arm64': 'm'}> +CONFIG_PWM_RENESAS_RZ_MTU3 policy<{'arm64': 'm'}> +CONFIG_PWM_RENESAS_TPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_SAMSUNG policy<{'armhf': 'n'}> +CONFIG_PWM_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_PWM_SOPHGO_SG2042 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_PWM_SPRD policy<{'arm64': 'm'}> +CONFIG_PWM_STM32 policy<{'arm64': 'm'}> +CONFIG_PWM_STM32_LP policy<{'arm64': 'm'}> +CONFIG_PWM_STMPE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_PWM_SUN4I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_PWM_SUNPLUS policy<{'armhf': 'm'}> +CONFIG_PWM_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_TIECAP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_TIEHRPWM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PWM_TWL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_TWL_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_PWM_VISCONTI policy<{'arm64': 'm'}> +CONFIG_PWM_XILINX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWRSEQ_EMMC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWRSEQ_SD8787 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PWRSEQ_SIMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_PXA168_ETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PXA1908_PM_DOMAINS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_PXA_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_PXA_SSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QAT_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA7000 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA7000_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA7000_UART policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA807X_PHY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCA808X_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QCA83XX_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QCM_DISPCC_2290 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCM_GCC_2290 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOMTEE policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_A53PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_A7PLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_AOSS_QMP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_APCS_IPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_APR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_BAM_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_BAM_DMUX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CLK_APCC_MSM8996 policy<{'arm64': 'm'}> +CONFIG_QCOM_CLK_APCS_MSM8916 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CLK_APCS_SDX55 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_QCOM_CLK_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CLK_RPMH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_CLK_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_COINCELL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_COMMAND_DB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_CPR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_CPUCP_MBOX policy<{'arm64': 'm'}> +CONFIG_QCOM_EBI2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_EMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QCOM_FALKOR_ERRATUM_1003 policy<{'arm64': 'y'}> +CONFIG_QCOM_FALKOR_ERRATUM_1009 policy<{'arm64': 'y'}> +CONFIG_QCOM_FALKOR_ERRATUM_E1041 policy<{'arm64': 'y'}> +CONFIG_QCOM_FASTRPC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_GDSC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_GENI_SE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_GPI_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_GSBI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_HFPLL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_HIDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QCOM_HIDMA_MGMT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QCOM_ICC_BWMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_INLINE_CRYPTO_ENGINE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_IOMMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_IPA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_IPCC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_IRQ_COMBINER policy<{'arm64': 'y'}> +CONFIG_QCOM_KRYO_L2_ACCESSORS policy<{'arm64': 'y'}> +CONFIG_QCOM_L2_PMU policy<{'arm64': 'y'}> +CONFIG_QCOM_L3_PMU policy<{'arm64': 'y'}> +CONFIG_QCOM_LLCC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_LMH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_MDT_LOADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_MPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_NET_PHYLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_OCMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_PBS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PDC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_PDR_HELPERS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PDR_MSG policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PD_MAPPER policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_QCOM_PIL_INFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_PM8XXX_XOADC policy<{'armhf': 'm'}> +CONFIG_QCOM_PMIC_GLINK policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PMIC_PDCHARGER_ULOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_PPE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_ADSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_MSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_PAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_Q6V5_WCSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_QMI_HELPERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_QSEECOM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_QSEECOM_UEFISECAPP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_RAMP_CTRL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RMTFS_MEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RPMH policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_RPMHPD policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_RPMPD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RPM_MASTER_STATS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_RPROC_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SCM policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'm'}> +CONFIG_QCOM_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SMEM_STATE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_SMP2P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SMSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SOCINFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_SPMI_ADC5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_SPMI_ADC_TM5 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPMI_IADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_SPMI_RRADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPMI_TEMP_ALARM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SPMI_VADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_SSC_BLOCK_BUS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_QCOM_STATS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_SYSMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_TSENS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_TZMEM policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'm'}> +CONFIG_QCOM_TZMEM_MODE_GENERIC policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'riscv64': 'y'}> +CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'n'}> +CONFIG_QCOM_UBWC_CONFIG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_VADC_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QCOM_WCNSS_CTRL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCOM_WCNSS_PIL policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_QCOM_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_CAMCC_615 policy<{'arm64': 'm'}> +CONFIG_QCS_DISPCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QCS_GCC_404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_GCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QCS_GCC_8300 policy<{'arm64': 'm'}> +CONFIG_QCS_GPUCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QCS_Q6SSTOP_404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_TURING_404 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QCS_VIDEOCC_615 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_QDIO policy<{'s390x': 'm'}> +CONFIG_QDU_ECPRICC_1000 policy<{'arm64': 'm'}> +CONFIG_QDU_GCC_1000 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_QED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QEDE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QEDF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QEDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QED_FCOE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_ISCSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_LL2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_OOO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_RDMA policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QED_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QETH policy<{'s390x': 'm'}> +CONFIG_QETH_L2 policy<{'s390x': 'm'}> +CONFIG_QETH_L3 policy<{'s390x': 'm'}> +CONFIG_QE_GPIO policy<{'ppc64el': 'y'}> +CONFIG_QE_TDM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_QE_USB policy<{'ppc64el': 'y'}> +CONFIG_QFMT_V1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_QFMT_V2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_QLA3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QLCNIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_QLCNIC_DCB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QLCNIC_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QLCNIC_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_QNX4FS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QNX6FS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_QNX6FS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QORIQ_CPUFREQ policy<{'arm64': 'm'}> +CONFIG_QORIQ_THERMAL policy<{'arm64': 'm'}> +CONFIG_QRTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_QRTR_MHI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QRTR_SMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QRTR_TUN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QSEMI_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_QTNFMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QTNFMAC_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_QUEUED_RWLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_QUEUED_SPINLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_QUICC_ENGINE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_QUOTA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_QUOTACTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_QUOTA_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_QUOTA_NETLINK_INTERFACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_QUOTA_TREE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_R6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_R8169 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_R8169_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RADIO_ADAPTERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_MAXIRADIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SAA7706H policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SHARK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SHARK2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SI470X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_SI476X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_TEA575X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_TEA5764 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RADIO_TEF6862 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RAID6_PQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RAID6_PQ_BENCHMARK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RAID_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RAMDAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RANDOM32_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RANDOMIZE_BASE policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDOMIZE_IDENTITY_BASE policy<{'s390x': 'n'}> +CONFIG_RANDOMIZE_KSTACK_OFFSET policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDOMIZE_MEMORY policy<{'amd64': 'y'}> +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING policy<{'amd64': '0xa'}> +CONFIG_RANDOMIZE_MODULE_REGION_FULL policy<{'arm64': 'y'}> +CONFIG_RANDOM_KMALLOC_CACHES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RANDSTRUCT_NONE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RAPIDIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_RAPIDIO_CHMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_CPS_GEN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_CPS_XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_RAPIDIO_DISC_TIMEOUT policy<{'amd64': '30', 'arm64': '30', 'armhf': '30', 'ppc64el': '30', 'riscv64': '30'}> +CONFIG_RAPIDIO_DMA_ENGINE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_RAPIDIO_ENUM_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_MPORT_CDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_RXS_GEN3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAPIDIO_TSI721 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RAS_CEC policy<{'amd64': 'y'}> +CONFIG_RAS_CEC_DEBUG policy<{'amd64': 'n'}> +CONFIG_RAS_FMPM policy<{'amd64': 'm'}> +CONFIG_RATIONAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RAVB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RAVE_SP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RAVE_SP_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RBTREE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCAR_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCAR_GEN3_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCAR_GYRO_ADC policy<{'armhf': 'm'}> +CONFIG_RCAR_REMOTEPROC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCAR_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RCU_CPU_STALL_CPUTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RCU_CPU_STALL_TIMEOUT policy<{'amd64': '60', 'arm64': '60', 'armhf': '60', 'ppc64el': '60', 'riscv64': '60', 's390x': '60'}> +CONFIG_RCU_EQS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_EXPERT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_RCU_NEED_SEGCBLIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RCU_REF_SCALE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_SCALE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_STALL_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RCU_TORTURE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RCU_TRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RC_ATI_REMOTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RC_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RC_DECODERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RC_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RC_LOOPBACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RC_MAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RC_XBOX_DVD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RDA_INTC policy<{'armhf': 'y'}> +CONFIG_RDA_TIMER policy<{'armhf': 'y'}> +CONFIG_RDMA_RXE policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDMA_SIW policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RDS_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RDS_TCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RD_BZIP2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_GZIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_LZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RD_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_READABLE_ASM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_READ_ONLY_THP_FOR_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_REALTEK_AUTOPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REALTEK_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_REALTEK_PHY_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REBOOT_MODE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REDMI_WMI policy<{'amd64': 'm'}> +CONFIG_REED_SOLOMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REED_SOLOMON_DEC16 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REED_SOLOMON_DEC8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REED_SOLOMON_ENC8 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REED_SOLOMON_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_REGMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_REGMAP_AC97 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGMAP_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_REGMAP_I3C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_REGMAP_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_REGMAP_SCCB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SLIMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SOUNDWIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SOUNDWIRE_MBQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REGMAP_SPI_AVMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_SPMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGMAP_W1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_REGULATOR_88PG86X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_88PM800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_88PM8607 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_88PM886 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AAT2870 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ACT8865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ACT8945A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AD5398 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ADP5055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ANATOP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_ARIZONA_LDO1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ARIZONA_MICSUPP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ARM_SCMI policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_REGULATOR_AS3711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_AS3722 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ATC260X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AW37503 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_AXP20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BCM590XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD71815 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD71828 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD718XX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD9571MWV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD957XMUF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BD96801 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_BQ257XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_CROS_EC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_DA903X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9062 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_DA9063 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_DA9121 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_DA9210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DA9211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_REGULATOR_FAN53555 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_FAN53880 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_FIXED_VOLTAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_FP9931 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_HI6421 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_HI6421V530 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_HI6421V600 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_HI655X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_ISL6271A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_ISL9305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LM363X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LP3971 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP3972 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP872X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP873X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LP8755 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LP87565 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LTC3589 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_LTC3676 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX14577 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX1586 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX20086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX20411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX5970 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77503 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77620 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77650 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77675 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77686 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX77802 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77826 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX77838 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX77857 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX8649 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8893 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8907 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX8925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8952 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8973 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MAX8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MC13783 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MC13892 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MC13XXX_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MCP16502 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MP5416 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MP8859 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MP886X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MPQ7920 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_MT6315 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6316 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6331 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6332 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6357 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6358 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6359 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MT6380 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_MT6397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_MTK_DVFSRC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_NETLINK_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REGULATOR_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PBIAS policy<{'armhf': 'm'}> +CONFIG_REGULATOR_PCA9450 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PF0900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF1550 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF530X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF8X00 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PF9453 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PFUZE100 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_PV88060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PV88080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PV88090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_QCOM_LABIBB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_QCOM_PM8008 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_QCOM_REFGEN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_RPMH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_SMD_RPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_QCOM_SPMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_QCOM_USB_VBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RAA215300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_REGULATOR_RC5T583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RK808 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RN5T618 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_ROHM policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT4801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RT4803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT4831 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5133 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5190A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5739 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT5759 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT6160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RT6190 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RT6245 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RT8092 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RTMV20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RTQ2134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RTQ2208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_RTQ6752 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_RZG2L_VBCTRL policy<{'arm64': 'y'}> +CONFIG_REGULATOR_S2DOS05 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_S2MPA01 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_S2MPS11 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_S5M8767 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SC2731 policy<{'arm64': 'm'}> +CONFIG_REGULATOR_SKY81452 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SLG51000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_STM32_BOOSTER policy<{'arm64': 'm'}> +CONFIG_REGULATOR_STM32_PWR policy<{'arm64': 'y'}> +CONFIG_REGULATOR_STM32_VREFBUF policy<{'arm64': 'm'}> +CONFIG_REGULATOR_STPMIC1 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SUN20I policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_REGULATOR_SY7636A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SY8106A policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SY8824X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_SY8827N policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TI_ABB policy<{'armhf': 'y'}> +CONFIG_REGULATOR_TPS51632 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6105X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS62360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6286X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS6287X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6507X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65132 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65185 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65218 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS65219 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS6524X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6586X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS65912 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_TPS6594 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_TPS68470 policy<{'amd64': 'm'}> +CONFIG_REGULATOR_USERSPACE_CONSUMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_VCTRL policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_REGULATOR_VEXPRESS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_VIRTUAL_CONSUMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_VQMMC_IPQ4019 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_REGULATOR_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_WM8400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_REGULATOR_WM8994 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RELAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RELOCATABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RELOCATABLE_TEST policy<{'ppc64el': 'n'}> +CONFIG_RELR policy<{'arm64': 'n'}> +CONFIG_REMOTEPROC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_REMOTEPROC_CDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_REMOTE_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RENESAS_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RENESAS_ETHER_SWITCH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_GEN4_PTP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_I3C policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_INTC_IRQPIN policy<{'armhf': 'y'}> +CONFIG_RENESAS_IRQC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RENESAS_OSTM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RENESAS_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RENESAS_RPCIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZA1_IRQC policy<{'armhf': 'y'}> +CONFIG_RENESAS_RZAWDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZG2LWDT policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_RENESAS_RZG2L_IRQC policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_RENESAS_RZN1WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZT2H_ICU policy<{'arm64': 'y'}> +CONFIG_RENESAS_RZV2HWDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_RZV2H_ICU policy<{'arm64': 'y'}> +CONFIG_RENESAS_USB_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_WDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RENESAS_WWDT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESCTRL_FS policy<{'amd64': 'y'}> +CONFIG_RESCTRL_FS_PSEUDO_LOCK policy<{'amd64': 'y'}> +CONFIG_RESET_A10SR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_ASPEED policy<{'armhf': 'm'}> +CONFIG_RESET_ATTACK_MITIGATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_RESET_BERLIN policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_RESET_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RESET_HISI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_IMX7 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_IMX8MP_AUDIOMIX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_IMX_SCU policy<{'arm64': 'm'}> +CONFIG_RESET_MCHP_SPARX5 policy<{'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RESET_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_MESON_AUDIO_ARB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_MESON_AUX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_MESON_COMMON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_NPCM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_NUVOTON_MA35D1 policy<{'arm64': 'y'}> +CONFIG_RESET_POLARFIRE_SOC policy<{'arm64': 'y'}> +CONFIG_RESET_QCOM_AOSS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_QCOM_PDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_RZG2L_USBPHY_CTRL policy<{'arm64': 'y'}> +CONFIG_RESET_RZV2H_USB2PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_SIMPLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RESET_SOCFPGA policy<{'armhf': 'y'}> +CONFIG_RESET_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_RESET_SUNXI policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_RESET_TEGRA_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RESET_TI_SCI policy<{'arm64': 'm'}> +CONFIG_RESET_TI_SYSCON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RESET_TI_TPS380X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RESET_TN48M_CPLD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RESET_ZYNQMP policy<{'arm64': 'y'}> +CONFIG_RETHOOK policy<{'amd64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RETU_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RFD77402 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RFD_FTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RFKILL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_RFKILL_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RFKILL_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RFKILL_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RFS_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RICHTEK_RTQ6056 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RING_BUFFER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RING_BUFFER_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RING_BUFFER_STARTUP_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RIONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RIONET_RX_SIZE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_RIONET_TX_SIZE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128'}> +CONFIG_RISCV policy<{'riscv64': 'y'}> +CONFIG_RISCV_ALTERNATIVE policy<{'riscv64': 'y'}> +CONFIG_RISCV_APLIC policy<{'riscv64': 'y'}> +CONFIG_RISCV_APLIC_MSI policy<{'riscv64': 'y'}> +CONFIG_RISCV_BOOT_SPINWAIT policy<{'riscv64': 'n'}> +CONFIG_RISCV_COMBO_SPINLOCKS policy<{'riscv64': 'y'}> +CONFIG_RISCV_DMA_NONCOHERENT policy<{'riscv64': 'y'}> +CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS policy<{'riscv64': 'n'}> +CONFIG_RISCV_IMSIC policy<{'riscv64': 'y'}> +CONFIG_RISCV_INTC policy<{'riscv64': 'y'}> +CONFIG_RISCV_IOMMU policy<{'riscv64': 'y'}> +CONFIG_RISCV_IOMMU_PCI policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_C policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_FALLBACK policy<{'riscv64': 'n'}> +CONFIG_RISCV_ISA_SUPM policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_SVNAPOT policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_SVPBMT policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_SVRSW60T59B policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_MIPS policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_VENDOR_EXT_THEAD policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V_PREEMPTIVE policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD policy<{'riscv64': '768'}> +CONFIG_RISCV_ISA_XTHEADVECTOR policy<{'riscv64': 'n'}> +CONFIG_RISCV_ISA_ZABHA policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZACAS policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZAWRS policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBA policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBB policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBC policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZBKB policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZICBOM policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZICBOP policy<{'riscv64': 'y'}> +CONFIG_RISCV_ISA_ZICBOZ policy<{'riscv64': 'y'}> +CONFIG_RISCV_MISALIGNED policy<{'riscv64': 'y'}> +CONFIG_RISCV_PMU policy<{'riscv64': 'y'}> +CONFIG_RISCV_PMU_LEGACY policy<{'riscv64': 'y'}> +CONFIG_RISCV_PMU_SBI policy<{'riscv64': 'y'}> +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS policy<{'riscv64': 'y'}> +CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS policy<{'riscv64': 'y'}> +CONFIG_RISCV_RPMI_SYSMSI policy<{'riscv64': 'y'}> +CONFIG_RISCV_SBI policy<{'riscv64': 'y'}> +CONFIG_RISCV_SBI_CPUIDLE policy<{'riscv64': 'y'}> +CONFIG_RISCV_SBI_MPXY_MBOX policy<{'riscv64': 'm'}> +CONFIG_RISCV_SBI_V01 policy<{'riscv64': 'n'}> +CONFIG_RISCV_SCALAR_MISALIGNED policy<{'riscv64': 'y'}> +CONFIG_RISCV_TICKET_SPINLOCKS policy<{'riscv64': 'n'}> +CONFIG_RISCV_TIMER policy<{'riscv64': 'y'}> +CONFIG_RISCV_USER_CFI policy<{'riscv64': 'y'}> +CONFIG_RISCV_VECTOR_MISALIGNED policy<{'riscv64': 'y'}> +CONFIG_RMI4_2D_SENSOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RMI4_F03 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F03_SERIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RMI4_F11 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F12 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F1A policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_F21 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_F30 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F34 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F3A policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_F54 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RMI4_F55 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_RMI4_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RMI4_SMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RMI4_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RMNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RN5T618_ADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RN5T618_POWER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RN5T618_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROCKCHIP_ANALOGIX_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_CDN_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DTPM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_DW_DP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_HDMI_QP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_DW_MIPI_DSI2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_ERRATUM_3568002 policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_ERRATUM_3588001 policy<{'arm64': 'y'}> +CONFIG_ROCKCHIP_GRF policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_INNO_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_IODOMAIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_IOMMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_LVDS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_MBOX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ROCKCHIP_PM_DOMAINS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_RGB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_RK3066_HDMI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_SARADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_ROCKCHIP_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_VOP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKCHIP_VOP2 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_ROCKER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ROHM_BD79112 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROHM_BD79124 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROHM_BM1390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROHM_BU27034 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ROMFS_BACKED_BY_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ROMFS_BACKED_BY_BOTH policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ROMFS_BACKED_BY_MTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_ROMFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ROMFS_ON_BLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ROSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPCSEC_GSS_KRB5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RPMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RPMSG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_CHAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_CTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_MTK_SCP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RPMSG_NS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_QCOM_GLINK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_QCOM_GLINK_RPM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_RPMSG_QCOM_GLINK_SMEM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RPMSG_QCOM_SMD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RPMSG_TTY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPMSG_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RPMSG_WWAN_CTRL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPR0521 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RSEQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RSEQ_DEBUG_DEFAULT_ENABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RSEQ_SLICE_EXTENSION policy<{'amd64': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RSEQ_STATS policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RSI_91X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RSI_COEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RSI_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RSI_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RSI_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RST_RCAR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RT2400PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2500PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2500USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800PCI_RT3290 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800PCI_RT33XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800PCI_RT35XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800PCI_RT53XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800USB_RT33XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT3573 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT35XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT53XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_RT55XX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800USB_UNKNOWN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2800_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2800_LIB_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RT2X00_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_LIB_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2X00_LIB_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RT2X00_LIB_FIRMWARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2X00_LIB_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RT2X00_LIB_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_LIB_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT2X00_LIB_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT61PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT73USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTASE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTAS_ERROR_LOGGING policy<{'ppc64el': 'y'}> +CONFIG_RTAS_FLASH policy<{'ppc64el': 'm'}> +CONFIG_RTAS_PROC policy<{'ppc64el': 'y'}> +CONFIG_RTC_CLASS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_88PM80X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_88PM886 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ABB5ZES3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ABEOZ9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ABX80X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_AMLOGIC_A4 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_ARMADA38X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_AS3722 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ASPEED policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_BBNSM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_BD70528 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_BQ32K policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_CADENCE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_CV1800 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_RTC_DRV_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DA9063 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1286 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1302 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1307 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1307_CENTURY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_DS1343 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1347 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1374 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1374_WDT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_DS1390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1511 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1553 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1672 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1685 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_DS1685_FAMILY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS1689 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS17285 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS1742 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS17485 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS17885 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_DS2404 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS3232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_DS3232_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_EM3027 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_FM3130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_FSL_FTM_ALARM policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_FTRTC010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_GENERIC policy<{'ppc64el': 'y'}> +CONFIG_RTC_DRV_GOLDFISH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'y'}> +CONFIG_RTC_DRV_HID_SENSOR_TIME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_HYM8563 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_IMXDI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_IMX_BBM_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_IMX_SC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_ISL12022 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ISL12026 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_ISL1208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_LP8788 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M41T80 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M41T80_WDT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_M41T93 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M41T94 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M48T35 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M48T59 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_M48T86 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MA35D1 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MACSMC policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_MAX31335 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX6900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX6902 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX6916 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX77686 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8907 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8997 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MAX8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MC13XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MCP795 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MESON policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_MESON_VRTC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MSC313 policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_MSM6242 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MT2712 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MT6397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_MT7622 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MV policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTC_DRV_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_MXC_V2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_NCT3018Y policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_NTXEC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_NVIDIA_VRS10 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_RTC_DRV_OMAP policy<{'armhf': 'y'}> +CONFIG_RTC_DRV_OPAL policy<{'ppc64el': 'y'}> +CONFIG_RTC_DRV_OPTEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_PALMAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF2123 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF2127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF85063 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF8523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF85363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF8563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PCF8583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_PL030 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_RTC_DRV_PL031 policy<{'arm64': 'm', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_RTC_DRV_PM8XXX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_R7301 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_R9701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RC5T583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RC5T619 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RENESAS_RTCA3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_RK808 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RP5C01 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RS5C348 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RS5C372 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RTD119X policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTC_DRV_RV3028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RV3029C2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RV3029_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_DRV_RV3032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RV8803 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX4581 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX6110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8025 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RX8581 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_RZN1 policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_S32G policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_S35390A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_S3C policy<{'armhf': 'n'}> +CONFIG_RTC_DRV_S5M policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_SA1100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_SC27XX policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SD2405AL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_SD3078 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_SH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_SNVS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_SSD202D policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_STK17TA8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_STM32 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_SUN6I policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_RTC_DRV_SUNPLUS policy<{'armhf': 'm'}> +CONFIG_RTC_DRV_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTC_DRV_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_DRV_TI_K3 policy<{'arm64': 'm'}> +CONFIG_RTC_DRV_TPS6586X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_TPS65910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_TPS6594 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_WILCO_EC policy<{'amd64': 'm'}> +CONFIG_RTC_DRV_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_X1205 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_DRV_XGENE policy<{'arm64': 'y'}> +CONFIG_RTC_DRV_ZYNQMP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTC_HCTOSYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_HCTOSYS_DEVICE policy<{'amd64': '"rtc0"', 'arm64': '"rtc0"', 'armhf': '"rtc0"', 'ppc64el': '"rtc0"', 'riscv64': '"rtc0"'}> +CONFIG_RTC_I2C_AND_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_INTF_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_INTF_DEV_UIE_EMUL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTC_INTF_PROC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_INTF_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_MC146818_LIB policy<{'amd64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_RTC_NVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_SYSTOHC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTC_SYSTOHC_DEVICE policy<{'amd64': '"rtc0"', 'arm64': '"rtc0"', 'armhf': '"rtc0"', 'ppc64el': '"rtc0"', 'riscv64': '"rtc0"'}> +CONFIG_RTD119X_WATCHDOG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTK_SYSTIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_RTL8180 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8187 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8187_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTL8188EE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192C_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192DE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192DU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192D_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192EE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8192SE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723BS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8723_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8821AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8XXXU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL8XXXU_UNTESTED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTLBTCOEXIST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTLWIFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTLWIFI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_RTLWIFI_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTLWIFI_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTL_CARDS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTSN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RTW88 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8703B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723DE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723DS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723DU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8723X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8812A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8812AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8814A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8814AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8814AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8821CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822BS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822BU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822CS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_8822CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_88XXA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW88_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW88_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW88_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW88_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8851B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8851BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8851BU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852AU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BTE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852BU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852B_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852CE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8852CU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8922A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_8922AE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW89_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW89_DEBUGMSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_RTW89_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RTW89_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_RT_MUTEXES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUNTIME_KERNEL_TESTING_MENU policy<{'riscv64': 'n'}> +CONFIG_RUNTIME_TESTING_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_HAS_COERCE_POINTEE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_HAS_FILE_AS_C_STR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_HAS_FILE_WITH_NUL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_HAS_SLICE_AS_FLATTENED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_HAS_SPAN_FILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_HAS_UNNECESSARY_TRANSMUTES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUSTC_LLVM_VERSION policy<{'amd64': '210108', 'arm64': '210108', 'armhf': '210108', 'ppc64el': '210108', 'riscv64': '210108', 's390x': '210108'}> +CONFIG_RUSTC_SUPPORTS_ARM64 policy<{'arm64': 'y'}> +CONFIG_RUSTC_SUPPORTS_RISCV policy<{'riscv64': 'y'}> +CONFIG_RUSTC_VERSION policy<{'amd64': '109301', 'arm64': '109301', 'armhf': '109301', 'ppc64el': '109301', 'riscv64': '109301', 's390x': '109301'}> +CONFIG_RUSTC_VERSION_TEXT policy<{'amd64': '"rustc 1.93.1 (01f6ddf75 2026-02-11) (built from a source tarball)"', 'arm64': '"rustc 1.93.1 (01f6ddf75 2026-02-11) (built from a source tarball)"'}> +CONFIG_RUST_BITMAP_HARDENED policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_RUST_BUILD_ASSERT_ALLOW policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_RUST_DEBUG_ASSERTIONS policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_RUST_FW_LOADER_ABSTRACTIONS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_RUST_IS_AVAILABLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RUST_OVERFLOW_CHECKS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_RUST_PHYLIB_ABSTRACTIONS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_RV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RVU_ESWITCH policy<{'arm64': 'm'}> +CONFIG_RV_LTL_MONITOR policy<{'armhf': 'y'}> +CONFIG_RV_MON_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_MAINTENANCE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_MON_RTAPP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_RV_MON_SLEEP policy<{'armhf': 'y'}> +CONFIG_RV_MON_WWNR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_PER_TASK_MONITORS policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2', 's390x': '2'}> +CONFIG_RV_REACTORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_REACT_PANIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RV_REACT_PRINTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RWSEM_SPIN_ON_OWNER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RXGK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RXKAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_RXPERF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_RZG2L_ADC policy<{'arm64': 'm'}> +CONFIG_RZG2L_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZG3E_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZG3S_THERMAL policy<{'arm64': 'm'}> +CONFIG_RZN1_ADC policy<{'armhf': 'm'}> +CONFIG_RZN1_DMAMUX policy<{'armhf': 'm'}> +CONFIG_RZN1_IRQMUX policy<{'armhf': 'y'}> +CONFIG_RZT2H_ADC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZ_DMAC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_RZ_MTU3 policy<{'arm64': 'y'}> +CONFIG_RZ_MTU3_CNT policy<{'arm64': 'm'}> +CONFIG_S32G_WDT policy<{'arm64': 'm'}> +CONFIG_S390 policy<{'s390x': 'y'}> +CONFIG_S390_GUEST policy<{'s390x': 'y'}> +CONFIG_S390_HYPFS policy<{'s390x': 'y'}> +CONFIG_S390_HYPFS_FS policy<{'s390x': 'y'}> +CONFIG_S390_IOMMU policy<{'s390x': 'y'}> +CONFIG_S390_PRNG policy<{'s390x': 'm'}> +CONFIG_S390_TAPE policy<{'s390x': 'm'}> +CONFIG_S390_VMUR policy<{'s390x': 'm'}> +CONFIG_S3C2410_WATCHDOG policy<{'armhf': 'n'}> +CONFIG_S5P_DEV_MFC policy<{'armhf': 'y'}> +CONFIG_SAMPLES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SAMPLES_RUST policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_SAMPLE_AUXDISPLAY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SAMPLE_CONFIGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FPROBE policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FTRACE_DIRECT policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FTRACE_DIRECT_MULTI policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_FTRACE_OPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_HUNG_TASK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SAMPLE_HW_BREAKPOINT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n'}> +CONFIG_SAMPLE_KDB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SAMPLE_KFIFO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_KOBJECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_KPROBES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_LIVEPATCH policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_QMI_CLIENT policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SAMPLE_RPMSG_CLIENT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SAMPLE_TRACE_ARRAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_TRACE_EVENTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_TSM_MR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MBOCHS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MDPY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_VFIO_MDEV_MTTY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SAMPLE_WATCHDOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SAMSUNG_GALAXYBOOK policy<{'amd64': 'm'}> +CONFIG_SAMSUNG_LAPTOP policy<{'amd64': 'm'}> +CONFIG_SAMSUNG_MC policy<{'armhf': 'y'}> +CONFIG_SAMSUNG_Q10 policy<{'amd64': 'm'}> +CONFIG_SAR_GCC_2130P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SAR_GPUCC_2130P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SATA_ACARD_AHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_AHCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_AHCI_SEATTLE policy<{'arm64': 'm'}> +CONFIG_SATA_DWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_DWC_OLD_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SATA_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SATA_INIC162X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_MOBILE_LPM_POLICY policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3'}> +CONFIG_SATA_MV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_NV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_PMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SATA_PROMISE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_QSTOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SATA_SIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SIL24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SVW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_SX4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_ULI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_VITESSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SATA_ZPODD policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_SA_CAMCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_DISPCC_8775P policy<{'arm64': 'm'}> +CONFIG_SA_GCC_8775P policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_SA_GPUCC_8775P policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SA_VIDEOCC_8775P policy<{'arm64': 'm'}> +CONFIG_SBC_EPX_C3_WATCHDOG policy<{'amd64': 'm'}> +CONFIG_SBC_FITPC2_WATCHDOG policy<{'amd64': 'm'}> +CONFIG_SBITMAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SBP_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SC1200_WDT policy<{'amd64': 'm'}> +CONFIG_SC27XX_ADC policy<{'arm64': 'm'}> +CONFIG_SC92031 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCA3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCA3300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD30_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD30_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD30_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCD4X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCF_TORTURE_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SCHEDSTATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_AUTOGROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_CLASS_EXT policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_CLUSTER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SCHED_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_SCHED_HRTICK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_HW_PRESSURE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SCHED_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_MC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_MC_PRIO policy<{'amd64': 'y'}> +CONFIG_SCHED_MM_CID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_OMIT_FRAME_POINTER policy<{'amd64': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_SCHED_PROXY_EXEC policy<{'armhf': 'y'}> +CONFIG_SCHED_SMT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_SCHED_STACK_END_CHECK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCHED_TOPOLOGY policy<{'s390x': 'y'}> +CONFIG_SCHED_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCLP_CONSOLE policy<{'s390x': 'y'}> +CONFIG_SCLP_TTY policy<{'s390x': 'y'}> +CONFIG_SCLP_VT220_CONSOLE policy<{'s390x': 'y'}> +CONFIG_SCLP_VT220_TTY policy<{'s390x': 'y'}> +CONFIG_SCM_BLOCK policy<{'s390x': 'm'}> +CONFIG_SCM_BUS policy<{'s390x': 'y'}> +CONFIG_SCOM_DEBUGFS policy<{'ppc64el': 'y'}> +CONFIG_SCREEN_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SCSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_3W_9XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_3W_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_AACRAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_ACARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_ADVANSYS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AIC79XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AIC7XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AIC94XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_AM53C974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_ARCMSR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BFA_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BNX2X_FCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BNX2_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_BUSLOGIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_CHELSIO_FCOE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_CONSTANTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_CXGB3_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_CXGB4_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_DC395x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_DEBUG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_DH_ALUA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH_EMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH_HP_SW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DH_RDAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_DMX3191D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_EFCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_ENCLOSURE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_ESAS2R policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_FC_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_FDOMAIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_FDOMAIN_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_FLASHPOINT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_HISI_SAS policy<{'arm64': 'm'}> +CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE policy<{'arm64': 'n'}> +CONFIG_SCSI_HISI_SAS_PCI policy<{'arm64': 'm'}> +CONFIG_SCSI_HPSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_HPTIOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_IBMVFC policy<{'ppc64el': 'm'}> +CONFIG_SCSI_IBMVFC_TRACE policy<{'ppc64el': 'y'}> +CONFIG_SCSI_IBMVSCSI policy<{'ppc64el': 'm'}> +CONFIG_SCSI_IBMVSCSIS policy<{'ppc64el': 'm'}> +CONFIG_SCSI_IMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_INIA100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_INITIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_IPR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_IPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_ISCI policy<{'amd64': 'm'}> +CONFIG_SCSI_ISCSI_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_IZIP_SLOW_CTR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SCSI_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_LOWLEVEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_LOWLEVEL_PCMCIA policy<{'amd64': 'y'}> +CONFIG_SCSI_LPFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_LPFC_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SCSI_MOD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_MPI3MR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_MPT2SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_MPT2SAS_MAX_SGE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128', 's390x': '128'}> +CONFIG_SCSI_MPT3SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_MPT3SAS_MAX_SGE policy<{'amd64': '128', 'arm64': '128', 'armhf': '128', 'ppc64el': '128', 'riscv64': '128', 's390x': '128'}> +CONFIG_SCSI_MVSAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_MVSAS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SCSI_MVSAS_TASKLET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SCSI_MVUMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_MYRB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_MYRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_NSP32 policy<{'armhf': 'm'}> +CONFIG_SCSI_PM8001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_PMCRAID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_PPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_PROC_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_QLA_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SCSI_QLA_ISCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_QLOGIC_1280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SAS_ATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_SAS_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_SAS_HOST_SMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_SAS_LIBSAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_SCAN_ASYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SCSI_SMARTPQI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_SNIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SNIC_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SCSI_SPI_ATTRS policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_SRP_ATTRS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'y', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SCSI_STEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16'}> +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SCSI_SYM53C8XX_MAX_TAGS policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_SCSI_SYM53C8XX_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_UFSHCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCSI_UFSHCD_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFSHCD_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_AMD_VERSAL2 policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_BSG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_UFS_CDNS_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SCSI_UFS_DWC_TC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_DWC_TC_PLATFORM policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SCSI_UFS_EXYNOS policy<{'armhf': 'n'}> +CONFIG_SCSI_UFS_HISI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_HWMON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SCSI_UFS_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_RENESAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_ROCKCHIP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SCSI_UFS_SPRD policy<{'arm64': 'm'}> +CONFIG_SCSI_UFS_TI_J721E policy<{'arm64': 'm'}> +CONFIG_SCSI_WD719X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SCTP_DBG_OBJCNT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SC_CAMCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_CAMCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_CAMCC_8180X policy<{'arm64': 'm'}> +CONFIG_SC_CAMCC_8280XP policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_DISPCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_DISPCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_DISPCC_8280XP policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_GCC_7180 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GCC_7280 policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GCC_8180X policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GCC_8280XP policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SC_GPUCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_GPUCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_GPUCC_8280XP policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_LPASSCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_LPASSCC_8280XP policy<{'arm64': 'm'}> +CONFIG_SC_LPASS_CORECC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_LPASS_CORECC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_VIDEOCC_7180 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SC_VIDEOCC_7280 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDIO_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SDMA_VERBOSITY policy<{'amd64': 'n'}> +CONFIG_SDM_CAMCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_DISPCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GCC_660 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GPUCC_660 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_GPUCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_LPASSCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_MMCC_660 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDM_VIDEOCC_845 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SDP500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SDR_MAX2175 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SDR_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SDX_GCC_55 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_SDX_GCC_65 policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_SDX_GCC_75 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SD_ADC_MODULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SECCOMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECCOMP_CACHE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECCOMP_FILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECONDARY_TRUSTED_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECRETMEM policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECTION_MISMATCH_WARN_ONLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITYFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_HASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_DMESG_RESTRICT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_INFINIBAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_IPE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_LANDLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_LOADPIN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_LOCKDOWN_LSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_NETWORK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_NETWORK_XFRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_PATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_PERF_EVENTS_RESTRICT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX_AVC_HASH_BITS policy<{'amd64': '9', 'arm64': '9', 'armhf': '9', 'ppc64el': '9', 'riscv64': '9', 's390x': '9'}> +CONFIG_SECURITY_SELINUX_AVC_STATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX_BOOTPARAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SECURITY_SELINUX_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_SELINUX_DEVELOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE policy<{'amd64': '256', 'arm64': '256', 'armhf': '256', 'ppc64el': '256', 'riscv64': '256', 's390x': '256'}> +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS policy<{'amd64': '9', 'arm64': '9', 'armhf': '9', 'ppc64el': '9', 'riscv64': '9', 's390x': '9'}> +CONFIG_SECURITY_SMACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SMACK_APPEND_SIGNALS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_SMACK_BRINGUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_SMACK_NETFILTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_TOMOYO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER policy<{'amd64': '"/sbin/init"', 'arm64': '"/sbin/init"', 'armhf': '"/sbin/init"', 'ppc64el': '"/sbin/init"', 'riscv64': '"/sbin/init"', 's390x': '"/sbin/init"'}> +CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY policy<{'amd64': '2048', 'arm64': '2048', 'armhf': '2048', 'ppc64el': '2048', 'riscv64': '2048', 's390x': '2048'}> +CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG policy<{'amd64': '1024', 'arm64': '1024', 'armhf': '1024', 'ppc64el': '1024', 'riscv64': '1024', 's390x': '1024'}> +CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SECURITY_TOMOYO_POLICY_LOADER policy<{'amd64': '"/sbin/tomoyo-init"', 'arm64': '"/sbin/tomoyo-init"', 'armhf': '"/sbin/tomoyo-init"', 'ppc64el': '"/sbin/tomoyo-init"', 'riscv64': '"/sbin/tomoyo-init"', 's390x': '"/sbin/tomoyo-init"'}> +CONFIG_SECURITY_YAMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SEG_LED_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SEL3350_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SELECT_MEMORY_MODEL policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SEN0322 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSEAIR_SUNRISE_CO2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSIRION_SGP30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSIRION_SGP40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_AAEON policy<{'amd64': 'm'}> +CONFIG_SENSORS_ABITUGURU policy<{'amd64': 'm'}> +CONFIG_SENSORS_ABITUGURU3 policy<{'amd64': 'm'}> +CONFIG_SENSORS_ACBEL_FSG032 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ACPI_POWER policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_AD7314 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AD7414 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AD7418 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADC128D818 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADCXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1025 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1026 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1029 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1031 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1177 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADM1266 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ADM1275 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ADM9240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADP1050 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ADP1050_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_ADS7828 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADS7871 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7410 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7462 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7470 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7475 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ADT7X10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_AHT10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AMC6821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_APDS990X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_APPLESMC policy<{'amd64': 'm'}> +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ARM_SCMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_ARM_SCPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_AS370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ASB100 policy<{'amd64': 'm'}> +CONFIG_SENSORS_ASC7621 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_ASPEED policy<{'armhf': 'm'}> +CONFIG_SENSORS_ASPEED_G6 policy<{'armhf': 'm'}> +CONFIG_SENSORS_ASUS_EC policy<{'amd64': 'm'}> +CONFIG_SENSORS_ASUS_ROG_RYUJIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ASUS_WMI policy<{'amd64': 'm'}> +CONFIG_SENSORS_ATK0110 policy<{'amd64': 'm'}> +CONFIG_SENSORS_ATXP1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_AXI_FAN_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_BEL_PFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_BH1770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_BPA_RS600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_CGBC policy<{'amd64': 'm'}> +CONFIG_SENSORS_CHIPCAP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_CORETEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_CORSAIR_CPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_CORSAIR_PSU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_CROS_EC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_CRPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_DA9052_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DA9055 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DELL_SMM policy<{'amd64': 'm'}> +CONFIG_SENSORS_DELTA_AHE50DC_FAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_DME1737 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DPS920AB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_DRIVETEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DS1621 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_DS620 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_EMC1403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_EMC2103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_EMC2305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_EMC6W201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_F71805F policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_F71882FG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_F75375S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_FAM15H_POWER policy<{'amd64': 'm'}> +CONFIG_SENSORS_FSCHMD policy<{'amd64': 'm'}> +CONFIG_SENSORS_FSP_3Y policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_FTSTEUTATES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_G760A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_G762 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_GIGABYTE_WATERFORCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_GL518SM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_GL520SM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_GPD policy<{'amd64': 'm'}> +CONFIG_SENSORS_GPIO_FAN policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_GSC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_GXP_FAN_CTRL policy<{'armhf': 'm'}> +CONFIG_SENSORS_HAC300S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HDAPS policy<{'amd64': 'm'}> +CONFIG_SENSORS_HIH6130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_HMC5843 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HMC5843_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HMC5843_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HP_WMI policy<{'amd64': 'm'}> +CONFIG_SENSORS_HS3001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_HTU31 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_I5500 policy<{'amd64': 'm'}> +CONFIG_SENSORS_I5K_AMB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_IBMAEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IBMPEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IBMPOWERNV policy<{'ppc64el': 'm'}> +CONFIG_SENSORS_IBM_CFFPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IIO_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INA209 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_INA233 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INA238 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INA2XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_INA3221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_INSPUR_IPSPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_INTEL_M10_BMC_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR35221 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR36021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR38064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IR38064_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_IRPS5401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL28022 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL29018 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL29028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ISL68137 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_IT87 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_JC42 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_K10TEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_K8TEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_KBATT policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_KFAN policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_LENOVO_EC policy<{'amd64': 'm'}> +CONFIG_SENSORS_LINEAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LIS3LV02D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LIS3_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_LIS3_SPI policy<{'armhf': 'm', 'ppc64el': 'm', 'riscv64': '-', 's390x': '-'}> +CONFIG_SENSORS_LM25066 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LM25066_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_LM3533 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LM63 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM70 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM73 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM75 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM77 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM78 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM80 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM83 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM85 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM87 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM90 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM92 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM93 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM95234 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM95241 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LM95245 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LOCHNAGAR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LT3074 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LT3074_REGULATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LT7182S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2945 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2947 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2947_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2947_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2978 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2978_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_LTC2990 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC2991 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC2992 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC3815 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC4151 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4215 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4222 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4245 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4261 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_LTC4282 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_LTC4286 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_MACSMC_HWMON policy<{'arm64': 'm'}> +CONFIG_SENSORS_MAX1111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX15301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX16064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX16065 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX1619 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX16601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX1668 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX17616 policy<{'amd64': 'm', 'arm64-generic': 'm', 'arm64-generic-64k': 'n', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_SENSORS_MAX197 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX20730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX20751 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX31722 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX31730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX31760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX31785 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX31790 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX34440 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX6620 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX6621 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX6639 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX6650 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX6697 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MAX77705 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MAX8688 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MC13783_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MC33XS2410 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MC34VR500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MCP3021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_MENF21BMC_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MLXREG_FAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_MP2856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2869 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2888 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2891 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2925 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP29502 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2975 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP2975_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_MP2993 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5920 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5926 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP5990 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP9941 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MP9945 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MPQ7932 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MPQ7932_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_MPQ8785 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_MR75203 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT6683 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT6694 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT6775 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT6775_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT6775_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT7363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NCT7802 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NCT7904 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NPCM7XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_NTC_THERMISTOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NZXT_KRAKEN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NZXT_KRAKEN3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_NZXT_SMART2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_OCC policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SENSORS_OCC_P8_I2C policy<{'amd64': 'm', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_SENSORS_OCC_P9_SBE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'n'}> +CONFIG_SENSORS_PC87360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PC87427 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PCF8591 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PECI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PECI_CPUTEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PECI_DIMMTEMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PIM4328 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PLI1209BC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PLI1209BC_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_PM6764TR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_POWERZ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_POWR1220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_PT5161L policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PWM_FAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_PXE1610 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_Q54SJ108A2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_QNAP_MCU_HWMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_RM3100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_RM3100_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_RM3100_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SBTSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SCH5627 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SCH5636 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SCH56XX_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SG2042_MCU policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SENSORS_SHT15 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHT21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHT3x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHT4x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SHTC1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SIS5595 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SL28CPLD policy<{'arm64': 'm'}> +CONFIG_SENSORS_SMPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SMSC47B397 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SMSC47M1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SMSC47M192 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SPARX5 policy<{'arm64': 'm'}> +CONFIG_SENSORS_SPD5118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_SPD5118_DETECT policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_STEF48H28 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_STPDDC60 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_STTS751 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_SURFACE_FAN policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_SURFACE_TEMP policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SENSORS_SY7636A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TC654 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TC74 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TDA38640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TDA38640_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_THMC50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP103 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP108 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP421 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TMP464 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TMP513 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TPS23861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_TPS25990 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TPS25990_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_TPS40422 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TPS53679 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TPS546D24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TSC1641 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_TSL2550 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SENSORS_TSL2563 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_UCD9000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_UCD9200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_VEXPRESS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SENSORS_VIA686A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_VIA_CPUTEMP policy<{'amd64': 'm'}> +CONFIG_SENSORS_VT1211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_VT8231 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83627EHF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83627HF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83773G policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83781D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83791D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83792D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83793 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83795 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83795_FANCTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SENSORS_W83L785TS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_W83L786NG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_WM8350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SENSORS_XDP710 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XDPE122 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XDPE122_REGULATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SENSORS_XDPE152 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_XGENE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SENSORS_ZL6100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_16550A_VARIANTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_ASPEED_VUART policy<{'armhf': 'm'}> +CONFIG_SERIAL_8250_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_CS policy<{'amd64': 'm'}> +CONFIG_SERIAL_8250_DETECT_IRQ policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SERIAL_8250_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_DWLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_EM policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SERIAL_8250_EXAR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_EXTENDED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_FINTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_FSL policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_SERIAL_8250_KEBA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SERIAL_8250_LPSS policy<{'amd64': 'm'}> +CONFIG_SERIAL_8250_MANY_PORTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_MEN_MCB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_MT6577 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_NI policy<{'amd64': 'm'}> +CONFIG_SERIAL_8250_NR_UARTS policy<{'amd64': '48', 'arm64': '48', 'armhf': '48', 'ppc64el': '48', 'riscv64': '48'}> +CONFIG_SERIAL_8250_OMAP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'n', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_PCILIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_PERICOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_8250_PNP policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_PXA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_8250_RSA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_RT288X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_RUNTIME_UARTS policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_SERIAL_8250_SHARE_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_8250_TEGRA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_ALTERA_JTAGUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ALTERA_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ALTERA_UART_BAUDRATE policy<{'amd64': '115200', 'arm64': '115200', 'armhf': '115200', 'ppc64el': '115200', 'riscv64': '115200'}> +CONFIG_SERIAL_ALTERA_UART_MAXPORTS policy<{'amd64': '4', 'arm64': '4', 'armhf': '4', 'ppc64el': '4', 'riscv64': '4'}> +CONFIG_SERIAL_AMBA_PL010 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SERIAL_AMBA_PL011 policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_SERIAL_AMBA_PL011_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_ARC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ARC_NR_PORTS policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SERIAL_ATMEL policy<{'arm64': 'y'}> +CONFIG_SERIAL_ATMEL_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_ATMEL_PDC policy<{'arm64': 'y'}> +CONFIG_SERIAL_ATMEL_TTYAT policy<{'arm64': 'n'}> +CONFIG_SERIAL_CONEXANT_DIGICOLOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'm'}> +CONFIG_SERIAL_CORE_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_EARLYCON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_EARLYCON_RISCV_SBI policy<{'riscv64': 'y'}> +CONFIG_SERIAL_EARLYCON_SEMIHOST policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_FSL_LINFLEXUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_FSL_LPUART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_ICOM policy<{'ppc64el': 'm'}> +CONFIG_SERIAL_IMX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_IMX_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_IMX_EARLYCON policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SERIAL_IPOCTAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_JSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIAL_LANTIQ policy<{'amd64': 'm'}> +CONFIG_SERIAL_LITEUART policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_LITEUART_MAX_PORTS policy<{'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_SERIAL_MAX3100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIAL_MAX310X policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_MCTRL_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_MEN_Z135 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_MESON policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MESON_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MILBEAUT_USIO policy<{'armhf': 'm'}> +CONFIG_SERIAL_MILBEAUT_USIO_PORTS policy<{'armhf': '4'}> +CONFIG_SERIAL_MSM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MSM_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MULTI_INSTANTIATE policy<{'amd64': 'm', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_SERIAL_MVEBU_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_MVEBU_UART policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_NONSTANDARD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SERIAL_NUVOTON_MA35D1 policy<{'arm64': 'm'}> +CONFIG_SERIAL_OF_PLATFORM policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_OWL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_OWL_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_PXA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_PXA_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_QCOM_GENI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_QCOM_GENI_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_QCOM_GENI_UART_PORTS policy<{'arm64': '8', 'armhf': '8'}> +CONFIG_SERIAL_QE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm'}> +CONFIG_SERIAL_RDA policy<{'armhf': 'y'}> +CONFIG_SERIAL_RDA_CONSOLE policy<{'armhf': 'y'}> +CONFIG_SERIAL_RP2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_RP2_NR_UARTS policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_SERIAL_RSCI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_SAMSUNG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_SAMSUNG_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SAMSUNG_UARTS policy<{'arm64': '4', 'armhf': '4'}> +CONFIG_SERIAL_SC16IS7XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SERIAL_SC16IS7XX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_SC16IS7XX_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_SCCNXP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SERIAL_SCCNXP_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIAL_SH_SCI_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_SH_SCI_NR_UARTS policy<{'arm64': '18', 'armhf': '2'}> +CONFIG_SERIAL_SIFIVE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'y'}> +CONFIG_SERIAL_SIFIVE_CONSOLE policy<{'riscv64': 'y'}> +CONFIG_SERIAL_SPRD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIAL_STM32 policy<{'arm64': 'm'}> +CONFIG_SERIAL_STM32_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIAL_ST_ASC policy<{'armhf': 'm'}> +CONFIG_SERIAL_SUNPLUS policy<{'armhf': 'y'}> +CONFIG_SERIAL_SUNPLUS_CONSOLE policy<{'armhf': 'y'}> +CONFIG_SERIAL_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_TEGRA_TCU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_TEGRA_TCU_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_TEGRA_UTC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIAL_TEGRA_UTC_CONSOLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SERIAL_UARTLITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SERIAL_UARTLITE_NR_UARTS policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1', 's390x': '1'}> +CONFIG_SERIAL_XILINX_PS_UART policy<{'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE policy<{'arm64': 'y'}> +CONFIG_SERIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SERIO_ALTERA_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_AMBAKMI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SERIO_APBPS2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIO_ARC_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_CT82C710 policy<{'amd64': 'm'}> +CONFIG_SERIO_GPIO_PS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_I8042 policy<{'amd64': 'y', 'ppc64el': 'y'}> +CONFIG_SERIO_LIBPS2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SERIO_NVEC_PS2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIO_OLPC_APSP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SERIO_PARKBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SERIO_PCIPS2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_PS2MULT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_RAW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_SERPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SERIO_SUN4I_PS2 policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SERIO_XILINX_XPS_PS2 policy<{'ppc64el': 'm'}> +CONFIG_SEV_GUEST policy<{'amd64': 'm'}> +CONFIG_SFC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SFC_FALCON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SFC_FALCON_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_MCDI_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_MCDI_MON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SFC_SIENA_MCDI_LOGGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA_MCDI_MON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA_MTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SIENA_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFC_SRIOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SFP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SF_PDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SGETMASK_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SGI_GRU policy<{'amd64': 'm'}> +CONFIG_SGI_GRU_DEBUG policy<{'amd64': 'n'}> +CONFIG_SGI_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SGI_XP policy<{'amd64': 'm'}> +CONFIG_SGL_ALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SG_POOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SG_SPLIT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SHADOW_CALL_STACK policy<{'arm64': 'y'}> +CONFIG_SHMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SHRINKER_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SHUFFLE_PAGE_ALLOCATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SH_ETH policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SH_TIMER_CMT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SH_TIMER_MTU2 policy<{'armhf': 'y'}> +CONFIG_SH_TIMER_TMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SI1133 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI1145 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI7005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI7020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SI7210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT_APOLLOLAKE policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_BATT_F7188X policy<{'amd64': 'm'}> +CONFIG_SIEMENS_SIMATIC_IPC_WDT policy<{'amd64': 'm'}> +CONFIG_SIFIVE_PLIC policy<{'riscv64': 'y'}> +CONFIG_SIGNALFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SIGNATURE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SIGNED_PE_FILE_VERIFICATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SILICOM_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SIOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SIOX_BUS_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SIS190 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SIS900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKB_DECRYPTED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SKB_EXTENSIONS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SKFP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKGE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SKGE_GENESIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SKY2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SKY2_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SL28CPLD_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SLAB_BUCKETS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_FREELIST_HARDENED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_FREELIST_RANDOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_MERGE_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLAB_OBJ_EXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLHC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLICOSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SLIC_DS26522 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SLIMBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SLIM_QCOM_NGD_CTRL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SLIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SLIP_COMPRESSED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLIP_MODE_SLIP6 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLIP_SMART policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SLUB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLUB_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SLUB_DEBUG_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SLUB_STATS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SLUB_TINY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SMARTJOYPLUS_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SMBFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMB_SERVER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMB_SERVER_KERBEROS5 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMB_SERVER_SMBDIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMC91X policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SMC_HS_CTRL_BPF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMI240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMI330 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMI330_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMI330_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SMPRO_ERRMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMPRO_MISC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMP_ON_UP policy<{'armhf': 'y'}> +CONFIG_SMSC37B787_WDT policy<{'amd64': 'm'}> +CONFIG_SMSC911X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SMSC9420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SMSC_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SMSC_SCH311X_WDT policy<{'amd64': 'm'}> +CONFIG_SMSGIUCV policy<{'s390x': 'y'}> +CONFIG_SMSGIUCV_EVENT policy<{'s390x': 'm'}> +CONFIG_SMS_SDIO_DRV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMS_SIANO_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SMS_SIANO_MDTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMS_SIANO_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SMS_USB_DRV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SMT_NUM_THREADS_DYNAMIC policy<{'ppc64el': 'y'}> +CONFIG_SM_CAMCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8150 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_CAMCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_CAMCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_6115 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_6125 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_6375 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_DISPCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_DISPCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_FTL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SM_GCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_6115 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_6125 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_6375 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_7150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8650 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_GCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_4450 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6115 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6125 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_6375 policy<{'arm64': 'm'}> +CONFIG_SM_GPUCC_8150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_8650 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_GPUCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SM_LPASSCC_6115 policy<{'arm64': 'm'}> +CONFIG_SM_TCSRCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_TCSRCC_8650 policy<{'arm64': 'm'}> +CONFIG_SM_TCSRCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_6350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_7150 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_8150 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8250 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8350 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8450 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8550 policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SM_VIDEOCC_8750 policy<{'arm64': 'm'}> +CONFIG_SM_VIDEOCC_MILOS policy<{'arm64': 'm'}> +CONFIG_SND_AC97_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AC97_POWER_SAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_AC97_POWER_SAVE_DEFAULT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_SND_AD1889 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ALI5451 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ALOOP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ALS300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ALS4000 policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SND_AMD_ACP_CONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AMD_ASOC_ACP63 policy<{'amd64': 'm'}> +CONFIG_SND_AMD_ASOC_ACP70 policy<{'amd64': 'm'}> +CONFIG_SND_AMD_ASOC_REMBRANDT policy<{'amd64': 'm'}> +CONFIG_SND_AMD_ASOC_RENOIR policy<{'amd64': 'm'}> +CONFIG_SND_AMD_SOUNDWIRE_ACPI policy<{'amd64': 'm'}> +CONFIG_SND_ARM policy<{'armhf': 'y'}> +CONFIG_SND_ARMAACI policy<{'armhf': 'm'}> +CONFIG_SND_ASIHPI policy<{'amd64': 'm'}> +CONFIG_SND_ATIIXP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ATIIXP_MODEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AU8810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AU8820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AU8830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD2 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AW2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_AZT3328 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_BCD2000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BCM63XX_I2S_WHISTLER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BEBOB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BT87X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_BT87X_OVERCLOCK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_CA0106 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CMIPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_COMPRESS_ACCEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_COMPRESS_OFFLOAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CS4281 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CS46XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CS46XX_NEW_DSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_CTL_FAST_LOOKUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_CTL_INPUT_VALIDATION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_CTL_LED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_CTXFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DARLA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DARLA24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_DESIGNWARE_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DESIGNWARE_PCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_DICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DMAENGINE_PCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DMA_SGBUF policy<{'amd64': 'y'}> +CONFIG_SND_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_DYNAMIC_MINORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_ECHO3G policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_EMU10K1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_EMU10K1X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_EMU10K1_SEQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ENS1370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ENS1371 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ES1938 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ES1968 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ES1968_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_ES1968_RADIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_FIREFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_FIREWIRE_DIGI00X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE_MOTU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWIRE_TASCAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FIREWORKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FM801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_FM801_TEA575X_BOOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_GINA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_GINA24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_ALIGNED_MMIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_HDA_CIRRUS_SCODEC policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CIX_IPBLOQ policy<{'arm64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC260 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC262 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC268 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC269 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC662 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC861 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC861VD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC880 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ALC882 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_ANALOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0132 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CA0132_DSP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_CODEC_CIRRUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CM9825 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CMEDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CONEXANT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CS420X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CS421X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_CS8409 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_ATI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_SIMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_HDMI_TEGRA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_REALTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_REALTEK_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_SENARYTECH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_SI3054 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_SIGMATEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CODEC_VIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_COMPONENT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_CTL_DEV_ID policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_HDA_DSP_LOADER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_EXT_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_GENERIC_LEDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_HWDEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_I915 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_SND_HDA_INPUT_BEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_INPUT_BEEP_MODE policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_SND_HDA_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_HDA_PATCH_LOADER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_HDA_PREALLOC_SIZE policy<{'amd64': '0', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_SND_HDA_SCODEC_COMPONENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41_I2C policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L41_SPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56_CAL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'riscv64': 'n'}> +CONFIG_SND_HDA_SCODEC_CS35L56_I2C policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_CS35L56_SPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781_I2C policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_SCODEC_TAS2781_SPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDA_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_HDSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HDSPM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HRTIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_HWDEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_I2S_HI6210_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_ICE1712 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_ICE1724 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_IMX_SOC policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_SND_INDIGO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGODJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGODJX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGOIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INDIGOIOX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL8X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL8X0M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL_BYT_PREFER_SOF policy<{'amd64': 'y'}> +CONFIG_SND_INTEL_DSP_CONFIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_INTEL_NHLT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_SND_INTEL_SOUNDWIRE_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_ISIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_JACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_JACK_INPUT_DEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_KIRKWOOD_SOC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_KORG1212 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LAYLA20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LAYLA24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LOLA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_LX6464ES policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MAESTRO3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MAESTRO3_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_MAX_CARDS policy<{'amd64': '32', 'arm64': '32', 'armhf': '32', 'ppc64el': '32', 'riscv64': '32'}> +CONFIG_SND_MESON_AIU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_FIFO policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_FRDDR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_PDM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_SOUND_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_SPDIFIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_SPDIFOUT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDMIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDMOUT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDM_FORMATTER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TDM_INTERFACE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_AXG_TODDR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_CARD_UTILS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_CODEC_GLUE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_G12A_TOACODEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_G12A_TOHDMITX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MESON_GX_SOUND_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MIXART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MIXER_OSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MMP_SOC_SSPA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_MONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MPU401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MPU401_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MTPAV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_MTS64 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_NM256 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OPL3_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OPL3_LIB_SEQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OSSEMUL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_OXFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OXYGEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_OXYGEN_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PCMCIA policy<{'amd64': 'y'}> +CONFIG_SND_PCMTEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PCM_ELD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCM_IEC958 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCM_TIMER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PCSP policy<{'amd64': 'm'}> +CONFIG_SND_PCXHR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PDAUDIOCF policy<{'amd64': 'm'}> +CONFIG_SND_PORTMAN2X4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_PPC policy<{'ppc64el': 'y'}> +CONFIG_SND_PROC_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_PXA910_SOC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_RAWMIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RIPTIDE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RME32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RME96 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_RME9652 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SB_COMMON policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SND_SEQUENCER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQUENCER_OSS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_SEQ_DEVICE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_HRTIMER_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SEQ_MIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_MIDI_EMUL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_MIDI_EVENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_UMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SEQ_UMP_CLIENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SEQ_VIRMIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SERIAL_GENERIC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SERIAL_U16550 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SIMPLE_CARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SIMPLE_CARD_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AC97_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_AC97_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ACPI_AMD_MATCH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ACPI_AMD_SDCA_QUIRKS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ACPI_INTEL_MATCH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ACPI_INTEL_SDCA_QUIRKS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ADAU1372 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1372_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1372_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1373 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1701 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1761_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU1761_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU17X1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7002 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7118_HW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU7118_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADAU_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADI_AXI_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ADI_AXI_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4104 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4118 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4375 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4458 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4554 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4613 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4619 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK4642 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK5386 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AK5558 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ALC5623 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ALC5632 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_AMD_ACP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_ACP3x policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP5x policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP63_TOPLEVEL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP6x policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACPI_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_I2S policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_LEGACY_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_PCI policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_PCM policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ACP_PDM policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_LEGACY_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_LEGACY_SDW_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_MACH_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_PS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_PS_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_RPL_ACP6x policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_RV_RT5682_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SDW_MACH_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOF_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOF_SDW_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOUNDWIRE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_SOUNDWIRE_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_ST_ES8336_MACH policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AMD_VANGOGH_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_AMD_YC_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_APPLE_MCA policy<{'arm64': 'm'}> +CONFIG_SND_SOC_APQ8016_SBC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ARIZONA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AUDIO_IIO_AUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW8738 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW87390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88081 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88166 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88261 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88395 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88395_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_AW88399 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_BD28623 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_BT_SCO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CHV3_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CHV3_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_CPCAP policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CROS_EC_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_CS35L32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L33 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L34 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L35 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L36 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L41_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L45 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L45_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L45_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_SOC_CS35L56_CAL_SET_CTRL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SND_SOC_CS35L56_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_SHARED policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS35L56_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS40L50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4234 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4265 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4270 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4271 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4271_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4271_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L42 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L42_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L42_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L43_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L51 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L51_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L52 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L56 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L73 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L83 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42L84 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42XX8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS42XX8_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS43130 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS4349 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS48L32 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS530X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS530X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS530X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS53L30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CS_AMP_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_CV1800B_ADC_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CV1800B_DAC_CODEC policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CV1800B_TDM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_CX2072X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_DA7213 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_DA7219 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_DAVINCI_MCASP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_DMIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES7134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES7241 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8316 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8323 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8326 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8328 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8328_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8328_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8375 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES8389 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ES83XX_DSM_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_EUKREA_TLV320 policy<{'armhf': 'm'}> +CONFIG_SND_SOC_FRAMER policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FS210X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_ASOC_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_FSL_ASRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_AUD2HTX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_FSL_AUDMIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_EASRC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_ESAI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_MICFIL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_MQS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_RPMSG policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_SAI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_SSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_UTILS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FSL_XCVR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_FS_AMP_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_GTM601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_HDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_HDAC_HDA policy<{'amd64': 'm'}> +CONFIG_SND_SOC_HDMI_CODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_I2C_AND_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ICS43432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_IDT821034 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_IMX_AUDIO_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_AUDMIX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_AUDMUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_IMX_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_ES8328 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_PCM_DMA policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_SND_SOC_IMX_PCM_FIQ policy<{'armhf': 'y'}> +CONFIG_SND_SOC_IMX_PCM_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_RPMSG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_IMX_SGTL5000 policy<{'arm64': 'm', 'armhf': 'y'}> +CONFIG_SND_SOC_INNO_RK3036 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SND_SOC_INTEL_AVS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_CARDNAME_OBSOLETE policy<{'amd64': 'n'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT274 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT286 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT298 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BROADWELL_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH policy<{'amd64': 'n'}> +CONFIG_SND_SOC_INTEL_CATPT policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_HASWELL_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_KEEMBAY policy<{'arm64': 'm'}> +CONFIG_SND_SOC_INTEL_MACH policy<{'amd64': 'y'}> +CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_BOARD_HELPERS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_CIRRUS_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_DA7219_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_NUVOTON_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_TI_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_INTEL_SST_TOPLEVEL policy<{'amd64': 'y'}> +CONFIG_SND_SOC_J721E_EVM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_LOCHNAGAR_SC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_APQ8016 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_CDC_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_CPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_HDMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_IPQ806X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_MACRO_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_PLATFORM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_RX_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_SC7180 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_SC7280 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_LPASS_TX_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_VA_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_LPASS_WSA_MACRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX9759 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98088 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98090 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98357A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98363 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98373 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98373_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98373_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98388 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98390 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98396 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98504 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98520 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX9860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX9867 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MAX98927 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MESON_T9015 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MIKROE_PROTO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MSIOF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MSM8916_WCD_ANALOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MSM8996 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT2701 policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SND_SOC_MT6351 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6357 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6358 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6359 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT6359_ACCDET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT6660 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_MT6797 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT6797_MT6351 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT7986 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT7986_WM8960 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8173 policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_SND_SOC_MT8183 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8183_DA7219_MAX98357A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8186 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8186_MT6366 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8188 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8188_MT6359 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8189 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8189_NAU8825 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8192 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8195 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8195_MT6359 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8365 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MT8365_MT6357 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_MTK_BTCVSD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8315 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8325 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8540 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8810 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8822 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8824 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NAU8825 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_NTP8835 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NTP8918 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_NTPFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_OMAP_MCBSP policy<{'armhf': 'm'}> +CONFIG_SND_SOC_PCM1681 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM1754 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM1789 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM1789_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM179X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM179X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM179X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM186X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM186X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM186X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3060_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3060_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3168A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3168A_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM3168A_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM5102A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM512x policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM512x_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM512x_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PCM6240 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PEB2466 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PM4125 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_PM4125_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QCOM_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QCOM_OFFLOAD_UTILS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QCOM_SDW policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ADM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE_CLOCKS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_AFE_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_APM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_APM_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ASM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ASM_DAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_COMMON policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_CORE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_PRM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_ROUTING policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_QDSP6_USB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RK3288_HDMI_ANALOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RK3308 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_RK3328 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SND_SOC_RK3399_GRU_SOUND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RK817 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RL6231 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RL6347A policy<{'amd64': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_MAX98090 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_PDM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_RT5645 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_SAI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_ROCKCHIP_SPDIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1015P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT1017_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1019 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT1308 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT1308_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1316_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1318_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT1320_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT274 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT286 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT298 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5514 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5514_SPI policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5575 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5575_SPI policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_RT5616 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5631 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5645 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5651 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5659 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5660 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5663 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5670 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_RT5677 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5677_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5682 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5682S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_RT5682_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT5682_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT700_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT711_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT711_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT712_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT715 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT715_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT715_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT721_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT722_SDCA_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT9120 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT9123 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT9123P policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RTQ9124 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RTQ9128 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RT_SDW_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_RZ policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SAMSUNG policy<{'armhf': 'n'}> +CONFIG_SND_SOC_SC7180 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SC7280 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SC8280XP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SDCA policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SDCA_CLASS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SDCA_CLASS_FUNCTION policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SDCA_FDL policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SDCA_HID policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SDCA_IRQ policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SDCA_OPTIONAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SDM845 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SDW_MOCKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SDW_UTILS policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SGTL5000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SH4_FSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SI476X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIGMADSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIGMADSP_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIGMADSP_REGMAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIMPLE_AMPLIFIER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SIMPLE_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SM8250 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_SMA1303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SMA1307 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SND_SOC_SOF_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF_ACPI_DEV policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_ACP_PROBES policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_ALDERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_ACP63 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_ACP70 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_REMBRANDT policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_RENOIR policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_TOPLEVEL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_AMD_VANGOGH policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_APOLLOLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_BAYTRAIL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_BROADWELL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_CANNONLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_CLIENT policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_COFFEELAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_COMETLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_COMPRESS policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_DEBUG_PROBES policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_SND_SOC_SOF_ELKHARTLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_GEMINILAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_GENERIC policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_MLINK policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_HDA_PROBES policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_ICELAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_IMX8 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX9 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_INTEL_APL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_CNL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_COMMON policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_ICL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_LNL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_MTL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_NVL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_PTL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_SKL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_TGL policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_IPC3 policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SND_SOC_SOF_IPC4 policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_JASPERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_KABYLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_LUNARLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_MERRIFIELD policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_METEORLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_MT8186 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MT8195 policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MTK_COMMON policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_MTK_TOPLEVEL policy<{'arm64': 'y'}> +CONFIG_SND_SOC_SOF_NOVALAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_OF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF_OF_DEV policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SOF_PANTHERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SOF_PCI_DEV policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE policy<{'amd64': 'y'}> +CONFIG_SND_SOC_SOF_SKYLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_TIGERLAKE policy<{'amd64': 'm'}> +CONFIG_SND_SOC_SOF_TOPLEVEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SOC_SOF_XTENSA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SND_SOC_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SPRD policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SPRD_MCDT policy<{'arm64': 'm'}> +CONFIG_SND_SOC_SRC4XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SRC4XXX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2305 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2518 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2602 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2602_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM2602_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM3515 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_SSM4567 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STA32X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STA350 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STI_SAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_STM32_DFSDM policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_I2S policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_SAI policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STM32_SPDIFRX policy<{'arm64': 'm'}> +CONFIG_SND_SOC_STORM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TAS2552 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2562 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2764 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_COMLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_COMLIB_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_FMWLIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2781_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS2783_SDW policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SOC_TAS5086 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS571X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS5720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS5805M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TAS6424 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TDA7419 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA186_ASRC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA186_DSPK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_AC97 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_DAS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA20_SPDIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_ADMAIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_ADX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_AHUB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_AMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_DMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_MIXER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_MVC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_OPE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA210_SFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA30_AHUB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA30_I2S policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_ALC5632 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_MACHINE_DRV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_MAX98088 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_MAX98090 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5631 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5640 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_RT5677 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_SGTL5000 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_TRIMSLICE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8753 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_WM8903 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TEGRA_WM9712 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TFA9879 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TFA989X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TI_EDMA_PCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TI_SDMA_PCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TI_UDMA_PCM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_TLV320ADC3XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320ADCX140 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC23_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC31XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC32X4_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TLV320AIC3X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TOPOLOGY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_SND_SOC_TPA6130A2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TS3A227E policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TSCS42XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_TSCS454 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_UDA1334 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_UDA1342 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD9335 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD934X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD937X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD937X_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD938X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD938X_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD939X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD939X_SDW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD_CLASSH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WCD_MBHC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM5102 policy<{'amd64': 'm'}> +CONFIG_SND_SOC_WM8510 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8523 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8524 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8580 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8711 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8728 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8731 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8731_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8731_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8737 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8741 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8750 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8753 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8770 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8776 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8782 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8804 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8804_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8804_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8903 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8904 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8940 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8960 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8961 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8962 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8974 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8978 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8985 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM8994 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_WM8998 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM9712 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_WM_ADSP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WM_HUBS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_WSA881X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WSA883X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_WSA884X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_X1E80100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_XILINX_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_XILINX_SPDIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_XTFPGA_I2S policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOC_ZL38060 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_SOF_SOF_HDA_SDW_BPT policy<{'amd64': 'm'}> +CONFIG_SND_SONICVIBES policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI policy<{'amd64': 'm'}> +CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI policy<{'amd64': 'm'}> +CONFIG_SND_SUN4I_CODEC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SUN4I_I2S policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SUN4I_SPDIF policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SND_SUN50I_CODEC_ANALOG policy<{'arm64': 'm'}> +CONFIG_SND_SUN50I_DMIC policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SND_SUN8I_ADDA_PR_REGMAP policy<{'arm64': 'm'}> +CONFIG_SND_SUN8I_CODEC policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SND_SUN8I_CODEC_ANALOG policy<{'arm64': 'm', 'armhf': '-'}> +CONFIG_SND_SUPPORT_OLD_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_SYNTH_EMUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_TEST_COMPONENT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_TIMER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_TRIDENT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_SND_UMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_UMP_LEGACY_RAWMIDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_6FIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_AUDIO_MIDI_V2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_AUDIO_QMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_CAIAQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_CAIAQ_INPUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_USB_HIFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_LINE6 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_POD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_PODHD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_TONEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_UA101 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_USB_US122L policy<{'amd64': 'm'}> +CONFIG_SND_USB_US144MKII policy<{'amd64': 'm'}> +CONFIG_SND_USB_USX2Y policy<{'amd64': 'm', 'ppc64el': 'm'}> +CONFIG_SND_USB_VARIAX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_UTIMER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_VERBOSE_PROCFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_VIA82XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIA82XX_MODEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIRMIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VIRTUOSO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VMASTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SND_VX222 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_VXPOCKET policy<{'amd64': 'm'}> +CONFIG_SND_VX_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SND_X86 policy<{'amd64': 'y'}> +CONFIG_SND_XEN_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_SND_YMFPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SNET_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SNI_NETSEC policy<{'arm64': 'm'}> +CONFIG_SOCFPGA_FPGA_BRIDGE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SOCFPGA_SUSPEND policy<{'armhf': 'y'}> +CONFIG_SOCIONEXT_SYNQUACER_PREITS policy<{'arm64': 'y'}> +CONFIG_SOCK_CGROUP_DATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOCK_RX_QUEUE_MAPPING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOCK_VALIDATE_XMIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOC_AM33XX policy<{'armhf': 'n'}> +CONFIG_SOC_AM43XX policy<{'armhf': 'n'}> +CONFIG_SOC_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SOC_DRA7XX policy<{'armhf': 'y'}> +CONFIG_SOC_HAS_OMAP2_SDRC policy<{'armhf': 'y'}> +CONFIG_SOC_HAS_REALTIME_COUNTER policy<{'armhf': 'y'}> +CONFIG_SOC_IMX5 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX50 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX51 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX53 policy<{'armhf': 'n'}> +CONFIG_SOC_IMX6 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6Q policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6SL policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6SLL policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6SX policy<{'armhf': 'y'}> +CONFIG_SOC_IMX6UL policy<{'armhf': 'y'}> +CONFIG_SOC_IMX7D policy<{'armhf': 'y'}> +CONFIG_SOC_IMX7D_CA7 policy<{'armhf': 'y'}> +CONFIG_SOC_IMX7ULP policy<{'armhf': 'y'}> +CONFIG_SOC_IMX8M policy<{'arm64': 'y', 'armhf': 'n'}> +CONFIG_SOC_IMX9 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SOC_LS1021A policy<{'armhf': 'n'}> +CONFIG_SOC_OMAP5 policy<{'armhf': 'n'}> +CONFIG_SOC_RENESAS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_SAMSUNG policy<{'armhf': 'y'}> +CONFIG_SOC_SP7021 policy<{'armhf': 'y'}> +CONFIG_SOC_STARFIVE policy<{'riscv64': 'n'}> +CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER policy<{'armhf': 'y'}> +CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER policy<{'armhf': 'y'}> +CONFIG_SOC_TEGRA_CBB policy<{'arm64': 'm'}> +CONFIG_SOC_TEGRA_FLOWCTRL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TEGRA_FUSE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TEGRA_PMC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TEGRA_POWERGATE_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SOC_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SOC_VF610 policy<{'armhf': 'y'}> +CONFIG_SOFTIRQ_ON_OWN_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOFTLOCKUP_DETECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SOFT_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SOFT_WATCHDOG_PRETIMEOUT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SOLARIS_X86_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SONYPI_COMPAT policy<{'amd64': 'y'}> +CONFIG_SONY_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SONY_LAPTOP policy<{'amd64': 'm'}> +CONFIG_SOPHGO_CV1800B_ADC policy<{'arm64': 'n', 'riscv64': '-'}> +CONFIG_SOPHGO_CV1800B_DMAMUX policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SOPHGO_CV1800_RTCSYS policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SOPHGO_SG2042_MSI policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_SOPHGO_SG2044_TOPSYS policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SOUNDWIRE_AMD policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_CADENCE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_INTEL policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SOUNDWIRE_QCOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SOUND_OSS_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SP5100_TCO policy<{'amd64': 'm'}> +CONFIG_SP7021_EMAC policy<{'armhf': 'm'}> +CONFIG_SPAPR_TCE_IOMMU policy<{'ppc64el': 'y'}> +CONFIG_SPARSEMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_EXTREME policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_MANUAL policy<{'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPARSEMEM_STATIC policy<{'armhf': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP_ENABLE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARSEMEM_VMEMMAP_PREINIT policy<{'amd64': 'y'}> +CONFIG_SPARSE_IRQ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPARX5_DCB policy<{'arm64': 'y'}> +CONFIG_SPARX5_SWITCH policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-'}> +CONFIG_SPEAKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_ACNTSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_APOLLO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_AUDPTR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_BNS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DECEXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DECTLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_LTLK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_SOFT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_SPKOUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPEAKUP_SYNTH_TXPRT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SPI_AIROHA_SNFI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_ALTERA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_ALTERA_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_ALTERA_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_AMD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_AMLOGIC_SPIFC_A1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_AMLOGIC_SPIFC_A4 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_AMLOGIC_SPISG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_APPLE policy<{'arm64': 'm'}> +CONFIG_SPI_ARMADA_3700 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_ASPEED_SMC policy<{'armhf': 'm'}> +CONFIG_SPI_ATMEL policy<{'arm64': 'm'}> +CONFIG_SPI_AX88796C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_AX88796C_COMPRESSION policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SPI_AXIADO policy<{'arm64': 'm'}> +CONFIG_SPI_AXI_SPI_ENGINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_BITBANG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_BUTTERFLY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CADENCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_CADENCE_QUADSPI policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CADENCE_XSPI policy<{'arm64': 'm', 'armhf': '-', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CH341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_CS42L43 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_SPI_DESIGNWARE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_DLN2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DW_DMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_DW_MMIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DW_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_FSI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_FSL_DSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_FSL_LIB policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_FSL_LPSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_FSL_QUADSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_FSL_SPI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_GXP policy<{'armhf': 'm'}> +CONFIG_SPI_HISI_KUNPENG policy<{'arm64': 'm'}> +CONFIG_SPI_HISI_SFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_HISI_SFC_V3XX policy<{'arm64': 'm'}> +CONFIG_SPI_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_INTEL policy<{'amd64': 'm'}> +CONFIG_SPI_INTEL_PCI policy<{'amd64': 'm'}> +CONFIG_SPI_INTEL_PLATFORM policy<{'amd64': 'm'}> +CONFIG_SPI_KSPI2 policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SPI_LANTIQ_SSC policy<{'amd64': 'm'}> +CONFIG_SPI_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_SPI_LM70_LLP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_LOOPBACK_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_MASTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_MEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_MESON_SPICC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MESON_SPIFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MICROCHIP_CORE_QSPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_MICROCHIP_CORE_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_MT65XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MTK_NOR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MTK_SNFI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_MUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_MXIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_NPCM_FIU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_NPCM_PSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_NXP_FLEXSPI policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_SPI_NXP_XSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_OC_TINY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_OFFLOAD_TRIGGER_PWM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_OMAP24XX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SPI_ORION policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_PCI1XXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_PL022 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_SPI_POLARFIRE_SOC policy<{'arm64': 'm'}> +CONFIG_SPI_PXA2XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_SPI_PXA2XX_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SPI_QCOM_GENI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_QCOM_QSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_QPIC_SNAND policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_QUP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_ROCKCHIP policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-', 's390x': '-'}> +CONFIG_SPI_ROCKCHIP_SFC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RPCIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RZV2H_RSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_RZV2M_CSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_S3C64XX policy<{'armhf': 'n'}> +CONFIG_SPI_SC18IS602 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SG2044_NOR policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SPI_SH_HSPI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_SH_MSIOF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_SIFIVE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SLAVE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SPI_SLAVE_MT27XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_SLAVE_SYSTEM_CONTROL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SLAVE_TIME policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SN_F_OSPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_SPIDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_SPRD policy<{'arm64': 'm'}> +CONFIG_SPI_SPRD_ADI policy<{'arm64': 'm'}> +CONFIG_SPI_STM32 policy<{'arm64': 'm'}> +CONFIG_SPI_STM32_OSPI policy<{'arm64': 'm'}> +CONFIG_SPI_STM32_QSPI policy<{'arm64': 'm'}> +CONFIG_SPI_SUN4I policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SPI_SUN6I policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SPI_SUNPLUS_SP7021 policy<{'armhf': 'm'}> +CONFIG_SPI_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_SPI_TEGRA114 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_TEGRA20_SFLASH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_TEGRA20_SLINK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_TEGRA210_QUAD policy<{'arm64': 'y', 'armhf': 'm'}> +CONFIG_SPI_THUNDERX policy<{'arm64': 'm'}> +CONFIG_SPI_TI_QSPI policy<{'armhf': 'm'}> +CONFIG_SPI_TLE62X0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_VIRTIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPI_WPCM_FIU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPI_XCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_XILINX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPI_XLP policy<{'arm64': 'm'}> +CONFIG_SPI_ZYNQMP_GQSPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SPLIT_PMD_PTLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPLIT_PTE_PTLOCKS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SPMI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SPMI_APPLE policy<{'arm64': 'm'}> +CONFIG_SPMI_HISI3670 policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_SPMI_MSM_PMIC_ARB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPMI_MTK_PMIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPMI_PMIC_CLKDIV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_SPRD_COMMON_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_DMA policy<{'arm64': 'm'}> +CONFIG_SPRD_IOMMU policy<{'arm64': 'm'}> +CONFIG_SPRD_MBOX policy<{'arm64': 'm'}> +CONFIG_SPRD_SC9860_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_SC9863A_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_THERMAL policy<{'arm64': 'm'}> +CONFIG_SPRD_TIMER policy<{'arm64': 'y'}> +CONFIG_SPRD_UMS512_CLK policy<{'arm64': 'm'}> +CONFIG_SPRD_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_SPS30 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPS30_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SPS30_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_COMP_CACHE_FULL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_DECOMP_MULTI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_DECOMP_SINGLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_EMBEDDED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_FILE_CACHE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SQUASHFS_FILE_DIRECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE policy<{'amd64': '3', 'arm64': '3', 'armhf': '3', 'ppc64el': '3', 'riscv64': '3', 's390x': '3'}> +CONFIG_SQUASHFS_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_XZ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_ZLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SQUASHFS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SRAM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SRAM_EXEC policy<{'armhf': 'y'}> +CONFIG_SRF04 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SRF08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_SSB_B43_PCI_BRIDGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_BLOCKIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_DRIVER_GPIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_SSB_DRIVER_PCICORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_PCIHOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_SSB_PCIHOST_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_PCMCIAHOST policy<{'amd64': 'n'}> +CONFIG_SSB_PCMCIAHOST_POSSIBLE policy<{'amd64': 'y'}> +CONFIG_SSB_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SSB_SDIOHOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_SDIOHOST_POSSIBLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSB_SPROM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SSFDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SSIF_IPMI_BMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STACKDEPOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STACKDEPOT_MAX_FRAMES policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64', 's390x': '64'}> +CONFIG_STACKPROTECTOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STACKPROTECTOR_PER_TASK policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_STACKPROTECTOR_STRONG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STACKTRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STACKTRACE_BUILD_ID policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STACKTRACE_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STACK_TRACER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STAGING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_STAGING_MEDIA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STAGING_MEDIA_DEPRECATED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_STANDALONE policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STATIC_CALL_SELFTEST policy<{'amd64': 'n'}> +CONFIG_STATIC_KEYS_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STATIC_USERMODEHELPER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STE10XP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STEAM_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STK3310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STK8312 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STK8BA50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM32MP_EXTI policy<{'arm64': 'm'}> +CONFIG_STM32_ADC policy<{'arm64': 'm'}> +CONFIG_STM32_ADC_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DAC policy<{'arm64': 'm'}> +CONFIG_STM32_DAC_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DFSDM_ADC policy<{'arm64': 'm'}> +CONFIG_STM32_DFSDM_CORE policy<{'arm64': 'm'}> +CONFIG_STM32_DMA policy<{'arm64': 'y'}> +CONFIG_STM32_DMA3 policy<{'arm64': 'm'}> +CONFIG_STM32_DMAMUX policy<{'arm64': 'y'}> +CONFIG_STM32_FIREWALL policy<{'arm64': 'y'}> +CONFIG_STM32_FMC2_EBI policy<{'arm64': 'm'}> +CONFIG_STM32_LPTIMER_CNT policy<{'arm64': 'm'}> +CONFIG_STM32_MDMA policy<{'arm64': 'y'}> +CONFIG_STM32_OMM policy<{'arm64': 'm'}> +CONFIG_STM32_RPROC policy<{'arm64': 'm'}> +CONFIG_STM32_TIMER_CNT policy<{'arm64': 'm'}> +CONFIG_STM32_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_STMMAC_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_STMMAC_LIBPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMMAC_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMMAC_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMMAC_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_STMPE_ADC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STMPE_I2C policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STMPE_SPI policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_STMP_DEVICE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_STM_DUMMY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_PROTO_BASIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_PROTO_SYS_T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_SOURCE_CONSOLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_SOURCE_FTRACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STM_SOURCE_HEARTBEAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_STPMIC1_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_STREAM_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_DEVMEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_KERNEL_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_MM_TYPECHECKS policy<{'s390x': 'y'}> +CONFIG_STRICT_MODULE_RWX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_STRICT_SIGALTSTACK_SIZE policy<{'amd64': 'n'}> +CONFIG_STRIP_ASM_SYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_STUB_CLK_HI3660 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_STUB_CLK_HI6220 policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_STX104 policy<{'amd64': 'm'}> +CONFIG_ST_THERMAL policy<{'arm64': 'm'}> +CONFIG_ST_THERMAL_MEMMAP policy<{'arm64': 'm'}> +CONFIG_ST_UVIS25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ST_UVIS25_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ST_UVIS25_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SUN20I_GPADC policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SUN20I_PPU policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_SUN4I_EMAC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN4I_GPADC policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN4I_TIMER policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN50I_A100_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_A100_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_A64_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_DE2_BUS policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN50I_ERRATUM_UNKNOWN1 policy<{'arm64': 'y'}> +CONFIG_SUN50I_H616_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_H6_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_H6_PRCM_PPU policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SUN50I_H6_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN50I_IOMMU policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN55I_A523_CCU policy<{'arm64': 'y'}> +CONFIG_SUN55I_A523_MCU_CCU policy<{'arm64': 'm'}> +CONFIG_SUN55I_A523_R_CCU policy<{'arm64': 'y'}> +CONFIG_SUN55I_PCK600 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_SUN6I_MSGBOX policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN6I_RTC_CCU policy<{'arm64': 'm'}> +CONFIG_SUN6I_R_INTC policy<{'arm64': 'y'}> +CONFIG_SUN8I_DE2_CCU policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN8I_H3_CCU policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SUN8I_R_CCU policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_SUN8I_THERMAL policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUNDANCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SUNDANCE_MMIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SUNGEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SUNGEM_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SUNPLUS_SP7021_INTC policy<{'armhf': 'y'}> +CONFIG_SUNPLUS_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_SUNRPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SUNRPC_BACKCHANNEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SUNRPC_DEBUG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SUNRPC_DEBUG_TRACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SUNRPC_GSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SUNRPC_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SUNRPC_XPRT_RDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_SUNXI_CCU policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUNXI_MBUS policy<{'arm64': 'y'}> +CONFIG_SUNXI_NMI_INTC policy<{'arm64': 'y'}> +CONFIG_SUNXI_RSB policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUNXI_SRAM policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_SUNXI_WATCHDOG policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_SUN_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SURFACE3_WMI policy<{'amd64': 'm'}> +CONFIG_SURFACE_3_POWER_OPREGION policy<{'amd64': 'm', 'arm64': 'n'}> +CONFIG_SURFACE_ACPI_NOTIFY policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_BUS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SURFACE_AGGREGATOR_CDEV policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_SURFACE_AGGREGATOR_HUB policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_REGISTRY policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_DTX policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_GPE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_HID policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_HID_CORE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_HOTPLUG policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_KBD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_PLATFORMS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SURFACE_PLATFORM_PROFILE policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_SURFACE_PRO3_BUTTON policy<{'amd64': 'm', 'arm64': 'n'}> +CONFIG_SUSPEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SUSPEND_FREEZER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_SUSPEND_SKIP_SYNC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_SVC_I3C_MASTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWIOTLB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWIOTLB_DYNAMIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWIOTLB_XEN policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_SWPHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SWP_EMULATE policy<{'armhf': 'y'}> +CONFIG_SW_SYNC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SX9310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SX9324 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SX9360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SX9500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SXGBE_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SX_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SYMBOLIC_ERRNAME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYNC_FILE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYNTH_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYNTH_EVENT_GEN_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SYN_COOKIES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSCON_REBOOT_MODE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW policy<{'riscv64': 'y'}> +CONFIG_SYSCTL_EXCEPTION_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSC_R8A7742 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7743 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7745 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A77470 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A774A1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774B1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774C0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A774E1 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A7779 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7790 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7791 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7792 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7794 policy<{'armhf': 'y'}> +CONFIG_SYSC_R8A7795 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77960 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77961 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77965 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77970 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77980 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77990 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A77995 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779A0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779F0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779G0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R8A779H0 policy<{'arm64': 'y'}> +CONFIG_SYSC_R9A08G045 policy<{'arm64': 'y'}> +CONFIG_SYSC_RCAR policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SYSC_RCAR_GEN4 policy<{'arm64': 'y'}> +CONFIG_SYSC_RMOBILE policy<{'armhf': 'y'}> +CONFIG_SYSC_RZ policy<{'arm64': 'y'}> +CONFIG_SYSFB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSFS_SYSCALL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM76_ACPI policy<{'amd64': 'm'}> +CONFIG_SYSTEMPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_SYSTEM_BLACKLIST_HASH_LIST policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_SYSTEM_BLACKLIST_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_DATA_VERIFICATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_EXTRA_CERTIFICATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE policy<{'amd64': '4096', 'arm64': '4096', 'armhf': '4096', 'ppc64el': '4096', 'riscv64': '4096', 's390x': '4096'}> +CONFIG_SYSTEM_REVOCATION_KEYS policy<{'amd64': '"debian/canonical-revoked-certs.pem"', 'arm64': '"debian/canonical-revoked-certs.pem"', 'armhf': '"debian/canonical-revoked-certs.pem"', 'ppc64el': '"debian/canonical-revoked-certs.pem"', 'riscv64': '"debian/canonical-revoked-certs.pem"', 's390x': '"debian/canonical-revoked-certs.pem"'}> +CONFIG_SYSTEM_REVOCATION_LIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_TRUSTED_KEYRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSTEM_TRUSTED_KEYS policy<{'amd64': '"debian/canonical-certs.pem"', 'arm64': '"debian/canonical-certs.pem"', 'armhf': '"debian/canonical-certs.pem"', 'ppc64el': '"debian/canonical-certs.pem"', 'riscv64': '"debian/canonical-certs.pem"', 's390x': '"debian/canonical-certs.pem"'}> +CONFIG_SYSV68_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_SYSVIPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYSVIPC_COMPAT policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'ppc64el': '-', 's390x': '-'}> +CONFIG_SYSVIPC_SYSCTL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_SYS_HYPERVISOR policy<{'amd64': 'y', 'arm64': 'y', 's390x': 'y'}> +CONFIG_SYS_R9A09G047 policy<{'arm64': 'y'}> +CONFIG_SYS_R9A09G056 policy<{'arm64': 'y'}> +CONFIG_SYS_R9A09G057 policy<{'arm64': 'y'}> +CONFIG_SYS_SUPPORTS_APM_EMULATION policy<{'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_EM_STI policy<{'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_SH_CMT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_SH_MTU2 policy<{'armhf': 'y'}> +CONFIG_SYS_SUPPORTS_SH_TMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_T5403 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TABLET_SERIAL_WACOM4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_ACECAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_AIPTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_HANWANG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_KBTAB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TABLET_USB_PEGASUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TAHVO_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TAHVO_USB_HOST_BY_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TARGET_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TARGET_CPU policy<{'ppc64el': '"power8"'}> +CONFIG_TARGET_CPU_BOOL policy<{'ppc64el': 'y'}> +CONFIG_TASKSTATS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_RCU_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_RUDE_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASKS_TRACE_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASK_DELAY_ACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASK_IO_ACCOUNTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TASK_XACCT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCG_ARM_CRB_FFA policy<{'arm64': 'm'}> +CONFIG_TCG_ATMEL policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCG_CRB policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_TCG_FTPM_TEE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TCG_IBMVTPM policy<{'ppc64el': 'y'}> +CONFIG_TCG_INFINEON policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_TCG_NSC policy<{'amd64': 'm'}> +CONFIG_TCG_SVSM policy<{'amd64': 'm'}> +CONFIG_TCG_TIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TCG_TIS_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TCG_TIS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_I2C_CR50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_SPI policy<{'amd64': 'm', 'arm64': 'y', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TCG_TIS_SPI_CR50 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TCG_TIS_ST33ZP24 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCG_TIS_ST33ZP24_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TCG_TIS_ST33ZP24_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TCG_TIS_SYNQUACER policy<{'arm64': 'm'}> +CONFIG_TCG_TPM2_HMAC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TCG_VTPM_PROXY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCG_XEN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_TCM_FC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_FILEIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_IBLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_PSCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCM_QLA2XXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCM_QLA2XXX_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TCM_USER2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_AO policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_CONG_ADVANCED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_CONG_BBR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_BIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_CDG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_CUBIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_CONG_DCTCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_HSTCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_HTCP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_HYBLA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_ILLINOIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_LP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_NV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_SCALABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_VEGAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_VENO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_WESTWOOD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_CONG_YEAH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TCP_MD5SIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCP_SIGPOOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TCS3414 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TCS3472 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TDX_GUEST_DRIVER policy<{'amd64': 'm'}> +CONFIG_TEE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEE_DMABUF_HEAPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEE_STMM_EFI policy<{'arm64-generic': 'n', 'arm64-generic-64k': 'm', 'armhf': 'm'}> +CONFIG_TEGRA124_CLK_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA124_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA186_GPC_DMA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA186_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA20_APB_DMA policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA20_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA210_ADMA policy<{'arm64': 'm', 'armhf': 'n'}> +CONFIG_TEGRA210_EMC policy<{'arm64': 'm'}> +CONFIG_TEGRA210_EMC_TABLE policy<{'arm64': 'y'}> +CONFIG_TEGRA241_CMDQV policy<{'arm64': 'y'}> +CONFIG_TEGRA30_EMC policy<{'armhf': 'y'}> +CONFIG_TEGRA30_TSENSOR policy<{'armhf': 'm'}> +CONFIG_TEGRA_ACONNECT policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_AHB policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_BPMP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_BPMP_THERMAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_CLK_DFLL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_GMI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_HOST1X policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEGRA_HOST1X_CONTEXT_BUS policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_HOST1X_FIREWALL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_HSP_MBOX policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_IOMMU_SMMU policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_IVC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_MC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_SOCTHERM policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_TEGRA_TIMER policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TEGRA_WATCHDOG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TEHUTI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TEHUTI_TN40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TELCLOCK policy<{'amd64': 'm'}> +CONFIG_TERANETICS_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEST_ASYNC_DRIVER_PROBE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_BITMAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_BITOPS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_BPF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEST_CLOCKSOURCE_WATCHDOG policy<{'amd64': 'n'}> +CONFIG_TEST_DHRY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_DIV64 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_DYNAMIC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_FIRMWARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_FPU policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_TEST_FREE_PAGES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_HEXDUMP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_HMM policy<{'amd64': 'n', 'arm64': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_IDA policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_KALLSYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_KEXEC_HANDOVER policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_TEST_KMOD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_KSTRTOX policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_LKM policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_LOCKUP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MAPLE_TREE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MEMCAT_P policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MEMINIT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_MULDIV64 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_OBJAGG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_OBJPOOL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_PARMAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TEST_REF_TRACKER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_RHASHTABLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_STATIC_KEYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_SYSCTL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_UBSAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_TEST_UDELAY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_VMALLOC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEST_XARRAY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TEXTSEARCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TEXTSEARCH_BM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEXTSEARCH_FSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TEXTSEARCH_KMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_THERMAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_THERMAL_CORE_TESTING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_THERMAL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0'}> +CONFIG_THERMAL_EMULATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_BANG_BANG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_FAIR_SHARE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_POWER_ALLOCATOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_STEP_WISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_GOV_USER_SPACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_MMIO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_THERMAL_NETLINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THERMAL_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THINKPAD_ACPI policy<{'amd64': 'm'}> +CONFIG_THINKPAD_ACPI_ALSA_SUPPORT policy<{'amd64': 'y'}> +CONFIG_THINKPAD_ACPI_DEBUG policy<{'amd64': 'n'}> +CONFIG_THINKPAD_ACPI_DEBUGFACILITIES policy<{'amd64': 'y'}> +CONFIG_THINKPAD_ACPI_HOTKEY_POLL policy<{'amd64': 'y'}> +CONFIG_THINKPAD_ACPI_UNSAFE_LEDS policy<{'amd64': 'n'}> +CONFIG_THINKPAD_ACPI_VIDEO policy<{'amd64': 'y'}> +CONFIG_THINKPAD_LMI policy<{'amd64': 'm'}> +CONFIG_THP_SWAP policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_THREAD_INFO_IN_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_THREAD_SHIFT policy<{'ppc64el': '14'}> +CONFIG_THREAD_SIZE_ORDER policy<{'riscv64': '2'}> +CONFIG_THRUSTMASTER_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_THUMB2_KERNEL policy<{'armhf': 'n'}> +CONFIG_THUNDERX2_PMU policy<{'arm64': 'm'}> +CONFIG_THUNDER_NIC_BGX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_THUNDER_NIC_PF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_THUNDER_NIC_RGX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_THUNDER_NIC_VF policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TICK_CPU_ACCOUNTING policy<{'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_TICK_ONESHOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIFM_7XX1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TIFM_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TIGON3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TIGON3_HWMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TIMERFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIMER_ACPI policy<{'arm64': 'y'}> +CONFIG_TIMER_IMX_SYS_CTR policy<{'arm64': 'y'}> +CONFIG_TIMER_OF policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_TIMER_PROBE policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y'}> +CONFIG_TIME_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TINYDRM_HX8357D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_ILI9163 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TINYDRM_ILI9225 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_ILI9341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_ILI9486 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_MI0283QT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_REPAPER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TINYDRM_SHARP_MEMORY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TIPC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TIPC_CRYPTO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIPC_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TIPC_MEDIA_IB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TIPC_MEDIA_UDP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TI_ADC081C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC0832 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC084S021 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC108S102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC12138 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC128S052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADC161S626 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1015 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1018 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1119 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS124S08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS1298 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS131E08 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS131M02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS7138 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS7924 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS7950 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS8344 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_ADS8688 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_AM335X_ADC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_TI_AM65_CPSW_QOS policy<{'arm64': 'y'}> +CONFIG_TI_CPPI41 policy<{'armhf': 'm'}> +CONFIG_TI_CPSW policy<{'armhf': 'y'}> +CONFIG_TI_CPSW_PHY_SEL policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TI_CPSW_SWITCHDEV policy<{'armhf': 'm'}> +CONFIG_TI_CPTS policy<{'armhf': 'y'}> +CONFIG_TI_DAC082S085 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAC5571 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAC7311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAC7612 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_DAVINCI_MDIO policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TI_DMA_CROSSBAR policy<{'armhf': 'y'}> +CONFIG_TI_ECAP_CAPTURE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_EDMA policy<{'armhf': 'y'}> +CONFIG_TI_EMIF policy<{'armhf': 'm'}> +CONFIG_TI_EQEP policy<{'arm64': 'm'}> +CONFIG_TI_FPC202 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TI_ICSSG_PRUETH policy<{'arm64': 'm'}> +CONFIG_TI_ICSSG_PRUETH_SR1 policy<{'arm64': 'm'}> +CONFIG_TI_ICSS_IEP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_K3_AM65_CPSW_NUSS policy<{'arm64': 'm'}> +CONFIG_TI_K3_AM65_CPSW_SWITCHDEV policy<{'arm64': 'y'}> +CONFIG_TI_K3_AM65_CPTS policy<{'arm64': 'm'}> +CONFIG_TI_K3_CPPI_DESC_POOL policy<{'arm64': 'm'}> +CONFIG_TI_K3_DSP_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_TI_K3_M4_REMOTEPROC policy<{'arm64': 'n', 'armhf': '-'}> +CONFIG_TI_K3_PSIL policy<{'arm64': 'y'}> +CONFIG_TI_K3_R5_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_TI_K3_RINGACC policy<{'arm64': 'y'}> +CONFIG_TI_K3_SOCINFO policy<{'arm64': 'y'}> +CONFIG_TI_K3_UDMA policy<{'arm64': 'y'}> +CONFIG_TI_K3_UDMA_GLUE_LAYER policy<{'arm64': 'y'}> +CONFIG_TI_LMP92064 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_MESSAGE_MANAGER policy<{'arm64': 'y'}> +CONFIG_TI_PIPE3 policy<{'armhf': 'm'}> +CONFIG_TI_PRUETH policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_PRUSS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_PRUSS_INTC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TI_PWMSS policy<{'armhf': 'y'}> +CONFIG_TI_SCI_CLK policy<{'arm64': 'm'}> +CONFIG_TI_SCI_CLK_PROBE_FROM_FW policy<{'arm64': 'n'}> +CONFIG_TI_SCI_INTA_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_TI_SCI_INTA_MSI_DOMAIN policy<{'arm64': 'y'}> +CONFIG_TI_SCI_INTR_IRQCHIP policy<{'arm64': 'y'}> +CONFIG_TI_SCI_PM_DOMAINS policy<{'arm64': 'm'}> +CONFIG_TI_SCI_PROTOCOL policy<{'arm64': 'y'}> +CONFIG_TI_SOC_THERMAL policy<{'arm64': '-', 'armhf': 'n', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_TI_SYSC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TI_SYSCON_CLK policy<{'arm64': 'y'}> +CONFIG_TI_TLC4541 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_TMAG5273 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TI_TSC2046 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TLS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TLS_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TLS_TOE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TMP006 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TMP007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TMP117 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TMPFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_INODE64 policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_QUOTA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TMPFS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TN3215 policy<{'s390x': 'y'}> +CONFIG_TN3215_CONSOLE policy<{'s390x': 'y'}> +CONFIG_TN3270 policy<{'s390x': 'y'}> +CONFIG_TN3270_CONSOLE policy<{'s390x': 'y'}> +CONFIG_TN3270_FS policy<{'s390x': 'm'}> +CONFIG_TOOLCHAIN_DEFAULT_CPU policy<{'ppc64el': 'n'}> +CONFIG_TOOLCHAIN_HAS_V policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_VECTOR_CRYPTO policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZABHA policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZACAS policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBA policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBB policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBC policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_HAS_ZBKB policy<{'riscv64': 'y'}> +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI policy<{'riscv64': 'y'}> +CONFIG_TOOLS_SUPPORT_RELR policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y'}> +CONFIG_TOPSTAR_LAPTOP policy<{'amd64': 'm'}> +CONFIG_TOSHIBA_BT_RFKILL policy<{'amd64': 'm'}> +CONFIG_TOSHIBA_HAPS policy<{'amd64': 'm'}> +CONFIG_TOSHIBA_WMI policy<{'amd64': 'n'}> +CONFIG_TOUCHSCREEN_88PM860X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AD7877 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AD7879 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AD7879_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_AD7879_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ADS7846 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_AR1021_I2C policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ATMEL_MXT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_AUO_PIXCIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_BU21013 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_BU21029 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_COLIBRI_VF50 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CY8CTMA140 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CY8CTMG110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CYTTSP5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_CYTTSP_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_CYTTSP_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_DA9034 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_DA9052 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_DMI policy<{'amd64': 'y'}> +CONFIG_TOUCHSCREEN_DYNAPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EDT_FT5X06 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EETI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EGALAX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_EGALAX_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EKTF2127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ELO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_EXC3000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_FUJITSU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_GOODIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_GUNZE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HAMPSHIRE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HIDEEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HIMAX_HX83112B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_HIMAX_HX852X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_HYCON_HY46XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_HYNITRON_CST816X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ILI210X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ILITEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_IMAGIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_IMX6UL_TSC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_INEXIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_IQS5XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_IQS7211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_MAX11801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MC13783 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_MELFAS_MIP4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MMS114 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MSG2638 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_MTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_PCAP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_PENMOUNT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_PIXCIR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_RM_TS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ROHM_BU21023 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_S6SY761 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_SILEAD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_SIS_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ST1232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_STMFTS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_STMPE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_SUN4I policy<{'arm64': 'n', 'armhf': '-', 'riscv64': '-'}> +CONFIG_TOUCHSCREEN_SUR40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_SURFACE3_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_SX8654 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TI_AM335X_TSC policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_TOUCHSCREEN_TOUCHIT213 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TOUCHRIGHT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TOUCHWIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TPS6507X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TS4800 policy<{'armhf': 'm'}> +CONFIG_TOUCHSCREEN_TSC2004 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TSC2005 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TSC2007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_TSC2007_IIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_TSC200X_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_TSC_SERIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_USB_3M policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_COMPOSITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_USB_DMC_TSC10 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_E2I policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_EASYTOUCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_EGALAX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ELO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ETURBO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GOTOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_GUNZE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_IDEALTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_IRTOUCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ITM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_JASTEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_NEXIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_PANJIT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_USB_ZYTRONIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WACOM_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WACOM_W8001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WDT87XX_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WM831X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_WM9705 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WM9712 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WM9713 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TOUCHSCREEN_WM97XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TOUCHSCREEN_ZET6223 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ZFORCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TOUCHSCREEN_ZINITIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TPL0102 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TPS6105X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TPS65010 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TPS6507X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_TPS6594_ESM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TPS6594_PFSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TPS68470_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_TQMX86_WDT policy<{'amd64': 'm'}> +CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACEPOINTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACEPOINT_BENCHMARK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACER_MAX_TRACE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACER_SNAPSHOT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACE_CLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACE_EVAL_MAP_FILE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACE_EVENT_INJECT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACE_GPU_MEM policy<{'amd64': 'n', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRACE_IRQFLAGS policy<{'armhf': 'y'}> +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_TRACE_IRQFLAGS_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACE_MMIO_ACCESS policy<{'arm64': 'y', 's390x': 'y'}> +CONFIG_TRACE_SYSCALL_BUF_SIZE_DEFAULT policy<{'amd64': '63', 'arm64': '63', 'armhf': '63', 'ppc64el': '63', 'riscv64': '63', 's390x': '63'}> +CONFIG_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACING_MAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRACING_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'y', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'n', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_NEVER policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ADVISE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_ALWAYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_NEVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_SHMEM_HUGE_WITHIN_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ADVISE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_ALWAYS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_NEVER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRANSPARENT_HUGEPAGE_TMPFS_HUGE_WITHIN_SIZE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRANS_TABLE policy<{'arm64': 'y'}> +CONFIG_TREE_RCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TREE_SRCU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRIM_UNUSED_KSYMS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TRUSTED_FOUNDATIONS policy<{'armhf': 'y'}> +CONFIG_TRUSTED_KEYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TRUSTED_KEYS_PKWM policy<{'ppc64el': 'y'}> +CONFIG_TRUSTED_KEYS_TPM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TS4800_IRQ policy<{'armhf': 'm'}> +CONFIG_TS4800_WATCHDOG policy<{'armhf': 'm'}> +CONFIG_TSL2583 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSL2591 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSL2772 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSL4531 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TSM_GUEST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TSM_MEASUREMENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_TSM_REPORTS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_TSNEP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_TSNEP_SELFTESTS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TSYS01 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TSYS02D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TTPCI_EEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TTY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TTY_PRINTK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_TTY_PRINTK_LEVEL policy<{'amd64': '6', 'arm64': '6', 'armhf': '6', 'ppc64el': '6', 'riscv64': '6'}> +CONFIG_TULIP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TULIP_MMIO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TULIP_MWI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TULIP_NAPI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_TUN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_TUNE_CPU policy<{'ppc64el': '"-mtune=power10"'}> +CONFIG_TUNE_DEFAULT policy<{'s390x': 'n'}> +CONFIG_TUNE_GENERIC policy<{'riscv64': 'y'}> +CONFIG_TUNE_Z10 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z13 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z14 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z15 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z17 policy<{'s390x': 'n'}> +CONFIG_TUNE_Z196 policy<{'s390x': 'n'}> +CONFIG_TUNE_ZEC12 policy<{'s390x': 'n'}> +CONFIG_TUN_VNET_CROSS_LE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_TURRIS_MOX_RWTM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TURRIS_MOX_RWTM_KEYCTL policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU policy<{'armhf': 'm'}> +CONFIG_TURRIS_OMNIA_MCU_GPIO policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_KEYCTL policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_SYSOFF_WAKEUP policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_TRNG policy<{'armhf': 'y'}> +CONFIG_TURRIS_OMNIA_MCU_WATCHDOG policy<{'armhf': 'y'}> +CONFIG_TURRIS_SIGNING_KEY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TUXEDO_NB04_WMI_AB policy<{'amd64': 'm'}> +CONFIG_TWL4030_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_TWL4030_MADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TWL4030_POWER policy<{'armhf': 'y'}> +CONFIG_TWL4030_USB policy<{'armhf': 'm'}> +CONFIG_TWL4030_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TWL6030_GPADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TWL6030_USB policy<{'armhf': 'm'}> +CONFIG_TWL6040_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_TXGBE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TXGBEVF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_TYPEC_ANX7411 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_DP_ALTMODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_FUSB302 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_HD3SS3220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MT6360 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_FSA4480 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_GPIO_SBU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_INTEL_PMC policy<{'amd64': 'm'}> +CONFIG_TYPEC_MUX_IT5205 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_NB7VPQ904M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_PI3USB30532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_PS883X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_PTN36502 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_TUSB1046 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_MUX_WCD939X_USBSS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_NVIDIA_ALTMODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_QCOM_PMIC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_TYPEC_RT1711H policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_RT1719 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_STUSB160X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TBT_ALTMODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPCI_MAXIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPCI_MT6370 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TCPM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_TPS6598X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_UCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPEC_WCOVE policy<{'amd64': 'm'}> +CONFIG_TYPEC_WUSB3801 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_TYPHOON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_UACCE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UACCESS_WITH_MEMCPY policy<{'armhf': 'n'}> +CONFIG_UBIFS_ATIME_SUPPORT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UBIFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UBIFS_FS_ADVANCED_COMPR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UBIFS_FS_AUTHENTICATION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_SECURITY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_XATTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_ZLIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBIFS_FS_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UBSAN_ALIGNMENT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UBSAN_BOOL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_BOUNDS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_BOUNDS_STRICT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_DIV_ZERO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UBSAN_ENUM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_KVM_EL2 policy<{'arm64': 'n'}> +CONFIG_UBSAN_SHIFT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 's390x': 'y'}> +CONFIG_UBSAN_TRAP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UBSAN_UNREACHABLE policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 's390x': 'n'}> +CONFIG_UBUNTU_HOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_UBUNTU_ODM_DRIVERS policy<{'amd64': 'y', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_UCC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_UCC_FAST policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_UCC_SLOW policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y'}> +CONFIG_UCLAMP_BUCKETS_COUNT policy<{'amd64': '5', 'arm64': '5', 'armhf': '5', 'ppc64el': '5', 'riscv64': '5'}> +CONFIG_UCLAMP_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UCLAMP_TASK_GROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UCS2_STRING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_UCSI_ACPI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_UCSI_CCG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UCSI_HUAWEI_GAOKUN policy<{'arm64': 'm'}> +CONFIG_UCSI_LENOVO_YOGA_C630 policy<{'arm64-generic': 'm'}> +CONFIG_UCSI_PMIC_GLINK policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UCSI_STM32G0 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UDF_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_UDMABUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UEFI_CPER policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_UEFI_CPER_ARM policy<{'arm64': 'y'}> +CONFIG_UEFI_CPER_X86 policy<{'amd64': 'y'}> +CONFIG_UEVENT_HELPER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UEVENT_HELPER_PATH policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_UFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UFS_FS_WRITE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_UHID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_UID16 policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 's390x': '-'}> +CONFIG_UIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_UIO_AEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_CIF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_DFL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UIO_DMEM_GENIRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_FSL_ELBC_GPCM policy<{'ppc64el': 'm'}> +CONFIG_UIO_FSL_ELBC_GPCM_NETX5152 policy<{'ppc64el': 'n'}> +CONFIG_UIO_HV_GENERIC policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_UIO_MF624 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_NETX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_PCI_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_PCI_GENERIC_SVA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_UIO_PDRV_GENIRQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_UIO_SERCOS3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ULI526X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_ULTRIX_PARTITION policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_UNACCEPTED_MEMORY policy<{'amd64': 'y'}> +CONFIG_UNCOMPRESS_INCLUDE policy<{'armhf': '"debug/uncompress.h"'}> +CONFIG_UNICODE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNINLINE_SPIN_UNLOCK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_UNION_FIND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNIWILL_LAPTOP policy<{'amd64': 'm'}> +CONFIG_UNIX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNIX98_PTYS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UNIXWARE_DISKLABEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_UNIX_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_UNMAP_KERNEL_AT_EL0 policy<{'arm64': 'y'}> +CONFIG_UNWINDER_ARM policy<{'armhf': 'n'}> +CONFIG_UNWINDER_ORC policy<{'amd64': 'n'}> +CONFIG_UNWIND_USER policy<{'amd64': 'y'}> +CONFIG_UPROBES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UPROBE_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_US5182D policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_USB4_DEBUGFS_WRITE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB4_DMA_TEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB4_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBIP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USBIP_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USBIP_HOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBIP_VHCI_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBIP_VHCI_HC_PORTS policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8'}> +CONFIG_USBIP_VHCI_NR_HCS policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_USBIP_VUDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USBPCWATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ACM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ADUTUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_AIRSPY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ALI_M5632 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_AMD5536UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_AN2720 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ANNOUNCE_NEW_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_APPLEDISPLAY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ARCH_HAS_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ARMLINUX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ASPEED_UDC policy<{'armhf': 'm'}> +CONFIG_USB_ASPEED_VHUB policy<{'armhf': 'm'}> +CONFIG_USB_ATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_AUTOSUSPEND_DELAY policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_USB_BDC_UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_BELKIN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_C67X00_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CATC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDC_COMPOSITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDC_PHONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS2_UDC policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS3_GADGET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNS3_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNS3_IMX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_CDNS3_PCI_WRAP policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS3_TI policy<{'arm64': 'm'}> +CONFIG_USB_CDNSP_GADGET policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNSP_HOST policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNSP_PCI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_CDNS_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CDNS_SUPPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CHAOSKEY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CHIPIDEA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CHIPIDEA_GENERIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CHIPIDEA_IMX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_MSM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_NPCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_TEGRA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CHIPIDEA_UDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CONFIGFS_ACM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_ECM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_ECM_SUBSET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_EEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_FS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_HID policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_LB_SS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_MIDI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_MIDI2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_PRINTER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_TCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC1 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UAC2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_F_UVC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_MASS_STORAGE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_NCM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_OBEX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_PHONET policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_RNDIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONFIGFS_SERIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_CONN_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CXACRU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_CYPRESS_CY7C63 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_CYTHERM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE policy<{'amd64': '1', 'arm64': '1', 'armhf': '1', 'ppc64el': '1', 'riscv64': '1'}> +CONFIG_USB_DEFAULT_PERSIST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DSBR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DUMMY_HCD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_DWC2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC2_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_DWC2_DUAL_ROLE policy<{'armhf': 'n'}> +CONFIG_USB_DWC2_HOST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC2_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_DWC2_PERIPHERAL policy<{'armhf': 'n'}> +CONFIG_USB_DWC2_TRACK_MISSED_SOFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_DWC3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_DWC3_AM62 policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_APPLE policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_DUAL_ROLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC3_EXYNOS policy<{'armhf': 'n'}> +CONFIG_USB_DWC3_GADGET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_DWC3_GENERIC_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_GOOGLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_HAPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_HOST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_DWC3_IMX8MP policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_KEYSTONE policy<{'arm64': 'm'}> +CONFIG_USB_DWC3_MESON_G12A policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_DWC3_OF_SIMPLE policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_OMAP policy<{'armhf': 'm'}> +CONFIG_USB_DWC3_PCI policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_DWC3_QCOM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_DWC3_RTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_DWC3_ULPI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_DWC3_XILINX policy<{'arm64': 'm'}> +CONFIG_USB_DYNAMIC_MINORS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EG20T policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_EHCI_EXYNOS policy<{'armhf': 'n'}> +CONFIG_USB_EHCI_FSL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EHCI_HCD_NPCM7XX policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_EHCI_HCD_OMAP policy<{'armhf': 'm'}> +CONFIG_USB_EHCI_HCD_ORION policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_EHCI_HCD_PPC_OF policy<{'ppc64el': 'y'}> +CONFIG_USB_EHCI_MV policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_EHCI_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHCI_ROOT_HUB_TT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_EHCI_TT_NEWSCHED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EHSET_TEST_FIXTURE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EMI26 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EMI62 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_EPSON2888 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ETH_EEM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ETH_RNDIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_EZUSB_FX2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_FEW_INIT_RETRIES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_FHCI_HCD policy<{'ppc64el': 'm'}> +CONFIG_USB_FUNCTIONFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_FUNCTIONFS_ETH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_FUNCTIONFS_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_FUNCTIONFS_RNDIS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_F_ACM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_ECM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_EEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_MASS_STORAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_MIDI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_MIDI2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_OBEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_PHONET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_RNDIS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_SS_LB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_SUBSET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_TCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UAC1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UAC1_LEGACY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UAC2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_F_UVC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GADGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'y', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_GADGETFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GADGET_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_GADGET_DEBUG_FILES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_GADGET_DEBUG_FS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_USB_GADGET_TARGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GADGET_VBUS_DRAW policy<{'amd64': '2', 'arm64': '2', 'armhf': '2', 'ppc64el': '2', 'riscv64': '2'}> +CONFIG_USB_GADGET_XILINX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GL860 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GOKU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GPIO_VBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_GR_UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_BENQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_CONEX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_CPIA1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_DTCS033 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_ETOMS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_FINEPIX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_JEILINJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_JL2005BCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_KINECT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_KONICA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_MARS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_MR97310A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_NW80X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_OV519 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_OV534 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_OV534_9 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_PAC207 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_PAC7302 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_PAC7311 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SE401 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SN9C2028 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SN9C20X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SONIXB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SONIXJ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA1528 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA501 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA505 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA506 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA508 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SPCA561 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SQ905 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SQ905C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SQ930X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_STK014 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_STK1135 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_STV0680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_SUNPLUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_T613 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_TOPRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_TOUPTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_TV8532 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_VC032X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_VICAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_XIRLINK_CIT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_GSPCA_ZC3XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_ACM_MS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_DBGP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_DBGP_PRINTK policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_G_DBGP_SERIAL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_G_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_MULTI policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_G_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_NOKIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_G_WEBCAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HACKRF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HCD_TEST_MODE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_HID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HIDDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_HSIC_USB3503 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HSIC_USB4604 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_HSO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_HUB_USB251XB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_IDMOUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_IOWARRIOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_IPHETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ISIGHTFW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP116X_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP1301 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP1760 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ISP1760_DUAL_ROLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ISP1760_GADGET_ROLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_ISP1760_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_ISP1760_HOST_ROLE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_ISP1761_UDC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_KAWETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_KBD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_KC2190 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_KEENE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_LAN78XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_LCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LEDS_TRIGGER_USBPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LED_TRIG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_LEGOTOWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LGM_PHY policy<{'amd64': 'm'}> +CONFIG_USB_LIBCOMPOSITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_LINK_LAYER_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_LJCA policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_USB_M5602 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MA901 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MASS_STORAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MAX3420_UDC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MAX3421_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MDC800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MICROTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MIDI_GADGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MOUSE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_MR800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MSI2500 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_MTU3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_MTU3_DEBUG policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_USB_MTU3_DUAL_ROLE policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_MTU3_GADGET policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_USB_MTU3_HOST policy<{'arm64': 'n', 'armhf': 'n'}> +CONFIG_USB_MUSB_DSPS policy<{'armhf': 'm'}> +CONFIG_USB_MUSB_DUAL_ROLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_MUSB_GADGET policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_MUSB_HOST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_MUSB_MEDIATEK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_MUSB_OMAP2PLUS policy<{'armhf': 'm'}> +CONFIG_USB_MUSB_SUNXI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_USB_MUSB_TUSB6010 policy<{'armhf': 'm'}> +CONFIG_USB_MXS_PHY policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_NET2280 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_AQC111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_AX88179_178A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_AX8817X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDCETHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_EEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_MBIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_SUBSET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CDC_SUBSET_ENABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CH9200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_CX82310_ETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_DM9601 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_DRIVERS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_NET_GL620A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_HUAWEI_CDC_NCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_INT51X1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_KALMIA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_MCS7830 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_NET1080 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_PLUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_QMI_WWAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_RNDIS_HOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SMSC75XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SMSC95XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SR9700 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_SR9800 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_NET_ZAURUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_OHCI_EXYNOS policy<{'armhf': 'n'}> +CONFIG_USB_OHCI_HCD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_OHCI_HCD_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_OHCI_HCD_PLATFORM policy<{'amd64': 'y', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_OHCI_HCD_PPC_OF_BE policy<{'ppc64el': 'n'}> +CONFIG_USB_OHCI_HCD_PPC_OF_LE policy<{'ppc64el': 'n'}> +CONFIG_USB_OHCI_LITTLE_ENDIAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USB_ONBOARD_DEV policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ONBOARD_DEV_USB5744 policy<{'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_OTG_FSM policy<{'riscv64': 'm'}> +CONFIG_USB_OTG_PRODUCTLIST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_OXU210HP_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PCI_AMD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PEGASUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_PHY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PRINTER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_PULSE8_CEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_PWC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_PWC_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_PWC_INPUT_EVDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_PXA27X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_QCOM_EUD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_R8A66597 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_R8A66597_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_RAINSHADOW_CEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_RAREMONO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RAW_GADGET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RENESAS_USB3 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBHS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBHS_HCD policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_RENESAS_USBHS_UDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_ROLES_INTEL_XHCI policy<{'amd64': 'm'}> +CONFIG_USB_ROLE_SWITCH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_RTL8150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RTL8152 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RTL8153_ECM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_RZV2M_USB3DRD policy<{'arm64': 'm'}> +CONFIG_USB_S2255 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SERIAL_AIRCABLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_ARK3116 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_BELKIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CH341 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CP210X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CYBERJACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_CYPRESS_M8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_DIGI_ACCELEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_EDGEPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_EDGEPORT_TI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_EMPEG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_F81232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_F8153X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_FTDI_SIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_GARMIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_GENERIC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_SERIAL_IPAQ policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_IPW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_IR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_IUU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KEYSPAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KEYSPAN_PDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KLSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_KOBIL_SCT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MCT_U232 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_METRO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MOS7715_PARPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_SERIAL_MOS7720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MOS7840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_MXUPORT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_NAVMAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OMNINET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OPTICON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OPTION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_OTI6858 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_PL2303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_QCAUX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_QT2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_QUALCOMM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SAFE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SAFE_PADDED policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_SERIAL_SIERRAWIRELESS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SIMPLE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SPCP8X5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SSU100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_SYMBOL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_TI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_UPD78F0730 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_VISOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_WHITEHEAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_WISHBONE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_WWAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_XR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SERIAL_XSENS_MT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SEVSEG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SI470X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SI4713 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SIERRA_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SISUSBVGA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SL811_CS policy<{'amd64': 'm'}> +CONFIG_USB_SL811_HCD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_SL811_HCD_ISO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_SNP_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SNP_UDC_PLAT policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SPEEDTOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_STORAGE_ALAUDA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_CYPRESS_ATACB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_DATAFAB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_STORAGE_ENE_UB6250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_FREECOM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_ISD200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_JUMPSHOT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_KARMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_ONETOUCH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_REALTEK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_SDDR09 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_SDDR55 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STORAGE_USBAT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_STV06XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_USB_TEGRA_PHY policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_TEGRA_XUDC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_TMC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_TRANCEVIBRATOR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_UAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_UEAGLEATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_UHCI_ASPEED policy<{'armhf': 'y'}> +CONFIG_USB_UHCI_PLATFORM policy<{'armhf': 'y'}> +CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC policy<{'armhf': 'y'}> +CONFIG_USB_ULPI policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_ULPI_BUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ULPI_VIEWPORT policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_USB_USBIO policy<{'amd64': 'm', 'arm64': '-', 'riscv64': '-'}> +CONFIG_USB_USBNET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_USS720 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_U_AUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_U_ETHER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_U_SERIAL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_VIDEO_CLASS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_VL600 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_WDM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_XEN_HCD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_USB_XHCI_HISTB policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_MTK policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_MVEBU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_PCI_RENESAS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'n', 's390x': '-'}> +CONFIG_USB_XHCI_PLATFORM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_XHCI_RCAR policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XHCI_RZV2M policy<{'arm64': 'y'}> +CONFIG_USB_XHCI_SIDEBAND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USB_XHCI_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_USB_XUSBATM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_YUREX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USB_ZERO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_USB_ZERO_HNPTEST policy<{'riscv64': 'n'}> +CONFIG_USERFAULTFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USERIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_USER_DECRYPTED_DATA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USER_EVENTS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USER_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USER_RETURN_NOTIFIER policy<{'amd64': 'y'}> +CONFIG_USER_STACKTRACE_SUPPORT policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_USE_OF policy<{'armhf': 'y'}> +CONFIG_USE_PERCPU_NUMA_NODE_ID policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_USE_X86_SEG_SUPPORT policy<{'amd64': 'y'}> +CONFIG_UTS_NS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_UVC_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_UV_MMTIMER policy<{'amd64': 'm'}> +CONFIG_UV_SYSFS policy<{'amd64': 'm'}> +CONFIG_U_SERIAL_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_V4L2_ASYNC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_CCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_CCI_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_FLASH_LED_CLASS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_FWNODE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_H264 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_V4L2_ISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_V4L2_JPEG_HELPER policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_V4L2_MEM2MEM_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_V4L2_VP9 policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_V4L_MEM2MEM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_V4L_PLATFORM_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_V4L_TEST_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VALIDATE_FS_PARSER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VBOXGUEST policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VBOXSF_FS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VCAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VCNL3020 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VCNL4000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VCNL4035 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VCPU_STALL_DETECTOR policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VDPA_SIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA_SIM_BLOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA_SIM_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDPA_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VDSO policy<{'armhf': 'y'}> +CONFIG_VDSO_GETRANDOM policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VEML3235 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6030 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6040 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6046X00 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6070 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VEML6075 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VERSION_SIGNATURE policy<{'amd64': '""', 'arm64': '""', 'armhf': '""', 'ppc64el': '""', 'riscv64': '""', 's390x': '""'}> +CONFIG_VETH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VEXPRESS_CONFIG policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VF610_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VF610_DAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VFIO_AMBA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_AP policy<{'s390x': 'm'}> +CONFIG_VFIO_CCW policy<{'s390x': 'm'}> +CONFIG_VFIO_CDX policy<{'arm64': 'm'}> +CONFIG_VFIO_CONTAINER policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_VFIO_DEVICE_CDEV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y'}> +CONFIG_VFIO_FSL_MC policy<{'arm64': 'm'}> +CONFIG_VFIO_GROUP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_IOMMU_SPAPR_TCE policy<{'ppc64el': 'm'}> +CONFIG_VFIO_IOMMU_TYPE1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 's390x': 'm'}> +CONFIG_VFIO_MDEV policy<{'amd64': 'm', 'arm64': '-', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-', 's390x': 'm'}> +CONFIG_VFIO_NOIOMMU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_PCI_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VFIO_PCI_DMABUF policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFIO_PCI_IGD policy<{'amd64': 'y'}> +CONFIG_VFIO_PCI_INTX policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VFIO_PCI_VGA policy<{'amd64': 'y'}> +CONFIG_VFIO_PLATFORM policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_PLATFORM_AMDXGBE_RESET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_PLATFORM_BASE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VFIO_VIRQFD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VFP policy<{'armhf': 'y'}> +CONFIG_VFPv3 policy<{'armhf': 'y'}> +CONFIG_VF_USE_ARM_GLOBAL_TIMER policy<{'armhf': 'y'}> +CONFIG_VF_USE_PIT_TIMER policy<{'armhf': 'n'}> +CONFIG_VGASTATE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VGA_ARB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VGA_ARB_MAX_GPUS policy<{'amd64': '16', 'arm64': '16', 'armhf': '16', 'ppc64el': '16', 'riscv64': '16'}> +CONFIG_VGA_CONSOLE policy<{'amd64': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VGA_SWITCHEROO policy<{'amd64': 'y'}> +CONFIG_VHOST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_CROSS_ENDIAN_LEGACY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VHOST_IOTLB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VHOST_NET policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_RING policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VHOST_SCSI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VHOST_TASK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VHOST_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VHOST_VSOCK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIA_RHINE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VIA_RHINE_MMIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIA_VELOCITY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VIA_WDT policy<{'amd64': 'm'}> +CONFIG_VIDEO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIDEOBUF2_CORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_DMA_CONTIG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_DMA_SG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_MEMOPS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_V4L2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOBUF2_VMALLOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEOMODE_HELPERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_AD5820 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADP1653 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7170 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7175 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7180 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7183 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7343 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7393 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV748X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7511 policy<{'amd64': 'm'}> +CONFIG_VIDEO_ADV7511_CEC policy<{'amd64': 'n'}> +CONFIG_VIDEO_ADV7604 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7604_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_ADV7842 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ADV7842_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_ADV_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_AK7375 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AK881X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ALLEGRO_DVT policy<{'arm64': 'm'}> +CONFIG_VIDEO_ALVIUM_CSI2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AMD_ISP4_CAPTURE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'n'}> +CONFIG_VIDEO_AMPHION_VPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_APTINA_PLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AR0521 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ASPEED policy<{'amd64': '-', 'arm64': '-', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_AU0828 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_AU0828_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_AU0828_V4L2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_BT819 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_BT848 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_BT856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_BT866 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_C3_ISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_C3_MIPI_ADAPTER policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_C3_MIPI_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_CADENCE_CSI2RX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CADENCE_CSI2TX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CAFE_CCIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CAMERA_LENS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CAMERA_SENSOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CCS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CCS_PLL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_COBALT policy<{'amd64': 'm'}> +CONFIG_VIDEO_CODA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_CS3308 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CS5345 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CS53L32A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX18 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX18_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX231XX_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CX2341X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX23885 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX25821 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX25821_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX25840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_BLACKBIRD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_ENABLE_VP3054 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_CX88_MPEG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_CX88_VP3054 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DS90UB913 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DS90UB953 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DS90UB960 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DT3155 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW100 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_DW9714 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW9719 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW9768 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW9807_VCM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_DW_MIPI_CSI2RX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_E5010_JPEG_ENC policy<{'amd64': '-', 'arm64': 'm', 'armhf': '-', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_EM28XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_RC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_EM28XX_V4L2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ET8EK8 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_FB_IVTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_FB_IVTV_FORCE_PAT policy<{'amd64': 'y'}> +CONFIG_VIDEO_FIXED_MINOR_RANGES policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_GC0308 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC0310 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC05A2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC08A3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GC2145 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007_LOADER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007_USB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GO7007_USB_S2250_BOARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_GS1662 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HANTRO policy<{'arm64': 'm', 'armhf': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_HANTRO_HEVC_RFC policy<{'arm64': 'y', 'armhf': 'y', 'riscv64': '-'}> +CONFIG_VIDEO_HANTRO_IMX8M policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_HANTRO_ROCKCHIP policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_HANTRO_STM32MP25 policy<{'arm64': 'y'}> +CONFIG_VIDEO_HANTRO_SUNXI policy<{'arm64': 'y', 'riscv64': '-'}> +CONFIG_VIDEO_HDPVR policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HEXIUM_GEMINI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HEXIUM_ORION policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HI556 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HI846 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_HI847 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX208 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX214 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX219 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX258 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX274 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX283 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX290 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX296 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX319 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX334 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX335 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX355 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX412 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX415 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IMX7_CSI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX8_ISI policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX8_ISI_M2M policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_IMX8_JPEG policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_MEDIA policy<{'arm64': '-', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_MIPI_CSIS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_PXP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_IMX_VDOA policy<{'armhf': 'm'}> +CONFIG_VIDEO_INTEL_IPU6 policy<{'amd64': 'm'}> +CONFIG_VIDEO_INTEL_IPU7 policy<{'amd64': 'm'}> +CONFIG_VIDEO_IPU3_CIO2 policy<{'amd64': 'm'}> +CONFIG_VIDEO_IPU3_IMGU policy<{'amd64': 'm'}> +CONFIG_VIDEO_IR_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ISL7998X policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IVTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_IVTV_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_KS0127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_LM3560 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_LM3646 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_LT6911UXE policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_M52790 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MALI_C55 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MAX9271_LIB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX9286 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX96712 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX96714 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MAX96717 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MEDIATEK_JPEG policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_MDP policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_MDP3 policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_VCODEC policy<{'arm64': 'm'}> +CONFIG_VIDEO_MEDIATEK_VCODEC_SCP policy<{'arm64': 'y'}> +CONFIG_VIDEO_MEDIATEK_VCODEC_VPU policy<{'arm64': 'y'}> +CONFIG_VIDEO_MEDIATEK_VPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MEM2MEM_DEINTERLACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MESON_GE2D policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MESON_VDEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MGB4 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ML86V7667 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MMP_CAMERA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_MSP3400 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9M001 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9M111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9M114 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9P031 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9T112 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9V011 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9V032 policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MT9V111 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MUX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_MXB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_NPCM_VCD_ECE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_OG01A1B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OG0VE1B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OS05B10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV01A10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV02A10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV02C10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV02E10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV08D10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV08X40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV13858 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV13B10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2659 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2680 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2685 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2735 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV2740 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV4689 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5640 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5645 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5647 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5648 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5670 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5675 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5693 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV5695 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV6211 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV64A40 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7251 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7670 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV772X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV7740 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV8856 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV8858 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV8865 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9282 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9640 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9650 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_OV9734 policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_PCI_SKELETON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_PVRUSB2 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_PVRUSB2_DEBUGIFC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_VIDEO_PVRUSB2_DVB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_PVRUSB2_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_QCOM_CAMSS policy<{'arm64': 'm'}> +CONFIG_VIDEO_QCOM_IRIS policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_QCOM_VENUS policy<{'arm64': 'm'}> +CONFIG_VIDEO_RCAR_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RCAR_DRIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RCAR_ISP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RCAR_VIN policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RDACM20 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_RDACM21 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_RENESAS_CEU policy<{'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_FCP policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_FDP1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_JPU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RENESAS_VSP1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RJ54N1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ROCKCHIP_CIF policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_ROCKCHIP_ISP1 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_ROCKCHIP_RGA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_ROCKCHIP_VDEC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RP1_CFE policy<{'amd64': 'n', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_VIDEO_RZG2L_CRU policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RZG2L_CSI2 policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_RZV2H_IVC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_S5C73M3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5K3M5 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5K5BAF policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5K6A3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_S5KJN1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA6588 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA6752HS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7110 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA711X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7127 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_ALSA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_DVB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_GO7007 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7134_RC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_SAA7146 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7146_VV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7164 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA717X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAA7185 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_S5P_G2D policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_S5P_JPEG policy<{'armhf': 'n'}> +CONFIG_VIDEO_SAMSUNG_S5P_MFC policy<{'armhf': 'n'}> +CONFIG_VIDEO_SOLO6X10 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'n', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SONY_BTF_MPX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_STK1160 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_STM32_CSI policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DCMI policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DCMIPP policy<{'arm64': 'm'}> +CONFIG_VIDEO_STM32_DMA2D policy<{'arm64': 'm'}> +CONFIG_VIDEO_ST_MIPID02 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_SUN4I_CSI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUN6I_CSI policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUN6I_ISP policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_SUN6I_MIPI_CSI2 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 policy<{'arm64': 'm', 'riscv64': '-'}> +CONFIG_VIDEO_SUN8I_DEINTERLACE policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUN8I_ROTATE policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUNXI policy<{'arm64': 'y', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SUNXI_CEDRUS policy<{'arm64': 'm', 'armhf': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SYNOPSYS_HDMIRX policy<{'amd64': '-', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID policy<{'amd64': '-', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-', 'riscv64': '-'}> +CONFIG_VIDEO_TC358743 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TC358743_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_TC358746 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TDA1997X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TDA7432 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TDA9840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TEA6415C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TEA6420 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TEGRA policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_TEGRA_TPG policy<{'arm64': 'y', 'armhf': '-'}> +CONFIG_VIDEO_TEGRA_VDE policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_THP7312 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_THS7303 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_THS8200 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TI_CAL policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_VIDEO_TI_CAL_MC policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIDEO_TI_CSC policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_J721E_CSI2RX policy<{'arm64': 'm'}> +CONFIG_VIDEO_TI_SC policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VIP policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VPDMA policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VPE policy<{'armhf': 'm'}> +CONFIG_VIDEO_TI_VPE_DEBUG policy<{'armhf': 'n'}> +CONFIG_VIDEO_TLV320AIC23B policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TUNER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVAUDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVEEPROM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVP514X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVP5150 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TVP7002 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW2804 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW5864 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW68 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW686X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9900 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9903 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9906 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_TW9910 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_UDA1342 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_UPD64031A policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_UPD64083 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_USBTV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_V4L2_I2C policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_V4L2_SUBDEV_API policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_V4L2_TPG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VD55G1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VD56G3 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VGXY61 policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIA_CAMERA policy<{'amd64': 'm'}> +CONFIG_VIDEO_VICODEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIM2M policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VISL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIVID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VIVID_CEC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_VIVID_MAX_DEVS policy<{'amd64': '64', 'arm64': '64', 'armhf': '64', 'ppc64el': '64', 'riscv64': '64'}> +CONFIG_VIDEO_VIVID_OSD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIDEO_VP27SMPX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_VPX3220 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_WAVE_VPU policy<{'arm64': 'm'}> +CONFIG_VIDEO_WM8739 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_WM8775 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX_CSI2RXSS policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX_TPG policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_XILINX_VTC policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIDEO_ZORAN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_VIPERBOARD_ADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIRTIO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_ANCHOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_BALLOON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_VIRTIO_DMA_SHARED_BUFFER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_INPUT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_IOMMU policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_VIRTIO_MEM policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_MENU policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIRTIO_PCI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PCI_ADMIN_LEGACY policy<{'amd64': 'y'}> +CONFIG_VIRTIO_PCI_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PCI_LIB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PCI_LIB_LEGACY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_PMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VIRTIO_RTC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_RTC_ARM policy<{'arm64': 'y', 'armhf': 'y'}> +CONFIG_VIRTIO_RTC_CLASS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIRTIO_RTC_PTP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRTIO_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIRTIO_VFIO_PCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VIRTIO_VFIO_PCI_ADMIN_LEGACY policy<{'amd64': 'y'}> +CONFIG_VIRTIO_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTIO_VSOCKETS_COMMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VIRTUALIZATION policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING_GEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VIRT_CPU_ACCOUNTING_NATIVE policy<{'ppc64el': 'n', 's390x': 'y'}> +CONFIG_VIRT_DRIVERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VIRT_WIFI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VIRT_XFER_TO_GUEST_WORK policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VISCONTI_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_VISL_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_VITESSE_PHY policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VL53L0X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VL6180 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VLAN_8021Q policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VLAN_8021Q_GVRP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VLAN_8021Q_MVRP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMAP_PFN policy<{'amd64': 'y', 'arm64': 'y', 'arm64-generic-64k': '-', 'armhf': 'y', 'ppc64el': '-', 'riscv64': 'y', 's390x': '-'}> +CONFIG_VMAP_STACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMCORE_INFO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMCP policy<{'s390x': 'y'}> +CONFIG_VMCP_CMA_SIZE policy<{'s390x': '4'}> +CONFIG_VMD policy<{'amd64': 'm'}> +CONFIG_VME_BUS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_VME_FAKE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VME_TSI148 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VME_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_VMGENID policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VMLINUX_MAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VMLOGRDR policy<{'s390x': 'm'}> +CONFIG_VMSPLIT_1G policy<{'armhf': 'n'}> +CONFIG_VMSPLIT_2G policy<{'armhf': 'n'}> +CONFIG_VMSPLIT_3G policy<{'armhf': 'y'}> +CONFIG_VMWARE_BALLOON policy<{'amd64': 'm'}> +CONFIG_VMWARE_PVSCSI policy<{'amd64': 'm'}> +CONFIG_VMWARE_VMCI policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VMWARE_VMCI_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_VMXNET3 policy<{'amd64': 'm', 'arm64': 'm', 'arm64-generic-64k': '-', 'armhf': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VM_EVENT_COUNTERS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VORTEX policy<{'amd64': 'm', 'arm64': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VPA_PMU policy<{'ppc64el': 'm'}> +CONFIG_VP_VDPA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_VSOCKETS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSOCKETS_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSOCKETS_LOOPBACK policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSOCKMON policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VSX policy<{'ppc64el': 'y'}> +CONFIG_VT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VT_CONSOLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VT_CONSOLE_SLEEP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_VT_HW_CONSOLE_BINDING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_VXFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_VXLAN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_VZ89X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_W1 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_W1_CON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': '-'}> +CONFIG_W1_MASTER_AMD_AXI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_W1_MASTER_DS2482 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_DS2490 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_GPIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_MATROX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_MXC policy<{'arm64': 'm', 'armhf': 'm'}> +CONFIG_W1_MASTER_SGI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_MASTER_UART policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_W1_SLAVE_DS2405 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2406 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2408 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2408_READBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_W1_SLAVE_DS2413 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2423 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2430 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2431 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2433 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2433_CRC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2438 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS250X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2780 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2781 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS2805 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS28E04 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_DS28E17 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_SMEM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W1_SLAVE_THERM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_W83627HF_WDT policy<{'amd64': 'm'}> +CONFIG_W83877F_WDT policy<{'amd64': 'm'}> +CONFIG_W83977F_WDT policy<{'amd64': 'm'}> +CONFIG_WAFER_WDT policy<{'amd64': 'm'}> +CONFIG_WAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_WANT_COMPAT_NETLINK_MESSAGES policy<{'amd64': 'y'}> +CONFIG_WANT_DEV_COREDUMP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WANXL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WATCHDOG policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WATCHDOG_NOWAYOUT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WATCHDOG_OPEN_TIMEOUT policy<{'amd64': '0', 'arm64': '0', 'armhf': '0', 'ppc64el': '0', 'riscv64': '0', 's390x': '0'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_WATCHDOG_RTAS policy<{'ppc64el': 'm'}> +CONFIG_WATCHDOG_SYSFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WATCH_QUEUE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WCN36XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WCN36XX_DEBUGFS policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_WDAT_WDT policy<{'amd64': 'm', 'arm64': 'm', 'riscv64': 'm'}> +CONFIG_WDTPCI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WERROR policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WEXT_CORE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WEXT_PRIV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WEXT_PROC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WFX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WIL6210 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WIL6210_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIL6210_ISR_COR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIL6210_TRACING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WILC1000 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WILC1000_HW_OOB_INTR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WILC1000_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WILC1000_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WILCO_EC policy<{'amd64': 'm'}> +CONFIG_WILCO_EC_DEBUGFS policy<{'amd64': 'm'}> +CONFIG_WILCO_EC_EVENTS policy<{'amd64': 'm'}> +CONFIG_WILCO_EC_TELEMETRY policy<{'amd64': 'm'}> +CONFIG_WINBOND_840 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WINDFARM policy<{'ppc64el': 'm'}> +CONFIG_WINMATE_FM07_KEYS policy<{'amd64': 'm'}> +CONFIG_WIREGUARD policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_WIREGUARD_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WIRELESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIRELESS_EXT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIRELESS_HOTKEY policy<{'amd64': 'm'}> +CONFIG_WIZNET_BUS_ANY policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WIZNET_BUS_DIRECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_WIZNET_BUS_INDIRECT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': '-'}> +CONFIG_WIZNET_W5100 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WIZNET_W5100_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WIZNET_W5300 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WL1251 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL1251_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL1251_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL12XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WL18XX policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WLAN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ADMTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ATH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ATMEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_BROADCOM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_INTEL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_INTERSIL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_MARVELL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_MEDIATEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_MICROCHIP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_PURELIFI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_QUANTENNA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_RALINK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_REALTEK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_RSI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_SILABS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ST policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLAN_VENDOR_ZYDAS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WLCORE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WLCORE_SDIO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WLCORE_SPI policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_WM831X_BACKUP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM831X_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM831X_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM8350_POWER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WM8350_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WMI_BMOF policy<{'amd64': 'm'}> +CONFIG_WPCM450_SOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_WQ_CPU_INTENSIVE_REPORT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_WQ_POWER_EFFICIENT_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WQ_WATCHDOG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_WWAN_DEBUGFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_WWAN_HWSIM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_WW_MUTEX_SELFTEST policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_X25 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_X86 policy<{'amd64': 'y'}> +CONFIG_X86_16BIT policy<{'amd64': 'y'}> +CONFIG_X86_64 policy<{'amd64': 'y'}> +CONFIG_X86_64_ACPI_NUMA policy<{'amd64': 'y'}> +CONFIG_X86_ACPI_CPUFREQ_CPB policy<{'amd64': 'y'}> +CONFIG_X86_AMD_FREQ_SENSITIVITY policy<{'amd64': 'm'}> +CONFIG_X86_AMD_PLATFORM_DEVICE policy<{'amd64': 'y'}> +CONFIG_X86_AMD_PSTATE policy<{'amd64': 'y'}> +CONFIG_X86_AMD_PSTATE_DEFAULT_MODE policy<{'amd64': '3'}> +CONFIG_X86_AMD_PSTATE_UT policy<{'amd64': 'n'}> +CONFIG_X86_ANDROID_TABLETS policy<{'amd64': 'm'}> +CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK policy<{'amd64': 'y'}> +CONFIG_X86_BUS_LOCK_DETECT policy<{'amd64': 'y'}> +CONFIG_X86_CET policy<{'amd64': 'y'}> +CONFIG_X86_CHECK_BIOS_CORRUPTION policy<{'amd64': 'y'}> +CONFIG_X86_CMOV policy<{'amd64': 'y'}> +CONFIG_X86_CPA_STATISTICS policy<{'amd64': 'n'}> +CONFIG_X86_CPUID policy<{'amd64': 'm'}> +CONFIG_X86_CPU_RESCTRL policy<{'amd64': 'y'}> +CONFIG_X86_CX8 policy<{'amd64': 'y'}> +CONFIG_X86_DEBUGCTLMSR policy<{'amd64': 'y'}> +CONFIG_X86_DEBUG_FPU policy<{'amd64': 'y'}> +CONFIG_X86_DECODER_SELFTEST policy<{'amd64': 'n'}> +CONFIG_X86_DIRECT_GBPAGES policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_CENTAUR_MCR policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_CYRIX_ARR policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_IBT policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_K6_MTRR policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_LAM policy<{'amd64': 'y'}> +CONFIG_X86_DISABLED_FEATURE_VME policy<{'amd64': 'y'}> +CONFIG_X86_ESPFIX64 policy<{'amd64': 'y'}> +CONFIG_X86_EXTENDED_PLATFORM policy<{'amd64': 'y'}> +CONFIG_X86_FRED policy<{'amd64': 'y'}> +CONFIG_X86_GOLDFISH policy<{'amd64': 'n'}> +CONFIG_X86_HAVE_PAE policy<{'amd64': 'y'}> +CONFIG_X86_HV_CALLBACK_VECTOR policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_LPSS policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_MID policy<{'amd64': 'n'}> +CONFIG_X86_INTEL_PSTATE policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_TSX_MODE_AUTO policy<{'amd64': 'n'}> +CONFIG_X86_INTEL_TSX_MODE_OFF policy<{'amd64': 'y'}> +CONFIG_X86_INTEL_TSX_MODE_ON policy<{'amd64': 'n'}> +CONFIG_X86_INTERNODE_CACHE_SHIFT policy<{'amd64': '6'}> +CONFIG_X86_IOPL_IOPERM policy<{'amd64': 'y'}> +CONFIG_X86_IO_APIC policy<{'amd64': 'y'}> +CONFIG_X86_L1_CACHE_SHIFT policy<{'amd64': '6'}> +CONFIG_X86_LOCAL_APIC policy<{'amd64': 'y'}> +CONFIG_X86_MCE policy<{'amd64': 'y'}> +CONFIG_X86_MCELOG_LEGACY policy<{'amd64': 'y'}> +CONFIG_X86_MCE_AMD policy<{'amd64': 'y'}> +CONFIG_X86_MCE_INJECT policy<{'amd64': 'm'}> +CONFIG_X86_MCE_INTEL policy<{'amd64': 'y'}> +CONFIG_X86_MCE_THRESHOLD policy<{'amd64': 'y'}> +CONFIG_X86_MEM_ENCRYPT policy<{'amd64': 'y'}> +CONFIG_X86_MINIMUM_CPU_FAMILY policy<{'amd64': '64'}> +CONFIG_X86_MPPARSE policy<{'amd64': 'y'}> +CONFIG_X86_MSR policy<{'amd64': 'm'}> +CONFIG_X86_NATIVE_CPU policy<{'amd64': 'n'}> +CONFIG_X86_NEED_RELOCS policy<{'amd64': 'y'}> +CONFIG_X86_NUMACHIP policy<{'amd64': 'y'}> +CONFIG_X86_P4_CLOCKMOD policy<{'amd64': 'm'}> +CONFIG_X86_PAT policy<{'amd64': 'y'}> +CONFIG_X86_PKG_TEMP_THERMAL policy<{'amd64': 'm'}> +CONFIG_X86_PLATFORM_DEVICES policy<{'amd64': 'y'}> +CONFIG_X86_PLATFORM_DRIVERS_DELL policy<{'amd64': 'y'}> +CONFIG_X86_PLATFORM_DRIVERS_HP policy<{'amd64': 'y'}> +CONFIG_X86_PLATFORM_DRIVERS_UNIWILL policy<{'amd64': 'y'}> +CONFIG_X86_PMEM_LEGACY policy<{'amd64': 'y'}> +CONFIG_X86_PMEM_LEGACY_DEVICE policy<{'amd64': 'y'}> +CONFIG_X86_PM_TIMER policy<{'amd64': 'y'}> +CONFIG_X86_POSTED_MSI policy<{'amd64': 'n'}> +CONFIG_X86_REQUIRED_FEATURE_ALWAYS policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_CMOV policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_CPUID policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_CX8 policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_FPU policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_FXSR policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_LM policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_MSR policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_NOPL policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_PAE policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_XMM policy<{'amd64': 'y'}> +CONFIG_X86_REQUIRED_FEATURE_XMM2 policy<{'amd64': 'y'}> +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS policy<{'amd64': 'y'}> +CONFIG_X86_SGX policy<{'amd64': 'y'}> +CONFIG_X86_SGX_KVM policy<{'amd64': 'y'}> +CONFIG_X86_SPEEDSTEP_LIB policy<{'amd64': 'm'}> +CONFIG_X86_SUPPORTS_MEMORY_FAILURE policy<{'amd64': 'y'}> +CONFIG_X86_THERMAL_VECTOR policy<{'amd64': 'y'}> +CONFIG_X86_TSC policy<{'amd64': 'y'}> +CONFIG_X86_UMIP policy<{'amd64': 'y'}> +CONFIG_X86_USER_SHADOW_STACK policy<{'amd64': 'y'}> +CONFIG_X86_VERBOSE_BOOTUP policy<{'amd64': 'n'}> +CONFIG_X86_VMX_FEATURE_NAMES policy<{'amd64': 'y'}> +CONFIG_X86_VSMP policy<{'amd64': 'n'}> +CONFIG_X86_VSYSCALL_EMULATION policy<{'amd64': 'y'}> +CONFIG_X86_X2APIC policy<{'amd64': 'y'}> +CONFIG_X9250 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XARRAY_MULTI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XDP_SOCKETS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XDP_SOCKETS_DIAG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XEN policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'n'}> +CONFIG_XENFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_ACPI policy<{'amd64': 'y'}> +CONFIG_XEN_AUTO_XLATE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_BACKEND policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_BALLOON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_BALLOON_MEMORY_HOTPLUG policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_BLKDEV_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_COMPAT_XENFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_DEBUG_FS policy<{'amd64': 'n'}> +CONFIG_XEN_DEV_EVTCHN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_DOM0 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_EFI policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_FBDEV_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_FRONT_PGDIR_SHBUF policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_XEN_GNTDEV policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_GNTDEV_DMABUF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_GRANT_DEV_ALLOC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_GRANT_DMA_ALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_GRANT_DMA_IOMMU policy<{'arm64': 'y'}> +CONFIG_XEN_GRANT_DMA_OPS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_HAVE_PVMMU policy<{'amd64': 'y'}> +CONFIG_XEN_HAVE_VPMU policy<{'amd64': 'y'}> +CONFIG_XEN_MCE_LOG policy<{'amd64': 'y'}> +CONFIG_XEN_MEMORY_HOTPLUG_LIMIT policy<{'amd64': '512'}> +CONFIG_XEN_NETDEV_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_PCIDEV_BACKEND policy<{'amd64': 'm'}> +CONFIG_XEN_PCIDEV_FRONTEND policy<{'amd64': 'm'}> +CONFIG_XEN_PCIDEV_STUB policy<{'arm64': 'm'}> +CONFIG_XEN_PCI_STUB policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_PRIVCMD policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_XEN_PRIVCMD_EVENTFD policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_PV policy<{'amd64': 'y'}> +CONFIG_XEN_PVCALLS_BACKEND policy<{'amd64': 'n', 'arm64': 'n', 'armhf': '-'}> +CONFIG_XEN_PVCALLS_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_PVH policy<{'amd64': 'y'}> +CONFIG_XEN_PVHVM policy<{'amd64': 'y'}> +CONFIG_XEN_PVHVM_GUEST policy<{'amd64': 'y'}> +CONFIG_XEN_PVHVM_SMP policy<{'amd64': 'y'}> +CONFIG_XEN_PV_DOM0 policy<{'amd64': 'y'}> +CONFIG_XEN_PV_MSR_SAFE policy<{'amd64': 'y'}> +CONFIG_XEN_PV_SMP policy<{'amd64': 'y'}> +CONFIG_XEN_SCRUB_PAGES_DEFAULT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_SCSI_BACKEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_SCSI_FRONTEND policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_SYMS policy<{'amd64': 'y'}> +CONFIG_XEN_SYS_HYPERVISOR policy<{'amd64': 'y', 'arm64': 'y', 'armhf': '-'}> +CONFIG_XEN_UNPOPULATED_ALLOC policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_VIRTIO policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XEN_VIRTIO_FORCE_GRANT policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_XEN_WDT policy<{'amd64': 'm', 'arm64': 'm', 'armhf': '-'}> +CONFIG_XEN_XENBUS_FRONTEND policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_XE_VFIO_PCI policy<{'amd64': 'm', 'arm64-generic': 'm', 'armhf': 'm', 'riscv64': 'm'}> +CONFIG_XFRM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_AH policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_ALGO policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_ESP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_ESPINTCP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_INTERFACE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_IPCOMP policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_IPTFS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_MIGRATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFRM_OFFLOAD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_STATISTICS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFRM_SUB_POLICY policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFRM_USER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFRM_USER_COMPAT policy<{'amd64': 'm'}> +CONFIG_XFS_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XFS_ONLINE_SCRUB policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XFS_POSIX_ACL policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_QUOTA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_RT policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_SUPPORT_ASCII_CI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_SUPPORT_V4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XFS_WARN policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_XGENE_DMA policy<{'arm64': 'm'}> +CONFIG_XGENE_PMU policy<{'arm64': 'y'}> +CONFIG_XGENE_SLIMPRO_MBOX policy<{'arm64': 'm'}> +CONFIG_XIAOMI_WMI policy<{'amd64': 'm'}> +CONFIG_XILINX_AMS policy<{'arm64': 'm'}> +CONFIG_XILINX_AXI_EMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_XILINX_DMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_EMACLITE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_GMII2RGMII policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XILINX_INTC policy<{'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_XILINX_LL_TEMAC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_PR_DECOUPLER policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_SDFEC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_VCU policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_XILINX_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILINX_WINDOW_WATCHDOG policy<{'arm64': 'm'}> +CONFIG_XILINX_XADC policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_XDMA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILINX_ZYNQMP_DMA policy<{'arm64': 'm'}> +CONFIG_XILINX_ZYNQMP_DPDMA policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYBUS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XILLYBUS_CLASS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYBUS_OF policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYBUS_PCIE policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XILLYUSB policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': '-'}> +CONFIG_XIL_AXIS_FIFO policy<{'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_XLNX_EVENT_MANAGER policy<{'arm64': 'y'}> +CONFIG_XLNX_R5_REMOTEPROC policy<{'arm64': 'm'}> +CONFIG_XMON policy<{'ppc64el': 'y'}> +CONFIG_XMON_DEFAULT policy<{'ppc64el': 'n'}> +CONFIG_XMON_DEFAULT_RO_MODE policy<{'ppc64el': 'y'}> +CONFIG_XMON_DISASSEMBLY policy<{'ppc64el': 'y'}> +CONFIG_XOR_BLOCKS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_XPOWER_PMIC_OPREGION policy<{'amd64': 'y'}> +CONFIG_XPS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XXHASH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_ARM policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_ARM64 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_ARMTHUMB policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_BCJ policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_MICROLZMA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_POWERPC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_RISCV policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_XZ_DEC_SPARC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_XZ_DEC_TEST policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_XZ_DEC_X86 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'n'}> +CONFIG_YAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_YAMAHA_YAS530 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_YELLOWFIN policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_YENTA policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': '-'}> +CONFIG_YENTA_ENE_TUNE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_O2 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_RICOH policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_TI policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YENTA_TOSHIBA policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': '-'}> +CONFIG_YOGABOOK policy<{'amd64': 'm'}> +CONFIG_YT2_1380 policy<{'amd64': 'm'}> +CONFIG_ZBOOT_ROM_BSS policy<{'armhf': '0x0'}> +CONFIG_ZBOOT_ROM_TEXT policy<{'armhf': '0x0'}> +CONFIG_ZCRYPT policy<{'s390x': 'm'}> +CONFIG_ZD1211RW policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZD1211RW_DEBUG policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n'}> +CONFIG_ZEROPLUS_FF policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y'}> +CONFIG_ZERO_CALL_USED_REGS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZFCP policy<{'s390x': 'm'}> +CONFIG_ZIIRAVE_WATCHDOG policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'n'}> +CONFIG_ZISOFS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZL3073X policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZL3073X_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZL3073X_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZLIB_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZLIB_INFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZONEFS_FS policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZONE_DEVICE policy<{'amd64': 'y', 'arm64': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZONE_DMA32 policy<{'amd64': 'y', 'arm64': 'y', 'riscv64': 'y'}> +CONFIG_ZOPT2201 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZPA2326 policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZPA2326_I2C policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZPA2326_SPI policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm'}> +CONFIG_ZRAM policy<{'amd64': 'm', 'arm64': 'm', 'armhf': 'm', 'ppc64el': 'm', 'riscv64': 'm', 's390x': 'm'}> +CONFIG_ZRAM_BACKEND_842 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_DEFLATE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_LZ4 policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_LZ4HC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_BACKEND_ZSTD policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_DEF_COMP policy<{'amd64': '"lzo-rle"', 'arm64': '"lzo-rle"', 'armhf': '"lzo-rle"', 'ppc64el': '"lzo-rle"', 'riscv64': '"lzo-rle"', 's390x': '"lzo-rle"'}> +CONFIG_ZRAM_DEF_COMP_842 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_DEFLATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZ4 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZ4HC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZO policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_DEF_COMP_LZORLE policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_DEF_COMP_ZSTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_MEMORY_TRACKING policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_MULTI_COMP policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZRAM_TRACK_ENTRY_ACTIME policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZRAM_WRITEBACK policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSMALLOC policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSMALLOC_CHAIN_SIZE policy<{'amd64': '8', 'arm64': '8', 'armhf': '8', 'ppc64el': '8', 'riscv64': '8', 's390x': '8'}> +CONFIG_ZSMALLOC_STAT policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSTD_COMMON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSTD_COMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSTD_DECOMPRESS policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSWAP policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT policy<{'amd64': '"lzo"', 'arm64': '"lzo"', 'armhf': '"lzo"', 'ppc64el': '"lzo"', 'riscv64': '"lzo"', 's390x': '"lzo"'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_DEFAULT_ON policy<{'amd64': 'n', 'arm64': 'n', 'armhf': 'n', 'ppc64el': 'n', 'riscv64': 'n', 's390x': 'n'}> +CONFIG_ZSWAP_SHRINKER_DEFAULT_ON policy<{'amd64': 'y', 'arm64': 'y', 'armhf': 'y', 'ppc64el': 'y', 'riscv64': 'y', 's390x': 'y'}> +CONFIG_ZYNQMP_FIRMWARE policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_FIRMWARE_DEBUG policy<{'arm64': 'n'}> +CONFIG_ZYNQMP_IPI_MBOX policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_PM_DOMAINS policy<{'arm64': 'y'}> +CONFIG_ZYNQMP_POWER policy<{'arm64': 'y'}> --- linux-nvidia-7.0.0.orig/debian.master/control.d/flavour-control.stub +++ linux-nvidia-7.0.0/debian.master/control.d/flavour-control.stub @@ -0,0 +1,88 @@ +# Items that get replaced: +# FLAVOUR +# ARCH +# SUPPORTED +# TARGET +# BOOTLOADER +# =PROVIDES= +# =DEPENDS= +# +# Items marked with =FOO= are optional +# +# This file describes the template for packages that are created for each flavour +# in debian/control.d/vars.* +# +# This file gets edited in a couple of places. See the debian/control.stub rule in +# debian/rules. PGGVER, ABINUM, and SRCPKGNAME are all converted in the +# process of creating debian/control. +# +# The flavour specific strings (ARCH, etc) are converted using values from the various +# flavour files in debian/control.d/vars.* +# +# XXX: Leave the blank line before the first package!! + +Package: linux-modules-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, =DEPENDS=wireless-regdb +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel modules for version PKGVER + Contains the corresponding System.map file, the modules built by the + packager, and scripts that try to ensure that the system is not left in an + unbootable state after an update. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-headers-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-headers-PKGVER-ABINUM, ${shlibs:Depends} +Provides: linux-headers, linux-headers-3.0 +Description: Linux kernel headers for version PKGVER + This package provides kernel header files for version PKGVER. + . + This is for sites that want the latest kernel headers. Please read + /usr/share/doc/linux-headers-PKGVER-ABINUM/debian.README.gz for details. + +Package: linux-lib-rust-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: amd64 +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Rust library files related to Linux kernel version PKGVER + This package provides kernel library files for version PKGVER, that allow to + compile out-of-tree kernel modules written in Rust. + +Package: linux-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-tools-PKGVER-ABINUM +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as x86_energy_perf_policy) for + version PKGVER-ABINUM. + +Package: linux-cloud-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud for version PKGVER-ABINUM. + --- linux-nvidia-7.0.0.orig/debian.master/control.d/flavour-signed-control.stub +++ linux-nvidia-7.0.0/debian.master/control.d/flavour-signed-control.stub @@ -0,0 +1,38 @@ +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Provides: linux-image, fuse-module, =PROVIDES=${linux:rprovides} +Depends: ${misc:Depends}, ${shlibs:Depends}, kmod, linux-base (>= 4.5ubuntu1~16.04.1), linux-modules-PKGVER-ABINUM-FLAVOUR +Recommends: BOOTLOADER, dracut | linux-initramfs-tool +Breaks: flash-kernel (<< 3.90ubuntu2) [arm64 armhf], s390-tools (<< 2.3.0-0ubuntu3) [s390x] +Conflicts: linux-image=SIGN-PEER-PKG=-PKGVER-ABINUM-FLAVOUR +Suggests: bpftool, linux-perf, SRCPKGNAME-tools, linux-headers-PKGVER-ABINUM-FLAVOUR +Description: Linux kernel image for version PKGVER + This package contains the=SIGN-ME-TXT= Linux kernel image for version PKGVER. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR-dbgsym +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends} +Provides: linux-debug +Description: Linux kernel debug image for version PKGVER + This package provides the=SIGN-ME-TXT= kernel debug image for version PKGVER. + . + This is for sites that wish to debug the kernel. + . + The kernel image contained in this package is NOT meant to boot from. It + is uncompressed, and unstripped. This package also includes the + unstripped modules. + --- linux-nvidia-7.0.0.orig/debian.master/control.d/vars.generic +++ linux-nvidia-7.0.0/debian.master/control.d/vars.generic @@ -0,0 +1,6 @@ +arch="amd64 armhf arm64 ppc64el s390x" +supported="Generic" +target="Geared toward desktop and server systems." +bootloader="grub-pc [amd64] | grub-efi-amd64 [amd64] | grub-efi-ia32 [amd64] | grub [amd64] | lilo [amd64] | flash-kernel [armhf arm64] | grub-efi-arm64 [arm64] | grub-efi-arm [armhf] | grub-ieee1275 [ppc64el]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules, virtualbox-guest-modules [amd64]" +depends="linux-main-modules-zfs-PKGVER-ABINUM-generic [amd64 arm64 ppc64el s390x]" --- linux-nvidia-7.0.0.orig/debian.master/control.d/vars.generic-64k +++ linux-nvidia-7.0.0/debian.master/control.d/vars.generic-64k @@ -0,0 +1,6 @@ +arch="arm64" +supported="Generic 64K pages" +target="Geared toward desktop and server systems." +bootloader="grub-efi-arm64 [arm64] | flash-kernel [arm64]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules" +depends="linux-main-modules-zfs-PKGVER-ABINUM-generic-64k [arm64]" --- linux-nvidia-7.0.0.orig/debian.master/control.stub.in +++ linux-nvidia-7.0.0/debian.master/control.stub.in @@ -0,0 +1,102 @@ +Source: SRCPKGNAME +Section: devel +Priority: optional +Maintainer: Ubuntu Kernel Team +Rules-Requires-Root: no +Standards-Version: 3.9.4.0 +Build-Depends: + autoconf , + automake , + bc , + bindgen:native [amd64 arm64 armhf ppc64el riscv64 s390x], + bison , + clang-21:native [amd64 arm64 armhf ppc64el riscv64 s390x], + cpio, + curl , + debhelper-compat (= 10), + default-jdk-headless:native , + dkms , + flex , + gawk , + java-common , + kmod , + libaudit-dev , + libbpf-dev , + libcap-dev , + libdebuginfod-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libdw-dev , + libelf-dev , + libiberty-dev , + liblzma-dev , + libnewt-dev , + libnl-3-dev, + libnl-genl-3-dev, + libnuma-dev [amd64 arm64 ppc64el s390x] , + libpci-dev , + libssl-dev , + libstdc++-dev, + libtool , + libtraceevent-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libtracefs-dev [amd64 arm64 armhf ppc64el s390x riscv64] , + libudev-dev , + libunwind8-dev [amd64 arm64 armhf ppc64el] , + llvm-21-dev, + makedumpfile:native [amd64] , + openssl , + pahole (>= 1.29-2ubuntu2) [amd64 arm64 armhf ppc64el s390x riscv64] | dwarves (>= 1.21) [amd64 arm64 armhf ppc64el s390x riscv64] , + pkg-config , + python3:native , + python3-dev:native , + libpython3-dev , + python3-setuptools, + rsync [!i386] , + rust-src:native [amd64 arm64 armhf ppc64el riscv64 s390x], + rustc:native (>= 1.82) [amd64 arm64 armhf ppc64el riscv64 s390x], + rustfmt:native [amd64 arm64 armhf ppc64el riscv64 s390x], + uuid-dev , + zstd , + bpftool:native [amd64 arm64 armhf ppc64el riscv64 s390x] , +Build-Depends-Indep: + asciidoc , + bzip2 , + python3-docutils , + sharutils , + xmlto , +Vcs-Git: git://git.launchpad.net/~ubuntu-kernel/ubuntu/+source/linux/+git/=SERIES= +XS-Testsuite: autopkgtest +#XS-Testsuite-Depends: gcc-4.7 binutils + +Package: SRCPKGNAME-headers-PKGVER-ABINUM +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Header files related to Linux kernel version PKGVER + This package provides kernel header files for version PKGVER, for sites + that want the latest kernel headers. Please read + /usr/share/doc/SRCPKGNAME-headers-PKGVER-ABINUM/debian.README.gz for details + +Package: SRCPKGNAME-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf arm64 ppc64el s390x +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-tools-common +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version PKGVER-ABINUM. + You probably want to install linux-tools-PKGVER-ABINUM-. + +Package: SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 armhf +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-cloud-tools-common +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud tools for version PKGVER-ABINUM. + You probably want to install linux-cloud-tools-PKGVER-ABINUM-. --- linux-nvidia-7.0.0.orig/debian.master/modprobe.d/common.conf +++ linux-nvidia-7.0.0/debian.master/modprobe.d/common.conf @@ -0,0 +1,3 @@ +# LP:1434842 -- disable OSS drivers by default to allow pulseaudio to emulate +blacklist snd-mixer-oss +blacklist snd-pcm-oss --- linux-nvidia-7.0.0.orig/debian.master/reconstruct +++ linux-nvidia-7.0.0/debian.master/reconstruct @@ -0,0 +1,34 @@ +# Recreate any symlinks created since the orig. +[ ! -L 'ubuntu/igh-ecat/master/rtdm-ioctl.c' ] && ln -sf 'ioctl.c' 'ubuntu/igh-ecat/master/rtdm-ioctl.c' +chmod +x 'debian/cloud-tools/hv_get_dhcp_info' +chmod +x 'debian/cloud-tools/hv_get_dns_info' +chmod +x 'debian/cloud-tools/hv_set_ifconfig' +chmod +x 'debian/rules' +chmod +x 'debian/scripts/checks/final-checks' +chmod +x 'debian/scripts/checks/module-signature-check' +chmod +x 'debian/scripts/control-create' +chmod +x 'debian/scripts/dkms-build' +chmod +x 'debian/scripts/dkms-build--nvidia-N' +chmod +x 'debian/scripts/dkms-build-configure--zfs' +chmod +x 'debian/scripts/file-downloader' +chmod +x 'debian/scripts/link-headers' +chmod +x 'debian/scripts/link-lib-rust' +chmod +x 'debian/scripts/misc/annotations' +chmod +x 'debian/scripts/misc/find-missing-sauce.sh' +chmod +x 'debian/scripts/misc/gen-auto-reconstruct' +chmod +x 'debian/scripts/misc/git-ubuntu-log' +chmod +x 'debian/scripts/misc/insert-changes' +chmod +x 'debian/scripts/misc/insert-ubuntu-changes' +chmod +x 'debian/scripts/misc/kernelconfig' +chmod +x 'debian/scripts/sign-module' +chmod +x 'debian/templates/extra.postinst.in' +chmod +x 'debian/templates/extra.postrm.in' +chmod +x 'debian/templates/headers.postinst.in' +chmod +x 'debian/templates/image.postinst.in' +chmod +x 'debian/templates/image.postrm.in' +chmod +x 'debian/templates/image.preinst.in' +chmod +x 'debian/templates/image.prerm.in' +chmod +x 'debian/tests/rebuild' +chmod +x 'debian/tests/ubuntu-regression-suite' +# Remove any files deleted from the orig. +exit 0 --- linux-nvidia-7.0.0.orig/debian.master/rules.d/amd64.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/amd64.mk @@ -0,0 +1,20 @@ +build_arch = x86 +defconfig = defconfig +flavours = generic +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz +vdso = vdso_install +no_dumpfile = true +uefi_signed = true +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_x86 = true +do_tools_hyperv = true +do_tools_rtla = true +do_tools_acpidbg = true +do_lib_rust = true --- linux-nvidia-7.0.0.orig/debian.master/rules.d/arm64.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/arm64.mk @@ -0,0 +1,20 @@ +build_arch = arm64 +defconfig = defconfig +flavours = generic generic-64k +build_image = vmlinuz.efi +kernel_file = arch/$(build_arch)/boot/vmlinuz.efi +install_file = vmlinuz +no_dumpfile = true +uefi_signed = true + +vdso = vdso_install + +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = true + +do_dtbs = true --- linux-nvidia-7.0.0.orig/debian.master/rules.d/armhf.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/armhf.mk @@ -0,0 +1,18 @@ +build_arch = arm +defconfig = defconfig +flavours = generic +build_image = zImage +kernel_file = arch/$(build_arch)/boot/zImage +install_file = vmlinuz +no_dumpfile = true + +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = false +do_tools_perf_jvmti = false +do_tools_perf_python = false +do_tools_bpftool = true +do_tools_bpftool_stub = true +do_tools_rtla = true + +do_dtbs = true --- linux-nvidia-7.0.0.orig/debian.master/rules.d/i386.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/i386.mk @@ -0,0 +1,12 @@ +build_arch = i386 +defconfig = defconfig +flavours = generic +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz +vdso = vdso_install +no_dumpfile = true +do_flavour_image_package = false +do_tools = false +do_flavour_header_package = false +do_common_headers_indep = false --- linux-nvidia-7.0.0.orig/debian.master/rules.d/ppc64el.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/ppc64el.mk @@ -0,0 +1,17 @@ +build_arch = powerpc +defconfig = pseries_le_defconfig +flavours = generic +build_image = vmlinux.strip +kernel_file = arch/powerpc/boot/vmlinux.strip +install_file = vmlinux +no_dumpfile = true +opal_signed = false +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = true + +#do_flavour_image_package = false --- linux-nvidia-7.0.0.orig/debian.master/rules.d/riscv64.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/riscv64.mk @@ -0,0 +1,21 @@ +build_arch = riscv +defconfig = defconfig +flavours = generic +build_image = Image +kernel_file = arch/$(build_arch)/boot/Image +install_file = vmlinuz + +vdso = vdso_install +no_dumpfile = true + +do_flavour_image_package = false +do_tools = true +do_flavour_header_package = false +do_common_headers_indep = false +do_tools_usbip = false +do_tools_cpupower = false +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_dtbs = false --- linux-nvidia-7.0.0.orig/debian.master/rules.d/s390x.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/s390x.mk @@ -0,0 +1,18 @@ +build_arch = s390 +defconfig = defconfig +flavours = generic +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz + +vdso = vdso_install +no_dumpfile = true + +sipl_signed = true +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = false --- linux-nvidia-7.0.0.orig/debian.master/rules.d/x32.mk +++ linux-nvidia-7.0.0/debian.master/rules.d/x32.mk @@ -0,0 +1,11 @@ +build_arch = x86 +defconfig = defconfig +flavours = +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz +vdso = vdso_install +no_dumpfile = true +uefi_signed = true + +do_flavour_image_package = false --- linux-nvidia-7.0.0.orig/debian.master/tracking-bug +++ linux-nvidia-7.0.0/debian.master/tracking-bug @@ -0,0 +1 @@ +2148159 d2026.04.13-1 --- linux-nvidia-7.0.0.orig/debian.master/upstream-realtime +++ linux-nvidia-7.0.0/debian.master/upstream-realtime @@ -0,0 +1,3 @@ +# The following upstream releases have been ported: +[upstream-realtime] + linux-7.0.y-rt = 7.0-rc1-rt1 --- linux-nvidia-7.0.0.orig/debian.master/upstream-stable +++ linux-nvidia-7.0.0/debian.master/upstream-stable @@ -0,0 +1,3 @@ +# The following upstream stable releases have been ported: +[upstream-stable] + linux-6.17.y = v6.17.1 --- linux-nvidia-7.0.0.orig/debian.master/variants +++ linux-nvidia-7.0.0/debian.master/variants @@ -0,0 +1,4 @@ +-7.0 +-- +-hwe-26.04 +-hwe-26.04-edge --- linux-nvidia-7.0.0.orig/debian.nvidia/changelog +++ linux-nvidia-7.0.0/debian.nvidia/changelog @@ -0,0 +1,1006 @@ +linux-nvidia (7.0.0-1006.6) resolute; urgency=medium + + * resolute/linux-nvidia: 7.0.0-1006.6 -proposed tracker (LP: #2148214) + + [ Ubuntu: 7.0.0-14.14 ] + + * resolute/linux: 7.0.0-14.14 -proposed tracker (LP: #2148159) + * support vflip/hflip for Sony IMX471 camera sensor (LP: #2138841) + - SAUCE: media: ipu-bridge: add TBE20A0 ACPI id for Sony IMX471 + * AA: disable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED (LP: #2147533) + - [Config] disable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED + * System doesn't response with mt76 call trace (LP: #2137448) + - wifi: mt76: mt792x: Fix a potential deadlock in high-load situations + * The second tbt storage plugged on the dock will not be recognized + (LP: #2139572) + - SAUCE: thunderbolt: Fix PCIe device enumeration with delayed rescan + * dma-buf filesystem flags fix (LP: #2139656) + - SAUCE: dma-buf: set SB_I_NOEXEC and SB_I_NODEV on dmabuf filesystem + * Bluetooth device (MT7925) not detected on USB bus with linux-oem-6.17 + (LP: #2145164) + - SAUCE: USB: hub: call ACPI _PRR reset during port power-cycle on + enumeration failure + * drm/i915/lnl+/tc: Fix false disconnect of active DP-alt TC port during + long HPD pulse (LP: #2143879) + - SAUCE: drm/i915/lnl+/tc: Fix false disconnect of active DP-alt TC port + during long HPD pulse + * i915 WARN_ON call trace during CB/WB on MTL/ARL platforms (LP: #2144537) + - SAUCE: drm/i915/xelpdp/tc: Convert TCSS power check WARN to a debug + message + * Miscellaneous Ubuntu changes + - [Packaging] Add support for per-flavour depends + - [Packaging] Don't hard-code lmm zfs dependency + - [Config] updateconfigs following v7.0 release + + [ Ubuntu: 7.0.0-13.13 ] + + * resolute/linux: 7.0.0-13.13 -proposed tracker (LP: #2147403) + * ubuntu_kselftests:_net/net:gre_gso.sh failing (LP: #2136820) + - SAUCE increase socat timeout in gre_gso.sh + * Canonical Kmod 2025 key rotation (LP: #2147447) + - [Packaging] ubuntu-compatible-signing -- make Ubuntu-Compatible-Signing + extensible + - [Packaging] ubuntu-compatible-signing -- allow consumption of positive + certs + - [Packaging] ubuntu-compatible-signing -- report the livepatch:2025 key + - [Config] prepare for Canonical Kmod key rotation + - [Packaging] ubuntu-compatible-signing -- report the kmod:2025 key + - [Packaging] ensure our cert rollups are always fresh + * On Dell system, the internal OLED display drops to a visibly low FPS after + suspend/resume (LP: #2144712) + - drm/i915/psr: Disable Panel Replay on Dell XPS 14 DA14260 as a quirk + - drm/i915/psr: Fixes for Dell XPS DA14260 quirk + * Realtek RTL8116AF SFP option module fails to get connected (LP: #2116144) + - SAUCE: r8169: add quirk for RTL8116af SerDes + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v7.0-rc7 rebase + + -- Jacob Martin Tue, 14 Apr 2026 16:19:48 -0500 + +linux-nvidia (7.0.0-1005.5) resolute; urgency=medium + + * resolute/linux-nvidia: 7.0.0-1005.5 -proposed tracker (LP: #2145971) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + + * Please make dracut the default initrd generator (LP: #2142775) + - [Packaging] recommends dracut instead of initramfs-tools + + [ Ubuntu: 7.0.0-12.12 ] + + * resolute/linux: 7.0.0-12.12 -proposed tracker (LP: #2146778) + * Packaging resync (LP: #1786013) + - [Packaging] update variants + * linux-generic does not run scripts in /usr/share/kernel/*.d (LP: #2147005) + - [Packaging] templates: Use consistent indentation + - [Packaging] templates: Run scripts in /usr/share/kernel/*.d too + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] riscv64: Enable COUNTER=m + - [Config] riscv64: Use GENDWARFKSYMS like other architectures + * unconfined profile denies userns_create for chromium based processes + (LP: #1990064) + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + * FFe: add network interface mediation to 26.04 (LP: #2144679) + - SAUCE: apparmor5.0.0 [57/57]: apparmor: add the ability to use interface + in network mediation. + * Jellyfin Desktop Flatpak doesn't work with the current AppArmor profile + (LP: #2142956) + - SAUCE: apparmor5.0.0 [29/57]: apparmor: fix fine grained inet mediation + sock_file_perm + - SAUCE: apparmor5.0.0 [30/57]: apparmor-next 7.1: aapparmor: use target + task's context in apparmor_getprocattr() + - SAUCE: apparmor5.0.0 [31/57]: apparmor-next 7.1: apparmor: return error + on namespace mismatch in verify_header + - SAUCE: apparmor5.0.0 [32/57]: apparmor-next 7.1: apparmor: enable + differential encoding + - SAUCE: apparmor5.0.0 [33/57]: apparmor-next 7.1: apparmor: propagate + -ENOMEM correctly in unpack_table + - SAUCE: apparmor5.0.0 [34/57]: apparmor-next 7.1: apparmor: Replace + memcpy + NUL termination with kmemdup_nul in do_setattr + - SAUCE: apparmor5.0.0 [35/57]: apparmor-next 7.1: apparmor: Remove + redundant if check in sk_peer_get_label + - SAUCE: apparmor5.0.0 [36/57]: apparmor-next 7.1: apparmor: use + __label_make_stale in __aa_proxy_redirect + - SAUCE: apparmor5.0.0 [37/57]: apparmor-next 7.1: apparmor: fix net.h and + policy.h circular include pattern + - SAUCE: apparmor5.0.0 [39/57]: apparmor-next 7.1: apparmor: make include + headers self-contained + - SAUCE: apparmor5.0.0 [40/57]: apparmor-next 7.1: apparmor: Use + sysfs_emit in param_get_{audit,mode} + - SAUCE: apparmor5.0.0 [41/57]: apparmor-next 7.1: apparmor: fix + rawdata_f_data implicit flex array + - SAUCE: apparmor5.0.0 [42/57]: apparmor-next 7.1: apparmor: free rawdata + as soon as possible + - SAUCE: apparmor5.0.0 [43/57]: apparmor-next 7.1: apparmor: Initial + support for compressed policies + - SAUCE: apparmor5.0.0 [44/57]: apparmor-next 7.1: apparmor: fix potential + UAF in aa_replace_profiles + - SAUCE: apparmor5.0.0 [45/57]: apparmor-next 7.1: apparmor: hide unused + get_loaddata_common_ref() function + - SAUCE: apparmor5.0.0 [46/57]: apparmor-next 7.1: apparmor: Fix string + overrun due to missing termination + - SAUCE: apparmor5.0.0 [47/57]: apparmor: fix packed tag on v5 header + struct + - SAUCE: apparmor5.0.0 [48/57]: apparmor: add temporal caching to audit + responses. + - SAUCE: apparmor5.0.0 [49/57]: apparmor: change fn_label_build() call to + not return NULL + - SAUCE: apparmor5.0.0 [50/57]: apparmor: make fn_label_build() capable of + handling not supported + - SAUCE: apparmor5.0.0 [51/57]: apparmor: move netfilter functions next to + the LSM network operations + - SAUCE: apparmor5.0.0 [52/57]: apparmor: move sock_rvc_skb() next to + inet_conn_request + - SAUCE: apparmor5.0.0 [53/57]: apparmor: fix af_unix local addr mediation + binding + - SAUCE: apparmor5.0.0 [54/57]: cleanups of apparmor af_unix mediation + - SAUCE: apparmor5.0.0 [55/57]: apparmor: fix apparmor_secmark_check() + when !inet and secmark defined. + - SAUCE: apparmor5.0.0 [56/57]: apparmor: fix auditing of non-mediation + falures + * snap service cannot change apparmor hat (LP: #2139664) // Jellyfin Desktop + Flatpak doesn't work with the current AppArmor profile (LP: #2142956) + - SAUCE: apparmor5.0.0 [38/57]: apparmor-next 7.1: apparmor: grab ns lock + and refresh when looking up changehat child profiles + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor5.0.0 [28/57]: apparmor: fix aa_label_sk_perm to check + for RULE_MEDIATES_NET + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/57]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/57]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/57]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [4/57]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [5/57]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [6/57]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [7/57]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [8/57]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [9/57]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [10/57]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [12/57]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [13/57]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [14/57]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [15/57]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [16/57]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [19/57]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [20/57]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [21/57]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [22/57]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [23/57]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [24/57]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [25/57]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [26/57]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [27/57]: apparmor: prevent profile->disconnected + double free in aa_free_profile + * update apparmor and LSM stacking patch set (LP: #2028253) // Installation + of AppArmor on a 6.14 kernel produces error message "Illegal number: yes" + (LP: #2102680) + - SAUCE: apparmor5.0.0 [17/57]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [18/57]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [11/57]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + * Enable new Intel WCL soundwire support (LP: #2143301) + - ASoC: sdw_utils: Add CS42L43B codec info + - ASoC: dt-bindings: cirrus, cs42l43: Add CS42L43B variant + - mfd: cs42l43: Add support for the B variant + - ASoC: cs42l43: Add support for the B variant + * Enable audio functions on Dell Huracan/Renegade platforms w/o built-in + microphone (LP: #2143902) + - ASoC: SDCA: Add default value for mipi-sdca-function-reset-max-delay + - ASoC: SDCA: Update counting of SU/GE DAPM routes + - ASoC: SDCA: Improve mapping of Q7.8 SDCA volumes + - ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops + - ASoC: add snd_soc_lookup_component_by_name helper + - ASoC: soc_sdw_utils: partial match the codec name + - ASoC: soc_sdw_utils: remove index from sdca codec name + * [SRU] MIPI camera is not working after upgrading to 6.17-oem + (LP: #2145171) + - SAUCE: ACPI: respect items already in honor_dep before skipping + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Actually enable llvm for perf + * Pull patch in qla2xxx to Resolute (LP: #2144856) + - scsi: qla2xxx: Add support to report MPI FW state + * Ubuntu Resolute Desktop image arm64 - Boot on SC8280XP stalls with gpi-dma + errors (LP: #2142403) + - Revert "arm64: dts: qcom: sc8280xp: Enable GPI DMA" + * 26.04 Snapdragon X Elite: Sync concept kernel changes (LP: #2144643) + - SAUCE: arm64: dts: add missing denali-oled.dtb to Makefile + - SAUCE: dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema + - SAUCE: phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add simple-mfd + compatible + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add optional PHY handle + definitions + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add support for combo- + mode endpoints + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Describe iommu entries + - SAUCE: media: qcom: camss: Add legacy_phy flag to SoC definition + structures + - SAUCE: media: qcom: camss: Add support for PHY API devices + - SAUCE: media: qcom: camss: Drop legacy PHY descriptions from x1e + - SAUCE: arm64: dts: qcom: x1e80100: Add CAMCC block definition + - SAUCE: arm64: dts: qcom: x1e80100: Add CCI definitions + - SAUCE: arm64: dts: qcom: x1e80100: Add CAMSS block definition + - SAUCE: arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m + regulators + - SAUCE: arm64: dts: qcom: x1e80100-crd: Add ov08x40 RGB sensor on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Add pm8010 camera PMIC with + voltage levels for IR and RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Add on ov02c10 RGB sensor on + CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add pm8010 camera + PMIC with voltage levels for IR and RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add l7b_2p8 + voltage regulator for RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add ov02c10 RGB + sensor on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-dell-inspiron14-7441: Switch on CAMSS + RGB sensor + - SAUCE: arm64: dts: qcom: x1-asus-zenbook-a14: Add on OV02C10 RGB sensor + on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: add camera support + - SAUCE: arm64: dts: qcom: x1e78100-t14s: enable camera privacy indicator + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: enable camera + privacy indicator + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: enable camera privacy + indicator + - SAUCE: dt-bindings: arm: qcom: Add ASUS Vivobook X1P42100 variant + - SAUCE: arm64: dts: qcom: x1-vivobook-s15: create a common dtsi for Hamoa + and Purwa variants + - SAUCE: arm64: dts: qcom: x1-vivobook-s15: add Purwa-compatible device + tree + - SAUCE: firmware: qcom: scm: allow QSEECOM on ASUS Vivobook X1P42100 + variant + - SAUCE: arm64: dts: qcom: hamoa: Move PCIe PERST and Wake GPIOs to port + nodes + - SAUCE: arm64: dts: qcom: x1e-acer-swift-14: Move PCIe PERST and Wake + GPIOs to port nodes + * 25.10 Snapdragon X Elite: Sync concept kernel changes (LP: #2121477) + - SAUCE: wip: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + * Miscellaneous Ubuntu changes + - SAUCE: dt-bindings: arm: qcom: Document HP EliteBook 6 G1q + - SAUCE: firmware: qcom: scm: Allow QSEECOM for HP EliteBook 6 G1q + - SAUCE: arm64: dts: qcom: x1p42100-hp-elitebook-6-g1q: DT for HP + EliteBook 6 G1q + - [Config] PHY_QCOM_MIPI_CSI2=m + - SAUCE: arm64: dts: x1e80100-lenovo-yoga-slim7x: Fix RGB camera supplies + - [Config] toolchain version update + - Update Changes.md after v7.0-rc5 rebase + - [Packaging] update Ubuntu.md + - [Config] enable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED + - [Packaging] Add linux-main-modules-zfs to linux-modules depends + * Miscellaneous upstream changes + - Revert "UBUNTU: SAUCE: Add Bluetooth support for the Lenovo Yoga Slim + 7x" + + [ Ubuntu: 7.0.0-10.10 ] + + * resolute/linux: 7.0.0-10.10 -proposed tracker (LP: #2144865) + * Miscellaneous upstream changes + - Revert "powerpc: fix KUAP warning in VMX usercopy path" + + [ Ubuntu: 7.0.0-9.9 ] + + * resolute/linux: 7.0.0-9.9 -proposed tracker (LP: #2144735) + * Please make dracut the default initrd generator (LP: #2142775) + - [Packaging] recommends dracut instead of initramfs-tools + * Miscellaneous Ubuntu changes + - SAUCE: Change RISC-V target to RVA23 (riscv64a23-unknown-linux-gnu) + + [ Ubuntu: 7.0.0-8.8 ] + + * resolute/linux: 7.0.0-8.8 -proposed tracker (LP: #2144652) + * UBUNTU: SAUCE: igc: Increase Thunderbolt MAC passthrough delay to 1000ms + (LP: #2143197) + - SAUCE: igc: Increase Thunderbolt MAC passthrough delay to 1000ms + * [usrmerge] evaluate kernel owned packages for DEP17 compliance + (LP: #2139276) + - [Packaging] Install modules in /usr/lib/modules + * Miscellaneous Ubuntu changes + - [Config] hardening: enable LIST_HARDENED + - [Config] hardening: disable LDISC_AUTOLOAD + - [Config] hardening: disable LEGACY_PTYS + - [Config] updateconfigs following v7.0-rc4 rebase + + [ Ubuntu: 7.0.0-7.7 ] + + * resolute/linux: 7.0.0-7.7 -proposed tracker (LP: #2143974) + * unconfined profile denies userns_create for chromium based processes + (LP: #1990064) + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + * Jellyfin Desktop Flatpak doesn't work with the current AppArmor profile + (LP: #2142956) + - SAUCE: apparmor5.0.0 [29/29]: apparmor: fix fine grained inet mediation + sock_file_perm + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor5.0.0 [28/29]: apparmor: fix aa_label_sk_perm to check + for RULE_MEDIATES_NET + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/29]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/29]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/29]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [4/29]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [5/29]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [6/29]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [7/29]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [8/29]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [9/29]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [10/29]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [12/29]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [13/29]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [14/29]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [15/29]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [16/29]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [19/29]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [20/29]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [21/29]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [22/29]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [23/29]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [24/29]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [25/29]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [26/29]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [27/29]: apparmor: prevent profile->disconnected + double free in aa_free_profile + * update apparmor and LSM stacking patch set (LP: #2028253) // Installation + of AppArmor on a 6.14 kernel produces error message "Illegal number: yes" + (LP: #2102680) + - SAUCE: apparmor5.0.0 [17/29]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [18/29]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [11/29]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + * NPU utilization on amdxdna is missing (LP: #2143243) + - SAUCE: accel/amdxdna: Add IOCTL to retrieve realtime NPU power estimate + - SAUCE: accel/amdxdna: Support sensors for column utilization + - SAUCE: accel/amdxdna: Import AMD_PMF namespace + * Adopting dark mode by default for OLED panel (LP: #2143203) + - SAUCE: drm/connector: Add a new 'panel_type' property + - SAUCE: drm/amd/display: Attach OLED property to eDP panels + * Support AMD Image Signal Processing (ISP) unit V4.0 (LP: #2110092) + - SAUCE: media: platform: amd: Introduce amd isp4 capture driver + - SAUCE: media: platform: amd: low level support for isp4 firmware + - SAUCE: media: platform: amd: Add isp4 fw and hw interface + - SAUCE: media: platform: amd: isp4 subdev and firmware loading handling + added + - SAUCE: media: platform: amd: isp4 video node and buffers handling added + - SAUCE: Documentation: add documentation of AMD isp 4 driver + - SAUCE: media: platform: amd: isp4 debug fs logging and more descriptive + errors + - [Config] Enable VIDEO_AMD_ISP4_CAPTURE + * Miscellaneous Ubuntu changes + - [Config] temporarily disable OBJTOOL_WERROR + + -- Jacob Martin Thu, 02 Apr 2026 10:48:01 -0500 + +linux-nvidia (7.0.0-1003.3) resolute; urgency=medium + + * Packaging resync (LP: #1786013) + - [Packaging] debian.nvidia/dkms-versions -- update from kernel-versions + (adhoc/d2026.02.16) + + * Backport NVIDIA: SAUCE: vfio/nvgrace-egm: split zapping EGM into 1GB + chunks (LP: #2142160) + - NVIDIA: SAUCE: vfio/nvgrace-egm: split zapping EGM into 1GB chunks + + * r8127 module unload triggers NAPI WARN in netif_napi_del_locked() + (LP: #2141780) + - NVIDIA: SAUCE: r8127: fix NAPI warning on module removal + + * Enable Coresight in Perf (LP: #2093957) + - [Packaging] Enable coresight in Perf if arm64 + - [Packaging] Add libopencsd-dev as a build dependency + + * Backport nvgrace-gpu hugepfnmap, ecc patches and miscellaneous cleanups + (LP: #2138892) + - NVIDIA: SAUCE: vfio/nvgrace-egm: register EGM PFNMAP range with + memory_failure + - NVIDIA: SAUCE: vfio: Remove vfio_device_from_file() declaration + + * missing prototype for vfio_device_from_file() (LP: #2138132) + - NVIDIA: SAUCE: vfio: Fix missing prototype warning + + * r8127: Downgrade GPL claim to info (LP: #2137588) + - NVIDIA: SAUCE: r8127: print GPL_CLAIM with KERN_INFO + + * mt7925: Incorrect MLO mode in firmware control (LP: #2138755) + - NVIDIA: SAUCE: wifi: mt76: mt7925: Fix incorrect MLO mode in firmware + control + + * Enable GDS in the 6.8 based linux-nvidia kernel (LP: #2059814) + - NVIDIA: [Packaging] Add nvidia-fs build dependencies + + * Add PCIe Hotplug Driver for CX7 on DGX Spark (LP: #2138269) + - NVIDIA: SAUCE: MEDIATEK: platform: Add PCIe Hotplug Driver for CX7 on + DGX Spark + + * Backport support for Grace MPAM (LP: #2122432) + - NVIDIA: SAUCE: DT: cacheinfo: Expose the code to generate a cache-id + from a device_node + - NVIDIA: SAUCE: DT: dt-bindings: arm: Add MPAM MSC binding + - NVIDIA: SAUCE: arm64: mpam: Context switch the MPAM registers + - NVIDIA: SAUCE: arm64: mpam: Re-initialise MPAM regs when CPU comes + online + - NVIDIA: SAUCE: arm64: mpam: Advertise the CPUs MPAM limits to the driver + - NVIDIA: SAUCE: arm64: mpam: Add cpu_pm notifier to restore MPAM sysregs + - NVIDIA: SAUCE: arm64: mpam: Add helpers to change a tasks and cpu mpam + partid/pmg values + - NVIDIA: SAUCE: cacheinfo: Add helper to find the cache size from + cpu+level + - NVIDIA: SAUCE: arm_mpam: resctrl: Add boilerplate cpuhp and domain + allocation + - NVIDIA: SAUCE: arm_mpam: resctrl: Pick the caches we will use as resctrl + resources + - NVIDIA: SAUCE: arm_mpam: resctrl: Implement + resctrl_arch_reset_all_ctrls() + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_get_config() + - NVIDIA: SAUCE: arm_mpam: resctrl: Implement helpers to update + configuration + - NVIDIA: SAUCE: arm_mpam: resctrl: Add plumbing against arm64 task and + cpu hooks + - NVIDIA: SAUCE: arm_mpam: resctrl: Add CDP emulation + - NVIDIA: SAUCE: arm_mpam: resctrl: Add rmid index helpers + - NVIDIA: SAUCE: arm_mpam: resctrl: Convert to/from MPAMs bitmaps and + fixed-point formats + - NVIDIA: SAUCE: arm_mpam: resctrl: Add support for 'MB' resource + - NVIDIA: SAUCE: arm_mpam: resctrl: Reject oversized memory bandwidth + portion bitmaps + - NVIDIA: SAUCE: arm_mpam: resctrl: Fix MB min_bandwidth value exposed to + userspace + - NVIDIA: SAUCE: arm_mpam: resctrl: Add kunit test for control format + conversions + - NVIDIA: SAUCE: arm_mpam: resctrl: Add support for csu counters + - NVIDIA: SAUCE: arm_mpam: resctrl: Pre-allocate free running monitors + - NVIDIA: SAUCE: arm_mpam: resctrl: Pre-allocate assignable monitors + - NVIDIA: SAUCE: arm_mpam: resctrl: Add kunit test for ABMC/CDP + interactions + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_config_cntr() for + ABMC use + - NVIDIA: SAUCE: arm_mpam: resctrl: Allow resctrl to allocate monitors + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_rmid_read() and + resctrl_arch_reset_rmid() + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_cntr_read() & + resctrl_arch_reset_cntr() + - NVIDIA: SAUCE: untested: arm_mpam: resctrl: Allow monitors to be + configured with filters + - NVIDIA: SAUCE: arm_mpam: resctrl: Add empty definitions for fine-grained + enables + - NVIDIA: SAUCE: arm64: mpam: Select ARCH_HAS_CPU_RESCTRL + - NVIDIA: SAUCE: fs/resctrl: Don't touch rmid_ptrs[] in free_rmid() when + there are no monitors + - NVIDIA: SAUCE: fs/resctrl: Avoid a race with dom_data_exit() and + closid_num_dirty_rmid[] + - NVIDIA: SAUCE: fs/resctrl: Avoid a race with dom_data_exit() and + rmid_ptrs[] + - NVIDIA: SAUCE: perf/arm-cmn: Stop claiming all the resources + - NVIDIA: SAUCE: arm_mpam: resctrl: Call resctrl_init() on platforms that + can support resctrl + - NVIDIA: SAUCE: arm_mpam: resctrl: Call resctrl_exit() in the event of + errors + - NVIDIA: SAUCE: arm_mpam: resctrl: Update the rmid reallocation limit + - NVIDIA: SAUCE: arm_mpam: resctrl: Sort the order of the domain lists + - NVIDIA: SAUCE: arm_mpam: Generate a configuration for min controls + - NVIDIA: SAUCE: arm_mpam: Add quirk framework + - NVIDIA: SAUCE: arm_mpam: Add workaround for T241-MPAM-1 + - NVIDIA: SAUCE: arm_mpam: Add workaround for T241-MPAM-4 + - NVIDIA: SAUCE: arm_mpam: Add workaround for T241-MPAM-6 + - NVIDIA: SAUCE: arm_mpam: Quirk CMN-650's CSU NRDY behaviour + - NVIDIA: SAUCE: debugfs: Add helpers for creating cpumask entries in + debugfs + - NVIDIA: SAUCE: arm_mpam: Add debugfs entries to show the MSC/RIS the + driver discovered + - NVIDIA: SAUCE: arm_mpam: Add force-disable debugfs trigger + - NVIDIA: SAUCE: arm_mpam: Expose the number of NRDY retries in debugfs + - NVIDIA: SAUCE: arm_mpam: Add resctrl_arch_round_bw() + - NVIDIA: SAUCE: fs/resctrl,x86/resctrl: Factor mba rounding to be per- + arch + - NVIDIA: SAUCE: arm_mpam: Relax num_rmids parameter advertised to + userspace + - NVIDIA: SAUCE: arm_mpam: Split the locking around the mon_sel registers + - NVIDIA: SAUCE: arm_mpam: Allow the maximum partid to be overridden from + the command line + - NVIDIA: SAUCE: arm_mpam: Allow MSC to be forced to have an unknown + location + - NVIDIA: SAUCE: fs/resctrl: Add this_is_not_abi mount option + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Register SMMU capabilities with MPAM + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Add mpam helpers to query and set + state + - NVIDIA: SAUCE: iommu: Add helpers to get and set the QoS state + - NVIDIA: SAUCE: iommu: Add helpers to retrieve iommu_groups by id or + kobject + - NVIDIA: SAUCE: iommu: Add helper to retrieve iommu kset + - NVIDIA: SAUCE: kobject: Add kset_get_next_obj() to allow a kset to be + walked + - NVIDIA: SAUCE: arm_mpam: resctrl: Add iommu helpers to get/set the + partid and pmg + - NVIDIA: SAUCE: fs/resctrl: Add support for assigning iommu_groups to + resctrl groups + - NVIDIA: SAUCE: firmware: arm_scmi: add MPAM-FB SCMI protocol stub + - NVIDIA: SAUCE: arm_mpam: add MPAM-FB MSC firmware access support + - NVIDIA: SAUCE: arm_mpam: Allow duplicate PCC subspace_ids + - NVIDIA: SAUCE: untested: mpam: Convert pcc_channels list to XArray and + cleanup + - NVIDIA: SAUCE: x86/resctrl: Add stub to allow other architecture to + disable monitor overflow + - NVIDIA: SAUCE: arm_mpam: resctrl: Determine if any exposed counter can + overflow + - NVIDIA: SAUCE: fs/restrl: Allow the overflow handler to be disabled + - NVIDIA: SAUCE: fs/resctrl: Uniform data type of + component_id/domid/id/cache_id + - NVIDIA: SAUCE: arm_mpam: Allow cmax/cmin to be configured + - NVIDIA: SAUCE: arm_mpam: Rename mbw conversion to 'fract16' for code re- + use + - NVIDIA: SAUCE: fs/resctrl: Group all the MBA specific properties in a + separate struct + - NVIDIA: SAUCE: fs/resctrl: Abstract duplicate domain test to a helper + - NVIDIA: SAUCE: fs/resctrl: Move MBA supported check to parse_line() + instead of parse_bw() + - NVIDIA: SAUCE: fs/resctrl: Rename resctrl_get_default_ctrl() to include + resource + - NVIDIA: SAUCE: fs/resctrl: Add a schema format to the schema, allowing + it to be different + - NVIDIA: SAUCE: fs/resctrl: Use schema format to check the resource is a + bitmap + - NVIDIA: SAUCE: fs/resctrl: Add specific schema types for 'range' + - NVIDIA: SAUCE: x86/resctrl: Move over to specifying MBA control formats + - NVIDIA: SAUCE: arm_mpam: resctrl: Convert MB resource to use percentage + - NVIDIA: SAUCE: fs/resctrl: Remove 'range' schema format + - NVIDIA: SAUCE: fs/resctrl: Add additional files for percentage and + bitmap controls + - NVIDIA: SAUCE: fs/resctrl: Add fflags_from_schema() for files based on + schema format + - NVIDIA: SAUCE: fs/resctrl: Expose the schema format to user-space + - NVIDIA: SAUCE: fs/resctrl: Add L2 and L3 'MAX' resource schema + - NVIDIA: SAUCE: arm_mpam: resctrl: Add the glue code to convert to/from + cmax + - NVIDIA: SAUCE: mm,memory_hotplug: Add lockdep assertion helper + - NVIDIA: SAUCE: fs/resctrl: Take memory hotplug lock whenever taking CPU + hotplug lock + - NVIDIA: SAUCE: fs/resctrl: Add mount option for mb_uses_numa_nid and + arch stubs + - NVIDIA: SAUCE: Fix unused variable warning + - NVIDIA: SAUCE: arm_mpam: resctrl: Pick whether MB can use NUMA nid + instead of cache-id + - NVIDIA: SAUCE: arm_mpam: resctrl: Change domain_hdr online/offline to + work with a set of CPUs + - NVIDIA: SAUCE: untested: arm_mpam: resctrl: Split + mpam_resctrl_alloc_domain() to have CPU and node + - NVIDIA: SAUCE: arm_mpam: resctrl: Add NUMA node notifier for domain + online/offline + - NVIDIA: SAUCE: untested: arm_mpam: resctrl: Allow resctrl to enable NUMA + nid as MB domain-id + - NVIDIA: SAUCE: [Config] RESCTRL configs added to annotations + - NVIDIA: SAUCE: arm_mpam: Fix missing SHIFT definitions + - NVIDIA: SAUCE: arm_mpam: resctrl: Fix MPAM kunit + - NVIDIA: SAUCE: resctrl/mpam: Align packed mpam_props to fix arm64 KUnit + alignment fault + - NVIDIA: SAUCE: resctrl/tests: mpam_devices: compare only meaningful + bytes of mpam_props + + * r8127: fix for LTS test panic (LP: #2134991) + - NVIDIA: SAUCE: r8127: Remove registers2 proc entry + + * Add two more Spark iGPU IDs for the existing iommu quirk (LP: #2132033) + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Add two more DGX Spark iGPU IDs for + existing iommu quirk + + * Pull CPPC mailing list patches for Spark (LP: #2131705) + - NVIDIA: SAUCE: ACPI: CPPC: Add cppc_get_perf() API to read performance + controls + - NVIDIA: SAUCE: ACPI: CPPC: extend APIs to support auto_sel and epp + - NVIDIA: SAUCE: ACPI: CPPC: add APIs and sysfs interface for min/max_perf + - NVIDIA: SAUCE: ACPI: CPPC: add APIs and sysfs interface for perf_limited + register + - NVIDIA: SAUCE: cpufreq: CPPC: Add sysfs for min/max_perf and + perf_limited + - NVIDIA: SAUCE: cpufreq: CPPC: update policy min/max when toggling + auto_select + - NVIDIA: SAUCE: cpufreq: CPPC: add autonomous mode boot parameter support + + * r8127: fix kernel panic when dump all registers (LP: #2130445) + - NVIDIA: SAUCE: r8127: fix a kernel panic when dump all registers + - NVIDIA: SAUCE: r8127: add support for RTL8127 cable diagnostic test + + * Set CONFIG_IOMMU_DEFAULT_PASSTHROUGH as default for Nvidia CPUs + (LP: #2129776) + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Set DGX Spark iGPU default domain type + to DMA + - [Config] nvidia: Update annotations to set + CONFIG_IOMMU_DEFAULT_PASSTHROUGH + + * mt7925: Introduce CSA support in non-MLO mode (LP: #2129209) + - NVIDIA: SAUCE: wifi: mt76: mt7925: introduce CSA support in non-MLO mode + + * IOMMU: Support contiguous bit in translation tables (LP: #2112600) + - NVIDIA: SAUCE: iommu/io-pgtable-arm: backport contiguous bit support + + * NVIDIA: SAUCE: MEDIATEK: usb: host: xhci-hub: fix MT89xx SoCs return + PORTLI value (LP: #2125126) + - NVIDIA: SAUCE: MEDIATEK: usb: host: xhci-hub: fix MT89xx SoCs return + PORTLI value + + * NVIDIA: SAUCE: ffa notification count initialization fix (LP: #2123861) + - NVIDIA: SAUCE: Fix FFA notification count initialization + + * Pull-request for setting CPU frequency gov to performance (LP: #2028576) + - [Config] nvidia: Use performance CPU frequency governor on amd64 + + * Set CONFIG_IOMMU_DEFAULT_DMA_LAZY as default for Nvidia CPUs + (LP: #2119661) + - [Config] nvidia: Update annotations to set CONFIG_IOMMU_DEFAULT_DMA_LAZY + + * Backport support for Grace virtualization features: vEVENTQ, HW QUEUE, and + vEGM (LP: #2119656) + - NVIDIA: SAUCE: arm64: configs: Build NVGRACE_GPU_VFIO_PCI as LKM + - NVIDIA: SAUCE: arm64: configs: Enable IOMMUFD and VFIO_DEVICE_CDEV + - NVIDIA: SAUCE: vfio/nvgrace-egm: Introduce module to manage EGM + - NVIDIA: SAUCE: vfio/nvgrace-egm: Handle pages with ECC errors on the EGM + - NVIDIA: SAUCE: arm64: configs: Build CONFIG_NVGRACE_EGM as LKM + - NVIDIA: SAUCE: vfio/nvgrace-egm: Move the egm header file to include + - NVIDIA: SAUCE: vfio/nvgrace-egm: Free region memory during + unregistration + - NVIDIA: SAUCE: vfio/nvgrace-egm: Move region hash initialization + - NVIDIA: SAUCE: vfio/nvgrace-egm: Handle and convey EGM registration + errors + - NVIDIA: SAUCE: vfio/nvgrace-gpu: Handle EGM registration failure + - NVIDIA: SAUCE: vfio/nvgrace-egm: Address sparse errors + - NVIDIA: SAUCE: vfio/nvgrace-gpu: Address smatch errors + - NVIDIA: SAUCE: vfio/nvgrace-egm: Ensure ACPI value reads are successful + - NVIDIA: SAUCE: vfio/nvgrace-egm: Avoid invalid retired pages base + - NVIDIA: SAUCE: vfio/nvgrace-egm: Update EGM unregistration API + - NVIDIA: SAUCE: vfio/nvgrace-egm: track GPUs associated with the EGM + regions + - NVIDIA: SAUCE: vfio/nvgrace-egm: list gpus through sysfs + - NVIDIA: SAUCE: vfio/nvgrace-egm: expose the egm size through sysfs + - NVIDIA: SAUCE: arm64: configs: enable NVGRACE_EGM as module + + * Backport support for arm64 BRBE and a future NVIDIA CPU ID (LP: #2118663) + - [Config] nvidia: Enable BRBE + + * nvidia-ffa-ec: Fix FFH data response length (LP: #2118357) + - NVIDIA: SAUCE: Fix FFH data response length + + * Add pincontrol driver for MT8901 chip (LP: #2117784) + - NVIDIA: SAUCE: MEDIATEK: pinctrl: mediatek: Add gpio-range record in + pinctrl driver + - NVIDIA: SAUCE: MEDIATEK: pinctrl: mediatek: Add acpi support + - NVIDIA: SAUCE: MEDIATEK: pinctrl: mt8901: Add pinctrl driver + - [Config] nvidia: Update annotations to enable CONFIG_PINCTRL_MT8901 + + * NVIDIA: SAUCE: Add FFA and EC Secure Service Driver to -nvidia kernel + (LP: #2114230) + - NVIDIA: SAUCE: Add support for custom ARM FFH offset handler + - NVIDIA: SAUCE: Add nvidia ffa driver for EC communication + - NVIDIA: SAUCE: Add ffa driver for each secure EC service + - NVIDIA: SAUCE: Add support for EC secure service communication + - NVIDIA: SAUCE: Rescan acpi devices that uses secure EC communication + - NVIDIA: SAUCE: irqchip/gic-v3: Allow unused SGIs for drivers/modules + - NVIDIA: SAUCE: Add support for notifications from secure EC services + - [Config] nvidia: Update annotations to enable NVIDIA FFA EC driver + + * Backport: TPM Service Command Response Buffer Interface Over FF-A + (LP: #2111511) + - [Config] nvidia-6.14: Update annotations to enable TPM over FFA + + * Backport: ALSA: hda - Add new driver for HDA controllers listed via ACPI + (LP: #2111447) + - NVIDIA: SAUCE: [Config] nvidia: CONFIG_SND_HDA_ACPI=m on arm64 + + * Pull request to enable GPU passthrough for CUDA (LP: #2095028) + - NVIDIA: SAUCE: WAR: iommufd/pages: Bypass PFNMAP + - NVIDIA: SAUCE: [Config] nvidia: Update annotations for Grace I/O + virtualization + - [Config] nvidia-6.14: Drop CONFIG_TEGRA241_CMDQV from annotations + + * Add Realtek r8127 ethernet driver (LP: #2109730) + - NVIDIA: SAUCE: r8127: Add Realtek r8127 ethernet driver + - NVIDIA: SAUCE: r8127: Remove Realtek r8127 non required files + - NVIDIA: SAUCE: r8127: Moved files from r8127/src to r8127 folder + - NVIDIA: SAUCE: Add r8127 in kernel build + - [Config] nvidia-6.11: Update annotations to enable realtek R8127 module + + * Pull request: Add quirk and disable SBR on Gen5 ports (LP: #2107509) + - NVIDIA: SAUCE: MEDIATEK: usb: host: xhci-plat: support usb3 bulks stream + low power + + * Apply backport of upstream commit to enable Realtek Bluetooth module + (LP: #2096882) + - NVIDIA: SAUCE: Adds MT7925 BT devices + + * Apply SAUCE patch to enable 8250 serial device (LP: #2096888) + - NVIDIA: SAUCE: serial: 8250_mtk: Add ACPI support + + * Backport: "Add support for AArch64 AMUv1-based average freq" Series + (LP: #2100032) + - NVIDIA: [Config] set CONFIG_CPUFREQ_ARCH_CUR_FREQ=y for x86 + + * MANA: include driver fixes and enable module on ARM64 (LP: #2084598) + - [Config] nvidia-6.17: Enable MANA configs on x86 and arm64 + + * Apply patch to set CONFIG_EFI_CAPSULE_LOADER=y for arm64 (LP: #2067111) + - NVIDIA: [Config] EFI: set CAPSULE_LOADER=y for arm64 + + * linux-nvidia-6.5_6.5.0-1014.14 breaks with earlier BIOS release, and + modeset/resolutions are wrong (LP: #2061930) // Blacklist coresight_etm4x + (LP: #2067106) + - [Packaging] blacklist coresight_etm4x + + * backport arm64 THP improvements from 6.9 (LP: #2059316) + - NVIDIA: [Config] arm64: ARM64_CONTPTE=y + + * Reapply the linux-nvidia kernel config options from the 5.15 and 6.5 + kernels (LP: #2060327) + - NVIDIA: [Config]: Disable the NOUVEAU driver which is not used with + -nvidia kernels + - NVIDIA: [Config]: Adding CORESIGHT and ARM64_ERRATUM configs to + annotations + + [ Ubuntu: 7.0.0-6.6 ] + + * resolute/linux: 7.0.0-6.6 -proposed tracker (LP: #2143745) + * Miscellaneous Ubuntu changes + - [Packaging] drop unstable suffix + + [ Ubuntu: 7.0.0-5.5 ] + + * resolute/linux-unstable: 7.0.0-5.5 -proposed tracker (LP: #2143700) + * Resolute real-time patchset: 7.0-rc1-rt1 (LP: #2143181) + - SAUCE: Reapply "serial: 8250: Switch to nbcon console" + - SAUCE: Reapply "serial: 8250: Revert "drop lockdep annotation from + serial8250_clear_IER()"" + - SAUCE: drm/i915: Use preempt_disable/enable_rt() where recommended + - SAUCE: drm/i915: Don't disable interrupts on PREEMPT_RT during atomic + updates + - SAUCE: drm/i915: Disable tracing points on PREEMPT_RT + - SAUCE: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + + spin_lock() + - SAUCE: drm/i915: Drop the irqs_disabled() check + - SAUCE: drm/i915/guc: Consider also RCU depth in busy loop. + - SAUCE: drm/i915: Consider RCU read section as atomic. + - SAUCE: Revert "drm/i915: Depend on !PREEMPT_RT." + - SAUCE: sysfs: Add /sys/kernel/realtime entry + - Real-time patchset 7.0-rc1-rt1 + * Miscellaneous Ubuntu changes + - [Config] rust toolchain version update + + [ Ubuntu-unstable: 7.0.0-4.4 ] + + * resolute/linux-unstable: 7.0.0-4.4 -proposed tracker (LP: #2143123) + * efi: Fix swapped arguments to bsearch() in efi_status_to_*() SAUCE patch + (LP: #2141276) + - SAUCE efi: Fix swapped arguments to bsearch() in efi_status_to_*() + * Plucky preinstalled server fails to boot on rb3gen2 (LP: #2106681) // + Questing preinstalled server fails to boot on sa8775p boards + (LP: #2121347) + - [Config] move more qcom interconnect/pinctrl/gcc options to builtin + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Add llvm-21-dev to build-depends for perf + * Miscellaneous Ubuntu changes + - [Packaging] Add intel-speed-select to linux-tools + - [Packaging] remove stale debian/dkms-versions + - [Packaging] remove stale debian/dkms-versions scripting + + [ Ubuntu-unstable: 7.0.0-3.3 ] + + * resolute/linux-unstable: 7.0.0-3.3 -proposed tracker (LP: #2143020) + * Miscellaneous Ubuntu changes + - [Config] updateconfig after rebase to v7.0-rc2 + - [Config] switch to PREEMPT_LAZY + + [ Ubuntu-unstable: 7.0.0-2.2 ] + + * resolute/linux-unstable: 7.0.0-2.2 -proposed tracker (LP: #2142764) + + [ Ubuntu-unstable: 7.0.0-1.1 ] + + * resolute/linux-unstable: 7.0.0-1.1 -proposed tracker (LP: #2142402) + * Miscellaneous Ubuntu changes + - [packaging] rename to linux-unstable + - [Config] updateconfig after rebase to v7.0-rc1 + - Update Changes.md + - [Packaging] add libbpf-dev to Build-Depends + - [Config] disable AMD_ISP4, FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove zfs FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove evdi FTBFS + - [Config] updateconfig after rebase to v7.0-rc1 + - [Config] update toolchain version + + -- Jacob Martin Thu, 26 Mar 2026 11:14:51 -0500 + +linux-nvidia (6.19.0-1001.1) resolute; urgency=medium + + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Add llvm-21-dev to build-depends for perf + + [ Ubuntu: 6.19.0-6.6 ] + + * resolute/linux: 6.19.0-6.6 -proposed tracker (LP: #2142114) + * Resolute update: v6.19.2 upstream stable release (LP: #2142112) + - Revert "driver core: enforce device_lock for driver_match_device()" + - Linux 6.19.2 + * Resolute update: v6.19.1 upstream stable release (LP: #2142111) + - io_uring/io-wq: add exit-on-idle state + - io_uring: allow io-wq workers to exit when unused + - smb: client: split cached_fid bitfields to avoid shared-byte RMW races + - ksmbd: fix infinite loop caused by next_smb2_rcv_hdr_off reset in error + paths + - ksmbd: add chann_lock to protect ksmbd_chann_list xarray + - smb: server: fix leak of active_num_conn in ksmbd_tcp_new_connection() + - smb: smbdirect: introduce smbdirect_socket.recv_io.credits.available + - smb: smbdirect: introduce smbdirect_socket.send_io.bcredits.* + - smb: server: make use of smbdirect_socket.recv_io.credits.available + - smb: server: let recv_done() queue a refill when the peer is low on + credits + - smb: server: make use of smbdirect_socket.send_io.bcredits + - smb: server: fix last send credit problem causing disconnects + - smb: server: let send_done handle a completion without IB_SEND_SIGNALED + - smb: client: make use of smbdirect_socket.recv_io.credits.available + - smb: client: let recv_done() queue a refill when the peer is low on + credits + - smb: client: let smbd_post_send() make use of request->wr + - smb: client: remove pointless sc->recv_io.credits.count rollback + - smb: client: remove pointless sc->send_io.pending handling in + smbd_post_send_iter() + - smb: client: port and use the wait_for_credits logic used by server + - smb: client: split out smbd_ib_post_send() + - smb: client: introduce and use smbd_{alloc, free}_send_io() + - smb: client: use smbdirect_send_batch processing + - smb: client: make use of smbdirect_socket.send_io.bcredits + - smb: client: fix last send credit problem causing disconnects + - smb: client: let smbd_post_send_negotiate_req() use smbd_post_send() + - smb: client: let send_done handle a completion without IB_SEND_SIGNALED + - driver core: enforce device_lock for driver_match_device() + - Bluetooth: btusb: Add USB ID 7392:e611 for Edimax EW-7611UXB + - ALSA: hda/conexant: Add quirk for HP ZBook Studio G4 + - crypto: iaa - Fix out-of-bounds index in find_empty_iaa_compression_mode + - crypto: octeontx - Fix length check to avoid truncation in + ucode_load_store + - crypto: omap - Allocate OMAP_CRYPTO_FORCE_COPY scatterlists correctly + - crypto: virtio - Add spinlock protection with virtqueue notification + - crypto: virtio - Remove duplicated virtqueue_kick in + virtio_crypto_skcipher_crypt_req + - nilfs2: Fix potential block overflow that cause system hang + - hfs: ensure sb->s_fs_info is always cleaned up + - wifi: rtw88: Fix alignment fault in rtw_core_enable_beacon() + - scsi: qla2xxx: Validate sp before freeing associated memory + - scsi: qla2xxx: Allow recovery for tape devices + - scsi: qla2xxx: Delay module unload while fabric scan in progress + - scsi: qla2xxx: Free sp in error path to fix system crash + - scsi: qla2xxx: Query FW again before proceeding with login + - sched/mmcid: Don't assume CID is CPU owned on mode switch + - bus: fsl-mc: fix use-after-free in driver_override_show() + - erofs: fix UAF issue for file-backed mounts w/ directio option + - xfs: fix UAF in xchk_btree_check_block_owner + - drm/exynos: vidi: use ctx->lock to protect struct vidi_context member + variables related to memory alloc/free + - PCI: endpoint: Avoid creating sub-groups asynchronously + - wifi: rtl8xxxu: fix slab-out-of-bounds in rtl8xxxu_sta_add + - Linux 6.19.1 + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor: fix aa_label_sk_perm to check for RULE_MEDIATES_NET + + -- Jacob Martin Tue, 03 Mar 2026 11:01:18 -0600 + +linux-nvidia (6.19.0-1000.0) resolute; urgency=medium + + * Initial changelog entry. + + -- Jacob Martin Fri, 27 Feb 2026 14:49:42 -0600 + +linux (6.19.0-6.6) resolute; urgency=medium + + * resolute/linux: 6.19.0-6.6 -proposed tracker (LP: #2142114) + + * Resolute update: v6.19.2 upstream stable release (LP: #2142112) + - Revert "driver core: enforce device_lock for driver_match_device()" + - Linux 6.19.2 + + * Resolute update: v6.19.1 upstream stable release (LP: #2142111) + - io_uring/io-wq: add exit-on-idle state + - io_uring: allow io-wq workers to exit when unused + - smb: client: split cached_fid bitfields to avoid shared-byte RMW races + - ksmbd: fix infinite loop caused by next_smb2_rcv_hdr_off reset in error + paths + - ksmbd: add chann_lock to protect ksmbd_chann_list xarray + - smb: server: fix leak of active_num_conn in ksmbd_tcp_new_connection() + - smb: smbdirect: introduce smbdirect_socket.recv_io.credits.available + - smb: smbdirect: introduce smbdirect_socket.send_io.bcredits.* + - smb: server: make use of smbdirect_socket.recv_io.credits.available + - smb: server: let recv_done() queue a refill when the peer is low on + credits + - smb: server: make use of smbdirect_socket.send_io.bcredits + - smb: server: fix last send credit problem causing disconnects + - smb: server: let send_done handle a completion without IB_SEND_SIGNALED + - smb: client: make use of smbdirect_socket.recv_io.credits.available + - smb: client: let recv_done() queue a refill when the peer is low on + credits + - smb: client: let smbd_post_send() make use of request->wr + - smb: client: remove pointless sc->recv_io.credits.count rollback + - smb: client: remove pointless sc->send_io.pending handling in + smbd_post_send_iter() + - smb: client: port and use the wait_for_credits logic used by server + - smb: client: split out smbd_ib_post_send() + - smb: client: introduce and use smbd_{alloc, free}_send_io() + - smb: client: use smbdirect_send_batch processing + - smb: client: make use of smbdirect_socket.send_io.bcredits + - smb: client: fix last send credit problem causing disconnects + - smb: client: let smbd_post_send_negotiate_req() use smbd_post_send() + - smb: client: let send_done handle a completion without IB_SEND_SIGNALED + - driver core: enforce device_lock for driver_match_device() + - Bluetooth: btusb: Add USB ID 7392:e611 for Edimax EW-7611UXB + - ALSA: hda/conexant: Add quirk for HP ZBook Studio G4 + - crypto: iaa - Fix out-of-bounds index in find_empty_iaa_compression_mode + - crypto: octeontx - Fix length check to avoid truncation in + ucode_load_store + - crypto: omap - Allocate OMAP_CRYPTO_FORCE_COPY scatterlists correctly + - crypto: virtio - Add spinlock protection with virtqueue notification + - crypto: virtio - Remove duplicated virtqueue_kick in + virtio_crypto_skcipher_crypt_req + - nilfs2: Fix potential block overflow that cause system hang + - hfs: ensure sb->s_fs_info is always cleaned up + - wifi: rtw88: Fix alignment fault in rtw_core_enable_beacon() + - scsi: qla2xxx: Validate sp before freeing associated memory + - scsi: qla2xxx: Allow recovery for tape devices + - scsi: qla2xxx: Delay module unload while fabric scan in progress + - scsi: qla2xxx: Free sp in error path to fix system crash + - scsi: qla2xxx: Query FW again before proceeding with login + - sched/mmcid: Don't assume CID is CPU owned on mode switch + - bus: fsl-mc: fix use-after-free in driver_override_show() + - erofs: fix UAF issue for file-backed mounts w/ directio option + - xfs: fix UAF in xchk_btree_check_block_owner + - drm/exynos: vidi: use ctx->lock to protect struct vidi_context member + variables related to memory alloc/free + - PCI: endpoint: Avoid creating sub-groups asynchronously + - wifi: rtl8xxxu: fix slab-out-of-bounds in rtl8xxxu_sta_add + - Linux 6.19.1 + + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor: fix aa_label_sk_perm to check for RULE_MEDIATES_NET + + -- Timo Aaltonen Wed, 18 Feb 2026 14:31:48 +0200 --- linux-nvidia-7.0.0.orig/debian.nvidia/config/README.rst +++ linux-nvidia-7.0.0/debian.nvidia/config/README.rst @@ -0,0 +1,185 @@ +================== +Config Annotations +================== + +:Author: Andrea Righi + +Overview +======== + +Each Ubuntu kernel needs to maintain its own .config for each supported +architecture and each flavour. + +Every time a new patch is applied or a kernel is rebased on top of a new +one, we need to update the .config's accordingly (config options can be +added, removed and also renamed). + +So, we need to make sure that some critical config options are always +matching the desired value in order to have a functional kernel. + +State of the art +================ + +At the moment configs are maintained as a set of Kconfig chunks (inside +`debian./config/`): a global one, plus per-arch / per-flavour +chunks. + +In addition to that, we need to maintain also a file called +'annotations'; the purpose of this file is to make sure that some +critical config options are not silently removed or changed when the +real .config is re-generated (for example after a rebase or after +applying a new set of patches). + +The main problem with this approach is that, often, we have duplicate +information that is stored both in the Kconfig chunks *and* in the +annotations files and, at the same time, the whole .config's information +is distributed between Kconfig chunks and annotations, making it hard to +maintain, review and manage in general. + +Proposed solution +================= + +The proposed solution is to store all the config information into the +"annotations" format and get rid of the config chunks (basically the +real .config's can be produced "compiling" annotations). + +Implementation +============== + +To help the management of the annotations an helper script is provided +(`debian/scripts/misc/annotations`): + +``` +usage: annotations [-h] [--version] [--file FILE] [--arch ARCH] [--flavour FLAVOUR] [--config CONFIG] + (--query | --export | --import FILE | --update FILE | --check FILE) + +Manage Ubuntu kernel .config and annotations + +options: + -h, --help show this help message and exit + --version, -v show program's version number and exit + --file FILE, -f FILE Pass annotations or .config file to be parsed + --arch ARCH, -a ARCH Select architecture + --flavour FLAVOUR, -l FLAVOUR + Select flavour (default is "generic") + --config CONFIG, -c CONFIG + Select a specific config option + +Action: + --query, -q Query annotations + --export, -e Convert annotations to .config format + --import FILE, -i FILE + Import a full .config for a specific arch and flavour into annotations + --update FILE, -u FILE + Import a partial .config into annotations (only resync configs specified in FILE) + --check FILE, -k FILE + Validate kernel .config with annotations +``` + +This script allows to query config settings (per arch/flavour/config), +export them into the Kconfig format (generating the real .config files) +and check if the final .config matches the rules defined in the +annotations. + +Examples (annotations is defined as an alias to `debian/scripts/annotations`): + + - Show settings for `CONFIG_DEBUG_INFO_BTF` for master kernel across all the + supported architectures and flavours: + +``` +$ annotations --query --config CONFIG_DEBUG_INFO_BTF +{ + "policy": { + "amd64": "y", + "arm64": "y", + "armhf": "n", + "ppc64el": "y", + "riscv64": "y", + "s390x": "y" + }, + "note": "'Needs newer pahole for armhf'" +} +``` + + - Dump kernel .config for arm64 and flavour generic-64k: + +``` +$ annotations --arch arm64 --flavour generic-64k --export +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_COMPAT=y +... +``` + + - Update annotations file with a new kernel .config for amd64 flavour + generic: + +``` +$ annotations --arch amd64 --flavour generic --import build/.config +``` + +Moreover, an additional kernelconfig commands are provided +(via debian/rules targets): + - `migrateconfigs`: automatically merge all the previous configs into + annotations (local changes still need to be committed) + +Annotations headers +=================== + +The main annotations file should contain a header to define the architectures +and flavours that are supported. + +Here is the format of the header for the generic kernel: +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 armhf ppc64el riscv64 s390x +# FLAVOUR: amd64-generic arm64-generic arm64-generic-64k armhf-generic armhf-generic-lpae ppc64el-generic riscv64-generic s390x-generic + +``` + +Example header of a derivative (linux-aws): +``` +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 +# FLAVOUR: amd64-aws arm64-aws +# FLAVOUR_DEP: {'amd64-aws': 'amd64-generic', 'arm64-aws': 'arm64-generic'} + +include "../../debian.master/config/annotations" + +# Below you can define only the specific linux-aws configs that differ from linux generic + +``` + +Pros and Cons +============= + + Pros: + - avoid duplicate information in .config's and annotations + - allow to easily define groups of config settings (for a specific + environment or feature, such as annotations.clouds, annotations.ubuntu, + annotations.snapd, etc.) + - config options are more accessible, easy to change and review + - we can easily document how config options are managed (and external + contributors won't be discouraged anymore when they need to to change a + config option) + + Cons: + - potential regressions: the new tool/scripts can have potential bugs, + so we could experience regressions due to some missed config changes + - kernel team need to understand the new process (even if everything + is transparent, kernel cranking process is the same, there might be + corner cases that need to be addressed and resolved manually) + +TODO +==== + + - Migrate all flavour and arch definitions into annotations (rather + than having this information defined in multiple places inside + debian/scripts); right now this information is "partially" migrated, + meaning that we need to define arches and flavours in the headers + section of annotations (so that the annotations tool can figure out + the list of supported arches and flavours), but arches and flavours + are still defined elsewhere, ideally we would like to have arches and + flavours defined only in one place: annotations. --- linux-nvidia-7.0.0.orig/debian.nvidia/config/annotations +++ linux-nvidia-7.0.0/debian.nvidia/config/annotations @@ -0,0 +1,292 @@ +# Menu: HEADER +# FORMAT: 4 +# ARCH: amd64 arm64 +# FLAVOUR: amd64-nvidia arm64-nvidia arm64-nvidia-64k +# FLAVOUR_DEP: {'amd64-nvidia': 'amd64-generic', 'arm64-nvidia': 'arm64-generic', 'arm64-nvidia-64k': 'arm64-generic-64k'} + +include "../../debian.master/config/annotations" + +CONFIG_ACPI_MPAM policy<{'amd64': '-', 'arm64': 'y'}> +CONFIG_ACPI_MPAM note<'LP: #2122432'> + +CONFIG_AMPERE_ERRATUM_AC04_CPU_23 policy<{'arm64': 'y'}> +CONFIG_AMPERE_ERRATUM_AC04_CPU_23 note<'LP: #2122432'> + +CONFIG_ARCH_HAS_CPU_RESCTRL policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_ARCH_HAS_CPU_RESCTRL note<'LP: #2122432'> + +CONFIG_ARM64_BRBE policy<{'arm64': 'y'}> +CONFIG_ARM64_BRBE note<'LP: #2118663'> + +CONFIG_ARM64_CONTPTE policy<{'arm64': 'y'}> +CONFIG_ARM64_CONTPTE note<'LP: #2059316'> + +CONFIG_ARM64_ERRATUM_1902691 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_1902691 note<'Required for Grace enablement'> + +CONFIG_ARM64_ERRATUM_2038923 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2038923 note<'Required for Grace enablement'> + +CONFIG_ARM64_ERRATUM_2064142 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2064142 note<'Required for Grace enablement'> + +CONFIG_ARM64_ERRATUM_2119858 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2119858 note<'Required for Grace enablement'> + +CONFIG_ARM64_ERRATUM_2139208 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2139208 note<'Required for Grace enablement'> + +CONFIG_ARM64_ERRATUM_2224489 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2224489 note<'Required for Grace enablement'> + +CONFIG_ARM64_ERRATUM_2253138 policy<{'arm64': 'y'}> +CONFIG_ARM64_ERRATUM_2253138 note<'Required for Grace enablement'> + +CONFIG_ARM64_MPAM policy<{'amd64': '-', 'arm64': 'y'}> +CONFIG_ARM64_MPAM note<'LP: #2122432'> + +CONFIG_ARM64_MPAM_DRIVER policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM_DRIVER note<'LP: #2122432'> + +CONFIG_ARM64_MPAM_DRIVER_DEBUG policy<{'amd64': '-', 'arm64': 'n'}> +CONFIG_ARM64_MPAM_DRIVER_DEBUG note<'LP: #2122432'> + +CONFIG_ARM64_MPAM_RESCTRL_FS policy<{'arm64': 'y'}> +CONFIG_ARM64_MPAM_RESCTRL_FS note<'LP: #2122432'> + +CONFIG_ARM64_SME policy<{'arm64': 'y'}> +CONFIG_ARM64_SME note<'LP: #2122432'> + +CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE note<'Required for Grace enablement'> + +CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE policy<{'arm64': 'y'}> +CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE note<'Required for Grace enablement'> + +CONFIG_ARM_CPU_RESCTRL policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_ARM_CPU_RESCTRL note<'LP: #2122432'> + +CONFIG_ARM_FFA_TRANSPORT policy<{'arm64': 'y'}> +CONFIG_ARM_FFA_TRANSPORT note<'LP: #2111511'> + +CONFIG_ARM_SMMU_V3_IOMMUFD policy<{'arm64': 'y'}> +CONFIG_ARM_SMMU_V3_IOMMUFD note<'LP: #2095028'> + +CONFIG_BATTERY_HUAWEI_GAOKUN policy<{'arm64': '-'}> +CONFIG_BATTERY_HUAWEI_GAOKUN note<'LP: #2122432'> + +CONFIG_CMA_SIZE_MBYTES policy<{'amd64': '0', 'arm64': '32', 'arm64-nvidia': '128', 'arm64-nvidia-64k': '1024'}> +CONFIG_CMA_SIZE_MBYTES note<'LP: #2095028'> + +CONFIG_CORESIGHT policy<{'arm64': 'm'}> +CONFIG_CORESIGHT note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_CATU policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_CATU note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_CPU_DEBUG policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_CPU_DEBUG note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_CPU_DEBUG_DEFAULT_ON policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_CPU_DEBUG_DEFAULT_ON note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_CTCU policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_CTCU note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_CTI policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_CTI note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_CTI_INTEGRATION_REGS policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_CTI_INTEGRATION_REGS note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_DUMMY policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_DUMMY note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_LINKS_AND_SINKS policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_LINKS_AND_SINKS note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_LINK_AND_SINK_TMC policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_LINK_AND_SINK_TMC note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_SINK_ETBV10 policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_SINK_ETBV10 note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_SINK_TPIU policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_SINK_TPIU note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_SOURCE_ETM4X policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_SOURCE_ETM4X note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_STM policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_STM note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_TNOC policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_TNOC note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_TPDA policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_TPDA note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_TPDM policy<{'arm64': 'n'}> +CONFIG_CORESIGHT_TPDM note<'Required for Grace enablement'> + +CONFIG_CORESIGHT_TRBE policy<{'arm64': 'm'}> +CONFIG_CORESIGHT_TRBE note<'Required for Grace enablement'> + +CONFIG_CPUFREQ_ARCH_CUR_FREQ policy<{'amd64': 'y'}> +CONFIG_CPUFREQ_ARCH_CUR_FREQ note<'LP: #2100032'> + +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND policy<{'arm64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND note<'LP: #2028576: Perf governor required for NVIDIA workloads'> + +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE note<'LP: #2028576: Perf governor required for NVIDIA workloads'> + +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL note<'LP: #2028576: Perf governor required for NVIDIA workloads'> + +CONFIG_DRM_NOUVEAU policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_DRM_NOUVEAU note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_DRM_NOUVEAU_BACKLIGHT policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_DRM_NOUVEAU_BACKLIGHT note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_DRM_NOUVEAU_CH7006 policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_DRM_NOUVEAU_CH7006 note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_DRM_NOUVEAU_SIL164 policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_DRM_NOUVEAU_SIL164 note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_DRM_NOUVEAU_SVM policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_DRM_NOUVEAU_SVM note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_EC_HUAWEI_GAOKUN policy<{'arm64': 'n'}> +CONFIG_EC_HUAWEI_GAOKUN note<'LP: #2122432'> + +CONFIG_EFI_CAPSULE_LOADER policy<{'amd64': 'm', 'arm64': 'y'}> +CONFIG_EFI_CAPSULE_LOADER note<'LP: #2067111'> + +CONFIG_ETM4X_IMPDEF_FEATURE policy<{'arm64': 'n'}> +CONFIG_ETM4X_IMPDEF_FEATURE note<'Required for Grace enablement'> + +CONFIG_FTRACE_SORT_STARTUP_TEST policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_FTRACE_SORT_STARTUP_TEST note<'LP: #2122432'> + +CONFIG_GPIO_AAEON policy<{'amd64': '-'}> +CONFIG_GPIO_AAEON note<'Disable all Ubuntu ODM drivers'> + +CONFIG_IOMMUFD_VFIO_CONTAINER policy<{'arm64': 'y'}> +CONFIG_IOMMUFD_VFIO_CONTAINER note<'LP: #2095028'> + +CONFIG_IOMMU_DEFAULT_DMA_LAZY policy<{'amd64': 'y', 'arm64': 'n'}> +CONFIG_IOMMU_DEFAULT_DMA_LAZY note<'On Nvidia CPU passthrough mode is recommend so set passthrough mode as default for better performance'> + +CONFIG_IOMMU_DEFAULT_DMA_STRICT policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_IOMMU_DEFAULT_DMA_STRICT note<'On Nvidia CPU passthrough mode is recommend so set passthrough mode as default for better performance'> + +CONFIG_IOMMU_DEFAULT_PASSTHROUGH policy<{'amd64': 'n', 'arm64': 'y'}> +CONFIG_IOMMU_DEFAULT_PASSTHROUGH note<'On Nvidia CPU passthrough mode is recommend so set passthrough mode as default for better performance'> + +CONFIG_LEDS_AAEON policy<{'amd64': '-'}> +CONFIG_LEDS_AAEON note<'Disable all Ubuntu ODM drivers'> + +CONFIG_MANA_INFINIBAND policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MANA_INFINIBAND note<'LP: #2084598'> + +CONFIG_MFD_AAEON policy<{'amd64': '-'}> +CONFIG_MFD_AAEON note<'Disable all Ubuntu ODM drivers'> + +CONFIG_MICROSOFT_MANA policy<{'amd64': 'm', 'arm64': 'm'}> +CONFIG_MICROSOFT_MANA note<'LP: #2084598'> + +CONFIG_MTD policy<{'amd64': 'm', 'arm64': 'y'}> +CONFIG_MTD note<'Essential for boot on ARM64'> + +CONFIG_MTK_PCIE_HOTPLUG policy<{'arm64': 'm'}> +CONFIG_MTK_PCIE_HOTPLUG note<'CX7 PCIe hotplug driver for NVIDIA DGX Spark systems with GB10 SoC.'> + +CONFIG_NOUVEAU_DEBUG policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_NOUVEAU_DEBUG note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_NOUVEAU_DEBUG_DEFAULT policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_NOUVEAU_DEBUG_DEFAULT note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_NOUVEAU_DEBUG_MMU policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_NOUVEAU_DEBUG_MMU note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_NOUVEAU_DEBUG_PUSH policy<{'amd64': '-', 'arm64': '-'}> +CONFIG_NOUVEAU_DEBUG_PUSH note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_NOUVEAU_PLATFORM_DRIVER policy<{'arm64': '-'}> +CONFIG_NOUVEAU_PLATFORM_DRIVER note<'Disable nouveau for NVIDIA kernels'> + +CONFIG_NR_CPUS policy<{'amd64': '8192', 'arm64': '512'}> +CONFIG_NR_CPUS note<'LP: #1864198'> + +CONFIG_NVGRACE_EGM policy<{'arm64': 'm'}> +CONFIG_NVGRACE_EGM note<'LP: #2119656'> + +CONFIG_NVIDIA_FFA_EC policy<{'arm64': 'y'}> +CONFIG_NVIDIA_FFA_EC note<'LP: #2114230'> + +CONFIG_PID_IN_CONTEXTIDR policy<{'arm64': 'y'}> +CONFIG_PID_IN_CONTEXTIDR note<'Required for Grace enablement'> + +CONFIG_PINCTRL_MT8901 policy<{'arm64': 'y'}> +CONFIG_PINCTRL_MT8901 note<'LP: #2117784'> + +CONFIG_PROC_CPU_RESCTRL policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_PROC_CPU_RESCTRL note<'LP: #2122432'> + +CONFIG_R8127 policy<{'amd64': 'n', 'arm64': 'm'}> +CONFIG_R8127 note<'LP: #2109730'> + +CONFIG_RESCTRL_FS policy<{'amd64': 'y', 'arm64': 'y'}> +CONFIG_RESCTRL_FS note<'LP: #2122432'> + +CONFIG_RESCTRL_FS_PSEUDO_LOCK policy<{'amd64': 'y', 'arm64': '-'}> +CONFIG_RESCTRL_FS_PSEUDO_LOCK note<'LP: #2122432'> + +CONFIG_RESCTRL_IOMMU policy<{'amd64': '-', 'arm64': 'y'}> +CONFIG_RESCTRL_IOMMU note<'LP: #2122432'> + +CONFIG_RESCTRL_RMID_DEPENDS_ON_CLOSID policy<{'amd64': '-', 'arm64': 'y'}> +CONFIG_RESCTRL_RMID_DEPENDS_ON_CLOSID note<'LP: #2122432'> + +CONFIG_SAMPLE_CORESIGHT_SYSCFG policy<{'arm64': 'n'}> +CONFIG_SAMPLE_CORESIGHT_SYSCFG note<'Required for Grace enablement'> + +CONFIG_SENSORS_AAEON policy<{'amd64': '-'}> +CONFIG_SENSORS_AAEON note<'Disable all Ubuntu ODM drivers'> + +CONFIG_SND_HDA_ACPI policy<{'amd64': 'n', 'arm64': 'm'}> +CONFIG_SND_HDA_ACPI note<'Add support for ACPI-enumerated HDA'> + +CONFIG_SPI_TEGRA210_QUAD policy<{'arm64': 'y'}> +CONFIG_SPI_TEGRA210_QUAD note<'Ensures the TPM is available before the IMA driver initializes'> + +CONFIG_TCG_ARM_CRB_FFA policy<{'arm64': 'y'}> +CONFIG_TCG_ARM_CRB_FFA note<'LP: #2111511'> + +CONFIG_TCG_TIS_SPI policy<{'amd64': 'm', 'arm64': 'y'}> +CONFIG_TCG_TIS_SPI note<'Ensures the TPM is available before the IMA driver initializes'> + +CONFIG_UBUNTU_ODM_DRIVERS policy<{'amd64': 'n', 'arm64': 'n'}> +CONFIG_UBUNTU_ODM_DRIVERS note<'Disable all Ubuntu ODM drivers'> + +CONFIG_UCSI_HUAWEI_GAOKUN policy<{'arm64': '-'}> +CONFIG_UCSI_HUAWEI_GAOKUN note<'LP: #2122432'> + +CONFIG_ULTRASOC_SMB policy<{'arm64': 'n'}> +CONFIG_ULTRASOC_SMB note<'Required for Grace enablement'> + +CONFIG_VFIO_CONTAINER policy<{'amd64': 'y', 'arm64': 'n'}> +CONFIG_VFIO_CONTAINER note<'LP: #2095028'> + +CONFIG_VFIO_IOMMU_TYPE1 policy<{'amd64': 'm', 'arm64': '-'}> +CONFIG_VFIO_IOMMU_TYPE1 note<'LP: #2095028'> + + +# ---- Annotations without notes ---- + +CONFIG_BCH policy<{'amd64': 'm', 'arm64': 'y'}> +CONFIG_MTD_NAND_CORE policy<{'amd64': 'm', 'arm64': 'y'}> --- linux-nvidia-7.0.0.orig/debian.nvidia/control.d/flavour-control.stub +++ linux-nvidia-7.0.0/debian.nvidia/control.d/flavour-control.stub @@ -0,0 +1,87 @@ +# Items that get replaced: +# FLAVOUR +# ARCH +# SUPPORTED +# TARGET +# BOOTLOADER +# =PROVIDES= +# +# Items marked with =FOO= are optional +# +# This file describes the template for packages that are created for each flavour +# in debian/control.d/vars.* +# +# This file gets edited in a couple of places. See the debian/control.stub rule in +# debian/rules. PGGVER, ABINUM, and SRCPKGNAME are all converted in the +# process of creating debian/control. +# +# The flavour specific strings (ARCH, etc) are converted using values from the various +# flavour files in debian/control.d/vars.* +# +# XXX: Leave the blank line before the first package!! + +Package: linux-modules-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, wireless-regdb +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel modules for version PKGVER + Contains the corresponding System.map file, the modules built by the + packager, and scripts that try to ensure that the system is not left in an + unbootable state after an update. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-headers-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-headers-PKGVER-ABINUM, ${shlibs:Depends} +Provides: linux-headers, linux-headers-3.0 +Description: Linux kernel headers for version PKGVER + This package provides kernel header files for version PKGVER. + . + This is for sites that want the latest kernel headers. Please read + /usr/share/doc/linux-headers-PKGVER-ABINUM/debian.README.gz for details. + +Package: linux-lib-rust-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: amd64 +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Rust library files related to Linux kernel version PKGVER + This package provides kernel library files for version PKGVER, that allow to + compile out-of-tree kernel modules written in Rust. + +Package: linux-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-tools-PKGVER-ABINUM +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as x86_energy_perf_policy) for + version PKGVER-ABINUM. + +Package: linux-cloud-tools-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends}, SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud for version PKGVER-ABINUM. + --- linux-nvidia-7.0.0.orig/debian.nvidia/control.d/flavour-signed-control.stub +++ linux-nvidia-7.0.0/debian.nvidia/control.d/flavour-signed-control.stub @@ -0,0 +1,38 @@ +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Provides: linux-image, fuse-module, =PROVIDES=${linux:rprovides} +Depends: ${misc:Depends}, ${shlibs:Depends}, kmod, linux-base (>= 4.5ubuntu1~16.04.1), linux-modules-PKGVER-ABINUM-FLAVOUR +Recommends: BOOTLOADER, dracut | linux-initramfs-tool +Breaks: flash-kernel (<< 3.90ubuntu2) [arm64 armhf], s390-tools (<< 2.3.0-0ubuntu3) [s390x] +Conflicts: linux-image=SIGN-PEER-PKG=-PKGVER-ABINUM-FLAVOUR +Suggests: bpftool, linux-perf, SRCPKGNAME-tools, linux-headers-PKGVER-ABINUM-FLAVOUR +Description: Linux kernel image for version PKGVER + This package contains the=SIGN-ME-TXT= Linux kernel image for version PKGVER. + . + Supports SUPPORTED processors. + . + TARGET + . + You likely do not want to install this package directly. Instead, install + the linux-FLAVOUR meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-image=SIGN-ME-PKG=-PKGVER-ABINUM-FLAVOUR-dbgsym +Build-Profiles: +Architecture: ARCH +Section: devel +Priority: optional +Depends: ${misc:Depends} +Provides: linux-debug +Description: Linux kernel debug image for version PKGVER + This package provides the=SIGN-ME-TXT= kernel debug image for version PKGVER. + . + This is for sites that wish to debug the kernel. + . + The kernel image contained in this package is NOT meant to boot from. It + is uncompressed, and unstripped. This package also includes the + unstripped modules. + --- linux-nvidia-7.0.0.orig/debian.nvidia/control.d/vars.nvidia +++ linux-nvidia-7.0.0/debian.nvidia/control.d/vars.nvidia @@ -0,0 +1,5 @@ +arch="amd64 arm64" +supported="NVIDIA" +target="Intended for NVIDIA platforms" +bootloader="grub-pc [amd64] | grub-efi-amd64 [amd64] | grub-efi-ia32 [amd64] | grub [amd64] | lilo [amd64] | flash-kernel [armhf arm64] | grub-efi-arm64 [arm64] | grub-efi-arm [armhf] | grub-ieee1275 [ppc64el]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules, virtualbox-guest-modules [amd64]" --- linux-nvidia-7.0.0.orig/debian.nvidia/control.d/vars.nvidia-64k +++ linux-nvidia-7.0.0/debian.nvidia/control.d/vars.nvidia-64k @@ -0,0 +1,5 @@ +arch="arm64" +supported="NVIDIA 64K pages" +target="Intended for NVIDIA systems" +bootloader="grub-efi-arm64 [arm64] | flash-kernel [arm64]" +provides="kvm-api-4, redhat-cluster-modules, ivtv-modules" --- linux-nvidia-7.0.0.orig/debian.nvidia/control.stub.in +++ linux-nvidia-7.0.0/debian.nvidia/control.stub.in @@ -0,0 +1,105 @@ +Source: SRCPKGNAME +Section: devel +Priority: optional +Maintainer: Ubuntu Kernel Team +Rules-Requires-Root: no +Standards-Version: 3.9.4.0 +Build-Depends: + autoconf , + automake , + bc , + bindgen:native [amd64 arm64], + bison , + clang-21:native [amd64 arm64], + cpio, + curl , + debhelper-compat (= 10), + default-jdk-headless:native , + dkms , + flex , + gawk , + java-common , + kmod , + libaudit-dev , + libbpf-dev , + libcap-dev , + libdebuginfod-dev [amd64 arm64] , + libdw-dev , + libelf-dev , + libiberty-dev , + liblzma-dev , + libnewt-dev , + libnl-3-dev, + libnl-genl-3-dev, + libnuma-dev [amd64 arm64] , + libpci-dev , + libssl-dev , + libstdc++-dev, + libtool , + libtraceevent-dev [amd64 arm64] , + libtracefs-dev [amd64 arm64] , + libudev-dev , + libunwind8-dev [amd64 arm64] , + llvm-21-dev, + makedumpfile:native [amd64] , + openssl , + pahole (>= 1.29-2ubuntu2) [amd64 arm64] | dwarves (>= 1.21) [amd64 arm64] , + pkg-config , + python3:native , + python3-dev:native , + libpython3-dev , + python3-setuptools, + rsync [!i386] , + rust-src:native [amd64 arm64], + rustc:native (>= 1.82) [amd64 arm64], + rustfmt:native [amd64 arm64], + uuid-dev , + zstd , + bpftool:native [amd64 arm64] , + nvidia-dkms-580-open [amd64 arm64] , + nvidia-kernel-source-580-open [amd64 arm64] , + libopencsd-dev [arm64] , +Build-Depends-Indep: + asciidoc , + bzip2 , + python3-docutils , + sharutils , + xmlto , +Vcs-Git: git://git.launchpad.net/~canonical-kernel/ubuntu/+source/linux-nvidia/+git/=SERIES= +XS-Testsuite: autopkgtest +#XS-Testsuite-Depends: gcc-4.7 binutils + +Package: SRCPKGNAME-headers-PKGVER-ABINUM +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Header files related to Linux kernel version PKGVER + This package provides kernel header files for version PKGVER, for sites + that want the latest kernel headers. Please read + /usr/share/doc/SRCPKGNAME-headers-PKGVER-ABINUM/debian.README.gz for details + +Package: SRCPKGNAME-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-tools-common +Description: Linux kernel version specific tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version PKGVER-ABINUM. + You probably want to install linux-tools-PKGVER-ABINUM-. + +Package: SRCPKGNAME-cloud-tools-PKGVER-ABINUM +Build-Profiles: +Architecture: amd64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-cloud-tools-common +Description: Linux kernel version specific cloud tools for version PKGVER-ABINUM + This package provides the architecture dependant parts for kernel + version locked tools for cloud tools for version PKGVER-ABINUM. + You probably want to install linux-cloud-tools-PKGVER-ABINUM-. --- linux-nvidia-7.0.0.orig/debian.nvidia/dkms-versions +++ linux-nvidia-7.0.0/debian.nvidia/dkms-versions @@ -0,0 +1,2 @@ +zfs-linux 2.4.1-1ubuntu1 modulename=zfs debpath=pool/universe/z/%package%/zfs-dkms_%version%_all.deb arch=amd64 arch=arm64 arch=ppc64el arch=riscv64 arch=s390x rprovides=spl-modules rprovides=spl-dkms rprovides=zfs-modules rprovides=zfs-dkms off_series=true +v4l2loopback 0.15.3-1ubuntu2 modulename=v4l2loopback debpath=pool/universe/v/%package%/v4l2loopback-dkms_%version%_all.deb arch=amd64 rprovides=v4l2loopback-modules rprovides=v4l2loopback-dkms off_series=true --- linux-nvidia-7.0.0.orig/debian.nvidia/etc/update.conf +++ linux-nvidia-7.0.0/debian.nvidia/etc/update.conf @@ -0,0 +1,7 @@ +# WARNING: we do not create update.conf when we are not a +# derivative. Various cranky components make use of this. +# If we start unconditionally creating update.conf we need +# to fix at least cranky close and cranky rebase. +RELEASE_REPO=git://git.launchpad.net/~ubuntu-kernel/ubuntu/+source/linux/+git/resolute +SOURCE_RELEASE_BRANCH=master-next +DEBIAN_MASTER=debian.master --- linux-nvidia-7.0.0.orig/debian.nvidia/modprobe.d/common.conf +++ linux-nvidia-7.0.0/debian.nvidia/modprobe.d/common.conf @@ -0,0 +1,4 @@ +# LP:1434842 -- disable OSS drivers by default to allow pulseaudio to emulate +blacklist snd-mixer-oss +blacklist snd-pcm-oss +blacklist coresight_etm4x --- linux-nvidia-7.0.0.orig/debian.nvidia/reconstruct +++ linux-nvidia-7.0.0/debian.nvidia/reconstruct @@ -0,0 +1,45 @@ +# Recreate any symlinks created since the orig. +[ ! -L 'ubuntu/igh-ecat/master/rtdm-ioctl.c' ] && ln -sf 'ioctl.c' 'ubuntu/igh-ecat/master/rtdm-ioctl.c' +chmod +x 'debian/cloud-tools/hv_get_dhcp_info' +chmod +x 'debian/cloud-tools/hv_get_dns_info' +chmod +x 'debian/cloud-tools/hv_set_ifconfig' +chmod +x 'debian/rules' +chmod +x 'debian/scripts/checks/final-checks' +chmod +x 'debian/scripts/checks/module-signature-check' +chmod +x 'debian/scripts/control-create' +chmod +x 'debian/scripts/dkms-build' +chmod +x 'debian/scripts/dkms-build--nvidia-N' +chmod +x 'debian/scripts/dkms-build-configure--zfs' +chmod +x 'debian/scripts/file-downloader' +chmod +x 'debian/scripts/link-headers' +chmod +x 'debian/scripts/link-lib-rust' +chmod +x 'debian/scripts/misc/annotations' +chmod +x 'debian/scripts/misc/find-missing-sauce.sh' +chmod +x 'debian/scripts/misc/gen-auto-reconstruct' +chmod +x 'debian/scripts/misc/git-ubuntu-log' +chmod +x 'debian/scripts/misc/insert-changes' +chmod +x 'debian/scripts/misc/insert-ubuntu-changes' +chmod +x 'debian/scripts/misc/kernelconfig' +chmod +x 'debian/scripts/sign-module' +chmod +x 'debian/templates/extra.postinst.in' +chmod +x 'debian/templates/extra.postrm.in' +chmod +x 'debian/templates/headers.postinst.in' +chmod +x 'debian/templates/image.postinst.in' +chmod +x 'debian/templates/image.postrm.in' +chmod +x 'debian/templates/image.preinst.in' +chmod +x 'debian/templates/image.prerm.in' +chmod +x 'debian/tests/rebuild' +chmod +x 'debian/tests/ubuntu-regression-suite' +chmod +x 'drivers/net/ethernet/realtek/r8127/Makefile' +chmod +x 'drivers/net/ethernet/realtek/r8127/r8127.h' +chmod +x 'drivers/net/ethernet/realtek/r8127/r8127_dash.h' +chmod +x 'drivers/net/ethernet/realtek/r8127/r8127_firmware.h' +chmod +x 'drivers/net/ethernet/realtek/r8127/r8127_n.c' +chmod +x 'drivers/net/ethernet/realtek/r8127/r8127_realwow.h' +chmod +x 'drivers/net/ethernet/realtek/r8127/r8127_rss.h' +chmod +x 'drivers/net/ethernet/realtek/r8127/rtl_eeprom.c' +chmod +x 'drivers/net/ethernet/realtek/r8127/rtl_eeprom.h' +chmod +x 'drivers/net/ethernet/realtek/r8127/rtltool.c' +chmod +x 'drivers/net/ethernet/realtek/r8127/rtltool.h' +# Remove any files deleted from the orig. +exit 0 --- linux-nvidia-7.0.0.orig/debian.nvidia/rules.d/amd64.mk +++ linux-nvidia-7.0.0/debian.nvidia/rules.d/amd64.mk @@ -0,0 +1,20 @@ +build_arch = x86 +defconfig = defconfig +flavours = nvidia +build_image = bzImage +kernel_file = arch/$(build_arch)/boot/bzImage +install_file = vmlinuz +vdso = vdso_install +no_dumpfile = true +uefi_signed = true +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_x86 = true +do_tools_hyperv = false +do_tools_rtla = true +do_tools_acpidbg = true +do_lib_rust = false --- linux-nvidia-7.0.0.orig/debian.nvidia/rules.d/arm64.mk +++ linux-nvidia-7.0.0/debian.nvidia/rules.d/arm64.mk @@ -0,0 +1,20 @@ +build_arch = arm64 +defconfig = defconfig +flavours = nvidia nvidia-64k +build_image = vmlinuz.efi +kernel_file = arch/$(build_arch)/boot/vmlinuz.efi +install_file = vmlinuz +no_dumpfile = true +uefi_signed = true + +vdso = vdso_install + +do_tools_usbip = true +do_tools_cpupower = true +do_tools_perf = true +do_tools_perf_jvmti = true +do_tools_perf_python = true +do_tools_bpftool = true +do_tools_rtla = true + +do_dtbs = true --- linux-nvidia-7.0.0.orig/debian.nvidia/tracking-bug +++ linux-nvidia-7.0.0/debian.nvidia/tracking-bug @@ -0,0 +1 @@ +2148214 d2026.04.13-1 --- linux-nvidia-7.0.0.orig/debian.nvidia/upstream-stable +++ linux-nvidia-7.0.0/debian.nvidia/upstream-stable @@ -0,0 +1,3 @@ +# The following upstream stable releases have been ported: +[upstream-stable] + linux-6.17.y = v6.17.1 --- linux-nvidia-7.0.0.orig/debian.nvidia/variants +++ linux-nvidia-7.0.0/debian.nvidia/variants @@ -0,0 +1,4 @@ +-7.0 +-- +-hwe-24.04 +-hwe-24.04-edge --- linux-nvidia-7.0.0.orig/debian/canonical-certs.pem +++ linux-nvidia-7.0.0/debian/canonical-certs.pem @@ -0,0 +1,496 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + 47:77:26:6d:ae:6c:57:73:eb:80:e2:96:dd:26:93:ff:e9:f5:62:5d + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN=Canonical Ltd. Live Patch Signing 2025 Kmod + Validity + Not Before: May 16 09:07:40 2025 GMT + Not After : May 16 09:07:40 2050 GMT + Subject: CN=Canonical Ltd. Live Patch Signing 2025 Kmod + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (4096 bit) + Modulus: + 00:b8:a9:03:47:2e:7b:c6:86:16:f4:b7:a8:4d:3b: + 05:f6:c4:75:35:e9:22:8a:4e:40:06:89:15:7f:ad: + 99:bb:e6:90:93:61:c8:16:cf:2e:00:1b:81:36:fd: + cc:31:7b:97:79:8d:5e:d2:4d:d3:2f:ab:35:2d:74: + 48:98:b3:d9:75:f9:bb:e1:f2:3f:6b:6d:dc:e4:bb: + ee:f5:aa:f7:8a:8c:7a:a8:0b:df:b1:f8:d6:04:13: + 27:e9:1a:aa:c2:4d:d2:35:3a:bc:06:d7:83:7f:e8: + c4:1c:63:8b:3a:ff:0e:0b:89:6e:4f:5f:ea:ad:78: + df:37:ab:f9:55:1d:fb:6e:29:a4:22:43:d1:9b:12: + 1e:b2:84:23:1b:d2:38:91:b8:a8:6c:1c:59:3c:ff: + 4c:a9:18:ce:d0:7f:1d:ef:04:cf:8a:e8:29:b2:4b: + 68:0d:92:32:bc:9c:5d:8f:0a:d1:dd:4d:25:ba:3a: + 8c:6a:48:5b:1e:9c:01:10:99:c1:a7:34:ee:68:ec: + a1:d3:26:be:45:c8:b4:97:ac:8a:aa:7e:13:a6:e5: + 43:f1:1b:3f:a1:80:0a:d2:a9:e7:f2:77:ca:e1:f5: + 29:36:df:75:8a:7e:02:d6:17:aa:46:12:b9:51:f0: + 6b:ca:22:f8:05:de:d6:02:47:76:0c:88:f1:c6:90: + 44:99:58:71:c7:62:1e:2b:94:c5:2b:8e:dc:ca:7b: + a7:bd:cd:38:8f:4e:73:6d:b0:9b:4e:7c:12:1f:5c: + c5:62:d6:82:c6:d2:78:09:52:dc:d7:78:2e:23:d0: + 63:1f:7d:77:91:c8:3f:66:7a:20:8a:cf:70:09:0f: + a2:c0:82:a5:42:d9:be:dc:5f:78:73:f7:fa:3c:70: + 47:7b:39:77:89:5a:6f:ef:83:09:c9:1b:21:53:89: + 7c:10:bf:99:9c:05:39:32:1e:84:3b:a5:84:7e:ef: + 08:6d:b0:b0:31:61:d6:1a:aa:dd:7a:d6:10:02:e6: + 72:02:e5:40:bf:07:b9:cd:61:d1:55:04:9a:cd:02: + 73:41:c1:df:20:30:12:97:ca:a1:83:1a:97:8a:92: + 1c:47:5c:0a:60:da:41:3b:e6:0e:2c:82:ce:45:65: + 81:ba:45:a1:66:cc:ef:ab:65:5c:e5:a8:0c:86:dd: + fc:86:54:f3:37:7c:89:a9:0c:fa:3a:da:82:c9:90: + 99:1e:1d:66:44:de:d3:c5:d4:0b:da:15:f8:d8:d4: + 63:2b:4e:6f:24:e9:c2:d7:74:9c:29:91:9f:25:39: + 8d:77:15:8c:cb:8e:ad:e3:80:0a:ea:79:04:72:9d: + 51:01:18:ae:35:51:ef:95:79:38:c4:db:99:50:47: + 62:38:e9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + D5:41:CE:F6:1D:C7:E7:93:B7:EB:7E:89:99:70:A2:EE:F0:B5:DC:8C + X509v3 Authority Key Identifier: + D5:41:CE:F6:1D:C7:E7:93:B7:EB:7E:89:99:70:A2:EE:F0:B5:DC:8C + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.2312.16.1.2 + Signature Algorithm: sha512WithRSAEncryption + Signature Value: + 40:9d:5b:70:66:fe:9c:99:eb:ed:78:61:be:da:67:da:ac:80: + a8:c2:78:91:f8:90:11:be:9f:6a:e7:bf:79:dc:11:0c:c7:83: + e8:13:c4:1c:b6:fe:f0:e7:7d:1a:12:97:5d:19:56:9c:10:12: + 1e:b9:19:88:30:95:c4:3b:2f:aa:91:6f:c1:9e:68:4a:f4:5c: + ef:a1:51:b5:a3:9b:58:3f:e2:ae:5c:29:a6:c4:30:fd:65:0b: + cc:8c:99:95:33:61:c6:07:fa:c3:bd:1a:57:80:e5:43:97:2e: + f3:5c:d6:1e:b7:23:9f:58:10:19:24:46:9e:f8:fd:2c:8e:88: + e7:ec:ef:15:4b:7a:6a:ce:b0:25:c0:01:c5:21:83:1a:d5:89: + 0c:90:86:ad:d4:3e:6e:28:bf:6c:21:91:ff:b9:a9:ef:d4:ac: + de:7c:67:c1:e4:ed:75:26:15:ff:5d:67:39:24:2d:15:57:21: + 09:76:e5:85:f3:45:e8:bf:b1:c0:39:2b:83:34:1a:f5:3f:1f: + ae:07:8c:82:1f:d4:dc:95:c0:4e:f3:7f:ac:db:8f:2c:db:a4: + d4:2a:4c:8c:de:e6:5b:84:fc:df:a3:74:d8:dc:9c:93:1f:5b: + c9:33:b5:b3:7d:2b:a4:4d:7a:bb:73:92:ff:8d:e9:9e:c7:a7: + d2:0d:83:bb:2c:2f:47:51:15:5c:6d:db:9a:d3:9e:6e:25:90: + 01:e6:09:bd:a2:d0:1e:cf:a3:12:22:0d:56:70:bf:89:e4:be: + 62:76:9c:d9:f5:c8:01:55:95:02:57:a1:67:59:88:97:57:f6: + bb:8d:c9:40:d5:e3:60:4f:43:dd:49:90:fa:a5:6d:08:96:b2: + 4d:dd:a7:c6:e3:5c:06:ba:af:8c:30:9d:d5:a5:b0:ab:c4:e5: + f3:09:47:05:ba:9b:46:f4:26:70:3b:fa:da:a5:0a:47:ce:be: + 43:87:eb:73:63:3b:cd:41:7a:78:a0:f6:7d:c5:37:fb:bb:26: + 3b:b3:e7:44:49:06:8c:14:03:fc:b3:46:54:3b:0d:57:02:08: + 99:79:68:a2:9c:62:95:4d:ac:8e:19:43:4e:8f:2d:52:fa:91: + ca:78:06:a2:b7:a3:66:6d:67:0b:13:ee:b1:01:38:e0:7c:ac: + 9a:16:27:36:f1:45:83:5d:eb:d6:cd:65:3f:56:9a:d3:56:c4: + 15:55:b2:64:ca:13:cb:31:1e:7e:03:85:68:61:40:02:99:4b: + 25:01:68:8d:97:cc:39:1a:54:1b:e5:51:38:8e:ce:66:74:61: + 5e:87:f4:31:7d:0d:be:9d:01:e1:b3:5c:bc:1a:d0:ea:5e:b2: + c8:ee:97:34:bc:9f:bb:98 +-----BEGIN CERTIFICATE----- +MIIFejCCA2KgAwIBAgIUR3cmba5sV3PrgOKW3SaT/+n1Yl0wDQYJKoZIhvcNAQEN +BQAwNjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTGl2ZSBQYXRjaCBTaWduaW5n +IDIwMjUgS21vZDAgFw0yNTA1MTYwOTA3NDBaGA8yMDUwMDUxNjA5MDc0MFowNjE0 +MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTGl2ZSBQYXRjaCBTaWduaW5nIDIwMjUg +S21vZDCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBALipA0cue8aGFvS3 +qE07BfbEdTXpIopOQAaJFX+tmbvmkJNhyBbPLgAbgTb9zDF7l3mNXtJN0y+rNS10 +SJiz2XX5u+HyP2tt3OS77vWq94qMeqgL37H41gQTJ+kaqsJN0jU6vAbXg3/oxBxj +izr/DguJbk9f6q143zer+VUd+24ppCJD0ZsSHrKEIxvSOJG4qGwcWTz/TKkYztB/ +He8Ez4roKbJLaA2SMrycXY8K0d1NJbo6jGpIWx6cARCZwac07mjsodMmvkXItJes +iqp+E6blQ/EbP6GACtKp5/J3yuH1KTbfdYp+AtYXqkYSuVHwa8oi+AXe1gJHdgyI +8caQRJlYccdiHiuUxSuO3Mp7p73NOI9Oc22wm058Eh9cxWLWgsbSeAlS3Nd4LiPQ +Yx99d5HIP2Z6IIrPcAkPosCCpULZvtxfeHP3+jxwR3s5d4lab++DCckbIVOJfBC/ +mZwFOTIehDulhH7vCG2wsDFh1hqq3XrWEALmcgLlQL8Huc1h0VUEms0Cc0HB3yAw +EpfKoYMal4qSHEdcCmDaQTvmDiyCzkVlgbpFoWbM76tlXOWoDIbd/IZU8zd8iakM ++jragsmQmR4dZkTe08XUC9oV+NjUYytObyTpwtd0nCmRnyU5jXcVjMuOreOACup5 +BHKdUQEYrjVR75V5OMTbmVBHYjjpAgMBAAGjfjB8MAwGA1UdEwEB/wQCMAAwCwYD +VR0PBAQDAgeAMB0GA1UdDgQWBBTVQc72Hcfnk7frfomZcKLu8LXcjDAfBgNVHSME +GDAWgBTVQc72Hcfnk7frfomZcKLu8LXcjDAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGSCBABAjANBgkqhkiG9w0BAQ0FAAOCAgEAQJ1bcGb+nJnr7Xhhvtpn2qyA +qMJ4kfiQEb6faue/edwRDMeD6BPEHLb+8Od9GhKXXRlWnBASHrkZiDCVxDsvqpFv +wZ5oSvRc76FRtaObWD/irlwppsQw/WULzIyZlTNhxgf6w70aV4DlQ5cu81zWHrcj +n1gQGSRGnvj9LI6I5+zvFUt6as6wJcABxSGDGtWJDJCGrdQ+bii/bCGR/7mp79Ss +3nxnweTtdSYV/11nOSQtFVchCXblhfNF6L+xwDkrgzQa9T8frgeMgh/U3JXATvN/ +rNuPLNuk1CpMjN7mW4T836N02Nyckx9byTO1s30rpE16u3OS/43pnsen0g2Duywv +R1EVXG3bmtOebiWQAeYJvaLQHs+jEiINVnC/ieS+Ynac2fXIAVWVAlehZ1mIl1f2 +u43JQNXjYE9D3UmQ+qVtCJayTd2nxuNcBrqvjDCd1aWwq8Tl8wlHBbqbRvQmcDv6 +2qUKR86+Q4frc2M7zUF6eKD2fcU3+7smO7PnREkGjBQD/LNGVDsNVwIImXloopxi +lU2sjhlDTo8tUvqRyngGorejZm1nCxPusQE44HysmhYnNvFFg13r1s1lP1aa01bE +FVWyZMoTyzEefgOFaGFAAplLJQFojZfMORpUG+VROI7OZnRhXof0MX0Nvp0B4bNc +vBrQ6l6yyO6XNLyfu5g= +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + c7:7e:51:6a:1c:25:cd:40 + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN = Canonical Ltd. Live Patch Signing + Validity + Not Before: Jul 18 23:41:27 2016 GMT + Not After : Jul 16 23:41:27 2026 GMT + Subject: CN = Canonical Ltd. Live Patch Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + RSA Public-Key: (4096 bit) + Modulus: + 00:bd:74:ee:72:b3:4a:ab:e6:31:e8:29:24:c2:bd: + 46:98:32:c0:39:ee:a3:fb:8a:ad:fe:ab:1a:5b:a3: + 2e:a1:80:db:79:61:9e:47:79:2c:75:57:a2:21:f0: + 93:f6:87:f2:9b:4b:9d:2f:b3:58:61:28:3c:41:70: + 13:16:a1:72:90:c9:d5:16:71:7c:e0:30:f9:28:5e: + 48:20:36:00:69:b7:59:9f:a3:ec:a8:eb:55:41:9f: + 38:1e:22:4a:57:20:f4:83:59:49:c5:00:93:d3:33: + 02:92:d1:fc:f0:84:3b:4a:5b:8f:b6:73:9a:89:fa: + 30:1e:e6:2a:68:f2:91:ef:59:57:3d:dc:1c:52:6f: + 5e:e6:9b:b5:b8:7c:98:c9:13:d1:39:68:01:67:91: + e0:d3:67:72:16:0a:5e:16:83:45:31:4f:b5:2b:b3: + f6:40:86:89:3a:84:6e:6f:16:61:bc:70:84:be:5a: + 13:36:7b:82:ea:07:19:fc:18:c1:16:c6:32:0b:7d: + 2c:6b:c4:21:b9:38:6b:31:dc:d9:0c:ad:56:40:68: + 7c:e3:c6:64:8e:bf:1c:e0:72:3e:6c:db:d2:73:79: + da:d7:c5:2f:5d:04:7d:b0:07:1e:95:dd:2a:47:5e: + bf:3e:3a:c8:66:f6:67:0f:d4:2a:f1:e2:71:59:d2: + 6c:7b:a0:37:ac:e6:97:80:30:13:97:48:d5:74:fc: + 38:68:e4:57:cb:99:69:5a:84:27:ac:98:51:e4:64: + bd:91:62:e8:58:27:06:2a:b9:0b:b8:08:e5:e5:b4: + 51:a7:a2:10:df:4e:07:6c:a0:3b:96:f2:6e:df:75: + 8c:97:1e:64:a0:9a:86:9b:98:26:f9:d8:b7:de:5b: + 21:b7:af:89:01:a3:f7:98:6b:da:19:ba:86:ef:ef: + f1:ce:bb:2f:89:ed:c0:b6:1b:e5:5b:f8:90:11:9a: + 52:93:e9:be:f7:35:b9:08:cb:ba:c3:ed:2f:73:af: + cc:96:07:55:b5:de:f6:03:f6:f1:89:f9:21:40:76: + c1:69:f2:61:cc:9a:94:df:9c:ec:6a:65:38:be:d1: + 4e:2a:87:c7:2f:3e:53:ae:8b:9f:54:a1:09:59:64: + 25:aa:a9:d8:44:a9:a8:a0:71:e1:32:aa:4c:32:fd: + 44:28:cc:9c:6f:8e:db:81:7e:6f:fa:00:56:c5:e5: + 03:46:63:fb:8e:71:8d:e3:13:91:9f:ac:60:3e:64: + f3:df:25:34:09:fa:2d:96:9f:16:05:ea:93:f5:e6: + 00:08:27:32:7b:3c:bd:ee:70:24:6c:3b:55:e9:db: + f4:10:2d:20:06:b4:ca:e9:29:65:55:ad:f6:52:54: + 5f:e5:a3 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 14:DF:34:D1:A8:7C:F3:76:25:AB:EC:03:9E:F2:BF:52:12:49:B9:69 + X509v3 Authority Key Identifier: + keyid:14:DF:34:D1:A8:7C:F3:76:25:AB:EC:03:9E:F2:BF:52:12:49:B9:69 + + Signature Algorithm: sha512WithRSAEncryption + 30:e7:48:02:37:e9:28:cf:04:a2:4d:5c:fa:d8:4e:c9:76:c7: + 14:3f:bd:2c:51:3d:33:f0:1a:bc:49:f1:47:95:8f:69:d8:a9: + 54:14:44:6c:4d:9f:55:82:08:1e:c6:5b:d5:91:d9:bc:2e:b0: + af:d6:25:65:74:96:aa:36:de:ae:31:a8:11:f2:a4:2c:5a:e1: + 4f:73:f8:4a:c3:35:b0:76:96:71:f2:b5:7d:4b:75:ee:5d:bf: + 86:a5:ba:0b:a9:52:cb:ec:ab:e5:23:4b:f2:74:55:28:17:1e: + b3:ac:27:ad:45:13:6e:69:b3:5a:be:42:36:29:48:db:e7:5c: + 22:58:a0:90:82:2c:2a:21:2b:db:f4:64:b7:91:5d:1f:2c:48: + a4:1a:85:e3:86:a5:aa:19:cd:19:e8:a5:fb:a3:7b:94:77:48: + 25:a4:cf:a0:cf:71:82:5c:6f:71:22:7c:d6:97:a0:53:bb:ec: + 30:f6:cb:16:fb:7b:fd:16:94:7a:53:6e:bd:04:64:a2:01:10: + 9f:f0:5b:b5:a6:73:41:9d:5f:6f:45:73:0d:05:f7:30:6d:39: + 90:b6:7d:55:7d:4c:2f:ae:5f:38:56:2f:8b:df:f4:bf:12:06: + 93:6e:0d:02:23:bf:71:91:57:88:e8:bd:62:72:99:00:40:29: + 1e:c9:13:11:da:7e:8e:e1:d2:a5:0d:bf:f7:d6:ec:01:0d:89: + 41:cd:d5:dc:d2:f7:5f:33:0d:4c:2f:85:b7:85:b7:81:e4:17: + 29:f0:74:cf:0e:15:8c:1a:50:0b:08:63:1a:91:4f:e7:76:97: + f1:d4:3b:7e:72:d4:c5:45:58:0c:6a:e9:0d:f2:85:d8:91:1e: + 37:bd:78:e3:39:4d:2e:fd:85:31:c1:a6:3b:6a:cc:2c:53:72: + 1d:8e:7b:f0:e6:76:86:09:6f:1a:f3:e4:a1:e2:dd:76:5f:b0: + 8c:e2:2a:54:5d:c1:88:49:90:10:15:42:7d:05:24:53:8c:54: + ff:48:18:1a:36:e3:31:d3:54:32:78:0d:fe:f2:3d:aa:0d:37: + 15:84:b4:36:47:31:e8:85:6e:0b:58:38:ff:21:91:09:c9:a8: + 43:a3:ea:60:cb:7e:ed:f7:41:6f:4e:91:c1:fd:77:46:e7:d4: + e7:86:c0:1b:fd:50:6c:aa:be:00:b3:63:02:ff:4e:c7:a5:57: + 6e:29:64:e9:54:d5:30:63:38:5f:2d:5a:db:49:5f:14:14:22: + d2:81:1f:61:9e:ee:ee:16:66:d6:bc:bd:ac:1b:5c:fb:38:31: + 95:33:2e:84:6e:7a:de:ee:b9:fc:97:17:06:13:bf:70:1c:6e: + 76:ed:66:38:e2:70:08:00 +-----BEGIN CERTIFICATE----- +MIIFODCCAyCgAwIBAgIJAMd+UWocJc1AMA0GCSqGSIb3DQEBDQUAMCwxKjAoBgNV +BAMMIUNhbm9uaWNhbCBMdGQuIExpdmUgUGF0Y2ggU2lnbmluZzAeFw0xNjA3MTgy +MzQxMjdaFw0yNjA3MTYyMzQxMjdaMCwxKjAoBgNVBAMMIUNhbm9uaWNhbCBMdGQu +IExpdmUgUGF0Y2ggU2lnbmluZzCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoC +ggIBAL107nKzSqvmMegpJMK9RpgywDnuo/uKrf6rGlujLqGA23lhnkd5LHVXoiHw +k/aH8ptLnS+zWGEoPEFwExahcpDJ1RZxfOAw+SheSCA2AGm3WZ+j7KjrVUGfOB4i +Slcg9INZScUAk9MzApLR/PCEO0pbj7Zzmon6MB7mKmjyke9ZVz3cHFJvXuabtbh8 +mMkT0TloAWeR4NNnchYKXhaDRTFPtSuz9kCGiTqEbm8WYbxwhL5aEzZ7guoHGfwY +wRbGMgt9LGvEIbk4azHc2QytVkBofOPGZI6/HOByPmzb0nN52tfFL10EfbAHHpXd +Kkdevz46yGb2Zw/UKvHicVnSbHugN6zml4AwE5dI1XT8OGjkV8uZaVqEJ6yYUeRk +vZFi6FgnBiq5C7gI5eW0UaeiEN9OB2ygO5bybt91jJceZKCahpuYJvnYt95bIbev +iQGj95hr2hm6hu/v8c67L4ntwLYb5Vv4kBGaUpPpvvc1uQjLusPtL3OvzJYHVbXe +9gP28Yn5IUB2wWnyYcyalN+c7GplOL7RTiqHxy8+U66Ln1ShCVlkJaqp2ESpqKBx +4TKqTDL9RCjMnG+O24F+b/oAVsXlA0Zj+45xjeMTkZ+sYD5k898lNAn6LZafFgXq +k/XmAAgnMns8ve5wJGw7Venb9BAtIAa0yukpZVWt9lJUX+WjAgMBAAGjXTBbMAwG +A1UdEwEB/wQCMAAwCwYDVR0PBAQDAgeAMB0GA1UdDgQWBBQU3zTRqHzzdiWr7AOe +8r9SEkm5aTAfBgNVHSMEGDAWgBQU3zTRqHzzdiWr7AOe8r9SEkm5aTANBgkqhkiG +9w0BAQ0FAAOCAgEAMOdIAjfpKM8Eok1c+thOyXbHFD+9LFE9M/AavEnxR5WPadip +VBREbE2fVYIIHsZb1ZHZvC6wr9YlZXSWqjberjGoEfKkLFrhT3P4SsM1sHaWcfK1 +fUt17l2/hqW6C6lSy+yr5SNL8nRVKBces6wnrUUTbmmzWr5CNilI2+dcIligkIIs +KiEr2/Rkt5FdHyxIpBqF44alqhnNGeil+6N7lHdIJaTPoM9xglxvcSJ81pegU7vs +MPbLFvt7/RaUelNuvQRkogEQn/BbtaZzQZ1fb0VzDQX3MG05kLZ9VX1ML65fOFYv +i9/0vxIGk24NAiO/cZFXiOi9YnKZAEApHskTEdp+juHSpQ2/99bsAQ2JQc3V3NL3 +XzMNTC+Ft4W3geQXKfB0zw4VjBpQCwhjGpFP53aX8dQ7fnLUxUVYDGrpDfKF2JEe +N7144zlNLv2FMcGmO2rMLFNyHY578OZ2hglvGvPkoeLddl+wjOIqVF3BiEmQEBVC +fQUkU4xU/0gYGjbjMdNUMngN/vI9qg03FYS0Nkcx6IVuC1g4/yGRCcmoQ6PqYMt+ +7fdBb06Rwf13RufU54bAG/1QbKq+ALNjAv9Ox6VXbilk6VTVMGM4Xy1a20lfFBQi +0oEfYZ7u7hZm1ry9rBtc+zgxlTMuhG563u65/JcXBhO/cBxudu1mOOJwCAA= +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + 2c:af:80:6d:b1:e0:8b:9f:49:90:7b:b2:39:4e:b3:c7:88:0e:44:53 + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod + Validity + Not Before: Nov 21 12:32:19 2025 GMT + Not After : Nov 21 12:32:19 2050 GMT + Subject: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (4096 bit) + Modulus: + 00:9e:20:bd:0d:2d:bd:af:fe:e2:68:a3:8e:fe:2b: + 50:21:08:03:3a:32:71:d5:35:ac:d0:0a:07:ae:f4: + dc:a2:8d:2f:c6:0d:2a:6b:ac:ef:84:72:d5:df:91: + 52:cf:76:01:b3:29:e1:ba:9f:5b:9f:f0:92:b7:03: + 65:80:ca:d0:aa:6d:26:28:07:8b:2c:19:9e:87:e9: + 5f:58:5c:aa:ad:3c:be:71:3a:2d:d6:79:72:23:7e: + bf:f3:39:48:c6:d0:2f:7f:c2:79:0e:35:51:c9:4f: + e9:bf:80:06:75:5e:76:30:c0:96:83:4a:79:f3:3a: + 9e:30:e5:0e:9d:b6:86:c3:7c:6a:eb:4d:4c:5c:0b: + e1:a8:48:b2:e4:f4:62:64:55:7b:f0:5b:10:15:07: + 51:89:e4:98:7e:7b:58:c0:38:dc:03:7e:ba:1a:0e: + c2:12:b0:1e:93:f1:dc:7d:8f:85:7d:d0:7f:d6:ef: + e6:6c:90:03:d9:85:a5:a1:43:20:af:b1:89:75:d4: + e7:af:63:b1:ba:0d:a3:a4:5e:29:a4:5c:f0:bf:9a: + c8:7e:c3:da:60:d4:ae:ad:13:3f:cc:4b:64:73:3d: + 59:3f:8b:91:7f:8c:fe:e6:4b:2f:e3:04:2b:e3:ae: + 0d:6f:8b:55:b9:e9:1b:67:37:25:9d:43:d3:70:b5: + 01:e8:d9:de:11:9a:b8:c9:5b:ba:b0:0c:6a:9f:9b: + fe:79:e3:a9:27:90:1d:56:95:84:8b:eb:96:a1:47: + 83:28:3c:d0:ea:81:7e:fe:a2:90:3d:84:02:5e:bc: + 68:0b:70:69:36:18:32:53:e3:4a:e1:c5:0d:dc:d6: + cd:3f:c0:1a:27:28:db:96:0a:ce:01:03:0d:8e:9e: + 38:e1:04:85:38:ad:f7:1f:10:40:b5:b1:d5:85:bd: + e6:62:b1:3c:f0:ac:8f:8a:88:62:46:cc:bf:64:9b: + e7:b6:c0:68:3e:96:14:54:6c:76:08:8d:6a:fd:08: + 4b:8e:0b:0e:ca:84:8a:17:60:fb:12:c7:f2:27:49: + 9b:b8:ff:a9:3f:70:5f:98:51:be:96:f1:0d:bf:1d: + 0e:c3:c7:34:5e:b3:35:e7:ff:43:e4:0e:7a:86:08: + d6:13:a6:6f:48:4a:d6:f5:61:cb:ba:29:e6:54:ac: + c9:c0:32:5e:fe:72:b2:e1:c4:e4:d9:ec:6a:1e:f2: + 5f:cc:db:44:30:42:79:ca:c8:d1:86:28:3b:3a:50: + d0:71:81:5f:ab:fb:f1:2f:65:df:8e:a4:7c:96:5c: + 46:c3:fc:b0:fd:3d:b1:38:cf:85:15:a6:da:ce:a9: + a3:b0:76:6a:4b:8a:4c:25:ce:c2:3d:fc:01:11:24: + 1d:c7:f9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 46:27:60:3D:23:57:A2:A3:F8:10:06:37:08:94:C2:21:17:58:93:E9 + X509v3 Authority Key Identifier: + 46:27:60:3D:23:57:A2:A3:F8:10:06:37:08:94:C2:21:17:58:93:E9 + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.2312.16.1.2 + Signature Algorithm: sha512WithRSAEncryption + Signature Value: + 21:a6:29:45:48:fc:42:37:12:b8:71:af:06:9e:2a:63:91:19: + 7b:52:a5:c9:2a:63:66:36:94:3f:2b:ac:f7:01:7e:04:48:92: + 7c:33:66:94:c8:c0:c3:1e:a4:f4:10:d2:4a:67:1a:10:64:15: + dd:70:86:8c:4d:ef:a9:c2:09:bc:44:9b:83:06:7c:ce:b3:2f: + 09:9f:32:51:dd:f9:e6:87:96:c7:3f:08:e1:8f:ed:4d:b0:39: + 02:9c:c0:86:40:28:56:59:5c:1d:11:af:a8:ad:49:e8:91:a0: + 31:a2:e8:c4:5e:88:c4:31:c3:d4:6f:3f:5a:94:c7:6e:b8:2a: + 74:27:90:12:c6:1f:35:87:32:31:e9:38:14:d9:09:c3:42:e6: + e7:f7:8f:46:22:a1:c9:12:0c:34:1a:7c:d0:6b:e5:c7:42:49: + 3f:7d:c9:bb:38:65:e3:93:16:1b:ae:48:6c:29:53:ec:1a:a0: + 75:3f:3e:e4:a7:30:59:79:e7:8d:4b:76:06:8d:f5:4b:97:06: + 0a:af:0e:0b:7b:37:8c:9d:86:3d:92:40:cf:2d:87:ca:5c:66: + 01:9b:bd:42:99:5c:4b:39:91:0e:8f:db:d3:2b:57:fe:4a:17: + a0:10:17:e4:39:f1:a1:28:1b:51:53:9c:cf:95:4e:23:55:e3: + 24:2b:2e:dc:ed:cb:9c:1a:fb:64:f6:05:be:c4:71:70:62:af: + 52:2d:64:9f:4b:f0:87:5d:5d:53:8d:41:2e:6a:81:2a:e2:fb: + 55:89:7d:70:93:eb:59:61:b1:f7:75:64:0e:6c:f7:eb:b9:d4: + 83:08:20:29:9c:03:0b:5b:d5:8f:de:4e:bd:e0:d9:c2:c5:01: + 03:9d:a5:3a:db:2b:f2:32:89:67:0e:ec:32:a4:74:bd:fb:f8: + 0e:b4:cf:cd:5e:49:bb:02:2d:d1:0c:3d:2f:d7:22:e4:89:4c: + 6a:3c:e5:ce:6d:21:68:7e:74:2e:35:5e:3b:9a:44:3b:a5:54: + 9a:3c:be:df:5d:e2:f6:dd:1c:bd:f8:05:99:82:2f:16:4d:6e: + f6:37:8b:77:3f:81:2f:10:a6:4c:04:67:a4:58:34:0d:5d:6f: + e4:2a:c4:c2:be:00:f1:8e:8b:85:98:77:48:8a:47:21:2e:ff: + cc:55:6d:8c:f2:ec:3e:14:75:a5:7d:0c:24:40:b6:54:49:30: + 84:1a:62:b2:19:60:42:3c:a4:3f:bc:fc:21:f6:1d:19:83:cc: + f8:cb:08:2a:15:49:c8:35:8f:bd:14:c3:22:92:c9:5b:84:88: + 50:01:db:10:08:4b:24:08:00:c4:60:76:be:e8:62:e2:0c:bd: + 9a:28:3c:70:86:9c:dd:94 +-----BEGIN CERTIFICATE----- +MIIFgDCCA2igAwIBAgIULK+AbbHgi59JkHuyOU6zx4gORFMwDQYJKoZIhvcNAQEN +BQAwOTE3MDUGA1UEAwwuQ2Fub25pY2FsIEx0ZC4gS2VybmVsIE1vZHVsZSBTaWdu +aW5nIDIwMjUgS21vZDAgFw0yNTExMjExMjMyMTlaGA8yMDUwMTEyMTEyMzIxOVow +OTE3MDUGA1UEAwwuQ2Fub25pY2FsIEx0ZC4gS2VybmVsIE1vZHVsZSBTaWduaW5n +IDIwMjUgS21vZDCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAJ4gvQ0t +va/+4mijjv4rUCEIAzoycdU1rNAKB6703KKNL8YNKmus74Ry1d+RUs92AbMp4bqf +W5/wkrcDZYDK0KptJigHiywZnofpX1hcqq08vnE6LdZ5ciN+v/M5SMbQL3/CeQ41 +UclP6b+ABnVedjDAloNKefM6njDlDp22hsN8autNTFwL4ahIsuT0YmRVe/BbEBUH +UYnkmH57WMA43AN+uhoOwhKwHpPx3H2PhX3Qf9bv5myQA9mFpaFDIK+xiXXU569j +sboNo6ReKaRc8L+ayH7D2mDUrq0TP8xLZHM9WT+LkX+M/uZLL+MEK+OuDW+LVbnp +G2c3JZ1D03C1AejZ3hGauMlburAMap+b/nnjqSeQHVaVhIvrlqFHgyg80OqBfv6i +kD2EAl68aAtwaTYYMlPjSuHFDdzWzT/AGico25YKzgEDDY6eOOEEhTit9x8QQLWx +1YW95mKxPPCsj4qIYkbMv2Sb57bAaD6WFFRsdgiNav0IS44LDsqEihdg+xLH8idJ +m7j/qT9wX5hRvpbxDb8dDsPHNF6zNef/Q+QOeoYI1hOmb0hK1vVhy7op5lSsycAy +Xv5ysuHE5Nnsah7yX8zbRDBCecrI0YYoOzpQ0HGBX6v78S9l346kfJZcRsP8sP09 +sTjPhRWm2s6po7B2akuKTCXOwj38AREkHcf5AgMBAAGjfjB8MAwGA1UdEwEB/wQC +MAAwCwYDVR0PBAQDAgeAMB0GA1UdDgQWBBRGJ2A9I1eio/gQBjcIlMIhF1iT6TAf +BgNVHSMEGDAWgBRGJ2A9I1eio/gQBjcIlMIhF1iT6TAfBgNVHSUEGDAWBggrBgEF +BQcDAwYKKwYBBAGSCBABAjANBgkqhkiG9w0BAQ0FAAOCAgEAIaYpRUj8QjcSuHGv +Bp4qY5EZe1KlySpjZjaUPyus9wF+BEiSfDNmlMjAwx6k9BDSSmcaEGQV3XCGjE3v +qcIJvESbgwZ8zrMvCZ8yUd355oeWxz8I4Y/tTbA5ApzAhkAoVllcHRGvqK1J6JGg +MaLoxF6IxDHD1G8/WpTHbrgqdCeQEsYfNYcyMek4FNkJw0Lm5/ePRiKhyRIMNBp8 +0Gvlx0JJP33Juzhl45MWG65IbClT7BqgdT8+5KcwWXnnjUt2Bo31S5cGCq8OC3s3 +jJ2GPZJAzy2HylxmAZu9QplcSzmRDo/b0ytX/koXoBAX5DnxoSgbUVOcz5VOI1Xj +JCsu3O3LnBr7ZPYFvsRxcGKvUi1kn0vwh11dU41BLmqBKuL7VYl9cJPrWWGx93Vk +Dmz367nUgwggKZwDC1vVj95OveDZwsUBA52lOtsr8jKJZw7sMqR0vfv4DrTPzV5J +uwIt0Qw9L9ci5IlMajzlzm0haH50LjVeO5pEO6VUmjy+313i9t0cvfgFmYIvFk1u +9jeLdz+BLxCmTARnpFg0DV1v5CrEwr4A8Y6LhZh3SIpHIS7/zFVtjPLsPhR1pX0M +JEC2VEkwhBpishlgQjykP7z8IfYdGYPM+MsIKhVJyDWPvRTDIpLJW4SIUAHbEAhL +JAgAxGB2vuhi4gy9mig8cIac3ZQ= +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + e9:df:13:0f:92:92:a9:b7 + Signature Algorithm: sha512WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Kernel Module Signing + Validity + Not Before: May 31 16:06:09 2016 GMT + Not After : May 29 16:06:09 2026 GMT + Subject: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Kernel Module Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + RSA Public-Key: (4096 bit) + Modulus: + 00:b3:b0:4f:c6:0a:77:8b:f9:d1:53:33:34:d2:80: + b5:63:6f:e1:f6:a2:83:99:d5:b6:b1:e4:99:91:fa: + 6c:19:c6:d0:91:2a:b9:7d:b5:98:a6:0d:28:01:b8: + 7c:8e:aa:38:ec:51:37:33:96:f0:b0:9b:8d:86:5f: + 67:23:69:2f:d7:c2:f3:fb:c5:d7:f9:04:ff:f2:e5: + 61:68:b7:29:b9:c6:8e:4b:4d:2d:8f:92:0c:00:b3: + a3:d2:5a:08:64:cd:f2:09:0b:a5:0e:e6:64:75:d5: + 41:f4:4d:49:3a:0d:dc:b9:27:8e:c4:d6:b1:df:8f: + 6c:f0:e4:f7:31:cb:a9:04:a1:f9:a7:aa:15:da:59: + 03:4d:46:14:d0:dd:bf:e0:f5:9e:f0:71:0c:70:78: + 2b:08:fb:e0:b6:68:a4:74:12:9d:f7:f2:64:88:17: + 2a:8a:ed:1a:91:b5:6c:13:bd:4c:10:0a:0b:72:0b: + 90:db:7d:f3:78:44:4c:d2:a5:41:f7:1c:77:7d:5a: + 8a:54:bc:8f:fe:b7:ee:e1:bc:59:37:c4:d4:e8:14: + d0:5b:42:9b:04:00:8e:6d:83:8a:25:21:5b:08:c4: + 7b:b2:d9:99:52:c9:5e:59:6d:c4:aa:52:59:e2:e4: + 2f:7e:7e:ac:05:01:99:bf:13:72:b7:45:c5:17:da: + 8a:d5:3e:71:73:2e:d8:aa:e6:eb:5a:d0:9a:c4:93: + f3:be:eb:d2:47:25:34:16:29:fa:dd:9a:2f:b1:20: + e5:41:4e:ed:ea:51:7c:23:80:ba:3d:b5:3a:0b:8c: + 9c:85:48:6c:3c:8b:29:2f:2f:12:c7:52:34:02:ea: + 0f:ac:53:23:3c:f8:3e:40:1b:30:63:e9:2d:e6:f6: + 58:cc:51:f9:eb:08:4a:b4:c7:16:80:d1:8b:c2:64: + 6a:71:a9:70:31:a4:a7:3a:c0:93:99:1b:0e:42:c1: + 00:6d:43:27:99:6c:e5:fd:23:16:c1:8e:b5:66:17: + 2b:4c:53:5a:6d:1e:96:16:13:6a:c6:d4:85:5b:74: + 2e:ce:7c:45:2f:ad:cb:75:9e:5e:91:bd:9a:6a:86: + 1a:06:bd:39:be:a3:50:56:ea:e1:f6:e3:95:69:d7: + 31:e4:66:f7:36:b5:51:c2:22:b4:9c:74:9c:44:0b: + 0e:16:5f:53:f0:23:c6:b9:40:bd:d6:b8:7d:1b:f6: + 73:f6:27:e7:c0:e3:65:a0:58:ab:5c:59:b7:80:8c: + 8c:04:b4:a9:ae:a0:51:40:10:3b:63:59:49:87:d1: + 9b:df:a3:8c:c4:2e:eb:70:c1:0a:18:1f:cb:22:c2: + f2:4a:65:0d:e5:81:74:d8:ce:72:c6:35:be:ba:63: + 72:c4:f9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 88:F7:52:E5:60:A1:E0:73:7E:31:16:3A:46:6A:D7:B7:0A:85:0C:19 + X509v3 Authority Key Identifier: + keyid:88:F7:52:E5:60:A1:E0:73:7E:31:16:3A:46:6A:D7:B7:0A:85:0C:19 + + Signature Algorithm: sha512WithRSAEncryption + 04:85:16:27:58:ba:71:28:57:86:7b:c2:83:db:e5:72:6f:1e: + b2:1c:63:b0:db:ad:c0:42:96:c0:4f:65:f6:35:4d:c0:07:0d: + 46:be:d3:1e:ec:f1:22:18:2a:18:5d:bb:69:a6:a6:d4:0d:c3: + 57:03:b9:e7:45:49:28:ca:6d:98:17:68:97:cb:7b:36:81:0a: + 37:9e:34:79:f3:e1:0e:5b:77:43:bb:5a:a5:45:b7:16:50:86: + fd:12:a4:96:0f:15:19:09:1c:e1:fa:80:a5:80:09:be:bb:c8: + 26:0b:3e:de:03:d2:c2:18:a4:8d:0d:de:c5:32:82:0b:fb:75: + 55:66:1a:2a:bb:e4:bd:25:91:20:15:d4:be:b8:3f:53:e3:fb: + a8:c3:55:e3:d5:e7:82:18:95:df:39:09:a7:fc:89:6e:b4:1c: + aa:2d:e8:67:c2:0d:34:34:3e:f9:fa:0b:ce:81:92:11:ae:12: + 0a:fe:35:63:ce:46:29:c4:2b:4f:cb:4e:05:0a:a1:11:e2:35: + f6:5a:5d:b5:e8:d2:6f:4c:fc:3d:24:a6:03:4b:dd:98:6b:f2: + 71:58:16:1d:a5:25:ef:d9:06:7c:e8:db:7b:88:6a:89:5c:59: + 01:92:64:db:44:08:63:6c:7c:32:d6:55:98:63:09:26:61:67: + 0a:fe:5d:ee:fd:23:59:b3:4d:91:c1:4d:41:8b:cd:20:58:fa: + 2d:45:e5:bd:1d:69:5c:03:a0:49:a6:97:54:13:b6:c9:e0:f8: + 56:83:a1:2a:c3:f4:6c:fd:ab:20:ca:3d:9c:95:c0:cf:04:bb: + 46:39:cf:34:81:65:45:27:64:01:7d:62:b3:b8:72:ea:10:d5: + 0f:53:7d:39:88:25:09:6f:8c:bc:e0:49:bb:39:e2:0e:8d:cf: + 56:4d:c1:82:6d:87:d2:e7:fc:c0:9f:a7:65:60:d2:6c:65:18: + 59:38:6e:d0:9c:d7:c3:81:9a:9a:29:8f:83:84:c3:b5:44:ff: + 28:ac:13:17:64:f2:26:13:d9:55:06:b7:69:68:7c:bf:ec:d1: + 8c:ef:b7:da:76:e1:07:73:c6:31:62:31:cb:b6:e1:e7:7f:0c: + c3:f7:4c:52:be:25:36:8e:a1:bb:60:02:c3:cb:3e:6f:29:fc: + 7f:6a:fa:f8:ec:0a:df:49:e2:57:0e:bc:bd:93:c3:1b:d5:36: + 8a:ff:d8:1b:17:c7:1f:cb:69:00:d2:54:9e:ad:61:89:92:95: + 11:f8:ea:17:83:9f:9b:09:7d:b8:94:a4:ea:f5:ae:ea:dc:dd: + 62:b9:9e:68:9c:18:ec:19:c4:13:08:c8:b1:62:ab:8e:84:69: + 11:3c:da:ea:0d:b7:22:bd +-----BEGIN CERTIFICATE----- +MIIF2jCCA8KgAwIBAgIJAOnfEw+Skqm3MA0GCSqGSIb3DQEBDQUAMH0xCzAJBgNV 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+sWKrjoRpETza6g23Ir0= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/canonical-revoked-certs.pem +++ linux-nvidia-7.0.0/debian/canonical-revoked-certs.pem @@ -0,0 +1,688 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 1 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Apr 12 11:39:08 2012 GMT + Not After : Apr 11 11:39:08 2042 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:c9:5f:9b:62:8f:0b:b0:64:82:ac:be:c9:e2:62: + e3:4b:d2:9f:1e:8a:d5:61:1a:2b:5d:38:f4:b7:ce: + b9:9a:b8:43:b8:43:97:77:ab:4f:7f:0c:70:46:0b: + fc:7f:6d:c6:6d:ea:80:5e:01:d2:b7:66:1e:87:de: + 0d:6d:d0:41:97:a8:a5:af:0c:63:4f:f7:7c:c2:52: + cc:a0:31:a9:bb:89:5d:99:1e:46:6f:55:73:b9:76: + 69:ec:d7:c1:fc:21:d6:c6:07:e7:4f:bd:22:de:e4: + a8:5b:2d:db:95:34:19:97:d6:28:4b:21:4c:ca:bb: + 1d:79:a6:17:7f:5a:f9:67:e6:5c:78:45:3d:10:6d: + b0:17:59:26:11:c5:57:e3:7f:4e:82:ba:f6:2c:4e: + c8:37:4d:ff:85:15:84:47:e0:ed:3b:7c:7f:bc:af: + e9:01:05:a7:0c:6f:c3:e9:8d:a3:ce:be:a6:e3:cd: + 3c:b5:58:2c:9e:c2:03:1c:60:22:37:39:ff:41:02: + c1:29:a4:65:51:ff:33:34:aa:42:15:f9:95:78:fc: + 2d:f5:da:8a:85:7c:82:9d:fb:37:2c:6b:a5:a8:df: + 7c:55:0b:80:2e:3c:b0:63:e1:cd:38:48:89:e8:14: + 06:0b:82:bc:fd:d4:07:68:1b:0f:3e:d9:15:dd:94: + 11:1b + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 61:48:2A:A2:83:0D:0A:B2:AD:5A:F1:0B:72:50:DA:90:33:DD:CE:F0 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 8f:8a:a1:06:1f:29:b7:0a:4a:d5:c5:fd:81:ab:25:ea:c0:7d: + e2:fc:6a:96:a0:79:93:67:ee:05:0e:25:12:25:e4:5a:f6:aa: + 1a:f1:12:f3:05:8d:87:5e:f1:5a:5c:cb:8d:23:73:65:1d:15: + b9:de:22:6b:d6:49:67:c9:a3:c6:d7:62:4e:5c:b5:f9:03:83: + 40:81:dc:87:9c:3c:3f:1c:0d:51:9f:94:65:0a:84:48:67:e4: + a2:f8:a6:4a:f0:e7:cd:cd:bd:94:e3:09:d2:5d:2d:16:1b:05: + 15:0b:cb:44:b4:3e:61:42:22:c4:2a:5c:4e:c5:1d:a3:e2:e0: + 52:b2:eb:f4:8b:2b:dc:38:39:5d:fb:88:a1:56:65:5f:2b:4f: + 26:ff:06:78:10:12:eb:8c:5d:32:e3:c6:45:af:25:9b:a0:ff: + 8e:ef:47:09:a3:e9:8b:37:92:92:69:76:7e:34:3b:92:05:67: + 4e:b0:25:ed:bc:5e:5f:8f:b4:d6:ca:40:ff:e4:e2:31:23:0c: + 85:25:ae:0c:55:01:ec:e5:47:5e:df:5b:bc:14:33:e3:c6:f5: + 18:b6:d9:f7:dd:b3:b4:a1:31:d3:5a:5c:5d:7d:3e:bf:0a:e4: + e4:e8:b4:59:7d:3b:b4:8c:a3:1b:b5:20:a3:b9:3e:84:6f:8c: + 21:00:c3:39 +-----BEGIN CERTIFICATE----- +MIIEIDCCAwigAwIBAgIBATANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xMjA0MTIxMTM5MDhaFw00MjA0MTEx +MTM5MDhaMH8xCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEXMBUG +A1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MSswKQYD +VQQDDCJDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nMIIBIjANBgkq +hkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAyV+bYo8LsGSCrL7J4mLjS9KfHorVYRor +XTj0t865mrhDuEOXd6tPfwxwRgv8f23GbeqAXgHSt2Yeh94NbdBBl6ilrwxjT/d8 +wlLMoDGpu4ldmR5Gb1VzuXZp7NfB/CHWxgfnT70i3uSoWy3blTQZl9YoSyFMyrsd +eaYXf1r5Z+ZceEU9EG2wF1kmEcVX439Ogrr2LE7IN03/hRWER+DtO3x/vK/pAQWn +DG/D6Y2jzr6m4808tVgsnsIDHGAiNzn/QQLBKaRlUf8zNKpCFfmVePwt9dqKhXyC +nfs3LGulqN98VQuALjywY+HNOEiJ6BQGC4K8/dQHaBsPPtkV3ZQRGwIDAQABo4Gg +MIGdMAwGA1UdEwEB/wQCMAAwHwYDVR0lBBgwFgYIKwYBBQUHAwMGCisGAQQBgjcK +AwYwLAYJYIZIAYb4QgENBB8WHU9wZW5TU0wgR2VuZXJhdGVkIENlcnRpZmljYXRl +MB0GA1UdDgQWBBRhSCqigw0Ksq1a8QtyUNqQM93O8DAfBgNVHSMEGDAWgBStkZkL +wiqx9RcEjCO2ZVomjjRaYzANBgkqhkiG9w0BAQsFAAOCAQEAj4qhBh8ptwpK1cX9 +gasl6sB94vxqlqB5k2fuBQ4lEiXkWvaqGvES8wWNh17xWlzLjSNzZR0Vud4ia9ZJ +Z8mjxtdiTly1+QODQIHch5w8PxwNUZ+UZQqESGfkovimSvDnzc29lOMJ0l0tFhsF +FQvLRLQ+YUIixCpcTsUdo+LgUrLr9Isr3Dg5XfuIoVZlXytPJv8GeBAS64xdMuPG +Ra8lm6D/ju9HCaPpizeSkml2fjQ7kgVnTrAl7bxeX4+01spA/+TiMSMMhSWuDFUB +7OVHXt9bvBQz48b1GLbZ992ztKEx01pcXX0+vwrk5Oi0WX07tIyjG7Ugo7k+hG+M +IQDDOQ== +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 2 (0x2) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 26 21:52:11 2017 GMT + Not After : Sep 25 21:52:11 2047 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2017) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:ef:9f:fa:9f:19:3a:9d:38:23:91:cc:c4:f9:42: + e0:f8:54:12:82:dc:97:2c:d6:5b:c1:35:eb:ff:4a: + 74:06:b5:9d:32:aa:7b:f3:fc:31:5a:34:3e:a1:a4: + 44:db:7b:6d:16:af:35:76:e0:9b:99:ad:21:11:c6: + 12:4b:ae:24:8f:bb:d3:b2:00:fe:c5:1d:9b:3a:1a: + 4a:6c:ca:fa:16:37:85:22:f9:ff:22:fc:40:e0:58: + 35:c1:39:27:b4:c6:42:1a:96:d8:a5:c5:95:2e:f7: + c5:1e:21:6e:36:84:f7:a9:a1:e1:f1:03:08:96:65: + 71:f8:eb:83:cf:82:f7:9a:44:58:72:00:14:39:29: + 4b:e9:78:2f:65:20:b3:80:76:3b:ba:0d:2d:46:f6: + 37:05:e7:05:fe:bd:6c:c7:a2:65:b5:06:6e:07:24: + 99:a1:c1:cf:e1:0e:5e:49:41:71:17:a8:50:e7:38: + 99:e5:6e:b6:db:9f:63:db:56:f4:9c:7d:89:f6:d2: + 03:6c:99:83:e0:99:23:39:36:bd:cb:b5:26:7c:7d: + b0:c6:fe:82:7c:52:ed:f9:2c:8f:79:71:3d:a9:2f: + b5:aa:7e:77:a0:fd:69:f9:97:10:a8:b2:c6:7d:88: + 9e:a2:19:bd:31:b8:02:2d:34:4d:9d:98:60:82:ad: + 04:ff + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 24:2A:DE:75:AC:4A:15:E5:0D:50:C8:4B:0D:45:FF:3E:AE:70:7A:03 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 00:b2:b7:57:b5:2b:5d:16:d3:04:88:6a:d7:77:d5:0d:89:f1: + d2:6e:11:d1:8e:f5:62:05:c4:6a:57:df:eb:d2:86:68:f2:fd: + a7:37:11:3c:f4:ce:5d:fe:32:5f:31:a2:6b:3a:da:28:c2:88: + fa:7f:70:b5:25:99:ea:27:9a:56:6a:9d:b2:0f:14:99:e2:b7: + c6:39:1e:8e:a7:76:31:d9:ed:c5:05:8d:48:ae:1b:68:18:14: + 51:a1:7d:f6:c7:df:cb:9d:eb:a4:3b:0b:ff:c2:07:c5:42:bc: + 0d:b2:11:fa:37:17:2b:1c:b5:84:48:2d:f9:31:4a:57:49:8e: + 61:a6:82:11:06:4c:34:ea:9c:2a:47:4d:eb:e0:26:af:da:d2: + c2:08:a0:37:35:7b:73:71:de:0b:c4:ba:c8:34:de:20:04:03: + 6f:46:26:0d:b9:91:02:5b:71:76:cc:45:e4:08:d0:a6:dd:a4: + 50:d3:d9:04:91:2b:d9:5c:34:88:fc:c2:37:fd:c6:d4:3e:57: + f7:6b:ba:7b:d7:02:7a:84:0c:c8:c1:19:cc:bc:fa:52:d5:7f: + b3:35:c4:53:5d:70:0a:f6:44:60:8d:a9:11:7a:1b:7d:ae:7b: + 20:5a:4c:8d:44:f6:c1:a9:61:cb:dc:cb:90:37:d5:28:24:73: + 87:d0:e0:d8 +-----BEGIN CERTIFICATE----- +MIIEKDCCAxCgAwIBAgIBAjANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xNzA5MjYyMTUyMTFaFw00NzA5MjUy +MTUyMTFaMIGGMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDEyMDAG +A1UEAwwpQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoMjAxNykw +ggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDvn/qfGTqdOCORzMT5QuD4 +VBKC3Jcs1lvBNev/SnQGtZ0yqnvz/DFaND6hpETbe20WrzV24JuZrSERxhJLriSP +u9OyAP7FHZs6GkpsyvoWN4Ui+f8i/EDgWDXBOSe0xkIaltilxZUu98UeIW42hPep +oeHxAwiWZXH464PPgveaRFhyABQ5KUvpeC9lILOAdju6DS1G9jcF5wX+vWzHomW1 +Bm4HJJmhwc/hDl5JQXEXqFDnOJnlbrbbn2PbVvScfYn20gNsmYPgmSM5Nr3LtSZ8 +fbDG/oJ8Uu35LI95cT2pL7Wqfneg/Wn5lxCossZ9iJ6iGb0xuAItNE2dmGCCrQT/ +AgMBAAGjgaAwgZ0wDAYDVR0TAQH/BAIwADAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGCNwoDBjAsBglghkgBhvhCAQ0EHxYdT3BlblNTTCBHZW5lcmF0ZWQgQ2Vy +dGlmaWNhdGUwHQYDVR0OBBYEFCQq3nWsShXlDVDISw1F/z6ucHoDMB8GA1UdIwQY +MBaAFK2RmQvCKrH1FwSMI7ZlWiaONFpjMA0GCSqGSIb3DQEBCwUAA4IBAQAAsrdX +tStdFtMEiGrXd9UNifHSbhHRjvViBcRqV9/r0oZo8v2nNxE89M5d/jJfMaJrOtoo +woj6f3C1JZnqJ5pWap2yDxSZ4rfGOR6Op3Yx2e3FBY1IrhtoGBRRoX32x9/Lneuk +Owv/wgfFQrwNshH6NxcrHLWESC35MUpXSY5hpoIRBkw06pwqR03r4Cav2tLCCKA3 +NXtzcd4LxLrINN4gBANvRiYNuZECW3F2zEXkCNCm3aRQ09kEkSvZXDSI/MI3/cbU +Plf3a7p71wJ6hAzIwRnMvPpS1X+zNcRTXXAK9kRgjakReht9rnsgWkyNRPbBqWHL +3MuQN9UoJHOH0ODY +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 3 (0x3) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Oct 26 18:31:14 2018 GMT + Not After : Oct 24 18:31:14 2048 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (ESM 2018) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:bf:6a:e5:6d:55:7a:ec:7a:11:37:45:9c:4c:8f: + 6b:2d:56:d3:74:2b:32:ac:84:2d:ba:cb:cc:ec:8d: + 92:22:69:48:a5:d4:f6:75:11:66:2f:cb:b2:fd:9e: + 56:ab:e6:f1:52:8e:75:3e:50:bd:25:b3:50:fc:ef: + 3d:76:f3:3f:7f:03:f6:e2:a1:25:69:5c:14:98:54: + bd:11:bf:e9:a5:ac:46:91:4b:1d:de:b7:18:2b:c8: + 22:83:15:a7:4a:00:8d:9d:e4:c0:da:f7:41:02:fd: + 9f:5f:79:93:56:cc:86:e1:b5:e0:39:0e:3c:a2:5b: + fe:c0:56:f0:92:50:5a:2b:67:67:93:56:d7:7a:75: + 99:6a:25:b4:63:a8:5f:69:7e:3a:49:58:2a:a7:80: + f6:5a:b4:be:b2:be:a8:8c:45:41:c9:f2:fc:76:a8: + 65:ef:99:29:0d:c9:9c:54:6b:0a:f0:4a:0e:61:0d: + ed:99:32:af:12:e2:12:7b:9f:7b:ec:05:c4:e0:b6: + d5:c3:71:28:ae:dd:0b:ba:97:ad:68:0b:76:e9:bf: + e7:01:7e:64:54:39:23:85:36:c8:9d:dd:27:a1:ff: + df:46:36:14:7e:cb:cc:a1:cd:49:0b:6d:c2:0c:45: + 99:56:58:7c:87:0d:59:9a:dc:4a:39:3b:1d:d9:15: + 2e:b5 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 36:51:88:C1:D3:74:D6:B0:7C:3C:8F:24:0F:8E:F7:22:43:3D:6A:8B + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 4c:0f:cd:77:60:b4:6f:53:87:f3:3c:4f:e6:81:5f:a7:1c:cc: + 60:29:b6:34:6c:4d:08:9b:e2:d2:bd:f6:17:1a:62:79:b8:17: + bc:a2:60:59:fd:03:51:c3:b7:6b:de:73:b3:48:95:f5:0b:aa: + b6:3c:b4:34:dc:1d:0b:c4:97:62:87:e7:48:d5:8f:c9:ea:e8: + 91:8f:2a:40:cd:b7:b3:ee:b2:98:9e:fb:37:31:29:e6:8e:2f: + 0a:39:99:1e:c6:aa:b8:05:62:85:d3:a8:3e:60:38:98:0f:f0: + fe:c7:ab:01:a5:6a:a5:7f:70:a6:26:94:76:23:2f:08:89:74: + 97:c2:2a:ca:22:3e:7a:ea:22:22:08:07:f4:bb:f6:bc:69:9c: + 4e:44:33:e2:8e:70:17:b0:9b:cb:33:94:66:6d:ff:9a:7d:e9: + 50:b2:e8:90:14:e4:2b:91:cb:a0:c5:2e:0e:cf:19:ef:44:ef: + 84:f0:bd:57:9e:26:c2:63:3d:df:fc:a1:84:de:5c:d7:5f:3b: + fb:94:61:f0:93:89:1f:cf:c3:b2:d1:90:97:35:7d:b9:8a:ad: + e6:05:f0:e8:3b:a1:7c:af:2b:c4:af:18:33:2e:5e:87:db:9d: + 80:b5:04:fd:00:d0:60:ab:ff:85:77:0f:cb:47:22:c9:b2:85: + a8:48:16:e2 +-----BEGIN CERTIFICATE----- +MIIELDCCAxSgAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xODEwMjYxODMxMTRaFw00ODEwMjQx +ODMxMTRaMIGKMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDE2MDQG +A1UEAwwtQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoRVNNIDIw +MTgpMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAv2rlbVV67HoRN0Wc +TI9rLVbTdCsyrIQtusvM7I2SImlIpdT2dRFmL8uy/Z5Wq+bxUo51PlC9JbNQ/O89 +dvM/fwP24qElaVwUmFS9Eb/ppaxGkUsd3rcYK8gigxWnSgCNneTA2vdBAv2fX3mT +VsyG4bXgOQ48olv+wFbwklBaK2dnk1bXenWZaiW0Y6hfaX46SVgqp4D2WrS+sr6o +jEVByfL8dqhl75kpDcmcVGsK8EoOYQ3tmTKvEuISe5977AXE4LbVw3Eort0Lupet +aAt26b/nAX5kVDkjhTbInd0nof/fRjYUfsvMoc1JC23CDEWZVlh8hw1ZmtxKOTsd +2RUutQIDAQABo4GgMIGdMAwGA1UdEwEB/wQCMAAwHwYDVR0lBBgwFgYIKwYBBQUH +AwMGCisGAQQBgjcKAwYwLAYJYIZIAYb4QgENBB8WHU9wZW5TU0wgR2VuZXJhdGVk +IENlcnRpZmljYXRlMB0GA1UdDgQWBBQ2UYjB03TWsHw8jyQPjvciQz1qizAfBgNV +HSMEGDAWgBStkZkLwiqx9RcEjCO2ZVomjjRaYzANBgkqhkiG9w0BAQsFAAOCAQEA +TA/Nd2C0b1OH8zxP5oFfpxzMYCm2NGxNCJvi0r32FxpiebgXvKJgWf0DUcO3a95z +s0iV9Quqtjy0NNwdC8SXYofnSNWPyerokY8qQM23s+6ymJ77NzEp5o4vCjmZHsaq +uAVihdOoPmA4mA/w/serAaVqpX9wpiaUdiMvCIl0l8IqyiI+euoiIggH9Lv2vGmc +TkQz4o5wF7CbyzOUZm3/mn3pULLokBTkK5HLoMUuDs8Z70TvhPC9V54mwmM93/yh +hN5c1187+5Rh8JOJH8/DstGQlzV9uYqt5gXw6DuhfK8rxK8YMy5eh9udgLUE/QDQ +YKv/hXcPy0ciybKFqEgW4g== +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 4 (0x4) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 18 16:10:17 2019 GMT + Not After : Sep 16 16:10:17 2049 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2019) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:e6:47:d8:75:e5:87:59:26:87:83:7d:5b:7a:b8: + 58:3d:7c:ef:36:f8:a0:7a:b7:14:56:58:7d:01:f1: + 1c:3b:8c:e6:5b:03:77:7d:a0:ed:47:0a:45:e6:75: + 5c:de:95:38:0d:38:fa:41:79:89:56:31:87:e7:a3: + 9a:36:70:b6:cf:24:2f:99:26:89:08:39:0e:14:c3: + 35:be:02:8b:52:e1:8e:7b:0c:a6:9d:78:ff:01:60: + d7:f5:c3:d5:f0:5e:dc:e4:23:09:59:72:93:d3:b5: + 22:af:7c:cd:e0:84:0f:af:11:2d:bc:c6:72:42:af: + ea:67:63:c4:10:41:78:02:80:62:0d:43:74:b4:1c: + ed:50:d7:94:f1:b0:bb:f9:57:80:e4:69:0f:83:4b: + a2:e6:2c:4a:9a:e1:7d:7c:62:19:29:27:97:1f:4c: + f1:85:f0:39:f5:31:9f:3a:39:0e:d4:4d:07:3a:40: + 55:4b:a6:6c:9d:04:89:51:2d:7c:b0:ef:40:b5:42: + 29:16:cc:65:73:38:62:21:f6:e3:2c:17:50:9d:74: + 34:4e:df:7c:4a:33:a4:bb:40:cf:d5:e5:ed:05:07: + cd:4c:f9:af:7f:a6:5c:b9:f7:c5:16:45:4e:44:40: + d7:85:32:de:ac:e5:75:ad:9b:d7:c0:26:33:1f:77: + a5:37 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + C0:74:6F:D6:C5:DA:3A:E8:27:86:46:51:AD:66:AE:47:FE:24:B3:E8 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + aa:12:6c:d1:9d:6a:da:f0:ec:7c:17:46:3b:57:b8:d6:76:5f: + 24:e6:06:a2:0a:55:1f:2f:d3:5e:8f:de:cf:02:f2:ff:e0:dd: + d3:c7:bd:75:59:aa:cd:34:f3:28:80:73:cc:28:69:e7:a2:70: + 88:a2:c7:dc:66:f0:92:0e:ff:64:bf:30:04:54:01:1b:96:ad: + 15:c5:61:fd:32:61:d7:5e:b5:ba:91:fd:31:fc:6b:15:df:ee: + 22:d9:e4:1f:f3:cc:8b:0c:9f:f5:e8:f7:e2:62:3f:40:52:c9: + f0:f1:1c:63:fc:6c:90:e1:5b:74:03:b9:df:d1:3e:a8:ec:db: + 2b:6e:83:6f:9f:7f:ba:b4:79:fc:3d:e7:12:2f:4a:e7:17:8c: + 2b:77:a5:90:74:3c:bd:cf:75:83:0d:1a:95:d5:56:ef:07:9b: + a6:b3:31:e3:8c:97:ce:68:11:b5:7b:25:03:72:1c:ea:67:e9: + 7c:3e:73:c7:7c:3e:fc:f5:ae:8a:b2:07:0d:15:6a:66:09:d7: + 23:b9:5d:80:7a:26:d6:b6:22:30:aa:84:af:c0:42:e9:75:c3: + 59:ab:a3:84:87:6b:0c:b7:ab:4e:92:69:ae:2c:82:6f:ab:01: + 24:ab:ff:78:6d:59:85:c2:3b:23:c0:bd:0d:d8:6e:3a:29:82: + e1:c4:5f:db +-----BEGIN CERTIFICATE----- +MIIEKDCCAxCgAwIBAgIBBDANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xOTA5MTgxNjEwMTdaFw00OTA5MTYx +NjEwMTdaMIGGMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDEyMDAG +A1UEAwwpQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoMjAxOSkw +ggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDmR9h15YdZJoeDfVt6uFg9 +fO82+KB6txRWWH0B8Rw7jOZbA3d9oO1HCkXmdVzelTgNOPpBeYlWMYfno5o2cLbP +JC+ZJokIOQ4UwzW+AotS4Y57DKadeP8BYNf1w9XwXtzkIwlZcpPTtSKvfM3ghA+v +ES28xnJCr+pnY8QQQXgCgGINQ3S0HO1Q15TxsLv5V4DkaQ+DS6LmLEqa4X18Yhkp +J5cfTPGF8Dn1MZ86OQ7UTQc6QFVLpmydBIlRLXyw70C1QikWzGVzOGIh9uMsF1Cd +dDRO33xKM6S7QM/V5e0FB81M+a9/ply598UWRU5EQNeFMt6s5XWtm9fAJjMfd6U3 +AgMBAAGjgaAwgZ0wDAYDVR0TAQH/BAIwADAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGCNwoDBjAsBglghkgBhvhCAQ0EHxYdT3BlblNTTCBHZW5lcmF0ZWQgQ2Vy +dGlmaWNhdGUwHQYDVR0OBBYEFMB0b9bF2jroJ4ZGUa1mrkf+JLPoMB8GA1UdIwQY +MBaAFK2RmQvCKrH1FwSMI7ZlWiaONFpjMA0GCSqGSIb3DQEBCwUAA4IBAQCqEmzR +nWra8Ox8F0Y7V7jWdl8k5gaiClUfL9Nej97PAvL/4N3Tx711WarNNPMogHPMKGnn +onCIosfcZvCSDv9kvzAEVAEblq0VxWH9MmHXXrW6kf0x/GsV3+4i2eQf88yLDJ/1 +6PfiYj9AUsnw8Rxj/GyQ4Vt0A7nf0T6o7NsrboNvn3+6tHn8PecSL0rnF4wrd6WQ +dDy9z3WDDRqV1VbvB5umszHjjJfOaBG1eyUDchzqZ+l8PnPHfD789a6KsgcNFWpm +CdcjuV2AeibWtiIwqoSvwELpdcNZq6OEh2sMt6tOkmmuLIJvqwEkq/94bVmFwjsj +wL0N2G46KYLhxF/b +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 6 (0x6) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:29:32 2021 GMT + Not After : Sep 22 19:29:32 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v1) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:aa:b8:34:5b:b6:ae:44:bf:41:e1:78:11:b9:7a: + c8:88:b3:b0:26:50:10:9c:98:d1:f3:98:9f:23:50: + 64:f6:39:dd:50:3a:23:44:53:65:fc:f3:9f:f5:a5: + 8b:ae:8b:df:47:9f:e9:d5:a0:92:19:f1:21:ea:cc: + 59:3a:74:df:45:71:bc:de:64:15:a5:f6:db:ca:71: + fa:19:d4:44:0d:12:ec:47:3a:43:e2:f2:dd:8b:fe: + 0d:7b:dc:4d:db:53:06:22:61:e5:8b:35:49:b6:33: + c4:0a:69:5f:5b:81:09:84:6b:42:33:18:09:9d:a0: + 35:f7:9c:1e:de:6e:de:90:69:1a:e8:32:e4:49:ad: + c3:31:e9:f8:4a:a2:28:1d:db:0d:29:b6:48:0a:44: + 93:86:41:62:8f:73:97:60:10:8a:74:46:66:55:fe: + a0:95:35:9e:ef:9f:af:11:fa:5b:a3:7c:c2:35:64: + 11:67:28:1e:14:0a:7d:68:61:9c:cd:c7:46:39:30: + 31:79:94:56:b3:45:16:9a:b5:77:66:fe:41:43:0f: + 00:48:6e:99:dd:0c:d4:47:2c:86:8c:50:04:61:20: + dd:aa:8e:73:4f:21:b4:ee:09:4d:d3:40:01:d0:f2: + a7:5b:7d:05:3d:c1:e7:65:26:aa:8c:9a:58:5a:7c: + 6d:6f + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + A8:D5:4B:BB:38:25:CF:B9:4F:A1:3C:9F:8A:59:4A:19:5C:10:7B:8D + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 24:25:25:7e:01:a5:c8:3d:54:8c:1b:05:73:d1:06:d8:db:d4: + 3a:71:d5:19:9d:97:1c:85:3c:ca:38:5a:0c:25:25:39:1a:67: + bc:6c:9d:98:6c:f3:7d:5f:b7:40:f9:73:a0:f5:7b:40:a8:66: + a5:f1:53:b1:78:80:24:3f:19:50:2f:02:09:ec:a1:8a:e6:0d: + df:c4:ae:24:9e:69:0d:5c:dc:44:4c:38:3a:53:4e:4b:a1:4b: + 92:9f:43:a4:9d:1e:76:33:18:1b:bf:62:e5:f5:bc:93:3c:4e: + 21:d5:5b:20:69:11:28:c1:c5:93:b5:8e:96:1d:1b:ca:72:79: + 24:de:67:2a:50:9d:ce:8b:41:dd:3e:82:dd:a5:04:75:54:fb: + 35:70:98:87:b4:f3:ea:41:23:23:80:0e:99:d7:03:16:ee:7e: + 11:e2:c8:29:ab:73:c5:6d:5c:a8:2f:32:03:9f:8e:66:d6:cb: + 54:84:55:75:ab:9a:dd:95:fd:05:1e:11:85:37:1e:63:d2:f4: + 7f:34:64:32:a1:63:91:91:50:39:14:1a:ea:54:78:e6:0d:04: + 23:c7:83:51:c5:25:27:07:6c:f8:65:b7:da:95:89:76:83:cc: + f3:7e:06:74:d3:6c:ef:e9:17:de:29:1e:ab:5c:d7:ec:df:f1: + 98:b8:e9:66 +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBBjANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTI5MzJaGA8yMDUxMDky +MjE5MjkzMlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYxKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKq4NFu2rkS/QeF4 +Ebl6yIizsCZQEJyY0fOYnyNQZPY53VA6I0RTZfzzn/Wli66L30ef6dWgkhnxIerM +WTp030VxvN5kFaX228px+hnURA0S7Ec6Q+Ly3Yv+DXvcTdtTBiJh5Ys1SbYzxApp +X1uBCYRrQjMYCZ2gNfecHt5u3pBpGugy5EmtwzHp+EqiKB3bDSm2SApEk4ZBYo9z +l2AQinRGZlX+oJU1nu+frxH6W6N8wjVkEWcoHhQKfWhhnM3HRjkwMXmUVrNFFpq1 +d2b+QUMPAEhumd0M1EcshoxQBGEg3aqOc08htO4JTdNAAdDyp1t9BT3B52Umqoya +WFp8bW8CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUqNVLuzglz7lPoTyfillKGVwQe40wHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +ACQlJX4Bpcg9VIwbBXPRBtjb1Dpx1RmdlxyFPMo4WgwlJTkaZ7xsnZhs831ft0D5 +c6D1e0CoZqXxU7F4gCQ/GVAvAgnsoYrmDd/EriSeaQ1c3ERMODpTTkuhS5KfQ6Sd +HnYzGBu/YuX1vJM8TiHVWyBpESjBxZO1jpYdG8pyeSTeZypQnc6LQd0+gt2lBHVU ++zVwmIe08+pBIyOADpnXAxbufhHiyCmrc8VtXKgvMgOfjmbWy1SEVXWrmt2V/QUe +EYU3HmPS9H80ZDKhY5GRUDkUGupUeOYNBCPHg1HFJScHbPhlt9qViXaDzPN+BnTT +bO/pF94pHqtc1+zf8Zi46WY= +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 7 (0x7) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:29:42 2021 GMT + Not After : Sep 22 19:29:42 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v2) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:ba:06:8b:ee:58:b7:8b:49:7b:53:7a:d1:df:02: + e3:f2:d8:b0:8c:03:5c:f4:2d:0b:d8:18:3b:23:fa: + 68:b0:e8:e9:9d:dc:a2:eb:5e:d3:06:a9:28:d4:9f: + 14:b6:1e:1c:1d:ef:69:0e:7f:44:f2:cc:4a:f1:b1: + d0:71:30:6a:50:1e:b0:d3:f8:a4:19:d0:4a:f1:e3: + eb:7a:e5:57:4c:a1:fb:d1:87:b9:48:e0:55:37:52: + f9:de:99:2e:95:85:36:ce:d3:1d:67:2f:14:cb:7f: + 05:82:75:21:b6:aa:a5:14:ac:da:4a:f4:fe:fa:5c: + 33:49:3d:6f:de:fd:9d:75:ba:e2:c4:02:38:b5:69: + f5:ff:a8:67:4b:3a:e0:34:f6:3b:07:03:a5:7e:59: + 6f:3a:d2:28:a4:2f:25:ac:d8:a9:1f:59:52:5d:24: + 36:58:51:b5:f0:12:a8:d3:78:56:57:b1:e0:a9:df: + 14:05:65:7c:b5:a5:00:f0:88:39:14:44:18:85:2d: + 0c:28:69:7b:b9:b4:1c:47:6f:43:66:4c:22:ad:f7: + f6:19:75:e1:14:2c:0d:33:3f:c1:3f:fc:73:56:b2: + 68:05:b5:92:03:9b:65:6b:81:80:92:35:03:9b:66: + 68:58:c5:66:11:b6:8c:7f:05:09:9a:45:a6:0e:5e: + 5f:bf + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 4C:F0:46:89:2D:6F:D3:C9:A5:B0:3F:98:D8:45:F9:08:51:DC:6A:8C + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 93:9d:49:7d:9f:3e:3e:27:79:97:d9:c2:fc:0b:f7:30:b7:f4: + 78:b2:c9:e4:5e:42:d3:27:26:70:cf:88:96:d1:f2:ea:a0:75: + 7e:3c:f6:b7:d2:e7:95:30:e3:a6:67:a7:ee:b9:53:8f:fd:b2: + cb:db:e1:98:32:be:98:79:09:46:c6:63:6a:57:87:4d:b2:26: + 46:f6:34:5e:18:75:ca:82:80:8e:33:c2:1d:c7:76:d7:14:57: + ef:2e:0e:9e:58:5c:81:8e:ed:53:2c:07:46:0a:8a:fc:2f:f5: + b2:c8:58:f5:fa:fa:bb:f9:7d:47:13:39:f0:f2:1c:15:9c:75: + 90:40:bd:08:04:b3:6a:de:c2:cd:34:21:7e:ba:31:48:bc:a1: + 23:bc:ee:93:b2:62:96:27:30:86:c2:d4:f7:b4:e6:3c:71:47: + 37:84:ff:3d:0c:1e:ec:f3:0e:da:6b:dc:64:7a:b8:c0:7e:45: + 13:09:bf:02:b3:b7:5b:6d:09:2d:6a:4e:0b:93:94:29:4c:a6: + c3:c7:05:fa:69:08:04:53:3c:4c:64:c0:7e:89:00:91:1b:a6: + c2:d7:ea:c4:db:86:38:fe:66:03:85:7b:fc:39:24:99:4c:2a: + 3e:10:8b:91:c3:6e:20:9d:0c:ee:51:70:b5:98:58:f3:5c:ac: + 16:98:7b:ce +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBBzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTI5NDJaGA8yMDUxMDky +MjE5Mjk0MlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYyKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALoGi+5Yt4tJe1N6 +0d8C4/LYsIwDXPQtC9gYOyP6aLDo6Z3coute0wapKNSfFLYeHB3vaQ5/RPLMSvGx +0HEwalAesNP4pBnQSvHj63rlV0yh+9GHuUjgVTdS+d6ZLpWFNs7THWcvFMt/BYJ1 +IbaqpRSs2kr0/vpcM0k9b979nXW64sQCOLVp9f+oZ0s64DT2OwcDpX5ZbzrSKKQv +JazYqR9ZUl0kNlhRtfASqNN4Vlex4KnfFAVlfLWlAPCIORREGIUtDChpe7m0HEdv +Q2ZMIq339hl14RQsDTM/wT/8c1ayaAW1kgObZWuBgJI1A5tmaFjFZhG2jH8FCZpF +pg5eX78CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUTPBGiS1v08mlsD+Y2EX5CFHcaowwHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +AJOdSX2fPj4neZfZwvwL9zC39HiyyeReQtMnJnDPiJbR8uqgdX489rfS55Uw46Zn +p+65U4/9ssvb4Zgyvph5CUbGY2pXh02yJkb2NF4YdcqCgI4zwh3HdtcUV+8uDp5Y +XIGO7VMsB0YKivwv9bLIWPX6+rv5fUcTOfDyHBWcdZBAvQgEs2rews00IX66MUi8 +oSO87pOyYpYnMIbC1Pe05jxxRzeE/z0MHuzzDtpr3GR6uMB+RRMJvwKzt1ttCS1q +TguTlClMpsPHBfppCARTPExkwH6JAJEbpsLX6sTbhjj+ZgOFe/w5JJlMKj4Qi5HD +biCdDO5RcLWYWPNcrBaYe84= +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 8 (0x8) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:30:02 2021 GMT + Not After : Sep 22 19:30:02 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v3) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:d6:29:96:87:ae:07:42:45:bb:65:09:b2:9b:de: + 5d:8e:78:61:10:d5:6d:ae:ae:26:08:6a:06:ec:4a: + dd:2b:e7:1a:a9:ad:78:e3:fc:cf:8f:d1:47:bd:1e: + 33:d8:7a:e3:66:9b:e9:73:c1:5f:42:e2:fe:bc:c3: + 41:f7:cd:d7:85:d7:42:c9:ea:31:e5:47:b1:93:5b: + 43:2b:07:51:b8:75:08:ad:0f:e7:0d:81:38:5a:21: + df:b1:43:5b:db:37:c5:ac:aa:14:3a:33:19:6a:26: + e0:05:fe:cd:41:31:af:5d:a8:ab:31:77:44:fc:da: + 00:e2:7a:44:33:c3:a7:ed:13:54:9f:19:5d:c9:98: + a2:3b:af:4d:0d:87:29:9c:90:9e:42:9e:9a:06:6a: + 70:27:c5:aa:f7:a2:f2:88:e0:b9:66:9a:72:a0:f6: + 61:7e:30:8f:14:9f:44:0d:dd:54:ae:47:c8:82:ba: + d2:b2:db:6f:24:c1:f4:0a:81:07:90:47:49:5f:57: + d6:3f:bf:2a:73:98:f2:f6:24:1a:74:03:d7:35:f0: + 42:d8:14:c5:94:27:5d:3c:49:0c:b0:f0:7a:61:1b: + d7:5a:e3:a3:40:57:e9:a4:07:ee:02:a3:32:27:94: + bb:f3:36:c5:5f:ef:d3:07:04:3a:80:4c:9c:0a:b7: + 88:9f + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 10:04:37:BB:6D:E6:E4:69:B5:81:E6:1C:D6:6B:CE:3E:F4:ED:53:AF + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 3b:37:d6:a8:8d:cd:d2:df:13:35:ac:8c:92:d6:b0:ac:d1:38: + a8:00:97:47:59:b8:4a:84:8c:80:a5:1d:c7:29:bf:00:66:e5: + 10:40:26:2e:31:f5:e1:13:c0:1b:29:f3:0b:7e:2d:71:d8:db: + e1:32:8f:79:8e:e3:97:0c:40:a9:a0:12:c1:fc:c2:50:88:72: + 44:c5:bc:8b:45:6e:28:fd:d2:37:d6:db:17:cf:4e:61:33:08: + 5a:5d:08:94:73:44:e2:76:00:44:1b:b8:00:a1:86:00:64:8a: + f1:42:32:3c:28:11:67:7c:8b:aa:06:34:74:58:e8:b3:3a:36: + 8d:f6:04:5d:37:f5:66:52:c9:48:b0:a7:6f:34:09:dd:60:2a: + 86:b9:14:f1:09:f6:06:16:56:e0:51:b1:e8:75:7f:fa:37:dc: + e0:98:a7:69:ae:7b:1a:73:89:0d:06:67:cc:01:ef:80:31:45: + 9e:bb:03:2a:eb:89:70:d6:19:b2:c7:ce:bc:81:df:da:c8:6f: + a9:4b:2d:d7:a7:e1:af:c6:e8:fb:f0:61:c9:cd:d2:91:cd:8b: + c2:6c:ef:e0:b6:7f:f1:c4:81:f9:bb:76:9c:26:e3:fa:a1:a0: + cd:5e:05:de:ee:f9:1b:5b:50:0a:8b:0f:47:e3:90:32:ac:2a: + e7:65:02:80 +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBCDANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTMwMDJaGA8yMDUxMDky +MjE5MzAwMlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYzKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBANYploeuB0JFu2UJ +spveXY54YRDVba6uJghqBuxK3SvnGqmteOP8z4/RR70eM9h642ab6XPBX0Li/rzD +QffN14XXQsnqMeVHsZNbQysHUbh1CK0P5w2BOFoh37FDW9s3xayqFDozGWom4AX+ +zUExr12oqzF3RPzaAOJ6RDPDp+0TVJ8ZXcmYojuvTQ2HKZyQnkKemgZqcCfFqvei +8ojguWaacqD2YX4wjxSfRA3dVK5HyIK60rLbbyTB9AqBB5BHSV9X1j+/KnOY8vYk +GnQD1zXwQtgUxZQnXTxJDLDwemEb11rjo0BX6aQH7gKjMieUu/M2xV/v0wcEOoBM +nAq3iJ8CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUEAQ3u23m5Gm1geYc1mvOPvTtU68wHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +ADs31qiNzdLfEzWsjJLWsKzROKgAl0dZuEqEjIClHccpvwBm5RBAJi4x9eETwBsp +8wt+LXHY2+Eyj3mO45cMQKmgEsH8wlCIckTFvItFbij90jfW2xfPTmEzCFpdCJRz +ROJ2AEQbuAChhgBkivFCMjwoEWd8i6oGNHRY6LM6No32BF039WZSyUiwp280Cd1g +Koa5FPEJ9gYWVuBRseh1f/o33OCYp2muexpziQ0GZ8wB74AxRZ67AyrriXDWGbLH +zryB39rIb6lLLden4a/G6PvwYcnN0pHNi8Js7+C2f/HEgfm7dpwm4/qhoM1eBd7u ++RtbUAqLD0fjkDKsKudlAoA= +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 3 (0x3) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Mar 4 10:27:14 2020 GMT + Not After : Mar 3 10:27:14 2050 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (Ubuntu Core 2019) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:b9:10:47:2e:75:5d:f3:10:23:bb:a0:75:d2:fa: + 02:2d:ff:22:df:c1:e6:cd:38:7c:36:0f:ae:74:15: + 6e:a5:34:52:2b:c3:a4:3a:60:d7:06:ee:1d:99:93: + ff:66:91:a3:18:52:2c:8c:58:e6:b4:2f:4b:c5:fb: + 83:e6:f3:19:bd:1b:ca:23:ec:97:1f:d8:f1:9a:f1: + 04:da:da:10:04:53:4b:ec:1d:b6:26:47:7c:bb:8f: + a7:0a:6e:2e:e8:91:e6:c4:bb:64:34:78:3c:fa:09: + 15:1c:8f:9e:eb:04:99:36:22:c6:8d:07:15:0f:b9: + 69:08:fa:ff:4b:45:bd:ba:2b:cd:01:0e:e7:01:23: + c9:e5:7a:39:3b:91:b0:45:3c:d5:77:ba:ca:f9:29: + 3d:11:3f:1c:6b:5b:8e:6c:4b:3f:c9:29:05:cb:59: + d6:b1:c1:c0:2d:56:88:70:27:fa:73:05:5c:c2:11: + d4:27:11:f7:0b:c2:d5:68:d3:1a:cd:ed:d0:e4:10: + ff:34:cb:b7:45:70:34:2c:23:53:b6:9c:30:70:b4: + 5c:d1:e2:64:18:82:8f:62:b1:5e:aa:0b:d4:89:f2: + 1c:53:c4:32:7d:ef:53:ee:9b:6e:02:ab:78:bd:25: + 67:8b:39:36:d8:84:3b:06:99:02:d6:75:73:4e:f2: + f6:b9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + C1:D5:7B:8F:6B:74:3F:23:EE:41:F4:F7:EE:29:2F:06:EE:CA:DF:B9 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 2d:b5:11:a8:d2:a0:af:81:a0:18:22:18:2c:08:d0:f4:63:e8: + 8f:9a:f4:f5:20:dd:eb:22:77:19:9a:1a:09:3d:7f:aa:7d:c9: + 81:bc:26:98:65:94:46:30:4b:c2:51:7c:f7:21:41:63:87:31: + fc:a4:c9:41:28:c7:2e:2a:2e:d8:a8:75:7a:72:77:3b:1b:9f: + 72:15:0d:0c:96:8d:8b:51:f3:ce:37:b6:ca:9f:ca:59:40:4a: + fc:73:7a:94:12:99:aa:c2:8d:52:ce:91:19:2e:b4:da:ff:e5: + 2c:67:74:d9:58:47:38:2f:61:88:c5:cf:a7:48:e1:08:ba:bc: + ec:d5:3a:47:d9:8c:dc:c3:bc:cb:98:2b:79:7a:02:46:ef:85: + 19:2f:03:4b:05:84:eb:56:98:5f:6d:cf:a5:8b:a2:b6:e5:50: + 51:7c:33:44:bd:7a:94:2e:0d:90:39:39:3e:62:60:ae:3a:e2: + f5:17:fa:f1:94:06:1d:ae:a3:f8:19:20:7f:4b:4c:07:c4:e6: + 2d:0d:e5:94:84:51:6d:6f:0f:c4:c6:79:1d:f0:e8:0e:23:9e: + fd:f9:46:2c:b9:ec:97:38:56:7e:b8:13:f6:d2:e1:8e:a5:93: + 02:7b:6e:dd:33:9a:bf:10:a8:1b:3d:fa:c4:f2:15:f0:27:73: + 26:a6:94:d1 +-----BEGIN CERTIFICATE----- +MIIENjCCAx6gAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMDAzMDQxMDI3MTRaGA8yMDUwMDMw +MzEwMjcxNFowgZIxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MT4w +PAYDVQQDDDVDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nIChVYnVu +dHUgQ29yZSAyMDE5KTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALkQ +Ry51XfMQI7ugddL6Ai3/It/B5s04fDYPrnQVbqU0UivDpDpg1wbuHZmT/2aRoxhS +LIxY5rQvS8X7g+bzGb0byiPslx/Y8ZrxBNraEARTS+wdtiZHfLuPpwpuLuiR5sS7 +ZDR4PPoJFRyPnusEmTYixo0HFQ+5aQj6/0tFvborzQEO5wEjyeV6OTuRsEU81Xe6 +yvkpPRE/HGtbjmxLP8kpBctZ1rHBwC1WiHAn+nMFXMIR1CcR9wvC1WjTGs3t0OQQ +/zTLt0VwNCwjU7acMHC0XNHiZBiCj2KxXqoL1InyHFPEMn3vU+6bbgKreL0lZ4s5 +NtiEOwaZAtZ1c07y9rkCAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQY +MBYGCCsGAQUFBwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NM +IEdlbmVyYXRlZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUwdV7j2t0PyPuQfT37ikv +Bu7K37kwHwYDVR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcN +AQELBQADggEBAC21EajSoK+BoBgiGCwI0PRj6I+a9PUg3esidxmaGgk9f6p9yYG8 +JphllEYwS8JRfPchQWOHMfykyUEoxy4qLtiodXpydzsbn3IVDQyWjYtR8843tsqf +yllASvxzepQSmarCjVLOkRkutNr/5SxndNlYRzgvYYjFz6dI4Qi6vOzVOkfZjNzD +vMuYK3l6AkbvhRkvA0sFhOtWmF9tz6WLorblUFF8M0S9epQuDZA5OT5iYK464vUX ++vGUBh2uo/gZIH9LTAfE5i0N5ZSEUW1vD8TGeR3w6A4jnv35Riy57Jc4Vn64E/bS +4Y6lkwJ7bt0zmr8QqBs9+sTyFfAncyamlNE= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/certs/canonical-livepatch-2025-all.pem +++ linux-nvidia-7.0.0/debian/certs/canonical-livepatch-2025-all.pem @@ -0,0 +1,125 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + 47:77:26:6d:ae:6c:57:73:eb:80:e2:96:dd:26:93:ff:e9:f5:62:5d + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN=Canonical Ltd. Live Patch Signing 2025 Kmod + Validity + Not Before: May 16 09:07:40 2025 GMT + Not After : May 16 09:07:40 2050 GMT + Subject: CN=Canonical Ltd. Live Patch Signing 2025 Kmod + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (4096 bit) + Modulus: + 00:b8:a9:03:47:2e:7b:c6:86:16:f4:b7:a8:4d:3b: + 05:f6:c4:75:35:e9:22:8a:4e:40:06:89:15:7f:ad: + 99:bb:e6:90:93:61:c8:16:cf:2e:00:1b:81:36:fd: + cc:31:7b:97:79:8d:5e:d2:4d:d3:2f:ab:35:2d:74: + 48:98:b3:d9:75:f9:bb:e1:f2:3f:6b:6d:dc:e4:bb: + ee:f5:aa:f7:8a:8c:7a:a8:0b:df:b1:f8:d6:04:13: + 27:e9:1a:aa:c2:4d:d2:35:3a:bc:06:d7:83:7f:e8: + c4:1c:63:8b:3a:ff:0e:0b:89:6e:4f:5f:ea:ad:78: + df:37:ab:f9:55:1d:fb:6e:29:a4:22:43:d1:9b:12: + 1e:b2:84:23:1b:d2:38:91:b8:a8:6c:1c:59:3c:ff: + 4c:a9:18:ce:d0:7f:1d:ef:04:cf:8a:e8:29:b2:4b: + 68:0d:92:32:bc:9c:5d:8f:0a:d1:dd:4d:25:ba:3a: + 8c:6a:48:5b:1e:9c:01:10:99:c1:a7:34:ee:68:ec: + a1:d3:26:be:45:c8:b4:97:ac:8a:aa:7e:13:a6:e5: + 43:f1:1b:3f:a1:80:0a:d2:a9:e7:f2:77:ca:e1:f5: + 29:36:df:75:8a:7e:02:d6:17:aa:46:12:b9:51:f0: + 6b:ca:22:f8:05:de:d6:02:47:76:0c:88:f1:c6:90: + 44:99:58:71:c7:62:1e:2b:94:c5:2b:8e:dc:ca:7b: + a7:bd:cd:38:8f:4e:73:6d:b0:9b:4e:7c:12:1f:5c: + c5:62:d6:82:c6:d2:78:09:52:dc:d7:78:2e:23:d0: + 63:1f:7d:77:91:c8:3f:66:7a:20:8a:cf:70:09:0f: + a2:c0:82:a5:42:d9:be:dc:5f:78:73:f7:fa:3c:70: + 47:7b:39:77:89:5a:6f:ef:83:09:c9:1b:21:53:89: + 7c:10:bf:99:9c:05:39:32:1e:84:3b:a5:84:7e:ef: + 08:6d:b0:b0:31:61:d6:1a:aa:dd:7a:d6:10:02:e6: + 72:02:e5:40:bf:07:b9:cd:61:d1:55:04:9a:cd:02: + 73:41:c1:df:20:30:12:97:ca:a1:83:1a:97:8a:92: + 1c:47:5c:0a:60:da:41:3b:e6:0e:2c:82:ce:45:65: + 81:ba:45:a1:66:cc:ef:ab:65:5c:e5:a8:0c:86:dd: + fc:86:54:f3:37:7c:89:a9:0c:fa:3a:da:82:c9:90: + 99:1e:1d:66:44:de:d3:c5:d4:0b:da:15:f8:d8:d4: + 63:2b:4e:6f:24:e9:c2:d7:74:9c:29:91:9f:25:39: + 8d:77:15:8c:cb:8e:ad:e3:80:0a:ea:79:04:72:9d: + 51:01:18:ae:35:51:ef:95:79:38:c4:db:99:50:47: + 62:38:e9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + D5:41:CE:F6:1D:C7:E7:93:B7:EB:7E:89:99:70:A2:EE:F0:B5:DC:8C + X509v3 Authority Key Identifier: + D5:41:CE:F6:1D:C7:E7:93:B7:EB:7E:89:99:70:A2:EE:F0:B5:DC:8C + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.2312.16.1.2 + Signature Algorithm: sha512WithRSAEncryption + Signature Value: + 40:9d:5b:70:66:fe:9c:99:eb:ed:78:61:be:da:67:da:ac:80: + a8:c2:78:91:f8:90:11:be:9f:6a:e7:bf:79:dc:11:0c:c7:83: + e8:13:c4:1c:b6:fe:f0:e7:7d:1a:12:97:5d:19:56:9c:10:12: + 1e:b9:19:88:30:95:c4:3b:2f:aa:91:6f:c1:9e:68:4a:f4:5c: + ef:a1:51:b5:a3:9b:58:3f:e2:ae:5c:29:a6:c4:30:fd:65:0b: + cc:8c:99:95:33:61:c6:07:fa:c3:bd:1a:57:80:e5:43:97:2e: + f3:5c:d6:1e:b7:23:9f:58:10:19:24:46:9e:f8:fd:2c:8e:88: + e7:ec:ef:15:4b:7a:6a:ce:b0:25:c0:01:c5:21:83:1a:d5:89: + 0c:90:86:ad:d4:3e:6e:28:bf:6c:21:91:ff:b9:a9:ef:d4:ac: + de:7c:67:c1:e4:ed:75:26:15:ff:5d:67:39:24:2d:15:57:21: + 09:76:e5:85:f3:45:e8:bf:b1:c0:39:2b:83:34:1a:f5:3f:1f: + ae:07:8c:82:1f:d4:dc:95:c0:4e:f3:7f:ac:db:8f:2c:db:a4: + d4:2a:4c:8c:de:e6:5b:84:fc:df:a3:74:d8:dc:9c:93:1f:5b: + c9:33:b5:b3:7d:2b:a4:4d:7a:bb:73:92:ff:8d:e9:9e:c7:a7: + d2:0d:83:bb:2c:2f:47:51:15:5c:6d:db:9a:d3:9e:6e:25:90: + 01:e6:09:bd:a2:d0:1e:cf:a3:12:22:0d:56:70:bf:89:e4:be: + 62:76:9c:d9:f5:c8:01:55:95:02:57:a1:67:59:88:97:57:f6: + bb:8d:c9:40:d5:e3:60:4f:43:dd:49:90:fa:a5:6d:08:96:b2: + 4d:dd:a7:c6:e3:5c:06:ba:af:8c:30:9d:d5:a5:b0:ab:c4:e5: + f3:09:47:05:ba:9b:46:f4:26:70:3b:fa:da:a5:0a:47:ce:be: + 43:87:eb:73:63:3b:cd:41:7a:78:a0:f6:7d:c5:37:fb:bb:26: + 3b:b3:e7:44:49:06:8c:14:03:fc:b3:46:54:3b:0d:57:02:08: + 99:79:68:a2:9c:62:95:4d:ac:8e:19:43:4e:8f:2d:52:fa:91: + ca:78:06:a2:b7:a3:66:6d:67:0b:13:ee:b1:01:38:e0:7c:ac: + 9a:16:27:36:f1:45:83:5d:eb:d6:cd:65:3f:56:9a:d3:56:c4: + 15:55:b2:64:ca:13:cb:31:1e:7e:03:85:68:61:40:02:99:4b: + 25:01:68:8d:97:cc:39:1a:54:1b:e5:51:38:8e:ce:66:74:61: + 5e:87:f4:31:7d:0d:be:9d:01:e1:b3:5c:bc:1a:d0:ea:5e:b2: + c8:ee:97:34:bc:9f:bb:98 +-----BEGIN CERTIFICATE----- +MIIFejCCA2KgAwIBAgIUR3cmba5sV3PrgOKW3SaT/+n1Yl0wDQYJKoZIhvcNAQEN +BQAwNjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTGl2ZSBQYXRjaCBTaWduaW5n +IDIwMjUgS21vZDAgFw0yNTA1MTYwOTA3NDBaGA8yMDUwMDUxNjA5MDc0MFowNjE0 +MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTGl2ZSBQYXRjaCBTaWduaW5nIDIwMjUg +S21vZDCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBALipA0cue8aGFvS3 +qE07BfbEdTXpIopOQAaJFX+tmbvmkJNhyBbPLgAbgTb9zDF7l3mNXtJN0y+rNS10 +SJiz2XX5u+HyP2tt3OS77vWq94qMeqgL37H41gQTJ+kaqsJN0jU6vAbXg3/oxBxj +izr/DguJbk9f6q143zer+VUd+24ppCJD0ZsSHrKEIxvSOJG4qGwcWTz/TKkYztB/ +He8Ez4roKbJLaA2SMrycXY8K0d1NJbo6jGpIWx6cARCZwac07mjsodMmvkXItJes +iqp+E6blQ/EbP6GACtKp5/J3yuH1KTbfdYp+AtYXqkYSuVHwa8oi+AXe1gJHdgyI +8caQRJlYccdiHiuUxSuO3Mp7p73NOI9Oc22wm058Eh9cxWLWgsbSeAlS3Nd4LiPQ +Yx99d5HIP2Z6IIrPcAkPosCCpULZvtxfeHP3+jxwR3s5d4lab++DCckbIVOJfBC/ +mZwFOTIehDulhH7vCG2wsDFh1hqq3XrWEALmcgLlQL8Huc1h0VUEms0Cc0HB3yAw +EpfKoYMal4qSHEdcCmDaQTvmDiyCzkVlgbpFoWbM76tlXOWoDIbd/IZU8zd8iakM ++jragsmQmR4dZkTe08XUC9oV+NjUYytObyTpwtd0nCmRnyU5jXcVjMuOreOACup5 +BHKdUQEYrjVR75V5OMTbmVBHYjjpAgMBAAGjfjB8MAwGA1UdEwEB/wQCMAAwCwYD +VR0PBAQDAgeAMB0GA1UdDgQWBBTVQc72Hcfnk7frfomZcKLu8LXcjDAfBgNVHSME +GDAWgBTVQc72Hcfnk7frfomZcKLu8LXcjDAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGSCBABAjANBgkqhkiG9w0BAQ0FAAOCAgEAQJ1bcGb+nJnr7Xhhvtpn2qyA +qMJ4kfiQEb6faue/edwRDMeD6BPEHLb+8Od9GhKXXRlWnBASHrkZiDCVxDsvqpFv +wZ5oSvRc76FRtaObWD/irlwppsQw/WULzIyZlTNhxgf6w70aV4DlQ5cu81zWHrcj +n1gQGSRGnvj9LI6I5+zvFUt6as6wJcABxSGDGtWJDJCGrdQ+bii/bCGR/7mp79Ss +3nxnweTtdSYV/11nOSQtFVchCXblhfNF6L+xwDkrgzQa9T8frgeMgh/U3JXATvN/ +rNuPLNuk1CpMjN7mW4T836N02Nyckx9byTO1s30rpE16u3OS/43pnsen0g2Duywv +R1EVXG3bmtOebiWQAeYJvaLQHs+jEiINVnC/ieS+Ynac2fXIAVWVAlehZ1mIl1f2 +u43JQNXjYE9D3UmQ+qVtCJayTd2nxuNcBrqvjDCd1aWwq8Tl8wlHBbqbRvQmcDv6 +2qUKR86+Q4frc2M7zUF6eKD2fcU3+7smO7PnREkGjBQD/LNGVDsNVwIImXloopxi +lU2sjhlDTo8tUvqRyngGorejZm1nCxPusQE44HysmhYnNvFFg13r1s1lP1aa01bE +FVWyZMoTyzEefgOFaGFAAplLJQFojZfMORpUG+VROI7OZnRhXof0MX0Nvp0B4bNc +vBrQ6l6yyO6XNLyfu5g= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/certs/canonical-livepatch-all.pem +++ linux-nvidia-7.0.0/debian/certs/canonical-livepatch-all.pem @@ -0,0 +1,121 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + c7:7e:51:6a:1c:25:cd:40 + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN = Canonical Ltd. Live Patch Signing + Validity + Not Before: Jul 18 23:41:27 2016 GMT + Not After : Jul 16 23:41:27 2026 GMT + Subject: CN = Canonical Ltd. Live Patch Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + RSA Public-Key: (4096 bit) + Modulus: + 00:bd:74:ee:72:b3:4a:ab:e6:31:e8:29:24:c2:bd: + 46:98:32:c0:39:ee:a3:fb:8a:ad:fe:ab:1a:5b:a3: + 2e:a1:80:db:79:61:9e:47:79:2c:75:57:a2:21:f0: + 93:f6:87:f2:9b:4b:9d:2f:b3:58:61:28:3c:41:70: + 13:16:a1:72:90:c9:d5:16:71:7c:e0:30:f9:28:5e: + 48:20:36:00:69:b7:59:9f:a3:ec:a8:eb:55:41:9f: + 38:1e:22:4a:57:20:f4:83:59:49:c5:00:93:d3:33: + 02:92:d1:fc:f0:84:3b:4a:5b:8f:b6:73:9a:89:fa: + 30:1e:e6:2a:68:f2:91:ef:59:57:3d:dc:1c:52:6f: + 5e:e6:9b:b5:b8:7c:98:c9:13:d1:39:68:01:67:91: + e0:d3:67:72:16:0a:5e:16:83:45:31:4f:b5:2b:b3: + f6:40:86:89:3a:84:6e:6f:16:61:bc:70:84:be:5a: + 13:36:7b:82:ea:07:19:fc:18:c1:16:c6:32:0b:7d: + 2c:6b:c4:21:b9:38:6b:31:dc:d9:0c:ad:56:40:68: + 7c:e3:c6:64:8e:bf:1c:e0:72:3e:6c:db:d2:73:79: + da:d7:c5:2f:5d:04:7d:b0:07:1e:95:dd:2a:47:5e: + bf:3e:3a:c8:66:f6:67:0f:d4:2a:f1:e2:71:59:d2: + 6c:7b:a0:37:ac:e6:97:80:30:13:97:48:d5:74:fc: + 38:68:e4:57:cb:99:69:5a:84:27:ac:98:51:e4:64: + bd:91:62:e8:58:27:06:2a:b9:0b:b8:08:e5:e5:b4: + 51:a7:a2:10:df:4e:07:6c:a0:3b:96:f2:6e:df:75: + 8c:97:1e:64:a0:9a:86:9b:98:26:f9:d8:b7:de:5b: + 21:b7:af:89:01:a3:f7:98:6b:da:19:ba:86:ef:ef: + f1:ce:bb:2f:89:ed:c0:b6:1b:e5:5b:f8:90:11:9a: + 52:93:e9:be:f7:35:b9:08:cb:ba:c3:ed:2f:73:af: + cc:96:07:55:b5:de:f6:03:f6:f1:89:f9:21:40:76: + c1:69:f2:61:cc:9a:94:df:9c:ec:6a:65:38:be:d1: + 4e:2a:87:c7:2f:3e:53:ae:8b:9f:54:a1:09:59:64: + 25:aa:a9:d8:44:a9:a8:a0:71:e1:32:aa:4c:32:fd: + 44:28:cc:9c:6f:8e:db:81:7e:6f:fa:00:56:c5:e5: + 03:46:63:fb:8e:71:8d:e3:13:91:9f:ac:60:3e:64: + f3:df:25:34:09:fa:2d:96:9f:16:05:ea:93:f5:e6: + 00:08:27:32:7b:3c:bd:ee:70:24:6c:3b:55:e9:db: + f4:10:2d:20:06:b4:ca:e9:29:65:55:ad:f6:52:54: + 5f:e5:a3 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 14:DF:34:D1:A8:7C:F3:76:25:AB:EC:03:9E:F2:BF:52:12:49:B9:69 + X509v3 Authority Key Identifier: + keyid:14:DF:34:D1:A8:7C:F3:76:25:AB:EC:03:9E:F2:BF:52:12:49:B9:69 + + Signature Algorithm: sha512WithRSAEncryption + 30:e7:48:02:37:e9:28:cf:04:a2:4d:5c:fa:d8:4e:c9:76:c7: + 14:3f:bd:2c:51:3d:33:f0:1a:bc:49:f1:47:95:8f:69:d8:a9: + 54:14:44:6c:4d:9f:55:82:08:1e:c6:5b:d5:91:d9:bc:2e:b0: + af:d6:25:65:74:96:aa:36:de:ae:31:a8:11:f2:a4:2c:5a:e1: + 4f:73:f8:4a:c3:35:b0:76:96:71:f2:b5:7d:4b:75:ee:5d:bf: + 86:a5:ba:0b:a9:52:cb:ec:ab:e5:23:4b:f2:74:55:28:17:1e: + b3:ac:27:ad:45:13:6e:69:b3:5a:be:42:36:29:48:db:e7:5c: + 22:58:a0:90:82:2c:2a:21:2b:db:f4:64:b7:91:5d:1f:2c:48: + a4:1a:85:e3:86:a5:aa:19:cd:19:e8:a5:fb:a3:7b:94:77:48: + 25:a4:cf:a0:cf:71:82:5c:6f:71:22:7c:d6:97:a0:53:bb:ec: + 30:f6:cb:16:fb:7b:fd:16:94:7a:53:6e:bd:04:64:a2:01:10: + 9f:f0:5b:b5:a6:73:41:9d:5f:6f:45:73:0d:05:f7:30:6d:39: + 90:b6:7d:55:7d:4c:2f:ae:5f:38:56:2f:8b:df:f4:bf:12:06: + 93:6e:0d:02:23:bf:71:91:57:88:e8:bd:62:72:99:00:40:29: + 1e:c9:13:11:da:7e:8e:e1:d2:a5:0d:bf:f7:d6:ec:01:0d:89: + 41:cd:d5:dc:d2:f7:5f:33:0d:4c:2f:85:b7:85:b7:81:e4:17: + 29:f0:74:cf:0e:15:8c:1a:50:0b:08:63:1a:91:4f:e7:76:97: + f1:d4:3b:7e:72:d4:c5:45:58:0c:6a:e9:0d:f2:85:d8:91:1e: + 37:bd:78:e3:39:4d:2e:fd:85:31:c1:a6:3b:6a:cc:2c:53:72: + 1d:8e:7b:f0:e6:76:86:09:6f:1a:f3:e4:a1:e2:dd:76:5f:b0: + 8c:e2:2a:54:5d:c1:88:49:90:10:15:42:7d:05:24:53:8c:54: + ff:48:18:1a:36:e3:31:d3:54:32:78:0d:fe:f2:3d:aa:0d:37: + 15:84:b4:36:47:31:e8:85:6e:0b:58:38:ff:21:91:09:c9:a8: + 43:a3:ea:60:cb:7e:ed:f7:41:6f:4e:91:c1:fd:77:46:e7:d4: + e7:86:c0:1b:fd:50:6c:aa:be:00:b3:63:02:ff:4e:c7:a5:57: + 6e:29:64:e9:54:d5:30:63:38:5f:2d:5a:db:49:5f:14:14:22: + d2:81:1f:61:9e:ee:ee:16:66:d6:bc:bd:ac:1b:5c:fb:38:31: + 95:33:2e:84:6e:7a:de:ee:b9:fc:97:17:06:13:bf:70:1c:6e: + 76:ed:66:38:e2:70:08:00 +-----BEGIN CERTIFICATE----- +MIIFODCCAyCgAwIBAgIJAMd+UWocJc1AMA0GCSqGSIb3DQEBDQUAMCwxKjAoBgNV +BAMMIUNhbm9uaWNhbCBMdGQuIExpdmUgUGF0Y2ggU2lnbmluZzAeFw0xNjA3MTgy +MzQxMjdaFw0yNjA3MTYyMzQxMjdaMCwxKjAoBgNVBAMMIUNhbm9uaWNhbCBMdGQu +IExpdmUgUGF0Y2ggU2lnbmluZzCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoC +ggIBAL107nKzSqvmMegpJMK9RpgywDnuo/uKrf6rGlujLqGA23lhnkd5LHVXoiHw +k/aH8ptLnS+zWGEoPEFwExahcpDJ1RZxfOAw+SheSCA2AGm3WZ+j7KjrVUGfOB4i +Slcg9INZScUAk9MzApLR/PCEO0pbj7Zzmon6MB7mKmjyke9ZVz3cHFJvXuabtbh8 +mMkT0TloAWeR4NNnchYKXhaDRTFPtSuz9kCGiTqEbm8WYbxwhL5aEzZ7guoHGfwY +wRbGMgt9LGvEIbk4azHc2QytVkBofOPGZI6/HOByPmzb0nN52tfFL10EfbAHHpXd +Kkdevz46yGb2Zw/UKvHicVnSbHugN6zml4AwE5dI1XT8OGjkV8uZaVqEJ6yYUeRk +vZFi6FgnBiq5C7gI5eW0UaeiEN9OB2ygO5bybt91jJceZKCahpuYJvnYt95bIbev +iQGj95hr2hm6hu/v8c67L4ntwLYb5Vv4kBGaUpPpvvc1uQjLusPtL3OvzJYHVbXe +9gP28Yn5IUB2wWnyYcyalN+c7GplOL7RTiqHxy8+U66Ln1ShCVlkJaqp2ESpqKBx +4TKqTDL9RCjMnG+O24F+b/oAVsXlA0Zj+45xjeMTkZ+sYD5k898lNAn6LZafFgXq +k/XmAAgnMns8ve5wJGw7Venb9BAtIAa0yukpZVWt9lJUX+WjAgMBAAGjXTBbMAwG +A1UdEwEB/wQCMAAwCwYDVR0PBAQDAgeAMB0GA1UdDgQWBBQU3zTRqHzzdiWr7AOe +8r9SEkm5aTAfBgNVHSMEGDAWgBQU3zTRqHzzdiWr7AOe8r9SEkm5aTANBgkqhkiG +9w0BAQ0FAAOCAgEAMOdIAjfpKM8Eok1c+thOyXbHFD+9LFE9M/AavEnxR5WPadip +VBREbE2fVYIIHsZb1ZHZvC6wr9YlZXSWqjberjGoEfKkLFrhT3P4SsM1sHaWcfK1 +fUt17l2/hqW6C6lSy+yr5SNL8nRVKBces6wnrUUTbmmzWr5CNilI2+dcIligkIIs +KiEr2/Rkt5FdHyxIpBqF44alqhnNGeil+6N7lHdIJaTPoM9xglxvcSJ81pegU7vs +MPbLFvt7/RaUelNuvQRkogEQn/BbtaZzQZ1fb0VzDQX3MG05kLZ9VX1ML65fOFYv +i9/0vxIGk24NAiO/cZFXiOi9YnKZAEApHskTEdp+juHSpQ2/99bsAQ2JQc3V3NL3 +XzMNTC+Ft4W3geQXKfB0zw4VjBpQCwhjGpFP53aX8dQ7fnLUxUVYDGrpDfKF2JEe +N7144zlNLv2FMcGmO2rMLFNyHY578OZ2hglvGvPkoeLddl+wjOIqVF3BiEmQEBVC +fQUkU4xU/0gYGjbjMdNUMngN/vI9qg03FYS0Nkcx6IVuC1g4/yGRCcmoQ6PqYMt+ +7fdBb06Rwf13RufU54bAG/1QbKq+ALNjAv9Ox6VXbilk6VTVMGM4Xy1a20lfFBQi +0oEfYZ7u7hZm1ry9rBtc+zgxlTMuhG563u65/JcXBhO/cBxudu1mOOJwCAA= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/certs/ubuntu-drivers-2025-all.pem +++ linux-nvidia-7.0.0/debian/certs/ubuntu-drivers-2025-all.pem @@ -0,0 +1,125 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + 2c:af:80:6d:b1:e0:8b:9f:49:90:7b:b2:39:4e:b3:c7:88:0e:44:53 + Signature Algorithm: sha512WithRSAEncryption + Issuer: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod + Validity + Not Before: Nov 21 12:32:19 2025 GMT + Not After : Nov 21 12:32:19 2050 GMT + Subject: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (4096 bit) + Modulus: + 00:9e:20:bd:0d:2d:bd:af:fe:e2:68:a3:8e:fe:2b: + 50:21:08:03:3a:32:71:d5:35:ac:d0:0a:07:ae:f4: + dc:a2:8d:2f:c6:0d:2a:6b:ac:ef:84:72:d5:df:91: + 52:cf:76:01:b3:29:e1:ba:9f:5b:9f:f0:92:b7:03: + 65:80:ca:d0:aa:6d:26:28:07:8b:2c:19:9e:87:e9: + 5f:58:5c:aa:ad:3c:be:71:3a:2d:d6:79:72:23:7e: + bf:f3:39:48:c6:d0:2f:7f:c2:79:0e:35:51:c9:4f: + e9:bf:80:06:75:5e:76:30:c0:96:83:4a:79:f3:3a: + 9e:30:e5:0e:9d:b6:86:c3:7c:6a:eb:4d:4c:5c:0b: + e1:a8:48:b2:e4:f4:62:64:55:7b:f0:5b:10:15:07: + 51:89:e4:98:7e:7b:58:c0:38:dc:03:7e:ba:1a:0e: + c2:12:b0:1e:93:f1:dc:7d:8f:85:7d:d0:7f:d6:ef: + e6:6c:90:03:d9:85:a5:a1:43:20:af:b1:89:75:d4: + e7:af:63:b1:ba:0d:a3:a4:5e:29:a4:5c:f0:bf:9a: + c8:7e:c3:da:60:d4:ae:ad:13:3f:cc:4b:64:73:3d: + 59:3f:8b:91:7f:8c:fe:e6:4b:2f:e3:04:2b:e3:ae: + 0d:6f:8b:55:b9:e9:1b:67:37:25:9d:43:d3:70:b5: + 01:e8:d9:de:11:9a:b8:c9:5b:ba:b0:0c:6a:9f:9b: + fe:79:e3:a9:27:90:1d:56:95:84:8b:eb:96:a1:47: + 83:28:3c:d0:ea:81:7e:fe:a2:90:3d:84:02:5e:bc: + 68:0b:70:69:36:18:32:53:e3:4a:e1:c5:0d:dc:d6: + cd:3f:c0:1a:27:28:db:96:0a:ce:01:03:0d:8e:9e: + 38:e1:04:85:38:ad:f7:1f:10:40:b5:b1:d5:85:bd: + e6:62:b1:3c:f0:ac:8f:8a:88:62:46:cc:bf:64:9b: + e7:b6:c0:68:3e:96:14:54:6c:76:08:8d:6a:fd:08: + 4b:8e:0b:0e:ca:84:8a:17:60:fb:12:c7:f2:27:49: + 9b:b8:ff:a9:3f:70:5f:98:51:be:96:f1:0d:bf:1d: + 0e:c3:c7:34:5e:b3:35:e7:ff:43:e4:0e:7a:86:08: + d6:13:a6:6f:48:4a:d6:f5:61:cb:ba:29:e6:54:ac: + c9:c0:32:5e:fe:72:b2:e1:c4:e4:d9:ec:6a:1e:f2: + 5f:cc:db:44:30:42:79:ca:c8:d1:86:28:3b:3a:50: + d0:71:81:5f:ab:fb:f1:2f:65:df:8e:a4:7c:96:5c: + 46:c3:fc:b0:fd:3d:b1:38:cf:85:15:a6:da:ce:a9: + a3:b0:76:6a:4b:8a:4c:25:ce:c2:3d:fc:01:11:24: + 1d:c7:f9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 46:27:60:3D:23:57:A2:A3:F8:10:06:37:08:94:C2:21:17:58:93:E9 + X509v3 Authority Key Identifier: + 46:27:60:3D:23:57:A2:A3:F8:10:06:37:08:94:C2:21:17:58:93:E9 + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.2312.16.1.2 + Signature Algorithm: sha512WithRSAEncryption + Signature Value: + 21:a6:29:45:48:fc:42:37:12:b8:71:af:06:9e:2a:63:91:19: + 7b:52:a5:c9:2a:63:66:36:94:3f:2b:ac:f7:01:7e:04:48:92: + 7c:33:66:94:c8:c0:c3:1e:a4:f4:10:d2:4a:67:1a:10:64:15: + dd:70:86:8c:4d:ef:a9:c2:09:bc:44:9b:83:06:7c:ce:b3:2f: + 09:9f:32:51:dd:f9:e6:87:96:c7:3f:08:e1:8f:ed:4d:b0:39: + 02:9c:c0:86:40:28:56:59:5c:1d:11:af:a8:ad:49:e8:91:a0: + 31:a2:e8:c4:5e:88:c4:31:c3:d4:6f:3f:5a:94:c7:6e:b8:2a: + 74:27:90:12:c6:1f:35:87:32:31:e9:38:14:d9:09:c3:42:e6: + e7:f7:8f:46:22:a1:c9:12:0c:34:1a:7c:d0:6b:e5:c7:42:49: + 3f:7d:c9:bb:38:65:e3:93:16:1b:ae:48:6c:29:53:ec:1a:a0: + 75:3f:3e:e4:a7:30:59:79:e7:8d:4b:76:06:8d:f5:4b:97:06: + 0a:af:0e:0b:7b:37:8c:9d:86:3d:92:40:cf:2d:87:ca:5c:66: + 01:9b:bd:42:99:5c:4b:39:91:0e:8f:db:d3:2b:57:fe:4a:17: + a0:10:17:e4:39:f1:a1:28:1b:51:53:9c:cf:95:4e:23:55:e3: + 24:2b:2e:dc:ed:cb:9c:1a:fb:64:f6:05:be:c4:71:70:62:af: + 52:2d:64:9f:4b:f0:87:5d:5d:53:8d:41:2e:6a:81:2a:e2:fb: + 55:89:7d:70:93:eb:59:61:b1:f7:75:64:0e:6c:f7:eb:b9:d4: + 83:08:20:29:9c:03:0b:5b:d5:8f:de:4e:bd:e0:d9:c2:c5:01: + 03:9d:a5:3a:db:2b:f2:32:89:67:0e:ec:32:a4:74:bd:fb:f8: + 0e:b4:cf:cd:5e:49:bb:02:2d:d1:0c:3d:2f:d7:22:e4:89:4c: + 6a:3c:e5:ce:6d:21:68:7e:74:2e:35:5e:3b:9a:44:3b:a5:54: + 9a:3c:be:df:5d:e2:f6:dd:1c:bd:f8:05:99:82:2f:16:4d:6e: + f6:37:8b:77:3f:81:2f:10:a6:4c:04:67:a4:58:34:0d:5d:6f: + e4:2a:c4:c2:be:00:f1:8e:8b:85:98:77:48:8a:47:21:2e:ff: + cc:55:6d:8c:f2:ec:3e:14:75:a5:7d:0c:24:40:b6:54:49:30: + 84:1a:62:b2:19:60:42:3c:a4:3f:bc:fc:21:f6:1d:19:83:cc: + f8:cb:08:2a:15:49:c8:35:8f:bd:14:c3:22:92:c9:5b:84:88: + 50:01:db:10:08:4b:24:08:00:c4:60:76:be:e8:62:e2:0c:bd: + 9a:28:3c:70:86:9c:dd:94 +-----BEGIN CERTIFICATE----- +MIIFgDCCA2igAwIBAgIULK+AbbHgi59JkHuyOU6zx4gORFMwDQYJKoZIhvcNAQEN +BQAwOTE3MDUGA1UEAwwuQ2Fub25pY2FsIEx0ZC4gS2VybmVsIE1vZHVsZSBTaWdu +aW5nIDIwMjUgS21vZDAgFw0yNTExMjExMjMyMTlaGA8yMDUwMTEyMTEyMzIxOVow +OTE3MDUGA1UEAwwuQ2Fub25pY2FsIEx0ZC4gS2VybmVsIE1vZHVsZSBTaWduaW5n +IDIwMjUgS21vZDCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAJ4gvQ0t +va/+4mijjv4rUCEIAzoycdU1rNAKB6703KKNL8YNKmus74Ry1d+RUs92AbMp4bqf +W5/wkrcDZYDK0KptJigHiywZnofpX1hcqq08vnE6LdZ5ciN+v/M5SMbQL3/CeQ41 +UclP6b+ABnVedjDAloNKefM6njDlDp22hsN8autNTFwL4ahIsuT0YmRVe/BbEBUH +UYnkmH57WMA43AN+uhoOwhKwHpPx3H2PhX3Qf9bv5myQA9mFpaFDIK+xiXXU569j +sboNo6ReKaRc8L+ayH7D2mDUrq0TP8xLZHM9WT+LkX+M/uZLL+MEK+OuDW+LVbnp +G2c3JZ1D03C1AejZ3hGauMlburAMap+b/nnjqSeQHVaVhIvrlqFHgyg80OqBfv6i +kD2EAl68aAtwaTYYMlPjSuHFDdzWzT/AGico25YKzgEDDY6eOOEEhTit9x8QQLWx +1YW95mKxPPCsj4qIYkbMv2Sb57bAaD6WFFRsdgiNav0IS44LDsqEihdg+xLH8idJ +m7j/qT9wX5hRvpbxDb8dDsPHNF6zNef/Q+QOeoYI1hOmb0hK1vVhy7op5lSsycAy +Xv5ysuHE5Nnsah7yX8zbRDBCecrI0YYoOzpQ0HGBX6v78S9l346kfJZcRsP8sP09 +sTjPhRWm2s6po7B2akuKTCXOwj38AREkHcf5AgMBAAGjfjB8MAwGA1UdEwEB/wQC +MAAwCwYDVR0PBAQDAgeAMB0GA1UdDgQWBBRGJ2A9I1eio/gQBjcIlMIhF1iT6TAf +BgNVHSMEGDAWgBRGJ2A9I1eio/gQBjcIlMIhF1iT6TAfBgNVHSUEGDAWBggrBgEF +BQcDAwYKKwYBBAGSCBABAjANBgkqhkiG9w0BAQ0FAAOCAgEAIaYpRUj8QjcSuHGv +Bp4qY5EZe1KlySpjZjaUPyus9wF+BEiSfDNmlMjAwx6k9BDSSmcaEGQV3XCGjE3v +qcIJvESbgwZ8zrMvCZ8yUd355oeWxz8I4Y/tTbA5ApzAhkAoVllcHRGvqK1J6JGg +MaLoxF6IxDHD1G8/WpTHbrgqdCeQEsYfNYcyMek4FNkJw0Lm5/ePRiKhyRIMNBp8 +0Gvlx0JJP33Juzhl45MWG65IbClT7BqgdT8+5KcwWXnnjUt2Bo31S5cGCq8OC3s3 +jJ2GPZJAzy2HylxmAZu9QplcSzmRDo/b0ytX/koXoBAX5DnxoSgbUVOcz5VOI1Xj +JCsu3O3LnBr7ZPYFvsRxcGKvUi1kn0vwh11dU41BLmqBKuL7VYl9cJPrWWGx93Vk +Dmz367nUgwggKZwDC1vVj95OveDZwsUBA52lOtsr8jKJZw7sMqR0vfv4DrTPzV5J +uwIt0Qw9L9ci5IlMajzlzm0haH50LjVeO5pEO6VUmjy+313i9t0cvfgFmYIvFk1u +9jeLdz+BLxCmTARnpFg0DV1v5CrEwr4A8Y6LhZh3SIpHIS7/zFVtjPLsPhR1pX0M +JEC2VEkwhBpishlgQjykP7z8IfYdGYPM+MsIKhVJyDWPvRTDIpLJW4SIUAHbEAhL +JAgAxGB2vuhi4gy9mig8cIac3ZQ= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/certs/ubuntu-drivers-all.pem +++ linux-nvidia-7.0.0/debian/certs/ubuntu-drivers-all.pem @@ -0,0 +1,125 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: + e9:df:13:0f:92:92:a9:b7 + Signature Algorithm: sha512WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Kernel Module Signing + Validity + Not Before: May 31 16:06:09 2016 GMT + Not After : May 29 16:06:09 2026 GMT + Subject: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Kernel Module Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + RSA Public-Key: (4096 bit) + Modulus: + 00:b3:b0:4f:c6:0a:77:8b:f9:d1:53:33:34:d2:80: + b5:63:6f:e1:f6:a2:83:99:d5:b6:b1:e4:99:91:fa: + 6c:19:c6:d0:91:2a:b9:7d:b5:98:a6:0d:28:01:b8: + 7c:8e:aa:38:ec:51:37:33:96:f0:b0:9b:8d:86:5f: + 67:23:69:2f:d7:c2:f3:fb:c5:d7:f9:04:ff:f2:e5: + 61:68:b7:29:b9:c6:8e:4b:4d:2d:8f:92:0c:00:b3: + a3:d2:5a:08:64:cd:f2:09:0b:a5:0e:e6:64:75:d5: + 41:f4:4d:49:3a:0d:dc:b9:27:8e:c4:d6:b1:df:8f: + 6c:f0:e4:f7:31:cb:a9:04:a1:f9:a7:aa:15:da:59: + 03:4d:46:14:d0:dd:bf:e0:f5:9e:f0:71:0c:70:78: + 2b:08:fb:e0:b6:68:a4:74:12:9d:f7:f2:64:88:17: + 2a:8a:ed:1a:91:b5:6c:13:bd:4c:10:0a:0b:72:0b: + 90:db:7d:f3:78:44:4c:d2:a5:41:f7:1c:77:7d:5a: + 8a:54:bc:8f:fe:b7:ee:e1:bc:59:37:c4:d4:e8:14: + d0:5b:42:9b:04:00:8e:6d:83:8a:25:21:5b:08:c4: + 7b:b2:d9:99:52:c9:5e:59:6d:c4:aa:52:59:e2:e4: + 2f:7e:7e:ac:05:01:99:bf:13:72:b7:45:c5:17:da: + 8a:d5:3e:71:73:2e:d8:aa:e6:eb:5a:d0:9a:c4:93: + f3:be:eb:d2:47:25:34:16:29:fa:dd:9a:2f:b1:20: + e5:41:4e:ed:ea:51:7c:23:80:ba:3d:b5:3a:0b:8c: + 9c:85:48:6c:3c:8b:29:2f:2f:12:c7:52:34:02:ea: + 0f:ac:53:23:3c:f8:3e:40:1b:30:63:e9:2d:e6:f6: + 58:cc:51:f9:eb:08:4a:b4:c7:16:80:d1:8b:c2:64: + 6a:71:a9:70:31:a4:a7:3a:c0:93:99:1b:0e:42:c1: + 00:6d:43:27:99:6c:e5:fd:23:16:c1:8e:b5:66:17: + 2b:4c:53:5a:6d:1e:96:16:13:6a:c6:d4:85:5b:74: + 2e:ce:7c:45:2f:ad:cb:75:9e:5e:91:bd:9a:6a:86: + 1a:06:bd:39:be:a3:50:56:ea:e1:f6:e3:95:69:d7: + 31:e4:66:f7:36:b5:51:c2:22:b4:9c:74:9c:44:0b: + 0e:16:5f:53:f0:23:c6:b9:40:bd:d6:b8:7d:1b:f6: + 73:f6:27:e7:c0:e3:65:a0:58:ab:5c:59:b7:80:8c: + 8c:04:b4:a9:ae:a0:51:40:10:3b:63:59:49:87:d1: + 9b:df:a3:8c:c4:2e:eb:70:c1:0a:18:1f:cb:22:c2: + f2:4a:65:0d:e5:81:74:d8:ce:72:c6:35:be:ba:63: + 72:c4:f9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Key Usage: + Digital Signature + X509v3 Subject Key Identifier: + 88:F7:52:E5:60:A1:E0:73:7E:31:16:3A:46:6A:D7:B7:0A:85:0C:19 + X509v3 Authority Key Identifier: + keyid:88:F7:52:E5:60:A1:E0:73:7E:31:16:3A:46:6A:D7:B7:0A:85:0C:19 + + Signature Algorithm: sha512WithRSAEncryption + 04:85:16:27:58:ba:71:28:57:86:7b:c2:83:db:e5:72:6f:1e: + b2:1c:63:b0:db:ad:c0:42:96:c0:4f:65:f6:35:4d:c0:07:0d: + 46:be:d3:1e:ec:f1:22:18:2a:18:5d:bb:69:a6:a6:d4:0d:c3: + 57:03:b9:e7:45:49:28:ca:6d:98:17:68:97:cb:7b:36:81:0a: + 37:9e:34:79:f3:e1:0e:5b:77:43:bb:5a:a5:45:b7:16:50:86: + fd:12:a4:96:0f:15:19:09:1c:e1:fa:80:a5:80:09:be:bb:c8: + 26:0b:3e:de:03:d2:c2:18:a4:8d:0d:de:c5:32:82:0b:fb:75: + 55:66:1a:2a:bb:e4:bd:25:91:20:15:d4:be:b8:3f:53:e3:fb: + a8:c3:55:e3:d5:e7:82:18:95:df:39:09:a7:fc:89:6e:b4:1c: + aa:2d:e8:67:c2:0d:34:34:3e:f9:fa:0b:ce:81:92:11:ae:12: + 0a:fe:35:63:ce:46:29:c4:2b:4f:cb:4e:05:0a:a1:11:e2:35: + f6:5a:5d:b5:e8:d2:6f:4c:fc:3d:24:a6:03:4b:dd:98:6b:f2: + 71:58:16:1d:a5:25:ef:d9:06:7c:e8:db:7b:88:6a:89:5c:59: + 01:92:64:db:44:08:63:6c:7c:32:d6:55:98:63:09:26:61:67: + 0a:fe:5d:ee:fd:23:59:b3:4d:91:c1:4d:41:8b:cd:20:58:fa: + 2d:45:e5:bd:1d:69:5c:03:a0:49:a6:97:54:13:b6:c9:e0:f8: + 56:83:a1:2a:c3:f4:6c:fd:ab:20:ca:3d:9c:95:c0:cf:04:bb: + 46:39:cf:34:81:65:45:27:64:01:7d:62:b3:b8:72:ea:10:d5: + 0f:53:7d:39:88:25:09:6f:8c:bc:e0:49:bb:39:e2:0e:8d:cf: + 56:4d:c1:82:6d:87:d2:e7:fc:c0:9f:a7:65:60:d2:6c:65:18: + 59:38:6e:d0:9c:d7:c3:81:9a:9a:29:8f:83:84:c3:b5:44:ff: + 28:ac:13:17:64:f2:26:13:d9:55:06:b7:69:68:7c:bf:ec:d1: + 8c:ef:b7:da:76:e1:07:73:c6:31:62:31:cb:b6:e1:e7:7f:0c: + c3:f7:4c:52:be:25:36:8e:a1:bb:60:02:c3:cb:3e:6f:29:fc: + 7f:6a:fa:f8:ec:0a:df:49:e2:57:0e:bc:bd:93:c3:1b:d5:36: + 8a:ff:d8:1b:17:c7:1f:cb:69:00:d2:54:9e:ad:61:89:92:95: + 11:f8:ea:17:83:9f:9b:09:7d:b8:94:a4:ea:f5:ae:ea:dc:dd: + 62:b9:9e:68:9c:18:ec:19:c4:13:08:c8:b1:62:ab:8e:84:69: + 11:3c:da:ea:0d:b7:22:bd +-----BEGIN CERTIFICATE----- +MIIF2jCCA8KgAwIBAgIJAOnfEw+Skqm3MA0GCSqGSIb3DQEBDQUAMH0xCzAJBgNV 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+sWKrjoRpETza6g23Ir0= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/changelog +++ linux-nvidia-7.0.0/debian/changelog @@ -0,0 +1,1006 @@ +linux-nvidia (7.0.0-1006.6) resolute; urgency=medium + + * resolute/linux-nvidia: 7.0.0-1006.6 -proposed tracker (LP: #2148214) + + [ Ubuntu: 7.0.0-14.14 ] + + * resolute/linux: 7.0.0-14.14 -proposed tracker (LP: #2148159) + * support vflip/hflip for Sony IMX471 camera sensor (LP: #2138841) + - SAUCE: media: ipu-bridge: add TBE20A0 ACPI id for Sony IMX471 + * AA: disable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED (LP: #2147533) + - [Config] disable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED + * System doesn't response with mt76 call trace (LP: #2137448) + - wifi: mt76: mt792x: Fix a potential deadlock in high-load situations + * The second tbt storage plugged on the dock will not be recognized + (LP: #2139572) + - SAUCE: thunderbolt: Fix PCIe device enumeration with delayed rescan + * dma-buf filesystem flags fix (LP: #2139656) + - SAUCE: dma-buf: set SB_I_NOEXEC and SB_I_NODEV on dmabuf filesystem + * Bluetooth device (MT7925) not detected on USB bus with linux-oem-6.17 + (LP: #2145164) + - SAUCE: USB: hub: call ACPI _PRR reset during port power-cycle on + enumeration failure + * drm/i915/lnl+/tc: Fix false disconnect of active DP-alt TC port during + long HPD pulse (LP: #2143879) + - SAUCE: drm/i915/lnl+/tc: Fix false disconnect of active DP-alt TC port + during long HPD pulse + * i915 WARN_ON call trace during CB/WB on MTL/ARL platforms (LP: #2144537) + - SAUCE: drm/i915/xelpdp/tc: Convert TCSS power check WARN to a debug + message + * Miscellaneous Ubuntu changes + - [Packaging] Add support for per-flavour depends + - [Packaging] Don't hard-code lmm zfs dependency + - [Config] updateconfigs following v7.0 release + + [ Ubuntu: 7.0.0-13.13 ] + + * resolute/linux: 7.0.0-13.13 -proposed tracker (LP: #2147403) + * ubuntu_kselftests:_net/net:gre_gso.sh failing (LP: #2136820) + - SAUCE increase socat timeout in gre_gso.sh + * Canonical Kmod 2025 key rotation (LP: #2147447) + - [Packaging] ubuntu-compatible-signing -- make Ubuntu-Compatible-Signing + extensible + - [Packaging] ubuntu-compatible-signing -- allow consumption of positive + certs + - [Packaging] ubuntu-compatible-signing -- report the livepatch:2025 key + - [Config] prepare for Canonical Kmod key rotation + - [Packaging] ubuntu-compatible-signing -- report the kmod:2025 key + - [Packaging] ensure our cert rollups are always fresh + * On Dell system, the internal OLED display drops to a visibly low FPS after + suspend/resume (LP: #2144712) + - drm/i915/psr: Disable Panel Replay on Dell XPS 14 DA14260 as a quirk + - drm/i915/psr: Fixes for Dell XPS DA14260 quirk + * Realtek RTL8116AF SFP option module fails to get connected (LP: #2116144) + - SAUCE: r8169: add quirk for RTL8116af SerDes + * Miscellaneous Ubuntu changes + - [Config] updateconfigs following v7.0-rc7 rebase + + -- Jacob Martin Tue, 14 Apr 2026 16:19:48 -0500 + +linux-nvidia (7.0.0-1005.5) resolute; urgency=medium + + * resolute/linux-nvidia: 7.0.0-1005.5 -proposed tracker (LP: #2145971) + + * Packaging resync (LP: #1786013) + - [Packaging] update variants + + * Please make dracut the default initrd generator (LP: #2142775) + - [Packaging] recommends dracut instead of initramfs-tools + + [ Ubuntu: 7.0.0-12.12 ] + + * resolute/linux: 7.0.0-12.12 -proposed tracker (LP: #2146778) + * Packaging resync (LP: #1786013) + - [Packaging] update variants + * linux-generic does not run scripts in /usr/share/kernel/*.d (LP: #2147005) + - [Packaging] templates: Use consistent indentation + - [Packaging] templates: Run scripts in /usr/share/kernel/*.d too + * RISC-V kernel config is out of sync with other archs (LP: #1981437) + - [Config] riscv64: Enable COUNTER=m + - [Config] riscv64: Use GENDWARFKSYMS like other architectures + * unconfined profile denies userns_create for chromium based processes + (LP: #1990064) + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + * FFe: add network interface mediation to 26.04 (LP: #2144679) + - SAUCE: apparmor5.0.0 [57/57]: apparmor: add the ability to use interface + in network mediation. + * Jellyfin Desktop Flatpak doesn't work with the current AppArmor profile + (LP: #2142956) + - SAUCE: apparmor5.0.0 [29/57]: apparmor: fix fine grained inet mediation + sock_file_perm + - SAUCE: apparmor5.0.0 [30/57]: apparmor-next 7.1: aapparmor: use target + task's context in apparmor_getprocattr() + - SAUCE: apparmor5.0.0 [31/57]: apparmor-next 7.1: apparmor: return error + on namespace mismatch in verify_header + - SAUCE: apparmor5.0.0 [32/57]: apparmor-next 7.1: apparmor: enable + differential encoding + - SAUCE: apparmor5.0.0 [33/57]: apparmor-next 7.1: apparmor: propagate + -ENOMEM correctly in unpack_table + - SAUCE: apparmor5.0.0 [34/57]: apparmor-next 7.1: apparmor: Replace + memcpy + NUL termination with kmemdup_nul in do_setattr + - SAUCE: apparmor5.0.0 [35/57]: apparmor-next 7.1: apparmor: Remove + redundant if check in sk_peer_get_label + - SAUCE: apparmor5.0.0 [36/57]: apparmor-next 7.1: apparmor: use + __label_make_stale in __aa_proxy_redirect + - SAUCE: apparmor5.0.0 [37/57]: apparmor-next 7.1: apparmor: fix net.h and + policy.h circular include pattern + - SAUCE: apparmor5.0.0 [39/57]: apparmor-next 7.1: apparmor: make include + headers self-contained + - SAUCE: apparmor5.0.0 [40/57]: apparmor-next 7.1: apparmor: Use + sysfs_emit in param_get_{audit,mode} + - SAUCE: apparmor5.0.0 [41/57]: apparmor-next 7.1: apparmor: fix + rawdata_f_data implicit flex array + - SAUCE: apparmor5.0.0 [42/57]: apparmor-next 7.1: apparmor: free rawdata + as soon as possible + - SAUCE: apparmor5.0.0 [43/57]: apparmor-next 7.1: apparmor: Initial + support for compressed policies + - SAUCE: apparmor5.0.0 [44/57]: apparmor-next 7.1: apparmor: fix potential + UAF in aa_replace_profiles + - SAUCE: apparmor5.0.0 [45/57]: apparmor-next 7.1: apparmor: hide unused + get_loaddata_common_ref() function + - SAUCE: apparmor5.0.0 [46/57]: apparmor-next 7.1: apparmor: Fix string + overrun due to missing termination + - SAUCE: apparmor5.0.0 [47/57]: apparmor: fix packed tag on v5 header + struct + - SAUCE: apparmor5.0.0 [48/57]: apparmor: add temporal caching to audit + responses. + - SAUCE: apparmor5.0.0 [49/57]: apparmor: change fn_label_build() call to + not return NULL + - SAUCE: apparmor5.0.0 [50/57]: apparmor: make fn_label_build() capable of + handling not supported + - SAUCE: apparmor5.0.0 [51/57]: apparmor: move netfilter functions next to + the LSM network operations + - SAUCE: apparmor5.0.0 [52/57]: apparmor: move sock_rvc_skb() next to + inet_conn_request + - SAUCE: apparmor5.0.0 [53/57]: apparmor: fix af_unix local addr mediation + binding + - SAUCE: apparmor5.0.0 [54/57]: cleanups of apparmor af_unix mediation + - SAUCE: apparmor5.0.0 [55/57]: apparmor: fix apparmor_secmark_check() + when !inet and secmark defined. + - SAUCE: apparmor5.0.0 [56/57]: apparmor: fix auditing of non-mediation + falures + * snap service cannot change apparmor hat (LP: #2139664) // Jellyfin Desktop + Flatpak doesn't work with the current AppArmor profile (LP: #2142956) + - SAUCE: apparmor5.0.0 [38/57]: apparmor-next 7.1: apparmor: grab ns lock + and refresh when looking up changehat child profiles + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor5.0.0 [28/57]: apparmor: fix aa_label_sk_perm to check + for RULE_MEDIATES_NET + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/57]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/57]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/57]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [4/57]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [5/57]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [6/57]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [7/57]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [8/57]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [9/57]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [10/57]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [12/57]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [13/57]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [14/57]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [15/57]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [16/57]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [19/57]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [20/57]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [21/57]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [22/57]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [23/57]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [24/57]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [25/57]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [26/57]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [27/57]: apparmor: prevent profile->disconnected + double free in aa_free_profile + * update apparmor and LSM stacking patch set (LP: #2028253) // Installation + of AppArmor on a 6.14 kernel produces error message "Illegal number: yes" + (LP: #2102680) + - SAUCE: apparmor5.0.0 [17/57]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [18/57]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [11/57]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + * Enable new Intel WCL soundwire support (LP: #2143301) + - ASoC: sdw_utils: Add CS42L43B codec info + - ASoC: dt-bindings: cirrus, cs42l43: Add CS42L43B variant + - mfd: cs42l43: Add support for the B variant + - ASoC: cs42l43: Add support for the B variant + * Enable audio functions on Dell Huracan/Renegade platforms w/o built-in + microphone (LP: #2143902) + - ASoC: SDCA: Add default value for mipi-sdca-function-reset-max-delay + - ASoC: SDCA: Update counting of SU/GE DAPM routes + - ASoC: SDCA: Improve mapping of Q7.8 SDCA volumes + - ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops + - ASoC: add snd_soc_lookup_component_by_name helper + - ASoC: soc_sdw_utils: partial match the codec name + - ASoC: soc_sdw_utils: remove index from sdca codec name + * [SRU] MIPI camera is not working after upgrading to 6.17-oem + (LP: #2145171) + - SAUCE: ACPI: respect items already in honor_dep before skipping + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Actually enable llvm for perf + * Pull patch in qla2xxx to Resolute (LP: #2144856) + - scsi: qla2xxx: Add support to report MPI FW state + * Ubuntu Resolute Desktop image arm64 - Boot on SC8280XP stalls with gpi-dma + errors (LP: #2142403) + - Revert "arm64: dts: qcom: sc8280xp: Enable GPI DMA" + * 26.04 Snapdragon X Elite: Sync concept kernel changes (LP: #2144643) + - SAUCE: arm64: dts: add missing denali-oled.dtb to Makefile + - SAUCE: dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema + - SAUCE: phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add simple-mfd + compatible + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add optional PHY handle + definitions + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Add support for combo- + mode endpoints + - SAUCE: dt-bindings: media: qcom,x1e80100-camss: Describe iommu entries + - SAUCE: media: qcom: camss: Add legacy_phy flag to SoC definition + structures + - SAUCE: media: qcom: camss: Add support for PHY API devices + - SAUCE: media: qcom: camss: Drop legacy PHY descriptions from x1e + - SAUCE: arm64: dts: qcom: x1e80100: Add CAMCC block definition + - SAUCE: arm64: dts: qcom: x1e80100: Add CCI definitions + - SAUCE: arm64: dts: qcom: x1e80100: Add CAMSS block definition + - SAUCE: arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m + regulators + - SAUCE: arm64: dts: qcom: x1e80100-crd: Add ov08x40 RGB sensor on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Add pm8010 camera PMIC with + voltage levels for IR and RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-t14s: Add on ov02c10 RGB sensor on + CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add pm8010 camera + PMIC with voltage levels for IR and RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add l7b_2p8 + voltage regulator for RGB camera + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add ov02c10 RGB + sensor on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-dell-inspiron14-7441: Switch on CAMSS + RGB sensor + - SAUCE: arm64: dts: qcom: x1-asus-zenbook-a14: Add on OV02C10 RGB sensor + on CSIPHY4 + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: add camera support + - SAUCE: arm64: dts: qcom: x1e78100-t14s: enable camera privacy indicator + - SAUCE: arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: enable camera + privacy indicator + - SAUCE: arm64: dts: qcom: x1e80100-dell-xps13-9345: enable camera privacy + indicator + - SAUCE: dt-bindings: arm: qcom: Add ASUS Vivobook X1P42100 variant + - SAUCE: arm64: dts: qcom: x1-vivobook-s15: create a common dtsi for Hamoa + and Purwa variants + - SAUCE: arm64: dts: qcom: x1-vivobook-s15: add Purwa-compatible device + tree + - SAUCE: firmware: qcom: scm: allow QSEECOM on ASUS Vivobook X1P42100 + variant + - SAUCE: arm64: dts: qcom: hamoa: Move PCIe PERST and Wake GPIOs to port + nodes + - SAUCE: arm64: dts: qcom: x1e-acer-swift-14: Move PCIe PERST and Wake + GPIOs to port nodes + * 25.10 Snapdragon X Elite: Sync concept kernel changes (LP: #2121477) + - SAUCE: wip: arm64: dts: qcom: x1e78100-t14s: enable bluetooth + * Miscellaneous Ubuntu changes + - SAUCE: dt-bindings: arm: qcom: Document HP EliteBook 6 G1q + - SAUCE: firmware: qcom: scm: Allow QSEECOM for HP EliteBook 6 G1q + - SAUCE: arm64: dts: qcom: x1p42100-hp-elitebook-6-g1q: DT for HP + EliteBook 6 G1q + - [Config] PHY_QCOM_MIPI_CSI2=m + - SAUCE: arm64: dts: x1e80100-lenovo-yoga-slim7x: Fix RGB camera supplies + - [Config] toolchain version update + - Update Changes.md after v7.0-rc5 rebase + - [Packaging] update Ubuntu.md + - [Config] enable SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED + - [Packaging] Add linux-main-modules-zfs to linux-modules depends + * Miscellaneous upstream changes + - Revert "UBUNTU: SAUCE: Add Bluetooth support for the Lenovo Yoga Slim + 7x" + + [ Ubuntu: 7.0.0-10.10 ] + + * resolute/linux: 7.0.0-10.10 -proposed tracker (LP: #2144865) + * Miscellaneous upstream changes + - Revert "powerpc: fix KUAP warning in VMX usercopy path" + + [ Ubuntu: 7.0.0-9.9 ] + + * resolute/linux: 7.0.0-9.9 -proposed tracker (LP: #2144735) + * Please make dracut the default initrd generator (LP: #2142775) + - [Packaging] recommends dracut instead of initramfs-tools + * Miscellaneous Ubuntu changes + - SAUCE: Change RISC-V target to RVA23 (riscv64a23-unknown-linux-gnu) + + [ Ubuntu: 7.0.0-8.8 ] + + * resolute/linux: 7.0.0-8.8 -proposed tracker (LP: #2144652) + * UBUNTU: SAUCE: igc: Increase Thunderbolt MAC passthrough delay to 1000ms + (LP: #2143197) + - SAUCE: igc: Increase Thunderbolt MAC passthrough delay to 1000ms + * [usrmerge] evaluate kernel owned packages for DEP17 compliance + (LP: #2139276) + - [Packaging] Install modules in /usr/lib/modules + * Miscellaneous Ubuntu changes + - [Config] hardening: enable LIST_HARDENED + - [Config] hardening: disable LDISC_AUTOLOAD + - [Config] hardening: disable LEGACY_PTYS + - [Config] updateconfigs following v7.0-rc4 rebase + + [ Ubuntu: 7.0.0-7.7 ] + + * resolute/linux: 7.0.0-7.7 -proposed tracker (LP: #2143974) + * unconfined profile denies userns_create for chromium based processes + (LP: #1990064) + - [Config] disable CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS + * Jellyfin Desktop Flatpak doesn't work with the current AppArmor profile + (LP: #2142956) + - SAUCE: apparmor5.0.0 [29/29]: apparmor: fix fine grained inet mediation + sock_file_perm + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor5.0.0 [28/29]: apparmor: fix aa_label_sk_perm to check + for RULE_MEDIATES_NET + * update apparmor and LSM stacking patch set (LP: #2028253) + - SAUCE: apparmor5.0.0 [1/29]: Stacking: LSM: Single calls in secid hooks + - SAUCE: apparmor5.0.0 [2/29]: Stacking: LSM: Exclusive secmark usage + - SAUCE: apparmor5.0.0 [3/29]: Stacking: AppArmor: Remove the exclusive + flag + - SAUCE: apparmor5.0.0 [4/29]: Revert "apparmor: fix dbus permission + queries to v9 ABI" + - SAUCE: apparmor5.0.0 [5/29]: Revert "apparmor: gate make fine grained + unix mediation behind v9 abi" + - SAUCE: apparmor5.0.0 [6/29]: apparmor: net: patch to provide + compatibility with v2.x net rules + - SAUCE: apparmor5.0.0 [7/29]: apparmor: net: add fine grained ipv4/ipv6 + mediation + - SAUCE: apparmor5.0.0 [8/29]: apparmor: lift compatibility check out of + profile_af_perm + - SAUCE: apparmor5.0.0 [9/29]: apparmor: userns: add unprivileged user ns + mediation + - SAUCE: apparmor5.0.0 [10/29]: apparmor: userns: Add sysctls for + additional controls of unpriv userns restrictions + - SAUCE: apparmor5.0.0 [12/29]: apparmor: userns: open userns related + sysctl so lxc can check if restriction are in place + - SAUCE: apparmor5.0.0 [13/29]: apparmor: userns: allow profile to be + transitioned when a userns is created + - SAUCE: apparmor5.0.0 [14/29]: apparmor: mqueue: call + security_inode_init_security on inode creation + - SAUCE: apparmor5.0.0 [15/29]: apparmor: mqueue: add fine grained + mediation of posix mqueues + - SAUCE: apparmor5.0.0 [16/29]: apparmor: uring: add io_uring mediation + - SAUCE: apparmor5.0.0 [19/29]: apparmor: prompt: setup slab cache for + audit data + - SAUCE: apparmor5.0.0 [20/29]: apparmor: prompt: add the ability for + profiles to have a learning cache + - SAUCE: apparmor5.0.0 [21/29]: apparmor: prompt: enable userspace upcall + for mediation + - SAUCE: apparmor5.0.0 [22/29]: apparmor: prompt: pass prompt boolean + through into path_name as well + - SAUCE: apparmor5.0.0 [23/29]: apparmor: check for supported version in + notification messages. + - SAUCE: apparmor5.0.0 [24/29]: apparmor: refactor building notice so it + is easier to extend + - SAUCE: apparmor5.0.0 [25/29]: apparmor: switch from ENOTSUPP to + EPROTONOSUPPORT + - SAUCE: apparmor5.0.0 [26/29]: apparmor: add support for meta data tags + - SAUCE: apparmor5.0.0 [27/29]: apparmor: prevent profile->disconnected + double free in aa_free_profile + * update apparmor and LSM stacking patch set (LP: #2028253) // Installation + of AppArmor on a 6.14 kernel produces error message "Illegal number: yes" + (LP: #2102680) + - SAUCE: apparmor5.0.0 [17/29]: apparmor: create an + AA_SFS_TYPE_BOOLEAN_INTPRINT sysctl variant + - SAUCE: apparmor5.0.0 [18/29]: apparmor: Use AA_SFS_FILE_BOOLEAN_INTPRINT + for userns and io_uring sysctls + * update apparmor and LSM stacking patch set (LP: #2028253) // [FFe] + apparmor-4.0.0-alpha2 for unprivileged user namespace restrictions in + mantic (LP: #2032602) + - SAUCE: apparmor5.0.0 [11/29]: apparmor: userns - make it so special + unconfined profiles can mediate user namespaces + * NPU utilization on amdxdna is missing (LP: #2143243) + - SAUCE: accel/amdxdna: Add IOCTL to retrieve realtime NPU power estimate + - SAUCE: accel/amdxdna: Support sensors for column utilization + - SAUCE: accel/amdxdna: Import AMD_PMF namespace + * Adopting dark mode by default for OLED panel (LP: #2143203) + - SAUCE: drm/connector: Add a new 'panel_type' property + - SAUCE: drm/amd/display: Attach OLED property to eDP panels + * Support AMD Image Signal Processing (ISP) unit V4.0 (LP: #2110092) + - SAUCE: media: platform: amd: Introduce amd isp4 capture driver + - SAUCE: media: platform: amd: low level support for isp4 firmware + - SAUCE: media: platform: amd: Add isp4 fw and hw interface + - SAUCE: media: platform: amd: isp4 subdev and firmware loading handling + added + - SAUCE: media: platform: amd: isp4 video node and buffers handling added + - SAUCE: Documentation: add documentation of AMD isp 4 driver + - SAUCE: media: platform: amd: isp4 debug fs logging and more descriptive + errors + - [Config] Enable VIDEO_AMD_ISP4_CAPTURE + * Miscellaneous Ubuntu changes + - [Config] temporarily disable OBJTOOL_WERROR + + -- Jacob Martin Thu, 02 Apr 2026 10:48:01 -0500 + +linux-nvidia (7.0.0-1003.3) resolute; urgency=medium + + * Packaging resync (LP: #1786013) + - [Packaging] debian.nvidia/dkms-versions -- update from kernel-versions + (adhoc/d2026.02.16) + + * Backport NVIDIA: SAUCE: vfio/nvgrace-egm: split zapping EGM into 1GB + chunks (LP: #2142160) + - NVIDIA: SAUCE: vfio/nvgrace-egm: split zapping EGM into 1GB chunks + + * r8127 module unload triggers NAPI WARN in netif_napi_del_locked() + (LP: #2141780) + - NVIDIA: SAUCE: r8127: fix NAPI warning on module removal + + * Enable Coresight in Perf (LP: #2093957) + - [Packaging] Enable coresight in Perf if arm64 + - [Packaging] Add libopencsd-dev as a build dependency + + * Backport nvgrace-gpu hugepfnmap, ecc patches and miscellaneous cleanups + (LP: #2138892) + - NVIDIA: SAUCE: vfio/nvgrace-egm: register EGM PFNMAP range with + memory_failure + - NVIDIA: SAUCE: vfio: Remove vfio_device_from_file() declaration + + * missing prototype for vfio_device_from_file() (LP: #2138132) + - NVIDIA: SAUCE: vfio: Fix missing prototype warning + + * r8127: Downgrade GPL claim to info (LP: #2137588) + - NVIDIA: SAUCE: r8127: print GPL_CLAIM with KERN_INFO + + * mt7925: Incorrect MLO mode in firmware control (LP: #2138755) + - NVIDIA: SAUCE: wifi: mt76: mt7925: Fix incorrect MLO mode in firmware + control + + * Enable GDS in the 6.8 based linux-nvidia kernel (LP: #2059814) + - NVIDIA: [Packaging] Add nvidia-fs build dependencies + + * Add PCIe Hotplug Driver for CX7 on DGX Spark (LP: #2138269) + - NVIDIA: SAUCE: MEDIATEK: platform: Add PCIe Hotplug Driver for CX7 on + DGX Spark + + * Backport support for Grace MPAM (LP: #2122432) + - NVIDIA: SAUCE: DT: cacheinfo: Expose the code to generate a cache-id + from a device_node + - NVIDIA: SAUCE: DT: dt-bindings: arm: Add MPAM MSC binding + - NVIDIA: SAUCE: arm64: mpam: Context switch the MPAM registers + - NVIDIA: SAUCE: arm64: mpam: Re-initialise MPAM regs when CPU comes + online + - NVIDIA: SAUCE: arm64: mpam: Advertise the CPUs MPAM limits to the driver + - NVIDIA: SAUCE: arm64: mpam: Add cpu_pm notifier to restore MPAM sysregs + - NVIDIA: SAUCE: arm64: mpam: Add helpers to change a tasks and cpu mpam + partid/pmg values + - NVIDIA: SAUCE: cacheinfo: Add helper to find the cache size from + cpu+level + - NVIDIA: SAUCE: arm_mpam: resctrl: Add boilerplate cpuhp and domain + allocation + - NVIDIA: SAUCE: arm_mpam: resctrl: Pick the caches we will use as resctrl + resources + - NVIDIA: SAUCE: arm_mpam: resctrl: Implement + resctrl_arch_reset_all_ctrls() + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_get_config() + - NVIDIA: SAUCE: arm_mpam: resctrl: Implement helpers to update + configuration + - NVIDIA: SAUCE: arm_mpam: resctrl: Add plumbing against arm64 task and + cpu hooks + - NVIDIA: SAUCE: arm_mpam: resctrl: Add CDP emulation + - NVIDIA: SAUCE: arm_mpam: resctrl: Add rmid index helpers + - NVIDIA: SAUCE: arm_mpam: resctrl: Convert to/from MPAMs bitmaps and + fixed-point formats + - NVIDIA: SAUCE: arm_mpam: resctrl: Add support for 'MB' resource + - NVIDIA: SAUCE: arm_mpam: resctrl: Reject oversized memory bandwidth + portion bitmaps + - NVIDIA: SAUCE: arm_mpam: resctrl: Fix MB min_bandwidth value exposed to + userspace + - NVIDIA: SAUCE: arm_mpam: resctrl: Add kunit test for control format + conversions + - NVIDIA: SAUCE: arm_mpam: resctrl: Add support for csu counters + - NVIDIA: SAUCE: arm_mpam: resctrl: Pre-allocate free running monitors + - NVIDIA: SAUCE: arm_mpam: resctrl: Pre-allocate assignable monitors + - NVIDIA: SAUCE: arm_mpam: resctrl: Add kunit test for ABMC/CDP + interactions + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_config_cntr() for + ABMC use + - NVIDIA: SAUCE: arm_mpam: resctrl: Allow resctrl to allocate monitors + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_rmid_read() and + resctrl_arch_reset_rmid() + - NVIDIA: SAUCE: arm_mpam: resctrl: Add resctrl_arch_cntr_read() & + resctrl_arch_reset_cntr() + - NVIDIA: SAUCE: untested: arm_mpam: resctrl: Allow monitors to be + configured with filters + - NVIDIA: SAUCE: arm_mpam: resctrl: Add empty definitions for fine-grained + enables + - NVIDIA: SAUCE: arm64: mpam: Select ARCH_HAS_CPU_RESCTRL + - NVIDIA: SAUCE: fs/resctrl: Don't touch rmid_ptrs[] in free_rmid() when + there are no monitors + - NVIDIA: SAUCE: fs/resctrl: Avoid a race with dom_data_exit() and + closid_num_dirty_rmid[] + - NVIDIA: SAUCE: fs/resctrl: Avoid a race with dom_data_exit() and + rmid_ptrs[] + - NVIDIA: SAUCE: perf/arm-cmn: Stop claiming all the resources + - NVIDIA: SAUCE: arm_mpam: resctrl: Call resctrl_init() on platforms that + can support resctrl + - NVIDIA: SAUCE: arm_mpam: resctrl: Call resctrl_exit() in the event of + errors + - NVIDIA: SAUCE: arm_mpam: resctrl: Update the rmid reallocation limit + - NVIDIA: SAUCE: arm_mpam: resctrl: Sort the order of the domain lists + - NVIDIA: SAUCE: arm_mpam: Generate a configuration for min controls + - NVIDIA: SAUCE: arm_mpam: Add quirk framework + - NVIDIA: SAUCE: arm_mpam: Add workaround for T241-MPAM-1 + - NVIDIA: SAUCE: arm_mpam: Add workaround for T241-MPAM-4 + - NVIDIA: SAUCE: arm_mpam: Add workaround for T241-MPAM-6 + - NVIDIA: SAUCE: arm_mpam: Quirk CMN-650's CSU NRDY behaviour + - NVIDIA: SAUCE: debugfs: Add helpers for creating cpumask entries in + debugfs + - NVIDIA: SAUCE: arm_mpam: Add debugfs entries to show the MSC/RIS the + driver discovered + - NVIDIA: SAUCE: arm_mpam: Add force-disable debugfs trigger + - NVIDIA: SAUCE: arm_mpam: Expose the number of NRDY retries in debugfs + - NVIDIA: SAUCE: arm_mpam: Add resctrl_arch_round_bw() + - NVIDIA: SAUCE: fs/resctrl,x86/resctrl: Factor mba rounding to be per- + arch + - NVIDIA: SAUCE: arm_mpam: Relax num_rmids parameter advertised to + userspace + - NVIDIA: SAUCE: arm_mpam: Split the locking around the mon_sel registers + - NVIDIA: SAUCE: arm_mpam: Allow the maximum partid to be overridden from + the command line + - NVIDIA: SAUCE: arm_mpam: Allow MSC to be forced to have an unknown + location + - NVIDIA: SAUCE: fs/resctrl: Add this_is_not_abi mount option + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Register SMMU capabilities with MPAM + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Add mpam helpers to query and set + state + - NVIDIA: SAUCE: iommu: Add helpers to get and set the QoS state + - NVIDIA: SAUCE: iommu: Add helpers to retrieve iommu_groups by id or + kobject + - NVIDIA: SAUCE: iommu: Add helper to retrieve iommu kset + - NVIDIA: SAUCE: kobject: Add kset_get_next_obj() to allow a kset to be + walked + - NVIDIA: SAUCE: arm_mpam: resctrl: Add iommu helpers to get/set the + partid and pmg + - NVIDIA: SAUCE: fs/resctrl: Add support for assigning iommu_groups to + resctrl groups + - NVIDIA: SAUCE: firmware: arm_scmi: add MPAM-FB SCMI protocol stub + - NVIDIA: SAUCE: arm_mpam: add MPAM-FB MSC firmware access support + - NVIDIA: SAUCE: arm_mpam: Allow duplicate PCC subspace_ids + - NVIDIA: SAUCE: untested: mpam: Convert pcc_channels list to XArray and + cleanup + - NVIDIA: SAUCE: x86/resctrl: Add stub to allow other architecture to + disable monitor overflow + - NVIDIA: SAUCE: arm_mpam: resctrl: Determine if any exposed counter can + overflow + - NVIDIA: SAUCE: fs/restrl: Allow the overflow handler to be disabled + - NVIDIA: SAUCE: fs/resctrl: Uniform data type of + component_id/domid/id/cache_id + - NVIDIA: SAUCE: arm_mpam: Allow cmax/cmin to be configured + - NVIDIA: SAUCE: arm_mpam: Rename mbw conversion to 'fract16' for code re- + use + - NVIDIA: SAUCE: fs/resctrl: Group all the MBA specific properties in a + separate struct + - NVIDIA: SAUCE: fs/resctrl: Abstract duplicate domain test to a helper + - NVIDIA: SAUCE: fs/resctrl: Move MBA supported check to parse_line() + instead of parse_bw() + - NVIDIA: SAUCE: fs/resctrl: Rename resctrl_get_default_ctrl() to include + resource + - NVIDIA: SAUCE: fs/resctrl: Add a schema format to the schema, allowing + it to be different + - NVIDIA: SAUCE: fs/resctrl: Use schema format to check the resource is a + bitmap + - NVIDIA: SAUCE: fs/resctrl: Add specific schema types for 'range' + - NVIDIA: SAUCE: x86/resctrl: Move over to specifying MBA control formats + - NVIDIA: SAUCE: arm_mpam: resctrl: Convert MB resource to use percentage + - NVIDIA: SAUCE: fs/resctrl: Remove 'range' schema format + - NVIDIA: SAUCE: fs/resctrl: Add additional files for percentage and + bitmap controls + - NVIDIA: SAUCE: fs/resctrl: Add fflags_from_schema() for files based on + schema format + - NVIDIA: SAUCE: fs/resctrl: Expose the schema format to user-space + - NVIDIA: SAUCE: fs/resctrl: Add L2 and L3 'MAX' resource schema + - NVIDIA: SAUCE: arm_mpam: resctrl: Add the glue code to convert to/from + cmax + - NVIDIA: SAUCE: mm,memory_hotplug: Add lockdep assertion helper + - NVIDIA: SAUCE: fs/resctrl: Take memory hotplug lock whenever taking CPU + hotplug lock + - NVIDIA: SAUCE: fs/resctrl: Add mount option for mb_uses_numa_nid and + arch stubs + - NVIDIA: SAUCE: Fix unused variable warning + - NVIDIA: SAUCE: arm_mpam: resctrl: Pick whether MB can use NUMA nid + instead of cache-id + - NVIDIA: SAUCE: arm_mpam: resctrl: Change domain_hdr online/offline to + work with a set of CPUs + - NVIDIA: SAUCE: untested: arm_mpam: resctrl: Split + mpam_resctrl_alloc_domain() to have CPU and node + - NVIDIA: SAUCE: arm_mpam: resctrl: Add NUMA node notifier for domain + online/offline + - NVIDIA: SAUCE: untested: arm_mpam: resctrl: Allow resctrl to enable NUMA + nid as MB domain-id + - NVIDIA: SAUCE: [Config] RESCTRL configs added to annotations + - NVIDIA: SAUCE: arm_mpam: Fix missing SHIFT definitions + - NVIDIA: SAUCE: arm_mpam: resctrl: Fix MPAM kunit + - NVIDIA: SAUCE: resctrl/mpam: Align packed mpam_props to fix arm64 KUnit + alignment fault + - NVIDIA: SAUCE: resctrl/tests: mpam_devices: compare only meaningful + bytes of mpam_props + + * r8127: fix for LTS test panic (LP: #2134991) + - NVIDIA: SAUCE: r8127: Remove registers2 proc entry + + * Add two more Spark iGPU IDs for the existing iommu quirk (LP: #2132033) + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Add two more DGX Spark iGPU IDs for + existing iommu quirk + + * Pull CPPC mailing list patches for Spark (LP: #2131705) + - NVIDIA: SAUCE: ACPI: CPPC: Add cppc_get_perf() API to read performance + controls + - NVIDIA: SAUCE: ACPI: CPPC: extend APIs to support auto_sel and epp + - NVIDIA: SAUCE: ACPI: CPPC: add APIs and sysfs interface for min/max_perf + - NVIDIA: SAUCE: ACPI: CPPC: add APIs and sysfs interface for perf_limited + register + - NVIDIA: SAUCE: cpufreq: CPPC: Add sysfs for min/max_perf and + perf_limited + - NVIDIA: SAUCE: cpufreq: CPPC: update policy min/max when toggling + auto_select + - NVIDIA: SAUCE: cpufreq: CPPC: add autonomous mode boot parameter support + + * r8127: fix kernel panic when dump all registers (LP: #2130445) + - NVIDIA: SAUCE: r8127: fix a kernel panic when dump all registers + - NVIDIA: SAUCE: r8127: add support for RTL8127 cable diagnostic test + + * Set CONFIG_IOMMU_DEFAULT_PASSTHROUGH as default for Nvidia CPUs + (LP: #2129776) + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Set DGX Spark iGPU default domain type + to DMA + - [Config] nvidia: Update annotations to set + CONFIG_IOMMU_DEFAULT_PASSTHROUGH + + * mt7925: Introduce CSA support in non-MLO mode (LP: #2129209) + - NVIDIA: SAUCE: wifi: mt76: mt7925: introduce CSA support in non-MLO mode + + * IOMMU: Support contiguous bit in translation tables (LP: #2112600) + - NVIDIA: SAUCE: iommu/io-pgtable-arm: backport contiguous bit support + + * NVIDIA: SAUCE: MEDIATEK: usb: host: xhci-hub: fix MT89xx SoCs return + PORTLI value (LP: #2125126) + - NVIDIA: SAUCE: MEDIATEK: usb: host: xhci-hub: fix MT89xx SoCs return + PORTLI value + + * NVIDIA: SAUCE: ffa notification count initialization fix (LP: #2123861) + - NVIDIA: SAUCE: Fix FFA notification count initialization + + * Pull-request for setting CPU frequency gov to performance (LP: #2028576) + - [Config] nvidia: Use performance CPU frequency governor on amd64 + + * Set CONFIG_IOMMU_DEFAULT_DMA_LAZY as default for Nvidia CPUs + (LP: #2119661) + - [Config] nvidia: Update annotations to set CONFIG_IOMMU_DEFAULT_DMA_LAZY + + * Backport support for Grace virtualization features: vEVENTQ, HW QUEUE, and + vEGM (LP: #2119656) + - NVIDIA: SAUCE: arm64: configs: Build NVGRACE_GPU_VFIO_PCI as LKM + - NVIDIA: SAUCE: arm64: configs: Enable IOMMUFD and VFIO_DEVICE_CDEV + - NVIDIA: SAUCE: vfio/nvgrace-egm: Introduce module to manage EGM + - NVIDIA: SAUCE: vfio/nvgrace-egm: Handle pages with ECC errors on the EGM + - NVIDIA: SAUCE: arm64: configs: Build CONFIG_NVGRACE_EGM as LKM + - NVIDIA: SAUCE: vfio/nvgrace-egm: Move the egm header file to include + - NVIDIA: SAUCE: vfio/nvgrace-egm: Free region memory during + unregistration + - NVIDIA: SAUCE: vfio/nvgrace-egm: Move region hash initialization + - NVIDIA: SAUCE: vfio/nvgrace-egm: Handle and convey EGM registration + errors + - NVIDIA: SAUCE: vfio/nvgrace-gpu: Handle EGM registration failure + - NVIDIA: SAUCE: vfio/nvgrace-egm: Address sparse errors + - NVIDIA: SAUCE: vfio/nvgrace-gpu: Address smatch errors + - NVIDIA: SAUCE: vfio/nvgrace-egm: Ensure ACPI value reads are successful + - NVIDIA: SAUCE: vfio/nvgrace-egm: Avoid invalid retired pages base + - NVIDIA: SAUCE: vfio/nvgrace-egm: Update EGM unregistration API + - NVIDIA: SAUCE: vfio/nvgrace-egm: track GPUs associated with the EGM + regions + - NVIDIA: SAUCE: vfio/nvgrace-egm: list gpus through sysfs + - NVIDIA: SAUCE: vfio/nvgrace-egm: expose the egm size through sysfs + - NVIDIA: SAUCE: arm64: configs: enable NVGRACE_EGM as module + + * Backport support for arm64 BRBE and a future NVIDIA CPU ID (LP: #2118663) + - [Config] nvidia: Enable BRBE + + * nvidia-ffa-ec: Fix FFH data response length (LP: #2118357) + - NVIDIA: SAUCE: Fix FFH data response length + + * Add pincontrol driver for MT8901 chip (LP: #2117784) + - NVIDIA: SAUCE: MEDIATEK: pinctrl: mediatek: Add gpio-range record in + pinctrl driver + - NVIDIA: SAUCE: MEDIATEK: pinctrl: mediatek: Add acpi support + - NVIDIA: SAUCE: MEDIATEK: pinctrl: mt8901: Add pinctrl driver + - [Config] nvidia: Update annotations to enable CONFIG_PINCTRL_MT8901 + + * NVIDIA: SAUCE: Add FFA and EC Secure Service Driver to -nvidia kernel + (LP: #2114230) + - NVIDIA: SAUCE: Add support for custom ARM FFH offset handler + - NVIDIA: SAUCE: Add nvidia ffa driver for EC communication + - NVIDIA: SAUCE: Add ffa driver for each secure EC service + - NVIDIA: SAUCE: Add support for EC secure service communication + - NVIDIA: SAUCE: Rescan acpi devices that uses secure EC communication + - NVIDIA: SAUCE: irqchip/gic-v3: Allow unused SGIs for drivers/modules + - NVIDIA: SAUCE: Add support for notifications from secure EC services + - [Config] nvidia: Update annotations to enable NVIDIA FFA EC driver + + * Backport: TPM Service Command Response Buffer Interface Over FF-A + (LP: #2111511) + - [Config] nvidia-6.14: Update annotations to enable TPM over FFA + + * Backport: ALSA: hda - Add new driver for HDA controllers listed via ACPI + (LP: #2111447) + - NVIDIA: SAUCE: [Config] nvidia: CONFIG_SND_HDA_ACPI=m on arm64 + + * Pull request to enable GPU passthrough for CUDA (LP: #2095028) + - NVIDIA: SAUCE: WAR: iommufd/pages: Bypass PFNMAP + - NVIDIA: SAUCE: [Config] nvidia: Update annotations for Grace I/O + virtualization + - [Config] nvidia-6.14: Drop CONFIG_TEGRA241_CMDQV from annotations + + * Add Realtek r8127 ethernet driver (LP: #2109730) + - NVIDIA: SAUCE: r8127: Add Realtek r8127 ethernet driver + - NVIDIA: SAUCE: r8127: Remove Realtek r8127 non required files + - NVIDIA: SAUCE: r8127: Moved files from r8127/src to r8127 folder + - NVIDIA: SAUCE: Add r8127 in kernel build + - [Config] nvidia-6.11: Update annotations to enable realtek R8127 module + + * Pull request: Add quirk and disable SBR on Gen5 ports (LP: #2107509) + - NVIDIA: SAUCE: MEDIATEK: usb: host: xhci-plat: support usb3 bulks stream + low power + + * Apply backport of upstream commit to enable Realtek Bluetooth module + (LP: #2096882) + - NVIDIA: SAUCE: Adds MT7925 BT devices + + * Apply SAUCE patch to enable 8250 serial device (LP: #2096888) + - NVIDIA: SAUCE: serial: 8250_mtk: Add ACPI support + + * Backport: "Add support for AArch64 AMUv1-based average freq" Series + (LP: #2100032) + - NVIDIA: [Config] set CONFIG_CPUFREQ_ARCH_CUR_FREQ=y for x86 + + * MANA: include driver fixes and enable module on ARM64 (LP: #2084598) + - [Config] nvidia-6.17: Enable MANA configs on x86 and arm64 + + * Apply patch to set CONFIG_EFI_CAPSULE_LOADER=y for arm64 (LP: #2067111) + - NVIDIA: [Config] EFI: set CAPSULE_LOADER=y for arm64 + + * linux-nvidia-6.5_6.5.0-1014.14 breaks with earlier BIOS release, and + modeset/resolutions are wrong (LP: #2061930) // Blacklist coresight_etm4x + (LP: #2067106) + - [Packaging] blacklist coresight_etm4x + + * backport arm64 THP improvements from 6.9 (LP: #2059316) + - NVIDIA: [Config] arm64: ARM64_CONTPTE=y + + * Reapply the linux-nvidia kernel config options from the 5.15 and 6.5 + kernels (LP: #2060327) + - NVIDIA: [Config]: Disable the NOUVEAU driver which is not used with + -nvidia kernels + - NVIDIA: [Config]: Adding CORESIGHT and ARM64_ERRATUM configs to + annotations + + [ Ubuntu: 7.0.0-6.6 ] + + * resolute/linux: 7.0.0-6.6 -proposed tracker (LP: #2143745) + * Miscellaneous Ubuntu changes + - [Packaging] drop unstable suffix + + [ Ubuntu: 7.0.0-5.5 ] + + * resolute/linux-unstable: 7.0.0-5.5 -proposed tracker (LP: #2143700) + * Resolute real-time patchset: 7.0-rc1-rt1 (LP: #2143181) + - SAUCE: Reapply "serial: 8250: Switch to nbcon console" + - SAUCE: Reapply "serial: 8250: Revert "drop lockdep annotation from + serial8250_clear_IER()"" + - SAUCE: drm/i915: Use preempt_disable/enable_rt() where recommended + - SAUCE: drm/i915: Don't disable interrupts on PREEMPT_RT during atomic + updates + - SAUCE: drm/i915: Disable tracing points on PREEMPT_RT + - SAUCE: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + + spin_lock() + - SAUCE: drm/i915: Drop the irqs_disabled() check + - SAUCE: drm/i915/guc: Consider also RCU depth in busy loop. + - SAUCE: drm/i915: Consider RCU read section as atomic. + - SAUCE: Revert "drm/i915: Depend on !PREEMPT_RT." + - SAUCE: sysfs: Add /sys/kernel/realtime entry + - Real-time patchset 7.0-rc1-rt1 + * Miscellaneous Ubuntu changes + - [Config] rust toolchain version update + + [ Ubuntu-unstable: 7.0.0-4.4 ] + + * resolute/linux-unstable: 7.0.0-4.4 -proposed tracker (LP: #2143123) + * efi: Fix swapped arguments to bsearch() in efi_status_to_*() SAUCE patch + (LP: #2141276) + - SAUCE efi: Fix swapped arguments to bsearch() in efi_status_to_*() + * Plucky preinstalled server fails to boot on rb3gen2 (LP: #2106681) // + Questing preinstalled server fails to boot on sa8775p boards + (LP: #2121347) + - [Config] move more qcom interconnect/pinctrl/gcc options to builtin + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Add llvm-21-dev to build-depends for perf + * Miscellaneous Ubuntu changes + - [Packaging] Add intel-speed-select to linux-tools + - [Packaging] remove stale debian/dkms-versions + - [Packaging] remove stale debian/dkms-versions scripting + + [ Ubuntu-unstable: 7.0.0-3.3 ] + + * resolute/linux-unstable: 7.0.0-3.3 -proposed tracker (LP: #2143020) + * Miscellaneous Ubuntu changes + - [Config] updateconfig after rebase to v7.0-rc2 + - [Config] switch to PREEMPT_LAZY + + [ Ubuntu-unstable: 7.0.0-2.2 ] + + * resolute/linux-unstable: 7.0.0-2.2 -proposed tracker (LP: #2142764) + + [ Ubuntu-unstable: 7.0.0-1.1 ] + + * resolute/linux-unstable: 7.0.0-1.1 -proposed tracker (LP: #2142402) + * Miscellaneous Ubuntu changes + - [packaging] rename to linux-unstable + - [Config] updateconfig after rebase to v7.0-rc1 + - Update Changes.md + - [Packaging] add libbpf-dev to Build-Depends + - [Config] disable AMD_ISP4, FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove zfs FTBFS + - [Packaging] debian.master/dkms-versions -- temporarily remove evdi FTBFS + - [Config] updateconfig after rebase to v7.0-rc1 + - [Config] update toolchain version + + -- Jacob Martin Thu, 26 Mar 2026 11:14:51 -0500 + +linux-nvidia (6.19.0-1001.1) resolute; urgency=medium + + * linux-tools: consider linking perf against LLVM (LP: #2138328) + - [Packaging] Add llvm-21-dev to build-depends for perf + + [ Ubuntu: 6.19.0-6.6 ] + + * resolute/linux: 6.19.0-6.6 -proposed tracker (LP: #2142114) + * Resolute update: v6.19.2 upstream stable release (LP: #2142112) + - Revert "driver core: enforce device_lock for driver_match_device()" + - Linux 6.19.2 + * Resolute update: v6.19.1 upstream stable release (LP: #2142111) + - io_uring/io-wq: add exit-on-idle state + - io_uring: allow io-wq workers to exit when unused + - smb: client: split cached_fid bitfields to avoid shared-byte RMW races + - ksmbd: fix infinite loop caused by next_smb2_rcv_hdr_off reset in error + paths + - ksmbd: add chann_lock to protect ksmbd_chann_list xarray + - smb: server: fix leak of active_num_conn in ksmbd_tcp_new_connection() + - smb: smbdirect: introduce smbdirect_socket.recv_io.credits.available + - smb: smbdirect: introduce smbdirect_socket.send_io.bcredits.* + - smb: server: make use of smbdirect_socket.recv_io.credits.available + - smb: server: let recv_done() queue a refill when the peer is low on + credits + - smb: server: make use of smbdirect_socket.send_io.bcredits + - smb: server: fix last send credit problem causing disconnects + - smb: server: let send_done handle a completion without IB_SEND_SIGNALED + - smb: client: make use of smbdirect_socket.recv_io.credits.available + - smb: client: let recv_done() queue a refill when the peer is low on + credits + - smb: client: let smbd_post_send() make use of request->wr + - smb: client: remove pointless sc->recv_io.credits.count rollback + - smb: client: remove pointless sc->send_io.pending handling in + smbd_post_send_iter() + - smb: client: port and use the wait_for_credits logic used by server + - smb: client: split out smbd_ib_post_send() + - smb: client: introduce and use smbd_{alloc, free}_send_io() + - smb: client: use smbdirect_send_batch processing + - smb: client: make use of smbdirect_socket.send_io.bcredits + - smb: client: fix last send credit problem causing disconnects + - smb: client: let smbd_post_send_negotiate_req() use smbd_post_send() + - smb: client: let send_done handle a completion without IB_SEND_SIGNALED + - driver core: enforce device_lock for driver_match_device() + - Bluetooth: btusb: Add USB ID 7392:e611 for Edimax EW-7611UXB + - ALSA: hda/conexant: Add quirk for HP ZBook Studio G4 + - crypto: iaa - Fix out-of-bounds index in find_empty_iaa_compression_mode + - crypto: octeontx - Fix length check to avoid truncation in + ucode_load_store + - crypto: omap - Allocate OMAP_CRYPTO_FORCE_COPY scatterlists correctly + - crypto: virtio - Add spinlock protection with virtqueue notification + - crypto: virtio - Remove duplicated virtqueue_kick in + virtio_crypto_skcipher_crypt_req + - nilfs2: Fix potential block overflow that cause system hang + - hfs: ensure sb->s_fs_info is always cleaned up + - wifi: rtw88: Fix alignment fault in rtw_core_enable_beacon() + - scsi: qla2xxx: Validate sp before freeing associated memory + - scsi: qla2xxx: Allow recovery for tape devices + - scsi: qla2xxx: Delay module unload while fabric scan in progress + - scsi: qla2xxx: Free sp in error path to fix system crash + - scsi: qla2xxx: Query FW again before proceeding with login + - sched/mmcid: Don't assume CID is CPU owned on mode switch + - bus: fsl-mc: fix use-after-free in driver_override_show() + - erofs: fix UAF issue for file-backed mounts w/ directio option + - xfs: fix UAF in xchk_btree_check_block_owner + - drm/exynos: vidi: use ctx->lock to protect struct vidi_context member + variables related to memory alloc/free + - PCI: endpoint: Avoid creating sub-groups asynchronously + - wifi: rtl8xxxu: fix slab-out-of-bounds in rtl8xxxu_sta_add + - Linux 6.19.1 + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor: fix aa_label_sk_perm to check for RULE_MEDIATES_NET + + -- Jacob Martin Tue, 03 Mar 2026 11:01:18 -0600 + +linux-nvidia (6.19.0-1000.0) resolute; urgency=medium + + * Initial changelog entry. + + -- Jacob Martin Fri, 27 Feb 2026 14:49:42 -0600 + +linux (6.19.0-6.6) resolute; urgency=medium + + * resolute/linux: 6.19.0-6.6 -proposed tracker (LP: #2142114) + + * Resolute update: v6.19.2 upstream stable release (LP: #2142112) + - Revert "driver core: enforce device_lock for driver_match_device()" + - Linux 6.19.2 + + * Resolute update: v6.19.1 upstream stable release (LP: #2142111) + - io_uring/io-wq: add exit-on-idle state + - io_uring: allow io-wq workers to exit when unused + - smb: client: split cached_fid bitfields to avoid shared-byte RMW races + - ksmbd: fix infinite loop caused by next_smb2_rcv_hdr_off reset in error + paths + - ksmbd: add chann_lock to protect ksmbd_chann_list xarray + - smb: server: fix leak of active_num_conn in ksmbd_tcp_new_connection() + - smb: smbdirect: introduce smbdirect_socket.recv_io.credits.available + - smb: smbdirect: introduce smbdirect_socket.send_io.bcredits.* + - smb: server: make use of smbdirect_socket.recv_io.credits.available + - smb: server: let recv_done() queue a refill when the peer is low on + credits + - smb: server: make use of smbdirect_socket.send_io.bcredits + - smb: server: fix last send credit problem causing disconnects + - smb: server: let send_done handle a completion without IB_SEND_SIGNALED + - smb: client: make use of smbdirect_socket.recv_io.credits.available + - smb: client: let recv_done() queue a refill when the peer is low on + credits + - smb: client: let smbd_post_send() make use of request->wr + - smb: client: remove pointless sc->recv_io.credits.count rollback + - smb: client: remove pointless sc->send_io.pending handling in + smbd_post_send_iter() + - smb: client: port and use the wait_for_credits logic used by server + - smb: client: split out smbd_ib_post_send() + - smb: client: introduce and use smbd_{alloc, free}_send_io() + - smb: client: use smbdirect_send_batch processing + - smb: client: make use of smbdirect_socket.send_io.bcredits + - smb: client: fix last send credit problem causing disconnects + - smb: client: let smbd_post_send_negotiate_req() use smbd_post_send() + - smb: client: let send_done handle a completion without IB_SEND_SIGNALED + - driver core: enforce device_lock for driver_match_device() + - Bluetooth: btusb: Add USB ID 7392:e611 for Edimax EW-7611UXB + - ALSA: hda/conexant: Add quirk for HP ZBook Studio G4 + - crypto: iaa - Fix out-of-bounds index in find_empty_iaa_compression_mode + - crypto: octeontx - Fix length check to avoid truncation in + ucode_load_store + - crypto: omap - Allocate OMAP_CRYPTO_FORCE_COPY scatterlists correctly + - crypto: virtio - Add spinlock protection with virtqueue notification + - crypto: virtio - Remove duplicated virtqueue_kick in + virtio_crypto_skcipher_crypt_req + - nilfs2: Fix potential block overflow that cause system hang + - hfs: ensure sb->s_fs_info is always cleaned up + - wifi: rtw88: Fix alignment fault in rtw_core_enable_beacon() + - scsi: qla2xxx: Validate sp before freeing associated memory + - scsi: qla2xxx: Allow recovery for tape devices + - scsi: qla2xxx: Delay module unload while fabric scan in progress + - scsi: qla2xxx: Free sp in error path to fix system crash + - scsi: qla2xxx: Query FW again before proceeding with login + - sched/mmcid: Don't assume CID is CPU owned on mode switch + - bus: fsl-mc: fix use-after-free in driver_override_show() + - erofs: fix UAF issue for file-backed mounts w/ directio option + - xfs: fix UAF in xchk_btree_check_block_owner + - drm/exynos: vidi: use ctx->lock to protect struct vidi_context member + variables related to memory alloc/free + - PCI: endpoint: Avoid creating sub-groups asynchronously + - wifi: rtl8xxxu: fix slab-out-of-bounds in rtl8xxxu_sta_add + - Linux 6.19.1 + + * AppArmor blocks write(2) to network sockets with Linux 6.19 (LP: #2141298) + - SAUCE: apparmor: fix aa_label_sk_perm to check for RULE_MEDIATES_NET + + -- Timo Aaltonen Wed, 18 Feb 2026 14:31:48 +0200 --- linux-nvidia-7.0.0.orig/debian/cloud-tools/hv_get_dhcp_info +++ linux-nvidia-7.0.0/debian/cloud-tools/hv_get_dhcp_info @@ -0,0 +1,55 @@ +#!/bin/bash + +# This example script retrieves the DHCP state of a given interface. +# In the interest of keeping the KVP daemon code free of distro specific +# information; the kvp daemon code invokes this external script to gather +# DHCP setting for the specific interface. +# +# Input: Name of the interface +# +# Output: The script prints the string "Enabled" to stdout to indicate +# that DHCP is enabled on the interface. If DHCP is not enabled, +# the script prints the string "Disabled" to stdout. +# +# Each Distro is expected to implement this script in a distro specific +# fashion. + +#set -x + +IF_FILE="/etc/network/interfaces" +NMCMD="nmcli" + +function checknetworkmanager { + #Assumes if $NMCMD exists, inteface exists and interface is not + # in $IF_FILE then dhcp is being used by NM + if hash $NMCMD >/dev/null 2>&1 ; then + if $NMCMD dev status |grep -q $1 ; then + echo "Enabled" + else + echo "Disabled" + fi + else + #Give up + echo "Disabled" + fi +} + +if [ -z $1 ] ; then echo "Disabled"; exit; fi + +if [ -e $IF_FILE ]; then + if grep -v -e "^#" $IF_FILE|grep -q $1 ; then + #interface exists so + if grep -q -e $1\.\*dhcp $IF_FILE; then + echo "Enabled"; exit; + else + echo "Disabled"; exit; + fi + else + checknetworkmanager $1 + exit + fi +else + checknetworkmanager $1 + exit +fi + --- linux-nvidia-7.0.0.orig/debian/cloud-tools/hv_get_dns_info +++ linux-nvidia-7.0.0/debian/cloud-tools/hv_get_dns_info @@ -0,0 +1,13 @@ +#!/bin/bash + +# This example script parses /etc/resolv.conf to retrive DNS information. +# In the interest of keeping the KVP daemon code free of distro specific +# information; the kvp daemon code invokes this external script to gather +# DNS information. +# This script is expected to print the nameserver values to stdout. +# Each Distro is expected to implement this script in a distro specific +# fashion. For instance on Distros that ship with Network Manager enabled, +# this script can be based on the Network Manager APIs for retrieving DNS +# entries. + +cat /etc/resolv.conf 2>/dev/null | awk '/^nameserver/ { print $2 }' --- linux-nvidia-7.0.0.orig/debian/cloud-tools/hv_set_ifconfig +++ linux-nvidia-7.0.0/debian/cloud-tools/hv_set_ifconfig @@ -0,0 +1,288 @@ +#!/usr/bin/python3 +# +# hv_set_ifconfig -- take the hv_kvp_daemon generated configuration +# file and apply it to the Ubuntu configuration. +# + +# CONFIG example: +# HWADDR=11:22:33:44:55:66 +# DEVICE=foo1 +# DHCP=yes + +# CONFIG example: +# HWADDR=11:22:33:44:55:66 +# DEVICE=foo1 +# IPADDR=192.168.99.10 +# GATEWAY=192.168.99.1 +# DNS1=192.168.88.250 +# IPADDR2=192.168.99.11 +# IPV6ADDR=2001:DB8:99::10 +# IPV6NETMASK=64 +# IPV6_DEFAULTGW=2001:DB8:99::10 + +# set interfaces in hv_kvp_daemon style +import fileinput +import sys +import errno +import os +import shutil +import tempfile +import subprocess + +if_filename="/etc/network/interfaces" + +# Drop our output (XXX?) +sys.stdout = open(os.devnull, 'w') +sys.stderr = open(os.devnull, 'w') + +# Confirm we can open the network configuration. +try: + if_file=open(if_filename,"r+") +except IOError as e: + exit(e.errno) +else: + if_file.close() + +# Usage: hv_set_ifconfig +if len(sys.argv) != 2 : + exit(errno.EINVAL) + +# +# Here is the format of the ip configuration file: +# +# HWADDR=macaddr +# DEVICE=interface name +# BOOTPROTO= (where is "dhcp" if DHCP is configured +# or "none" if no boot-time protocol should be used) +# +# IPADDR0=ipaddr1 +# IPADDR1=ipaddr2 +# IPADDRx=ipaddry (where y = x + 1) +# +# NETMASK0=netmask1 +# NETMASKx=netmasky (where y = x + 1) +# +# GATEWAY=ipaddr1 +# GATEWAYx=ipaddry (where y = x + 1) +# +# DNSx=ipaddrx (where first DNS address is tagged as DNS1 etc) +# +# IPV6 addresses will be tagged as IPV6ADDR, IPV6 gateway will be +# tagged as IPV6_DEFAULTGW and IPV6 NETMASK will be tagged as +# IPV6NETMASK. +# + +kvp=dict(line.strip().split("=") for line in fileinput.input()) + +# Setting the hwaddress to something azure is not expecting is fatal +# to networking. +if not "HWADDR" in kvp : + exit(errno.EPROTO) + +# Confirm we have a device specified. +if not "DEVICE" in kvp : + exit(1) + +autolist = [] +output=[] +basename=kvp["DEVICE"] + +# DNS entries will go with the first interface and there can be a max +# of three. These will be emitted with the first interface. +dns = [] +for count in (1, 2, 3): + key = "DNS" + str(count) + if key in kvp: + dns += [kvp[key]] +dns_emitted = False + +# IPV4 may either be dhcp or static. +if ("DHCP" in kvp and kvp["DHCP"] == "yes") or \ + ("BOOTPROTO" in kvp and kvp["BOOTPROTO"] == "dhcp"): + autolist.append(basename) + output += ["iface " + basename + " inet dhcp"] + output += [""] +else: + # Matchup the interface specific lines + + # No real max for the number of interface + aliases ... + # only required is the address (but mate everything up that comes in. + + # IPv4 -- ensure we sort by numeric suffixes. + v4names = [ int(name[6:]) for name in kvp.keys() if name.startswith("IPADDR") ] + v4names.sort() + + for if_count in v4names: + ifname = basename + which = str(if_count) + + if if_count: + ifname += ":" + str(if_count) + which_gw = which + else: + which_gw = "" + + if not ifname in autolist: + autolist += [ifname] + + output += [ "iface " + ifname + " inet static" ] + output += [ "\t" + "address " + kvp["IPADDR" + which] ] + if "NETMASK" + which in kvp: + output += [ "\tnetmask " + kvp["NETMASK" + which] ] + if "GATEWAY" + which_gw in kvp: + output += ["\tgateway " + kvp["GATEWAY" + which_gw]] + + if not dns_emitted: + dns_emitted = True + output += ["\tdns-nameservers " + ' '.join(dns)] + output += [""] + +# IPv6 requires a netmask +# If an ipv6 exists, you'll want to turn off /proc/sys/net/ipv6/conf/all/autoconf with +# echo 0 > /proc/sys/net/ipv6/conf/all/autoconf +v6names = [ int(name[8:]) for name in kvp.keys() if name.startswith("IPV6ADDR") ] +v6names.sort() + +for if6_count in v6names: + ifname = basename + which = str(if6_count) + + if if6_count: + ifname += ":" + str(if6_count) + which_gw = which + else: + which_gw = "" + + if not ifname in autolist: + autolist += [ifname] + + if "IPV6NETMASK" + which in kvp: + output += [ "iface " + ifname + " inet6 static"] + output += [ "\taddress " + kvp["IPV6ADDR" + which]] + output += [ "\tnetmask " + kvp["IPV6NETMASK" + which]] + if "IPV6_DEFAULTGW" + which_gw in kvp: + output += [ "\tgateway " + kvp["IPV6_DEFAULTGW" + which_gw] ] + if not dns_emitted: + dns_emitted = True + output += ["\tdns-nameservers " + ' '.join(dns)] + output += [""] + +# Mark this new interface for automatic up. +if len(autolist): + output = ["auto "+" ".join(autolist)] + output + +print("===================================") +print(output) +print("===================================") + + +# Time to clean out the existing interface file + +# Markers. +start_mark = "# The following stanza(s) added by hv_set_ifconfig" +end_mark = "#End of hv_set_ifconfig stanzas" + +f=open(if_filename,"r") +flines=f.readlines() +f.close() +newfile=[] +pitchstanza=0 +inastanza=0 +stanza=[] +prev_line=None +for line in flines: + if line.startswith("auto"): + if inastanza: + if not pitchstanza: + newfile.extend(stanza) + stanza=[] + inastanza=0 + newline="" + autoline=line.strip().split(" ") + for word in autoline: + if (not word == basename) and (not word.startswith(basename+":")): + newline+=word + " " + newline = newline.strip() + if not newline == "auto": + newfile += [newline.strip()] + elif line.startswith(("iface","mapping","source")): + '''Read a stanza''' + '''A Stanza can also start with allow- ie allow-hotplug''' + if inastanza: + if not pitchstanza: + newfile.extend(stanza) + stanza=[] + inastanza=1 + pitchstanza=0 + autoline=line.strip().split(" ") + for word in autoline: + if (word == basename) or (word.startswith(basename+":")): + pitchstanza=1 + if not pitchstanza: + stanza+=[line.strip()] + elif line.strip() in (start_mark, end_mark): + if inastanza: + if not pitchstanza: + newfile.extend(stanza) + stanza=[] + inastanza = 0 + pitchstanza = 0 + # Deduplicate markers. + if line != prev_line: + newfile += [line.strip()] + else: + if inastanza: + if not pitchstanza: + stanza+=[line.strip()] + else: + if not pitchstanza: + newfile += [line.strip()] + prev_line=line + +# Include pending stanza if any. +if inastanza and not pitchstanza: + newfile.extend(stanza) + + +def emit(line): + print(line) + output = line + "\n" + os.write(fd, output.encode('utf-8')) + +# Insert the new output at the end and inside the existing markers if found. +emitted = False +fd, path = tempfile.mkstemp() +for line in newfile: + if line == end_mark: + emit("\n".join(output)) + emitted = True + emit(line) +if not emitted: + emit(start_mark) + emit("\n".join(output)) + emit(end_mark) +os.close(fd) + +shutil.copy(path,if_filename) +os.chmod(if_filename,0o644) + +#print("TMPFILE is at: " + path) +#print("Copied file is at: " + if_filename) + +try: + retcode = subprocess.call("ifdown "+basename , shell=True) + if retcode < 0: + print("Child was terminated by signal", -retcode, file=sys.stderr) + else: + print("Child returned", retcode, file=sys.stderr) +except OSError as e: + print("Execution failed:", e, file=sys.stderr) + +try: + retcode = subprocess.call("ifup "+basename , shell=True) + if retcode < 0: + print("Child was terminated by signal", -retcode, file=sys.stderr) + else: + print("Child returned", retcode, file=sys.stderr) +except OSError as e: + print("Execution failed:", e, file=sys.stderr) --- linux-nvidia-7.0.0.orig/debian/control +++ linux-nvidia-7.0.0/debian/control @@ -0,0 +1,342 @@ +Source: linux-nvidia +Section: devel +Priority: optional +Maintainer: Ubuntu Kernel Team +XSC-Ubuntu-Compatible-Signing: ubuntu/4 pro/3 livepatch:2025 kmod:2025 +Rules-Requires-Root: no +Standards-Version: 3.9.4.0 +Build-Depends: + gcc:native, gcc-aarch64-linux-gnu [arm64] , gcc-arm-linux-gnueabihf [armhf] , gcc-powerpc64le-linux-gnu [ppc64el] , gcc-riscv64-linux-gnu [riscv64] , gcc-s390x-linux-gnu [s390x] , gcc-x86-64-linux-gnu [amd64] , + autoconf , + automake , + bc , + bindgen:native [amd64 arm64], + bison , + clang-21:native [amd64 arm64], + cpio, + curl , + debhelper-compat (= 10), + default-jdk-headless:native , + dkms , + flex , + gawk , + java-common , + kmod , + libaudit-dev , + libbpf-dev , + libcap-dev , + libdebuginfod-dev [amd64 arm64] , + libdw-dev , + libelf-dev , + libiberty-dev , + liblzma-dev , + libnewt-dev , + libnl-3-dev, + libnl-genl-3-dev, + libnuma-dev [amd64 arm64] , + libpci-dev , + libssl-dev , + libstdc++-dev, + libtool , + libtraceevent-dev [amd64 arm64] , + libtracefs-dev [amd64 arm64] , + libudev-dev , + libunwind8-dev [amd64 arm64] , + llvm-21-dev, + makedumpfile:native [amd64] , + openssl , + pahole (>= 1.29-2ubuntu2) [amd64 arm64] | dwarves (>= 1.21) [amd64 arm64] , + pkg-config , + python3:native , + python3-dev:native , + libpython3-dev , + python3-setuptools, + rsync [!i386] , + rust-src:native [amd64 arm64], + rustc:native (>= 1.82) [amd64 arm64], + rustfmt:native [amd64 arm64], + uuid-dev , + zstd , + bpftool:native [amd64 arm64] , + nvidia-dkms-580-open [amd64 arm64] , + nvidia-kernel-source-580-open [amd64 arm64] , + libopencsd-dev [arm64] , +Build-Depends-Indep: + asciidoc , + bzip2 , + python3-docutils , + sharutils , + xmlto , +Vcs-Git: git://git.launchpad.net/~canonical-kernel/ubuntu/+source/linux-nvidia/+git/resolute +XS-Testsuite: autopkgtest +#XS-Testsuite-Depends: gcc-4.7 binutils + +Package: linux-nvidia-headers-7.0.0-1006 +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Header files related to Linux kernel version 7.0.0 + This package provides kernel header files for version 7.0.0, for sites + that want the latest kernel headers. Please read + /usr/share/doc/linux-nvidia-headers-7.0.0-1006/debian.README.gz for details + +Package: linux-nvidia-tools-7.0.0-1006 +Build-Profiles: +Architecture: amd64 arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-tools-common +Description: Linux kernel version specific tools for version 7.0.0-1006 + This package provides the architecture dependant parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version 7.0.0-1006. + You probably want to install linux-tools-7.0.0-1006-. + +Package: linux-nvidia-cloud-tools-7.0.0-1006 +Build-Profiles: +Architecture: amd64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, linux-cloud-tools-common +Description: Linux kernel version specific cloud tools for version 7.0.0-1006 + This package provides the architecture dependant parts for kernel + version locked tools for cloud tools for version 7.0.0-1006. + You probably want to install linux-cloud-tools-7.0.0-1006-. + +Package: linux-image-unsigned-7.0.0-1006-nvidia +Build-Profiles: +Architecture: amd64 arm64 +Section: kernel +Priority: optional +Provides: linux-image, fuse-module, kvm-api-4, redhat-cluster-modules, ivtv-modules, virtualbox-guest-modules [amd64], ${linux:rprovides} +Depends: ${misc:Depends}, ${shlibs:Depends}, kmod, linux-base (>= 4.5ubuntu1~16.04.1), linux-modules-7.0.0-1006-nvidia +Recommends: grub-pc [amd64] | grub-efi-amd64 [amd64] | grub-efi-ia32 [amd64] | grub [amd64] | lilo [amd64] | flash-kernel [armhf arm64] | grub-efi-arm64 [arm64] | grub-efi-arm [armhf] | grub-ieee1275 [ppc64el], dracut | linux-initramfs-tool +Breaks: flash-kernel (<< 3.90ubuntu2) [arm64 armhf], s390-tools (<< 2.3.0-0ubuntu3) [s390x] +Conflicts: linux-image-7.0.0-1006-nvidia +Suggests: bpftool, linux-perf, linux-nvidia-tools, linux-headers-7.0.0-1006-nvidia +Description: Linux kernel image for version 7.0.0 + This package contains the unsigned Linux kernel image for version 7.0.0. + . + Supports NVIDIA processors. + . + Intended for NVIDIA platforms + . + You likely do not want to install this package directly. Instead, install + the linux-nvidia meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-image-unsigned-7.0.0-1006-nvidia-dbgsym +Build-Profiles: +Architecture: amd64 arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends} +Provides: linux-debug +Description: Linux kernel debug image for version 7.0.0 + This package provides the unsigned kernel debug image for version 7.0.0. + . + This is for sites that wish to debug the kernel. + . + The kernel image contained in this package is NOT meant to boot from. It + is uncompressed, and unstripped. This package also includes the + unstripped modules. + + +Package: linux-modules-7.0.0-1006-nvidia +Build-Profiles: +Architecture: amd64 arm64 +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, wireless-regdb +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel modules for version 7.0.0 + Contains the corresponding System.map file, the modules built by the + packager, and scripts that try to ensure that the system is not left in an + unbootable state after an update. + . + Supports NVIDIA processors. + . + Intended for NVIDIA platforms + . + You likely do not want to install this package directly. Instead, install + the linux-nvidia meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-headers-7.0.0-1006-nvidia +Build-Profiles: +Architecture: amd64 arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, linux-nvidia-headers-7.0.0-1006, ${shlibs:Depends} +Provides: linux-headers, linux-headers-3.0 +Description: Linux kernel headers for version 7.0.0 + This package provides kernel header files for version 7.0.0. + . + This is for sites that want the latest kernel headers. Please read + /usr/share/doc/linux-headers-7.0.0-1006/debian.README.gz for details. + +Package: linux-lib-rust-7.0.0-1006-nvidia +Build-Profiles: +Architecture: amd64 +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Rust library files related to Linux kernel version 7.0.0 + This package provides kernel library files for version 7.0.0, that allow to + compile out-of-tree kernel modules written in Rust. + +Package: linux-tools-7.0.0-1006-nvidia +Build-Profiles: +Architecture: amd64 arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, linux-nvidia-tools-7.0.0-1006 +Description: Linux kernel version specific tools for version 7.0.0-1006 + This package provides the architecture dependant parts for kernel + version locked tools (such as x86_energy_perf_policy) for + version 7.0.0-1006. + +Package: linux-cloud-tools-7.0.0-1006-nvidia +Build-Profiles: +Architecture: amd64 arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, linux-nvidia-cloud-tools-7.0.0-1006 +Description: Linux kernel version specific cloud tools for version 7.0.0-1006 + This package provides the architecture dependant parts for kernel + version locked tools for cloud for version 7.0.0-1006. + + +Package: linux-buildinfo-7.0.0-1006-nvidia +Build-Profiles: +Architecture: amd64 arm64 +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends} +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel buildinfo for version 7.0.0 + This package contains the Linux kernel buildinfo for version 7.0.0. + . + You likely do not want to install this package. + +Package: linux-image-unsigned-7.0.0-1006-nvidia-64k +Build-Profiles: +Architecture: arm64 +Section: kernel +Priority: optional +Provides: linux-image, fuse-module, kvm-api-4, redhat-cluster-modules, ivtv-modules, ${linux:rprovides} +Depends: ${misc:Depends}, ${shlibs:Depends}, kmod, linux-base (>= 4.5ubuntu1~16.04.1), linux-modules-7.0.0-1006-nvidia-64k +Recommends: grub-efi-arm64 [arm64] | flash-kernel [arm64], dracut | linux-initramfs-tool +Breaks: flash-kernel (<< 3.90ubuntu2) [arm64 armhf], s390-tools (<< 2.3.0-0ubuntu3) [s390x] +Conflicts: linux-image-7.0.0-1006-nvidia-64k +Suggests: bpftool, linux-perf, linux-nvidia-tools, linux-headers-7.0.0-1006-nvidia-64k +Description: Linux kernel image for version 7.0.0 + This package contains the unsigned Linux kernel image for version 7.0.0. + . + Supports NVIDIA 64K pages processors. + . + Intended for NVIDIA systems + . + You likely do not want to install this package directly. Instead, install + the linux-nvidia-64k meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-image-unsigned-7.0.0-1006-nvidia-64k-dbgsym +Build-Profiles: +Architecture: arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends} +Provides: linux-debug +Description: Linux kernel debug image for version 7.0.0 + This package provides the unsigned kernel debug image for version 7.0.0. + . + This is for sites that wish to debug the kernel. + . + The kernel image contained in this package is NOT meant to boot from. It + is uncompressed, and unstripped. This package also includes the + unstripped modules. + + +Package: linux-modules-7.0.0-1006-nvidia-64k +Build-Profiles: +Architecture: arm64 +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends}, wireless-regdb +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel modules for version 7.0.0 + Contains the corresponding System.map file, the modules built by the + packager, and scripts that try to ensure that the system is not left in an + unbootable state after an update. + . + Supports NVIDIA 64K pages processors. + . + Intended for NVIDIA systems + . + You likely do not want to install this package directly. Instead, install + the linux-nvidia-64k meta-package, which will ensure that upgrades work + correctly, and that supporting packages are also installed. + +Package: linux-headers-7.0.0-1006-nvidia-64k +Build-Profiles: +Architecture: arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, linux-nvidia-headers-7.0.0-1006, ${shlibs:Depends} +Provides: linux-headers, linux-headers-3.0 +Description: Linux kernel headers for version 7.0.0 + This package provides kernel header files for version 7.0.0. + . + This is for sites that want the latest kernel headers. Please read + /usr/share/doc/linux-headers-7.0.0-1006/debian.README.gz for details. + +Package: linux-lib-rust-7.0.0-1006-nvidia-64k +Build-Profiles: +Architecture: amd64 +Multi-Arch: foreign +Section: devel +Priority: optional +Depends: ${misc:Depends}, coreutils +Description: Rust library files related to Linux kernel version 7.0.0 + This package provides kernel library files for version 7.0.0, that allow to + compile out-of-tree kernel modules written in Rust. + +Package: linux-tools-7.0.0-1006-nvidia-64k +Build-Profiles: +Architecture: arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, linux-nvidia-tools-7.0.0-1006 +Description: Linux kernel version specific tools for version 7.0.0-1006 + This package provides the architecture dependant parts for kernel + version locked tools (such as x86_energy_perf_policy) for + version 7.0.0-1006. + +Package: linux-cloud-tools-7.0.0-1006-nvidia-64k +Build-Profiles: +Architecture: arm64 +Section: devel +Priority: optional +Depends: ${misc:Depends}, linux-nvidia-cloud-tools-7.0.0-1006 +Description: Linux kernel version specific cloud tools for version 7.0.0-1006 + This package provides the architecture dependant parts for kernel + version locked tools for cloud for version 7.0.0-1006. + + +Package: linux-buildinfo-7.0.0-1006-nvidia-64k +Build-Profiles: +Architecture: arm64 +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends} +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel buildinfo for version 7.0.0 + This package contains the Linux kernel buildinfo for version 7.0.0. + . + You likely do not want to install this package. + --- linux-nvidia-7.0.0.orig/debian/control.d/bpftool.stub +++ linux-nvidia-7.0.0/debian/control.d/bpftool.stub @@ -0,0 +1,10 @@ +Package: bpftool +Architecture: amd64 armhf arm64 ppc64el riscv64 s390x +Depends: ${misc:Depends}, ${shlibs:Depends} +Breaks: + linux-tools-common (<< 6.14.0-8~), +Replaces: + linux-tools-common (<< 6.14.0-8~), +Description: Inspection and simple manipulation of BPF programs and maps + The bpftool command allows for inspection and simple modification of + Berkeley Packet Filter (BPF) objects on the system. --- linux-nvidia-7.0.0.orig/debian/control.d/flavour-buildinfo.stub +++ linux-nvidia-7.0.0/debian/control.d/flavour-buildinfo.stub @@ -0,0 +1,13 @@ + +Package: linux-buildinfo-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Depends: ${misc:Depends}, ${shlibs:Depends} +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel buildinfo for version PKGVER + This package contains the Linux kernel buildinfo for version PKGVER. + . + You likely do not want to install this package. + --- linux-nvidia-7.0.0.orig/debian/control.d/flavour-module.stub +++ linux-nvidia-7.0.0/debian/control.d/flavour-module.stub @@ -0,0 +1,20 @@ + +Package: linux-modules-MODULE-PKGVER-ABINUM-FLAVOUR +Build-Profiles: +Architecture: ARCH +Section: kernel +Priority: optional +Provides: ${MODULE:rprovides} +Depends: + ${misc:Depends}, + linux-image-PKGVER-ABINUM-FLAVOUR | linux-image-unsigned-PKGVER-ABINUM-FLAVOUR, +Built-Using: ${linux:BuiltUsing} +Description: Linux kernel MODULE modules for version PKGVER-ABINUM + This package provides the Linux kernel MODULE modules for version + PKGVER-ABINUM. + . + You likely do not want to install this package directly. Instead, install the + one of the linux-modules-MODULE-FLAVOUR* meta-packages, + which will ensure that upgrades work correctly, and that supporting packages are + also installed. + --- linux-nvidia-7.0.0.orig/debian/control.d/linux-bpf-dev.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-bpf-dev.stub @@ -0,0 +1,7 @@ +Package: linux-bpf-dev +Architecture: amd64 armhf arm64 i386 ppc64el riscv64 s390x +Depends: ${misc:Depends} +Multi-Arch: same +Description: Headers for BPF development + The vmlinux.h header is provided to allow userspace to build BPF CO-RE + programs targeting the packaged kernel. --- linux-nvidia-7.0.0.orig/debian/control.d/linux-cloud-tools-common.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-cloud-tools-common.stub @@ -0,0 +1,10 @@ +Package: linux-cloud-tools-common +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: kernel +Priority: optional +Depends: ${misc:Depends} +Description: Linux kernel version specific cloud tools for version PKGVER + This package provides the architecture independent parts for kernel + version locked tools for cloud tools for version PKGVER. --- linux-nvidia-7.0.0.orig/debian/control.d/linux-doc.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-doc.stub @@ -0,0 +1,8 @@ +Package: linux-doc +Build-Profiles: +Architecture: all +Section: doc +Priority: optional +Description: Linux kernel specific documentation for version PKGVER + This package is deprecated and it is temporarily provided only for + compatibility reasons. It will be dropped in the future. --- linux-nvidia-7.0.0.orig/debian/control.d/linux-libc-dev.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-libc-dev.stub @@ -0,0 +1,12 @@ +Package: linux-libc-dev +Architecture: amd64 armhf arm64 i386 ppc64el riscv64 s390x +Depends: ${misc:Depends} +Conflicts: linux-kernel-headers +Replaces: linux-kernel-headers +Provides: linux-kernel-headers, aufs-dev +Multi-Arch: same +Description: Linux Kernel Headers for development + This package provides headers from the Linux kernel. These headers + are used by the installed headers for GNU glibc and other system + libraries. They are NOT meant to be used to build third-party modules for + your kernel. Use SRCPKGNAME-headers-* packages for that. --- linux-nvidia-7.0.0.orig/debian/control.d/linux-perf.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-perf.stub @@ -0,0 +1,8 @@ +Package: linux-perf +Architecture: amd64 armhf arm64 ppc64el riscv64 s390x +Depends: ${misc:Depends}, ${shlibs:Depends} +Breaks: + linux-tools-common (<< 6.14.0-8~), +Replaces: + linux-tools-common (<< 6.14.0-8~), +Description: Performance analysis tools for Linux --- linux-nvidia-7.0.0.orig/debian/control.d/linux-source.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-source.stub @@ -0,0 +1,23 @@ +Package: linux-source-PKGVER +Build-Profiles: +Architecture: all +Section: devel +Priority: optional +Provides: linux-source +Depends: ${misc:Depends}, binutils, bzip2, coreutils +Recommends: libc-dev, gcc, make +Suggests: libncurses-dev | ncurses-dev, kernel-package, libqt3-dev +Description: Linux kernel source for version PKGVER with Ubuntu patches + This package provides the source code for the Linux kernel version + PKGVER. + . + This package is mainly meant for other packages to use, in order to build + custom flavours. + . + If you wish to use this package to create a custom Linux kernel, then it + is suggested that you investigate the package kernel-package, which has + been designed to ease the task of creating kernel image packages. + . + If you are simply trying to build third-party modules for your kernel, + you do not want this package. Install the appropriate linux-headers + package instead. --- linux-nvidia-7.0.0.orig/debian/control.d/linux-tools-common.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-tools-common.stub @@ -0,0 +1,16 @@ +Package: linux-tools-common +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: kernel +Priority: optional +Provides: + linux-cpupower, +Recommends: + bpftool (>= 7.6.0+6.14.0-8~), + linux-perf, +Depends: ${misc:Depends}, lsb-release, hwdata +Description: Linux kernel version specific tools for version PKGVER + This package provides the architecture independent parts for kernel + version locked tools (such as perf and x86_energy_perf_policy) for + version PKGVER. --- linux-nvidia-7.0.0.orig/debian/control.d/linux-tools-host.stub +++ linux-nvidia-7.0.0/debian/control.d/linux-tools-host.stub @@ -0,0 +1,9 @@ +Package: linux-tools-host +Build-Profiles: +Architecture: all +Multi-Arch: foreign +Section: kernel +Priority: optional +Depends: ${misc:Depends}, python3 +Description: Linux kernel VM host tools + This package provides kernel tools useful for VM hosts. --- linux-nvidia-7.0.0.orig/debian/copyright +++ linux-nvidia-7.0.0/debian/copyright @@ -0,0 +1,29 @@ +This is the Ubuntu prepackaged version of the Linux kernel. +Linux was written by Linus Torvalds +and others. + +This package was put together by the Ubuntu Kernel Team, from +sources retrieved from upstream linux git. +The sources may be found at most Linux ftp sites, including +ftp://ftp.kernel.org/pub/linux/kernel/ + +This package is currently maintained by the +Ubuntu Kernel Team + +Linux is copyrighted by Linus Torvalds and others. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 dated June, 1991. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +On Ubuntu Linux systems, the complete text of the GNU General +Public License v2 can be found in `/usr/share/common-licenses/GPL-2'. --- linux-nvidia-7.0.0.orig/debian/debian.env +++ linux-nvidia-7.0.0/debian/debian.env @@ -0,0 +1 @@ +DEBIAN=debian.nvidia --- linux-nvidia-7.0.0.orig/debian/gbp.conf +++ linux-nvidia-7.0.0/debian/gbp.conf @@ -0,0 +1,2 @@ +[buildpackage] +debian-tag = Ubuntu-%(version)s --- linux-nvidia-7.0.0.orig/debian/linux-cloud-tools-common.hv-fcopy-daemon.service +++ linux-nvidia-7.0.0/debian/linux-cloud-tools-common.hv-fcopy-daemon.service @@ -0,0 +1,14 @@ +# On Azure/Hyper-V systems start the hv_fcopy_uio_daemon +# +# author "Andy Whitcroft " +[Unit] +Description=Hyper-V File Copy Protocol Daemon +ConditionVirtualization=microsoft +ConditionPathExists=/dev/vmbus/hv_fcopy +BindsTo=sys-devices-virtual-misc-vmbus\x21hv_fcopy.device + +[Service] +ExecStart=/usr/sbin/hv_fcopy_uio_daemon -n + +[Install] +WantedBy=multi-user.target --- linux-nvidia-7.0.0.orig/debian/linux-cloud-tools-common.hv-fcopy-daemon.udev +++ linux-nvidia-7.0.0/debian/linux-cloud-tools-common.hv-fcopy-daemon.udev @@ -0,0 +1 @@ +SUBSYSTEM=="misc", KERNEL=="vmbus/hv_fcopy", TAG+="systemd", ENV{SYSTEMD_WANTS}+="hv-fcopy-daemon.service" --- linux-nvidia-7.0.0.orig/debian/linux-cloud-tools-common.hv-kvp-daemon.service +++ linux-nvidia-7.0.0/debian/linux-cloud-tools-common.hv-kvp-daemon.service @@ -0,0 +1,20 @@ +# On Azure/Hyper-V systems start the hv_kvp_daemon +# +# author "Andy Whitcroft " +[Unit] +Description=Hyper-V KVP Protocol Daemon +ConditionVirtualization=microsoft +ConditionKernelCommandLine=!snapd_recovery_mode +DefaultDependencies=no +BindsTo=sys-devices-virtual-misc-vmbus\x21hv_kvp.device +After=sys-devices-virtual-misc-vmbus\x21hv_kvp.device systemd-remount-fs.service +Before=shutdown.target cloud-init-local.service walinuxagent.service +Conflicts=shutdown.target +RequiresMountsFor=/var/lib/hyperv +ConditionPathExists=/dev/vmbus/hv_kvp + +[Service] +ExecStart=/usr/sbin/hv_kvp_daemon -n + +[Install] +WantedBy=multi-user.target --- linux-nvidia-7.0.0.orig/debian/linux-cloud-tools-common.hv-kvp-daemon.udev +++ linux-nvidia-7.0.0/debian/linux-cloud-tools-common.hv-kvp-daemon.udev @@ -0,0 +1 @@ +SUBSYSTEM=="misc", KERNEL=="vmbus/hv_kvp", TAG+="systemd", ENV{SYSTEMD_WANTS}+="hv-kvp-daemon.service" --- linux-nvidia-7.0.0.orig/debian/linux-cloud-tools-common.hv-vss-daemon.service +++ linux-nvidia-7.0.0/debian/linux-cloud-tools-common.hv-vss-daemon.service @@ -0,0 +1,14 @@ +# On Azure/Hyper-V systems start the hv_vss_daemon +# +# author "Andy Whitcroft " +[Unit] +Description=Hyper-V VSS Protocol Daemon +ConditionVirtualization=microsoft +ConditionPathExists=/dev/vmbus/hv_vss +BindsTo=sys-devices-virtual-misc-vmbus\x21hv_vss.device + +[Service] +ExecStart=/usr/sbin/hv_vss_daemon -n + +[Install] +WantedBy=multi-user.target --- linux-nvidia-7.0.0.orig/debian/linux-cloud-tools-common.hv-vss-daemon.udev +++ linux-nvidia-7.0.0/debian/linux-cloud-tools-common.hv-vss-daemon.udev @@ -0,0 +1 @@ +SUBSYSTEM=="misc", KERNEL=="vmbus/hv_vss", TAG+="systemd", ENV{SYSTEMD_WANTS}+="hv-vss-daemon.service" --- linux-nvidia-7.0.0.orig/debian/linux-cloud-tools-common.intel-sgx-load-module.service +++ linux-nvidia-7.0.0/debian/linux-cloud-tools-common.intel-sgx-load-module.service @@ -0,0 +1,13 @@ +[Unit] +Description=Install SGX kernel module +DefaultDependencies=false +ConditionVirtualization=microsoft + +[Service] +Type=oneshot +RemainAfterExit=true +ExecStart=/sbin/modprobe intel_sgx +ExecStop=/sbin/modprobe -r intel_sgx + +[Install] +WantedBy=multi-user.target --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-2012-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-2012-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 1 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Apr 12 11:39:08 2012 GMT + Not After : Apr 11 11:39:08 2042 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:c9:5f:9b:62:8f:0b:b0:64:82:ac:be:c9:e2:62: + e3:4b:d2:9f:1e:8a:d5:61:1a:2b:5d:38:f4:b7:ce: + b9:9a:b8:43:b8:43:97:77:ab:4f:7f:0c:70:46:0b: + fc:7f:6d:c6:6d:ea:80:5e:01:d2:b7:66:1e:87:de: + 0d:6d:d0:41:97:a8:a5:af:0c:63:4f:f7:7c:c2:52: + cc:a0:31:a9:bb:89:5d:99:1e:46:6f:55:73:b9:76: + 69:ec:d7:c1:fc:21:d6:c6:07:e7:4f:bd:22:de:e4: + a8:5b:2d:db:95:34:19:97:d6:28:4b:21:4c:ca:bb: + 1d:79:a6:17:7f:5a:f9:67:e6:5c:78:45:3d:10:6d: + b0:17:59:26:11:c5:57:e3:7f:4e:82:ba:f6:2c:4e: + c8:37:4d:ff:85:15:84:47:e0:ed:3b:7c:7f:bc:af: + e9:01:05:a7:0c:6f:c3:e9:8d:a3:ce:be:a6:e3:cd: + 3c:b5:58:2c:9e:c2:03:1c:60:22:37:39:ff:41:02: + c1:29:a4:65:51:ff:33:34:aa:42:15:f9:95:78:fc: + 2d:f5:da:8a:85:7c:82:9d:fb:37:2c:6b:a5:a8:df: + 7c:55:0b:80:2e:3c:b0:63:e1:cd:38:48:89:e8:14: + 06:0b:82:bc:fd:d4:07:68:1b:0f:3e:d9:15:dd:94: + 11:1b + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 61:48:2A:A2:83:0D:0A:B2:AD:5A:F1:0B:72:50:DA:90:33:DD:CE:F0 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 8f:8a:a1:06:1f:29:b7:0a:4a:d5:c5:fd:81:ab:25:ea:c0:7d: + e2:fc:6a:96:a0:79:93:67:ee:05:0e:25:12:25:e4:5a:f6:aa: + 1a:f1:12:f3:05:8d:87:5e:f1:5a:5c:cb:8d:23:73:65:1d:15: + b9:de:22:6b:d6:49:67:c9:a3:c6:d7:62:4e:5c:b5:f9:03:83: + 40:81:dc:87:9c:3c:3f:1c:0d:51:9f:94:65:0a:84:48:67:e4: + a2:f8:a6:4a:f0:e7:cd:cd:bd:94:e3:09:d2:5d:2d:16:1b:05: + 15:0b:cb:44:b4:3e:61:42:22:c4:2a:5c:4e:c5:1d:a3:e2:e0: + 52:b2:eb:f4:8b:2b:dc:38:39:5d:fb:88:a1:56:65:5f:2b:4f: + 26:ff:06:78:10:12:eb:8c:5d:32:e3:c6:45:af:25:9b:a0:ff: + 8e:ef:47:09:a3:e9:8b:37:92:92:69:76:7e:34:3b:92:05:67: + 4e:b0:25:ed:bc:5e:5f:8f:b4:d6:ca:40:ff:e4:e2:31:23:0c: + 85:25:ae:0c:55:01:ec:e5:47:5e:df:5b:bc:14:33:e3:c6:f5: + 18:b6:d9:f7:dd:b3:b4:a1:31:d3:5a:5c:5d:7d:3e:bf:0a:e4: + e4:e8:b4:59:7d:3b:b4:8c:a3:1b:b5:20:a3:b9:3e:84:6f:8c: + 21:00:c3:39 +-----BEGIN CERTIFICATE----- +MIIEIDCCAwigAwIBAgIBATANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xMjA0MTIxMTM5MDhaFw00MjA0MTEx +MTM5MDhaMH8xCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEXMBUG +A1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MSswKQYD +VQQDDCJDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nMIIBIjANBgkq +hkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAyV+bYo8LsGSCrL7J4mLjS9KfHorVYRor +XTj0t865mrhDuEOXd6tPfwxwRgv8f23GbeqAXgHSt2Yeh94NbdBBl6ilrwxjT/d8 +wlLMoDGpu4ldmR5Gb1VzuXZp7NfB/CHWxgfnT70i3uSoWy3blTQZl9YoSyFMyrsd +eaYXf1r5Z+ZceEU9EG2wF1kmEcVX439Ogrr2LE7IN03/hRWER+DtO3x/vK/pAQWn +DG/D6Y2jzr6m4808tVgsnsIDHGAiNzn/QQLBKaRlUf8zNKpCFfmVePwt9dqKhXyC +nfs3LGulqN98VQuALjywY+HNOEiJ6BQGC4K8/dQHaBsPPtkV3ZQRGwIDAQABo4Gg +MIGdMAwGA1UdEwEB/wQCMAAwHwYDVR0lBBgwFgYIKwYBBQUHAwMGCisGAQQBgjcK +AwYwLAYJYIZIAYb4QgENBB8WHU9wZW5TU0wgR2VuZXJhdGVkIENlcnRpZmljYXRl +MB0GA1UdDgQWBBRhSCqigw0Ksq1a8QtyUNqQM93O8DAfBgNVHSMEGDAWgBStkZkL +wiqx9RcEjCO2ZVomjjRaYzANBgkqhkiG9w0BAQsFAAOCAQEAj4qhBh8ptwpK1cX9 +gasl6sB94vxqlqB5k2fuBQ4lEiXkWvaqGvES8wWNh17xWlzLjSNzZR0Vud4ia9ZJ +Z8mjxtdiTly1+QODQIHch5w8PxwNUZ+UZQqESGfkovimSvDnzc29lOMJ0l0tFhsF +FQvLRLQ+YUIixCpcTsUdo+LgUrLr9Isr3Dg5XfuIoVZlXytPJv8GeBAS64xdMuPG +Ra8lm6D/ju9HCaPpizeSkml2fjQ7kgVnTrAl7bxeX4+01spA/+TiMSMMhSWuDFUB +7OVHXt9bvBQz48b1GLbZ992ztKEx01pcXX0+vwrk5Oi0WX07tIyjG7Ugo7k+hG+M +IQDDOQ== +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-2017-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-2017-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 2 (0x2) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 26 21:52:11 2017 GMT + Not After : Sep 25 21:52:11 2047 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2017) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:ef:9f:fa:9f:19:3a:9d:38:23:91:cc:c4:f9:42: + e0:f8:54:12:82:dc:97:2c:d6:5b:c1:35:eb:ff:4a: + 74:06:b5:9d:32:aa:7b:f3:fc:31:5a:34:3e:a1:a4: + 44:db:7b:6d:16:af:35:76:e0:9b:99:ad:21:11:c6: + 12:4b:ae:24:8f:bb:d3:b2:00:fe:c5:1d:9b:3a:1a: + 4a:6c:ca:fa:16:37:85:22:f9:ff:22:fc:40:e0:58: + 35:c1:39:27:b4:c6:42:1a:96:d8:a5:c5:95:2e:f7: + c5:1e:21:6e:36:84:f7:a9:a1:e1:f1:03:08:96:65: + 71:f8:eb:83:cf:82:f7:9a:44:58:72:00:14:39:29: + 4b:e9:78:2f:65:20:b3:80:76:3b:ba:0d:2d:46:f6: + 37:05:e7:05:fe:bd:6c:c7:a2:65:b5:06:6e:07:24: + 99:a1:c1:cf:e1:0e:5e:49:41:71:17:a8:50:e7:38: + 99:e5:6e:b6:db:9f:63:db:56:f4:9c:7d:89:f6:d2: + 03:6c:99:83:e0:99:23:39:36:bd:cb:b5:26:7c:7d: + b0:c6:fe:82:7c:52:ed:f9:2c:8f:79:71:3d:a9:2f: + b5:aa:7e:77:a0:fd:69:f9:97:10:a8:b2:c6:7d:88: + 9e:a2:19:bd:31:b8:02:2d:34:4d:9d:98:60:82:ad: + 04:ff + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 24:2A:DE:75:AC:4A:15:E5:0D:50:C8:4B:0D:45:FF:3E:AE:70:7A:03 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 00:b2:b7:57:b5:2b:5d:16:d3:04:88:6a:d7:77:d5:0d:89:f1: + d2:6e:11:d1:8e:f5:62:05:c4:6a:57:df:eb:d2:86:68:f2:fd: + a7:37:11:3c:f4:ce:5d:fe:32:5f:31:a2:6b:3a:da:28:c2:88: + fa:7f:70:b5:25:99:ea:27:9a:56:6a:9d:b2:0f:14:99:e2:b7: + c6:39:1e:8e:a7:76:31:d9:ed:c5:05:8d:48:ae:1b:68:18:14: + 51:a1:7d:f6:c7:df:cb:9d:eb:a4:3b:0b:ff:c2:07:c5:42:bc: + 0d:b2:11:fa:37:17:2b:1c:b5:84:48:2d:f9:31:4a:57:49:8e: + 61:a6:82:11:06:4c:34:ea:9c:2a:47:4d:eb:e0:26:af:da:d2: + c2:08:a0:37:35:7b:73:71:de:0b:c4:ba:c8:34:de:20:04:03: + 6f:46:26:0d:b9:91:02:5b:71:76:cc:45:e4:08:d0:a6:dd:a4: + 50:d3:d9:04:91:2b:d9:5c:34:88:fc:c2:37:fd:c6:d4:3e:57: + f7:6b:ba:7b:d7:02:7a:84:0c:c8:c1:19:cc:bc:fa:52:d5:7f: + b3:35:c4:53:5d:70:0a:f6:44:60:8d:a9:11:7a:1b:7d:ae:7b: + 20:5a:4c:8d:44:f6:c1:a9:61:cb:dc:cb:90:37:d5:28:24:73: + 87:d0:e0:d8 +-----BEGIN CERTIFICATE----- +MIIEKDCCAxCgAwIBAgIBAjANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xNzA5MjYyMTUyMTFaFw00NzA5MjUy +MTUyMTFaMIGGMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDEyMDAG +A1UEAwwpQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoMjAxNykw +ggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDvn/qfGTqdOCORzMT5QuD4 +VBKC3Jcs1lvBNev/SnQGtZ0yqnvz/DFaND6hpETbe20WrzV24JuZrSERxhJLriSP +u9OyAP7FHZs6GkpsyvoWN4Ui+f8i/EDgWDXBOSe0xkIaltilxZUu98UeIW42hPep +oeHxAwiWZXH464PPgveaRFhyABQ5KUvpeC9lILOAdju6DS1G9jcF5wX+vWzHomW1 +Bm4HJJmhwc/hDl5JQXEXqFDnOJnlbrbbn2PbVvScfYn20gNsmYPgmSM5Nr3LtSZ8 +fbDG/oJ8Uu35LI95cT2pL7Wqfneg/Wn5lxCossZ9iJ6iGb0xuAItNE2dmGCCrQT/ +AgMBAAGjgaAwgZ0wDAYDVR0TAQH/BAIwADAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGCNwoDBjAsBglghkgBhvhCAQ0EHxYdT3BlblNTTCBHZW5lcmF0ZWQgQ2Vy +dGlmaWNhdGUwHQYDVR0OBBYEFCQq3nWsShXlDVDISw1F/z6ucHoDMB8GA1UdIwQY +MBaAFK2RmQvCKrH1FwSMI7ZlWiaONFpjMA0GCSqGSIb3DQEBCwUAA4IBAQAAsrdX +tStdFtMEiGrXd9UNifHSbhHRjvViBcRqV9/r0oZo8v2nNxE89M5d/jJfMaJrOtoo +woj6f3C1JZnqJ5pWap2yDxSZ4rfGOR6Op3Yx2e3FBY1IrhtoGBRRoX32x9/Lneuk +Owv/wgfFQrwNshH6NxcrHLWESC35MUpXSY5hpoIRBkw06pwqR03r4Cav2tLCCKA3 +NXtzcd4LxLrINN4gBANvRiYNuZECW3F2zEXkCNCm3aRQ09kEkSvZXDSI/MI3/cbU +Plf3a7p71wJ6hAzIwRnMvPpS1X+zNcRTXXAK9kRgjakReht9rnsgWkyNRPbBqWHL +3MuQN9UoJHOH0ODY +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-2018-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-2018-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 3 (0x3) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Oct 26 18:31:14 2018 GMT + Not After : Oct 24 18:31:14 2048 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (ESM 2018) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:bf:6a:e5:6d:55:7a:ec:7a:11:37:45:9c:4c:8f: + 6b:2d:56:d3:74:2b:32:ac:84:2d:ba:cb:cc:ec:8d: + 92:22:69:48:a5:d4:f6:75:11:66:2f:cb:b2:fd:9e: + 56:ab:e6:f1:52:8e:75:3e:50:bd:25:b3:50:fc:ef: + 3d:76:f3:3f:7f:03:f6:e2:a1:25:69:5c:14:98:54: + bd:11:bf:e9:a5:ac:46:91:4b:1d:de:b7:18:2b:c8: + 22:83:15:a7:4a:00:8d:9d:e4:c0:da:f7:41:02:fd: + 9f:5f:79:93:56:cc:86:e1:b5:e0:39:0e:3c:a2:5b: + fe:c0:56:f0:92:50:5a:2b:67:67:93:56:d7:7a:75: + 99:6a:25:b4:63:a8:5f:69:7e:3a:49:58:2a:a7:80: + f6:5a:b4:be:b2:be:a8:8c:45:41:c9:f2:fc:76:a8: + 65:ef:99:29:0d:c9:9c:54:6b:0a:f0:4a:0e:61:0d: + ed:99:32:af:12:e2:12:7b:9f:7b:ec:05:c4:e0:b6: + d5:c3:71:28:ae:dd:0b:ba:97:ad:68:0b:76:e9:bf: + e7:01:7e:64:54:39:23:85:36:c8:9d:dd:27:a1:ff: + df:46:36:14:7e:cb:cc:a1:cd:49:0b:6d:c2:0c:45: + 99:56:58:7c:87:0d:59:9a:dc:4a:39:3b:1d:d9:15: + 2e:b5 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 36:51:88:C1:D3:74:D6:B0:7C:3C:8F:24:0F:8E:F7:22:43:3D:6A:8B + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 4c:0f:cd:77:60:b4:6f:53:87:f3:3c:4f:e6:81:5f:a7:1c:cc: + 60:29:b6:34:6c:4d:08:9b:e2:d2:bd:f6:17:1a:62:79:b8:17: + bc:a2:60:59:fd:03:51:c3:b7:6b:de:73:b3:48:95:f5:0b:aa: + b6:3c:b4:34:dc:1d:0b:c4:97:62:87:e7:48:d5:8f:c9:ea:e8: + 91:8f:2a:40:cd:b7:b3:ee:b2:98:9e:fb:37:31:29:e6:8e:2f: + 0a:39:99:1e:c6:aa:b8:05:62:85:d3:a8:3e:60:38:98:0f:f0: + fe:c7:ab:01:a5:6a:a5:7f:70:a6:26:94:76:23:2f:08:89:74: + 97:c2:2a:ca:22:3e:7a:ea:22:22:08:07:f4:bb:f6:bc:69:9c: + 4e:44:33:e2:8e:70:17:b0:9b:cb:33:94:66:6d:ff:9a:7d:e9: + 50:b2:e8:90:14:e4:2b:91:cb:a0:c5:2e:0e:cf:19:ef:44:ef: + 84:f0:bd:57:9e:26:c2:63:3d:df:fc:a1:84:de:5c:d7:5f:3b: + fb:94:61:f0:93:89:1f:cf:c3:b2:d1:90:97:35:7d:b9:8a:ad: + e6:05:f0:e8:3b:a1:7c:af:2b:c4:af:18:33:2e:5e:87:db:9d: + 80:b5:04:fd:00:d0:60:ab:ff:85:77:0f:cb:47:22:c9:b2:85: + a8:48:16:e2 +-----BEGIN CERTIFICATE----- +MIIELDCCAxSgAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xODEwMjYxODMxMTRaFw00ODEwMjQx +ODMxMTRaMIGKMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDE2MDQG +A1UEAwwtQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoRVNNIDIw +MTgpMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAv2rlbVV67HoRN0Wc +TI9rLVbTdCsyrIQtusvM7I2SImlIpdT2dRFmL8uy/Z5Wq+bxUo51PlC9JbNQ/O89 +dvM/fwP24qElaVwUmFS9Eb/ppaxGkUsd3rcYK8gigxWnSgCNneTA2vdBAv2fX3mT +VsyG4bXgOQ48olv+wFbwklBaK2dnk1bXenWZaiW0Y6hfaX46SVgqp4D2WrS+sr6o +jEVByfL8dqhl75kpDcmcVGsK8EoOYQ3tmTKvEuISe5977AXE4LbVw3Eort0Lupet +aAt26b/nAX5kVDkjhTbInd0nof/fRjYUfsvMoc1JC23CDEWZVlh8hw1ZmtxKOTsd +2RUutQIDAQABo4GgMIGdMAwGA1UdEwEB/wQCMAAwHwYDVR0lBBgwFgYIKwYBBQUH +AwMGCisGAQQBgjcKAwYwLAYJYIZIAYb4QgENBB8WHU9wZW5TU0wgR2VuZXJhdGVk +IENlcnRpZmljYXRlMB0GA1UdDgQWBBQ2UYjB03TWsHw8jyQPjvciQz1qizAfBgNV +HSMEGDAWgBStkZkLwiqx9RcEjCO2ZVomjjRaYzANBgkqhkiG9w0BAQsFAAOCAQEA +TA/Nd2C0b1OH8zxP5oFfpxzMYCm2NGxNCJvi0r32FxpiebgXvKJgWf0DUcO3a95z +s0iV9Quqtjy0NNwdC8SXYofnSNWPyerokY8qQM23s+6ymJ77NzEp5o4vCjmZHsaq +uAVihdOoPmA4mA/w/serAaVqpX9wpiaUdiMvCIl0l8IqyiI+euoiIggH9Lv2vGmc +TkQz4o5wF7CbyzOUZm3/mn3pULLokBTkK5HLoMUuDs8Z70TvhPC9V54mwmM93/yh +hN5c1187+5Rh8JOJH8/DstGQlzV9uYqt5gXw6DuhfK8rxK8YMy5eh9udgLUE/QDQ +YKv/hXcPy0ciybKFqEgW4g== +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-2019-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-2019-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 4 (0x4) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 18 16:10:17 2019 GMT + Not After : Sep 16 16:10:17 2049 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2019) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:e6:47:d8:75:e5:87:59:26:87:83:7d:5b:7a:b8: + 58:3d:7c:ef:36:f8:a0:7a:b7:14:56:58:7d:01:f1: + 1c:3b:8c:e6:5b:03:77:7d:a0:ed:47:0a:45:e6:75: + 5c:de:95:38:0d:38:fa:41:79:89:56:31:87:e7:a3: + 9a:36:70:b6:cf:24:2f:99:26:89:08:39:0e:14:c3: + 35:be:02:8b:52:e1:8e:7b:0c:a6:9d:78:ff:01:60: + d7:f5:c3:d5:f0:5e:dc:e4:23:09:59:72:93:d3:b5: + 22:af:7c:cd:e0:84:0f:af:11:2d:bc:c6:72:42:af: + ea:67:63:c4:10:41:78:02:80:62:0d:43:74:b4:1c: + ed:50:d7:94:f1:b0:bb:f9:57:80:e4:69:0f:83:4b: + a2:e6:2c:4a:9a:e1:7d:7c:62:19:29:27:97:1f:4c: + f1:85:f0:39:f5:31:9f:3a:39:0e:d4:4d:07:3a:40: + 55:4b:a6:6c:9d:04:89:51:2d:7c:b0:ef:40:b5:42: + 29:16:cc:65:73:38:62:21:f6:e3:2c:17:50:9d:74: + 34:4e:df:7c:4a:33:a4:bb:40:cf:d5:e5:ed:05:07: + cd:4c:f9:af:7f:a6:5c:b9:f7:c5:16:45:4e:44:40: + d7:85:32:de:ac:e5:75:ad:9b:d7:c0:26:33:1f:77: + a5:37 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + C0:74:6F:D6:C5:DA:3A:E8:27:86:46:51:AD:66:AE:47:FE:24:B3:E8 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + aa:12:6c:d1:9d:6a:da:f0:ec:7c:17:46:3b:57:b8:d6:76:5f: + 24:e6:06:a2:0a:55:1f:2f:d3:5e:8f:de:cf:02:f2:ff:e0:dd: + d3:c7:bd:75:59:aa:cd:34:f3:28:80:73:cc:28:69:e7:a2:70: + 88:a2:c7:dc:66:f0:92:0e:ff:64:bf:30:04:54:01:1b:96:ad: + 15:c5:61:fd:32:61:d7:5e:b5:ba:91:fd:31:fc:6b:15:df:ee: + 22:d9:e4:1f:f3:cc:8b:0c:9f:f5:e8:f7:e2:62:3f:40:52:c9: + f0:f1:1c:63:fc:6c:90:e1:5b:74:03:b9:df:d1:3e:a8:ec:db: + 2b:6e:83:6f:9f:7f:ba:b4:79:fc:3d:e7:12:2f:4a:e7:17:8c: + 2b:77:a5:90:74:3c:bd:cf:75:83:0d:1a:95:d5:56:ef:07:9b: + a6:b3:31:e3:8c:97:ce:68:11:b5:7b:25:03:72:1c:ea:67:e9: + 7c:3e:73:c7:7c:3e:fc:f5:ae:8a:b2:07:0d:15:6a:66:09:d7: + 23:b9:5d:80:7a:26:d6:b6:22:30:aa:84:af:c0:42:e9:75:c3: + 59:ab:a3:84:87:6b:0c:b7:ab:4e:92:69:ae:2c:82:6f:ab:01: + 24:ab:ff:78:6d:59:85:c2:3b:23:c0:bd:0d:d8:6e:3a:29:82: + e1:c4:5f:db +-----BEGIN CERTIFICATE----- +MIIEKDCCAxCgAwIBAgIBBDANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAeFw0xOTA5MTgxNjEwMTdaFw00OTA5MTYx +NjEwMTdaMIGGMQswCQYDVQQGEwJHQjEUMBIGA1UECAwLSXNsZSBvZiBNYW4xFzAV +BgNVBAoMDkNhbm9uaWNhbCBMdGQuMRQwEgYDVQQLDAtTZWN1cmUgQm9vdDEyMDAG +A1UEAwwpQ2Fub25pY2FsIEx0ZC4gU2VjdXJlIEJvb3QgU2lnbmluZyAoMjAxOSkw +ggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDmR9h15YdZJoeDfVt6uFg9 +fO82+KB6txRWWH0B8Rw7jOZbA3d9oO1HCkXmdVzelTgNOPpBeYlWMYfno5o2cLbP +JC+ZJokIOQ4UwzW+AotS4Y57DKadeP8BYNf1w9XwXtzkIwlZcpPTtSKvfM3ghA+v +ES28xnJCr+pnY8QQQXgCgGINQ3S0HO1Q15TxsLv5V4DkaQ+DS6LmLEqa4X18Yhkp +J5cfTPGF8Dn1MZ86OQ7UTQc6QFVLpmydBIlRLXyw70C1QikWzGVzOGIh9uMsF1Cd +dDRO33xKM6S7QM/V5e0FB81M+a9/ply598UWRU5EQNeFMt6s5XWtm9fAJjMfd6U3 +AgMBAAGjgaAwgZ0wDAYDVR0TAQH/BAIwADAfBgNVHSUEGDAWBggrBgEFBQcDAwYK +KwYBBAGCNwoDBjAsBglghkgBhvhCAQ0EHxYdT3BlblNTTCBHZW5lcmF0ZWQgQ2Vy +dGlmaWNhdGUwHQYDVR0OBBYEFMB0b9bF2jroJ4ZGUa1mrkf+JLPoMB8GA1UdIwQY +MBaAFK2RmQvCKrH1FwSMI7ZlWiaONFpjMA0GCSqGSIb3DQEBCwUAA4IBAQCqEmzR +nWra8Ox8F0Y7V7jWdl8k5gaiClUfL9Nej97PAvL/4N3Tx711WarNNPMogHPMKGnn +onCIosfcZvCSDv9kvzAEVAEblq0VxWH9MmHXXrW6kf0x/GsV3+4i2eQf88yLDJ/1 +6PfiYj9AUsnw8Rxj/GyQ4Vt0A7nf0T6o7NsrboNvn3+6tHn8PecSL0rnF4wrd6WQ +dDy9z3WDDRqV1VbvB5umszHjjJfOaBG1eyUDchzqZ+l8PnPHfD789a6KsgcNFWpm +CdcjuV2AeibWtiIwqoSvwELpdcNZq6OEh2sMt6tOkmmuLIJvqwEkq/94bVmFwjsj +wL0N2G46KYLhxF/b +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-2021v1-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-2021v1-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 6 (0x6) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:29:32 2021 GMT + Not After : Sep 22 19:29:32 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v1) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:aa:b8:34:5b:b6:ae:44:bf:41:e1:78:11:b9:7a: + c8:88:b3:b0:26:50:10:9c:98:d1:f3:98:9f:23:50: + 64:f6:39:dd:50:3a:23:44:53:65:fc:f3:9f:f5:a5: + 8b:ae:8b:df:47:9f:e9:d5:a0:92:19:f1:21:ea:cc: + 59:3a:74:df:45:71:bc:de:64:15:a5:f6:db:ca:71: + fa:19:d4:44:0d:12:ec:47:3a:43:e2:f2:dd:8b:fe: + 0d:7b:dc:4d:db:53:06:22:61:e5:8b:35:49:b6:33: + c4:0a:69:5f:5b:81:09:84:6b:42:33:18:09:9d:a0: + 35:f7:9c:1e:de:6e:de:90:69:1a:e8:32:e4:49:ad: + c3:31:e9:f8:4a:a2:28:1d:db:0d:29:b6:48:0a:44: + 93:86:41:62:8f:73:97:60:10:8a:74:46:66:55:fe: + a0:95:35:9e:ef:9f:af:11:fa:5b:a3:7c:c2:35:64: + 11:67:28:1e:14:0a:7d:68:61:9c:cd:c7:46:39:30: + 31:79:94:56:b3:45:16:9a:b5:77:66:fe:41:43:0f: + 00:48:6e:99:dd:0c:d4:47:2c:86:8c:50:04:61:20: + dd:aa:8e:73:4f:21:b4:ee:09:4d:d3:40:01:d0:f2: + a7:5b:7d:05:3d:c1:e7:65:26:aa:8c:9a:58:5a:7c: + 6d:6f + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + A8:D5:4B:BB:38:25:CF:B9:4F:A1:3C:9F:8A:59:4A:19:5C:10:7B:8D + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 24:25:25:7e:01:a5:c8:3d:54:8c:1b:05:73:d1:06:d8:db:d4: + 3a:71:d5:19:9d:97:1c:85:3c:ca:38:5a:0c:25:25:39:1a:67: + bc:6c:9d:98:6c:f3:7d:5f:b7:40:f9:73:a0:f5:7b:40:a8:66: + a5:f1:53:b1:78:80:24:3f:19:50:2f:02:09:ec:a1:8a:e6:0d: + df:c4:ae:24:9e:69:0d:5c:dc:44:4c:38:3a:53:4e:4b:a1:4b: + 92:9f:43:a4:9d:1e:76:33:18:1b:bf:62:e5:f5:bc:93:3c:4e: + 21:d5:5b:20:69:11:28:c1:c5:93:b5:8e:96:1d:1b:ca:72:79: + 24:de:67:2a:50:9d:ce:8b:41:dd:3e:82:dd:a5:04:75:54:fb: + 35:70:98:87:b4:f3:ea:41:23:23:80:0e:99:d7:03:16:ee:7e: + 11:e2:c8:29:ab:73:c5:6d:5c:a8:2f:32:03:9f:8e:66:d6:cb: + 54:84:55:75:ab:9a:dd:95:fd:05:1e:11:85:37:1e:63:d2:f4: + 7f:34:64:32:a1:63:91:91:50:39:14:1a:ea:54:78:e6:0d:04: + 23:c7:83:51:c5:25:27:07:6c:f8:65:b7:da:95:89:76:83:cc: + f3:7e:06:74:d3:6c:ef:e9:17:de:29:1e:ab:5c:d7:ec:df:f1: + 98:b8:e9:66 +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBBjANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTI5MzJaGA8yMDUxMDky +MjE5MjkzMlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYxKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKq4NFu2rkS/QeF4 +Ebl6yIizsCZQEJyY0fOYnyNQZPY53VA6I0RTZfzzn/Wli66L30ef6dWgkhnxIerM +WTp030VxvN5kFaX228px+hnURA0S7Ec6Q+Ly3Yv+DXvcTdtTBiJh5Ys1SbYzxApp +X1uBCYRrQjMYCZ2gNfecHt5u3pBpGugy5EmtwzHp+EqiKB3bDSm2SApEk4ZBYo9z +l2AQinRGZlX+oJU1nu+frxH6W6N8wjVkEWcoHhQKfWhhnM3HRjkwMXmUVrNFFpq1 +d2b+QUMPAEhumd0M1EcshoxQBGEg3aqOc08htO4JTdNAAdDyp1t9BT3B52Umqoya +WFp8bW8CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUqNVLuzglz7lPoTyfillKGVwQe40wHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +ACQlJX4Bpcg9VIwbBXPRBtjb1Dpx1RmdlxyFPMo4WgwlJTkaZ7xsnZhs831ft0D5 +c6D1e0CoZqXxU7F4gCQ/GVAvAgnsoYrmDd/EriSeaQ1c3ERMODpTTkuhS5KfQ6Sd +HnYzGBu/YuX1vJM8TiHVWyBpESjBxZO1jpYdG8pyeSTeZypQnc6LQd0+gt2lBHVU ++zVwmIe08+pBIyOADpnXAxbufhHiyCmrc8VtXKgvMgOfjmbWy1SEVXWrmt2V/QUe +EYU3HmPS9H80ZDKhY5GRUDkUGupUeOYNBCPHg1HFJScHbPhlt9qViXaDzPN+BnTT +bO/pF94pHqtc1+zf8Zi46WY= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-2021v2-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-2021v2-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 7 (0x7) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:29:42 2021 GMT + Not After : Sep 22 19:29:42 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v2) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:ba:06:8b:ee:58:b7:8b:49:7b:53:7a:d1:df:02: + e3:f2:d8:b0:8c:03:5c:f4:2d:0b:d8:18:3b:23:fa: + 68:b0:e8:e9:9d:dc:a2:eb:5e:d3:06:a9:28:d4:9f: + 14:b6:1e:1c:1d:ef:69:0e:7f:44:f2:cc:4a:f1:b1: + d0:71:30:6a:50:1e:b0:d3:f8:a4:19:d0:4a:f1:e3: + eb:7a:e5:57:4c:a1:fb:d1:87:b9:48:e0:55:37:52: + f9:de:99:2e:95:85:36:ce:d3:1d:67:2f:14:cb:7f: + 05:82:75:21:b6:aa:a5:14:ac:da:4a:f4:fe:fa:5c: + 33:49:3d:6f:de:fd:9d:75:ba:e2:c4:02:38:b5:69: + f5:ff:a8:67:4b:3a:e0:34:f6:3b:07:03:a5:7e:59: + 6f:3a:d2:28:a4:2f:25:ac:d8:a9:1f:59:52:5d:24: + 36:58:51:b5:f0:12:a8:d3:78:56:57:b1:e0:a9:df: + 14:05:65:7c:b5:a5:00:f0:88:39:14:44:18:85:2d: + 0c:28:69:7b:b9:b4:1c:47:6f:43:66:4c:22:ad:f7: + f6:19:75:e1:14:2c:0d:33:3f:c1:3f:fc:73:56:b2: + 68:05:b5:92:03:9b:65:6b:81:80:92:35:03:9b:66: + 68:58:c5:66:11:b6:8c:7f:05:09:9a:45:a6:0e:5e: + 5f:bf + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 4C:F0:46:89:2D:6F:D3:C9:A5:B0:3F:98:D8:45:F9:08:51:DC:6A:8C + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 93:9d:49:7d:9f:3e:3e:27:79:97:d9:c2:fc:0b:f7:30:b7:f4: + 78:b2:c9:e4:5e:42:d3:27:26:70:cf:88:96:d1:f2:ea:a0:75: + 7e:3c:f6:b7:d2:e7:95:30:e3:a6:67:a7:ee:b9:53:8f:fd:b2: + cb:db:e1:98:32:be:98:79:09:46:c6:63:6a:57:87:4d:b2:26: + 46:f6:34:5e:18:75:ca:82:80:8e:33:c2:1d:c7:76:d7:14:57: + ef:2e:0e:9e:58:5c:81:8e:ed:53:2c:07:46:0a:8a:fc:2f:f5: + b2:c8:58:f5:fa:fa:bb:f9:7d:47:13:39:f0:f2:1c:15:9c:75: + 90:40:bd:08:04:b3:6a:de:c2:cd:34:21:7e:ba:31:48:bc:a1: + 23:bc:ee:93:b2:62:96:27:30:86:c2:d4:f7:b4:e6:3c:71:47: + 37:84:ff:3d:0c:1e:ec:f3:0e:da:6b:dc:64:7a:b8:c0:7e:45: + 13:09:bf:02:b3:b7:5b:6d:09:2d:6a:4e:0b:93:94:29:4c:a6: + c3:c7:05:fa:69:08:04:53:3c:4c:64:c0:7e:89:00:91:1b:a6: + c2:d7:ea:c4:db:86:38:fe:66:03:85:7b:fc:39:24:99:4c:2a: + 3e:10:8b:91:c3:6e:20:9d:0c:ee:51:70:b5:98:58:f3:5c:ac: + 16:98:7b:ce +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBBzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTI5NDJaGA8yMDUxMDky +MjE5Mjk0MlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYyKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALoGi+5Yt4tJe1N6 +0d8C4/LYsIwDXPQtC9gYOyP6aLDo6Z3coute0wapKNSfFLYeHB3vaQ5/RPLMSvGx +0HEwalAesNP4pBnQSvHj63rlV0yh+9GHuUjgVTdS+d6ZLpWFNs7THWcvFMt/BYJ1 +IbaqpRSs2kr0/vpcM0k9b979nXW64sQCOLVp9f+oZ0s64DT2OwcDpX5ZbzrSKKQv +JazYqR9ZUl0kNlhRtfASqNN4Vlex4KnfFAVlfLWlAPCIORREGIUtDChpe7m0HEdv +Q2ZMIq339hl14RQsDTM/wT/8c1ayaAW1kgObZWuBgJI1A5tmaFjFZhG2jH8FCZpF +pg5eX78CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUTPBGiS1v08mlsD+Y2EX5CFHcaowwHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +AJOdSX2fPj4neZfZwvwL9zC39HiyyeReQtMnJnDPiJbR8uqgdX489rfS55Uw46Zn +p+65U4/9ssvb4Zgyvph5CUbGY2pXh02yJkb2NF4YdcqCgI4zwh3HdtcUV+8uDp5Y +XIGO7VMsB0YKivwv9bLIWPX6+rv5fUcTOfDyHBWcdZBAvQgEs2rews00IX66MUi8 +oSO87pOyYpYnMIbC1Pe05jxxRzeE/z0MHuzzDtpr3GR6uMB+RRMJvwKzt1ttCS1q +TguTlClMpsPHBfppCARTPExkwH6JAJEbpsLX6sTbhjj+ZgOFe/w5JJlMKj4Qi5HD +biCdDO5RcLWYWPNcrBaYe84= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-2021v3-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-2021v3-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 8 (0x8) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Sep 23 19:30:02 2021 GMT + Not After : Sep 22 19:30:02 2051 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v3) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:d6:29:96:87:ae:07:42:45:bb:65:09:b2:9b:de: + 5d:8e:78:61:10:d5:6d:ae:ae:26:08:6a:06:ec:4a: + dd:2b:e7:1a:a9:ad:78:e3:fc:cf:8f:d1:47:bd:1e: + 33:d8:7a:e3:66:9b:e9:73:c1:5f:42:e2:fe:bc:c3: + 41:f7:cd:d7:85:d7:42:c9:ea:31:e5:47:b1:93:5b: + 43:2b:07:51:b8:75:08:ad:0f:e7:0d:81:38:5a:21: + df:b1:43:5b:db:37:c5:ac:aa:14:3a:33:19:6a:26: + e0:05:fe:cd:41:31:af:5d:a8:ab:31:77:44:fc:da: + 00:e2:7a:44:33:c3:a7:ed:13:54:9f:19:5d:c9:98: + a2:3b:af:4d:0d:87:29:9c:90:9e:42:9e:9a:06:6a: + 70:27:c5:aa:f7:a2:f2:88:e0:b9:66:9a:72:a0:f6: + 61:7e:30:8f:14:9f:44:0d:dd:54:ae:47:c8:82:ba: + d2:b2:db:6f:24:c1:f4:0a:81:07:90:47:49:5f:57: + d6:3f:bf:2a:73:98:f2:f6:24:1a:74:03:d7:35:f0: + 42:d8:14:c5:94:27:5d:3c:49:0c:b0:f0:7a:61:1b: + d7:5a:e3:a3:40:57:e9:a4:07:ee:02:a3:32:27:94: + bb:f3:36:c5:5f:ef:d3:07:04:3a:80:4c:9c:0a:b7: + 88:9f + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + 10:04:37:BB:6D:E6:E4:69:B5:81:E6:1C:D6:6B:CE:3E:F4:ED:53:AF + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 3b:37:d6:a8:8d:cd:d2:df:13:35:ac:8c:92:d6:b0:ac:d1:38: + a8:00:97:47:59:b8:4a:84:8c:80:a5:1d:c7:29:bf:00:66:e5: + 10:40:26:2e:31:f5:e1:13:c0:1b:29:f3:0b:7e:2d:71:d8:db: + e1:32:8f:79:8e:e3:97:0c:40:a9:a0:12:c1:fc:c2:50:88:72: + 44:c5:bc:8b:45:6e:28:fd:d2:37:d6:db:17:cf:4e:61:33:08: + 5a:5d:08:94:73:44:e2:76:00:44:1b:b8:00:a1:86:00:64:8a: + f1:42:32:3c:28:11:67:7c:8b:aa:06:34:74:58:e8:b3:3a:36: + 8d:f6:04:5d:37:f5:66:52:c9:48:b0:a7:6f:34:09:dd:60:2a: + 86:b9:14:f1:09:f6:06:16:56:e0:51:b1:e8:75:7f:fa:37:dc: + e0:98:a7:69:ae:7b:1a:73:89:0d:06:67:cc:01:ef:80:31:45: + 9e:bb:03:2a:eb:89:70:d6:19:b2:c7:ce:bc:81:df:da:c8:6f: + a9:4b:2d:d7:a7:e1:af:c6:e8:fb:f0:61:c9:cd:d2:91:cd:8b: + c2:6c:ef:e0:b6:7f:f1:c4:81:f9:bb:76:9c:26:e3:fa:a1:a0: + cd:5e:05:de:ee:f9:1b:5b:50:0a:8b:0f:47:e3:90:32:ac:2a: + e7:65:02:80 +-----BEGIN CERTIFICATE----- +MIIELTCCAxWgAwIBAgIBCDANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMTA5MjMxOTMwMDJaGA8yMDUxMDky +MjE5MzAwMlowgYkxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MTUw +MwYDVQQDDCxDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nICgyMDIx +IHYzKTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBANYploeuB0JFu2UJ +spveXY54YRDVba6uJghqBuxK3SvnGqmteOP8z4/RR70eM9h642ab6XPBX0Li/rzD +QffN14XXQsnqMeVHsZNbQysHUbh1CK0P5w2BOFoh37FDW9s3xayqFDozGWom4AX+ +zUExr12oqzF3RPzaAOJ6RDPDp+0TVJ8ZXcmYojuvTQ2HKZyQnkKemgZqcCfFqvei +8ojguWaacqD2YX4wjxSfRA3dVK5HyIK60rLbbyTB9AqBB5BHSV9X1j+/KnOY8vYk +GnQD1zXwQtgUxZQnXTxJDLDwemEb11rjo0BX6aQH7gKjMieUu/M2xV/v0wcEOoBM +nAq3iJ8CAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQYMBYGCCsGAQUF +BwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NMIEdlbmVyYXRl +ZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUEAQ3u23m5Gm1geYc1mvOPvTtU68wHwYD +VR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcNAQELBQADggEB +ADs31qiNzdLfEzWsjJLWsKzROKgAl0dZuEqEjIClHccpvwBm5RBAJi4x9eETwBsp +8wt+LXHY2+Eyj3mO45cMQKmgEsH8wlCIckTFvItFbij90jfW2xfPTmEzCFpdCJRz +ROJ2AEQbuAChhgBkivFCMjwoEWd8i6oGNHRY6LM6No32BF039WZSyUiwp280Cd1g +Koa5FPEJ9gYWVuBRseh1f/o33OCYp2muexpziQ0GZ8wB74AxRZ67AyrriXDWGbLH +zryB39rIb6lLLden4a/G6PvwYcnN0pHNi8Js7+C2f/HEgfm7dpwm4/qhoM1eBd7u ++RtbUAqLD0fjkDKsKudlAoA= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/revoked-certs/canonical-uefi-uc2019-all.pem +++ linux-nvidia-7.0.0/debian/revoked-certs/canonical-uefi-uc2019-all.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 3 (0x3) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C = GB, ST = Isle of Man, L = Douglas, O = Canonical Ltd., CN = Canonical Ltd. Master Certificate Authority + Validity + Not Before: Mar 4 10:27:14 2020 GMT + Not After : Mar 3 10:27:14 2050 GMT + Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (Ubuntu Core 2019) + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:b9:10:47:2e:75:5d:f3:10:23:bb:a0:75:d2:fa: + 02:2d:ff:22:df:c1:e6:cd:38:7c:36:0f:ae:74:15: + 6e:a5:34:52:2b:c3:a4:3a:60:d7:06:ee:1d:99:93: + ff:66:91:a3:18:52:2c:8c:58:e6:b4:2f:4b:c5:fb: + 83:e6:f3:19:bd:1b:ca:23:ec:97:1f:d8:f1:9a:f1: + 04:da:da:10:04:53:4b:ec:1d:b6:26:47:7c:bb:8f: + a7:0a:6e:2e:e8:91:e6:c4:bb:64:34:78:3c:fa:09: + 15:1c:8f:9e:eb:04:99:36:22:c6:8d:07:15:0f:b9: + 69:08:fa:ff:4b:45:bd:ba:2b:cd:01:0e:e7:01:23: + c9:e5:7a:39:3b:91:b0:45:3c:d5:77:ba:ca:f9:29: + 3d:11:3f:1c:6b:5b:8e:6c:4b:3f:c9:29:05:cb:59: + d6:b1:c1:c0:2d:56:88:70:27:fa:73:05:5c:c2:11: + d4:27:11:f7:0b:c2:d5:68:d3:1a:cd:ed:d0:e4:10: + ff:34:cb:b7:45:70:34:2c:23:53:b6:9c:30:70:b4: + 5c:d1:e2:64:18:82:8f:62:b1:5e:aa:0b:d4:89:f2: + 1c:53:c4:32:7d:ef:53:ee:9b:6e:02:ab:78:bd:25: + 67:8b:39:36:d8:84:3b:06:99:02:d6:75:73:4e:f2: + f6:b9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Basic Constraints: critical + CA:FALSE + X509v3 Extended Key Usage: + Code Signing, 1.3.6.1.4.1.311.10.3.6 + Netscape Comment: + OpenSSL Generated Certificate + X509v3 Subject Key Identifier: + C1:D5:7B:8F:6B:74:3F:23:EE:41:F4:F7:EE:29:2F:06:EE:CA:DF:B9 + X509v3 Authority Key Identifier: + AD:91:99:0B:C2:2A:B1:F5:17:04:8C:23:B6:65:5A:26:8E:34:5A:63 + Signature Algorithm: sha256WithRSAEncryption + Signature Value: + 2d:b5:11:a8:d2:a0:af:81:a0:18:22:18:2c:08:d0:f4:63:e8: + 8f:9a:f4:f5:20:dd:eb:22:77:19:9a:1a:09:3d:7f:aa:7d:c9: + 81:bc:26:98:65:94:46:30:4b:c2:51:7c:f7:21:41:63:87:31: + fc:a4:c9:41:28:c7:2e:2a:2e:d8:a8:75:7a:72:77:3b:1b:9f: + 72:15:0d:0c:96:8d:8b:51:f3:ce:37:b6:ca:9f:ca:59:40:4a: + fc:73:7a:94:12:99:aa:c2:8d:52:ce:91:19:2e:b4:da:ff:e5: + 2c:67:74:d9:58:47:38:2f:61:88:c5:cf:a7:48:e1:08:ba:bc: + ec:d5:3a:47:d9:8c:dc:c3:bc:cb:98:2b:79:7a:02:46:ef:85: + 19:2f:03:4b:05:84:eb:56:98:5f:6d:cf:a5:8b:a2:b6:e5:50: + 51:7c:33:44:bd:7a:94:2e:0d:90:39:39:3e:62:60:ae:3a:e2: + f5:17:fa:f1:94:06:1d:ae:a3:f8:19:20:7f:4b:4c:07:c4:e6: + 2d:0d:e5:94:84:51:6d:6f:0f:c4:c6:79:1d:f0:e8:0e:23:9e: + fd:f9:46:2c:b9:ec:97:38:56:7e:b8:13:f6:d2:e1:8e:a5:93: + 02:7b:6e:dd:33:9a:bf:10:a8:1b:3d:fa:c4:f2:15:f0:27:73: + 26:a6:94:d1 +-----BEGIN CERTIFICATE----- +MIIENjCCAx6gAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBhDELMAkGA1UEBhMCR0Ix +FDASBgNVBAgMC0lzbGUgb2YgTWFuMRAwDgYDVQQHDAdEb3VnbGFzMRcwFQYDVQQK +DA5DYW5vbmljYWwgTHRkLjE0MDIGA1UEAwwrQ2Fub25pY2FsIEx0ZC4gTWFzdGVy +IENlcnRpZmljYXRlIEF1dGhvcml0eTAgFw0yMDAzMDQxMDI3MTRaGA8yMDUwMDMw +MzEwMjcxNFowgZIxCzAJBgNVBAYTAkdCMRQwEgYDVQQIDAtJc2xlIG9mIE1hbjEX +MBUGA1UECgwOQ2Fub25pY2FsIEx0ZC4xFDASBgNVBAsMC1NlY3VyZSBCb290MT4w +PAYDVQQDDDVDYW5vbmljYWwgTHRkLiBTZWN1cmUgQm9vdCBTaWduaW5nIChVYnVu +dHUgQ29yZSAyMDE5KTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALkQ +Ry51XfMQI7ugddL6Ai3/It/B5s04fDYPrnQVbqU0UivDpDpg1wbuHZmT/2aRoxhS +LIxY5rQvS8X7g+bzGb0byiPslx/Y8ZrxBNraEARTS+wdtiZHfLuPpwpuLuiR5sS7 +ZDR4PPoJFRyPnusEmTYixo0HFQ+5aQj6/0tFvborzQEO5wEjyeV6OTuRsEU81Xe6 +yvkpPRE/HGtbjmxLP8kpBctZ1rHBwC1WiHAn+nMFXMIR1CcR9wvC1WjTGs3t0OQQ +/zTLt0VwNCwjU7acMHC0XNHiZBiCj2KxXqoL1InyHFPEMn3vU+6bbgKreL0lZ4s5 +NtiEOwaZAtZ1c07y9rkCAwEAAaOBoDCBnTAMBgNVHRMBAf8EAjAAMB8GA1UdJQQY +MBYGCCsGAQUFBwMDBgorBgEEAYI3CgMGMCwGCWCGSAGG+EIBDQQfFh1PcGVuU1NM +IEdlbmVyYXRlZCBDZXJ0aWZpY2F0ZTAdBgNVHQ4EFgQUwdV7j2t0PyPuQfT37ikv +Bu7K37kwHwYDVR0jBBgwFoAUrZGZC8IqsfUXBIwjtmVaJo40WmMwDQYJKoZIhvcN +AQELBQADggEBAC21EajSoK+BoBgiGCwI0PRj6I+a9PUg3esidxmaGgk9f6p9yYG8 +JphllEYwS8JRfPchQWOHMfykyUEoxy4qLtiodXpydzsbn3IVDQyWjYtR8843tsqf +yllASvxzepQSmarCjVLOkRkutNr/5SxndNlYRzgvYYjFz6dI4Qi6vOzVOkfZjNzD +vMuYK3l6AkbvhRkvA0sFhOtWmF9tz6WLorblUFF8M0S9epQuDZA5OT5iYK464vUX ++vGUBh2uo/gZIH9LTAfE5i0N5ZSEUW1vD8TGeR3w6A4jnv35Riy57Jc4Vn64E/bS +4Y6lkwJ7bt0zmr8QqBs9+sTyFfAncyamlNE= +-----END CERTIFICATE----- --- linux-nvidia-7.0.0.orig/debian/rules +++ linux-nvidia-7.0.0/debian/rules @@ -0,0 +1,206 @@ +#!/usr/bin/make -f +# +# $(DEBIAN)/rules for Ubuntu linux +# +# Use this however you want, just give credit where credit is due. +# +# Copyright (c) 2007 Ben Collins +# + +# Do not use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour) +MAKEFLAGS += -rR + +# Allow to run debian/rules directly without root +export DEB_RULES_REQUIRES_ROOT := no + +.NOTPARALLEL: + +DEBIAN=$(shell awk -F= '($$1 == "DEBIAN") { print $$2 }' "debian/substvars" + echo "$(foreach dkms,$(all_standalone_dkms_modules),$(dkms):rprovides=$(strip $(foreach provides,$(dkms_$(dkms)_rprovides),$(provides)$(comma)))=NL=)" | sed -e 's/~(/ (/g' -e 's/, (/ (/g' -e 's/=NL= */\n/g' >>"debian/substvars" + +.PHONY: distclean +distclean: clean + rm -rf debian/control debian/changelog + +# Builds the image, arch headers and debug packages +include debian/rules.d/2-binary-arch.mk + +# Builds the source and linux-headers indep packages +include debian/rules.d/3-binary-indep.mk + +# Calculate Ubuntu Compatible Signing levels +UBUNTU_COMPATIBLE_SIGNING=$(shell /bin/sh debian/scripts/ubuntu-compatible-signing) + +# Misc stuff +debian/control: debian/canonical-revoked-certs.pem debian/canonical-certs.pem $(DEBIAN)/changelog FORCE + $(SHELL) debian/scripts/control-create $(DEB_SOURCE) > $@ + sed -i -e 's/PKGVER/$(DEB_VERSION_UPSTREAM)/g' \ + -e 's/ABINUM/$(abinum)/g' \ + -e 's/SRCPKGNAME/$(DEB_SOURCE)/g' \ + -e 's/=SERIES=/$(DEB_DISTRIBUTION)/g' \ + -e 's|\(^Maintainer:.*\)|\1\nXSC-Ubuntu-Compatible-Signing: $(UBUNTU_COMPATIBLE_SIGNING)|g' \ + -e 's/\(^Build-Depends:$$\)/\1\n$(GCC_BUILD_DEPENDS)/g' \ + $@ + +debian/canonical-certs.pem: $(wildcard debian/certs/*.pem $(DEBIAN)/certs/*.pem) + for cert in $(sort $(notdir $^)); \ + do \ + for dir in $(DEBIAN) debian; \ + do \ + if [ -f "$$dir/certs/$$cert" ]; then \ + cat "$$dir/certs/$$cert"; \ + break; \ + fi; \ + done; \ + done >"$@" + +debian/canonical-revoked-certs.pem: $(wildcard debian/revoked-certs/*.pem $(DEBIAN)/revoked-certs/*.pem) + for cert in $(sort $(notdir $^)); \ + do \ + for dir in $(DEBIAN) debian; \ + do \ + if [ -f "$$dir/revoked-certs/$$cert" ]; then \ + cat "$$dir/revoked-certs/$$cert"; \ + break; \ + fi; \ + done; \ + done >"$@" + +# delete partially updated (i.e. corrupted) files on error +.DELETE_ON_ERROR: + +# Add FORCE to the prerequisites of a target to force it to be always rebuilt. +.PHONY: FORCE debian/canonical-certs.pem debian/canonical-revoked-certs.pem --- linux-nvidia-7.0.0.orig/debian/rules.d/0-common-vars.mk +++ linux-nvidia-7.0.0/debian/rules.d/0-common-vars.mk @@ -0,0 +1,269 @@ +# Used when you need to 'escape' a comma. +comma = , +empty := +space := $(empty) $(empty) + +# We cannot include /usr/share/dpkg/pkg-info.mk because the variables defined +# here depend on the $(DEBIAN) directory, which can vary between kernels. +# Instead, this file will define the same variables but using the $(DEBIAN) +# variable to use the correct files. + +# The source package name will be the first token from $(DEBIAN)/changelog +DEB_SOURCE := $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -S source) + +# Get the series +DEB_DISTRIBUTION := $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -S distribution | sed -e 's/-\(security\|updates\|proposed\)$$//') + +# Get some version info +DEB_VERSION := $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -S version) +DEB_REVISION ?= $(lastword $(subst -,$(space),$(DEB_VERSION))) +DEB_VERSION_UPSTREAM := $(patsubst %-$(DEB_REVISION),%,$(DEB_VERSION)) + +DEB_VERSION_PREV ?= $(shell dpkg-parsechangelog -l$(DEBIAN)/changelog -o1 -c1 -S version) +DEB_REVISION_PREV := $(lastword 0.0 $(subst -,$(space),$(DEB_VERSION_PREV))) + +# Get upstream version info +upstream_version := $(shell sed -n 's/^VERSION = \(.*\)$$/\1/p' Makefile) +upstream_patchlevel := $(shell sed -n 's/^PATCHLEVEL = \(.*\)$$/\1/p' Makefile) +upstream_tag := "v$(upstream_version).$(upstream_patchlevel)" + +# Get the kernels own extra version to be added to the release signature. +raw_kernelversion := $(shell make -s kernelversion) + +packages_enabled := $(shell dh_listpackages 2>/dev/null) +define if_package +$(if $(filter $(1),$(packages_enabled)),$(2)) +endef + +stamp = [ -d $(dir $@) ] || mkdir $(dir $@); touch $@ + +# +# do_full_build -- are we doing a full buildd style build, i.e., are we +# building in a PPA +# +ifeq ($(wildcard /CurrentlyBuilding),) + do_full_build ?= false +else + do_full_build ?= true +endif + +# +# The debug packages are ginormous, so you probably want to skip +# building them (as a developer). +# +do_dbgsym_package = true +ifeq ($(do_full_build),false) + do_dbgsym_package = false +endif +ifeq ($(filter $(DEB_BUILD_OPTIONS),noautodbgsym),noautodbgsym) + # Disable debug package builds if we're building in a PPA that has the + # 'Build debug symbols' option disabled + do_dbgsym_package = false +endif + +abinum := $(firstword $(subst .,$(space),$(DEB_REVISION))) +abi_release := $(DEB_VERSION_UPSTREAM)-$(abinum) + +uploadnum := $(patsubst $(abinum).%,%,$(DEB_REVISION)) +ifneq ($(do_full_build),false) + uploadnum := $(uploadnum)-Ubuntu +endif + +DEB_HOST_MULTIARCH ?= $(shell dpkg-architecture -qDEB_HOST_MULTIARCH) +DEB_HOST_GNU_TYPE ?= $(shell dpkg-architecture -qDEB_HOST_GNU_TYPE) +DEB_BUILD_GNU_TYPE ?= $(shell dpkg-architecture -qDEB_BUILD_GNU_TYPE) +DEB_HOST_ARCH ?= $(shell dpkg-architecture -qDEB_HOST_ARCH) +DEB_BUILD_ARCH ?= $(shell dpkg-architecture -qDEB_BUILD_ARCH) + +# +# Detect invocations of the form 'fakeroot debian/rules binary arch=armhf' +# within an x86'en schroot. This only gets you part of the way since the +# packaging phase fails, but you can at least compile the kernel quickly. +# +arch := $(DEB_HOST_ARCH) +CROSS_COMPILE ?= $(DEB_HOST_GNU_TYPE)- + +# +# Set consistent toolchain +# If a given kernel wants to change this, they can do so via their own +# $(DEBIAN)/rules.d/hooks.mk and $(DEBIAN)/rules.d/$(arch).mk files +# +export gcc?=gcc +export rustc?=rustc +export rustfmt?=rustfmt +export bindgen?=bindgen +GCC_BUILD_DEPENDS=\ $(gcc):native, $(gcc)-aarch64-linux-gnu [arm64] , $(gcc)-arm-linux-gnueabihf [armhf] , $(gcc)-powerpc64le-linux-gnu [ppc64el] , $(gcc)-riscv64-linux-gnu [riscv64] , $(gcc)-s390x-linux-gnu [s390x] , $(gcc)-x86-64-linux-gnu [amd64] , + +builddir := $(CURDIR)/debian/build +stampdir := $(CURDIR)/debian/stamps + +# +# The binary package name always starts with linux-image-$KVER-$ABI.$UPLOAD_NUM. There +# are places that you'll find linux-image hard coded, but I guess thats OK since the +# assumption that the binary package always starts with linux-image will never change. +# +bin_pkg_name_signed=linux-image-$(abi_release) +bin_pkg_name_unsigned=linux-image-unsigned-$(abi_release) +mods_pkg_name=linux-modules-$(abi_release) +bldinfo_pkg_name=linux-buildinfo-$(abi_release) +hdrs_pkg_name=linux-headers-$(abi_release) +rust_pkg_name=linux-lib-rust-$(abi_release) +indep_hdrs_pkg_name=$(DEB_SOURCE)-headers-$(abi_release) + +# +# Similarly with the linux-source package, you need not build it as a developer. Its +# somewhat I/O intensive and utterly useless. +# +do_source_package=true +do_source_package_content=true +ifeq ($(do_full_build),false) +do_source_package_content=false +endif + +# common headers normally is built as an indep package, but may be arch +do_common_headers_indep=true + +# build tools +ifneq ($(wildcard $(CURDIR)/tools),) + do_tools?=true +else + do_tools?=false +endif +bpftool_pkg_name=bpftool +perf_pkg_name=linux-perf +tools_pkg_name=$(DEB_SOURCE)-tools-$(abi_release) +tools_common_pkg_name=linux-tools-common +tools_flavour_pkg_name=linux-tools-$(abi_release) +cloud_pkg_name=$(DEB_SOURCE)-cloud-tools-$(abi_release) +cloud_common_pkg_name=linux-cloud-tools-common +cloud_flavour_pkg_name=linux-cloud-tools-$(abi_release) +hosttools_pkg_name=linux-tools-host + +# The general flavour specific image package. +do_flavour_image_package=true + +# The general flavour specific header package. +do_flavour_header_package=true + +# DTBs +do_dtbs=false + +# ZSTD compressed kernel modules +do_zstd_ko=true +ifeq ($(DEB_DISTRIBUTION),jammy) +do_zstd_ko= +endif + +# Support parallel= in DEB_BUILD_OPTIONS (see #209008) +# +# These 2 environment variables set the -j value of the kernel build. For example, +# CONCURRENCY_LEVEL=16 fakeroot $(DEBIAN)/rules binary-debs +# or +# DEB_BUILD_OPTIONS=parallel=16 fakeroot $(DEBIAN)/rules binary-debs +# +# The default is to use the number of CPUs. +# +COMMA=, +DEB_BUILD_OPTIONS_PARA = $(subst parallel=,,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS)))) +ifneq (,$(DEB_BUILD_OPTIONS_PARA)) + CONCURRENCY_LEVEL := $(DEB_BUILD_OPTIONS_PARA) +endif + +ifeq ($(CONCURRENCY_LEVEL),) + # Check the environment + CONCURRENCY_LEVEL := $(shell echo $$CONCURRENCY_LEVEL) + # No? Then build with the number of CPUs on the host. + ifeq ($(CONCURRENCY_LEVEL),) + CONCURRENCY_LEVEL := $(shell expr `getconf _NPROCESSORS_ONLN` \* 1) + endif + # Oh hell, give 'em one + ifeq ($(CONCURRENCY_LEVEL),) + CONCURRENCY_LEVEL := 1 + endif +endif + +conc_level = -j$(CONCURRENCY_LEVEL) + +PYTHON ?= $(firstword $(wildcard /usr/bin/python3) $(wildcard /usr/bin/python2) $(wildcard /usr/bin/python)) + +HOSTCC ?= $(DEB_BUILD_GNU_TYPE)-$(gcc) + +# $* is the flavour name which is filled in for each step +kmake = make ARCH=$(build_arch) \ + CROSS_COMPILE=$(CROSS_COMPILE) \ + HOSTCC=$(HOSTCC) \ + CC=$(CROSS_COMPILE)$(gcc) \ + RUSTC=$(rustc) \ + HOSTRUSTC=$(rustc) \ + RUSTFMT=$(rustfmt) \ + BINDGEN=$(bindgen) \ + KERNELRELEASE=$(abi_release)-$* \ + CONFIG_DEBUG_SECTION_MISMATCH=y \ + KBUILD_BUILD_VERSION="$(uploadnum)" \ + CFLAGS_MODULE="-DPKG_ABI=$(abinum)" \ + PYTHON=$(PYTHON) +ifneq ($(LOCAL_ENV_CC),) +kmake += CC="$(LOCAL_ENV_CC)" DISTCC_HOSTS="$(LOCAL_ENV_DISTCC_HOSTS)" +endif + +# Locking is required in parallel builds to prevent loss of contents +# of the debian/files. +lockme = flock -w 60 $(CURDIR)/debian/.LOCK + +# Don't fail if a link already exists. +LN = ln -sf + +# Checks if a var is overriden by the custom rules. Called with var and +# flavour as arguments. +custom_override = $(or $($(1)_$(2)),$($(1))) + +# selftests that Ubuntu cares about +ubuntu_selftests = breakpoints cpu-hotplug efivarfs memfd memory-hotplug mount net ptrace seccomp timers powerpc user ftrace + +# DKMS +all_dkms_modules = + +subst_paired = $(subst $(firstword $(subst =, ,$(1))),$(lastword $(subst =, ,$(1))),$(2)) +recursive_call = $(if $(2),$(call recursive_call,$(1),$(wordlist 2,$(words $(2)),$(2)),$(call $(1),$(firstword $(2)),$(3))),$(3)) + +$(foreach _line,$(shell gawk '{ OFS = "!"; $$1 = $$1; print }' $(DEBIAN)/dkms-versions), \ + $(eval _params = $(subst !, ,$(_line))) \ + $(eval _deb_pkgname = $(firstword $(_params))) \ + $(eval _deb_version = $(word 2,$(_params))) \ + $(if $(filter modulename=%,$(_params)), \ + $(eval _m = $(word 2,$(subst =, ,$(filter modulename=%,$(_params))))) \ + , \ + $(info modulename for $(_deb_pkgname) not specified in dkms-versions. Assume $(_deb_pkgname).) \ + $(eval _m = $(_deb_pkgname)) \ + ) \ + $(eval all_dkms_modules += $(_m)) \ + $(eval dkms_$(_m)_version = $(_deb_version)) \ + $(foreach _p,$(patsubst debpath=%,%,$(filter debpath=%,$(_params))), \ + $(eval dkms_$(_m)_debpath += $(strip \ + $(call recursive_call,subst_paired, \ + %module%=$(_m) \ + %package%=$(_deb_pkgname) \ + %version%=$(lastword $(subst :, ,$(_deb_version))) \ + , \ + $(_p) \ + ) \ + )) \ + ) \ + $(if $(dkms_$(_m)_debpath),,$(error debpath for $(_deb_pkgname) not specified.)) \ + $(if $(filter arch=%,$(_params)), \ + $(eval dkms_$(_m)_archs = $(patsubst arch=%,%,$(filter arch=%,$(_params)))) \ + , \ + $(eval dkms_$(_m)_archs = any) \ + ) \ + $(eval _rprovides_raw = $(filter rprovides=%,$(_params))) \ + $(eval dkms_$(_m)_rprovides = $(patsubst rprovides=%,%,$(_rprovides_raw))) \ + $(eval dkms_$(_m)_type = $(word 1,$(patsubst type=%,%,$(filter type=%,$(_params))) built-in)) \ + $(eval all_$(dkms_$(_m)_type)_dkms_modules += $(_m)) \ + $(if $(filter standalone,$(dkms_$(_m)_type)), \ + $(eval dkms_$(_m)_pkg_name = linux-modules-$(_m)-$(abi_release)) \ + $(eval dkms_$(_m)_subdir = ubuntu) \ + , \ + $(eval dkms_$(_m)_pkg_name = $(mods_pkg_name)) \ + $(eval dkms_$(_m)_subdir = kernel) \ + ) \ +) --- linux-nvidia-7.0.0.orig/debian/rules.d/1-maintainer.mk +++ linux-nvidia-7.0.0/debian/rules.d/1-maintainer.mk @@ -0,0 +1,134 @@ +# The following targets are for the maintainer only! do not run if you don't +# know what they do. + +.PHONY: help +help: + @echo "These are the targets in addition to the normal $(DEBIAN) ones:" + @echo + @echo " printenv : Print some variables used in the build" + @echo " updateconfigs : Update core arch configs" + @echo " defaultconfigs : Update core arch configs using defaults" + @echo " genconfigs : Generate core arch configs in CONFIGS/*" + @echo " editconfigs : Edit core arch configs" + @echo " printchanges : Print the current changelog entries (from git)" + @echo " insertchanges : Insert current changelog entries (from git)" + @echo " compileselftests : Only compile the selftests listed on ubuntu_selftests variable" + @echo " runselftests : Run the selftests listed on ubuntu_selftests variable" + @echo + @echo "Environment variables:" + @echo + @echo " CONCURRENCY_LEVEL=X : Use -jX for kernel compile" + +.PHONY: printdebian +printdebian: + @echo "$(DEBIAN)" + +configs-targets := updateconfigs defaultconfigs genconfigs editconfigs + +.PHONY: $(configs-targets) +$(configs-targets): + dh_testdir + kmake='$(kmake)' skip_checks=$(do_skip_checks) conc_level=$(conc_level) \ + $(SHELL) debian/scripts/misc/kernelconfig $@ + +.PHONY: printenv +printenv: + @dh_testdir + @echo "DEB_SOURCE = $(DEB_SOURCE)" + @echo "DEB_DISTRIBUTION = $(DEB_DISTRIBUTION)" + @echo "DEB_VERSION_UPSTREAM = $(DEB_VERSION_UPSTREAM)" + @echo "DEB_REVISION = $(DEB_REVISION)" + @echo "uploadnum = $(uploadnum)" + @echo "abinum = $(abinum)" + @echo "upstream_tag = $(upstream_tag)" + @echo "flavours = $(flavours)" + @echo "bin_pkg_name = $(bin_pkg_name)" + @echo "hdr_pkg_name = $(hdrs_pkg_name)" + @echo "rust_pkg_name = $(rust_pkg_name)" + @echo "ubuntu_selftests = $(ubuntu_selftests)" + @echo "arch = $(arch)" + @echo "kmake = $(kmake)" + @echo + @echo "CONCURRENCY_LEVEL = $(CONCURRENCY_LEVEL)" + @echo "DEB_HOST_GNU_TYPE = $(DEB_HOST_GNU_TYPE)" + @echo "DEB_BUILD_GNU_TYPE = $(DEB_BUILD_GNU_TYPE)" + @echo "DEB_HOST_ARCH = $(DEB_HOST_ARCH)" + @echo "DEB_BUILD_ARCH = $(DEB_BUILD_ARCH)" + @echo + @echo "any_signed = $(any_signed)" + @echo " uefi_signed = $(uefi_signed)" + @echo " opal_signed = $(opal_signed)" + @echo " sipl_signed = $(sipl_signed)" + @echo + @echo "do_skip_checks = $(do_skip_checks)" + @echo "do_full_build = $(do_full_build)" + @echo "do_mainline_build = $(do_mainline_build)" + @echo "do_dbgsym_package = $(do_dbgsym_package)" + @echo "do_dtbs = $(do_dtbs)" + @echo "do_source_package = $(do_source_package)" + @echo "do_source_package_content = $(do_source_package_content)" + @echo "do_flavour_image_package = $(do_flavour_image_package)" + @echo "do_flavour_header_package = $(do_flavour_header_package)" + @echo "do_common_headers_indep = $(do_common_headers_indep)" + @echo "do_lib_rust = $(do_lib_rust)" + @echo "do_tools = $(do_tools)" + @echo "do_tools_common = $(do_tools_common)" + @echo "do_any_tools = $(do_any_tools)" + @echo "do_linux_tools = $(do_linux_tools)" + @echo " do_tools_acpidbg = $(do_tools_acpidbg)" + @echo " do_tools_bpftool = $(do_tools_bpftool)" + @echo " do_tools_cpupower = $(do_tools_cpupower)" + @echo " do_tools_host = $(do_tools_host)" + @echo " do_tools_perf = $(do_tools_perf)" + @echo " do_tools_perf_jvmti = $(do_tools_perf_jvmti)" + @echo " do_tools_perf_python = $(do_tools_perf_python)" + @echo " do_tools_rtla = $(do_tools_rtla)" + @echo " do_tools_usbip = $(do_tools_usbip)" + @echo " do_tools_x86 = $(do_tools_x86)" + @echo "do_cloud_tools = $(do_cloud_tools)" + @echo " do_tools_hyperv = $(do_tools_hyperv)" + @echo + @echo "all_dkms_modules = $(all_dkms_modules)" + @$(foreach mod,$(all_dkms_modules),$(foreach var,$(do_$(mod)),\ + printf " %-24s = %s\n" "do_$(mod)" "$(var)";)) + +.PHONY: printchanges +printchanges: + @baseCommit=$$(git log --pretty=format:'%H %s' | \ + gawk '/UBUNTU: '".*Ubuntu-.*`echo $(DEB_VERSION_PREV) | sed 's/+/\\\\+/'`"'(~.*)?$$/ { print $$1; exit }'); \ + if [ -z "$$baseCommit" ]; then \ + echo "WARNING: couldn't find a commit for the previous version. Using the lastest one." >&2; \ + baseCommit=$$(git log --pretty=format:'%H %s' | \ + gawk '/UBUNTU:\s*Ubuntu-.*$$/ { print $$1; exit }'); \ + fi; \ + git log "$$baseCommit"..HEAD | \ + debian/scripts/misc/git-ubuntu-log + +.PHONY: insertchanges +insertchanges: autoreconstruct finalchecks + debian/scripts/misc/insert-changes debian $(DEBIAN) + +.PHONY: autoreconstruct +autoreconstruct: + # No need for reconstruct for -rc kernels since we don't upload an + # orig tarball, so just remove it. + if grep -q "^EXTRAVERSION = -rc[0-9]\+$$" Makefile; then \ + echo "exit 0" >$(DEBIAN)/reconstruct; \ + else \ + debian/scripts/misc/gen-auto-reconstruct $(upstream_tag) $(DEBIAN)/reconstruct debian/source/options; \ + fi + +.PHONY: finalchecks +finalchecks: debian/control + debian/scripts/checks/final-checks "$(DEBIAN)" "$(DEB_VERSION_PREV)" $(do_skip_checks) + +.PHONY: compileselftests +compileselftests: + # a loop is needed here to fail on errors + for test in $(ubuntu_selftests); do \ + $(kmake) -C tools/testing/selftests TARGETS="$$test"; \ + done; + +.PHONY: runselftests +runselftests: + $(kmake) -C tools/testing/selftests TARGETS="$(ubuntu_selftests)" run_tests --- linux-nvidia-7.0.0.orig/debian/rules.d/2-binary-arch.mk +++ linux-nvidia-7.0.0/debian/rules.d/2-binary-arch.mk @@ -0,0 +1,758 @@ +# We don't want make removing intermediary stamps +.SECONDARY : + +# Per-flavor variables (evaluated at runtime) +abi_dir = $(builddir)/abi-$* +build_dir = $(builddir)/build-$* + +# TODO this is probably wrong, and should be using $(DEB_HOST_MULTIARCH) +shlibdeps_opts = $(if $(CROSS_COMPILE),-- -l$(CROSS_COMPILE:%-=/usr/%)/lib) + +# These are used by binary-perarch target. +BPFTOOL_VERSION_MAJOR = $(shell sed -ne \ + 's,^#define LIBBPF_MAJOR_VERSION \(.*\)$$,\1,p' \ + tools/lib/bpf/libbpf_version.h) +BPFTOOL_VERSION_MINOR = $(shell sed -ne \ + 's,^#define LIBBPF_MINOR_VERSION \(.*\)$$,\1,p' \ + tools/lib/bpf/libbpf_version.h) +BPFTOOL_VERSION_PATCH = $(shell sed -ne \ + 's,^#define BPFTOOL_PATCH_VERSION \(.*\)$$,\1,p' \ + tools/bpf/bpftool/main.c) +BPFTOOL_VERSION = $(shell expr $(BPFTOOL_VERSION_MAJOR) + 6).$(BPFTOOL_VERSION_MINOR).$(BPFTOOL_VERSION_PATCH) +BPFTOOL_GENCONTROL_ARGS = -v$(BPFTOOL_VERSION)+$(DEB_VERSION) +ifneq ($(DEB_HOST_ARCH),$(DEB_BUILD_ARCH)) +# Use system bpftool when cross-building +BPFTOOL_PATH = /usr/sbin/bpftool +else +BPFTOOL_PATH = $(builddirpa)/tools/bpf/bpftool/bpftool +endif + +# Pick LLVM version from the build-depends +LLVM_VERSION = $(shell sed -n -r '/^Build/,/^$$/s/.*llvm-([0-9]+)-dev.*/\1/p' debian/control) + +debian/scripts/fix-filenames: debian/scripts/fix-filenames.c + $(HOSTCC) $^ -o $@ + +$(stampdir)/stamp-prepare-%: debian/scripts/fix-filenames + @echo Debug: $@ + install -d $(build_dir) + touch $(build_dir)/ubuntu-build + python3 debian/scripts/misc/annotations --export --arch $(arch) --flavour $* > $(build_dir)/.config + sed -i 's/.*CONFIG_VERSION_SIGNATURE.*/CONFIG_VERSION_SIGNATURE="Ubuntu $(DEB_VERSION_UPSTREAM)-$(DEB_REVISION)-$* $(raw_kernelversion)"/' $(build_dir)/.config + find $(build_dir) -name "*.ko" | xargs rm -f + $(kmake) O=$(build_dir) $(conc_level) rustavailable || true + $(kmake) O=$(build_dir) $(conc_level) olddefconfig +ifneq ($(do_skip_checks),true) + python3 debian/scripts/misc/annotations -f $(CURDIR)/$(DEBIAN)/config/annotations \ + --arch $(arch) --flavour $* --check $(build_dir)/.config +endif + $(stamp) + +# Used by developers as a shortcut to prepare a tree for compilation. +prepare-%: $(stampdir)/stamp-prepare-% + @echo Debug: $@ +# Used by developers to allow efficient pre-building without fakeroot. +build-%: $(stampdir)/stamp-install-% + @echo Debug: $@ + +# Do the actual build, including image and modules +$(stampdir)/stamp-build-%: bldimg = $(call custom_override,build_image,$*) +$(stampdir)/stamp-build-%: $(stampdir)/stamp-build-perarch $(stampdir)/stamp-prepare-% + @echo Debug: $@ build_image $(build_image) bldimg $(bldimg) + $(kmake) O=$(build_dir) $(conc_level) $(bldimg) modules $(if $(filter true,$(do_dtbs)),dtbs) + +ifeq ($(do_dbgsym_package),true) + # The target scripts_gdb is part of "all", so we need to call it manually + if grep -q CONFIG_GDB_SCRIPTS=y $(build_dir)/.config; then \ + $(kmake) O=$(build_dir) $(conc_level) scripts_gdb ; \ + fi +endif + +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifeq ($(do_tools_bpftool_stub),true) + echo '#error "Kernel does not support CONFIG_DEBUG_INFO_BTF"' > $(build_dir)/vmlinux.h + else + $(BPFTOOL_PATH) btf dump file $(build_dir)/vmlinux format c > $(build_dir)/vmlinux.h + endif + endif +endif + $(stamp) + +define build_dkms_sign = + $(shell set -x; if grep -q CONFIG_MODULE_SIG=y $(1)/.config; then + echo $(1)/scripts/sign-file $(MODHASHALGO) $(MODSECKEY) $(MODPUBKEY); + else + echo "-"; + fi + ) +endef +define build_dkms = + rc=0; unset MAKEFLAGS; ARCH=$(build_arch) CROSS_COMPILE=$(CROSS_COMPILE) $(SHELL) debian/scripts/dkms-build $(dkms_dir) $(abi_release)-$* '$(call build_dkms_sign,$(build_dir))' $(1) $(2) $(3) $(4) $(5) || rc=$$?; if [ "$$rc" = "9" -o "$$rc" = "77" ]; then echo do_$(4)_$*=false >> $(builddir)/skipped-dkms.mk; rc=0; fi; if [ "$$rc" != "0" ]; then exit $$rc; fi +endef + +define install_control = + for which in $(3); \ + do \ + template="debian/templates/$(2).$$which.in"; \ + script="debian/$(1).$$which"; \ + sed -e 's/@abiname@/$(abi_release)/g' \ + -e 's/@localversion@/-$*/g' \ + -e 's/@image-stem@/$(instfile)/g' \ + <"$$template" >"$$script"; \ + done +endef + +# Ensure the directory prefix is exactly 140 characters long so pathnames are the +# exact same length in any binary files produced by the builds. These will be +# commonised later. +dkms_20d=.................... +dkms_140d=$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d)$(dkms_20d) +dkms_140c=$(shell echo '$(dkms_140d)' | sed -e 's/\./_/g') +define dkms_dir_prefix = +$(shell echo $(1)/$(dkms_140c) | \ + sed -e 's/\($(dkms_140d)\).*/\1/' -e 's/^\(.*\)....$$/\1dkms/') +endef + +# Install the finished build +$(stampdir)/stamp-install-%: pkgdir_bin = $(CURDIR)/debian/$(bin_pkg_name)-$* +$(stampdir)/stamp-install-%: pkgdir = $(CURDIR)/debian/$(mods_pkg_name)-$* +$(stampdir)/stamp-install-%: pkgdir_bldinfo = $(CURDIR)/debian/$(bldinfo_pkg_name)-$* +$(stampdir)/stamp-install-%: bindoc = $(pkgdir)/usr/share/doc/$(bin_pkg_name)-$* +$(stampdir)/stamp-install-%: dbgpkgdir = $(CURDIR)/debian/$(bin_pkg_name)-$*-dbgsym +$(stampdir)/stamp-install-%: signingv = $(CURDIR)/debian/$(bin_pkg_name)-signing/$(DEB_VERSION_UPSTREAM)-$(DEB_REVISION) +$(stampdir)/stamp-install-%: toolspkgdir = $(CURDIR)/debian/$(tools_flavour_pkg_name)-$* +$(stampdir)/stamp-install-%: cloudpkgdir = $(CURDIR)/debian/$(cloud_flavour_pkg_name)-$* +$(stampdir)/stamp-install-%: bpfdevpkgdir = $(CURDIR)/debian/linux-bpf-dev +$(stampdir)/stamp-install-%: bpftoolpkgdir = $(CURDIR)/debian/$(bpftool_pkg_name) +$(stampdir)/stamp-install-%: perfpkgdir = $(CURDIR)/debian/$(perf_pkg_name) +$(stampdir)/stamp-install-%: basepkg = $(hdrs_pkg_name) +$(stampdir)/stamp-install-%: baserustpkg = $(rust_pkg_name) +$(stampdir)/stamp-install-%: indeppkg = $(indep_hdrs_pkg_name) +$(stampdir)/stamp-install-%: kernfile = $(call custom_override,kernel_file,$*) +$(stampdir)/stamp-install-%: instfile = $(call custom_override,install_file,$*) +$(stampdir)/stamp-install-%: hdrdir = $(CURDIR)/debian/$(basepkg)-$*/usr/src/$(basepkg)-$* +$(stampdir)/stamp-install-%: rustdir = $(CURDIR)/debian/$(baserustpkg)-$*/usr/src/$(baserustpkg)-$* +$(stampdir)/stamp-install-%: MODHASHALGO=sha512 +$(stampdir)/stamp-install-%: MODSECKEY=$(build_dir)/certs/signing_key.pem +$(stampdir)/stamp-install-%: MODPUBKEY=$(build_dir)/certs/signing_key.x509 +$(stampdir)/stamp-install-%: dkms_dir=$(call dkms_dir_prefix,$(build_dir)) +$(foreach _m,$(all_dkms_modules), \ + $(eval $$(stampdir)/stamp-install-%: enable_$(_m) = $$(filter true,$$(call custom_override,do_$(_m),$$*))) \ + $(eval $$(stampdir)/stamp-install-%: dkms_$(_m)_pkgdir = $$(CURDIR)/debian/$(dkms_$(_m)_pkg_name)-$$*) \ +) +$(stampdir)/stamp-install-%: dbgpkgdir_dkms = $(if $(filter true,$(do_dbgsym_package)),$(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/kernel,"") +$(stampdir)/stamp-install-%: $(stampdir)/stamp-install-headers $(stampdir)/stamp-build-% + @echo Debug: $@ kernel_file $(kernel_file) kernfile $(kernfile) install_file $(install_file) instfile $(instfile) + dh_testdir + dh_prep -p$(bin_pkg_name)-$* + dh_prep -p$(mods_pkg_name)-$* + dh_prep -p$(hdrs_pkg_name)-$* +ifeq ($(do_lib_rust),true) + dh_prep -p$(rust_pkg_name)-$* +endif + $(foreach _m,$(all_standalone_dkms_modules), \ + $(if $(enable_$(_m)),dh_prep -p$(dkms_$(_m)_pkg_name)-$*;)\ + ) +ifeq ($(do_dbgsym_package),true) + dh_prep -p$(bin_pkg_name)-$*-dbgsym +endif +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter linux-bpf-dev,$(packages_enabled)),) + # Do this only for the primary (first) flavor + # linux-bpf-dev is broken: It provides vmlinux.h which is a flavored header file! + if [ $* = $(firstword $(flavours)) ] ; then \ + dh_prep -plinux-bpf-dev ; \ + fi + endif + endif +endif + + # The main image + install -m600 -D $(build_dir)/$(kernfile) \ + $(pkgdir_bin)/boot/$(instfile)-$(abi_release)-$* + install -d $(pkgdir)/boot + install -m644 $(build_dir)/.config \ + $(pkgdir)/boot/config-$(abi_release)-$* + install -m600 $(build_dir)/System.map \ + $(pkgdir)/boot/System.map-$(abi_release)-$* + +ifeq ($(do_dtbs),true) + $(kmake) O=$(build_dir) $(conc_level) dtbs_install \ + INSTALL_DTBS_PATH=$(pkgdir)/usr/lib/firmware/$(abi_release)-$*/device-tree +endif + +ifeq ($(no_dumpfile),) + makedumpfile -g $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* \ + -x $(build_dir)/vmlinux + chmod 0600 $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* +endif + + $(kmake) O=$(build_dir) $(conc_level) modules_install $(vdso) \ + INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=$(pkgdir)/usr + + # + # Build module blacklists: + # - blacklist all watchdog drivers (LP:1432837) + # + install -d $(pkgdir)/usr/lib/modprobe.d + echo "# Kernel supplied blacklist for $(DEB_SOURCE) $(abi_release)-$* $(arch)" \ + >$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + for conf in $(arch)-$* $(arch) common.conf; do \ + if [ -f $(DEBIAN)/modprobe.d/$$conf ]; then \ + echo "# modprobe.d/$$conf"; \ + cat $(DEBIAN)/modprobe.d/$$conf; \ + fi; \ + done >>$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + echo "# Autogenerated watchdog blacklist" \ + >>$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + ls -1 $(pkgdir)/usr/lib/modules/$(abi_release)-$*/kernel/drivers/watchdog/ | \ + grep -v '^bcm2835_wdt.ko$$' | \ + grep -v '^sbsa_gwdt.ko$$' | \ + sed -e 's/^/blacklist /' -e 's/.ko$$//' | \ + sort -u \ + >>$(pkgdir)/usr/lib/modprobe.d/blacklist_$(DEB_SOURCE)_$(abi_release)-$*.conf + +ifeq ($(no_dumpfile),) + makedumpfile -g $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* \ + -x $(build_dir)/vmlinux + chmod 0600 $(pkgdir)/boot/vmcoreinfo-$(abi_release)-$* +endif + rm -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/build + rm -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/source + + # Some initramfs-tools specific modules + install -d $(pkgdir)/usr/lib/modules/$(abi_release)-$*/initrd + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/kernel/drivers/video/vesafb.ko ]; then\ + $(LN) $(pkgdir)/usr/lib/modules/$(abi_release)-$*/kernel/drivers/video/vesafb.ko \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/initrd/; \ + fi + + echo "interest linux-update-$(abi_release)-$*" >"debian/$(bin_pkg_name)-$*.triggers" + install -d $(pkgdir_bin)/usr/lib/linux/triggers + $(call install_control,$(bin_pkg_name)-$*,image,postinst postrm preinst prerm) + install -d $(pkgdir)/usr/lib/linux/triggers + $(call install_control,$(mods_pkg_name)-$*,extra,postinst postrm) + $(foreach _m,$(all_standalone_dkms_modules), \ + $(if $(enable_$(_m)), \ + install -d $(dkms_$(_m)_pkgdir)/usr/lib/linux/triggers; \ + $(call install_control,$(dkms_$(_m)_pkg_name)-$*,extra,postinst postrm); \ + ) \ + ) + +ifeq ($(do_dbgsym_package),true) + # Debug image is simple + install -m644 -D $(build_dir)/vmlinux \ + $(dbgpkgdir)/usr/lib/debug/boot/vmlinux-$(abi_release)-$* + if [ -d $(build_dir)/scripts/gdb/linux ]; then \ + install -m644 -D $(build_dir)/vmlinux-gdb.py \ + $(dbgpkgdir)/usr/share/gdb/auto-load/boot/vmlinux-$(abi_release)-$*/vmlinuz-$(abi_release)-$*-gdb.py; \ + fi + $(kmake) O=$(build_dir) modules_install $(vdso) \ + INSTALL_MOD_PATH=$(dbgpkgdir)/usr/lib/debug + # Add .gnu_debuglink sections only after all/DKMS modules are built. + rm -f $(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/build + rm -f $(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/source + rm -f $(dbgpkgdir)/usr/lib/debug/usr/lib/modules/$(abi_release)-$*/modules.* + rm -fr $(dbgpkgdir)/usr/lib/debug/lib/firmware +endif + + # The flavour specific headers image + # TODO: Would be nice if we didn't have to dupe the original builddir + install -d -m755 $(hdrdir) + cp $(build_dir)/.config $(hdrdir) + chmod 644 $(hdrdir)/.config + $(kmake) O=$(hdrdir) -j1 syncconfig prepare scripts + # Makefile may need per-arch-flavour CC settings, which are + # normally set via $(kmake) during build + rm -f $(hdrdir)/Makefile + cp -a $(indep_hdrdir)/Makefile $(hdrdir)/Makefile + sed -i 's|\(^HOSTCC = \)gcc$$|\1$(gcc)|' $(hdrdir)/Makefile + sed -i 's|\(^CC = $$(CROSS_COMPILE)\)gcc$$|\1$(gcc)|' $(hdrdir)/Makefile + # Quick check for successful substitutions + grep '^HOSTCC .*$(gcc)$$' $(hdrdir)/Makefile + grep '^CC .*$(gcc)$$' $(hdrdir)/Makefile + rm -rf $(hdrdir)/include2 $(hdrdir)/source + # Copy over the compilation version. + cp "$(build_dir)/include/generated/compile.h" \ + "$(hdrdir)/include/generated/compile.h" + # Add UTS_UBUNTU_RELEASE_ABI since UTS_RELEASE is difficult to parse. + echo "#define UTS_UBUNTU_RELEASE_ABI $(abinum)" >> $(hdrdir)/include/generated/utsrelease.h + # powerpc kernel arch seems to need some .o files for external module linking. Add them in. +ifeq ($(build_arch),powerpc) + mkdir -p $(hdrdir)/arch/powerpc/lib + cp $(build_dir)/arch/powerpc/lib/*.o $(hdrdir)/arch/powerpc/lib +endif +ifeq ($(build_arch),s390) + if [ -n "$$(find $(build_dir)/arch/s390/lib/expoline -maxdepth 1 -name '*.o' -print -quit)" ]; then \ + mkdir -p $(hdrdir)/arch/s390/lib/expoline/; \ + cp $(build_dir)/arch/s390/lib/expoline/*.o $(hdrdir)/arch/s390/lib/expoline/; \ + fi +endif + # Copy over scripts/module.lds for building external modules + cp $(build_dir)/scripts/module.lds $(hdrdir)/scripts + # Script to symlink everything up + $(SHELL) debian/scripts/link-headers "$(hdrdir)" "$(indeppkg)" "$*" + # The build symlink + install -d debian/$(basepkg)-$*/usr/lib/modules/$(abi_release)-$* + $(LN) /usr/src/$(basepkg)-$* \ + debian/$(basepkg)-$*/usr/lib/modules/$(abi_release)-$*/build + # And finally the symvers + install -m644 $(build_dir)/Module.symvers \ + $(hdrdir)/Module.symvers + + # Now the header scripts + $(call install_control,$(hdrs_pkg_name)-$*,headers,postinst) + + # At the end of the package prep, run the module signature check + debian/scripts/checks/module-signature-check "$*" "$(pkgdir)" $(do_skip_checks) + + # + # Remove files which are generated at installation by postinst, + # except for modules.order and modules.builtin + # + # NOTE: need to keep this list in sync with postrm + # + mkdir $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_ + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.order \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_ + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin ] ; then \ + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_; \ + fi + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo ] ; then \ + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_; \ + fi + rm -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.* + mv $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_/* \ + $(pkgdir)/usr/lib/modules/$(abi_release)-$* + rmdir $(pkgdir)/usr/lib/modules/$(abi_release)-$*/_ + +ifeq ($(do_linux_tools),true) + # Create the linux-tools tool link + install -d $(toolspkgdir)/usr/lib/linux-tools + $(LN) ../$(DEB_SOURCE)-tools-$(abi_release) $(toolspkgdir)/usr/lib/linux-tools/$(abi_release)-$* + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter linux-bpf-dev,$(packages_enabled)),) + # Do this only for the primary (first) flavor + # linux-bpf-dev is broken: It provides vmlinux.h which is a flavored header file! + if [ $* = $(firstword $(flavours)) ] ; then \ + install -d -m755 $(bpfdevpkgdir)/usr/include/$(DEB_HOST_MULTIARCH)/linux/bpf/ ; \ + install -m644 $(build_dir)/vmlinux.h \ + $(bpfdevpkgdir)/usr/include/$(DEB_HOST_MULTIARCH)/linux/bpf/ ; \ + fi + endif + endif +endif + +ifeq ($(do_cloud_tools),true) + ifeq ($(do_tools_hyperv),true) + # Create the linux-hyperv tool link + install -d $(cloudpkgdir)/usr/lib/linux-tools + $(LN) ../$(DEB_SOURCE)-tools-$(abi_release) $(cloudpkgdir)/usr/lib/linux-tools/$(abi_release)-$* + endif +endif + + # Build a temporary "installed headers" directory. + install -d $(dkms_dir) $(dkms_dir)/headers $(dkms_dir)/build $(dkms_dir)/source + cp -rp "$(hdrdir)" "$(indep_hdrdir)" "$(dkms_dir)/headers" + + $(foreach _m,$(all_dkms_modules), \ + $(if $(enable_$(_m)), \ + $(call build_dkms,$(dkms_$(_m)_pkg_name)-$*,$(dkms_$(_m)_pkgdir)/usr/lib/modules/$(abi_release)-$*/$(dkms_$(_m)_subdir),$(dbgpkgdir_dkms),$(_m),$(dkms_$(_m)_debpath)); \ + ) \ + ) + + +ifeq ($(do_dbgsym_package),true) + # Add .gnu_debuglink sections to each stripped .ko + # pointing to unstripped verson + find $(pkgdir) \ + -name '*.ko' | while read path_module ; do \ + module="/usr/lib/modules/$${path_module#*/usr/lib/modules/}"; \ + if [[ -f "$(dbgpkgdir)/usr/lib/debug/$$module" ]] ; then \ + while IFS= read -r -d '' signature < <(tail -c 28 "$$path_module"); do \ + break; \ + done; \ + $(CROSS_COMPILE)objcopy \ + --add-gnu-debuglink=$(dbgpkgdir)/usr/lib/debug/$$module \ + $$path_module; \ + if grep -q CONFIG_MODULE_SIG=y $(build_dir)/.config && \ + [ "$$signature" = $$'~Module signature appended~\n' ]; then \ + $(build_dir)/scripts/sign-file $(MODHASHALGO) \ + $(MODSECKEY) \ + $(MODPUBKEY) \ + $$path_module; \ + fi; \ + else \ + echo "WARNING: Missing debug symbols for module '$$module'."; \ + fi; \ + done +endif + + # Build the final ABI information. + install -d $(abi_dir) + sed -e 's/^\(.\+\)[[:space:]]\+\(.\+\)[[:space:]]\(.\+\)$$/\3 \2 \1/' \ + $(build_dir)/Module.symvers | sort > $(abi_dir)/$* + + # Build the final ABI modules information. + find $(pkgdir_bin) $(pkgdir) \( -name '*.ko' -o -name '*.ko.*' \) | \ + sed -e 's/.*\/\([^\/]*\)\.ko.*/\1/' | sort > $(abi_dir)/$*.modules + + # Build the final ABI built-in modules information. + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin ] ; then \ + sed -e 's/.*\/\([^\/]*\)\.ko/\1/' $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin | \ + sort > $(abi_dir)/$*.modules.builtin; \ + fi + + # Build the final ABI firmware information. + find $(pkgdir_bin) $(pkgdir) -name \*.ko | \ + while read ko; do \ + /sbin/modinfo $$ko | grep ^firmware || true; \ + done | sort -u >$(abi_dir)/$*.fwinfo + + # Build the final ABI built-in firmware information. + if [ -f $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo ] ; then \ + cat $(pkgdir)/usr/lib/modules/$(abi_release)-$*/modules.builtin.modinfo | \ + tr '\0' '\n' | sed -n 's/^.*firmware=/firmware: /p' | \ + sort -u > $(abi_dir)/$*.fwinfo.builtin; \ + fi + + # Build the final ABI compiler information. + ko=$$(find $(pkgdir_bin) $(pkgdir) -name \*.ko | head -1); \ + readelf -p .comment "$$ko" | gawk ' \ + ($$1 == "[") { \ + printf("%s", $$3); \ + for (n=4; n<=NF; n++) { \ + printf(" %s", $$n); \ + } \ + print "" \ + }' | sort -u >$(abi_dir)/$*.compiler + + # Build the buildinfo package content. + install -d $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$* + install -m644 $(build_dir)/.config \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/config + install -m644 $(abi_dir)/$* \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/abi + install -m644 $(abi_dir)/$*.modules \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/modules + install -m644 $(abi_dir)/$*.fwinfo \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/fwinfo + install -m644 $(abi_dir)/$*.compiler \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/compiler + if [ -f $(abi_dir)/$*.modules.builtin ] ; then \ + install -m644 $(abi_dir)/$*.modules.builtin \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/modules.builtin; \ + fi + if [ -f $(abi_dir)/$*.fwinfo.builtin ] ; then \ + install -m644 $(abi_dir)/$*.fwinfo.builtin \ + $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/fwinfo.builtin; \ + fi + install -m644 debian/canonical-certs.pem $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/canonical-certs.pem + install -m644 debian/canonical-revoked-certs.pem $(pkgdir_bldinfo)/usr/lib/linux/$(abi_release)-$*/canonical-revoked-certs.pem + + # Get rid of .o and .cmd artifacts in headers + find $(hdrdir) -name \*.o -or -name \*.cmd -exec rm -f {} \; + # Strip .so files (e.g., rust/libmacros.so) to reduce size even more + find $(hdrdir) -name libmacros.so -exec strip -s {} \; + +ifeq ($(do_lib_rust),true) + # Generate Rust lib files + install -d -m755 $(rustdir) + mv $(hdrdir)/rust $(rustdir) + # Generate symlink for Rust lib directory in headers + $(SHELL) debian/scripts/link-lib-rust "$(hdrdir)" "$(indeppkg)" "$*" +endif + +ifneq ($(do_full_build),false) + # Clean out this flavours build directory. + rm -rf $(build_dir) + rm -rf $(abi_dir) +endif + $(stamp) + +headers_dir := $(CURDIR)/debian/linux-libc-dev + +$(stampdir)/stamp-install-arch-headers: headers_tmp = $(CURDIR)/debian/tmp-headers +$(stampdir)/stamp-install-arch-headers: + @echo Debug: $@ + dh_testdir + dh_testroot + $(call if_package, linux-libc-dev, dh_prep -plinux-libc-dev) + rm -rf $(headers_tmp) $(headers_dir) + $(kmake) O=$(headers_tmp) INSTALL_HDR_PATH=$(headers_dir)/usr $(conc_level) headers_install + mkdir $(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH) + mv $(headers_dir)/usr/include/asm $(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH)/ + rm -rf $(headers_tmp) + $(stamp) + +define dh_all + dh_installchangelogs -p$(1) + dh_installdocs -p$(1) + dh_compress -p$(1) + # Compress kernel modules, on mantic+ + $(if $(do_zstd_ko),find debian/$(1) -name '*.ko' -print0 | xargs -0 -n1 -P $(CONCURRENCY_LEVEL) -r zstd -19 --quiet --rm, true) + dh_fixperms -p$(1) -X/boot/ + dh_shlibdeps -p$(1) $(shlibdeps_opts) + dh_installdeb -p$(1) + dh_installdebconf -p$(1) + $(lockme) dh_gencontrol -p$(1) -- -Tdebian/substvars $(2) + dh_md5sums -p$(1) + dh_builddeb -p$(1) +endef +define newline + + +endef +define dh_all_inline + $(subst ${newline},; \${newline},$(call dh_all,$(1),$(2))) +endef + +.PHONY: binary-arch-headers +binary-arch-headers: $(stampdir)/stamp-install-arch-headers + @echo Debug: $@ + dh_testdir + dh_testroot + $(call if_package, linux-libc-dev, $(call dh_all,linux-libc-dev)) + +-include $(builddir)/skipped-dkms.mk +binary-%: pkgimg = $(bin_pkg_name)-$* +binary-%: pkgimg_mods = $(mods_pkg_name)-$* +binary-%: pkgbldinfo = $(bldinfo_pkg_name)-$* +binary-%: pkghdr = $(hdrs_pkg_name)-$* +binary-%: pkgrust = $(rust_pkg_name)-$* +binary-%: dbgpkg = $(bin_pkg_name)-$*-dbgsym +binary-%: dbgpkgdir = $(CURDIR)/debian/$(bin_pkg_name)-$*-dbgsym +binary-%: pkgtools = $(tools_flavour_pkg_name)-$* +binary-%: pkgcloud = $(cloud_flavour_pkg_name)-$* +$(foreach _m,$(all_dkms_modules), \ + $(eval binary-%: enable_$(_m) = $$(filter true,$$(call custom_override,do_$(_m),$$*))) \ +) +binary-%: $(stampdir)/stamp-install-% + @echo Debug: $@ + dh_testdir + dh_testroot + + $(call dh_all,$(pkgimg)) -- -Znone + $(call dh_all,$(pkgimg_mods))$(if $(do_zstd_ko), -- -Znone) + + $(foreach _m,$(all_standalone_dkms_modules), \ + $(if $(enable_$(_m)),$(call dh_all,$(dkms_$(_m)_pkg_name)-$*)$(if $(do_zstd_ko), -- -Znone);)\ + ) + + $(call dh_all,$(pkgbldinfo)) + $(call dh_all,$(pkghdr)) +ifeq ($(do_lib_rust),true) + $(call dh_all,$(pkgrust)) +endif + +ifeq ($(do_dbgsym_package),true) + $(call dh_all,$(dbgpkg)) -- -Zxz + + # Hokay...here's where we do a little twiddling... + # Renaming the debug package prevents it from getting into + # the primary archive, and therefore prevents this very large + # package from being mirrored. It is instead, through some + # archive admin hackery, copied to http://ddebs.ubuntu.com. + # + mv ../$(dbgpkg)_$(DEB_VERSION_UPSTREAM)-$(DEB_REVISION)_$(arch).deb \ + ../$(dbgpkg)_$(DEB_VERSION_UPSTREAM)-$(DEB_REVISION)_$(arch).ddeb + $(lockme) sed -i '/^$(dbgpkg)_/s/\.deb /.ddeb /' debian/files + # Now, the package wont get into the archive, but it will get put + # into the debug system. + + # Clean out the debugging package source directory. + rm -rf $(dbgpkgdir) +endif + +ifeq ($(do_linux_tools),true) + $(call dh_all,$(pkgtools)) +endif +ifeq ($(do_cloud_tools),true) + $(call dh_all,$(pkgcloud)) +endif +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter linux-bpf-dev,$(packages_enabled)),) + # Do this only for the primary (first) flavor + # linux-bpf-dev is broken: It provides vmlinux.h which is a flavored header file! + if [ $* = $(firstword $(flavours)) ] ; then \ + $(call dh_all_inline,linux-bpf-dev) ; \ + fi + endif + endif +endif + +# +# per-architecture packages +# +builddirpa = $(builddir)/tools-perarch + +$(stampdir)/stamp-prepare-perarch: + @echo Debug: $@ +ifeq ($(do_any_tools),true) + rm -rf $(builddirpa) + install -d $(builddirpa) + rsync -a --exclude debian --exclude debian.master --exclude $(DEBIAN) --exclude .git -a ./ $(builddirpa)/ +endif + $(stamp) + +$(stampdir)/stamp-build-perarch: $(stampdir)/stamp-install-arch-headers $(stampdir)/stamp-prepare-perarch + @echo Debug: $@ +ifeq ($(do_linux_tools),true) +ifeq ($(do_tools_usbip),true) + chmod 755 $(builddirpa)/tools/usb/usbip/autogen.sh + cd $(builddirpa)/tools/usb/usbip && ./autogen.sh + chmod 755 $(builddirpa)/tools/usb/usbip/configure + cd $(builddirpa)/tools/usb/usbip && ./configure --host=$(DEB_HOST_GNU_TYPE) --prefix=$(builddirpa)/tools/usb/usbip/bin + cd $(builddirpa)/tools/usb/usbip && make install CFLAGS="-g -O2 -static" CROSS_COMPILE=$(CROSS_COMPILE) +endif +ifeq ($(do_tools_acpidbg),true) + cd $(builddirpa)/tools/power/acpi && make clean && make CFLAGS="-g -O2 -static -I$(builddirpa)/include" CROSS_COMPILE=$(CROSS_COMPILE) acpidbg +endif +ifeq ($(do_tools_rtla),true) + cd $(builddirpa) && $(kmake) -C tools/tracing/rtla clean && $(kmake) LD=$(CROSS_COMPILE)ld HOSTLD=ld -C tools/tracing/rtla static +endif +ifeq ($(do_tools_cpupower),true) + make -C $(builddirpa)/tools/power/cpupower \ + CROSS_COMPILE=$(CROSS_COMPILE) \ + CROSS=$(CROSS_COMPILE) \ + STATIC=true \ + CPUFREQ_BENCH=false +endif +ifeq ($(do_tools_perf),true) + cd $(builddirpa)/tools/perf && \ + LLVM_CONFIG=llvm-config-$(LLVM_VERSION) $(kmake) prefix=/usr HAVE_CPLUS_DEMANGLE_SUPPORT=1 CROSS_COMPILE=$(CROSS_COMPILE) NO_LIBPERL=1 WERROR=0 $(if $(filter arm64,$(build_arch)),CORESIGHT=1) +endif +ifeq ($(do_tools_bpftool),true) + $(kmake) CROSS_COMPILE=$(CROSS_COMPILE) -C $(builddirpa)/tools/bpf/bpftool +endif +ifeq ($(do_tools_x86),true) + cd $(builddirpa)/tools/power/x86/x86_energy_perf_policy && make CROSS_COMPILE=$(CROSS_COMPILE) + cd $(builddirpa)/tools/power/x86/turbostat && make CROSS_COMPILE=$(CROSS_COMPILE) + cd $(builddirpa)/tools/power/x86/intel-speed-select && make CROSS_COMPILE=$(CROSS_COMPILE) +endif +endif +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + cd $(builddirpa)/tools/hv && make CFLAGS="-I$(headers_dir)/usr/include -I$(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH)" CROSS_COMPILE=$(CROSS_COMPILE) hv_kvp_daemon hv_vss_daemon +ifneq ($(build_arch),arm64) + cd $(builddirpa)/tools/hv && make CFLAGS="-I$(headers_dir)/usr/include -I$(headers_dir)/usr/include/$(DEB_HOST_MULTIARCH)" CROSS_COMPILE=$(CROSS_COMPILE) hv_fcopy_uio_daemon +endif +endif +endif + $(stamp) + +.PHONY: install-perarch +install-perarch: toolspkgdir = $(CURDIR)/debian/$(tools_pkg_name) +install-perarch: cloudpkgdir = $(CURDIR)/debian/$(cloud_pkg_name) +install-perarch: bpftoolpkgdir = $(CURDIR)/debian/$(bpftool_pkg_name) +install-perarch: perfpkgdir = $(CURDIR)/debian/$(perf_pkg_name) +install-perarch: $(stampdir)/stamp-build-perarch + @echo Debug: $@ + # Add the tools. +ifeq ($(do_linux_tools),true) + install -d $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +ifeq ($(do_tools_usbip),true) + install -m755 $(addprefix $(builddirpa)/tools/usb/usbip/bin/sbin/, usbip usbipd) \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +ifeq ($(do_tools_acpidbg),true) + install -m755 $(builddirpa)/tools/power/acpi/acpidbg \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +ifeq ($(do_tools_cpupower),true) + install -m755 $(builddirpa)/tools/power/cpupower/cpupower \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +ifeq ($(do_tools_rtla),true) + install -m755 $(builddirpa)/tools/tracing/rtla/rtla-static \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release)/rtla +endif +ifeq ($(do_tools_perf),true) + install -d $(perfpkgdir)/usr/bin + install -m755 $(builddirpa)/tools/perf/perf \ + $(perfpkgdir)/usr/bin/perf +ifeq ($(do_tools_perf_jvmti),true) + install -d $(perfpkgdir)/usr/lib + install -m644 $(builddirpa)/tools/perf/libperf-jvmti.so \ + $(perfpkgdir)/usr/lib/ +endif +ifeq ($(do_tools_perf_python),true) + install -d $(perfpkgdir)/usr/lib/python3/dist-packages + install -m644 $(builddirpa)/tools/perf/python/perf.*.so \ + $(perfpkgdir)/usr/lib/python3/dist-packages/ +endif +endif # do_tools_perf +ifeq ($(do_tools_bpftool),true) + install -d $(bpftoolpkgdir)/usr/sbin + install -m755 $(builddirpa)/tools/bpf/bpftool/bpftool \ + $(bpftoolpkgdir)/usr/sbin/bpftool +endif +ifeq ($(do_tools_x86),true) + install -m755 $(addprefix $(builddirpa)/tools/power/x86/, x86_energy_perf_policy/x86_energy_perf_policy turbostat/turbostat intel-speed-select/intel-speed-select) \ + $(toolspkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +endif # do_linux_tools +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + install -d $(cloudpkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) + install -m755 $(addprefix $(builddirpa)/tools/hv/, hv_kvp_daemon hv_vss_daemon lsvmbus) \ + $(cloudpkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +ifneq ($(build_arch),arm64) + install -m755 $(addprefix $(builddirpa)/tools/hv/, hv_fcopy_uio_daemon) \ + $(cloudpkgdir)/usr/lib/$(DEB_SOURCE)-tools-$(abi_release) +endif +endif # do_tools_hyperv +endif # do_cloud_tools + +.PHONY: binary-perarch +binary-perarch: toolspkg = $(tools_pkg_name) +binary-perarch: cloudpkg = $(cloud_pkg_name) +binary-perarch: bpftoolpkg = $(bpftool_pkg_name) +binary-perarch: perfpkg = $(perf_pkg_name) +binary-perarch: install-perarch + @echo Debug: $@ +ifeq ($(do_linux_tools),true) + $(call dh_all,$(toolspkg)) +endif +ifeq ($(do_cloud_tools),true) + $(call dh_all,$(cloudpkg)) +endif +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + ifneq ($(filter $(bpftool_pkg_name),$(packages_enabled)),) + $(call dh_all_inline,$(bpftoolpkg),$(BPFTOOL_GENCONTROL_ARGS)) + endif + endif + ifeq ($(do_tools_perf),true) + ifneq ($(filter $(perf_pkg_name),$(packages_enabled)),) + $(call dh_all_inline,$(perfpkg)) + endif + endif +endif + +binary-debs-deps-$(do_flavour_image_package) += $(addprefix binary-,$(flavours)) + +.PHONY: binary-debs +binary-debs: binary-perarch $(binary-debs-deps-true) + @echo Debug: $@ + +build-arch-deps-$(do_flavour_image_package) += $(addprefix $(stampdir)/stamp-install-,$(flavours)) + +.PHONY: build-arch +build-arch: $(build-arch-deps-true) + @echo Debug: $@ + +binary-arch-deps-true += binary-debs binary-arch-headers +ifneq ($(do_common_headers_indep),true) +binary-arch-deps-$(do_flavour_header_package) += binary-headers +endif + +.PHONY: binary-arch +binary-arch: $(binary-arch-deps-true) + @echo Debug: $@ + --- linux-nvidia-7.0.0.orig/debian/rules.d/3-binary-indep.mk +++ linux-nvidia-7.0.0/debian/rules.d/3-binary-indep.mk @@ -0,0 +1,233 @@ +.PHONY: build-indep +build-indep: + @echo Debug: $@ + +# The binary-indep dependency chain is: +# +# install-headers <- install-source <- install-tools <- install-indep <- binary-indep +# install-headers <- binary-headers +# +indep_hdrpkg = $(indep_hdrs_pkg_name) +indep_hdrdir = $(CURDIR)/debian/$(indep_hdrpkg)/usr/src/$(indep_hdrpkg) + +$(stampdir)/stamp-install-headers: + @echo Debug: $@ + dh_testdir + dh_prep -p$(indep_hdrpkg) + +ifeq ($(do_flavour_header_package),true) + install -d $(indep_hdrdir) + find . -path './debian' -prune -o -path './$(DEBIAN)' -prune \ + -o -path './include/*' -prune \ + -o -path './scripts/*' -prune -o -type f \ + \( -name 'Makefile*' -o -name 'Kconfig*' -o -name 'Kbuild*' -o \ + -name '*.sh' -o -name '*.pl' -o -name '*.lds' \) \ + -print | cpio -pd --preserve-modification-time $(indep_hdrdir) + cp -a scripts include $(indep_hdrdir) + (find arch -name include -type d -print | \ + xargs -n1 -i: find : -type f) | \ + cpio -pd --preserve-modification-time $(indep_hdrdir) + # Do not ship .o and .cmd artifacts in headers + find $(indep_hdrdir) -name \*.o -or -name \*.cmd -exec rm -f {} \; +endif + $(stamp) + +srcpkg = linux-source-$(DEB_VERSION_UPSTREAM) +srcdir = $(CURDIR)/debian/$(srcpkg)/usr/src/$(srcpkg) +balldir = $(CURDIR)/debian/$(srcpkg)/usr/src/$(srcpkg)/$(srcpkg) +install-source: + @echo Debug: $@ +ifeq ($(do_source_package),true) + dh_prep -p$(srcpkg) + + install -d $(srcdir) +ifeq ($(do_source_package_content),true) + find . -path './debian' -prune -o -path './$(DEBIAN)' -prune -o \ + -path './.*' -prune -o -print | \ + cpio -pd --preserve-modification-time $(balldir) + (cd $(srcdir); tar cf - $(srcpkg)) | bzip2 -9c > \ + $(srcdir)/$(srcpkg).tar.bz2 + rm -rf $(balldir) + $(LN) $(srcpkg)/$(srcpkg).tar.bz2 $(srcdir)/.. +endif +endif + +.PHONY: install-tools +install-tools: bpftoolpkg = $(bpftool_pkg_name) +install-tools: bpftoolsbin = $(CURDIR)/debian/$(bpftoolpkg)/usr/sbin +install-tools: bpftoolman = $(CURDIR)/debian/$(bpftoolpkg)/usr/share/man +install-tools: bpftoolbashcomp = $(CURDIR)/debian/$(bpftoolpkg)/usr/share/bash-completion/completions +install-tools: perfpkg = $(perf_pkg_name) +install-tools: perfbin = $(CURDIR)/debian/$(perfpkg)/usr/bin +install-tools: perfman = $(CURDIR)/debian/$(perfpkg)/usr/share/man +install-tools: toolspkg = $(tools_common_pkg_name) +install-tools: toolsbin = $(CURDIR)/debian/$(toolspkg)/usr/bin +install-tools: toolssbin = $(CURDIR)/debian/$(toolspkg)/usr/sbin +install-tools: toolsman = $(CURDIR)/debian/$(toolspkg)/usr/share/man +install-tools: toolsbashcomp = $(CURDIR)/debian/$(toolspkg)/usr/share/bash-completion/completions +install-tools: hosttoolspkg = $(hosttools_pkg_name) +install-tools: hosttoolsbin = $(CURDIR)/debian/$(hosttoolspkg)/usr/bin +install-tools: hosttoolsman = $(CURDIR)/debian/$(hosttoolspkg)/usr/share/man +install-tools: hosttoolssystemd = $(CURDIR)/debian/$(hosttoolspkg)/lib/systemd/system +install-tools: cloudpkg = $(cloud_common_pkg_name) +install-tools: cloudbin = $(CURDIR)/debian/$(cloudpkg)/usr/bin +install-tools: cloudsbin = $(CURDIR)/debian/$(cloudpkg)/usr/sbin +install-tools: cloudman = $(CURDIR)/debian/$(cloudpkg)/usr/share/man +install-tools: $(stampdir)/stamp-build-perarch + @echo Debug: $@ + +ifeq ($(do_tools_common),true) + dh_prep -p$(toolspkg) + dh_prep -p$(perfpkg) + + rm -rf $(builddir)/tools + install -d $(builddir)/tools + for i in *; do $(LN) $(CURDIR)/$$i $(builddir)/tools/; done + rm $(builddir)/tools/tools + rsync -a tools/ $(builddir)/tools/tools/ + + install -d $(toolsbin) + install -d $(toolssbin) + install -d $(toolsman)/man1 + install -d $(toolsman)/man8 + install -d $(toolsbashcomp) + install -d $(perfbin) + install -d $(perfman)/man1 + + install -m755 debian/tools/generic $(toolsbin)/usbip + install -m755 debian/tools/generic $(toolsbin)/usbipd + install -m644 $(CURDIR)/tools/usb/usbip/doc/*.8 $(toolsman)/man8/ + + install -m755 debian/tools/generic $(toolsbin)/cpupower + install -m644 $(CURDIR)/tools/power/cpupower/man/*.1 $(toolsman)/man1/ + + install -m755 debian/tools/generic $(toolsbin)/rtla + + install -m755 debian/tools/generic $(toolsbin)/x86_energy_perf_policy + install -m755 debian/tools/generic $(toolsbin)/turbostat + + cd $(builddir)/tools/tools/perf && make man + install -m644 $(builddir)/tools/tools/perf/Documentation/*.1 \ + $(perfman)/man1 + + install -m644 $(CURDIR)/tools/power/x86/x86_energy_perf_policy/*.8 $(toolsman)/man8 + install -m644 $(CURDIR)/tools/power/x86/turbostat/*.8 $(toolsman)/man8 + +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + dh_prep -p$(cloudpkg) + + install -d $(cloudsbin) + install -m755 debian/tools/generic $(cloudsbin)/hv_kvp_daemon + install -m755 debian/tools/generic $(cloudsbin)/hv_vss_daemon +ifneq ($(build_arch),arm64) + install -m755 debian/tools/generic $(cloudsbin)/hv_fcopy_uio_daemon +endif + install -m755 debian/tools/generic $(cloudsbin)/lsvmbus + install -m755 debian/cloud-tools/hv_get_dhcp_info $(cloudsbin) + install -m755 debian/cloud-tools/hv_get_dns_info $(cloudsbin) + install -m755 debian/cloud-tools/hv_set_ifconfig $(cloudsbin) + + install -d $(cloudman)/man8 + install -m644 $(CURDIR)/tools/hv/*.8 $(cloudman)/man8 +endif +endif + +ifeq ($(do_tools_acpidbg),true) + install -m755 debian/tools/generic $(toolsbin)/acpidbg +endif + +endif + +ifeq ($(do_tools_host),true) + dh_prep -p$(hosttoolspkg) + + install -d $(hosttoolsbin) + install -d $(hosttoolsman)/man1 + install -d $(hosttoolssystemd) + + install -m 755 $(CURDIR)/tools/kvm/kvm_stat/kvm_stat $(hosttoolsbin)/ + install -m 644 $(CURDIR)/tools/kvm/kvm_stat/kvm_stat.service \ + $(hosttoolssystemd)/ + + cd $(builddir)/tools/tools/kvm/kvm_stat && make man + install -m644 $(builddir)/tools/tools/kvm/kvm_stat/*.1 \ + $(hosttoolsman)/man1 +endif + +ifeq ($(do_linux_tools),true) + ifeq ($(do_tools_bpftool),true) + dh_prep -p$(bpftoolpkg) + + install -d $(bpftoolsbin) + install -d $(bpftoolman)/man8 + install -d $(bpftoolbashcomp) + make -C $(builddir)/tools/tools/bpf/bpftool doc + install -m644 $(builddir)/tools/tools/bpf/bpftool/Documentation/*.8 \ + $(bpftoolman)/man8 + install -m644 $(builddir)/tools/tools/bpf/bpftool/bash-completion/bpftool \ + $(bpftoolbashcomp) + endif +endif + +.PHONY: install-indep +install-indep: $(stampdir)/stamp-install-headers install-source install-tools + @echo Debug: $@ + +# This is just to make it easy to call manually. Normally done in +# binary-indep target during builds. +.PHONY: binary-headers +binary-headers: $(stampdir)/stamp-install-headers + @echo Debug: $@ + dh_installchangelogs -p$(indep_hdrpkg) + dh_installdocs -p$(indep_hdrpkg) + dh_compress -p$(indep_hdrpkg) + dh_fixperms -p$(indep_hdrpkg) + dh_installdeb -p$(indep_hdrpkg) + $(lockme) dh_gencontrol -p$(indep_hdrpkg) + dh_md5sums -p$(indep_hdrpkg) + dh_builddeb -p$(indep_hdrpkg) + +binary-indep: cloudpkg = $(cloud_common_pkg_name) +binary-indep: hosttoolspkg = $(hosttools_pkg_name) +binary-indep: install-indep + @echo Debug: $@ + dh_installchangelogs -i + dh_installdocs -i + dh_compress -i + dh_fixperms -i +ifeq ($(do_tools_common),true) +ifeq ($(do_cloud_tools),true) +ifeq ($(do_tools_hyperv),true) + dh_installinit -p$(cloudpkg) -n --name hv-kvp-daemon + dh_installinit -p$(cloudpkg) -n --name hv-vss-daemon +ifneq ($(build_arch),arm64) + dh_installinit -p$(cloudpkg) -n --name hv-fcopy-daemon +endif + dh_installudev -p$(cloudpkg) -n --name hv-kvp-daemon + dh_installudev -p$(cloudpkg) -n --name hv-vss-daemon +ifneq ($(build_arch),arm64) + dh_installudev -p$(cloudpkg) -n --name hv-fcopy-daemon +endif + dh_systemd_enable -p$(cloudpkg) + dh_installinit -p$(cloudpkg) -o --name hv-kvp-daemon + dh_installinit -p$(cloudpkg) -o --name hv-vss-daemon +ifneq ($(build_arch),arm64) + dh_installinit -p$(cloudpkg) -o --name hv-fcopy-daemon +endif + dh_systemd_start -p$(cloudpkg) +endif + # Keep intel_sgx service disabled by default, so add it after dh_systemd_enable + # and dh_systemd_start are called: + dh_installinit -p$(cloudpkg) --no-start --no-enable --name intel-sgx-load-module +endif +endif +ifeq ($(do_tools_host),true) + # Keep kvm_stat.service disabled by default (after dh_systemd_enable + # and dh_systemd_start: + dh_installinit -p$(hosttoolspkg) --no-enable --no-start --name kvm_stat +endif + dh_installdeb -i + $(lockme) dh_gencontrol -i + dh_md5sums -i + dh_builddeb -i --- linux-nvidia-7.0.0.orig/debian/scripts/checks/final-checks +++ linux-nvidia-7.0.0/debian/scripts/checks/final-checks @@ -0,0 +1,47 @@ +#!/bin/bash + +debian="$1" +abi="$2" + +archs=$(awk '/^Architecture:/ { $1=""; for (i=1; i<=NF; i++) { if ($i != "all") { print $i }}}' debian/control | sort -u) + +fail=0 + +failure() +{ + echo "EE: $*" 1>&2 + fail=1 +} + +for arch in $archs +do + if [ ! -f "$debian/rules.d/$arch.mk" ]; then + continue + fi + + image_pkg=$(awk -F '\\s*=\\s*' '$1 == "do_flavour_image_package" { print $2 }' "$debian/rules.d/$arch.mk") + if [ "$image_pkg" = "false" ]; then + continue + fi + + flavours=$( + awk '/^\s*flavours\s*=/{ + sub(/^\s*flavours\s*=\s*/, ""); + print + }' "$debian/rules.d/$arch.mk") + for flavour in $flavours + do + if [ -d debian/certs ]; then + if ! python3 debian/scripts/misc/annotations --export -c CONFIG_SYSTEM_TRUSTED_KEYS --arch "$arch" --flavour "$flavour" | grep -q '^CONFIG_SYSTEM_TRUSTED_KEYS="debian/canonical-certs.pem"$' ; then + failure "'CONFIG_SYSTEM_TRUSTED_KEYS=\"debian/canonical-certs.pem\"' is required" + fi + fi + if [ -d debian/revoked-certs ]; then + if ! python3 debian/scripts/misc/annotations --export -c CONFIG_SYSTEM_REVOCATION_KEYS --arch "$arch" --flavour "$flavour" | grep -q '^CONFIG_SYSTEM_REVOCATION_KEYS="debian/canonical-revoked-certs.pem"$' ; then + failure "'CONFIG_SYSTEM_REVOCATION_KEYS=\"debian/canonical-revoked-certs.pem\"' is required" + fi + fi + done +done + +exit "$fail" --- linux-nvidia-7.0.0.orig/debian/scripts/checks/module-signature-check +++ linux-nvidia-7.0.0/debian/scripts/checks/module-signature-check @@ -0,0 +1,85 @@ +#!/bin/bash -eu + +flavor="${1}" +mods_dir="${2}" + +skip_checks=${3:-} +case "${skip_checks,,}" in + 1|true|yes) skip_checks=1 ;; + *) skip_checks=0 ;; +esac + +echo "II: Checking signature of staging modules for ${flavor}..." + +root=$(dirname "$(realpath -e "${0}")")/../../.. +. "${root}"/debian/debian.env + +# Collect the signature-inclusion files +sig_incs=() +for d in debian "${DEBIAN}" ; do + if [ -f "${root}"/"${d}"/signature-inclusion ] ; then + sig_incs+=("${root}"/"${d}"/signature-inclusion) + fi +done + +if [ "${#sig_incs[@]}" -gt 0 ] ; then + echo "II: Use signature inclusion file(s):" + printf " %s\n" "${sig_incs[@]}" + sig_all=0 +else + echo "WW: Signature inclusion file(s) missing" + echo "II: All modules must be signed" + sig_all=1 +fi + +if ! [ -d "${mods_dir}" ] ; then + echo "EE: Modules directory missing:" + echo " ${mods_dir}" + if [ ${skip_checks} -eq 1 ] ; then + echo "WW: Explicitly asked to ignore failures" + echo "II: Done" + exit 0 + fi + exit 1 +fi + +echo "II: Checking modules directory:" +echo " ${mods_dir}" +mods_dirs=("${mods_dir}") + +pass=0 +fail=0 +while IFS= read -r mod ; do + is=0 + if /sbin/modinfo "${mod}" | grep -q "^signature:" ; then + # Module is signed + is=1 + fi + + must=0 + if [ ${sig_all} -eq 1 ] || grep -qFx "${mod##*/}" "${sig_incs[@]}" ; then + # Module must be signed + must=1 + fi + + case "${is}${must}" in + 00) echo " PASS (unsigned) : ${mod##*/}" ; pass=$((pass + 1)) ;; + 01) echo " FAIL (unsigned) : ${mod##*/}" ; fail=$((fail + 1)) ;; + 10) echo " FAIL (signed) : ${mod##*/}" ; fail=$((fail + 1)) ;; + 11) echo " PASS (signed) : ${mod##*/}" ; pass=$((pass + 1)) ;; + esac +done < <(find "${mods_dirs[@]}" -path '*/drivers/staging/*.ko' | sort) + +echo "II: Checked $((pass + fail)) modules : ${pass} PASS, ${fail} FAIL" + +if [ ${fail} -ne 0 ] ; then + if [ ${skip_checks} -eq 1 ] ; then + echo "WW: Explicitly asked to ignore failures" + else + echo "EE: Modules signature failures" + exit 1 + fi +fi + +echo "II: Done" +exit 0 --- linux-nvidia-7.0.0.orig/debian/scripts/control-create +++ linux-nvidia-7.0.0/debian/scripts/control-create @@ -0,0 +1,137 @@ +#!/bin/bash + +set -e +shopt -s nullglob + +DEB_SOURCE=$1 + +. debian/debian.env + +if [ -z "${DEBIAN}" ]; then + echo "DEBIAN is empty" >&2 + exit 1 +fi + +gen_common () { + local stubs=("${DEBIAN}/control.stub.in") + + if [ "${DEB_SOURCE}" = linux ]; then + stubs+=( + debian/control.d/linux-libc-dev.stub + debian/control.d/linux-tools-common.stub + debian/control.d/linux-cloud-tools-common.stub + debian/control.d/linux-tools-host.stub + debian/control.d/linux-source.stub + debian/control.d/linux-doc.stub + debian/control.d/linux-bpf-dev.stub + debian/control.d/bpftool.stub + debian/control.d/linux-perf.stub + ) + fi + + for f in "${stubs[@]}" + do + cat "${f}" + echo "" + done +} + +gen_per_flavour () { + local arch bootloader conflicts flavour provides supported target + local sed_common_patterns signed_arch unsigned_arch depends + + var=$1 + + flavour=${var##*.} + + . "${var}" + + if [ "$provides" != '' ]; then + provides+=", " + fi + + if [ "$depends" != '' ]; then + depends+=", " + fi + + for a in ${arch} + do + # This is a makefile, so grepping... + if grep -q -E '(uefi|opal|sipl)_signed[[:space:]]*=[[:space:]]*true' "${DEBIAN}/rules.d/${a}.mk"; then + signed_arch+=("${a}") + else + unsigned_arch+=("${a}") + fi + done + + sed_common_patterns=( + -e "/^#/d" + -e "s/=DEPENDS=/${depends}/g" + -e "s/BOOTLOADER/${bootloader}/g" + -e "s/=CONFLICTS=/${conflicts}/g" + -e "s/FLAVOUR/${flavour}/g" + -e "s/=PROVIDES=/${provides}/g" + -e "s/SUPPORTED/${supported}/g" + -e "s/TARGET/${target}/g" + ) + + if [ "${#signed_arch[@]}" != 0 ]; then + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${signed_arch[*]}/g" \ + -e "s/=SIGN-ME-PKG=/-unsigned/g" \ + -e "s/=SIGN-ME-TXT=/ unsigned/g" \ + -e "s/=SIGN-PEER-PKG=//g" \ + "${DEBIAN}/control.d/flavour-signed-control.stub" + fi + + if [ "${#unsigned_arch[@]}" != 0 ]; then + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${unsigned_arch[*]}/g" \ + -e "s/=SIGN-ME-PKG=//g" \ + -e "s/=SIGN-ME-TXT=//g" \ + -e "s/=SIGN-PEER-PKG=/-unsigned/g" \ + "${DEBIAN}/control.d/flavour-signed-control.stub" + fi + + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${arch}/g" \ + "${DEBIAN}/control.d/flavour-control.stub" + + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${arch}/g" \ + "debian/control.d/flavour-buildinfo.stub" + + while read -r package version extras + do + module="$package" + module_type= + + # Module arch parameters are skipped here, so a package section will + # be generated for each flavour, and its Architecture will be set to + # all architectures with that flavour. Even that is being generated, + # it doesn't follow all of them will be built. That's to work-around + # dkms_exclude/dkms_include that manipulates supported architectures + # in $(DEBIAN)/rules.d/$(arch).mk. + for param in $extras; do + case "$param" in + modulename=*) module="${param#modulename=}" ;; + type=*) module_type="${param#type=}" ;; + *) continue ;; + esac + done + + [ "$module_type" = "standalone" ] || continue + + sed "${sed_common_patterns[@]}" \ + -e "s/ARCH/${arch}/g" \ + -e "s/MODULE/${module}/g" \ + debian/control.d/flavour-module.stub + done < "${DEBIAN}/dkms-versions" +} + +gen_common + +for v in "${DEBIAN}"/control.d/vars.* +do + gen_per_flavour "${v}" +done --- linux-nvidia-7.0.0.orig/debian/scripts/dkms-build +++ linux-nvidia-7.0.0/debian/scripts/dkms-build @@ -0,0 +1,281 @@ +#!/bin/sh +set -e + +dkms_dir="$1" +abi_flavour="$2" +sign="$3" +pkgname="$4" +pkgdir="$5" +dbgpkgdir="$6" +package="$7" +shift 7 + +here=$(dirname "$(readlink -f "${0}")") + +srcdir=$(pwd) +cd "$dkms_dir" || exit 1 + +built_using_record() +{ + local subst="$1" + local built_using="$2" + if [ ! -f "$subst" ]; then + touch "$subst" + fi + if ! grep -q -s "^linux:BuiltUsing=" "$subst"; then + echo "linux:BuiltUsing=" >>"$subst" + fi + sed -i -e "s/^\(linux:BuiltUsing=.*\)/\1$built_using, /" "$subst" +} + +# ABI: returns present in $? and located path in lpackage_path when found. +package_present() +{ + for lpackage_path in "$1"_*.deb + do + break + done + [ -f "$lpackage_path" ] +} + +# Download and extract the DKMS package -- note there may be more +# than one package to install. +for package_path in "$@" +do + package_file=$(basename "$package_path") + echo "II: dkms-build downloading $package ($package_file)" + rpackage=$( echo "$package_path" | sed -e 's@.*/@@' -e 's@_.*@@' ) + lpackage=$( echo "$rpackage" | sed -e 's@=.*@@' ) + + while true + do + if package_present "$lpackage"; then + break + fi + case "$package_path" in + pool/*) + # Attempt download from the launchpad librarian first. + "$here/file-downloader" "https://launchpad.net/ubuntu/+archive/primary/+files/$package_file" || true + if package_present "$lpackage"; then + break + fi + + # Get pools from *.list files. + slist_files="/etc/apt/sources.list $( find /etc/apt/sources.list.d/ -type f -name "*.list" | xargs )" + slist_pools=$( grep -h '^deb ' $slist_files | awk '{print $2}' ) + + # Get pools from *.sources (deb822-style) files. + deb822_files=$( find /etc/apt/sources.list.d/ -type f -name "*.sources" | xargs ) + # Split stanzas on empty lines and only select deb pools, then get the URIs. + # Since RS != \n, regex is not line-by-line so the newline matching is more explicit. + deb822_pools=$( awk -v RS= '/(^|\n)Types:[^\n]* deb($|\s)/' $deb822_files | sed -n 's/^URIs: //p' ) + + # Download from the available pools. + for pool in $( echo $slist_pools $deb822_pools | xargs -n1 | sort -u ) + do + if package_present "$lpackage"; then + break + fi + url="$pool/$package_path" + "$here/file-downloader" "$url" && break || true + # No components in PPAs. + url=$(echo "$url" | sed -e 's@/pool/[^/]*/@/pool/main/@') + "$here/file-downloader" "$url" && break || true + done + ;; + http*:*) + "$here/file-downloader" "$package_path" + ;; + */*) + cp -p "$package_path" . + ;; + *) + apt-get download "$rpackage" + ;; + esac + break + done + if ! package_present "$lpackage"; then + echo "EE: $lpackage not found" + exit 1 + fi + + dpkg -x "$lpackage"_*.deb "$package" + + lversion=$( echo "$lpackage_path" | sed -e 's@.*/@@' -e 's@_[^_]*$@@' -e 's@.*_@@') + #built_using_record "$srcdir/debian/$pkgname.substvars" "$built_using$lpackage (= $lversion)" +done + +# Pick out the package/version from the dkms.conf. +for dkms_conf in "$package/usr/src"/*/"dkms.conf" +do + break +done + +# It seems some packages have a # in the name which works fine if the +# package is installed directly, but not so much if we build it out +# of the normal location. +sed -i -e '/^PACKAGE_NAME=/ s/#//g' "$dkms_conf" + +# Run any dkms-package specfic configuration steps +dkms_config_specific="$srcdir/$0-configure--$package" +dkms_config_generic=$(echo "$dkms_config_specific" | sed -e 's/-[0-9][0-9]*$/-N/') +for dkms_config in "$dkms_config_specific" "$dkms_config_generic" +do + if [ -z "$dkms_config" -o ! -e "$dkms_config" ]; then + continue + fi + echo "II: dkms-build-configure $(basename "$dkms_config") found, executing" + "$dkms_config" \ + "$srcdir" \ + "$dkms_conf" \ + "$dkms_dir" \ + "$abi_flavour" \ + "$sign" \ + "$pkgname" \ + "$pkgdir" \ + "$dbgpkgdir" \ + "$package" \ + "$@" || exit 1 + break +done + +cat - <<'EOF' >>"$dkms_conf" +POST_BUILD="ubuntu-save-objects ${dkms_tree}/${PACKAGE_NAME}/${PACKAGE_VERSION}/build ${dkms_tree}/${PACKAGE_NAME}/${PACKAGE_VERSION}/objects $POST_BUILD" +EOF +ubuntu_script="$(dirname "$dkms_conf")/ubuntu-save-objects" +cat - <<'EOF' >"$ubuntu_script" +#!/bin/sh +from="$1" +to="$2" +script="$3" +shift 2 + +# Copy the objects. +echo "II: copying objects to '$to'" +mkdir -p "$to" +(cd "$from" && find -name \*.o -o -name \*.mod | cpio -Lpd "$to") + +# Call the original post_install script if there is one. +[ "$script" = '' ] && exit 0 + +shift +exec "$(dirname "$0")/$script" "$@" +EOF +chmod +x "$ubuntu_script" +dkms_package=$( sed -ne 's/PACKAGE_NAME="\(.*\)"/\1/p' "$dkms_conf" ) +dkms_version=$( sed -ne 's/PACKAGE_VERSION="\(.*\)"/\1/p' "$dkms_conf" ) + +# Build the DKMS binaries. +echo "II: dkms-build building $package" +fakeroot="" +[ $(id -u) -ne 0 ] && fakeroot="/usr/bin/fakeroot" +rc=0 +$fakeroot /usr/sbin/dkms build --no-prepare-kernel --no-clean-kernel \ + -k "$abi_flavour" ${ARCH:+-a $ARCH} \ + --sourcetree "$dkms_dir/source" \ + --dkmstree "$dkms_dir/build" \ + --kernelsourcedir "$dkms_dir/headers/linux-headers-$abi_flavour" \ + "$dkms_conf" || rc=$? + +# Find the log and add it to our own. +for log in "$dkms_dir/build/$dkms_package/$dkms_version/$abi_flavour"/*/"log/make.log" "$dkms_dir/build/$dkms_package/$dkms_version/build/make.log" +do + if [ -f "$log" ]; then + sed -e "s@$dkms_dir@<>@g" <"$log" + break + fi +done + +# If this build failed then exit here. +[ "$rc" != 0 ] && exit "$rc" + +# Install the modules with debug symbols we possibly built, +# and strip the original modules for the next install step. +if [ -n "$dbgpkgdir" ]; then + dbgpkgdir="$dbgpkgdir/$package" + echo "II: dkms-build installing $package into $dbgpkgdir (debug symbols)" + install -d "$dbgpkgdir" + find "$dkms_dir/build/$dkms_package/$dkms_version/$abi_version" -name \*.ko | + while read module; do + vmodule=$( basename "$module" ) + + # Check for '.debug_info' section in order to copy module. + # Useful if debug symbols are requested but not built for + # any reason (including not yet supported by DKMS package). + # Strip module just in case even if section isn't present. + if ${CROSS_COMPILE}objdump -h -j '.debug_info' "$module" >/dev/null 2>&1 + then + echo "copying $vmodule" + cp "$module" "$dbgpkgdir" + else + echo "ignoring $vmodule (missing debug symbols)" + fi + + # Just 'strip -g' as '/usr/sbin/dkms' does. + echo "stripping $vmodule" + strip -g "$module" + done +fi + +# Install and optionally sign the modules we have built. +pkgdir="$pkgdir/$package" +echo "II: dkms-build installing $package into $pkgdir" +install -d "$pkgdir" +find "$dkms_dir/build/$dkms_package/$dkms_version/$abi_version" -name \*.ko | +while read module; do + vmodule=$( basename "$module" ) + case "$sign" in + --*) + echo "copying $vmodule" + cp "$module" "$pkgdir" + ;; + *) + echo "signing $vmodule" + $sign "$module" "$pkgdir/$vmodule" + ;; + esac +done + +find "$dkms_dir/build/$dkms_package/$dkms_version/objects" -name \*.o -print | \ +while read object +do + "$srcdir/debian/scripts/fix-filenames" "$object" "$dkms_dir" +done + +# This assumes that .mod files are in the top level build tree +# If there are ever .mod files in sub-directories, the dirname of objectlist needs to be stripped as well +find "$dkms_dir/build/$dkms_package/$dkms_version/objects" -name \*.mod -print | \ +while read objectlist +do + sed "s|^$dkms_dir/build/$dkms_package/$dkms_version/build/||" -i $objectlist +done + +# Finally see if there is a dkms-package specific post processor present. Hand +# it the original source directory, destination package directory, the objects +# as squirreled away, and the log in case it is useful. Finally pass a formed +# signing command line in case we need to do that. +dkms_build_specific="$srcdir/$0--$package" +dkms_build_generic=$(echo "$dkms_build_specific" | sed -n -e 's/-[0-9][0-9]*[a-z]*$/-N/p') +for dkms_build in "$dkms_build_specific" "$dkms_build_generic" +do + if [ -z "$dkms_build" -o ! -e "$dkms_build" ]; then + continue + fi + echo "II: dkms-build override $(basename "$dkms_build") found, executing" + "$dkms_build" \ + "$srcdir" \ + "$dkms_dir/build/$dkms_package/$dkms_version/objects" \ + "$log" \ + "$dkms_dir" \ + "$abi_flavour" \ + "$sign" \ + "$pkgname" \ + "$pkgdir" \ + "$dbgpkgdir" \ + "$package" \ + "$@" || exit 1 + break +done + +echo "II: dkms-build build $package complete" --- linux-nvidia-7.0.0.orig/debian/scripts/dkms-build--nvidia-N +++ linux-nvidia-7.0.0/debian/scripts/dkms-build--nvidia-N @@ -0,0 +1,113 @@ +#!/bin/sh +set -e + +srcdir="$1" +objects="$2" +log="$3" +shift 3 + +dkms_dir="$1" +abi_flavour="$2" +sign="$3" +pkgname="$4" +pkgdir="$5" +dbgpkgdir="$6" +package="$7" +shift 7 + +build="$( dirname "$objects" )/build" + +# Copy over the objects ready for reconstruction. The objects copy +# contains the *.o files. For our purposes we only want the *.o files, +# elide the rest. And .mod files for ld linking in recentish kernels. +mkdir -p "$pkgdir/bits/scripts" +( + gcc_variant1=$(gcc --version | head -1 | sed -e 's/^gcc/GCC:/') + gcc_variant2=$(gcc --version | head -1 | sed -e 's/^\(gcc\) \((.*)\) \(.*\)$/\1 version \3 \2/') + cd "$objects" || exit 1 + find -name \*.o -o -name \*.mod | \ + while read file + do + cp --parents "$file" "$pkgdir/bits" + "$srcdir/debian/scripts/fix-filenames" "$pkgdir/bits/$file" "$gcc_variant1" + "$srcdir/debian/scripts/fix-filenames" "$pkgdir/bits/$file" "$gcc_variant2" + done +) + +# Install the support files we need. +echo "II: copying support files ..." +for lds_src in \ + "$dkms_dir/headers/linux-headers-$abi_flavour/scripts/module.lds" \ + "/usr/src/linux-headers-$abi_flavour/scripts/module.lds" \ + "$dkms_dir/headers/linux-headers-$abi_flavour/scripts/module-common.lds" \ + "/usr/src/linux-headers-$abi_flavour/scripts/module-common.lds" +do + [ ! -f "$lds_src" ] && continue + echo "II: copying support files ... found $lds_src" + cp "$lds_src" "$pkgdir/bits/scripts" + break +done + +# Build helper scripts. +cat - <<'EOL' >"$pkgdir/bits/BUILD" +[ "$1" = "unsigned" ] && { signed_only=:; shift; } +[ "$1" = "nocheck" ] && { check_only=:; shift; } +EOL +echo "export ELF_PACKAGE_METADATA='${ELF_PACKAGE_METADATA}'" >>"$pkgdir/bits/BUILD" +grep /usr/bin/ld.bfd "$log" | grep -v scripts/genksyms/genksyms | grep -v "warning:\|NOTE:" | sed -e "s@$build/@@g" -e 's@/build/[^ ]*/scripts/module.lds@scripts/module.lds@' >>"$pkgdir/bits/BUILD" +sed -e 's/.*-o *\([^ ]*\) .*/rm -f \1/g' <"$pkgdir/bits/BUILD" >"$pkgdir/bits/CLEAN" + +# As the builds contain the absolute filenames as used. Use RECONSTRUCT to +# rebuild the .ko's, sign them, pull off the signatures and then finally clean +# up again. +( + cd "$pkgdir/bits" + + # Add checksum check. + echo "\$check_only sha256sum -c SHA256SUMS || exit 1" >>"$pkgdir/bits/BUILD" + + # Add .ko handling to the CLEAN/BUILD dance. + for ko in "$pkgdir"/*.ko + do + ko=$(basename "$ko") + echo "\$signed_only cat '$ko' '$ko.sig' >'../$ko'" >>"$pkgdir/bits/BUILD" + echo "\$signed_only rm -f '$ko'" >>"$pkgdir/bits/BUILD" + echo "rm -f '../$ko'" >>"$pkgdir/bits/CLEAN" + done + + # Clear out anything we are not going to distribute and build unsigned .kos. + sh ./CLEAN + sh ./BUILD unsigned nocheck + + if [ "$sign" = "--custom" ]; then + # We are building for and archive custom signing upload. Keep everything. + : + elif [ "$sign" = "--lrm" ]; then + # We are in the LRM build; grab sha256 checksums and clean up. + sha256sum -b *.ko >"SHA256SUMS" + sh ./CLEAN + + else + # We are in the main kernel, put the .kos together as we will + # on the users machine, sign them, and keep just the signature. + : >"SHA256SUMS" + for ko in *.ko + do + echo "detached-signature $ko" + $sign "$ko" "$ko.signed" + length=$( stat --format %s "$ko" ) + dd if="$ko.signed" of="$ko.sig" bs=1 skip="$length" 2>/dev/null + + rm -f "$ko.signed" + # Keep a checksum of the pre-signed object so we can check it is + # built correctly in LRM. + sha256sum -b "$ko" >>"SHA256SUMS" + done + + # Clean out anything which not a signature. + mv "$pkgdir/bits/"*.sig "$pkgdir" + mv "$pkgdir/bits/SHA256SUMS" "$pkgdir" + find "$pkgdir" -name \*.sig -prune -o -name SHA256SUMS -prune -o -type f -print | xargs rm -f + find "$pkgdir" -depth -type d -print | xargs rmdir --ignore-fail-on-non-empty + fi +) --- linux-nvidia-7.0.0.orig/debian/scripts/dkms-build-configure--zfs +++ linux-nvidia-7.0.0/debian/scripts/dkms-build-configure--zfs @@ -0,0 +1,24 @@ +#!/bin/sh +set -e + +srcdir="$1" +dkms_conf="$2" +shift 2 + +dkms_dir="$1" +abi_flavour="$2" +sign="$3" +pkgname="$4" +pkgdir="$5" +dbgpkgdir="$6" +package="$7" +shift 7 + +# ZFS debug symbols are enabled in dkms.conf via PACKAGE_CONFIG file. +if [ -n "$dbgpkgdir" ]; then + echo "enable zfs debug symbols" + pkg_cfg="$(dirname "$dkms_conf")/pkg_cfg" + echo 'ZFS_DKMS_ENABLE_DEBUGINFO=yes' >"$pkg_cfg" + echo 'ZFS_DKMS_DISABLE_STRIP=yes' >>"$pkg_cfg" + sed -i "s,^\(PACKAGE_CONFIG=\).*,\1$pkg_cfg," $dkms_conf +fi --- linux-nvidia-7.0.0.orig/debian/scripts/file-downloader +++ linux-nvidia-7.0.0/debian/scripts/file-downloader @@ -0,0 +1,34 @@ +#!/bin/sh + +if [ "$#" -ne 1 ]; then + echo "Usage: $0 " 1>&2 + exit 1 +fi +url="$1" + +to=$(basename "$url") + +count=0 +what='fetching' +while : +do + if [ "$count" -eq 20 ]; then + echo "EE: excessive redirects" 1>&2 + exit 1 + fi + count=$(($count+1)) + + echo "II: $what $url" + + curl --silent --fail --show-error "$url" -o "$to" -D "$to.hdr" || exit 1 + redirect=$(awk '/^Location: / {gsub(/^[[:space:]]+|[[:space:]]+$/,"",$2); print $2;}' "$to.hdr") + [ -z "$redirect" ] && break + what=' following' + + url=$(echo "$redirect" | sed -e 's@https://launchpadlibrarian.net/@http://launchpadlibrarian.net/@') + if [ "$redirect" != "$url" ]; then + echo "II: fixing $redirect" + fi +done + +exit 0 --- linux-nvidia-7.0.0.orig/debian/scripts/fix-filenames.c +++ linux-nvidia-7.0.0/debian/scripts/fix-filenames.c @@ -0,0 +1,80 @@ +/* + * fix-filenames: find a specified pathname prefix and remove it from + * C strings. + * + * Copyright (C) 2018 Canonical Ltd. + * Author: Andy Whitcroft + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +main(int argc, char *argv[]) +{ + int rc; + char *in_name; + char *prefix; + int prefix_len; + int in_fd; + struct stat in_info; + char *in; + off_t size; + int length; + + if (argc != 3) { + fprintf(stderr, "Usage: %s \n", argv[0]); + exit(1); + } + in_name = argv[1]; + prefix = argv[2]; + prefix_len = strlen(prefix); + + in_fd = open(in_name, O_RDWR); + if (in_fd < 0) { + perror("open input failed"); + exit(1); + } + + rc = fstat(in_fd, &in_info); + if (rc < 0) { + perror("fstat input failed"); + exit(1); + } + size = in_info.st_size; + + in = mmap((void *)0, size, PROT_READ|PROT_WRITE, MAP_SHARED, in_fd, (off_t)0); + if (!in) { + perror("mmap failed"); + exit(1); + } + + for (; size > 0; size--, in++) { + if (*in != *prefix) + continue; + if (strncmp(in, prefix, prefix_len) != 0) + continue; + /* In the case of an exact match there there is nothing to move. */ + if (in[prefix_len] == '\0') + length = 0; + /* If this is a filename, strip the leading slash. */ + else if (in[prefix_len] == '/') + length = strlen(in + prefix_len + 1) + 1; + /* Otherwise just keep the suffix. */ + else + length = strlen(in + prefix_len) + 1; + + /* + * Copy the suffix portion down to the start and clear + * the remainder of the space to 0. + */ + memmove(in, in + prefix_len + 1, length); + memset(in + length, '\0', prefix_len); + } +} --- linux-nvidia-7.0.0.orig/debian/scripts/link-headers +++ linux-nvidia-7.0.0/debian/scripts/link-headers @@ -0,0 +1,42 @@ +#!/bin/bash -e + +. debian/debian.env + +hdrdir="$1" +symdir="$2" +flavour="$3" + +echo "Symlinking and copying headers for $flavour..." + +excludes="( -path ./debian -prune -o -path ./${DEBIAN} -prune -o -path ./.git ) -prune -o" + +( +find . $excludes -type f \ + \( -name 'Makefile*' -o -name 'Kconfig*' -o -name 'Kbuild*' -o \ + -name '*.sh' -o -name '*.pl' -o -name '*.lds' \) -print +find ./include ./scripts -name .gitignore -prune -o -type f -print +find ./include -mindepth 1 -maxdepth 1 $excludes -type d -print +) | ( +while read file; do + dir=$file + lastdir=$file + + if [ -e "$hdrdir/$file" -o -L "$hdrdir/$file" ]; then + continue + fi + + while [ ! -e "$hdrdir/$dir" -a ! -L "$hdrdir/$dir" ]; do + lastdir=$dir + dir=`dirname $dir` + done + # If the last item to exist is a symlink we assume all is good + if [ ! -L "$hdrdir/$dir" ]; then + # Turns things like "./foo" into "../" + deref="`echo -n $lastdir | sed -e 's/^\.//' -e's,/[^/]*,../,g'`" + item="`echo -n $lastdir | sed -e 's/^\.\///'`" + ln -s $deref$symdir/$item $hdrdir/$item + fi +done +) + +exit --- linux-nvidia-7.0.0.orig/debian/scripts/link-lib-rust +++ linux-nvidia-7.0.0/debian/scripts/link-lib-rust @@ -0,0 +1,17 @@ +#!/bin/bash -e + +. debian/debian.env + +hdrdir="$1" +symdir="$2" +flavour="$3" + +echo "Symlinking and copying Rust files for $flavour..." + +# Symlink Rust folder +item=rust +relpath=$(echo $symdir | sed s/headers/lib-rust/)-$flavour/$item +echo ln -s ../$relpath $hdrdir/$item +ln -s ../$relpath $hdrdir/$item + +exit --- linux-nvidia-7.0.0.orig/debian/scripts/misc/annotations +++ linux-nvidia-7.0.0/debian/scripts/misc/annotations @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 +# -*- mode: python -*- + +# This file is not installed; it's just to run annotations from inside a source +# distribution without installing it in the system. + +import sys + +# Prevent generating .pyc files on import +# +# We may end up adding these files to our git repos by mistake, so simply +# prevent generating them in advance. +# +# There's a tiny performance penalty with this, because python needs to +# re-generate the bytecode on-the-fly every time the script is executed, but +# this overhead is absolutely negligible compared the rest of the kernel build +# time. +sys.dont_write_bytecode = True + +import os # noqa: E402 Import not at top of file + +from kconfig import run # noqa: E402 Import not at top of file + + +# Update PATH to make sure that annotations can be executed directly from the +# source directory. +def update_path(): + script_dir = os.path.dirname(os.path.abspath(__file__)) + current_path = os.environ.get("PATH", "") + new_path = f"{script_dir}:{current_path}" + os.environ["PATH"] = new_path + + +update_path() +exit(run.main()) --- linux-nvidia-7.0.0.orig/debian/scripts/misc/find-missing-sauce.sh +++ linux-nvidia-7.0.0/debian/scripts/misc/find-missing-sauce.sh @@ -0,0 +1,15 @@ +#!/bin/bash +# +# Find the 'UBUNTU: SAUCE:' patches that have been dropped from +# the previous release. +# +PREV_REL=focal +PREV_REPO=git://kernel.ubuntu.com/ubuntu/ubuntu-${PREV_REL}.git + +git fetch ${PREV_REPO} master-next +git log --pretty=oneline FETCH_HEAD|grep SAUCE|while read c m;do echo $m;done |sort > $$.prev-rel +git log --pretty=oneline |grep SAUCE|while read c m;do echo $m;done |sort > $$.curr-rel + +diff -u $$.prev-rel $$.curr-rel |grep "^-" +rm -f $$.prev-rel $$.curr-rel + --- linux-nvidia-7.0.0.orig/debian/scripts/misc/gen-auto-reconstruct +++ linux-nvidia-7.0.0/debian/scripts/misc/gen-auto-reconstruct @@ -0,0 +1,89 @@ +#!/bin/bash + +if [ "$#" -ne 3 ]; then + echo "Usage: $0 | " 1>&2 + exit 1 +fi +tag="$1" +reconstruct="$2" +options="$3" + +case "$tag" in +v*) ;; +*) tag="v${tag%.*}" ;; +esac + +# Validate the tag. +count=$( git tag -l "$tag" | wc -l ) +if [ "$count" != 1 ]; then + echo "$0: $tag: tag invalid" 1>&2 + exit 1 +fi + +#git ls-tree -r --full-tree HEAD | grep ^120 | \ +#while read mode type blobid name + +( + # Identify all new symlinks since the proffered tag. + echo "# Recreate any symlinks created since the orig." + git diff "$tag.." --raw --no-renames | awk '(/^:000000 120000/ && $5 == "A") { print $NF }' | \ + while read name + do + link=$( readlink "$name" ) + + echo "[ ! -L '$name' ] && ln -sf '$link' '$name'" + done + + # Identify files with execute permissions added since the proffered tag. + git diff "$tag.." --raw --no-renames | awk -F '[: \t]' '{print $2, $3, $NF }' | \ + while IFS=" " read old new name + do + old=$( printf "0%s" $old ) + new=$( printf "0%s" $new ) + changed=$(( (old ^ new) & 0111 )) + if [ "$changed" -ne 0 ]; then + added=$(( new & 0111 )) + if [ "$added" -ne 0 ]; then + echo "chmod +x '$name'" + elif [ "$new" -ne 0 ]; then + echo "chmod -x '$name'" + fi + fi + done + + # Identify all removed files since the proffered tag. + echo "# Remove any files deleted from the orig." + git diff "$tag.." --raw --no-renames | awk '(/^:/ && $5 == "D") { print $NF }' | \ + while read name + do + echo "rm -f '$name'" + done + + # All done, make sure this does not complete in error. + echo "exit 0" +) >"$reconstruct" + +( + # Identify all new symlinks since the proffered tag. + echo "# Ignore any symlinks created since the orig which are rebuilt by reconstruct." + git diff "$tag.." --raw --no-renames | awk '(/^:000000 120000/ && $5 == "A") { print $NF }' | \ + while read name + do + echo "extend-diff-ignore=^$name\$" + done +) >"$options.update" + + +head='^## autoreconstruct -- begin$' +foot='^## autoreconstruct -- end$' +sed -i -e " + /$head/,/$foot/{ + /$head/{ + p; + r $options.update + }; + /$foot/p; + d + } +" "$options" +rm -f "$options.update" --- linux-nvidia-7.0.0.orig/debian/scripts/misc/git-ubuntu-log +++ linux-nvidia-7.0.0/debian/scripts/misc/git-ubuntu-log @@ -0,0 +1,163 @@ +#!/usr/bin/env python3 + +import codecs +import json +import sys +import textwrap +import urllib.request + +sys.stdin = codecs.getreader("utf-8")(sys.stdin.detach()) +sys.stdout = codecs.getwriter("utf-8")(sys.stdout.detach()) + +entries = [] + + +def add_entry(entry): + global tracking_bug + + if entry and "ignore" not in entry: + combo = [] + for bug in set(entry.get("bugs", [])): + combo.append(bug) + for cve in set(entry.get("cves", [])): + combo.append(cve) + combo = sorted(combo) + + if len(combo) == 0: + if entry.get("subject", "").startswith("UBUNTU"): + combo = "__packaging__" + else: + combo = "__mainline__" + else: + if entry.get("subject", "") == "UBUNTU: link-to-tracker: update tracking bug": + tracking_bug = combo + if combo not in keys: + keys.append(combo) + + entry["key"] = combo + entries.append(entry) + + +# Suck up the git log output and extract the information we need. +keys = [] +tracking_bug = None +entry = None +subject_wait = False +for line in sys.stdin: + if line.startswith("commit "): + add_entry(entry) + entry = {} + subject_wait = True + + elif line.startswith("Author: "): + bits = line.strip().split(maxsplit=1) + entry["author"] = bits[1] + + elif subject_wait and line.startswith(" "): + subject_wait = False + entry["subject"] = line.strip() + + elif line.startswith(" BugLink: "): + bits = line.strip().split(maxsplit=2) + if len(bits) > 2: + # There is text after the URL, so use that (after stripping the + # enclosing characters) + entry.setdefault("bugs", []).append(bits[2][1:-1]) + elif "launchpad.net" in bits[1]: + # Extract the bug number from the launchpad URL + bits = bits[1].split("/") + entry.setdefault("bugs", []).append(bits[-1]) + + elif line.startswith(" CVE-"): + entry.setdefault("cves", []).append(line.strip()) + + elif line.startswith(" Ignore:"): + entry["ignore"] = True + + elif line.startswith(" Properties:"): + for prop in line.strip().split()[1:]: + if prop in ("ignore", "no-changelog"): + entry["ignore"] = True + +add_entry(entry) + +entries.reverse() + +# Go through the entries and clear out authors for upstream commits. +for entry in entries: + if entry["subject"].startswith("UBUNTU:"): + entry["subject"] = entry["subject"][7:].strip() + else: + del entry["author"] + +# Lump everything without a bug at the bottom. +keys.append("__packaging__") +keys.append("__mainline__") + +# Ensure we list the tracking bug updates first. +if tracking_bug is not None: + keys.remove(tracking_bug) + keys.insert(0, tracking_bug) + +emit_nl = False +for key in keys: + if key == "__packaging__": + title_set = ["Miscellaneous Ubuntu changes"] + elif key == "__mainline__": + title_set = ["Miscellaneous upstream changes"] + else: + title_set = [] + for bug in key: + if bug.startswith("CVE-"): + title_set.append(bug) + elif bug.isdigit(): + # Assume that it is an LP bug number if 'bug' contains only digits + bug_info = None + + try: + # urllib.request.urlcleanup() + request = urllib.request.Request("https://api.launchpad.net/devel/bugs/" + bug) + request.add_header("Cache-Control", "no-cache") + with urllib.request.urlopen(request) as response: + data = response.read() + bug_info = json.loads(data.decode("utf-8")) + + title = bug_info["title"] + if "description" in bug_info: + for line in bug_info["description"].split("\n"): + if line.startswith("Kernel-Description:"): + title = line.split(" ", 1)[1] + + except urllib.error.HTTPError: + title = "INVALID or PRIVATE BUG" + + title += " (LP###" + bug + ")" + title_set.append(title) + else: + # Finally treat 'bug' itself as the title + title_set.append(bug) + + emit_title = True + for entry in entries: + if entry["key"] != key: + continue + + if emit_title: + if emit_nl: + print("") + emit_nl = True + + title_lines = textwrap.wrap("#// ".join(title_set), 76) + print(" * " + title_lines[0].replace("LP###", "LP: #").replace("#//", " //")) + for line in title_lines[1:]: + line = line.replace("LP###", "LP: #").replace("#//", " //") + print(" " + line) + + emit_title = False + + if key != tracking_bug or (key == tracking_bug and entry["subject"] != "link-to-tracker: update tracking bug"): + title_lines = textwrap.wrap(entry["subject"], 76) + print(" - " + title_lines[0]) + for line in title_lines[1:]: + line = line.replace("LP###", "LP: #") + print(" " + line) --- linux-nvidia-7.0.0.orig/debian/scripts/misc/insert-changes +++ linux-nvidia-7.0.0/debian/scripts/misc/insert-changes @@ -0,0 +1,42 @@ +#!/usr/bin/python3 + +import os +import sys + +from subprocess import check_output + +droot = 'debian' +if len(sys.argv) > 1: + droot = sys.argv[1] + +debian = 'debian.master' +if len(sys.argv) > 2: + debian = sys.argv[2] + +rules = os.path.join(droot, 'rules') +changelog = os.path.join(debian, 'changelog') +changelog_new = os.path.join(debian, 'changelog.new') + +# Generate the list of new changes +changes = check_output(['make', '-s', '-f', rules, 'printchanges']).decode('UTF-8') + +# Insert the new changes into the changelog +with open(changelog) as orig, open(changelog_new, 'w') as new: + printed = False + skip_newline = False + for line in orig: + if line.startswith(' CHANGELOG: '): + if not printed: + printed = True + if changes == '': + skip_newline = True + continue + new.write(changes) + else: + if skip_newline and line.strip() == '': + skip_newline = False + continue + new.write(line) + +# Replace the original changelog with the new one +os.rename(changelog_new, changelog) --- linux-nvidia-7.0.0.orig/debian/scripts/misc/insert-ubuntu-changes +++ linux-nvidia-7.0.0/debian/scripts/misc/insert-ubuntu-changes @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 + +import re +import os +import sys + +def version_cmp(a, b): + a = re.split(r"[\.-]+", a) + b = re.split(r"[\.-]+", b) + i = 0 + while True: + if len(a) <= i: + if len(b) <= i: + return 0 + return -1 + if len(b) <= i: + return 1 + if int(a[i]) < int(b[i]): + return -1 + if int(a[i]) > int(b[i]): + return 1 + i += 1 + +if len(sys.argv) == 4: + sys.argv.append("debian.master/changelog") + +if len(sys.argv) == 5: + changelog, end, start, source_changelog = sys.argv[1:] +else: + print("Usage: insert-ubuntu-changes []") + sys.exit(1) + +changes = [] +output = False +with open(source_changelog) as fh: + for line in fh: + m = re.match(r"^\S+\s+\((.*)\)", line) + if m: + if version_cmp(m.group(1), end) <= 0: + break + if m.group(1) == start: + output = True + if output: + changes.append("\n") + changes.append(" [ Ubuntu: {} ]\n".format(m.group(1))) + changes.append("\n") + continue + + if output and re.match(r"^( * | | )\S", line): + changes.append(line) + +printed = 3 +with open(changelog + ".new", "w") as fh_new: + with open(changelog) as fh: + for line in fh: + if line.startswith(" CHANGELOG: "): + printed -= 1 + fh_new.write(line) + if printed == 0: + fh_new.write("".join(changes)) + continue + fh_new.write(line) + +os.rename(changelog + ".new", changelog) --- linux-nvidia-7.0.0.orig/debian/scripts/misc/kconfig/annotations.py +++ linux-nvidia-7.0.0/debian/scripts/misc/kconfig/annotations.py @@ -0,0 +1,521 @@ +# -*- mode: python -*- +# python module to manage Ubuntu kernel .config and annotations +# Copyright © 2022 Canonical Ltd. + +import json +import re +import shutil +import tempfile +from abc import abstractmethod +from ast import literal_eval +from os.path import abspath, dirname + +from kconfig.version import ANNOTATIONS_FORMAT_VERSION + + +class Config: + def __init__(self, fname, do_include=True): + """ + Basic configuration file object + """ + self.fname = fname + self.config = {} + self.do_include = do_include + + raw_data = self._load(fname) + self._parse(raw_data) + + @staticmethod + def _load(fname: str) -> str: + with open(fname, "rt", encoding="utf-8") as fd: + data = fd.read() + return data.rstrip() + + def __str__(self): + """Return a JSON representation of the config""" + return json.dumps(self.config, indent=4) + + @abstractmethod + def _parse(self, data: str): + pass + + +class KConfig(Config): + """ + Parse a .config file, individual config options can be accessed via + .config[] + """ + + def _parse(self, data: str): + self.config = {} + for line in data.splitlines(): + m = re.match(r"^# (CONFIG_.*) is not set$", line) + if m: + self.config[m.group(1)] = literal_eval("'n'") + continue + m = re.match(r"^(CONFIG_[A-Za-z0-9_]+)=(.*)$", line) + if m: + self.config[m.group(1)] = literal_eval("'" + m.group(2) + "'") + continue + + +class Annotation(Config): + """ + Parse body of annotations file + """ + + def __init__(self, fname, do_include=True, do_json=False): + self.do_json = do_json + super().__init__(fname, do_include=True) + + def _parse_body(self, data: str, parent=True): + for line in data.splitlines(): + # Replace tabs with spaces, squeeze multiple into singles and + # remove leading and trailing spaces + line = line.replace("\t", " ") + line = re.sub(r" +", " ", line) + line = line.strip() + + # Ignore empty lines + if not line: + continue + + # Catpure flavors of included files + if line.startswith("# FLAVOUR: "): + self.include_flavour += line.split(" ")[2:] + continue + + # Ignore comments + if line.startswith("#"): + continue + + # Handle includes (recursively) + m = re.match(r'^include\s+"?([^"]*)"?', line) + if m: + if parent: + self.include.append(m.group(1)) + if self.do_include: + include_fname = dirname(abspath(self.fname)) + "/" + m.group(1) + include_data = self._load(include_fname) + self._parse_body(include_data, parent=False) + continue + + # Handle policy and note lines + if re.match(r".* (policy|note)<", line): + try: + conf = line.split(" ")[0] + if conf in self.config: + entry = self.config[conf] + else: + entry = {"policy": {}} + + match = False + m = re.match(r".* policy<(.*?)>", line) + if m: + match = True + # Update the previous entry considering potential overrides: + # - if the new entry is adding a rule for a new + # arch/flavour, simply add that + # - if the new entry is overriding a previous + # arch-flavour item, then overwrite that item + # - if the new entry is overriding a whole arch, then + # remove all the previous flavour rules of that arch + new_entry = literal_eval(m.group(1)) + for key in new_entry: + if key in self.arch: + for flavour_key in list(entry["policy"].keys()): + if flavour_key.startswith(key): + del entry["policy"][flavour_key] + entry["policy"][key] = new_entry[key] + else: + entry["policy"][key] = new_entry[key] + + m = re.match(r".* note<(.*?)>", line) + if m: + entry["oneline"] = match + match = True + entry["note"] = "'" + m.group(1).replace("'", "") + "'" + + if not match: + raise SyntaxError("syntax error") + self.config[conf] = entry + except Exception as e: + raise SyntaxError(str(e) + f", line = {line}") from e + continue + + # Invalid line + raise SyntaxError(f"invalid line: {line}") + + def _legacy_parse(self, data: str): + """ + Parse main annotations file, individual config options can be accessed + via self.config[] + """ + self.config = {} + self.arch = [] + self.flavour = [] + self.flavour_dep = {} + self.include = [] + self.header = "" + self.include_flavour = [] + + # Parse header (only main header will considered, headers in includes + # will be treated as comments) + for line in data.splitlines(): + if re.match(r"^#.*", line): + m = re.match(r"^# ARCH: (.*)", line) + if m: + self.arch = list(m.group(1).split(" ")) + m = re.match(r"^# FLAVOUR: (.*)", line) + if m: + self.flavour = list(m.group(1).split(" ")) + m = re.match(r"^# FLAVOUR_DEP: (.*)", line) + if m: + self.flavour_dep = literal_eval(m.group(1)) + self.header += line + "\n" + else: + break + + # Return an error if architectures are not defined + if not self.arch: + raise SyntaxError("ARCH not defined in annotations") + # Return an error if flavours are not defined + if not self.flavour: + raise SyntaxError("FLAVOUR not defined in annotations") + + # Parse body + self._parse_body(data) + + # Sanity check: Verify that all FLAVOUR_DEP flavors are valid + if self.do_include: + for src, tgt in self.flavour_dep.items(): + if src not in self.flavour: + raise SyntaxError(f"Invalid source flavour in FLAVOUR_DEP: {src}") + if tgt not in self.include_flavour: + raise SyntaxError(f"Invalid target flavour in FLAVOUR_DEP: {tgt}") + + def _json_parse(self, data, is_included=False): + data = json.loads(data) + + # Check if version is supported + version = data["attributes"]["_version"] + if version > ANNOTATIONS_FORMAT_VERSION: + raise SyntaxError(f"annotations format version {version} not supported") + + # Check for top-level annotations vs imported annotations + if not is_included: + self.config = data["config"] + self.arch = data["attributes"]["arch"] + self.flavour = data["attributes"]["flavour"] + self.flavour_dep = data["attributes"]["flavour_dep"] + self.include = data["attributes"]["include"] + self.include_flavour = [] + else: + # We are procesing an imported annotations, so merge all the + # configs and attributes. + try: + self.config = data["config"] | self.config + except TypeError: + self.config = {**self.config, **data["config"]} + self.arch = list(set(self.arch) | set(data["attributes"]["arch"])) + self.flavour = list(set(self.flavour) | set(data["attributes"]["flavour"])) + self.include_flavour = list(set(self.include_flavour) | set(data["attributes"]["flavour"])) + self.flavour_dep = self.flavour_dep | data["attributes"]["flavour_dep"] + + # Handle recursive inclusions + if self.do_include: + for f in data["attributes"]["include"]: + include_fname = dirname(abspath(self.fname)) + "/" + f + data = self._load(include_fname) + self._json_parse(data, is_included=True) + + def _parse(self, data: str): + if self.do_json: + self._json_parse(data, is_included=False) + else: + self._legacy_parse(data) + + def _remove_entry(self, config: str): + if self.config[config]: + del self.config[config] + + def remove(self, config: str, arch: str = None, flavour: str = None): + if config not in self.config: + return + if arch is not None: + if flavour is not None: + flavour = f"{arch}-{flavour}" + else: + flavour = arch + del self.config[config]["policy"][flavour] + if not self.config[config]["policy"]: + self._remove_entry(config) + else: + self._remove_entry(config) + + def set( + self, + config: str, + arch: str = None, + flavour: str = None, + value: str = None, + note: str = None, + ): + if value is not None: + if config not in self.config: + self.config[config] = {"policy": {}} + if arch is not None: + if flavour is not None: + flavour = f"{arch}-{flavour}" + else: + flavour = arch + self.config[config]["policy"][flavour] = value + else: + for a in self.arch: + self.config[config]["policy"][a] = value + if note is not None: + self.config[config]["note"] = "'" + note.replace("'", "") + "'" + + def update(self, c: KConfig, arch: str, flavour: str = None, configs: list = None): + """Merge configs from a Kconfig object into Annotation object""" + + # Determine if we need to import all configs or a single config + if not configs: + configs = c.config.keys() + try: + configs |= self.search_config(arch=arch, flavour=flavour).keys() + except TypeError: + configs = { + **configs, + **self.search_config(arch=arch, flavour=flavour).keys(), + } + + # Import configs from the Kconfig object into Annotations + flavour_arg = flavour + if flavour is not None: + flavour = arch + f"-{flavour}" + else: + flavour = arch + for conf in configs: + if conf in c.config: + val = c.config[conf] + else: + val = "-" + if conf in self.config: + if "policy" in self.config[conf]: + # Add a TODO if a config with a note is changing and print + # a warning + old_val = self.search_config(config=conf, arch=arch, flavour=flavour_arg) + if old_val: + old_val = old_val[conf] + if val != old_val and "note" in self.config[conf]: + self.config[conf]["note"] = "TODO: update note" + print(f"WARNING: {conf} changed from {old_val} to {val}, updating note") + self.config[conf]["policy"][flavour] = val + else: + self.config[conf]["policy"] = {flavour: val} + else: + self.config[conf] = {"policy": {flavour: val}} + + def _compact(self): + # Try to remove redundant settings: if the config value of a flavour is + # the same as the one of the main arch simply drop it. + for conf in self.config.copy(): + if "policy" not in self.config[conf]: + continue + for flavour in self.flavour: + if flavour not in self.config[conf]["policy"]: + continue + m = re.match(r"^(.*?)-(.*)$", flavour) + if not m: + continue + arch = m.group(1) + if arch in self.config[conf]["policy"]: + if self.config[conf]["policy"][flavour] == self.config[conf]["policy"][arch]: + del self.config[conf]["policy"][flavour] + continue + if flavour not in self.flavour_dep: + continue + generic = self.flavour_dep[flavour] + if generic in self.config[conf]["policy"]: + if self.config[conf]["policy"][flavour] == self.config[conf]["policy"][generic]: + del self.config[conf]["policy"][flavour] + continue + # Remove rules for flavours / arches that are not supported (not + # listed in the annotations header). + for flavour in self.config[conf]["policy"].copy(): + if flavour not in list(set(self.arch + self.flavour)): + del self.config[conf]["policy"][flavour] + # Remove configs that are all undefined across all arches/flavours + # (unless we have includes) + if not self.include: + if "policy" in self.config[conf]: + if list(set(self.config[conf]["policy"].values())) == ["-"]: + self.config[conf]["policy"] = {} + # Drop empty rules + if not self.config[conf]["policy"]: + del self.config[conf] + else: + # Compact same value across all flavour within the same arch + for arch in self.arch: + arch_flavours = [i for i in self.flavour if i.startswith(arch)] + value = None + for flavour in arch_flavours: + if flavour not in self.config[conf]["policy"]: + break + if value is None: + value = self.config[conf]["policy"][flavour] + elif value != self.config[conf]["policy"][flavour]: + break + else: + for flavour in arch_flavours: + del self.config[conf]["policy"][flavour] + self.config[conf]["policy"][arch] = value + # After the first round of compaction we may end up having configs that + # are undefined across all arches, so do another round of compaction to + # drop these settings that are not needed anymore + # (unless we have includes). + if not self.include: + for conf in self.config.copy(): + # Remove configs that are all undefined across all arches/flavours + if "policy" in self.config[conf]: + if list(set(self.config[conf]["policy"].values())) == ["-"]: + self.config[conf]["policy"] = {} + # Drop empty rules + if not self.config[conf]["policy"]: + del self.config[conf] + + @staticmethod + def _sorted(config): + """Sort configs alphabetically but return configs with a note first""" + w_note = [] + wo_note = [] + for c in sorted(config): + if "note" in config[c]: + w_note.append(c) + else: + wo_note.append(c) + return w_note + wo_note + + def save(self, fname: str): + """Save annotations data to the annotation file""" + # Compact annotations structure + self._compact() + + # Save annotations to disk + with tempfile.NamedTemporaryFile(mode="w+t", delete=False) as tmp: + # Write header + tmp.write(self.header + "\n") + + # Write includes + for i in self.include: + tmp.write(f'include "{i}"\n') + if self.include: + tmp.write("\n") + + # Write config annotations and notes + tmp.flush() + shutil.copy(tmp.name, fname) + tmp_a = Annotation(fname) + + # Only save local differences (preserve includes) + marker = False + for conf in self._sorted(self.config): + new_val = self.config[conf] + if "policy" not in new_val: + continue + + # If new_val is a subset of old_val, skip it unless there are + # new notes that are different than the old ones. + old_val = tmp_a.config.get(conf) + if old_val and "policy" in old_val: + try: + can_skip = old_val["policy"] == old_val["policy"] | new_val["policy"] + except TypeError: + can_skip = old_val["policy"] == { + **old_val["policy"], + **new_val["policy"], + } + if can_skip: + if "note" not in new_val: + continue + if "note" in old_val and "note" in new_val: + if old_val["note"] == new_val["note"]: + continue + + # Write out the policy (and note) line(s) + val = dict(sorted(new_val["policy"].items())) + line = f"{conf: <47} policy<{val}>" + if "note" in new_val: + val = new_val["note"] + if new_val.get("oneline", False): + # Single line + line += f" note<{val}>" + else: + # Separate policy and note lines, + # followed by an empty line + line += f"\n{conf: <47} note<{val}>\n" + elif not marker: + # Write out a marker indicating the start of annotations + # without notes + tmp.write("\n# ---- Annotations without notes ----\n\n") + marker = True + tmp.write(line + "\n") + + # Replace annotations with the updated version + tmp.flush() + shutil.move(tmp.name, fname) + + def search_config(self, config: str = None, arch: str = None, flavour: str = None) -> dict: + """Return config value of a specific config option or architecture""" + if flavour is None: + flavour = "generic" + flavour = f"{arch}-{flavour}" + if flavour in self.flavour_dep: + generic = self.flavour_dep[flavour] + else: + generic = flavour + if config is None and arch is None: + # Get all config options for all architectures + return self.config + if config is None and arch is not None: + # Get config options of a specific architecture + ret = {} + for c, val in self.config.items(): + if "policy" not in val: + continue + if flavour in val["policy"]: + ret[c] = val["policy"][flavour] + elif generic != flavour and generic in val["policy"]: + ret[c] = val["policy"][generic] + elif arch in val["policy"]: + ret[c] = val["policy"][arch] + return ret + if config is not None and arch is None: + # Get a specific config option for all architectures + return self.config[config] if config in self.config else None + if config is not None and arch is not None: + # Get a specific config option for a specific architecture + if config in self.config: + if "policy" in self.config[config]: + if flavour in self.config[config]["policy"]: + return {config: self.config[config]["policy"][flavour]} + if generic != flavour and generic in self.config[config]["policy"]: + return {config: self.config[config]["policy"][generic]} + if arch in self.config[config]["policy"]: + return {config: self.config[config]["policy"][arch]} + return None + + @staticmethod + def to_config(data: dict) -> str: + """Convert annotations data to .config format""" + s = "" + for c in data: + v = data[c] + if v == "n": + s += f"# {c} is not set\n" + elif v == "-": + pass + else: + s += f"{c}={v}\n" + return s.rstrip() --- linux-nvidia-7.0.0.orig/debian/scripts/misc/kconfig/run.py +++ linux-nvidia-7.0.0/debian/scripts/misc/kconfig/run.py @@ -0,0 +1,375 @@ +# -*- mode: python -*- +# Manage Ubuntu kernel .config and annotations +# Copyright © 2022 Canonical Ltd. + +import argparse +import json +import os +import sys +from signal import SIG_DFL, SIGPIPE, signal + +try: + from argcomplete import autocomplete +except ModuleNotFoundError: + # Allow to run this program also when argcomplete is not available + def autocomplete(_unused): + pass + + +from kconfig.annotations import Annotation, KConfig # noqa: E402 Import not at top of file +from kconfig.utils import arg_fail, autodetect_annotations # noqa: E402 Import not at top of file +from kconfig.version import ANNOTATIONS_FORMAT_VERSION, VERSION # noqa: E402 Import not at top of file + +SKIP_CONFIGS = ( + # CONFIG_VERSION_SIGNATURE is dynamically set during the build + "CONFIG_VERSION_SIGNATURE", + # Allow to use a different versions of toolchain tools + "CONFIG_GCC_VERSION", + "CONFIG_CC_VERSION_TEXT", + "CONFIG_AS_VERSION", + "CONFIG_LD_VERSION", + "CONFIG_LLD_VERSION", + "CONFIG_CLANG_VERSION", + "CONFIG_PAHOLE_VERSION", + "CONFIG_RUSTC_VERSION_TEXT", + "CONFIG_BINDGEN_VERSION_TEXT", +) + + +def removeprefix(data, prefix): + if data[: len(prefix)] == prefix: + data = data[len(prefix) :] + return data + + +def make_parser(): + parser = argparse.ArgumentParser( + description="Manage Ubuntu kernel .config and annotations", + ) + parser.add_argument("--version", "-v", action="version", version=f"%(prog)s {VERSION}") + + parser.add_argument( + "--file", + "-f", + action="store", + help="Pass annotations or .config file to be parsed", + ) + parser.add_argument("--arch", "-a", action="store", help="Select architecture") + parser.add_argument("--flavour", "-l", action="store", help='Select flavour (default is "generic")') + parser.add_argument("--config", "-c", action="store", help="Select a specific config option") + parser.add_argument("--query", "-q", action="store_true", help="Query annotations") + parser.add_argument( + "--note", + "-n", + action="store", + help="Write a specific note to a config option in annotations", + ) + parser.add_argument( + "--autocomplete", + action="store_true", + help="Enable config bash autocomplete: `source <(annotations --autocomplete)`", + ) + parser.add_argument( + "--source", + "-t", + action="store_true", + help="Jump to a config definition in the kernel source code", + ) + parser.add_argument( + "--no-include", + action="store_true", + help="Do not process included annotations (stop at the main file)", + ) + parser.add_argument( + "--json", + action="store_true", + help="Try to parse annotations file in pure JSON format", + ) + + ga = parser.add_argument_group(title="Action").add_mutually_exclusive_group(required=False) + ga.add_argument( + "--write", + "-w", + action="store", + metavar="VALUE", + dest="value", + help="Set a specific config value in annotations (use 'null' to remove)", + ) + ga.add_argument( + "--export", + "-e", + action="store_true", + help="Convert annotations to .config format", + ) + ga.add_argument( + "--import", + "-i", + action="store", + metavar="FILE", + dest="import_file", + help="Import a full .config for a specific arch and flavour into annotations", + ) + ga.add_argument( + "--update", + "-u", + action="store", + metavar="FILE", + dest="update_file", + help="Import a partial .config into annotations (only resync configs specified in FILE)", + ) + ga.add_argument( + "--check", + "-k", + action="store", + metavar="FILE", + dest="check_file", + help="Validate kernel .config with annotations", + ) + return parser + + +_ARGPARSER = make_parser() + + +def export_result(data): + # Dump metadata / attributes first + out = '{\n "attributes": {\n' + for key, value in sorted(data["attributes"].items()): + out += f' "{key}": {json.dumps(value)},\n' + out = out.rstrip(",\n") + out += "\n }," + print(out) + + configs_with_note = {key: value for key, value in data["config"].items() if "note" in value} + configs_without_note = {key: value for key, value in data["config"].items() if "note" not in value} + + # Dump configs, sorted alphabetically, showing items with a note first + out = ' "config": {\n' + for key in sorted(configs_with_note) + sorted(configs_without_note): + policy = data["config"][key]["policy"] + if "note" in data["config"][key]: + note = data["config"][key]["note"] + out += f' "{key}": {{"policy": {json.dumps(policy)}, "note": {json.dumps(note)}}},\n' + else: + out += f' "{key}": {{"policy": {json.dumps(policy)}}},\n' + out = out.rstrip(",\n") + out += "\n }\n}" + print(out) + + +def print_result(config, data): + if data is not None and config is not None and config not in data: + data = {config: data} + print(json.dumps(data, sort_keys=True, indent=2)) + + +def do_query(args): + if args.arch is None and args.flavour is not None: + arg_fail(_ARGPARSER, "error: --flavour requires --arch") + a = Annotation(args.file, do_include=(not args.no_include), do_json=args.json) + res = a.search_config(config=args.config, arch=args.arch, flavour=args.flavour) + # If no arguments are specified dump the whole annotations structure + if args.config is None and args.arch is None and args.flavour is None: + res = { + "attributes": { + "arch": a.arch, + "flavour": a.flavour, + "flavour_dep": a.flavour_dep, + "include": a.include, + "_version": ANNOTATIONS_FORMAT_VERSION, + }, + "config": res, + } + export_result(res) + else: + print_result(args.config, res) + + +def do_autocomplete(args): + a = Annotation(args.file) + res = (removeprefix(c, "CONFIG_") for c in a.search_config()) + res_str = " ".join(res) + print(f'complete -W "{res_str}" annotations') + + +def do_source(args): + if args.config is None: + arg_fail(_ARGPARSER, "error: --source requires --config") + if not os.path.exists("tags"): + print("tags not found in the current directory, try: `make tags`") + sys.exit(1) + os.system(f"vim -t {args.config}") + + +def do_note(args): + if args.config is None: + arg_fail(_ARGPARSER, "error: --note requires --config") + + # Set the note in annotations + a = Annotation(args.file) + a.set(args.config, note=args.note) + + # Save back to annotations + a.save(args.file) + + # Query and print back the value + a = Annotation(args.file) + res = a.search_config(config=args.config) + print_result(args.config, res) + + +def do_write(args): + if args.config is None: + arg_fail(_ARGPARSER, "error: --write requires --config") + + # Set the value in annotations ('null' means remove) + a = Annotation(args.file) + if args.value == "null": + a.remove(args.config, arch=args.arch, flavour=args.flavour) + else: + a.set( + args.config, + arch=args.arch, + flavour=args.flavour, + value=args.value, + note=args.note, + ) + + # Save back to annotations + a.save(args.file) + + # Query and print back the value + a = Annotation(args.file) + res = a.search_config(config=args.config) + print_result(args.config, res) + + +def do_export(args): + if args.arch is None: + arg_fail(_ARGPARSER, "error: --export requires --arch") + a = Annotation(args.file) + conf = a.search_config(config=args.config, arch=args.arch, flavour=args.flavour) + if conf: + print(a.to_config(conf)) + + +def do_import(args): + if args.arch is None: + arg_fail(_ARGPARSER, "error: --arch is required with --import") + if args.flavour is None: + arg_fail(_ARGPARSER, "error: --flavour is required with --import") + if args.config is not None: + arg_fail(_ARGPARSER, "error: --config cannot be used with --import (try --update)") + + # Merge with the current annotations + a = Annotation(args.file) + c = KConfig(args.import_file) + a.update(c, arch=args.arch, flavour=args.flavour) + + # Save back to annotations + a.save(args.file) + + +def do_update(args): + if args.arch is None: + arg_fail(_ARGPARSER, "error: --arch is required with --update") + + # Merge with the current annotations + a = Annotation(args.file) + c = KConfig(args.update_file) + if args.config is None: + configs = list(set(c.config.keys()) - set(SKIP_CONFIGS)) + if configs: + a.update(c, arch=args.arch, flavour=args.flavour, configs=configs) + + # Save back to annotations + a.save(args.file) + + +def do_check(args): + # Determine arch and flavour + if args.arch is None: + arg_fail(_ARGPARSER, "error: --arch is required with --check") + + print(f"check-config: loading annotations from {args.file}") + total = good = ret = 0 + + # Load annotations settings + a = Annotation(args.file) + a_configs = a.search_config(arch=args.arch, flavour=args.flavour).keys() + + # Parse target .config + c = KConfig(args.check_file) + c_configs = c.config.keys() + + # Validate .config against annotations + for conf in sorted(a_configs | c_configs): + if conf in SKIP_CONFIGS: + continue + entry = a.search_config(config=conf, arch=args.arch, flavour=args.flavour) + expected = entry[conf] if entry else "-" + value = c.config[conf] if conf in c.config else "-" + if value != expected: + policy = a.config[conf] if conf in a.config else "undefined" + if "policy" in policy: + policy = f"policy<{policy['policy']}>" + print(f"check-config: {conf} changed from {expected} to {value}: {policy})") + ret = 1 + else: + good += 1 + total += 1 + + num = total - good + if ret: + if os.path.exists(".git"): + print(f"check-config: {num} config options have been changed, review them with `git diff`") + else: + print(f"check-config: {num} config options have changed") + else: + print("check-config: all good") + sys.exit(ret) + + +def main(): + # Prevent broken pipe errors when showing output in pipe to other tools + # (less for example) + signal(SIGPIPE, SIG_DFL) + + # Main annotations program + autocomplete(_ARGPARSER) + args = _ARGPARSER.parse_args() + + if args.file is None: + args.file = autodetect_annotations() + if args.file is None: + arg_fail( + _ARGPARSER, + "error: could not determine DEBDIR, try using: --file/-f", + show_usage=False, + ) + + if args.config and not args.config.startswith("CONFIG_"): + args.config = "CONFIG_" + args.config + + if args.value: + do_write(args) + elif args.note: + do_note(args) + elif args.export: + do_export(args) + elif args.import_file: + do_import(args) + elif args.update_file: + do_update(args) + elif args.check_file: + do_check(args) + elif args.autocomplete: + do_autocomplete(args) + elif args.source: + do_source(args) + else: + do_query(args) + + +if __name__ == "__main__": + main() --- linux-nvidia-7.0.0.orig/debian/scripts/misc/kconfig/utils.py +++ linux-nvidia-7.0.0/debian/scripts/misc/kconfig/utils.py @@ -0,0 +1,20 @@ +# -*- mode: python -*- +# Misc helpers for Kconfig and annotations +# Copyright © 2023 Canonical Ltd. + +import sys + + +def autodetect_annotations(): + try: + with open("debian/debian.env", "rt", encoding="utf-8") as fd: + return fd.read().rstrip().split("=")[1] + "/config/annotations" + except (FileNotFoundError, IndexError): + return None + + +def arg_fail(parser, message, show_usage=True): + print(message) + if show_usage: + parser.print_usage() + sys.exit(1) --- linux-nvidia-7.0.0.orig/debian/scripts/misc/kconfig/version.py +++ linux-nvidia-7.0.0/debian/scripts/misc/kconfig/version.py @@ -0,0 +1,10 @@ +# -*- mode: python -*- +# version of annotations module +# Copyright © 2022 Canonical Ltd. + +VERSION = "0.1" + +ANNOTATIONS_FORMAT_VERSION = 5 + +if __name__ == "__main__": + print(VERSION) --- linux-nvidia-7.0.0.orig/debian/scripts/misc/kernelconfig +++ linux-nvidia-7.0.0/debian/scripts/misc/kernelconfig @@ -0,0 +1,178 @@ +#!/bin/bash -u +# +# Manage kernel config annotations +# +# Supported environment variales: +# conc_level : Concurrency level for upstream make (-jX) +# skip_checks : Skip config checks if set to 'true' +# gcc : Default gcc to use (mandatory) +# + +function cleanup() +{ + rm -rf build "${TMP_DIR}" +} + +# We have to be in the top level Ubuntu kernel source directory +if ! [ -e debian/debian.env ] ; then + echo "ERROR: This is not an Ubuntu kernel source directory" >&2 + exit 1 +fi + +if [ -z "${gcc:-}" ] ; then + echo "ERROR: 'gcc' environment variable must be set" >&2 + exit 1 +fi + +if [ ${#} -ne 1 ] ; then + echo "Usage: $0 updateconfigs|defaultconfigs|genconfigs|editconfigs" + exit 2 +fi + +mode=${1} + +case "${mode}" in + updateconfigs) target="syncconfig" ;; + defaultconfigs) target="olddefconfig" ;; + genconfigs) target="oldconfig" ;; + editconfigs) ;; # Target is set later based on user input + *) echo "ERROR: Invalid mode: ${1}" >&2 + exit 1 ;; +esac + +. debian/debian.env + +annotations_file=${DEBIAN}/config/annotations +warning_partial=() + +TMP_DIR=$(mktemp -d) +trap cleanup EXIT + +# Use annotations to generate configs +FLAVOURS=$(sed -ne 's/^# FLAVOUR: //p' "${annotations_file}") + +for arch_flavour in ${FLAVOURS} ; do + arch=${arch_flavour%%-*} + flavour=${arch_flavour#*-} + tmp_conf_file=${TMP_DIR}/${arch}-config.flavour.${flavour} + + # Map debian archs to kernel archs + case "${arch}" in + amd64) kern_arch="x86_64" ;; + arm64) kern_arch="arm64" ;; + armhf) kern_arch="arm" ;; + ppc64el) kern_arch="powerpc" ;; + riscv64) kern_arch="riscv" ;; + s390x) kern_arch="s390" ;; + *) echo "WARNING: Unsupported architecture: ${arch}" + warning_partial+=("${arch}") + continue ;; + esac + + # Determine cross toolchain to use for Kconfig compiler tests + cross_compile="$(dpkg-architecture -qDEB_HOST_GNU_TYPE -a"${arch}" 2>/dev/null)-" + + # Arch-specific compiler, if any + arch_gcc=$(cat < build/.config + + # Environment variables for 'make *config' + env=(ARCH="${kern_arch}" + DEB_ARCH="${arch}" + CROSS_COMPILE="${cross_compile}" + CC="${gcc_path}") + + # Concurrency level + if [ -n "${conc_level:-}" ] ; then + env+=("${conc_level}") + fi + + # Call config target + echo + echo "* Run ${target} on ${arch}/${flavour} ..." + ${kmake} O=build "${env[@]}" "${target}" + + # Move config for further processing + mv build/.config "${tmp_conf_file}" +done + +rc=0 + +if [ "${skip_checks:-}" = "true" ] ; then + echo + echo "Skipping config-check (skip_checks=${skip_checks}) ..." +else + echo + echo "Running config-check for all configurations ..." + fail=0 + for arch_flavour in ${FLAVOURS} ; do + arch=${arch_flavour%%-*} + flavour=${arch_flavour#*-} + tmp_conf_file=${TMP_DIR}/${arch}-config.flavour.${flavour} + + echo + echo "* Run config-check for ${arch}-${flavour} ..." + python3 debian/scripts/misc/annotations -f "${annotations_file}" \ + --arch "${arch}" --flavour "${flavour}" --check "${tmp_conf_file}" || \ + fail=$((fail + 1)) + done + + if [ ${fail} -gt 0 ] ; then + rc=1 + echo "ERROR: ${fail} config-check failures detected" >&2 + fi +fi + +if [ ${#warning_partial[@]} -gt 0 ] ; then + rc=1 + echo "ERROR: Config operation not applied to all architectures (skipped ${warning_partial[*]})" >&2 +fi + +# Recreate the annotations file +if [ "${mode}" = "genconfigs" ] ; then + rm -rf CONFIGS + mv "${TMP_DIR}" CONFIGS +else + echo + echo "Importing all configurations ..." + echo + for arch_flavour in ${FLAVOURS} ; do + arch=${arch_flavour%%-*} + flavour=${arch_flavour#*-} + tmp_conf_file=${TMP_DIR}/${arch}-config.flavour.${flavour} + + echo "* Import configs for ${arch}-${flavour} ..." + python3 debian/scripts/misc/annotations -f "${annotations_file}" \ + --arch "${arch}" --flavour "${flavour}" --import "${tmp_conf_file}" + done +fi + +exit "${rc}" --- linux-nvidia-7.0.0.orig/debian/scripts/sign-module +++ linux-nvidia-7.0.0/debian/scripts/sign-module @@ -0,0 +1,40 @@ +#!/bin/bash -eu +# +# Staging drivers must not be signed if they are not listed in a +# signature-inclusion file to prevent loading of 'unsafe' drivers in a +# Secure Boot environment. +# +# Exit with status 0 if the provided module needs to be signed, 1 otherwise +# + +mod=${1} + +# Sign the module if not a staging driver +if [ "${mod/\/drivers\/staging\//}" = "${mod}" ] ; then + exit 0 +fi + +root=$(dirname "$(realpath -e "${0}")")/../.. +. "${root}"/debian/debian.env + +# Collect the signature-inclusion files +sig_incls=() +for d in debian "${DEBIAN}" ; do + if [ -f "${root}"/"${d}"/signature-inclusion ] ; then + sig_incls+=("${root}"/"${d}"/signature-inclusion) + fi +done + +# Sign the module if no signature-inclusion files +if [ ${#sig_incls[@]} -eq 0 ] ; then + exit 0 +fi + +# Sign the module if listed in signature-inclusion files +if grep -qFx "${mod##*/}" "${sig_incls[@]}" ; then + exit 0 +fi + +# Don't sign the module +echo "UBUNTU: Not signing ${1}" +exit 1 --- linux-nvidia-7.0.0.orig/debian/scripts/ubuntu-compatible-signing +++ linux-nvidia-7.0.0/debian/scripts/ubuntu-compatible-signing @@ -0,0 +1,7 @@ +#!/bin/sh + +echo $( + grep -qx ' *Subject: C = GB, ST = Isle of Man, O = Canonical Ltd., OU = Secure Boot, CN = Canonical Ltd. Secure Boot Signing (2021 v3)' debian/canonical-revoked-certs.pem && echo ubuntu/4 pro/3 + grep -qx ' *Subject: CN=Canonical Ltd. Live Patch Signing 2025 Kmod' debian/canonical-certs.pem && echo livepatch:2025 + grep -qx ' *Subject: CN=Canonical Ltd. Kernel Module Signing 2025 Kmod' debian/canonical-certs.pem && echo kmod:2025 +) --- linux-nvidia-7.0.0.orig/debian/signature-inclusion +++ linux-nvidia-7.0.0/debian/signature-inclusion @@ -0,0 +1,4 @@ +# +# This file lists the staging drivers that are safe for signing +# and loading in a secure boot environment with signed module enforcement. +# --- linux-nvidia-7.0.0.orig/debian/snapcraft.mk +++ linux-nvidia-7.0.0/debian/snapcraft.mk @@ -0,0 +1,11 @@ +ifeq ($(ARCH),) + arch := $(shell uname -m | sed -e s/i.86/i386/ -e s/x86_64/amd64/ \ + -e s/arm.*/armhf/ -e s/s390/s390x/ -e s/ppc.*/powerpc/ \ + -e s/aarch64.*/arm64/ ) +else ifeq ($(ARCH),arm) + arch := armhf +else + arch := $(ARCH) +endif +config: + python3 debian/scripts/misc/annotations --export --arch $(arch) --flavour $(flavour) >.config --- linux-nvidia-7.0.0.orig/debian/source/format +++ linux-nvidia-7.0.0/debian/source/format @@ -0,0 +1 @@ +1.0 --- linux-nvidia-7.0.0.orig/debian/source/options +++ linux-nvidia-7.0.0/debian/source/options @@ -0,0 +1,9 @@ +# Ignore vbox symlinks, we will regenerate these at clean (LP:1426113) +## autoreconstruct -- begin +# Ignore any symlinks created since the orig which are rebuilt by reconstruct. +extend-diff-ignore=^ubuntu/igh-ecat/master/rtdm-ioctl.c$ +## autoreconstruct -- end + +# force "dpkg-source -I -i" behavior +diff-ignore +tar-ignore --- linux-nvidia-7.0.0.orig/debian/substvars +++ linux-nvidia-7.0.0/debian/substvars @@ -0,0 +1,2 @@ +linux:rprovides=spl-modules, spl-dkms, zfs-modules, zfs-dkms, v4l2loopback-modules, v4l2loopback-dkms, + --- linux-nvidia-7.0.0.orig/debian/templates/extra.postinst.in +++ linux-nvidia-7.0.0/debian/templates/extra.postinst.in @@ -0,0 +1,20 @@ +#!/bin/sh +set -e + +version=@abiname@@localversion@ +image_path=/boot/@image-stem@-$version + +if [ "$1" != configure ]; then + exit 0 +fi + +depmod -a -F /boot/System.map-$version $version || true +if [ -d /etc/kernel/postinst.d ] || [ -d /usr/share/kernel/postinst.d ]; then + cat - >/usr/lib/linux/triggers/$version </dev/null || true +# +# We should be rebuilding the initramfs here on removal to pare down the +# initramfs if it contains any of the objects we just removed. But people +# commonly remove kernels in order to free space in /boot, and rebuilding the +# initramfs now risks ENOSPC when we are trying to make space. The files we +# leave lying about could be confusing, but we trade that against safety on +# removal. +# +#if [ -d /etc/kernel/postinst.d ] || [ -d /usr/share/kernel/postinst.d ]; then +# # We want to behave as if linux-image (without us) was installed, therefore +# # we do not want the postinst support to know we are being removed, claim +# # this is an installation event. +# cat - >/usr/lib/linux/triggers/$version </usr/lib/linux/triggers/$version </dev/null; then + linux-update-symlinks remove $version $image_path +fi + +if [ -d /etc/kernel/postrm.d ] || [ -d /usr/share/kernel/postrm.d ]; then + # We cannot trigger ourselves as at the end of this we will no longer + # exist and can no longer respond to the trigger. The trigger would + # then become lost. Therefore we clear any pending trigger and apply + # postrm directly. + if [ -f /usr/lib/linux/triggers/$version ]; then + echo "$0 ... removing pending trigger" + rm -f /usr/lib/linux/triggers/$version + fi + DEB_MAINT_PARAMS="$*" run-parts --report --exit-on-error --arg=$version \ + --arg=$image_path /etc/kernel/postrm.d /usr/share/kernel/postrm.d +fi + +if [ "$1" = purge ]; then + for extra_file in modules.dep modules.isapnpmap modules.pcimap \ + modules.usbmap modules.parportmap \ + modules.generic_string modules.ieee1394map \ + modules.ieee1394map modules.pnpbiosmap \ + modules.alias modules.ccwmap modules.inputmap \ + modules.symbols modules.ofmap \ + modules.seriomap modules.\*.bin \ + modules.softdep modules.weakdep modules.devname; do + eval rm -f /usr/lib/modules/$version/$extra_file + done + rmdir /usr/lib/modules/$version || true +fi + +exit 0 --- linux-nvidia-7.0.0.orig/debian/templates/image.preinst.in +++ linux-nvidia-7.0.0/debian/templates/image.preinst.in @@ -0,0 +1,22 @@ +#!/bin/sh +set -e + +version=@abiname@@localversion@ +image_path=/boot/@image-stem@-$version + +if [ "$1" = abort-upgrade ]; then + exit 0 +fi + +if [ "$1" = install ]; then + # Create a flag file for postinst + mkdir -p /usr/lib/modules/$version + touch /usr/lib/modules/$version/.fresh-install +fi + +if [ -d /etc/kernel/preinst.d ] || [ -d /usr/share/kernel/preinst.d ]; then + DEB_MAINT_PARAMS="$*" run-parts --report --exit-on-error --arg=$version \ + --arg=$image_path /etc/kernel/preinst.d /usr/share/kernel/preinst.d +fi + +exit 0 --- linux-nvidia-7.0.0.orig/debian/templates/image.prerm.in +++ linux-nvidia-7.0.0/debian/templates/image.prerm.in @@ -0,0 +1,18 @@ +#!/bin/sh +set -e + +version=@abiname@@localversion@ +image_path=/boot/@image-stem@-$version + +if [ "$1" != remove ]; then + exit 0 +fi + +linux-check-removal $version + +if [ -d /etc/kernel/prerm.d ] || [ -d /usr/share/kernel/prerm.d ]; then + DEB_MAINT_PARAMS="$*" run-parts --report --exit-on-error --arg=$version \ + --arg=$image_path /etc/kernel/prerm.d /usr/share/kernel/prerm.d +fi + +exit 0 --- linux-nvidia-7.0.0.orig/debian/tests/control +++ linux-nvidia-7.0.0/debian/tests/control @@ -0,0 +1,7 @@ +Tests: rebuild +Depends: @builddeps@, fakeroot +Restrictions: allow-stderr, skippable + +Tests: ubuntu-regression-suite +Depends: build-essential, fakeroot, gcc-multilib [amd64 armhf i386], gdb, git, python3, snapd, fuse-overlayfs +Restrictions: allow-stderr, isolation-machine, breaks-testbed, skippable --- linux-nvidia-7.0.0.orig/debian/tests/rebuild +++ linux-nvidia-7.0.0/debian/tests/rebuild @@ -0,0 +1,20 @@ +#!/bin/sh + +# If we are triggering for just linux or linux-meta we know we have +# just built the kernel and there is no point in repeating that +# build, it just wastes time. (LP: #1498862) +build_needed=0 +for trigger in ${ADT_TEST_TRIGGERS:-force} +do + case "$trigger" in + linux/*|linux-lts-*/*|linux-meta*/*|linux-oem*/*|fakeroot/*|gdb/*|git/*|bzr/*|gcc-multilib/*) ;; + *) build_needed=1 ;; + esac +done +if [ "$build_needed" -eq 0 ]; then + echo "rebuild: short circuiting build for '${ADT_TEST_TRIGGERS}'" + exit 77 +fi + +set -e +dpkg-buildpackage -rfakeroot -us -uc -b -Pautopkgtest --- linux-nvidia-7.0.0.orig/debian/tests/ubuntu-regression-suite +++ linux-nvidia-7.0.0/debian/tests/ubuntu-regression-suite @@ -0,0 +1,46 @@ +#!/bin/sh +set -e + +# Only run regression-suite on kernels we can boot in canonistack +source=`dpkg-parsechangelog -SSource` +case $source in + linux|linux-unstable|linux-hwe*|linux-lowlatency*|linux-kvm|linux-oem) + ;; + *) + echo "ubuntu-regression-suite is pointless, if one cannot boot the kernel" + exit 77 + ;; +esac + +# Only run regression-suite if we were requested to +have_meta=0 +for trigger in ${ADT_TEST_TRIGGERS} +do + case "$trigger" in + linux-meta/*|linux-meta-*/*) + have_meta=1 + ;; + esac +done +if [ -n "$ADT_TEST_TRIGGERS" ] && [ "$have_meta" -eq 0 ]; then + echo "ubuntu-regression-suite is not requested, as there is no linux-meta trigger" + exit 77 +fi + +sver=`dpkg-parsechangelog -SVersion` +read x rver x &2 + exit 1 +fi + +git clone --depth=1 -b autotest3 https://git.launchpad.net/~canonical-kernel-team/+git/kernel-testing +git -C kernel-testing/ show HEAD -q +kernel-testing/run-dep8-tests --- linux-nvidia-7.0.0.orig/debian/tools/generic +++ linux-nvidia-7.0.0/debian/tools/generic @@ -0,0 +1,60 @@ +#!/bin/bash +full_version=`uname -r` + +# First check for a fully qualified version. +this="/usr/lib/linux-tools/$full_version/`basename $0`" +if [ -f "$this" ]; then + exec "$this" "$@" +fi + +# Removing flavour from version i.e. generic or server. +flavour_abi=${full_version#*-} +flavour=${flavour_abi#*-} +version=${full_version%-$flavour} +this="$0_$version" +if [ -f "$this" ]; then + exec "$this" "$@" +fi + +# Before saucy kernels we had no flavour linkage. +if dpkg --compare-versions "$version" lt "3.11.0"; then + flavour='' +else + flavour="-$flavour" +fi +# Hint at the cloud tools if they exist (trusty and later) +if dpkg --compare-versions "$version" ge "3.13.0"; then + cld="" +else + cld=":" +fi +# Work out if this is an LTS backport or not. +codename=`lsb_release -cs` +case "$codename" in +precise) base='3.2.0-9999' ;; +trusty) base='3.13.0-9999' ;; +*) base='' ;; +esac +std="" +lts=":" +if [ "$base" != "" ]; then + if dpkg --compare-versions "$version" gt "$base"; then + std=":" + lts="" + fi +fi + +# Give them a hint as to what to install. + echo "WARNING: `basename $0` not found for kernel $version" >&2 + echo "" >&2 + echo " You may need to install the following packages for this specific kernel:" >&2 + echo " linux-tools-$version$flavour" >&2 +$cld echo " linux-cloud-tools-$version$flavour" >&2 + echo "" >&2 + echo " You may also want to install one of the following packages to keep up to date:" >&2 +$std echo " linux-tools$flavour" >&2 +$std $cld echo " linux-cloud-tools$flavour" >&2 +$lts echo " linux-tools$flavour-lts-" >&2 +$lts $cld echo " linux-cloud-tools$flavour-lts-" >&2 + +exit 2 --- linux-nvidia-7.0.0.orig/debian/v4l2loopback-modules.ignore +++ linux-nvidia-7.0.0/debian/v4l2loopback-modules.ignore @@ -0,0 +1 @@ +v4l2loopback --- linux-nvidia-7.0.0.orig/debian/zfs-modules.ignore +++ linux-nvidia-7.0.0/debian/zfs-modules.ignore @@ -0,0 +1,11 @@ +icp +spl +splat +zavl +zcommon +zfs +zlua +znvpair +zpios +zunicode +zzstd --- linux-nvidia-7.0.0.orig/drivers/Makefile +++ linux-nvidia-7.0.0/drivers/Makefile @@ -64,14 +64,9 @@ # iommu/ comes before gpu as gpu are using iommu controllers obj-y += iommu/ -# gpu/ comes after char for AGP vs DRM startup and after iommu -obj-y += gpu/ obj-$(CONFIG_CONNECTOR) += connector/ -# i810fb depends on char/agp/ -obj-$(CONFIG_FB_I810) += video/fbdev/i810/ - obj-$(CONFIG_PARPORT) += parport/ obj-y += base/ block/ misc/ mfd/ nfc/ obj-$(CONFIG_LIBNVDIMM) += nvdimm/ @@ -83,6 +78,11 @@ obj-y += scsi/ obj-y += nvme/ obj-$(CONFIG_ATA) += ata/ + +# gpu/ comes after char for AGP vs DRM startup and after iommu +obj-y += gpu/ +# i810fb depends on char/agp/ +obj-$(CONFIG_FB_I810) += video/fbdev/i810/ obj-$(CONFIG_TARGET_CORE) += target/ obj-$(CONFIG_MTD) += mtd/ obj-$(CONFIG_SPI) += spi/ --- linux-nvidia-7.0.0.orig/drivers/accel/amdxdna/aie2_pci.c +++ linux-nvidia-7.0.0/drivers/accel/amdxdna/aie2_pci.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -791,6 +792,52 @@ return ret; } +static int aie2_get_sensors(struct amdxdna_client *client, + struct amdxdna_drm_get_info *args) +{ + struct amdxdna_dev_hdl *ndev = client->xdna->dev_handle; + struct amdxdna_drm_query_sensor sensor = {}; + struct amd_pmf_npu_metrics npu_metrics; + u32 sensors_count, util_count, i; + int ret; + + util_count = min_t(u32, ndev->total_col, 8); + sensors_count = 1 + util_count; + + if (args->buffer_size < sensors_count * sizeof(sensor)) + return -EINVAL; + + ret = AIE2_GET_PMF_NPU_METRICS(&npu_metrics); + if (ret) + return ret; + + sensor.type = AMDXDNA_SENSOR_TYPE_POWER; + sensor.input = npu_metrics.npu_power; + sensor.unitm = -3; + scnprintf(sensor.label, sizeof(sensor.label), "Total Power"); + scnprintf(sensor.units, sizeof(sensor.units), "mW"); + + if (copy_to_user(u64_to_user_ptr(args->buffer), &sensor, sizeof(sensor))) + return -EFAULT; + + for (i = 0; i < util_count; i++) { + memset(&sensor, 0, sizeof(sensor)); + sensor.input = npu_metrics.npu_busy[i]; + sensor.type = AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION; + sensor.unitm = 0; + scnprintf(sensor.label, sizeof(sensor.label), "Column %d Utilization", i); + scnprintf(sensor.units, sizeof(sensor.units), "%%"); + + if (copy_to_user(u64_to_user_ptr(args->buffer) + (i + 1) * sizeof(sensor), + &sensor, sizeof(sensor))) + return -EFAULT; + } + + args->buffer_size = sensors_count * sizeof(sensor); + + return 0; +} + static int aie2_hwctx_status_cb(struct amdxdna_hwctx *hwctx, void *arg) { struct amdxdna_drm_hwctx_entry *tmp __free(kfree) = NULL; @@ -994,6 +1041,9 @@ case DRM_AMDXDNA_QUERY_CLOCK_METADATA: ret = aie2_get_clock_metadata(client, args); break; + case DRM_AMDXDNA_QUERY_SENSORS: + ret = aie2_get_sensors(client, args); + break; case DRM_AMDXDNA_QUERY_HW_CONTEXTS: ret = aie2_get_hwctx_status(client, args); break; --- linux-nvidia-7.0.0.orig/drivers/accel/amdxdna/aie2_pci.h +++ linux-nvidia-7.0.0/drivers/accel/amdxdna/aie2_pci.h @@ -7,6 +7,7 @@ #define _AIE2_PCI_H_ #include +#include #include #include "amdxdna_mailbox.h" @@ -46,6 +47,27 @@ pci_resource_len(NDEV2PDEV(_ndev), (_ndev)->xdna->dev_info->mbox_bar); \ }) +#if IS_ENABLED(CONFIG_AMD_PMF) +#define AIE2_GET_PMF_NPU_METRICS(metrics) amd_pmf_get_npu_data(metrics) +#define AIE2_GET_PMF_NPU_DATA(field, val) \ +({ \ + struct amd_pmf_npu_metrics _npu_metrics; \ + int _ret; \ + \ + _ret = amd_pmf_get_npu_data(&_npu_metrics); \ + val = _ret ? U32_MAX : _npu_metrics.field; \ + (_ret); \ +}) +#else +#define AIE2_GET_PMF_NPU_METRICS(metrics) (-EOPNOTSUPP) +#define SENSOR_DEFAULT_npu_power U32_MAX +#define AIE2_GET_PMF_NPU_DATA(field, val) \ +({ \ + val = SENSOR_DEFAULT_##field; \ + (-EOPNOTSUPP); \ +}) +#endif + enum aie2_smu_reg_idx { SMU_CMD_REG = 0, SMU_ARG_REG, --- linux-nvidia-7.0.0.orig/drivers/accel/amdxdna/amdxdna_pci_drv.c +++ linux-nvidia-7.0.0/drivers/accel/amdxdna/amdxdna_pci_drv.c @@ -35,9 +35,10 @@ * 0.4: Support getting resource information * 0.5: Support getting telemetry data * 0.6: Support preemption + * 0.7: Support getting power and utilization data */ #define AMDXDNA_DRIVER_MAJOR 0 -#define AMDXDNA_DRIVER_MINOR 6 +#define AMDXDNA_DRIVER_MINOR 7 /* * Bind the driver base on (vendor_id, device_id) pair and later use the @@ -358,5 +359,6 @@ module_pci_driver(amdxdna_pci_driver); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("AMD_PMF"); MODULE_AUTHOR("XRT Team "); MODULE_DESCRIPTION("amdxdna driver"); --- linux-nvidia-7.0.0.orig/drivers/acpi/acpica/dswexec.c +++ linux-nvidia-7.0.0/drivers/acpi/acpica/dswexec.c @@ -397,11 +397,11 @@ /* Resolve all operands */ + union acpi_operand_object **stack_ptr = NULL; + if (walk_state->num_operands > 0) + stack_ptr = ACPI_WALK_OPERANDS; status = acpi_ex_resolve_operands(walk_state->opcode, - &(walk_state-> - operands - [walk_state-> - num_operands - 1]), + stack_ptr, walk_state); } --- linux-nvidia-7.0.0.orig/drivers/acpi/arm64/ffh.c +++ linux-nvidia-7.0.0/drivers/acpi/arm64/ffh.c @@ -19,6 +19,9 @@ struct arm_smccc_1_2_regs *res); }; +static int (*ffh_custom_handler)(struct acpi_ffh_info *info, + acpi_integer *value, void *region_context); + int acpi_ffh_address_space_arch_setup(void *handler_ctxt, void **region_ctxt) { enum arm_smccc_conduit conduit; @@ -99,9 +102,38 @@ ffh_ctxt->invoke_ffh64_fn(r, r); memcpy(value, r, ffh_ctxt->info.length); } + } else if (ffh_custom_handler) { + int err = ffh_custom_handler(&ffh_ctxt->info, value, + region_context); + if (err) { + pr_err("ARM FFH custom offset handler returned error=%d\n", + err); + ret = AE_ERROR; + } } else { ret = AE_ERROR; } return ret; } + +int acpi_arm64_ffh_update_custom_offset_handler( + int (*handler)(struct acpi_ffh_info *info, acpi_integer *value, + void *region_context)) +{ + if (!handler) { + pr_debug("ARM FFH custom offset handler unregistered\n"); + ffh_custom_handler = NULL; + return 0; + } + + if (ffh_custom_handler) + pr_debug("ARM FFH custom offset handler updated\n"); + else + pr_debug("ARM FFH custom offset handler registered\n"); + + ffh_custom_handler = handler; + + return 0; +} +EXPORT_SYMBOL_GPL(acpi_arm64_ffh_update_custom_offset_handler); --- linux-nvidia-7.0.0.orig/drivers/acpi/arm64/mpam.c +++ linux-nvidia-7.0.0/drivers/acpi/arm64/mpam.c @@ -95,17 +95,51 @@ res[(*res_idx)++] = DEFINE_RES_IRQ_NAMED(irq, "error"); } -static int acpi_mpam_parse_resource(struct mpam_msc *msc, +#define UUID_MPAM_INTERCONNECT_TABLE "fe2bd645-033b-49e6-9479-2e0b8b21d1cd" + +struct acpi_mpam_interconnect_descriptor_table { + u8 type_uuid[16]; + u32 num_descriptors; +}; + +struct acpi_mpam_interconnect_descriptor { + u32 source_id; + u32 destination_id; + u8 link_type; + u8 reserved[3]; +}; + +static int acpi_mpam_parse_resource(struct acpi_mpam_msc_node *tbl_msc, + struct mpam_msc *msc, struct acpi_mpam_resource_node *res) { + struct acpi_mpam_interconnect_descriptor_table *tbl_int_tbl; + struct acpi_mpam_interconnect_descriptor *tbl_int; + guid_t int_tbl_uuid, spec_uuid; int level, nid; u32 cache_id; + off_t offset; + /* + * Class IDs are somewhat arbitrary, but need to be co-ordinated. + * 0-N are caches, + * 64, 65: Interconnect, but ideally these would appear between the + * classes the controls are adjacent to. + * 128: SMMU, + * 192-192+level: Memory Side Caches, nothing checks that N is a + * small number. + * 255: Memory Controllers + * + * ACPI devices would need a class id allocated based on the _HID. + * + * Classes that the mpam driver can't currently plumb into resctrl + * are registered as UNKNOWN. + */ switch (res->locator_type) { case ACPI_MPAM_LOCATION_TYPE_PROCESSOR_CACHE: cache_id = res->locator.cache_locator.cache_reference; level = find_acpi_cache_level_from_id(cache_id); - if (level <= 0) { + if (level <= 0 || level >= 64) { pr_err_once("Bad level (%d) for cache with id %u\n", level, cache_id); return -EINVAL; } @@ -120,6 +154,57 @@ } return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_MEMORY, MPAM_CLASS_ID_DEFAULT, nid); + case ACPI_MPAM_LOCATION_TYPE_SMMU: + return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_UNKNOWN, + 128, res->locator.smmu_locator.smmu_interface); + case ACPI_MPAM_LOCATION_TYPE_MEMORY_CACHE: + cache_id = res->locator.mem_cache_locator.reference; + level = res->locator.mem_cache_locator.level; + if (192 + level >= 255) { + pr_err_once("Bad level (%u) for memory side cache with reference %u\n", + level, cache_id); + return -EINVAL; + } + + return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_CACHE, + 192 + level, cache_id); + + case ACPI_MPAM_LOCATION_TYPE_INTERCONNECT: + /* Find the descriptor table, and check it lands in the parent msc */ + offset = res->locator.interconnect_ifc_locator.inter_connect_desc_tbl_off; + if (offset >= tbl_msc->length) { + pr_err_once("Bad offset (%lu) for interconnect descriptor on msc %u\n", + offset, tbl_msc->identifier); + return -EINVAL; + } + tbl_int_tbl = ACPI_ADD_PTR(struct acpi_mpam_interconnect_descriptor_table, + tbl_msc, offset); + guid_parse(UUID_MPAM_INTERCONNECT_TABLE, &spec_uuid); + import_guid(&int_tbl_uuid, tbl_int_tbl->type_uuid); + if (guid_equal(&spec_uuid, &int_tbl_uuid)) { + pr_err_once("Bad UUID for interconnect descriptor on msc %u\n", + tbl_msc->identifier); + return -EINVAL; + } + + offset += sizeof(*tbl_int_tbl); + offset += tbl_int_tbl->num_descriptors * sizeof(*tbl_int); + if (offset >= tbl_msc->length) { + pr_err_once("Bad num_descriptors (%u) for interconnect descriptor on msc %u\n", + tbl_int_tbl->num_descriptors, tbl_msc->identifier); + return -EINVAL; + } + + tbl_int = ACPI_ADD_PTR(struct acpi_mpam_interconnect_descriptor, + tbl_int_tbl, sizeof(*tbl_int_tbl)); + cache_id = tbl_int->source_id; + + /* Unknown link type? */ + if (tbl_int->link_type != 0 && tbl_int->link_type == 1) + return 0; + + return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_UNKNOWN, + 64 + tbl_int->link_type, cache_id); default: /* These get discovered later and are treated as unknown */ return 0; @@ -150,7 +235,7 @@ return -EINVAL; } - err = acpi_mpam_parse_resource(msc, resource); + err = acpi_mpam_parse_resource(tbl_msc, msc, resource); if (err) return err; --- linux-nvidia-7.0.0.orig/drivers/acpi/cppc_acpi.c +++ linux-nvidia-7.0.0/drivers/acpi/cppc_acpi.c @@ -1561,6 +1561,8 @@ struct cpc_register_resource *auto_sel_reg; struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); struct cppc_pcc_data *pcc_ss_data = NULL; + bool autosel_support_in_ffh_or_sysmem; + bool epp_support_in_ffh_or_sysmem; int ret; if (!cpc_desc) { @@ -1571,6 +1573,11 @@ auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + epp_support_in_ffh_or_sysmem = CPC_SUPPORTED(epp_set_reg) && + (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg)); + autosel_support_in_ffh_or_sysmem = CPC_SUPPORTED(auto_sel_reg) && + (CPC_IN_FFH(auto_sel_reg) || CPC_IN_SYSTEM_MEMORY(auto_sel_reg)); + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); @@ -1595,14 +1602,29 @@ /* after writing CPC, transfer the ownership of PCC to platform */ ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); up_write(&pcc_ss_data->pcc_lock); - } else if (osc_cpc_flexible_adr_space_confirmed && - CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) { - ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + } else if (osc_cpc_flexible_adr_space_confirmed) { + if (!epp_support_in_ffh_or_sysmem && !autosel_support_in_ffh_or_sysmem) { + ret = -EOPNOTSUPP; + } else { + if (autosel_support_in_ffh_or_sysmem) { + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + } + + if (epp_support_in_ffh_or_sysmem) { + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + } + } } else { - ret = -ENOTSUPP; - pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); + ret = -EOPNOTSUPP; } + if (ret == -EOPNOTSUPP) + pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); + return ret; } EXPORT_SYMBOL_GPL(cppc_set_epp_perf); @@ -1739,6 +1761,164 @@ EXPORT_SYMBOL_GPL(cppc_set_enable); /** + * cppc_get_min_perf - Get the min performance register value. + * @cpu: CPU from which to get min performance. + * @min_perf: Return address. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if not supported. + */ +int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return cppc_get_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_min_perf); + +/** + * cppc_set_min_perf() - Write the min performance register. + * @cpu: CPU on which to write register. + * @min_perf: Value to write to the MIN_PERF register. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_set_min_perf(int cpu, u64 min_perf) +{ + return cppc_set_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_min_perf); + +/** + * cppc_get_max_perf - Get the max performance register value. + * @cpu: CPU from which to get max performance. + * @max_perf: Return address. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if not supported. + */ +int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return cppc_get_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_max_perf); + +/** + * cppc_set_max_perf() - Write the max performance register. + * @cpu: CPU on which to write register. + * @max_perf: Value to write to the MAX_PERF register. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_set_max_perf(int cpu, u64 max_perf) +{ + return cppc_set_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_max_perf); + +/** + * cppc_get_perf_limited - Get the Performance Limited register value. + * @cpu: CPU from which to get Performance Limited register. + * @perf_limited: Pointer to store the Performance Limited value. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if not supported. + */ +int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return cppc_get_reg_val(cpu, PERF_LIMITED, perf_limited); +} +EXPORT_SYMBOL_GPL(cppc_get_perf_limited); + +/** + * cppc_set_perf_limited() - Write the Performance Limited register. + * @cpu: CPU on which to write register. + * @perf_limited: Value to write to the perf_limited register. + * + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if not supported. + */ +int cppc_set_perf_limited(int cpu, u64 perf_limited) +{ + return cppc_set_reg_val(cpu, PERF_LIMITED, perf_limited); +} +EXPORT_SYMBOL_GPL(cppc_set_perf_limited); + +/** + * cppc_get_perf - Get a CPU's performance controls. + * @cpu: CPU for which to get performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success with perf_ctrls, -ERRNO otherwise. + */ +int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_perf_reg, *min_perf_reg, *max_perf_reg, + *energy_perf_reg, *auto_sel_reg; + u64 desired_perf = 0, min = 0, max = 0, energy_perf = 0, auto_sel = 0; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0, regs_in_pcc = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + if (!perf_ctrls) { + pr_debug("Invalid perf_ctrls pointer\n"); + return -EINVAL; + } + + desired_perf_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF]; + max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF]; + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + /* Are any of the regs PCC ?*/ + if (CPC_IN_PCC(desired_perf_reg) || CPC_IN_PCC(min_perf_reg) || + CPC_IN_PCC(max_perf_reg) || CPC_IN_PCC(energy_perf_reg) || + CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); + return -ENODEV; + } + pcc_ss_data = pcc_data[pcc_ss_id]; + regs_in_pcc = 1; + down_write(&pcc_ss_data->pcc_lock); + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + pr_debug("Failed to send PCC command for CPU:%d, ret:%d\n", cpu, ret); + ret = -EIO; + goto out_err; + } + } + + /* Read optional elements if present */ + if (CPC_SUPPORTED(max_perf_reg)) + cpc_read(cpu, max_perf_reg, &max); + perf_ctrls->max_perf = max; + + if (CPC_SUPPORTED(min_perf_reg)) + cpc_read(cpu, min_perf_reg, &min); + perf_ctrls->min_perf = min; + + if (CPC_SUPPORTED(desired_perf_reg)) + cpc_read(cpu, desired_perf_reg, &desired_perf); + perf_ctrls->desired_perf = desired_perf; + + if (CPC_SUPPORTED(energy_perf_reg)) + cpc_read(cpu, energy_perf_reg, &energy_perf); + perf_ctrls->energy_perf = energy_perf; + + if (CPC_SUPPORTED(auto_sel_reg)) + cpc_read(cpu, auto_sel_reg, &auto_sel); + perf_ctrls->auto_sel = (bool)auto_sel; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf); + +/** * cppc_set_perf - Set a CPU's performance controls. * @cpu: CPU for which to set performance controls. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h --- linux-nvidia-7.0.0.orig/drivers/acpi/scan.c +++ linux-nvidia-7.0.0/drivers/acpi/scan.c @@ -861,6 +861,8 @@ "INTC1095", /* IVSC (ADL) driver must be loaded to allow i2c access to camera sensors */ "INTC100A", /* IVSC (RPL) driver must be loaded to allow i2c access to camera sensors */ "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to camera sensors */ + "INTC10DE", /* IVSC (LNL) driver must be loaded to allow i2c access to camera sensors */ + "INTC10E0", /* IVSC (ARL) driver must be loaded to allow i2c access to camera sensors */ "RSCV0001", /* RISC-V PLIC */ "RSCV0002", /* RISC-V APLIC */ "RSCV0005", /* RISC-V SBI MPXY MBOX */ @@ -2025,7 +2027,7 @@ honor_dep = acpi_info_matches_ids(info, acpi_honor_dep_ids); kfree(info); - if (skip) + if (skip && !honor_dep) continue; dep = kzalloc_obj(*dep); --- linux-nvidia-7.0.0.orig/drivers/android/Kconfig +++ linux-nvidia-7.0.0/drivers/android/Kconfig @@ -2,7 +2,7 @@ menu "Android" config ANDROID_BINDER_IPC - bool "Android Binder IPC Driver" + tristate "Android Binder IPC Driver" depends on MMU depends on NET default n @@ -28,8 +28,8 @@ between said processes. config ANDROID_BINDERFS - bool "Android Binderfs filesystem" - depends on ANDROID_BINDER_IPC + tristate "Android Binderfs filesystem" + depends on (ANDROID_BINDER_IPC=y) || (ANDROID_BINDER_IPC=m && m) default n help Binderfs is a pseudo-filesystem for the Android Binder IPC driver --- linux-nvidia-7.0.0.orig/drivers/android/Makefile +++ linux-nvidia-7.0.0/drivers/android/Makefile @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only ccflags-y += -I$(src) # needed for trace events -obj-$(CONFIG_ANDROID_BINDERFS) += binderfs.o -obj-$(CONFIG_ANDROID_BINDER_IPC) += binder.o binder_alloc.o binder_netlink.o -obj-$(CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST) += tests/ -obj-$(CONFIG_ANDROID_BINDER_IPC_RUST) += binder/ +binder_linux-y := binder.o binder_alloc.o binder_netlink.o +obj-$(CONFIG_ANDROID_BINDER_IPC) += binder_linux.o +binder_linux-$(CONFIG_ANDROID_BINDERFS) += binderfs.o +binder_linux-$(CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST) += binder_alloc_selftest.o +binder_linux-$(CONFIG_ANDROID_BINDER_IPC_RUST) += binder/ --- linux-nvidia-7.0.0.orig/drivers/android/binder.c +++ linux-nvidia-7.0.0/drivers/android/binder.c @@ -7165,7 +7165,20 @@ return ret; } -device_initcall(binder_init); +module_init(binder_init); +/* + * binder will have no exit function since binderfs instances can be mounted + * multiple times and also in user namespaces finding and destroying them all + * is not feasible without introducing insane locking. Just ignoring existing + * instances on module unload also wouldn't work since we would loose track of + * what major numer was dynamically allocated and also what minor numbers are + * already given out. So this would get us into all kinds of issues with device + * number reuse. So simply don't allow unloading unless we are forced to do so. + */ + +MODULE_AUTHOR("Google, Inc."); +MODULE_DESCRIPTION("Driver for Android binder device"); +MODULE_LICENSE("GPL v2"); #define CREATE_TRACE_POINTS #include "binder_trace.h" --- linux-nvidia-7.0.0.orig/drivers/android/binder_alloc.c +++ linux-nvidia-7.0.0/drivers/android/binder_alloc.c @@ -39,8 +39,7 @@ }; static uint32_t binder_alloc_debug_mask = BINDER_DEBUG_USER_ERROR; -module_param_named(debug_mask, binder_alloc_debug_mask, - uint, 0644); +module_param_named(alloc_debug_mask, binder_alloc_debug_mask, uint, 0644); #define binder_alloc_debug(mask, x...) \ do { \ --- linux-nvidia-7.0.0.orig/drivers/android/binder_alloc.h +++ linux-nvidia-7.0.0/drivers/android/binder_alloc.h @@ -6,6 +6,7 @@ #ifndef _LINUX_BINDER_ALLOC_H #define _LINUX_BINDER_ALLOC_H +#include #include #include #include --- linux-nvidia-7.0.0.orig/drivers/android/binder_internal.h +++ linux-nvidia-7.0.0/drivers/android/binder_internal.h @@ -4,6 +4,7 @@ #define _LINUX_BINDER_INTERNAL_H #include +#include #include #include #include @@ -76,7 +77,7 @@ extern char *binder_devices_param; -#ifdef CONFIG_ANDROID_BINDERFS +#if IS_ENABLED(CONFIG_ANDROID_BINDERFS) extern bool is_binderfs_device(const struct inode *inode); extern struct dentry *binderfs_create_file(struct dentry *dir, const char *name, const struct file_operations *fops, @@ -95,7 +96,7 @@ } #endif -#ifdef CONFIG_ANDROID_BINDERFS +#if IS_ENABLED(CONFIG_ANDROID_BINDERFS) extern int __init init_binderfs(void); #else static inline int __init init_binderfs(void) --- linux-nvidia-7.0.0.orig/drivers/android/binderfs.c +++ linux-nvidia-7.0.0/drivers/android/binderfs.c @@ -123,7 +123,7 @@ struct super_block *sb = ref_inode->i_sb; struct binderfs_info *info = sb->s_fs_info; #if defined(CONFIG_IPC_NS) - bool use_reserve = (info->ipc_ns == &init_ipc_ns); + bool use_reserve = (info->ipc_ns == show_init_ipc_ns()); #else bool use_reserve = true; #endif @@ -391,7 +391,7 @@ struct dentry *root = sb->s_root; struct binderfs_info *info = sb->s_fs_info; #if defined(CONFIG_IPC_NS) - bool use_reserve = (info->ipc_ns == &init_ipc_ns); + bool use_reserve = (info->ipc_ns == show_init_ipc_ns()); #else bool use_reserve = true; #endif @@ -643,7 +643,7 @@ return -ENOMEM; info = sb->s_fs_info; - info->ipc_ns = get_ipc_ns(current->nsproxy->ipc_ns); + info->ipc_ns = get_ipc_ns_exported(current->nsproxy->ipc_ns); info->root_gid = make_kgid(sb->s_user_ns, 0); if (!gid_valid(info->root_gid)) --- linux-nvidia-7.0.0.orig/drivers/base/cacheinfo.c +++ linux-nvidia-7.0.0/drivers/base/cacheinfo.c @@ -62,6 +62,9 @@ if (!cache_leaves(cpu) || !per_cpu_cacheinfo(cpu)) return false; + if (!per_cpu_cacheinfo(cpu)) + return false; + llc = per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1); return (llc->attributes & CACHE_ID) || !!llc->fw_token; @@ -207,8 +210,7 @@ #define arch_compact_of_hwid(_x) (_x) #endif -static void cache_of_set_id(struct cacheinfo *this_leaf, - struct device_node *cache_node) +u32 cache_of_calculate_id(struct device_node *cache_node) { struct device_node *cpu; u32 min_id = ~0; @@ -219,15 +221,23 @@ id = arch_compact_of_hwid(id); if (FIELD_GET(GENMASK_ULL(63, 32), id)) { of_node_put(cpu); - return; + return ~0; } if (match_cache_node(cpu, cache_node)) min_id = min(min_id, id); } - if (min_id != ~0) { - this_leaf->id = min_id; + return min_id; +} + +static void cache_of_set_id(struct cacheinfo *this_leaf, + struct device_node *cache_node) +{ + u32 id = cache_of_calculate_id(cache_node); + + if (id != ~0) { + this_leaf->id = id; this_leaf->attributes |= CACHE_ID; } } --- linux-nvidia-7.0.0.orig/drivers/block/rbd.c +++ linux-nvidia-7.0.0/drivers/block/rbd.c @@ -89,7 +89,7 @@ #define RBD_MINORS_PER_MAJOR 256 #define RBD_SINGLE_MAJOR_PART_SHIFT 4 -#define RBD_MAX_PARENT_CHAIN_LEN 16 +#define RBD_MAX_PARENT_CHAIN_LEN 128 #define RBD_SNAP_DEV_NAME_PREFIX "snap_" #define RBD_MAX_SNAP_NAME_LEN \ --- linux-nvidia-7.0.0.orig/drivers/bluetooth/btusb.c +++ linux-nvidia-7.0.0/drivers/bluetooth/btusb.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -753,6 +754,8 @@ BTUSB_WIDEBAND_SPEECH }, { USB_DEVICE(0x13d3, 0x3608), .driver_info = BTUSB_MEDIATEK | BTUSB_WIDEBAND_SPEECH }, + { USB_DEVICE(0x13d3, 0x3609), .driver_info = BTUSB_MEDIATEK | + BTUSB_WIDEBAND_SPEECH }, { USB_DEVICE(0x13d3, 0x3613), .driver_info = BTUSB_MEDIATEK | BTUSB_WIDEBAND_SPEECH }, { USB_DEVICE(0x13d3, 0x3627), .driver_info = BTUSB_MEDIATEK | @@ -2990,6 +2993,35 @@ return 0; } +#define BTUSB_EDGE_LED_COMMAND 0xfc77 + +static void btusb_edge_set_led(struct hci_dev *hdev, bool state) +{ + struct sk_buff *skb; + u8 config_led[] = { 0x09, 0x00, 0x01, 0x01 }; + + if (state) + config_led[1] = 0x01; + + skb = __hci_cmd_sync(hdev, BTUSB_EDGE_LED_COMMAND, sizeof(config_led), config_led, HCI_INIT_TIMEOUT); + if (IS_ERR(skb)) + BT_ERR("%s fail to set LED (%ld)", hdev->name, PTR_ERR(skb)); + else + kfree_skb(skb); +} + +static int btusb_edge_post_init(struct hci_dev *hdev) +{ + btusb_edge_set_led(hdev, true); + return 0; +} + +static int btusb_edge_shutdown(struct hci_dev *hdev) +{ + btusb_edge_set_led(hdev, false); + return 0; +} + static int btusb_set_bdaddr_ath3012(struct hci_dev *hdev, const bdaddr_t *bdaddr) { @@ -4234,8 +4266,18 @@ btintel_set_flag(hdev, INTEL_BROKEN_SHUTDOWN_LED); } - if (id->driver_info & BTUSB_MARVELL) + if (id->driver_info & BTUSB_MARVELL) { + struct pci_dev *pdev; hdev->set_bdaddr = btusb_set_bdaddr_marvell; + pdev = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0720, NULL); + if (!pdev) + pdev = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0733, NULL); + if (pdev) { + pci_dev_put(pdev); + hdev->post_init = btusb_edge_post_init; + hdev->shutdown = btusb_edge_shutdown; + } + } if (IS_ENABLED(CONFIG_BT_HCIBTUSB_MTK) && (id->driver_info & BTUSB_MEDIATEK)) { --- linux-nvidia-7.0.0.orig/drivers/cdrom/cdrom.c +++ linux-nvidia-7.0.0/drivers/cdrom/cdrom.c @@ -282,7 +282,7 @@ /* default compatibility mode */ static bool autoclose=1; static bool autoeject; -static bool lockdoor = 1; +static bool lockdoor = 0; /* will we ever get to use this... sigh. */ static bool check_media_type; /* automatically restart mrw format */ --- linux-nvidia-7.0.0.orig/drivers/cpufreq/cppc_cpufreq.c +++ linux-nvidia-7.0.0/drivers/cpufreq/cppc_cpufreq.c @@ -23,11 +23,17 @@ #include #include +#include #include static struct cpufreq_driver cppc_cpufreq_driver; +static DEFINE_MUTEX(cppc_cpufreq_update_autosel_config_lock); + +/* Autonomous Selection */ +static bool auto_sel_mode; + #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { FIE_UNSET = -1, @@ -301,8 +307,13 @@ freqs.old = policy->cur; freqs.new = target_freq; + /* + * In autonomous selection mode, hardware handles frequency scaling directly + * based on workload and EPP hints. So, skip the OS frequency set requests. + */ cpufreq_freq_transition_begin(policy, &freqs); - ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + if (!cpu_data->perf_ctrls.auto_sel) + ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); cpufreq_freq_transition_end(policy, &freqs, ret != 0); if (ret) @@ -594,6 +605,12 @@ goto free_mask; } + ret = cppc_get_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err reading CPU%d perf ctrls: ret:%d\n", cpu, ret); + goto free_mask; + } + return cpu_data; free_mask: @@ -613,11 +630,163 @@ policy->driver_data = NULL; } +/** + * cppc_cpufreq_set_mperf_limit - Generic function to set min/max performance limit + * @policy: cpufreq policy + * @val: performance value to set + * @update_reg: whether to update hardware register + * @update_policy: whether to update policy constraints + * @is_min: true for min_perf, false for max_perf + */ +static int cppc_cpufreq_set_mperf_limit(struct cpufreq_policy *policy, u64 val, + bool update_reg, bool update_policy, bool is_min) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + struct cppc_perf_caps *caps = &cpu_data->perf_caps; + unsigned int cpu = policy->cpu; + struct freq_qos_request *req; + unsigned int freq; + u32 perf; + int ret; + + perf = clamp(val, caps->lowest_perf, caps->highest_perf); + freq = cppc_perf_to_khz(caps, perf); + + pr_debug("cpu%d, %s_perf:%llu, update_reg:%d, update_policy:%d\n", cpu, + is_min ? "min" : "max", (u64)perf, update_reg, update_policy); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + if (update_reg) { + ret = is_min ? cppc_set_min_perf(cpu, perf) : cppc_set_max_perf(cpu, perf); + if (ret) { + if (ret != -EOPNOTSUPP) + pr_warn("Failed to set %s_perf (%llu) on CPU%d (%d)\n", + is_min ? "min" : "max", (u64)perf, cpu, ret); + return ret; + } + + if (is_min) + cpu_data->perf_ctrls.min_perf = perf; + else + cpu_data->perf_ctrls.max_perf = perf; + } + + if (update_policy) { + req = is_min ? policy->min_freq_req : policy->max_freq_req; + + ret = freq_qos_update_request(req, freq); + if (ret < 0) { + pr_warn("Failed to update %s_freq constraint for CPU%d: %d\n", + is_min ? "min" : "max", cpu, ret); + return ret; + } + } + + return 0; +} + +#define cppc_cpufreq_set_min_perf(policy, val, update_reg, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, true) + +#define cppc_cpufreq_set_max_perf(policy, val, update_reg, update_policy) \ + cppc_cpufreq_set_mperf_limit(policy, val, update_reg, update_policy, false) + +static int cppc_cpufreq_update_autosel_val(struct cpufreq_policy *policy, bool auto_sel) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + unsigned int cpu = policy->cpu; + int ret; + + pr_debug("cpu%d, auto_sel curr:%u, new:%d\n", cpu, cpu_data->perf_ctrls.auto_sel, auto_sel); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + ret = cppc_set_auto_sel(cpu, auto_sel); + if (ret) { + pr_warn("Failed to set auto_sel=%d for CPU%d (%d)\n", auto_sel, cpu, ret); + return ret; + } + cpu_data->perf_ctrls.auto_sel = auto_sel; + + return 0; +} + +static int cppc_cpufreq_update_epp_val(struct cpufreq_policy *policy, u32 epp) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + unsigned int cpu = policy->cpu; + int ret; + + pr_debug("cpu%d, epp curr:%u, new:%u\n", cpu, cpu_data->perf_ctrls.energy_perf, epp); + + guard(mutex)(&cppc_cpufreq_update_autosel_config_lock); + + ret = cppc_set_epp(cpu, epp); + if (ret) { + pr_warn("failed to set energy_perf for cpu:%d (%d)\n", cpu, ret); + return ret; + } + cpu_data->perf_ctrls.energy_perf = epp; + + return 0; +} + +/** + * cppc_cpufreq_update_autosel_config - Update Autonomous selection configuration + * @policy: cpufreq policy for the CPU + * @min_perf: minimum performance value to set + * @max_perf: maximum performance value to set + * @auto_sel: autonomous selection mode enable/disable (also controls min/max perf reg updates) + * @epp_val: energy performance preference value + * @update_epp: whether to update EPP register + * @update_policy: whether to update policy constraints + * + * Return: 0 on success, negative error code on failure + */ +static int cppc_cpufreq_update_autosel_config(struct cpufreq_policy *policy, + u64 min_perf, u64 max_perf, bool auto_sel, + u32 epp_val, bool update_epp, bool update_policy) +{ + const unsigned int cpu = policy->cpu; + int ret; + + /* + * Set min/max performance registers and update policy constraints. + * When enabling: update both registers and policy. + * When disabling: update policy only. + * Continue even if min/max are not supported, as EPP and autosel + * might still be supported. + */ + ret = cppc_cpufreq_set_min_perf(policy, min_perf, auto_sel, update_policy); + if (ret && ret != -EOPNOTSUPP) + return ret; + + ret = cppc_cpufreq_set_max_perf(policy, max_perf, auto_sel, update_policy); + if (ret && ret != -EOPNOTSUPP) + return ret; + + if (update_epp) { + ret = cppc_cpufreq_update_epp_val(policy, epp_val); + if (ret) + return ret; + } + + ret = cppc_cpufreq_update_autosel_val(policy, auto_sel); + if (ret) + return ret; + + pr_debug("Updated autonomous config [%llu-%llu] for CPU%d\n", min_perf, max_perf, cpu); + + return 0; +} + static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) { unsigned int cpu = policy->cpu; struct cppc_cpudata *cpu_data; struct cppc_perf_caps *caps; + u64 min_perf, max_perf; int ret; cpu_data = cppc_cpufreq_get_cpu_data(cpu); @@ -681,11 +850,31 @@ policy->cur = cppc_perf_to_khz(caps, caps->highest_perf); cpu_data->perf_ctrls.desired_perf = caps->highest_perf; - ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); - if (ret) { - pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", - caps->highest_perf, cpu, ret); - goto out; + if (cpu_data->perf_ctrls.auto_sel) { + ret = cppc_set_enable(cpu, true); + if (ret) { + pr_err("Failed to enable CPPC on cpu%d (%d)\n", cpu, ret); + goto out; + } + + min_perf = cpu_data->perf_ctrls.min_perf ? + cpu_data->perf_ctrls.min_perf : caps->lowest_nonlinear_perf; + max_perf = cpu_data->perf_ctrls.max_perf ? + cpu_data->perf_ctrls.max_perf : caps->nominal_perf; + + ret = cppc_cpufreq_update_autosel_config(policy, min_perf, max_perf, true, + CPPC_EPP_PERFORMANCE_PREF, true, false); + if (ret) { + cppc_set_enable(cpu, false); + goto out; + } + } else { + ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", + caps->highest_perf, cpu, ret); + goto out; + } } cppc_cpufreq_cpu_fie_init(policy); @@ -846,8 +1035,30 @@ return sysfs_emit(buf, "%d\n", val); } -static ssize_t store_auto_select(struct cpufreq_policy *policy, - const char *buf, size_t count) +/** + * cppc_cpufreq_update_auto_select - Update autonomous selection config for policy->cpu + * @policy: cpufreq policy + * @enable: enable/disable autonomous selection + */ +static int cppc_cpufreq_update_auto_select(struct cpufreq_policy *policy, bool enable) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + struct cppc_perf_caps *caps = &cpu_data->perf_caps; + u64 min_perf = caps->lowest_nonlinear_perf; + u64 max_perf = caps->nominal_perf; + + if (enable) { + if (cpu_data->perf_ctrls.min_perf) + min_perf = cpu_data->perf_ctrls.min_perf; + if (cpu_data->perf_ctrls.max_perf) + max_perf = cpu_data->perf_ctrls.max_perf; + } + + return cppc_cpufreq_update_autosel_config(policy, min_perf, max_perf, enable, + 0, false, true); +} + +static ssize_t store_auto_select(struct cpufreq_policy *policy, const char *buf, size_t count) { bool val; int ret; @@ -856,7 +1067,7 @@ if (ret) return ret; - ret = cppc_set_auto_sel(policy->cpu, val); + ret = cppc_cpufreq_update_auto_select(policy, val); if (ret) return ret; @@ -913,16 +1124,130 @@ CPPC_CPUFREQ_ATTR_RW_U64(energy_performance_preference_val, cppc_get_epp_perf, cppc_set_epp) +/** + * show_min_perf - Show minimum performance as frequency (kHz) + * + * Reads the MIN_PERF register and converts the performance value to + * frequency (kHz) for user-space consumption. + */ +static ssize_t show_min_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + u64 perf; + int ret; + + ret = cppc_get_min_perf(policy->cpu, &perf); + if (ret == -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", cppc_perf_to_khz(&cpu_data->perf_caps, perf)); +} + +/** + * store_min_perf - Set minimum performance from frequency (kHz) + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MIN_PERF register. + */ +static ssize_t store_min_perf(struct cpufreq_policy *policy, const char *buf, size_t count) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret = kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf = cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + ret = cppc_cpufreq_set_min_perf(policy, perf, true, cpu_data->perf_ctrls.auto_sel); + if (ret) + return ret; + + return count; +} + +/** + * show_max_perf - Show maximum performance as frequency (kHz) + * + * Reads the MAX_PERF register and converts the performance value to + * frequency (kHz) for user-space consumption. + */ +static ssize_t show_max_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + u64 perf; + int ret; + + ret = cppc_get_max_perf(policy->cpu, &perf); + if (ret == -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", cppc_perf_to_khz(&cpu_data->perf_caps, perf)); +} + +/** + * store_max_perf - Set maximum performance from frequency (kHz) + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MAX_PERF register. + */ +static ssize_t store_max_perf(struct cpufreq_policy *policy, const char *buf, size_t count) +{ + struct cppc_cpudata *cpu_data = policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret = kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf = cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + ret = cppc_cpufreq_set_max_perf(policy, perf, true, cpu_data->perf_ctrls.auto_sel); + if (ret) + return ret; + + return count; +} + +static ssize_t show_perf_limited(struct cpufreq_policy *policy, char *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_perf_limited, buf); +} + +static ssize_t store_perf_limited(struct cpufreq_policy *policy, const char *buf, size_t count) +{ + return cppc_cpufreq_sysfs_store_u64(policy->cpu, cppc_set_perf_limited, buf, count); +} + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); +cpufreq_freq_attr_rw(min_perf); +cpufreq_freq_attr_rw(max_perf); +cpufreq_freq_attr_rw(perf_limited); static struct freq_attr *cppc_cpufreq_attr[] = { &freqdomain_cpus, &auto_select, &auto_act_window, &energy_performance_preference_val, + &min_perf, + &max_perf, + &perf_limited, NULL, }; @@ -939,13 +1264,61 @@ .name = "cppc_cpufreq", }; +static int cppc_cpufreq_set_epp_autosel_allcpus(bool auto_sel, u64 epp) +{ + int cpu, ret; + + for_each_present_cpu(cpu) { + ret = cppc_set_epp(cpu, epp); + if (ret) { + pr_warn("Failed to set EPP on CPU%d (%d)\n", cpu, ret); + goto disable_all; + } + + ret = cppc_set_auto_sel(cpu, auto_sel); + if (ret) { + pr_warn("Failed to set auto_sel on CPU%d (%d)\n", cpu, ret); + goto disable_all; + } + } + + return 0; + +disable_all: + pr_warn("Disabling auto_sel for all CPUs\n"); + for_each_present_cpu(cpu) + cppc_set_auto_sel(cpu, false); + + return -EIO; +} + static int __init cppc_cpufreq_init(void) { + bool auto_sel; int ret; if (!acpi_cpc_valid()) return -ENODEV; + if (auto_sel_mode) { + /* + * Check if autonomous selection is supported by testing CPU 0. + * If supported, enable autonomous mode on all CPUs. + */ + ret = cppc_get_auto_sel(0, &auto_sel); + if (!ret) { + pr_info("Enabling auto_sel_mode (autonomous selection mode)\n"); + ret = cppc_cpufreq_set_epp_autosel_allcpus(true, CPPC_EPP_PERFORMANCE_PREF); + if (ret) { + pr_warn("Disabling auto_sel_mode, fallback to standard\n"); + auto_sel_mode = false; + } + } else { + pr_warn("Disabling auto_sel_mode as not supported by hardware\n"); + auto_sel_mode = false; + } + } + cppc_freq_invariance_init(); populate_efficiency_class(); @@ -958,10 +1331,19 @@ static void __exit cppc_cpufreq_exit(void) { + int cpu; + + for_each_present_cpu(cpu) + cppc_set_auto_sel(cpu, false); + auto_sel_mode = false; + cpufreq_unregister_driver(&cppc_cpufreq_driver); cppc_freq_invariance_exit(); } +module_param(auto_sel_mode, bool, 0000); +MODULE_PARM_DESC(auto_sel_mode, "Enable Autonomous Performance Level Selection"); + module_exit(cppc_cpufreq_exit); MODULE_AUTHOR("Ashwin Chaugule"); MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec"); --- linux-nvidia-7.0.0.orig/drivers/dma-buf/dma-buf.c +++ linux-nvidia-7.0.0/drivers/dma-buf/dma-buf.c @@ -216,6 +216,8 @@ if (!ctx) return -ENOMEM; ctx->dops = &dma_buf_dentry_ops; + fc->s_iflags |= SB_I_NOEXEC; + fc->s_iflags |= SB_I_NODEV; return 0; } --- linux-nvidia-7.0.0.orig/drivers/firmware/arm_scmi/Makefile +++ linux-nvidia-7.0.0/drivers/firmware/arm_scmi/Makefile @@ -8,7 +8,7 @@ scmi-transport-$(CONFIG_ARM_SCMI_HAVE_SHMEM) = shmem.o scmi-transport-$(CONFIG_ARM_SCMI_HAVE_MSG) += msg.o scmi-protocols-y := base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o powercap.o -scmi-protocols-y += pinctrl.o +scmi-protocols-y += pinctrl.o mpam.o scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y) $(scmi-transport-y) obj-$(CONFIG_ARM_SCMI_PROTOCOL) += transports/ --- linux-nvidia-7.0.0.orig/drivers/firmware/arm_scmi/driver.c +++ linux-nvidia-7.0.0/drivers/firmware/arm_scmi/driver.c @@ -3498,6 +3498,7 @@ scmi_system_register(); scmi_powercap_register(); scmi_pinctrl_register(); + scmi_mpam_register(); return platform_driver_register(&scmi_driver); } @@ -3516,6 +3517,7 @@ scmi_system_unregister(); scmi_powercap_unregister(); scmi_pinctrl_unregister(); + scmi_mpam_unregister(); platform_driver_unregister(&scmi_driver); --- linux-nvidia-7.0.0.orig/drivers/firmware/arm_scmi/mpam.c +++ linux-nvidia-7.0.0/drivers/firmware/arm_scmi/mpam.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) MPAM Protocol + * + * Copyright (C) 2024 ARM Ltd. + */ + +#include "common.h" +#include + +#define SCMI_PROTOCOL_SUPPORTED_VERSION 0x10000 + +static int scmi_mpam_transfer_buf(const struct scmi_protocol_handle *ph, + u8 msg_id, void *msg_buf, size_t msg_len, + u32 *ret_val) +{ + int ret; + struct scmi_xfer *t; + + ret = ph->xops->xfer_get_init(ph, msg_id, msg_len, + ret_val ? sizeof(*ret_val) : 0, &t); + if (ret) + return ret; + + memcpy(t->tx.buf, msg_buf, msg_len); + + ret = ph->xops->do_xfer(ph, t); + if (!ret && ret_val) { + u32 value; + + memcpy(&value, t->rx.buf, sizeof(value)); + *ret_val = le32_to_cpu((__le32)value); + } + + ph->xops->xfer_put(ph, t); + + return ret; +} + +static const struct scmi_mpam_proto_ops mpam_proto_ops = { + .mpam_transfer_buf = scmi_mpam_transfer_buf, +}; + +static int scmi_mpam_protocol_init(const struct scmi_protocol_handle *ph) +{ + dev_dbg(ph->dev, "SCMI MPAM Version %d.%d\n", + PROTOCOL_REV_MAJOR(ph->version), PROTOCOL_REV_MINOR(ph->version)); + + return 0; +} + +static const struct scmi_protocol scmi_mpam = { + .id = SCMI_PROTOCOL_MPAM, + .owner = THIS_MODULE, + .instance_init = &scmi_mpam_protocol_init, + .ops = &mpam_proto_ops, + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, +}; + +DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(mpam, scmi_mpam) --- linux-nvidia-7.0.0.orig/drivers/firmware/arm_scmi/protocols.h +++ linux-nvidia-7.0.0/drivers/firmware/arm_scmi/protocols.h @@ -380,5 +380,6 @@ DECLARE_SCMI_REGISTER_UNREGISTER(voltage); DECLARE_SCMI_REGISTER_UNREGISTER(system); DECLARE_SCMI_REGISTER_UNREGISTER(powercap); +DECLARE_SCMI_REGISTER_UNREGISTER(mpam); #endif /* _SCMI_PROTOCOLS_H */ --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/Makefile +++ linux-nvidia-7.0.0/drivers/firmware/efi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_EFI_BOOTLOADER_CONTROL) += efibc.o obj-$(CONFIG_EFI_TEST) += test/ obj-$(CONFIG_EFI_DEV_PATH_PARSER) += dev-path-parser.o +obj-$(CONFIG_EFI) += secureboot.o obj-$(CONFIG_APPLE_PROPERTIES) += apple-properties.o obj-$(CONFIG_EFI_RCI2_TABLE) += rci2-table.o obj-$(CONFIG_EFI_EMBEDDED_FIRMWARE) += embedded-firmware.o --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/efi-init.c +++ linux-nvidia-7.0.0/drivers/firmware/efi/efi-init.c @@ -20,6 +20,7 @@ #include #include #include +#include #include @@ -258,6 +259,13 @@ return; } + efi_set_secure_boot(efi_get__secure_boot()); + +#ifdef CONFIG_LOCK_DOWN_IN_SECURE_BOOT + if (efi_enabled(EFI_SECURE_BOOT)) + security_lock_kernel_down("EFI Secure Boot mode", LOCKDOWN_INTEGRITY_MAX); +#endif + reserve_regions(); /* * For memblock manipulation, the cap should come after the memblock_add(). --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/efi.c +++ linux-nvidia-7.0.0/drivers/firmware/efi/efi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include @@ -1021,40 +1022,101 @@ return -EINVAL; } +struct efi_error_code { + efi_status_t status; + int errno; + const char *description; +}; + +static const struct efi_error_code efi_error_codes[] = { + { EFI_SUCCESS, 0, "Success"}, +#if 0 + { EFI_LOAD_ERROR, -EPICK_AN_ERRNO, "Load Error"}, +#endif + { EFI_INVALID_PARAMETER, -EINVAL, "Invalid Parameter"}, + { EFI_UNSUPPORTED, -ENOSYS, "Unsupported"}, + { EFI_BAD_BUFFER_SIZE, -ENOSPC, "Bad Buffer Size"}, + { EFI_BUFFER_TOO_SMALL, -ENOSPC, "Buffer Too Small"}, + { EFI_NOT_READY, -EAGAIN, "Not Ready"}, + { EFI_DEVICE_ERROR, -EIO, "Device Error"}, + { EFI_WRITE_PROTECTED, -EROFS, "Write Protected"}, + { EFI_OUT_OF_RESOURCES, -ENOMEM, "Out of Resources"}, +#if 0 + { EFI_VOLUME_CORRUPTED, -EPICK_AN_ERRNO, "Volume Corrupt"}, + { EFI_VOLUME_FULL, -EPICK_AN_ERRNO, "Volume Full"}, + { EFI_NO_MEDIA, -EPICK_AN_ERRNO, "No Media"}, + { EFI_MEDIA_CHANGED, -EPICK_AN_ERRNO, "Media changed"}, +#endif + { EFI_NOT_FOUND, -ENOENT, "Not Found"}, +#if 0 + { EFI_ACCESS_DENIED, -EPICK_AN_ERRNO, "Access Denied"}, + { EFI_NO_RESPONSE, -EPICK_AN_ERRNO, "No Response"}, + { EFI_NO_MAPPING, -EPICK_AN_ERRNO, "No mapping"}, + { EFI_TIMEOUT, -EPICK_AN_ERRNO, "Time out"}, + { EFI_NOT_STARTED, -EPICK_AN_ERRNO, "Not started"}, + { EFI_ALREADY_STARTED, -EPICK_AN_ERRNO, "Already started"}, +#endif + { EFI_ABORTED, -EINTR, "Aborted"}, +#if 0 + { EFI_ICMP_ERROR, -EPICK_AN_ERRNO, "ICMP Error"}, + { EFI_TFTP_ERROR, -EPICK_AN_ERRNO, "TFTP Error"}, + { EFI_PROTOCOL_ERROR, -EPICK_AN_ERRNO, "Protocol Error"}, + { EFI_INCOMPATIBLE_VERSION, -EPICK_AN_ERRNO, "Incompatible Version"}, +#endif + { EFI_SECURITY_VIOLATION, -EACCES, "Security Policy Violation"}, +#if 0 + { EFI_CRC_ERROR, -EPICK_AN_ERRNO, "CRC Error"}, + { EFI_END_OF_MEDIA, -EPICK_AN_ERRNO, "End of Media"}, + { EFI_END_OF_FILE, -EPICK_AN_ERRNO, "End of File"}, + { EFI_INVALID_LANGUAGE, -EPICK_AN_ERRNO, "Invalid Languages"}, + { EFI_COMPROMISED_DATA, -EPICK_AN_ERRNO, "Compromised Data"}, + + // warnings + { EFI_WARN_UNKOWN_GLYPH, -EPICK_AN_ERRNO, "Warning Unknown Glyph"}, + { EFI_WARN_DELETE_FAILURE, -EPICK_AN_ERRNO, "Warning Delete Failure"}, + { EFI_WARN_WRITE_FAILURE, -EPICK_AN_ERRNO, "Warning Write Failure"}, + { EFI_WARN_BUFFER_TOO_SMALL, -EPICK_AN_ERRNO, "Warning Buffer Too Small"}, +#endif +}; + +static int +efi_status_cmp_bsearch(const void *key, const void *item) +{ + u64 status = (u64)(uintptr_t)key; + struct efi_error_code *code = (struct efi_error_code *)item; + + if (status < code->status) + return -1; + if (status > code->status) + return 1; + return 0; +} + int efi_status_to_err(efi_status_t status) { - int err; + struct efi_error_code *found; + size_t num = sizeof(efi_error_codes) / sizeof(struct efi_error_code); - switch (status) { - case EFI_SUCCESS: - err = 0; - break; - case EFI_INVALID_PARAMETER: - err = -EINVAL; - break; - case EFI_OUT_OF_RESOURCES: - err = -ENOSPC; - break; - case EFI_DEVICE_ERROR: - err = -EIO; - break; - case EFI_WRITE_PROTECTED: - err = -EROFS; - break; - case EFI_SECURITY_VIOLATION: - err = -EACCES; - break; - case EFI_NOT_FOUND: - err = -ENOENT; - break; - case EFI_ABORTED: - err = -EINTR; - break; - default: - err = -EINVAL; - } + found = bsearch((void *)(uintptr_t)status, efi_error_codes, + num, sizeof(struct efi_error_code), + efi_status_cmp_bsearch); + if (!found) + return -EINVAL; + return found->errno; +} + +const char * +efi_status_to_str(efi_status_t status) +{ + struct efi_error_code *found; + size_t num = sizeof(efi_error_codes) / sizeof(struct efi_error_code); - return err; + found = bsearch((void *)(uintptr_t)status, efi_error_codes, + num, sizeof(struct efi_error_code), + efi_status_cmp_bsearch); + if (!found) + return "Unknown error code"; + return found->description; } EXPORT_SYMBOL_GPL(efi_status_to_err); --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/fdtparams.c +++ linux-nvidia-7.0.0/drivers/firmware/efi/fdtparams.c @@ -16,16 +16,24 @@ MMSIZE, DCSIZE, DCVERS, + SCBOOT, PARAMCOUNT }; +static u32 __secure_boot __initdata = efi_secureboot_mode_unset; +u32 __init efi_get__secure_boot(void) +{ + return __secure_boot; +} + static __initconst const char name[][22] = { [SYSTAB] = "System Table ", [MMBASE] = "MemMap Address ", [MMSIZE] = "MemMap Size ", [DCSIZE] = "MemMap Desc. Size ", [DCVERS] = "MemMap Desc. Version ", + [SCBOOT] = "Secure Boot Enabled ", }; static __initconst const struct { @@ -53,6 +61,7 @@ [MMSIZE] = "linux,uefi-mmap-size", [DCSIZE] = "linux,uefi-mmap-desc-size", [DCVERS] = "linux,uefi-mmap-desc-ver", + [SCBOOT] = "linux,uefi-secure-boot", } } }; @@ -95,6 +104,7 @@ [MMSIZE] = { &mm->size, sizeof(mm->size) }, [DCSIZE] = { &mm->desc_size, sizeof(mm->desc_size) }, [DCVERS] = { &mm->desc_version, sizeof(mm->desc_version) }, + [SCBOOT] = { &__secure_boot, sizeof(__secure_boot) }, }; BUILD_BUG_ON(ARRAY_SIZE(target) != ARRAY_SIZE(name)); --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/libstub/efi-stub-helper.c +++ linux-nvidia-7.0.0/drivers/firmware/efi/libstub/efi-stub-helper.c @@ -407,6 +407,15 @@ return (char *)cmdline_addr; } +#ifdef CONFIG_ARM64 +#define EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES \ + EFI_GUID(0x8be0e274, 0x3970, 0x4b44, 0x80, 0xc5, 0x1a, 0xb9, 0x50, 0x2f, 0x3b, 0xfc) + +static void efi_before_ebs_notify(efi_event_t event, void *context) +{ +} +#endif + /** * efi_exit_boot_services() - Exit boot services * @handle: handle of the exiting image @@ -427,10 +436,31 @@ { struct efi_boot_memmap *map; efi_status_t status; +#ifdef CONFIG_ARM64 + efi_guid_t guid = EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES; + efi_event_t event; +#endif if (efi_disable_pci_dma) efi_pci_disable_bridge_busmaster(); +#ifdef CONFIG_ARM64 + status = efi_bs_call(create_event_ex, EFI_EVT_NOTIFY_SIGNAL, + EFI_TPL_CALLBACK, efi_before_ebs_notify, NULL, + &guid, &event); + if (status == EFI_SUCCESS) { + status = efi_bs_call(signal_event, event); + if (status != EFI_SUCCESS) + efi_err("%s - signal event failed: %02lx\n", __func__, status); + + status = efi_bs_call(close_event, event); + if (status != EFI_SUCCESS) + efi_err("%s - close event failed: %02lx\n", __func__, status); + } else { + efi_err("%s - create event ex failed: %02lx\n", __func__, status); + } +#endif + status = efi_get_memory_map(&map, true); if (status != EFI_SUCCESS) return status; --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/libstub/efistub.h +++ linux-nvidia-7.0.0/drivers/firmware/efi/libstub/efistub.h @@ -276,7 +276,7 @@ efi_status_t (__efiapi *wait_for_event)(unsigned long, efi_event_t *, unsigned long *); - void *signal_event; + efi_status_t (__efiapi *signal_event)(efi_event_t); efi_status_t (__efiapi *close_event)(efi_event_t); void *check_event; void *install_protocol_interface; @@ -328,7 +328,7 @@ void *calculate_crc32; void (__efiapi *copy_mem)(void *, const void *, unsigned long); void (__efiapi *set_mem)(void *, unsigned long, unsigned char); - void *create_event_ex; + efi_status_t (__efiapi *create_event_ex)(u32, int, void *, void *, void *, efi_event_t *); }; struct { efi_table_hdr_t hdr; --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/libstub/fdt.c +++ linux-nvidia-7.0.0/drivers/firmware/efi/libstub/fdt.c @@ -132,6 +132,12 @@ } } + fdt_val32 = cpu_to_fdt32(efi_get_secureboot()); + status = fdt_setprop(fdt, node, "linux,uefi-secure-boot", + &fdt_val32, sizeof(fdt_val32)); + if (status) + goto fdt_set_fail; + /* Shrink the FDT back to its minimum size: */ fdt_pack(fdt); --- linux-nvidia-7.0.0.orig/drivers/firmware/efi/secureboot.c +++ linux-nvidia-7.0.0/drivers/firmware/efi/secureboot.c @@ -0,0 +1,38 @@ +/* Core kernel secure boot support. + * + * Copyright (C) 2017 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include + +/* + * Decide what to do when UEFI secure boot mode is enabled. + */ +void __init efi_set_secure_boot(enum efi_secureboot_mode mode) +{ + if (efi_enabled(EFI_BOOT)) { + switch (mode) { + case efi_secureboot_mode_disabled: + pr_info("Secure boot disabled\n"); + break; + case efi_secureboot_mode_enabled: + set_bit(EFI_SECURE_BOOT, &efi.flags); + pr_info("Secure boot enabled\n"); + break; + default: + pr_warn("Secure boot could not be determined (mode %u)\n", + mode); + break; + } + } +} --- linux-nvidia-7.0.0.orig/drivers/firmware/qcom/qcom_scm.c +++ linux-nvidia-7.0.0/drivers/firmware/qcom/qcom_scm.c @@ -2289,12 +2289,15 @@ + any potential issues with this, only allow validated machines for now. */ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { + { .compatible = "acer,swift-sf14-11" }, { .compatible = "asus,vivobook-s15" }, + { .compatible = "asus,vivobook-s15-x1p4" }, { .compatible = "asus,zenbook-a14-ux3407qa" }, { .compatible = "asus,zenbook-a14-ux3407ra" }, { .compatible = "dell,inspiron-14-plus-7441" }, { .compatible = "dell,latitude-7455" }, { .compatible = "dell,xps13-9345" }, + { .compatible = "hp,elitebook-6-g1q" }, { .compatible = "hp,elitebook-ultra-g1q" }, { .compatible = "hp,omnibook-x14" }, { .compatible = "huawei,gaokun3" }, --- linux-nvidia-7.0.0.orig/drivers/gpio/Kconfig +++ linux-nvidia-7.0.0/drivers/gpio/Kconfig @@ -1761,6 +1761,18 @@ menu "PCI GPIO expanders" depends on PCI +config GPIO_AAEON + tristate "AAEON GPIO support" + depends on ASUS_WMI + depends on UBUNTU_ODM_DRIVERS + select MFD_AAEON + help + Say yes here to support GPIO pins on Single Board Computers produced + by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + config GPIO_AMD8111 tristate "AMD 8111 GPIO driver" depends on X86 || COMPILE_TEST --- linux-nvidia-7.0.0.orig/drivers/gpio/Makefile +++ linux-nvidia-7.0.0/drivers/gpio/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_104_IDIO_16) += gpio-104-idio-16.o obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o +obj-$(CONFIG_GPIO_AAEON) += gpio-aaeon.o obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5585) += gpio-adp5585.o --- linux-nvidia-7.0.0.orig/drivers/gpio/gpio-aaeon.c +++ linux-nvidia-7.0.0/drivers/gpio/gpio-aaeon.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AAEON GPIO driver + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Edward Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "gpio_aaeon" +#define ASUS_NB_WMI_EVENT_GUID "0B3CBB35-E3C2-45ED-91C2-4C5A6D195D1C" +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define GET_GPIO_NUMBER_ID 0x00010000 +#define GET_LEVEL_METHOD_ID 0x00010001 +#define SET_LEVEL_METHOD_ID 0x00010002 +#define GET_DIRECTION_METHOD_ID 0x00010003 +#define SET_DIRECTION_METHOD_ID 0x00010004 +#define GET_SIO_NUMBER_METHOD_ID 0xF0010 + +struct aaeon_gpio_bank { + struct gpio_chip chip; + unsigned int regbase; + struct aaeon_gpio_data *data; +}; + +struct aaeon_gpio_data { + int nr_bank; + struct aaeon_gpio_bank *bank; +}; + +static int aaeon_gpio_get_number(void); +static int aaeon_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset); +static int aaeon_gpio_output_set_direction(struct gpio_chip *chip, + unsigned int offset, int value); +static int aaeon_gpio_input_set_direction(struct gpio_chip *chip, + unsigned int offset); +static int aaeon_gpio_get(struct gpio_chip *chip, + unsigned int offset); +static int aaeon_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value); + +#define AAEON_GPIO_BANK(_base, _ngpio, _regbase) \ +{ \ + .chip = { \ + .label = DRVNAME, \ + .owner = THIS_MODULE, \ + .get_direction = aaeon_gpio_get_direction, \ + .direction_input = aaeon_gpio_input_set_direction, \ + .direction_output = aaeon_gpio_output_set_direction, \ + .get = aaeon_gpio_get, \ + .set = aaeon_gpio_set, \ + .base = _base, \ + .ngpio = _ngpio, \ + .can_sleep = true, \ + }, \ + .regbase = _regbase, \ +} + +static struct aaeon_gpio_bank aaeon_gpio_bank[] = { + AAEON_GPIO_BANK(0, 0, 0xF0), +}; + +static int aaeon_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + int err, retval; + u32 dev_id = 0x0; + + dev_id |= offset; + err = asus_wmi_evaluate_method(GET_DIRECTION_METHOD_ID, dev_id, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_input_set_direction(struct gpio_chip *chip, + unsigned int offset) +{ + int err, retval; + u32 dev_id; + + dev_id = BIT(16) | offset; + err = asus_wmi_evaluate_method(SET_DIRECTION_METHOD_ID, dev_id, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_output_set_direction(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int err, retval; + u32 dev_id = 0x0; + + dev_id |= offset; + err = asus_wmi_evaluate_method(SET_DIRECTION_METHOD_ID, dev_id, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + int err, retval; + u32 dev_id = 0x0; + + dev_id |= offset; + err = asus_wmi_evaluate_method(GET_LEVEL_METHOD_ID, dev_id, 0, &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + int retval; + u32 dev_id = offset; + + if (value) + dev_id = BIT(16) | dev_id; + + return asus_wmi_evaluate_method(SET_LEVEL_METHOD_ID, dev_id, 0, &retval); +} + +static int aaeon_gpio_get_number(void) +{ + int err, retval; + + err = asus_wmi_evaluate_method(GET_GPIO_NUMBER_ID, + GET_SIO_NUMBER_METHOD_ID, + 0, &retval); + if (err) + return err; + + return retval; +} + +static int __init aaeon_gpio_probe(struct platform_device *pdev) +{ + int err, i; + int dio_number = 0; + struct aaeon_gpio_data *data; + struct aaeon_gpio_bank *bank; + + /* Prevent other drivers adding this platfom device */ + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + pr_debug("AAEON Management GUID not found\n"); + return -ENODEV; + } + + dio_number = aaeon_gpio_get_number(); + if (dio_number < 0) + return -ENODEV; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->nr_bank = ARRAY_SIZE(aaeon_gpio_bank); + data->bank = aaeon_gpio_bank; + platform_set_drvdata(pdev, data); + bank = &data->bank[0]; + bank->chip.parent = &pdev->dev; + bank->chip.ngpio = dio_number; + bank->data = data; + err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank); + if (err) + pr_debug("Failed to register gpiochip %d: %d\n", i, err); + + return err; +} + +static struct platform_driver aaeon_gpio_driver = { + .driver = { + .name = "gpio-aaeon", + }, +}; + +module_platform_driver_probe(aaeon_gpio_driver, aaeon_gpio_probe); + +MODULE_ALIAS("platform:gpio-aaeon"); +MODULE_DESCRIPTION("AAEON GPIO Driver"); +MODULE_AUTHOR("Edward Lin "); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -91,6 +91,7 @@ #include #include #include +#include #include #include #include @@ -3765,6 +3766,10 @@ caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; caps->aux_support = false; + drm_object_property_set_value(&conn_base->base, + adev_to_drm(adev)->mode_config.panel_type_property, + caps->ext_caps->bits.oled ? DRM_MODE_PANEL_TYPE_OLED : DRM_MODE_PANEL_TYPE_UNKNOWN); + if (caps->ext_caps->bits.oled == 1 /* * || @@ -9074,6 +9079,8 @@ if (connector_type == DRM_MODE_CONNECTOR_eDP) { struct drm_privacy_screen *privacy_screen; + drm_connector_attach_panel_type_property(&aconnector->base); + privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); if (!IS_ERR(privacy_screen)) { drm_connector_attach_privacy_screen_provider(&aconnector->base, --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/drm_connector.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/drm_connector.c @@ -1173,6 +1173,11 @@ { DRM_MODE_LINK_STATUS_BAD, "Bad" }, }; +static const struct drm_prop_enum_list drm_panel_type_enum_list[] = { + { DRM_MODE_PANEL_TYPE_UNKNOWN, "unknown" }, + { DRM_MODE_PANEL_TYPE_OLED, "OLED" }, +}; + /** * drm_display_info_set_bus_formats - set the supported bus formats * @info: display info to store bus formats in @@ -1501,6 +1506,9 @@ * Summarizing: Only set "DPMS" when the connector is known to be enabled, * assume that a successful SETCONFIG call also sets "DPMS" to on, and * never read back the value of "DPMS" because it can be incorrect. + * panel_type: + * Immutable enum property to indicate the type of connected panel. + * Possible values are "unknown" (default) and "OLED". * PATH: * Connector path property to identify how this sink is physically * connected. Used by DP MST. This should be set by calling @@ -1851,6 +1859,13 @@ return -ENOMEM; dev->mode_config.link_status_property = prop; + prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE, "panel_type", + drm_panel_type_enum_list, + ARRAY_SIZE(drm_panel_type_enum_list)); + if (!prop) + return -ENOMEM; + dev->mode_config.panel_type_property = prop; + prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, "non-desktop"); if (!prop) return -ENOMEM; @@ -3626,3 +3641,21 @@ return tg; } EXPORT_SYMBOL(drm_mode_create_tile_group); + +/** + * drm_connector_attach_panel_type_property - attaches panel type property + * @connector: connector to attach the property on. + * + * This is used to add support for panel type detection. + */ +void drm_connector_attach_panel_type_property(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct drm_property *prop = dev->mode_config.panel_type_property; + + if (!prop) + return; + + drm_object_attach_property(&connector->base, prop, DRM_MODE_PANEL_TYPE_UNKNOWN); +} +EXPORT_SYMBOL(drm_connector_attach_panel_type_property); --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/Kconfig +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/Kconfig @@ -3,7 +3,6 @@ tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics" depends on DRM depends on X86 && PCI - depends on !PREEMPT_RT select INTEL_GTT if X86 select INTERVAL_TREE # we need shmfs for the swappable backing store, and in particular --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_crtc.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_crtc.c @@ -587,7 +587,8 @@ */ intel_psr_wait_for_idle_locked(new_crtc_state); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); crtc->debug.min_vbl = evade.min; crtc->debug.max_vbl = evade.max; @@ -605,7 +606,8 @@ return; irq_disable: - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); } #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) @@ -750,7 +752,8 @@ if (!state->base.legacy_cursor_update) intel_vrr_send_push(NULL, new_crtc_state); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_parent_vgpu_active(display)) goto out; --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_cursor.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_cursor.c @@ -919,13 +919,15 @@ */ intel_psr_wait_for_idle_locked(crtc_state); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); intel_vblank_evade(&evade); drm_crtc_vblank_put(&crtc->base); } else { - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); } if (new_plane_state->uapi.visible) { @@ -935,7 +937,8 @@ intel_plane_disable_arm(NULL, plane, crtc_state); } - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); intel_psr_unlock(crtc_state); --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_display_trace.h +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -13,6 +13,10 @@ #if !defined(__INTEL_DISPLAY_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) #define __INTEL_DISPLAY_TRACE_H__ +#if defined(CONFIG_PREEMPT_RT) && !defined(NOTRACE) +#define NOTRACE +#endif + #include #include #include --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_psr.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_psr.c @@ -49,6 +49,7 @@ #include "intel_hdmi.h" #include "intel_psr.h" #include "intel_psr_regs.h" +#include "intel_quirks.h" #include "intel_snps_phy.h" #include "intel_step.h" #include "intel_vblank.h" @@ -609,6 +610,13 @@ if (intel_dp->mst_detect == DRM_DP_MST) return; + if (intel_dp_is_edp(intel_dp) && + intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) { + drm_dbg_kms(display->drm, + "Panel Replay support not currently available for this setup\n"); + return; + } + ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, &connector->dp.panel_replay_caps.dpcd, sizeof(connector->dp.panel_replay_caps.dpcd)); --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_quirks.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_quirks.c @@ -86,6 +86,14 @@ drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n"); } +static void quirk_disable_edp_panel_replay(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + + intel_set_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY); + drm_info(display->drm, "Applying disable Panel Replay quirk\n"); +} + struct intel_quirk { int device; int subsystem_vendor; @@ -108,6 +116,8 @@ #define SINK_DEVICE_ID_ANY SINK_DEVICE_ID(0, 0, 0, 0, 0, 0) +#define DEVICE_ID_ANY 0 + /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ struct intel_dmi_quirk { void (*hook)(struct intel_display *display); @@ -251,7 +261,14 @@ .sink_oui = SINK_OUI(0x38, 0xec, 0x11), .hook = quirk_fw_sync_len, }, - + /* Dell XPS 14 DA14260 */ + { + .device = DEVICE_ID_ANY, + .subsystem_vendor = 0x1028, + .subsystem_device = 0x0db9, + .sink_oui = SINK_OUI(0x00, 0x22, 0xb9), + .hook = quirk_disable_edp_panel_replay, + }, }; void intel_init_quirks(struct intel_display *display) @@ -262,7 +279,8 @@ for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { struct intel_quirk *q = &intel_quirks[i]; - if (d->device == q->device && + if ((d->device == q->device || + q->device == DEVICE_ID_ANY) && (d->subsystem_vendor == q->subsystem_vendor || q->subsystem_vendor == PCI_ANY_ID) && (d->subsystem_device == q->subsystem_device || @@ -285,7 +303,8 @@ for (i = 0; i < ARRAY_SIZE(intel_dpcd_quirks); i++) { const struct intel_dpcd_quirk *q = &intel_dpcd_quirks[i]; - if (d->device == q->device && + if ((d->device == q->device || + q->device == DEVICE_ID_ANY) && (d->subsystem_vendor == q->subsystem_vendor || q->subsystem_vendor == PCI_ANY_ID) && (d->subsystem_device == q->subsystem_device || --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_quirks.h +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_quirks.h @@ -21,6 +21,7 @@ QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK, QUIRK_FW_SYNC_LEN, QUIRK_EDP_LIMIT_RATE_HBR2, + QUIRK_DISABLE_EDP_PANEL_REPLAY, }; void intel_init_quirks(struct intel_display *display); --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_tc.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_tc.c @@ -1187,9 +1187,10 @@ tc->max_lane_count = 4; } - drm_WARN_ON(display->drm, - (tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) && - !xelpdp_tc_phy_tcss_power_is_enabled(tc)); + if ((tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) && + !xelpdp_tc_phy_tcss_power_is_enabled(tc)) + drm_dbg_kms(display->drm, "Port %s: TCSS unexpectedly not powered\n", + tc->port_name); __tc_cold_unblock(tc, domain, tc_cold_wref); } @@ -1732,6 +1733,11 @@ if (tc->mode != TC_PORT_DISCONNECTED) mask = BIT(tc->mode); + if (tc->link_refcount > 0 && + tc->mode == TC_PORT_DP_ALT && + tc_phy_is_owned(tc)) + return true; + return tc_phy_hpd_live_status(tc) & mask; } --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/display/intel_vblank.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/display/intel_vblank.c @@ -316,6 +316,21 @@ struct intel_uncore *uncore = to_intel_uncore(display->drm); spin_unlock(&uncore->lock); } + +static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags) +__acquires(i915->uncore.lock) +{ + struct intel_uncore *uncore = to_intel_uncore(display->drm); + spin_lock_irqsave(&uncore->lock, *flags); +} + +static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags) +__releases(i915->uncore.lock) +{ + struct intel_uncore *uncore = to_intel_uncore(display->drm); + spin_unlock_irqrestore(&uncore->lock, flags); +} + #else static void intel_vblank_section_enter(struct intel_display *display) { @@ -324,6 +339,17 @@ static void intel_vblank_section_exit(struct intel_display *display) { } + +static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags) +{ + *flags = 0; +} + +static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags) +{ + if (flags) + return; +} #endif static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, @@ -360,10 +386,10 @@ * timing critical raw register reads, potentially with * preemption disabled, so the following code must not block. */ - local_irq_save(irqflags); - intel_vblank_section_enter(display); + intel_vblank_section_enter_irqf(display, &irqflags); - /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ + if (IS_ENABLED(CONFIG_PREEMPT_RT)) + preempt_disable(); /* Get optional system timestamp before query. */ if (stime) @@ -427,10 +453,10 @@ if (etime) *etime = ktime_get(); - /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ + if (IS_ENABLED(CONFIG_PREEMPT_RT)) + preempt_enable(); - intel_vblank_section_exit(display); - local_irq_restore(irqflags); + intel_vblank_section_exit_irqf(display, irqflags); /* * While in vblank, position will be negative @@ -468,13 +494,11 @@ unsigned long irqflags; int position; - local_irq_save(irqflags); - intel_vblank_section_enter(display); + intel_vblank_section_enter_irqf(display, &irqflags); position = __intel_get_crtc_scanline(crtc); - intel_vblank_section_exit(display); - local_irq_restore(irqflags); + intel_vblank_section_exit_irqf(display, irqflags); return position; } @@ -764,11 +788,13 @@ break; } - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); timeout = schedule_timeout(timeout); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); } finish_wait(wq, &wait); --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1607,7 +1607,7 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) { - if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ + if (in_atomic() || irqs_disabled() || rcu_preempt_depth()) /* inside atomic preempt-reset? */ return 0; /* --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1300,7 +1300,7 @@ * and context switches) submission. */ - spin_lock(&sched_engine->lock); + spin_lock_irq(&sched_engine->lock); /* * If the queue is higher priority than the last @@ -1400,7 +1400,7 @@ * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ - spin_unlock(&sched_engine->lock); + spin_unlock_irq(&sched_engine->lock); return; } } @@ -1426,7 +1426,7 @@ if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.sched_engine->lock); - spin_unlock(&engine->sched_engine->lock); + spin_unlock_irq(&engine->sched_engine->lock); return; /* leave this for another sibling */ } @@ -1588,7 +1588,7 @@ */ sched_engine->queue_priority_hint = queue_prio(sched_engine); i915_sched_engine_reset_on_empty(sched_engine); - spin_unlock(&sched_engine->lock); + spin_unlock_irq(&sched_engine->lock); /* * We can skip poking the HW if we ended up with exactly the same set @@ -1614,13 +1614,6 @@ } } -static void execlists_dequeue_irq(struct intel_engine_cs *engine) -{ - local_irq_disable(); /* Suspend interrupts across request submission */ - execlists_dequeue(engine); - local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */ -} - static void clear_ports(struct i915_request **ports, int count) { memset_p((void **)ports, NULL, count); @@ -2475,7 +2468,7 @@ } if (!engine->execlists.pending[0]) { - execlists_dequeue_irq(engine); + execlists_dequeue(engine); start_timeslice(engine); } --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -362,7 +362,7 @@ { int err; unsigned int sleep_period_ms = 1; - bool not_atomic = !in_atomic() && !irqs_disabled(); + bool not_atomic = !in_atomic() && !irqs_disabled() && !rcu_preempt_depth(); /* * FIXME: Have caller pass in if we are in an atomic context to avoid --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/i915_request.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/i915_request.c @@ -610,7 +610,6 @@ RQ_TRACE(request, "\n"); - GEM_BUG_ON(!irqs_disabled()); lockdep_assert_held(&engine->sched_engine->lock); /* @@ -719,7 +718,6 @@ */ RQ_TRACE(request, "\n"); - GEM_BUG_ON(!irqs_disabled()); lockdep_assert_held(&engine->sched_engine->lock); /* --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/i915_trace.h +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/i915_trace.h @@ -6,6 +6,10 @@ #if !defined(_I915_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) #define _I915_TRACE_H_ +#if defined(CONFIG_PREEMPT_RT) && !defined(NOTRACE) +#define NOTRACE +#endif + #include #include #include --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/i915/intel_uncore_trace.h +++ linux-nvidia-7.0.0/drivers/gpu/drm/i915/intel_uncore_trace.h @@ -7,6 +7,10 @@ #if !defined(__INTEL_UNCORE_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) #define __INTEL_UNCORE_TRACE_H__ +#if defined(CONFIG_PREEMPT_RT) && !defined(NOTRACE) +#define NOTRACE +#endif + #include "i915_reg_defs.h" #include --- linux-nvidia-7.0.0.orig/drivers/gpu/drm/panel/panel-edp.c +++ linux-nvidia-7.0.0/drivers/gpu/drm/panel/panel-edp.c @@ -1975,6 +1975,7 @@ EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a6a, &delay_200_500_e80, "NV140WUM-N44"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a84, &delay_200_500_e50, "NV133WUM-T01"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ac5, &delay_200_500_e50, "NV116WHM-N4C"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a84, &delay_200_500_e50, "NV133WUM-T01"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ae8, &delay_200_500_e50_p2e80, "NV140WUM-N41"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b09, &delay_200_500_e50_po2e200, "NV140FHM-NZ"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b1e, &delay_200_500_e80, "NE140QDM-N6A"), --- linux-nvidia-7.0.0.orig/drivers/hwmon/Kconfig +++ linux-nvidia-7.0.0/drivers/hwmon/Kconfig @@ -38,6 +38,18 @@ comment "Native drivers" +config SENSORS_AAEON + tristate "AAEON hwmon driver" + depends on X86 + depends on UBUNTU_ODM_DRIVERS + select MFD_AAEON + help + This hwmon driver adds support for reporting temperature or fan + speed and voltage on Single Board Computers produced by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + config SENSORS_ABITUGURU tristate "Abit uGuru (rev 1 & 2)" depends on (X86 && DMI) || COMPILE_TEST && HAS_IOPORT --- linux-nvidia-7.0.0.orig/drivers/hwmon/Makefile +++ linux-nvidia-7.0.0/drivers/hwmon/Makefile @@ -15,6 +15,7 @@ # Native drivers # asb100, then w83781d go first, as they can override other drivers' addresses. +obj-$(CONFIG_SENSORS_AAEON) += hwmon-aaeon.o obj-$(CONFIG_SENSORS_ASB100) += asb100.o obj-$(CONFIG_SENSORS_W83627HF) += w83627hf.o obj-$(CONFIG_SENSORS_W83773G) += w83773g.o --- linux-nvidia-7.0.0.orig/drivers/hwmon/hwmon-aaeon.c +++ linux-nvidia-7.0.0/drivers/hwmon/hwmon-aaeon.c @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AAEON HWMON driver + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Edward Lin + * Author: Kunyang Fan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "hwmon-aaeon" + +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define AAEON_VERSION_METHOD_ID 0x00000000 +#define HWM_INFORMATION_METHOD_ID 0x00030000 +#define HWM_METHOD_ID 0x00030001 + +#define BITMAP_TEMP_ARG 0x12 +#define BITMAP_FAN_ARG 0x13 +#define BITMAP_VOLTAGE_ARG 0x14 + +#define SENSOR_TEMP_NUMBER 0 +#define SENSOR_FAN_NUMBER 1 +#define SENSOR_VOLTAGE_NUMBER 2 +#define SENSOR_MAX_NUMBER 2 + +static ssize_t aaeon_show_sensor(struct device *dev, + struct device_attribute *devattr, char *buf); +static ssize_t aaeon_show_sensor_name(struct device *dev, + struct device_attribute *devattr, + char *buf); +static ssize_t aaeon_show_version(struct device *dev, + struct device_attribute *devattr, char *buf); +static ssize_t name_show(struct device *dev, struct device_attribute *devattr, + char *buf); +static int aaeon_get_version(void); +static int aaeon_hwmon_probe(struct platform_device *pdev); +static void aaeon_hwmon_remove(struct platform_device *pdev); + +static const char * const temp_sensors_name_table[] = { + "CPU_Temp", + "SYS1_Temp", + "SYS2_Temp", +}; + +static const char * const temp_sensors_name_table_V3[] = { + "SYS_Temp", + "CPU_Temp", +}; + +static const char * const fan_sensors_name_table[] = { + "CPU_FAN", + "SYS1_FAN", + "SYS2_FAN", + "Chasis1_FAN", + "Chasis2_FAN", +}; + +static const char * const fan_sensors_name_table_V3[] = { + "Chasis_FAN", + "CPU_FAN", +}; + +static const char * const voltage_sensors_name_table[] = { + "VCORE_Voltage", + "VMEM_Voltage", + "+12_Voltage", + "+5_Voltage", + "+3.3_Voltage", + "+1.8_Voltage", + "5VSB_Voltage", + "3VSB_Voltage", + "VBAT_Voltage", +}; + +static const char * const voltage_sensors_name_table_V3[] = { + "VCORE_Voltage", + "+5_Voltage", + "AVCC_Voltage", + "+3.3_Voltage", + "+12_Voltage", + "VCOREREFIN_Voltage", + "VIN4_Voltage", + "3VSB_Voltage", + "VBAT_Voltage", +}; + +struct aaeon_hwmon_data { + struct device *hwmon_dev; + int bfpi_version; + u32 temp_bitmap; + u32 fan_bitmap; + u32 voltage_bitmap; + unsigned int sensors_number[SENSOR_MAX_NUMBER + 1]; + const char * const *temp_names; + const char * const *fan_names; + const char * const *voltage_names; +}; + +/* Temperature attributes */ +static struct sensor_device_attribute_2 temp_sys_nodes_atts[] = { + SENSOR_ATTR_2(temp1_input, 0444, aaeon_show_sensor, NULL, + SENSOR_TEMP_NUMBER, 0), + SENSOR_ATTR_2(temp1_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_TEMP_NUMBER, 0), + SENSOR_ATTR_2(temp2_input, 0444, aaeon_show_sensor, NULL, + SENSOR_TEMP_NUMBER, 1), + SENSOR_ATTR_2(temp2_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_TEMP_NUMBER, 1), + SENSOR_ATTR_2(temp3_input, 0444, aaeon_show_sensor, NULL, + SENSOR_TEMP_NUMBER, 2), + SENSOR_ATTR_2(temp3_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_TEMP_NUMBER, 2), +}; + +/* Cooler Fan attributes */ +static struct sensor_device_attribute_2 fan_sys_nodes_atts[] = { + SENSOR_ATTR_2(fan1_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 0), + SENSOR_ATTR_2(fan1_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 0), + SENSOR_ATTR_2(fan2_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 1), + SENSOR_ATTR_2(fan2_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 1), + SENSOR_ATTR_2(fan3_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 2), + SENSOR_ATTR_2(fan3_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 2), + SENSOR_ATTR_2(fan4_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 3), + SENSOR_ATTR_2(fan4_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 3), + SENSOR_ATTR_2(fan5_input, 0444, aaeon_show_sensor, NULL, + SENSOR_FAN_NUMBER, 4), + SENSOR_ATTR_2(fan5_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_FAN_NUMBER, 4), +}; + +/* Voltage attributes */ +static struct sensor_device_attribute_2 voltage_sys_nodes_atts[] = { + SENSOR_ATTR_2(in1_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 0), + SENSOR_ATTR_2(in1_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 0), + SENSOR_ATTR_2(in2_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 1), + SENSOR_ATTR_2(in2_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 1), + SENSOR_ATTR_2(in3_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 2), + SENSOR_ATTR_2(in3_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 2), + SENSOR_ATTR_2(in4_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 3), + SENSOR_ATTR_2(in4_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 3), + SENSOR_ATTR_2(in5_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 4), + SENSOR_ATTR_2(in5_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 4), + SENSOR_ATTR_2(in6_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 5), + SENSOR_ATTR_2(in6_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 5), + SENSOR_ATTR_2(in7_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 6), + SENSOR_ATTR_2(in7_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 6), + SENSOR_ATTR_2(in8_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 7), + SENSOR_ATTR_2(in8_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 7), + SENSOR_ATTR_2(in9_input, 0444, aaeon_show_sensor, NULL, + SENSOR_VOLTAGE_NUMBER, 8), + SENSOR_ATTR_2(in9_label, 0444, aaeon_show_sensor_name, NULL, + SENSOR_VOLTAGE_NUMBER, 8), + +}; + +static struct sensor_device_attribute_2 info_sys_nodes_atts[] = { + /* WMI version Information */ + SENSOR_ATTR_2(AAEON_VERSION, 0444, aaeon_show_version, NULL, 0, 0), +}; + +DEVICE_ATTR_RO(name); +static ssize_t name_show(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + return sprintf(buf, "%s\n", DRVNAME); +} + +static ssize_t aaeon_show_version(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct aaeon_hwmon_data *data = + (struct aaeon_hwmon_data *)dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", data->bfpi_version); +} + +static ssize_t aaeon_show_sensor_name(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + u8 nr = to_sensor_dev_attr_2(devattr)->nr; + u8 index = to_sensor_dev_attr_2(devattr)->index; + struct aaeon_hwmon_data *data = + (struct aaeon_hwmon_data *)dev_get_drvdata(dev); + + if (nr > SENSOR_MAX_NUMBER || index >= data->sensors_number[nr]) { + pr_debug("Can not check the device"); + return -1; + } + + switch (nr) { + case SENSOR_TEMP_NUMBER: + return sprintf(buf, "%s\n", data->temp_names[index]); + case SENSOR_FAN_NUMBER: + return sprintf(buf, "%s\n", data->fan_names[index]); + case SENSOR_VOLTAGE_NUMBER: + return sprintf(buf, "%s\n", data->voltage_names[index]); + default: + break; + } + + return 0; +} + +static ssize_t aaeon_show_sensor(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + u8 nr = to_sensor_dev_attr_2(devattr)->nr; + u8 index = to_sensor_dev_attr_2(devattr)->index; + u32 dev_id; + int retval, err; + struct aaeon_hwmon_data *data = + (struct aaeon_hwmon_data *)dev_get_drvdata(dev); + + if (nr > SENSOR_MAX_NUMBER || index >= data->sensors_number[nr]) { + pr_debug("Can not check the device"); + return -1; + } + + /* For the V3 version, index need offset */ + if (data->bfpi_version == 0x03 && nr != SENSOR_VOLTAGE_NUMBER) + index++; + + dev_id = (index << 12) | (nr << 8); + err = asus_wmi_evaluate_method(HWM_METHOD_ID, dev_id, 0, &retval); + if (err) + return err; + + /* For the V3 version, need to convert the raw value*/ + if (nr == SENSOR_VOLTAGE_NUMBER && data->bfpi_version == 0x03) { + switch (index) { + case 0: /* VCORE */ + retval = retval * 16; + break; + case 1: /* +5V */ + retval = (retval * 2008) / 50; + break; + case 2: /* AVCC */ + retval = retval * 16; + break; + case 3: /* +3.3V */ + retval = retval * 16; + break; + case 4: /* +12V */ + retval = retval * 96; + break; + case 5: /* VCOREREFIN */ + retval = (retval * 552) / 41; + break; + case 6: /* VIN4 */ + retval = retval * 8; + break; + case 7: /* 3VSB */ + retval = retval * 16; + break; + case 8: /* VBAT */ + retval = retval * 16; + break; + default: + break; + } + } else if (nr == SENSOR_TEMP_NUMBER && data->bfpi_version == 0x03) + retval = retval * 1000; + + return sprintf(buf, "%d\n", retval); +} + +static int aaeon_hwmon_create_sub_sysfs_fs(struct platform_device *pdev, + struct sensor_device_attribute_2 *attr, + int sensor_number, + u32 sensor_mask, + int bfpi_version) +{ + int i, err = 0; + + for (i = 0; i < sensor_number; i++) { + if (bfpi_version == 0x03 || sensor_mask & BIT(i)) { + err = device_create_file(&pdev->dev, &attr[2 * i].dev_attr); + if (err) + break; + err = device_create_file(&pdev->dev, &attr[2 * i + 1].dev_attr); + if (err) + break; + } + } + + return err; +} + +static int +aaeon_hwmon_create_sysfs_files(struct platform_device *pdev, struct aaeon_hwmon_data *data) +{ + int err; + + /* register sysfs interface files */ + err = device_create_file(&pdev->dev, &dev_attr_name); + if (err) + return err; + + /* registe sysfs to dump sensors BFPI version */ + err = device_create_file(&pdev->dev, &info_sys_nodes_atts[0].dev_attr); + if (err) + return err; + + /* create temperature name and value node */ + err = aaeon_hwmon_create_sub_sysfs_fs(pdev, temp_sys_nodes_atts, + data->sensors_number[SENSOR_TEMP_NUMBER], + data->temp_bitmap, data->bfpi_version); + if (err) + return err; + + /* create fan name and value node */ + err = aaeon_hwmon_create_sub_sysfs_fs(pdev, fan_sys_nodes_atts, + data->sensors_number[SENSOR_FAN_NUMBER], + data->fan_bitmap, data->bfpi_version); + if (err) + return err; + + /* create voltage name and value node */ + err = aaeon_hwmon_create_sub_sysfs_fs(pdev, voltage_sys_nodes_atts, + data->sensors_number[SENSOR_VOLTAGE_NUMBER], + data->voltage_bitmap, data->bfpi_version); + if (err) + return err; + + return 0; +} + +static void aaeon_hwmon_remove_sub_sysfs_fs(struct platform_device *pdev, + struct sensor_device_attribute_2 *attr, + int sensor_number, + u32 sensor_mask, + int bfpi_version) +{ + int i; + + for (i = 0; i < sensor_number; i++) { + if (bfpi_version == 0x03 || sensor_mask & BIT(i)) { + device_remove_file(&pdev->dev, &attr[2 * i].dev_attr); + device_remove_file(&pdev->dev, &attr[2 * i + 1].dev_attr); + } + } +} + +static void +aaeon_hwmon_remove_sysfs_files(struct platform_device *pdev, + struct aaeon_hwmon_data *data) +{ + /* degister sysfs interface files */ + device_remove_file(&pdev->dev, &dev_attr_name); + + /* degiste sysfs to dump sensors BFPI version */ + device_remove_file(&pdev->dev, &info_sys_nodes_atts[0].dev_attr); + + /* remove temperature name and value node */ + aaeon_hwmon_remove_sub_sysfs_fs(pdev, temp_sys_nodes_atts, + data->sensors_number[SENSOR_TEMP_NUMBER], + data->temp_bitmap, + data->bfpi_version); + + /* remove fan name and value node */ + aaeon_hwmon_remove_sub_sysfs_fs(pdev, fan_sys_nodes_atts, + data->sensors_number[SENSOR_FAN_NUMBER], + data->fan_bitmap, + data->bfpi_version); + + /* remove voltage name and value node */ + aaeon_hwmon_remove_sub_sysfs_fs(pdev, voltage_sys_nodes_atts, + data->sensors_number[SENSOR_VOLTAGE_NUMBER], + data->voltage_bitmap, + data->bfpi_version); +} + +static void aaeon_hwmon_remove(struct platform_device *pdev) +{ + struct aaeon_hwmon_data *data = platform_get_drvdata(pdev); + + if (data->hwmon_dev) + hwmon_device_unregister(data->hwmon_dev); + + aaeon_hwmon_remove_sysfs_files(pdev, data); + + return; +} + +static int aaeon_get_version(void) +{ + int err, retval; + u32 dev_id = 0x00; + + err = asus_wmi_evaluate_method(AAEON_VERSION_METHOD_ID, dev_id, 0, + &retval); + if (err) + return err; + + return retval; +} + +static int aaeon_hwmon_init_drv_data(struct aaeon_hwmon_data *data) +{ + int err; + + data->bfpi_version = aaeon_get_version(); + if (data->bfpi_version < 0) { + pr_debug("Error BFPI verion\n"); + return -1; + } + + if (data->bfpi_version == 0x03) { + /* set the number of bits in temp bitmap */ + data->sensors_number[SENSOR_TEMP_NUMBER] = + ARRAY_SIZE(temp_sensors_name_table_V3); + data->temp_names = temp_sensors_name_table_V3; + + /* set the number of bits in fan bitmap */ + data->sensors_number[SENSOR_FAN_NUMBER] = + ARRAY_SIZE(fan_sensors_name_table_V3); + data->fan_names = fan_sensors_name_table_V3; + + /* set the number of bits in voltage bitmap */ + data->sensors_number[SENSOR_VOLTAGE_NUMBER] = + ARRAY_SIZE(voltage_sensors_name_table_V3); + data->voltage_names = voltage_sensors_name_table_V3; + } else { + /* set the number of bits in temp bitmap */ + data->sensors_number[SENSOR_TEMP_NUMBER] = + ARRAY_SIZE(temp_sensors_name_table); + data->temp_names = temp_sensors_name_table; + + /* set the number of bits in fan bitmap */ + data->sensors_number[SENSOR_FAN_NUMBER] = + ARRAY_SIZE(fan_sensors_name_table); + data->fan_names = fan_sensors_name_table; + + /* set the number of bits in voltage bitmap */ + data->sensors_number[SENSOR_VOLTAGE_NUMBER] = + ARRAY_SIZE(voltage_sensors_name_table); + data->voltage_names = voltage_sensors_name_table; + } + + /* get temp supported bitmap */ + err = asus_wmi_evaluate_method(HWM_INFORMATION_METHOD_ID, + BITMAP_TEMP_ARG, 0, &data->temp_bitmap); + if (err) + return err; + + /* get fan supported bitmap */ + err = asus_wmi_evaluate_method(HWM_INFORMATION_METHOD_ID, + BITMAP_FAN_ARG, 0, &data->fan_bitmap); + if (err) + return err; + + /* get voltage supported bitmap */ + err = asus_wmi_evaluate_method(HWM_INFORMATION_METHOD_ID, + BITMAP_VOLTAGE_ARG, 0, &data->voltage_bitmap); + if (err) + return err; + + return 0; +} + +static int aaeon_hwmon_probe(struct platform_device *pdev) +{ + int err; + struct aaeon_hwmon_data *data; + + pr_debug("aaeon hwomon device probe (support V3)!\n"); + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + pr_info("AAEON Management GUID not found\n"); + return -ENODEV; + } + + data = devm_kzalloc(&pdev->dev, sizeof(struct aaeon_hwmon_data), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + err = aaeon_hwmon_init_drv_data(data); + if (err) { + pr_info("Error to get sensor support bitmap\n"); + goto exit; + } + + if (data->bfpi_version != 0x03 && data->temp_bitmap == 0 && + data->fan_bitmap == 0 && data->voltage_bitmap == 0) { + pr_debug("No sensors found\n"); + err = -ENODEV; + goto exit; + } + + platform_set_drvdata(pdev, data); + err = aaeon_hwmon_create_sysfs_files(pdev, data); + if (err) + goto exit; + + data->hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, + "AAEON_HWM", + data, + NULL, + NULL); + if (IS_ERR(data->hwmon_dev)) { + err = PTR_ERR(data->hwmon_dev); + data->hwmon_dev = NULL; + goto exit_unregister_sysfs; + } + + return 0; + +exit_unregister_sysfs: + aaeon_hwmon_remove(pdev); +exit: + return err; +} + +static struct platform_driver aaeon_hwmon_driver = { + .driver = { + .name = DRVNAME, + .owner = THIS_MODULE, + }, + .probe = aaeon_hwmon_probe, + .remove = aaeon_hwmon_remove, +}; + +module_platform_driver_probe(aaeon_hwmon_driver, aaeon_hwmon_probe); + +MODULE_ALIAS("platform:hwmon-aaeon"); +MODULE_DESCRIPTION("AAEON Hardware Monitoring Driver"); +MODULE_AUTHOR("Edward Lin "); +MODULE_AUTHOR("Kunyang Fan "); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); --- linux-nvidia-7.0.0.orig/drivers/i2c/busses/i2c-i801.c +++ linux-nvidia-7.0.0/drivers/i2c/busses/i2c-i801.c @@ -988,6 +988,14 @@ iowrite8(priv->original_slvcmd, SMBSLVCMD(priv)); } +static inline __maybe_unused void __i801_register_spd(struct i801_priv *priv) +{ + if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) + i2c_register_spd_write_disable(&priv->adapter); + else + i2c_register_spd_write_enable(&priv->adapter); +} + static const struct i2c_algorithm smbus_algorithm = { .smbus_xfer = i801_access, .functionality = i801_func, @@ -1170,6 +1178,19 @@ } } +#ifdef CONFIG_I2C_I801_MUX +static void i801_register_spd(struct i801_priv *priv) +{ + if (!priv->mux_pdev) + __i801_register_spd(priv); +} +#else +static void i801_register_spd(struct i801_priv *priv) +{ + __i801_register_spd(priv); +} +#endif + /* Register optional targets */ static void i801_probe_optional_targets(struct i801_priv *priv) { @@ -1190,10 +1211,7 @@ dmi_walk(dmi_check_onboard_devices, &priv->adapter); /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ -#ifdef CONFIG_I2C_I801_MUX - if (!priv->mux_pdev) -#endif - i2c_register_spd_write_enable(&priv->adapter); + i801_register_spd(priv); } #else static void __init input_apanel_init(void) {} @@ -1296,7 +1314,7 @@ return NOTIFY_DONE; /* Call i2c_register_spd for muxed child segments */ - i2c_register_spd_write_enable(to_i2c_adapter(dev)); + __i801_register_spd(priv); return NOTIFY_OK; } --- linux-nvidia-7.0.0.orig/drivers/input/mouse/cypress_ps2.c +++ linux-nvidia-7.0.0/drivers/input/mouse/cypress_ps2.c @@ -348,7 +348,9 @@ if (error) return error; +#if ( CYPRESS_SIMULATED_MT != 1 ) __set_bit(INPUT_PROP_SEMI_MT, input->propbit); +#endif input_abs_set_res(input, ABS_X, cytp->tp_res_x); input_abs_set_res(input, ABS_Y, cytp->tp_res_y); @@ -435,6 +437,22 @@ ((packet[5] & 0x0f) << 8) | packet[7]; if (cytp->mode & CYTP_BIT_ABS_PRESSURE) report_data->contacts[1].z = report_data->contacts[0].z; +#if ( CYPRESS_SIMULATED_MT == 1 ) + /* simulate contact positions for >2 fingers */ + if ( report_data->contact_cnt >= 3 ) { + int i; + for ( i=1; icontact_cnt; i++ ) { + report_data->contacts[i].x = + report_data->contacts[0].x + + 100*(i)*((i%2)?-1:1); + report_data->contacts[i].y = + report_data->contacts[0].y; + if (cytp->mode & CYTP_BIT_ABS_PRESSURE) + report_data->contacts[i].z = + report_data->contacts[0].z; + } + } +#endif } report_data->left = (header_byte & BTN_LEFT_BIT) ? 1 : 0; --- linux-nvidia-7.0.0.orig/drivers/input/mouse/cypress_ps2.h +++ linux-nvidia-7.0.0/drivers/input/mouse/cypress_ps2.h @@ -125,7 +125,18 @@ #define RESP_REMOTE_BIT 0x40 #define RESP_SMBUS_BIT 0x80 -#define CYTP_MAX_MT_SLOTS 2 +/* + * CYPRESS_SIMULATED_MT + * set to 1 for simulated multitouch (up to 5 contact points) + * set to 0 for SEMI_MT (only 2 corner points, and count of fingers) + */ +#define CYPRESS_SIMULATED_MT 1 + +#if ( CYPRESS_SIMULATED_MT == 1 ) +# define CYTP_MAX_MT_SLOTS 5 +#else +# define CYTP_MAX_MT_SLOTS 2 +#endif struct cytp_contact { int x; --- linux-nvidia-7.0.0.orig/drivers/input/serio/i8042.c +++ linux-nvidia-7.0.0/drivers/input/serio/i8042.c @@ -23,6 +23,7 @@ #include #include #include +#include #include @@ -183,6 +184,24 @@ static i8042_filter_t i8042_platform_filter; static void *i8042_platform_filter_context; +static int __init i8042_set_noaux(const struct dmi_system_id *dmi) +{ + i8042_noaux = true; + return 1; +} + +static const struct dmi_system_id i8042_quirks[] = { + { + .callback = i8042_set_noaux, + .ident = "Dell laptop", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Precision 5550"), + }, + }, + {}, +}; + void i8042_lock_chip(void) { mutex_lock(&i8042_mutex); @@ -622,7 +641,7 @@ if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { i8042_ctr &= ~I8042_CTR_KBDINT; i8042_ctr |= I8042_CTR_KBDDIS; - pr_err("Failed to enable KBD port\n"); + pr_info("Failed to enable KBD port\n"); return -EIO; } @@ -641,7 +660,7 @@ if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { i8042_ctr &= ~I8042_CTR_AUXINT; i8042_ctr |= I8042_CTR_AUXDIS; - pr_err("Failed to enable AUX port\n"); + pr_info("Failed to enable AUX port\n"); return -EIO; } @@ -733,7 +752,7 @@ i8042_ctr &= ~I8042_CTR_AUXINT; if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { - pr_err("Failed to disable AUX port, can't use MUX\n"); + pr_info("Failed to disable AUX port, can't use MUX\n"); return -EIO; } @@ -942,25 +961,28 @@ { unsigned char param; int i = 0; + int ret; /* * We try this 5 times; on some really fragile systems this does not * take the first time... */ - do { + while (i++ < 5) { - if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { - pr_err("i8042 controller selftest timeout\n"); - return -ENODEV; - } - - if (param == I8042_RET_CTL_TEST) + ret = i8042_command(¶m, I8042_CMD_CTL_TEST); + if (ret) + pr_info("i8042 controller selftest timeout (%d/5)\n", i); + else if (param == I8042_RET_CTL_TEST) return 0; + else + dbg("i8042 controller selftest: %#x != %#x\n", + param, I8042_RET_CTL_TEST); - dbg("i8042 controller selftest: %#x != %#x\n", - param, I8042_RET_CTL_TEST); msleep(50); - } while (i++ < 5); + } + + if (ret) + return -ENODEV; #ifdef CONFIG_X86 /* @@ -972,7 +994,7 @@ pr_info("giving up on controller selftest, continuing anyway...\n"); return 0; #else - pr_err("i8042 controller selftest failed\n"); + pr_info("i8042 controller selftest failed\n"); return -EIO; #endif } @@ -1553,6 +1575,8 @@ i8042_dritek_enable(); #endif + dmi_check_system(i8042_quirks); + if (!i8042_noaux) { error = i8042_setup_aux(); if (error && error != -ENODEV && error != -EBUSY) --- linux-nvidia-7.0.0.orig/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ linux-nvidia-7.0.0/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -3730,11 +3731,106 @@ if (IS_HISI_PTT_DEVICE(pdev)) return IOMMU_DOMAIN_IDENTITY; + + if (pdev->vendor == PCI_VENDOR_ID_NVIDIA && + (pdev->device == 0x2E12 || pdev->device == 0x2E2A || + pdev->device == 0x2E2B)) + return IOMMU_DOMAIN_DMA; } return 0; } +static int arm_smmu_group_set_mpam(struct iommu_group *group, u16 partid, + u8 pmg) +{ + int i; + u32 sid; + unsigned long flags; + struct arm_smmu_ste *step; + struct iommu_domain *domain; + struct arm_smmu_device *smmu; + struct arm_smmu_master *master; + struct arm_smmu_cmdq_batch cmds; + struct arm_smmu_domain *smmu_domain; + struct arm_smmu_cmdq_ent cmd = { + .opcode = CMDQ_OP_CFGI_STE, + .cfgi = { + .leaf = true, + }, + }; + struct arm_smmu_master_domain *master_domain; + + domain = iommu_get_domain_for_group(group); + smmu_domain = to_smmu_domain(domain); + if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_MPAM)) + return -EIO; + smmu = smmu_domain->smmu; + + arm_smmu_cmdq_batch_init(smmu, &cmds, &cmd); + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master_domain, &smmu_domain->devices, + devices_elm) { + master = master_domain->master; + + for (i = 0; i < master->num_streams; i++) { + sid = master->streams[i].id; + step = arm_smmu_get_step_for_sid(smmu, sid); + + /* These need locking if the VMSPtr is ever used */ + step->data[4] = FIELD_PREP(STRTAB_STE_4_PARTID, partid); + step->data[5] = FIELD_PREP(STRTAB_STE_5_PMG, pmg); + + cmd.cfgi.sid = sid; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); + } + + master->partid = partid; + master->pmg = pmg; + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_cmdq_batch_submit(smmu, &cmds); + + return 0; +} + +static int arm_smmu_group_get_mpam(struct iommu_group *group, u16 *partid, + u8 *pmg) +{ + int err = -EINVAL; + unsigned long flags; + struct iommu_domain *domain; + struct arm_smmu_master *master; + struct arm_smmu_domain *smmu_domain; + struct arm_smmu_master_domain *master_domain; + + domain = iommu_get_domain_for_group(group); + smmu_domain = to_smmu_domain(domain); + if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_MPAM)) + return -EIO; + + if (!partid && !pmg) + return 0; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master_domain, &smmu_domain->devices, + devices_elm) { + master = master_domain->master; + if (master) { + if (partid) + *partid = master->partid; + if (pmg) + *pmg = master->pmg; + err = 0; + } + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + return err; +} + static const struct iommu_ops arm_smmu_ops = { .identity_domain = &arm_smmu_identity_domain, .blocked_domain = &arm_smmu_blocked_domain, @@ -3748,6 +3844,8 @@ .device_group = arm_smmu_device_group, .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, + .get_group_qos_params = arm_smmu_group_get_mpam, + .set_group_qos_params = arm_smmu_group_set_mpam, .page_response = arm_smmu_page_response, .def_domain_type = arm_smmu_def_domain_type, .get_viommu_size = arm_smmu_get_viommu_size, @@ -4365,6 +4463,29 @@ hw_features, fw_features); } +static void arm_smmu_mpam_register_smmu(struct arm_smmu_device *smmu) +{ + u16 partid_max; + u8 pmg_max; + u32 reg; + + if (!IS_ENABLED(CONFIG_ARM64_MPAM)) + return; + + if (!(smmu->features & ARM_SMMU_FEAT_MPAM)) + return; + + reg = readl_relaxed(smmu->base + ARM_SMMU_MPAMIDR); + if (!reg) + return; + + partid_max = FIELD_GET(SMMU_MPAMIDR_PARTID_MAX, reg); + pmg_max = FIELD_GET(SMMU_MPAMIDR_PMG_MAX, reg); + + if (mpam_register_requestor(partid_max, pmg_max)) + smmu->features &= ~ARM_SMMU_FEAT_MPAM; +} + static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) { u32 reg; @@ -4512,6 +4633,8 @@ smmu->features |= ARM_SMMU_FEAT_RANGE_INV; if (FIELD_GET(IDR3_FWB, reg)) smmu->features |= ARM_SMMU_FEAT_S2FWB; + if (FIELD_GET(IDR3_MPAM, reg)) + smmu->features |= ARM_SMMU_FEAT_MPAM; if (FIELD_GET(IDR3_BBM, reg) == 2) smmu->features |= ARM_SMMU_FEAT_BBML2; @@ -4577,8 +4700,11 @@ if (arm_smmu_sva_supported(smmu)) smmu->features |= ARM_SMMU_FEAT_SVA; + arm_smmu_mpam_register_smmu(smmu); + dev_info(smmu->dev, "oas %lu-bit (features 0x%08x)\n", smmu->oas, smmu->features); + return 0; } --- linux-nvidia-7.0.0.orig/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ linux-nvidia-7.0.0/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -58,6 +58,7 @@ #define IDR1_SIDSIZE GENMASK(5, 0) #define ARM_SMMU_IDR3 0xc +#define IDR3_MPAM (1 << 7) #define IDR3_FWB (1 << 8) #define IDR3_RIL (1 << 10) #define IDR3_BBM GENMASK(12, 11) @@ -169,6 +170,10 @@ #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc +#define ARM_SMMU_MPAMIDR 0x130 +#define SMMU_MPAMIDR_PARTID_MAX GENMASK(15, 0) +#define SMMU_MPAMIDR_PMG_MAX GENMASK(23, 16) + #define ARM_SMMU_REG_SZ 0xe00 /* Common MSI config fields */ @@ -270,6 +275,7 @@ #define STRTAB_STE_1_MEV (1UL << 19) #define STRTAB_STE_1_S2FWB (1UL << 25) #define STRTAB_STE_1_S1STALLD (1UL << 27) +#define STRTAB_STE_1_S1MPAM (1UL << 26) #define STRTAB_STE_1_EATS GENMASK_ULL(29, 28) #define STRTAB_STE_1_EATS_ABT 0UL @@ -300,6 +306,10 @@ #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) +#define STRTAB_STE_4_PARTID GENMASK_ULL(31, 16) + +#define STRTAB_STE_5_PMG GENMASK_ULL(7, 0) + /* These bits can be controlled by userspace for STRTAB_STE_0_CFG_NESTED */ #define STRTAB_STE_0_NESTING_ALLOWED \ cpu_to_le64(STRTAB_STE_0_V | STRTAB_STE_0_CFG | STRTAB_STE_0_S1FMT | \ @@ -767,6 +777,7 @@ #define ARM_SMMU_FEAT_HD (1 << 22) #define ARM_SMMU_FEAT_S2FWB (1 << 23) #define ARM_SMMU_FEAT_BBML2 (1 << 24) +#define ARM_SMMU_FEAT_MPAM (1 << 25) u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) @@ -850,6 +861,8 @@ bool stall_enabled; unsigned int ssid_bits; unsigned int iopf_refcount; + u16 partid; + u8 pmg; }; /* SMMU private data for an IOMMU domain */ --- linux-nvidia-7.0.0.orig/drivers/iommu/intel/iommu.c +++ linux-nvidia-7.0.0/drivers/iommu/intel/iommu.c @@ -37,6 +37,14 @@ #define IS_GFX_DEVICE(pdev) pci_is_display(pdev) #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB) #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) +#define IS_INTEL_IPU(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL && \ + ((pdev)->device == 0xa75d || \ + (pdev)->device == 0x9a19 || \ + (pdev)->device == 0x9a39 || \ + (pdev)->device == 0x7d19 || \ + (pdev)->device == 0x4e19 || \ + (pdev)->device == 0x465d || \ + (pdev)->device == 0x1919)) #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) #define IOAPIC_RANGE_START (0xfee00000) @@ -202,12 +210,14 @@ int intel_iommu_enabled = 0; EXPORT_SYMBOL_GPL(intel_iommu_enabled); +static int dmar_map_ipu = 1; static int intel_iommu_superpage = 1; static int iommu_identity_mapping; static int iommu_skip_te_disable; static int disable_igfx_iommu; #define IDENTMAP_AZALIA 4 +#define IDENTMAP_IPU 8 const struct iommu_ops intel_iommu_ops; @@ -1398,6 +1408,9 @@ if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) return IOMMU_DOMAIN_IDENTITY; + + if ((iommu_identity_mapping & IDENTMAP_IPU) && IS_INTEL_IPU(pdev)) + return IOMMU_DOMAIN_IDENTITY; } return 0; @@ -1688,6 +1701,9 @@ iommu_set_root_entry(iommu); } + if (!dmar_map_ipu) + iommu_identity_mapping |= IDENTMAP_IPU; + check_tylersburg_isoch(); /* @@ -3933,6 +3949,18 @@ disable_igfx_iommu = 1; } +static void quirk_iommu_ipu(struct pci_dev *dev) +{ + if (!IS_INTEL_IPU(dev)) + return; + + if (risky_device(dev)) + return; + + pci_info(dev, "Passthrough IOMMU for integrated Intel IPU\n"); + dmar_map_ipu = 0; +} + /* G4x/GM45 integrated gfx dmar support is totally busted. */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_igfx); @@ -3971,6 +3999,77 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx); +/* SKL */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1906, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1913, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x190E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1915, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1902, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x190A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x190B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1917, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1916, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1921, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1912, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x191D, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1923, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1926, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1927, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x192A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x192B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x192D, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1932, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x193A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x193B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x193D, quirk_iommu_igfx); + +/* KBL */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5902, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5906, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5908, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x590A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x590B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x590E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5912, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5913, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5915, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5916, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5917, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591A, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591B, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591D, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x591E, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5921, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5923, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5926, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5927, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x593B, quirk_iommu_igfx); + +/* CML */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9B21, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA2, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA4, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA5, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BA8, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BAA, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BAC, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC2, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC4, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC5, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC6, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BC8, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BE6, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BF6, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9B41, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BCA, quirk_iommu_igfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9BCC, quirk_iommu_igfx); + +/* disable IPU dmar support */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_iommu_ipu); + static void quirk_iommu_rwbf(struct pci_dev *dev) { if (risky_device(dev)) --- linux-nvidia-7.0.0.orig/drivers/iommu/io-pgtable-arm.c +++ linux-nvidia-7.0.0/drivers/iommu/io-pgtable-arm.c @@ -75,6 +75,7 @@ #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63) #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53) +#define ARM_LPAE_PTE_CONT (((arm_lpae_iopte)1) << 52) #define ARM_LPAE_PTE_DBM (((arm_lpae_iopte)1) << 51) #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10) #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8) @@ -320,6 +321,27 @@ sizeof(*ptep) * num_entries, DMA_TO_DEVICE); } +static int arm_lpae_cont_ptes(int lvl, struct arm_lpae_io_pgtable *data) +{ + switch (ARM_LPAE_GRANULE(data)) { + case SZ_4K: + if (lvl >= 1) + return 16; + break; + case SZ_16K: + if (lvl == 2) + return 32; + else if (lvl == 3) + return 128; + break; + case SZ_64K: + if (lvl >= 2) + return 32; + break; + } + return 1; +} + static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg, int num_entries) { for (int i = 0; i < num_entries; i++) @@ -329,13 +351,35 @@ __arm_lpae_sync_pte(ptep, num_entries, cfg); } +static bool arm_lpae_use_contpte(struct arm_lpae_io_pgtable *data, + unsigned long iova, phys_addr_t paddr, + int lvl, int num_entries, int i) +{ + size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data); + int cont_ptes = arm_lpae_cont_ptes(lvl, data); + int contmask = cont_ptes - 1; + int contpte_addr_mask = sz * cont_ptes - 1; + int map_idx_start, tbl_idx; + + if ((paddr & contpte_addr_mask) != (iova & contpte_addr_mask)) + return false; + + map_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data); + tbl_idx = map_idx_start + i; + if (((tbl_idx & contmask) <= i) && + (tbl_idx < ((map_idx_start + num_entries) & ~contmask))) + return true; + + return false; +} + static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, struct iommu_iotlb_gather *gather, unsigned long iova, size_t size, size_t pgcount, int lvl, arm_lpae_iopte *ptep); static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, - phys_addr_t paddr, arm_lpae_iopte prot, + unsigned long iova, phys_addr_t paddr, arm_lpae_iopte prot, int lvl, int num_entries, arm_lpae_iopte *ptep) { arm_lpae_iopte pte = prot; @@ -349,7 +393,9 @@ pte |= ARM_LPAE_PTE_TYPE_BLOCK; for (i = 0; i < num_entries; i++) - ptep[i] = pte | paddr_to_iopte(paddr + i * sz, data); + ptep[i] = pte | paddr_to_iopte(paddr + i * sz, data) | + (arm_lpae_use_contpte(data, iova, paddr, lvl, num_entries, i) ? + ARM_LPAE_PTE_CONT : 0); if (!cfg->coherent_walk) __arm_lpae_sync_pte(ptep, num_entries, cfg); @@ -383,7 +429,7 @@ } } - __arm_lpae_init_pte(data, paddr, prot, lvl, num_entries, ptep); + __arm_lpae_init_pte(data, iova, paddr, prot, lvl, num_entries, ptep); return 0; } --- linux-nvidia-7.0.0.orig/drivers/iommu/iommu.c +++ linux-nvidia-7.0.0/drivers/iommu/iommu.c @@ -1109,6 +1109,45 @@ } EXPORT_SYMBOL_GPL(iommu_group_alloc); +struct iommu_group *iommu_group_get_from_kobj(struct kobject *group_kobj) +{ + struct iommu_group *group; + + if (!iommu_group_kset || !group_kobj) + return NULL; + + group = container_of(group_kobj, struct iommu_group, kobj); + + kobject_get(group->devices_kobj); + kobject_put(&group->kobj); + + return group; +} + +struct iommu_group *iommu_group_get_by_id(int id) +{ + struct kobject *group_kobj; + const char *name; + + if (!iommu_group_kset) + return NULL; + + name = kasprintf(GFP_KERNEL, "%d", id); + if (!name) + return NULL; + + group_kobj = kset_find_obj(iommu_group_kset, name); + kfree(name); + + return iommu_group_get_from_kobj(group_kobj); +} +EXPORT_SYMBOL_GPL(iommu_group_get_by_id); + +struct kset *iommu_get_group_kset(void) +{ + return kset_get(iommu_group_kset); +} + /** * iommu_group_get_iommudata - retrieve iommu_data registered for a group * @group: the group @@ -2259,6 +2298,12 @@ } EXPORT_SYMBOL_GPL(iommu_get_domain_for_dev); +struct iommu_domain *iommu_get_domain_for_group(struct iommu_group *group) +{ + return group->domain; +} +EXPORT_SYMBOL_GPL(iommu_get_domain_for_group); + /** * iommu_driver_get_domain_for_dev() - Return the driver-level domain pointer * @dev: Device to query @@ -4097,3 +4142,79 @@ return ret; } #endif /* CONFIG_IRQ_MSI_IOMMU */ + +/* + * iommu_group_set_qos_params() - Set the QoS parameters for a group + * @group: the iommu group. + * @partition: the partition label all traffic from the group should use. + * @perf_mon_grp: the performance label all traffic from the group should use. + * + * Return: 0 on success, or an error. + */ +int iommu_group_set_qos_params(struct iommu_group *group, + u16 partition, u8 perf_mon_grp) +{ + const struct iommu_ops *ops; + struct group_device *device; + int ret; + + mutex_lock(&group->mutex); + device = list_first_entry_or_null(&group->devices, typeof(*device), + list); + if (!device) { + ret = -ENODEV; + goto out_unlock; + } + + ops = dev_iommu_ops(device->dev); + if (!ops->set_group_qos_params) { + ret = -EOPNOTSUPP; + goto out_unlock; + } + + ret = ops->set_group_qos_params(group, partition, perf_mon_grp); + +out_unlock: + mutex_unlock(&group->mutex); + + return ret; +} +EXPORT_SYMBOL_NS_GPL(iommu_group_set_qos_params, "IOMMUFD_INTERNAL"); + +/* + * iommu_group_get_qos_params() - Get the QoS parameters for a group + * @group: the iommu group. + * @partition: the partition label all traffic from the group uses. + * @perf_mon_grp: the performance label all traffic from the group uses. + * + * Return: 0 on success, or an error. + */ +int iommu_group_get_qos_params(struct iommu_group *group, + u16 *partition, u8 *perf_mon_grp) +{ + const struct iommu_ops *ops; + struct group_device *device; + int ret; + + mutex_lock(&group->mutex); + device = list_first_entry_or_null(&group->devices, typeof(*device), + list); + if (!device) { + ret = -ENODEV; + goto out_unlock; + } + + ops = dev_iommu_ops(device->dev); + if (!ops->get_group_qos_params) { + ret = -EOPNOTSUPP; + goto out_unlock; + } + + ret = ops->get_group_qos_params(group, partition, perf_mon_grp); + +out_unlock: + mutex_unlock(&group->mutex); + + return ret; +} +EXPORT_SYMBOL_NS_GPL(iommu_group_get_qos_params, "IOMMUFD_INTERNAL"); --- linux-nvidia-7.0.0.orig/drivers/iommu/iommufd/pages.c +++ linux-nvidia-7.0.0/drivers/iommu/iommufd/pages.c @@ -711,9 +711,10 @@ size_t to_unpin = min_t(size_t, npages, batch->npfns[cur] - first_page_off); - unpin_user_page_range_dirty_lock( - pfn_to_page(batch->pfns[cur] + first_page_off), - to_unpin, pages->writable); + if (pfn_valid(batch->pfns[cur] + first_page_off)) + unpin_user_page_range_dirty_lock( + pfn_to_page(batch->pfns[cur] + first_page_off), + to_unpin, pages->writable); iopt_pages_sub_npinned(pages, to_unpin); cur++; first_page_off = 0; @@ -873,6 +874,41 @@ return npages_out; } +static int follow_fault_pfn(struct vm_area_struct *vma, struct mm_struct *mm, + unsigned long vaddr, unsigned long *pfn, + bool write_fault) +{ + struct follow_pfnmap_args args = { .vma = vma, .address = vaddr }; + int ret; + + ret = follow_pfnmap_start(&args); + if (ret) { + bool unlocked = false; + + ret = fixup_user_fault(mm, vaddr, + FAULT_FLAG_REMOTE | + (write_fault ? FAULT_FLAG_WRITE : 0), + &unlocked); + if (unlocked) + return -EAGAIN; + + if (ret) + return ret; + + ret = follow_pfnmap_start(&args); + if (ret) + return ret; + } + + if (write_fault && !args.writable) + ret = -EFAULT; + else + *pfn = args.pfn; + + follow_pfnmap_end(&args); + return ret; +} + static int pfn_reader_user_pin(struct pfn_reader_user *user, struct iopt_pages *pages, unsigned long start_index, @@ -941,6 +977,42 @@ user->gup_flags, user->upages, &user->locked); } + + if (rc < 0) { + struct vm_area_struct *vma; + unsigned long vaddr; + unsigned long pfn; + int pinned = 0; + + /* fast path above doesn't hold the lock */ + if (!user->locked) + mmap_read_lock(pages->source_mm); + vaddr = untagged_addr_remote(pages->source_mm, uptr); +retry: + vma = vma_lookup(pages->source_mm, vaddr); + if (vma && vma->vm_flags & VM_PFNMAP) { + do { + rc = follow_fault_pfn(vma, pages->source_mm, vaddr, + &pfn, pages->writable); + if (rc == -EAGAIN) + goto retry; + if (!rc) { + if (!pfn_valid(pfn)) { + user->upages[pinned] = pfn_to_page(pfn); + pinned += 1; + vaddr += PAGE_SIZE; + } else { + rc = -EFAULT; + } + } + } while (pinned < npages && vaddr < vma->vm_end && !rc); + } + if (pinned) + rc = pinned; + if (!user->locked) + mmap_read_unlock(pages->source_mm); + } + if (rc <= 0) { if (WARN_ON(!rc)) return -EFAULT; @@ -1313,7 +1385,8 @@ user->upages_start; if (!user->file) { - unpin_user_pages(user->upages + start_index, npages); + if (pfn_valid(page_to_pfn(user->upages[0]))) + unpin_user_pages(user->upages + start_index, npages); } else { long n = user->ufolios_len / sizeof(*user->ufolios); --- linux-nvidia-7.0.0.orig/drivers/irqchip/irq-gic-v3.c +++ linux-nvidia-7.0.0/drivers/irqchip/irq-gic-v3.c @@ -1634,7 +1634,13 @@ if(fwspec->param_count != 2) return -EINVAL; - if (fwspec->param[0] < 16) { + /* + * Below check was added on assumption that MAX_IPI + * value will not be greater than 8. + */ + BUILD_BUG_ON(MAX_IPI > 8); + + if (fwspec->param[0] < MAX_IPI) { pr_err(FW_BUG "Illegal GSI%d translation request\n", fwspec->param[0]); return -EINVAL; --- linux-nvidia-7.0.0.orig/drivers/leds/Kconfig +++ linux-nvidia-7.0.0/drivers/leds/Kconfig @@ -72,6 +72,18 @@ This option enables support for on-chip LED drivers found on Marvell Semiconductor 88PM8606 PMIC. +config LEDS_AAEON + tristate "AAEON LED driver" + depends on X86 + depends on UBUNTU_ODM_DRIVERS + select MFD_AAEON + help + This led driver adds support for LED brightness control on Single + Board Computers produced by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + config LEDS_AN30259A tristate "LED support for Panasonic AN30259A" depends on LEDS_CLASS && I2C && OF --- linux-nvidia-7.0.0.orig/drivers/leds/Makefile +++ linux-nvidia-7.0.0/drivers/leds/Makefile @@ -10,6 +10,7 @@ # LED Platform Drivers (keep this sorted, M-| sort) obj-$(CONFIG_LEDS_88PM860X) += leds-88pm860x.o +obj-$(CONFIG_LEDS_AAEON) += leds-aaeon.o obj-$(CONFIG_LEDS_ACER_A500) += leds-acer-a500.o obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o obj-$(CONFIG_LEDS_AN30259A) += leds-an30259a.o --- linux-nvidia-7.0.0.orig/drivers/leds/leds-aaeon.c +++ linux-nvidia-7.0.0/drivers/leds/leds-aaeon.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AAEON LED driver + * + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Kunyang Fan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include + +#define DRVNAME "led_aaeon" +#define ASUS_NB_WMI_EVENT_GUID "0B3CBB35-E3C2-45ED-91C2-4C5A6D195D1C" +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define GET_LED_NUMBER_ID 0x00060000 +#define GET_LED_METHOD_ID 0x00060001 +#define SET_LED_METHOD_ID 0x00060002 +#define GET_LED_NUMBER_METHOD_ID 0x10 + + +struct aaeon_led_data { + int id; + struct led_classdev cdev; +}; + +static int aaeon_led_get_number(void) +{ + int err, retval; + + err = asus_wmi_evaluate_method(GET_LED_NUMBER_ID, + GET_LED_NUMBER_METHOD_ID, + 0, &retval); + if (err) + return err; + + return retval; +} + +static enum led_brightness aaeon_led_brightness_get(struct led_classdev + *cdev) +{ + int err, brightness; + struct aaeon_led_data *led = + container_of(cdev, struct aaeon_led_data, cdev); + u32 arg0; + + arg0 = (u32)(led->id & 0xF); + err = asus_wmi_evaluate_method(GET_LED_METHOD_ID, arg0, 0, &brightness); + if (err) + return err; + + return brightness; +}; + +static void aaeon_led_brightness_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + int err, retval; + struct aaeon_led_data *led = + container_of(cdev, struct aaeon_led_data, cdev); + u32 arg0; + + arg0 = (u32)(led->id & 0xF); + if (brightness != LED_OFF) + arg0 |= BIT(16); + + err = asus_wmi_evaluate_method(SET_LED_METHOD_ID, arg0, 0, &retval); +}; + +static int __init aaeon_add_led_device(struct platform_device *pdev, + int id) +{ + struct aaeon_led_data *led; + + led = devm_kzalloc(&pdev->dev, sizeof(struct aaeon_led_data), GFP_KERNEL); + if (!led) + return -ENOMEM; + + led->id = id; + led->cdev.brightness_get = aaeon_led_brightness_get; + led->cdev.brightness_set = aaeon_led_brightness_set; + led->cdev.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "led:%d:", id); + + if (!led->cdev.name) + return -ENOMEM; + + return devm_led_classdev_register(&pdev->dev, &led->cdev); +} + +static int aaeon_led_probe(struct platform_device *pdev) +{ + int err = -ENODEV, i; + int led_number = 0; + + pr_debug("aaeon led device probe!\n"); + /* Prevent other drivers adding this platfom device */ + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + pr_debug("AAEON Management GUID not found\n"); + return -ENODEV; + } + + /* Query the number of led devices board support */ + led_number = aaeon_led_get_number(); + + /* + * If the number is 0 or can't get the number of leds, + * no need to register any led device node. + */ + if (led_number <= 0) + return -ENODEV; + + for (i = 0; i < led_number; i++) { + err = aaeon_add_led_device(pdev, i); + if (err) + break; + } + + return err; +} + +static struct platform_driver aaeon_led_driver = { + .driver = { + .name = "leds-aaeon", + }, +}; + +module_platform_driver_probe(aaeon_led_driver, aaeon_led_probe); + +MODULE_ALIAS("platform:leds-aaeon"); +MODULE_DESCRIPTION("AAEON LED Driver"); +MODULE_AUTHOR("Kunyang Fan "); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); --- linux-nvidia-7.0.0.orig/drivers/md/raid0.c +++ linux-nvidia-7.0.0/drivers/md/raid0.c @@ -267,11 +267,12 @@ default_layout == RAID0_ALT_MULTIZONE_LAYOUT) { conf->layout = default_layout; } else { - pr_err("md/raid0:%s: cannot assemble multi-zone RAID0 with default_layout setting\n", - mdname(mddev)); - pr_err("md/raid0: please set raid0.default_layout to 1 or 2\n"); - err = -EOPNOTSUPP; - goto abort; + conf->layout = RAID0_ALT_MULTIZONE_LAYOUT; + pr_warn("md/raid0:%s: !!! DEFAULTING TO ALTERNATE LAYOUT !!!\n", + mdname(mddev)); + pr_warn("md/raid0: Please set raid0.default_layout to 1 or 2\n"); + pr_warn("md/raid0: Read the following page for more information:\n"); + pr_warn("md/raid0: https://wiki.ubuntu.com/Kernel/Raid0LayoutMigration\n"); } if (conf->layout == RAID0_ORIG_LAYOUT) { --- linux-nvidia-7.0.0.orig/drivers/media/pci/intel/ipu-bridge.c +++ linux-nvidia-7.0.0/drivers/media/pci/intel/ipu-bridge.c @@ -97,6 +97,9 @@ IPU_SENSOR_CONFIG("SONY471A", 1, 200000000), /* Toshiba T4KA3 */ IPU_SENSOR_CONFIG("XMCC0003", 1, 321468000), + /* Sony IMX471 */ + IPU_SENSOR_CONFIG("SONY471A", 1, 200000000), + IPU_SENSOR_CONFIG("TBE20A0" , 1, 200000000), }; /* --- linux-nvidia-7.0.0.orig/drivers/media/platform/Kconfig +++ linux-nvidia-7.0.0/drivers/media/platform/Kconfig @@ -63,6 +63,7 @@ # Platform drivers - Please keep it alphabetically sorted source "drivers/media/platform/allegro-dvt/Kconfig" +source "drivers/media/platform/amd/Kconfig" source "drivers/media/platform/amlogic/Kconfig" source "drivers/media/platform/amphion/Kconfig" source "drivers/media/platform/arm/Kconfig" --- linux-nvidia-7.0.0.orig/drivers/media/platform/Makefile +++ linux-nvidia-7.0.0/drivers/media/platform/Makefile @@ -6,6 +6,7 @@ # Place here, alphabetically sorted by directory # (e. g. LC_ALL=C sort Makefile) obj-y += allegro-dvt/ +obj-y += amd/ obj-y += amlogic/ obj-y += amphion/ obj-y += arm/ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/Kconfig +++ linux-nvidia-7.0.0/drivers/media/platform/amd/Kconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +source "drivers/media/platform/amd/isp4/Kconfig" --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/Makefile +++ linux-nvidia-7.0.0/drivers/media/platform/amd/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += isp4/ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/Kconfig +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ + +config VIDEO_AMD_ISP4_CAPTURE + tristate "AMD ISP4 and camera driver" + depends on DRM_AMD_ISP && VIDEO_DEV && HAS_DMA + select VIDEOBUF2_CORE + select VIDEOBUF2_MEMOPS + select VIDEOBUF2_V4L2 + select VIDEOBUF2_VMALLOC + select VIDEO_V4L2_SUBDEV_API + help + This is support for AMD ISP4 and camera subsystem driver. + Say Y here to enable the ISP4 and camera device for video capture. + To compile this driver as a module, choose M here. The module will + be called amd_isp4_capture. --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/Makefile +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. + +obj-$(CONFIG_VIDEO_AMD_ISP4_CAPTURE) += amd_isp4_capture.o +amd_isp4_capture-objs := isp4.o \ + isp4_debug.o \ + isp4_interface.o \ + isp4_subdev.o \ + isp4_video.o --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4.c +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include + +#include "isp4.h" +#include "isp4_debug.h" +#include "isp4_hw_reg.h" + +#define ISP4_DRV_NAME "amd_isp_capture" +#define ISP4_FW_RESP_RB_IRQ_STATUS_MASK \ + (ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT9_INT_MASK | \ + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT12_INT_MASK) + +static const struct { + const char *name; + u32 status_mask; + u32 en_mask; + u32 ack_mask; + u32 rb_int_num; +} isp4_irq[ISP4SD_MAX_FW_RESP_STREAM_NUM] = { + /* The IRQ order is aligned with the isp4_subdev.fw_resp_thread order */ + { + .name = "isp_irq_global", + .status_mask = + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT12_INT_MASK, + .en_mask = ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT12_EN_MASK, + .ack_mask = ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT12_ACK_MASK, + .rb_int_num = 4, /* ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12 */ + }, + { + .name = "isp_irq_stream1", + .status_mask = + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT9_INT_MASK, + .en_mask = ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT9_EN_MASK, + .ack_mask = ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT9_ACK_MASK, + .rb_int_num = 0, /* ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9 */ + }, +}; + +void isp4_intr_enable(struct isp4_subdev *isp_subdev, u32 index, bool enable) +{ + u32 intr_en; + + /* Synchronize ISP_SYS_INT0_EN writes with the IRQ handler's writes */ + spin_lock_irq(&isp_subdev->irq_lock); + intr_en = isp4hw_rreg(isp_subdev->mmio, ISP_SYS_INT0_EN); + if (enable) + intr_en |= isp4_irq[index].en_mask; + else + intr_en &= ~isp4_irq[index].en_mask; + + isp4hw_wreg(isp_subdev->mmio, ISP_SYS_INT0_EN, intr_en); + spin_unlock_irq(&isp_subdev->irq_lock); +} + +static void isp4_wake_up_resp_thread(struct isp4_subdev *isp_subdev, u32 index) +{ + struct isp4sd_thread_handler *thread_ctx = + &isp_subdev->fw_resp_thread[index]; + + thread_ctx->resp_ready = true; + wake_up_interruptible(&thread_ctx->waitq); +} + +static irqreturn_t isp4_irq_handler(int irq, void *arg) +{ + struct isp4_subdev *isp_subdev = arg; + u32 intr_ack = 0, intr_en = 0, intr_status; + int seen = 0; + + /* Get the ISP_SYS interrupt status */ + intr_status = isp4hw_rreg(isp_subdev->mmio, ISP_SYS_INT0_STATUS); + intr_status &= ISP4_FW_RESP_RB_IRQ_STATUS_MASK; + + /* Find which ISP_SYS interrupts fired */ + for (size_t i = 0; i < ARRAY_SIZE(isp4_irq); i++) { + if (intr_status & isp4_irq[i].status_mask) { + intr_ack |= isp4_irq[i].ack_mask; + intr_en |= isp4_irq[i].en_mask; + seen |= BIT(i); + } + } + + /* + * Disable the ISP_SYS interrupts that fired. Must be done before waking + * the response threads, since they re-enable interrupts when finished. + * The lock synchronizes RMW of INT0_EN with isp4_enable_interrupt(). + */ + spin_lock(&isp_subdev->irq_lock); + intr_en = isp4hw_rreg(isp_subdev->mmio, ISP_SYS_INT0_EN) & ~intr_en; + isp4hw_wreg(isp_subdev->mmio, ISP_SYS_INT0_EN, intr_en); + spin_unlock(&isp_subdev->irq_lock); + + /* + * Clear the ISP_SYS interrupts. This must be done after the interrupts + * are disabled, so that ISP FW won't flag any new interrupts on these + * streams, and thus we don't need to clear interrupts again before + * re-enabling them in the response thread. + */ + isp4hw_wreg(isp_subdev->mmio, ISP_SYS_INT0_ACK, intr_ack); + + /* + * The operation `(seen >> i) << i` is logically equivalent to + * `seen &= ~BIT(i)`, with fewer instructions after compilation. + */ + for (int i; (i = ffs(seen)); seen = (seen >> i) << i) + isp4_wake_up_resp_thread(isp_subdev, i - 1); + + return IRQ_HANDLED; +} + +static int isp4_capture_probe(struct platform_device *pdev) +{ + int irq[ISP4SD_MAX_FW_RESP_STREAM_NUM]; + struct device *dev = &pdev->dev; + struct isp4_subdev *isp_subdev; + struct isp4_device *isp_dev; + int ret; + + isp_dev = devm_kzalloc(dev, sizeof(*isp_dev), GFP_KERNEL); + if (!isp_dev) + return -ENOMEM; + + dev->init_name = ISP4_DRV_NAME; + + isp_subdev = &isp_dev->isp_subdev; + isp_subdev->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(isp_subdev->mmio)) + return dev_err_probe(dev, PTR_ERR(isp_subdev->mmio), + "isp ioremap fail\n"); + + for (size_t i = 0; i < ARRAY_SIZE(isp4_irq); i++) { + irq[i] = platform_get_irq(pdev, isp4_irq[i].rb_int_num); + if (irq[i] < 0) + return dev_err_probe(dev, irq[i], + "fail to get irq %d\n", + isp4_irq[i].rb_int_num); + + ret = devm_request_irq(dev, irq[i], isp4_irq_handler, + IRQF_NO_AUTOEN, isp4_irq[i].name, + isp_subdev); + if (ret) + return dev_err_probe(dev, ret, "fail to req irq %d\n", + irq[i]); + } + + isp_dev->v4l2_dev.mdev = &isp_dev->mdev; + + strscpy(isp_dev->mdev.model, "amd_isp41_mdev", + sizeof(isp_dev->mdev.model)); + isp_dev->mdev.dev = dev; + media_device_init(&isp_dev->mdev); + + snprintf(isp_dev->v4l2_dev.name, sizeof(isp_dev->v4l2_dev.name), + "AMD-V4L2-ROOT"); + ret = v4l2_device_register(dev, &isp_dev->v4l2_dev); + if (ret) { + dev_err_probe(dev, ret, "fail register v4l2 device\n"); + goto err_clean_media; + } + + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + spin_lock_init(&isp_subdev->irq_lock); + ret = isp4sd_init(&isp_dev->isp_subdev, &isp_dev->v4l2_dev, irq); + if (ret) { + dev_err_probe(dev, ret, "fail init isp4 sub dev\n"); + goto err_pm_disable; + } + + ret = media_create_pad_link(&isp_dev->isp_subdev.sdev.entity, + 0, + &isp_dev->isp_subdev.isp_vdev.vdev.entity, + 0, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + if (ret) { + dev_err_probe(dev, ret, "fail to create pad link\n"); + goto err_isp4_deinit; + } + + ret = media_device_register(&isp_dev->mdev); + if (ret) { + dev_err_probe(dev, ret, "fail to register media device\n"); + goto err_isp4_deinit; + } + + platform_set_drvdata(pdev, isp_dev); + isp_debugfs_create(isp_dev); + + return 0; + +err_isp4_deinit: + isp4sd_deinit(&isp_dev->isp_subdev); +err_pm_disable: + pm_runtime_disable(dev); + v4l2_device_unregister(&isp_dev->v4l2_dev); +err_clean_media: + media_device_cleanup(&isp_dev->mdev); + + return ret; +} + +static void isp4_capture_remove(struct platform_device *pdev) +{ + struct isp4_device *isp_dev = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + isp_debugfs_remove(isp_dev); + + media_device_unregister(&isp_dev->mdev); + isp4sd_deinit(&isp_dev->isp_subdev); + pm_runtime_disable(dev); + v4l2_device_unregister(&isp_dev->v4l2_dev); + media_device_cleanup(&isp_dev->mdev); +} + +static struct platform_driver isp4_capture_drv = { + .probe = isp4_capture_probe, + .remove = isp4_capture_remove, + .driver = { + .name = ISP4_DRV_NAME, + } +}; + +module_platform_driver(isp4_capture_drv); + +MODULE_ALIAS("platform:" ISP4_DRV_NAME); +MODULE_IMPORT_NS("DMA_BUF"); + +MODULE_DESCRIPTION("AMD ISP4 Driver"); +MODULE_AUTHOR("Bin Du "); +MODULE_AUTHOR("Pratap Nirujogi "); +MODULE_LICENSE("GPL"); --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4.h +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_H_ +#define _ISP4_H_ + +#include +#include "isp4_subdev.h" + +struct isp4_device { + struct v4l2_device v4l2_dev; + struct isp4_subdev isp_subdev; + struct media_device mdev; +}; + +void isp4_intr_enable(struct isp4_subdev *isp_subdev, u32 index, bool enable); + +#endif /* _ISP4_H_ */ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_debug.c +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_debug.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include "isp4.h" +#include "isp4_debug.h" +#include "isp4_hw_reg.h" +#include "isp4_interface.h" + +#define ISP4DBG_FW_LOG_RINGBUF_SIZE (2 * 1024 * 1024) +#define ISP4DBG_MACRO_2_STR(X) #X +#define ISP4DBG_ONE_TIME_LOG_LEN 510 + +#ifdef CONFIG_DEBUG_FS + +void isp_debugfs_create(struct isp4_device *isp_dev) +{ + isp_dev->isp_subdev.debugfs_dir = debugfs_create_dir("amd_isp4", NULL); + debugfs_create_bool("fw_log_enable", 0644, + isp_dev->isp_subdev.debugfs_dir, + &isp_dev->isp_subdev.enable_fw_log); + isp_dev->isp_subdev.fw_log_output = + devm_kzalloc(isp_dev->isp_subdev.dev, + ISP4DBG_FW_LOG_RINGBUF_SIZE + 32, + GFP_KERNEL); +} + +void isp_debugfs_remove(struct isp4_device *isp_dev) +{ + debugfs_remove_recursive(isp_dev->isp_subdev.debugfs_dir); + isp_dev->isp_subdev.debugfs_dir = NULL; +} + +static u32 isp_fw_fill_rb_log(struct isp4_subdev *isp, void *sys, u32 rb_size) +{ + struct isp4_interface *ispif = &isp->ispif; + char *buf = isp->fw_log_output; + struct device *dev = isp->dev; + u32 rd_ptr, wr_ptr; + u32 total_cnt = 0; + u32 offset = 0; + u32 cnt; + + if (!sys || !rb_size) + return 0; + + guard(mutex)(&ispif->isp4if_mutex); + + rd_ptr = isp4hw_rreg(isp->mmio, ISP_LOG_RB_RPTR0); + wr_ptr = isp4hw_rreg(isp->mmio, ISP_LOG_RB_WPTR0); + + do { + if (wr_ptr > rd_ptr) + cnt = wr_ptr - rd_ptr; + else if (wr_ptr < rd_ptr) + cnt = rb_size - rd_ptr; + else + goto quit; + + if (cnt > rb_size) { + dev_err(dev, "fail bad fw log size %u\n", cnt); + goto quit; + } + + memcpy(buf + offset, sys + rd_ptr, cnt); + + offset += cnt; + total_cnt += cnt; + rd_ptr = (rd_ptr + cnt) % rb_size; + } while (rd_ptr < wr_ptr); + + isp4hw_wreg(isp->mmio, ISP_LOG_RB_RPTR0, rd_ptr); + +quit: + return total_cnt; +} + +void isp_fw_log_print(struct isp4_subdev *isp) +{ + struct isp4_interface *ispif = &isp->ispif; + char *fw_log_buf = isp->fw_log_output; + u32 cnt; + + if (!isp->enable_fw_log || !fw_log_buf) + return; + + cnt = isp_fw_fill_rb_log(isp, ispif->fw_log_buf->sys_addr, + ispif->fw_log_buf->mem_size); + + if (cnt) { + char temp_ch; + char *str; + char *end; + /* line end */ + char *le; + + str = (char *)fw_log_buf; + end = ((char *)fw_log_buf + cnt); + fw_log_buf[cnt] = 0; + + while (str < end) { + le = strchr(str, 0x0A); + if ((le && str + ISP4DBG_ONE_TIME_LOG_LEN >= le) || + (!le && str + ISP4DBG_ONE_TIME_LOG_LEN >= end)) { + if (le) + *le = 0; + + if (*str != '\0') + dev_dbg(isp->dev, "%s", str); + + if (le) { + *le = 0x0A; + str = le + 1; + } else { + break; + } + } else { + u32 tmp_len = ISP4DBG_ONE_TIME_LOG_LEN; + + temp_ch = str[tmp_len]; + str[tmp_len] = 0; + dev_dbg(isp->dev, "%s", str); + str[tmp_len] = temp_ch; + str = &str[tmp_len]; + } + } + } +} +#endif + +char *isp4dbg_get_buf_src_str(u32 src) +{ + switch (src) { + case ISP4FW_BUFFER_SOURCE_STREAM: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_SOURCE_STREAM); + default: + return "Unknown buf source"; + } +} + +char *isp4dbg_get_buf_done_str(u32 status) +{ + switch (status) { + case ISP4FW_BUFFER_STATUS_INVALID: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_STATUS_INVALID); + case ISP4FW_BUFFER_STATUS_SKIPPED: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_STATUS_SKIPPED); + case ISP4FW_BUFFER_STATUS_EXIST: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_STATUS_EXIST); + case ISP4FW_BUFFER_STATUS_DONE: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_STATUS_DONE); + case ISP4FW_BUFFER_STATUS_LACK: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_STATUS_LACK); + case ISP4FW_BUFFER_STATUS_DIRTY: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_STATUS_DIRTY); + case ISP4FW_BUFFER_STATUS_MAX: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_STATUS_MAX); + default: + return "Unknown Buf Done Status"; + } +} + +char *isp4dbg_get_img_fmt_str(int fmt /* enum isp4fw_image_format * */) +{ + switch (fmt) { + case ISP4FW_IMAGE_FORMAT_NV12: + return "NV12"; + case ISP4FW_IMAGE_FORMAT_YUV422INTERLEAVED: + return "YUV422INTERLEAVED"; + default: + return "unknown fmt"; + } +} + +void isp4dbg_show_bufmeta_info(struct device *dev, char *pre, + void *in, void *orig_buf) +{ + struct isp4fw_buffer_meta_info *p; + struct isp4if_img_buf_info *orig; + + if (!in) + return; + + if (!pre) + pre = ""; + + p = in; + orig = orig_buf; + + dev_dbg(dev, "%s(%s) en:%d,stat:%s(%u),src:%s\n", pre, + isp4dbg_get_img_fmt_str(p->image_prop.image_format), + p->enabled, isp4dbg_get_buf_done_str(p->status), p->status, + isp4dbg_get_buf_src_str(p->source)); + + dev_dbg(dev, "%p,0x%llx(%u) %p,0x%llx(%u) %p,0x%llx(%u)\n", + orig->planes[0].sys_addr, orig->planes[0].mc_addr, + orig->planes[0].len, orig->planes[1].sys_addr, + orig->planes[1].mc_addr, orig->planes[1].len, + orig->planes[2].sys_addr, orig->planes[2].mc_addr, + orig->planes[2].len); +} + +char *isp4dbg_get_buf_type(u32 type) +{ + /* enum isp4fw_buffer_type */ + switch (type) { + case ISP4FW_BUFFER_TYPE_PREVIEW: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_TYPE_PREVIEW); + case ISP4FW_BUFFER_TYPE_META_INFO: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_TYPE_META_INFO); + case ISP4FW_BUFFER_TYPE_MEM_POOL: + return ISP4DBG_MACRO_2_STR(ISP4FW_BUFFER_TYPE_MEM_POOL); + default: + return "unknown type"; + } +} + +char *isp4dbg_get_cmd_str(u32 cmd) +{ + switch (cmd) { + case ISP4FW_CMD_ID_START_STREAM: + return ISP4DBG_MACRO_2_STR(ISP4FW_CMD_ID_START_STREAM); + case ISP4FW_CMD_ID_STOP_STREAM: + return ISP4DBG_MACRO_2_STR(ISP4FW_CMD_ID_STOP_STREAM); + case ISP4FW_CMD_ID_SEND_BUFFER: + return ISP4DBG_MACRO_2_STR(ISP4FW_CMD_ID_SEND_BUFFER); + case ISP4FW_CMD_ID_SET_STREAM_CONFIG: + return ISP4DBG_MACRO_2_STR(ISP4FW_CMD_ID_SET_STREAM_CONFIG); + case ISP4FW_CMD_ID_SET_OUT_CHAN_PROP: + return ISP4DBG_MACRO_2_STR(ISP4FW_CMD_ID_SET_OUT_CHAN_PROP); + case ISP4FW_CMD_ID_ENABLE_OUT_CHAN: + return ISP4DBG_MACRO_2_STR(ISP4FW_CMD_ID_ENABLE_OUT_CHAN); + default: + return "unknown cmd"; + } +} + +char *isp4dbg_get_resp_str(u32 cmd) +{ + switch (cmd) { + case ISP4FW_RESP_ID_CMD_DONE: + return ISP4DBG_MACRO_2_STR(ISP4FW_RESP_ID_CMD_DONE); + case ISP4FW_RESP_ID_NOTI_FRAME_DONE: + return ISP4DBG_MACRO_2_STR(ISP4FW_RESP_ID_NOTI_FRAME_DONE); + default: + return "unknown respid"; + } +} + +char *isp4dbg_get_if_stream_str(u32 stream /* enum fw_cmd_resp_stream_id */) +{ + switch (stream) { + case ISP4IF_STREAM_ID_GLOBAL: + return "STREAM_GLOBAL"; + case ISP4IF_STREAM_ID_1: + return "STREAM1"; + default: + return "unknown streamID"; + } +} + +char *isp4dbg_get_out_ch_str(int ch /* enum isp4fw_pipe_out_ch */) +{ + switch ((enum isp4fw_pipe_out_ch)ch) { + case ISP4FW_ISP_PIPE_OUT_CH_PREVIEW: + return "prev"; + default: + return "unknown channel"; + } +} --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_debug.h +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_debug.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_DEBUG_H_ +#define _ISP4_DEBUG_H_ + +#include +#include + +#include "isp4_subdev.h" + +#ifdef CONFIG_DEBUG_FS +struct isp4_device; + +void isp_debugfs_create(struct isp4_device *isp_dev); +void isp_debugfs_remove(struct isp4_device *isp_dev); +void isp_fw_log_print(struct isp4_subdev *isp); + +#else + +/* to avoid checkpatch warning */ +#define isp_debugfs_create(cam) ((void)(cam)) +#define isp_debugfs_remove(cam) ((void)(cam)) +#define isp_fw_log_print(isp) ((void)(isp)) + +#endif /* CONFIG_DEBUG_FS */ + +void isp4dbg_show_bufmeta_info(struct device *dev, char *pre, void *p, + void *orig_buf /* struct sys_img_buf_handle */); +char *isp4dbg_get_img_fmt_str(int fmt /* enum _image_format_t */); +char *isp4dbg_get_out_ch_str(int ch /* enum _isp_pipe_out_ch_t */); +char *isp4dbg_get_cmd_str(u32 cmd); +char *isp4dbg_get_buf_type(u32 type);/* enum _buffer_type_t */ +char *isp4dbg_get_resp_str(u32 resp); +char *isp4dbg_get_buf_src_str(u32 src); +char *isp4dbg_get_buf_done_str(u32 status); +char *isp4dbg_get_if_stream_str(u32 stream); + +#endif /* _ISP4_DEBUG_H_ */ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_fw_cmd_resp.h +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_fw_cmd_resp.h @@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_FW_CMD_RESP_H_ +#define _ISP4_FW_CMD_RESP_H_ + +/* + * Two types of command/response channel. + * Type Global Command has one command/response channel. + * Type Stream Command has one command/response channel. + *----------- ------------ + *| | --------------------------- | | + *| | ---->| Global Command |----> | | + *| | --------------------------- | | + *| | | | + *| | | | + *| | --------------------------- | | + *| | ---->| Stream Command |----> | | + *| | --------------------------- | | + *| | | | + *| | | | + *| | | | + *| HOST | | Firmware | + *| | | | + *| | | | + *| | -------------------------- | | + *| | <----| Global Response |<---- | | + *| | -------------------------- | | + *| | | | + *| | | | + *| | -------------------------- | | + *| | <----| Stream Response |<---- | | + *| | -------------------------- | | + *| | | | + *| | | | + *----------- ------------ + */ + +/* + * cmd_id is in the format of following type: + * type: indicate command type, global/stream commands. + * group: indicate the command group. + * id: A unique command identification in one type and group. + * |<-Bit31 ~ Bit24->|<-Bit23 ~ Bit16->|<-Bit15 ~ Bit0->| + * | type | group | id | + */ + +#define ISP4FW_CMD_TYPE_SHIFT 24 +#define ISP4FW_CMD_GROUP_SHIFT 16 +#define ISP4FW_CMD_TYPE_STREAM_CTRL (0x2U << ISP4FW_CMD_TYPE_SHIFT) + +#define ISP4FW_CMD_GROUP_STREAM_CTRL (0x1U << ISP4FW_CMD_GROUP_SHIFT) +#define ISP4FW_CMD_GROUP_STREAM_BUFFER (0x4U << ISP4FW_CMD_GROUP_SHIFT) + +/* Stream Command */ +#define ISP4FW_CMD_ID_SET_STREAM_CONFIG (ISP4FW_CMD_TYPE_STREAM_CTRL\ + | ISP4FW_CMD_GROUP_STREAM_CTRL | 0x1) +#define ISP4FW_CMD_ID_SET_OUT_CHAN_PROP (ISP4FW_CMD_TYPE_STREAM_CTRL\ + | ISP4FW_CMD_GROUP_STREAM_CTRL | 0x3) +#define ISP4FW_CMD_ID_ENABLE_OUT_CHAN (ISP4FW_CMD_TYPE_STREAM_CTRL\ + | ISP4FW_CMD_GROUP_STREAM_CTRL | 0x5) +#define ISP4FW_CMD_ID_START_STREAM (ISP4FW_CMD_TYPE_STREAM_CTRL\ + | ISP4FW_CMD_GROUP_STREAM_CTRL | 0x7) +#define ISP4FW_CMD_ID_STOP_STREAM (ISP4FW_CMD_TYPE_STREAM_CTRL\ + | ISP4FW_CMD_GROUP_STREAM_CTRL | 0x8) + +/* Stream Buffer Command */ +#define ISP4FW_CMD_ID_SEND_BUFFER (ISP4FW_CMD_TYPE_STREAM_CTRL\ + | ISP4FW_CMD_GROUP_STREAM_BUFFER | 0x1) + +/* + * resp_id is in the format of following type: + * type: indicate command type, global/stream commands. + * group: indicate the command group. + * id: A unique command identification in one type and group. + * |<-Bit31 ~ Bit24->|<-Bit23 ~ Bit16->|<-Bit15 ~ Bit0->| + * | type | group | id | + */ + +#define ISP4FW_RESP_GROUP_SHIFT 16 + +#define ISP4FW_RESP_GROUP_GENERAL (0x1 << ISP4FW_RESP_GROUP_SHIFT) +#define ISP4FW_RESP_GROUP_NOTIFICATION (0x3 << ISP4FW_RESP_GROUP_SHIFT) + +/* General Response */ +#define ISP4FW_RESP_ID_CMD_DONE (ISP4FW_RESP_GROUP_GENERAL | 0x1) + +/* Notification */ +#define ISP4FW_RESP_ID_NOTI_FRAME_DONE (ISP4FW_RESP_GROUP_NOTIFICATION | 0x1) + +#define ISP4FW_CMD_STATUS_SUCCESS 0 +#define ISP4FW_CMD_STATUS_FAIL 1 +#define ISP4FW_CMD_STATUS_SKIPPED 2 + +#define ISP4FW_ADDR_SPACE_TYPE_GPU_VA 4 + +#define ISP4FW_MEMORY_POOL_SIZE (100 * 1024 * 1024) + +/* + * standard ISP pipeline: mipicsi=>isp + */ +#define ISP4FW_MIPI0_ISP_PIPELINE_ID 0x5f91 + +enum isp4fw_sensor_id { + /* Sensor id for ISP input from MIPI port 0 */ + ISP4FW_SENSOR_ID_ON_MIPI0 = 0, +}; + +enum isp4fw_stream_id { + ISP4FW_STREAM_ID_INVALID = -1, + ISP4FW_STREAM_ID_1 = 0, + ISP4FW_STREAM_ID_2 = 1, + ISP4FW_STREAM_ID_3 = 2, + ISP4FW_STREAM_ID_MAXIMUM +}; + +enum isp4fw_image_format { + /* 4:2:0,semi-planar, 8-bit */ + ISP4FW_IMAGE_FORMAT_NV12 = 1, + /* interleave, 4:2:2, 8-bit */ + ISP4FW_IMAGE_FORMAT_YUV422INTERLEAVED = 7, +}; + +enum isp4fw_pipe_out_ch { + ISP4FW_ISP_PIPE_OUT_CH_PREVIEW = 0, +}; + +enum isp4fw_yuv_range { + ISP4FW_ISP_YUV_RANGE_FULL = 0, /* YUV value range in 0~255 */ + ISP4FW_ISP_YUV_RANGE_NARROW = 1, /* YUV value range in 16~235 */ + ISP4FW_ISP_YUV_RANGE_MAX +}; + +enum isp4fw_buffer_type { + ISP4FW_BUFFER_TYPE_PREVIEW = 8, + ISP4FW_BUFFER_TYPE_META_INFO = 10, + ISP4FW_BUFFER_TYPE_MEM_POOL = 15, +}; + +enum isp4fw_buffer_status { + /* The buffer is INVALID */ + ISP4FW_BUFFER_STATUS_INVALID, + /* The buffer is not filled with image data */ + ISP4FW_BUFFER_STATUS_SKIPPED, + /* The buffer is available and awaiting to be filled */ + ISP4FW_BUFFER_STATUS_EXIST, + /* The buffer is filled with image data */ + ISP4FW_BUFFER_STATUS_DONE, + /* The buffer is unavailable */ + ISP4FW_BUFFER_STATUS_LACK, + /* The buffer is dirty, probably caused by LMI leakage */ + ISP4FW_BUFFER_STATUS_DIRTY, + ISP4FW_BUFFER_STATUS_MAX +}; + +enum isp4fw_buffer_source { + /* The buffer is from the stream buffer queue */ + ISP4FW_BUFFER_SOURCE_STREAM, +}; + +struct isp4fw_error_code { + u32 code1; + u32 code2; + u32 code3; + u32 code4; + u32 code5; +}; + +/* Command Structure for FW */ + +struct isp4fw_cmd { + u32 cmd_seq_num; + u32 cmd_id; + u32 cmd_param[12]; + u16 cmd_stream_id; + u8 cmd_silent_resp; + u8 reserved; + u32 cmd_check_sum; +}; + +struct isp4fw_resp_cmd_done { + /* + * The host2fw command seqNum. + * To indicate which command this response refers to. + */ + u32 cmd_seq_num; + /* The host2fw command id for host double check. */ + u32 cmd_id; + /* + * Indicate the command process status. + * 0 means success. 1 means fail. 2 means skipped + */ + u16 cmd_status; + /* + * If cmd_status is 1, the command failed. The host can check + * isp4fw_error_code for details. + */ + u16 isp4fw_error_code; + /* The response payload type varies by cmd. */ + u8 payload[36]; +}; + +struct isp4fw_resp_param_package { + u32 package_addr_lo; /* The low 32 bit of the pkg address. */ + u32 package_addr_hi; /* The high 32 bit of the pkg address. */ + u32 package_size; /* The total pkg size in bytes. */ + u32 package_check_sum; /* The byte sum of the pkg. */ +}; + +struct isp4fw_resp { + u32 resp_seq_num; + u32 resp_id; + union { + struct isp4fw_resp_cmd_done cmd_done; + struct isp4fw_resp_param_package frame_done; + u32 resp_param[12]; + } param; + u8 reserved[4]; + u32 resp_check_sum; +}; + +struct isp4fw_mipi_pipe_path_cfg { + u32 b_enable; + enum isp4fw_sensor_id isp4fw_sensor_id; +}; + +struct isp4fw_isp_pipe_path_cfg { + u32 isp_pipe_id; /* pipe ids for pipeline construction */ +}; + +struct isp4fw_isp_stream_cfg { + /* Isp mipi path */ + struct isp4fw_mipi_pipe_path_cfg mipi_pipe_path_cfg; + /* Isp pipe path */ + struct isp4fw_isp_pipe_path_cfg isp_pipe_path_cfg; + /* enable TNR */ + u32 b_enable_tnr; + /* + * Number of frames for RTA processing. + * Set to 0 to use the firmware's default value. + */ + u32 rta_frames_per_proc; +}; + +struct isp4fw_image_prop { + enum isp4fw_image_format image_format; + u32 width; + u32 height; + u32 luma_pitch; + u32 chroma_pitch; + enum isp4fw_yuv_range yuv_range; +}; + +struct isp4fw_buffer { + /* + * A check num for debug usage, host can set the buf_tags + * to different numbers + */ + u32 buf_tags; + union { + u32 value; + struct { + u32 space : 16; + u32 vmid : 16; + } bit; + } vmid_space; + u32 buf_base_a_lo; /* Low address of buffer A */ + u32 buf_base_a_hi; /* High address of buffer A */ + u32 buf_size_a; /* Buffer size of buffer A */ + + u32 buf_base_b_lo; /* Low address of buffer B */ + u32 buf_base_b_hi; /* High address of buffer B */ + u32 buf_size_b; /* Buffer size of buffer B */ + + u32 buf_base_c_lo; /* Low address of buffer C */ + u32 buf_base_c_hi; /* High address of buffer C */ + u32 buf_size_c; /* Buffer size of buffer C */ +}; + +struct isp4fw_buffer_meta_info { + u32 enabled; /* enabled flag */ + enum isp4fw_buffer_status status; /* BufferStatus */ + struct isp4fw_error_code err; /* err code */ + enum isp4fw_buffer_source source; /* BufferSource */ + struct isp4fw_image_prop image_prop; /* image_prop */ + struct isp4fw_buffer buffer; /* buffer info */ +}; + +struct isp4fw_meta_info { + u32 poc; /* frame id */ + u32 fc_id; /* frame ctl id */ + u32 time_stamp_lo; /* timestamp low 32 bits */ + u32 time_stamp_hi; /* timestamp_high 32 bits */ + struct isp4fw_buffer_meta_info preview; /* preview BufferMetaInfo */ +}; + +struct isp4fw_cmd_send_buffer { + enum isp4fw_buffer_type buffer_type; + struct isp4fw_buffer buffer; /* buffer info */ +}; + +struct isp4fw_cmd_set_out_ch_prop { + enum isp4fw_pipe_out_ch ch; /* ISP output channel */ + struct isp4fw_image_prop image_prop; /* image property */ +}; + +struct isp4fw_cmd_enable_out_ch { + enum isp4fw_pipe_out_ch ch; /* ISP output channel */ + u32 is_enable; /* If channel is enabled or not */ +}; + +struct isp4fw_cmd_set_stream_cfg { + struct isp4fw_isp_stream_cfg stream_cfg; /* stream path config */ +}; + +#endif /* _ISP4_FW_CMD_RESP_H_ */ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_hw_reg.h +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_hw_reg.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_HW_REG_H_ +#define _ISP4_HW_REG_H_ + +#include + +#define ISP_SOFT_RESET 0x62000 +#define ISP_SYS_INT0_EN 0x62010 +#define ISP_SYS_INT0_STATUS 0x62014 +#define ISP_SYS_INT0_ACK 0x62018 +#define ISP_CCPU_CNTL 0x62054 +#define ISP_STATUS 0x62058 +#define ISP_LOG_RB_BASE_LO0 0x62148 +#define ISP_LOG_RB_BASE_HI0 0x6214c +#define ISP_LOG_RB_SIZE0 0x62150 +#define ISP_LOG_RB_RPTR0 0x62154 +#define ISP_LOG_RB_WPTR0 0x62158 +#define ISP_RB_BASE_LO1 0x62170 +#define ISP_RB_BASE_HI1 0x62174 +#define ISP_RB_SIZE1 0x62178 +#define ISP_RB_RPTR1 0x6217c +#define ISP_RB_WPTR1 0x62180 +#define ISP_RB_BASE_LO2 0x62184 +#define ISP_RB_BASE_HI2 0x62188 +#define ISP_RB_SIZE2 0x6218c +#define ISP_RB_RPTR2 0x62190 +#define ISP_RB_WPTR2 0x62194 +#define ISP_RB_BASE_LO3 0x62198 +#define ISP_RB_BASE_HI3 0x6219c +#define ISP_RB_SIZE3 0x621a0 +#define ISP_RB_RPTR3 0x621a4 +#define ISP_RB_WPTR3 0x621a8 +#define ISP_RB_BASE_LO4 0x621ac +#define ISP_RB_BASE_HI4 0x621b0 +#define ISP_RB_SIZE4 0x621b4 +#define ISP_RB_RPTR4 0x621b8 +#define ISP_RB_WPTR4 0x621bc +#define ISP_RB_BASE_LO5 0x621c0 +#define ISP_RB_BASE_HI5 0x621c4 +#define ISP_RB_SIZE5 0x621c8 +#define ISP_RB_RPTR5 0x621cc +#define ISP_RB_WPTR5 0x621d0 +#define ISP_RB_BASE_LO6 0x621d4 +#define ISP_RB_BASE_HI6 0x621d8 +#define ISP_RB_SIZE6 0x621dc +#define ISP_RB_RPTR6 0x621e0 +#define ISP_RB_WPTR6 0x621e4 +#define ISP_RB_BASE_LO7 0x621e8 +#define ISP_RB_BASE_HI7 0x621ec +#define ISP_RB_SIZE7 0x621f0 +#define ISP_RB_RPTR7 0x621f4 +#define ISP_RB_WPTR7 0x621f8 +#define ISP_RB_BASE_LO8 0x621fc +#define ISP_RB_BASE_HI8 0x62200 +#define ISP_RB_SIZE8 0x62204 +#define ISP_RB_RPTR8 0x62208 +#define ISP_RB_WPTR8 0x6220c +#define ISP_RB_BASE_LO9 0x62210 +#define ISP_RB_BASE_HI9 0x62214 +#define ISP_RB_SIZE9 0x62218 +#define ISP_RB_RPTR9 0x6221c +#define ISP_RB_WPTR9 0x62220 +#define ISP_RB_BASE_LO10 0x62224 +#define ISP_RB_BASE_HI10 0x62228 +#define ISP_RB_SIZE10 0x6222c +#define ISP_RB_RPTR10 0x62230 +#define ISP_RB_WPTR10 0x62234 +#define ISP_RB_BASE_LO11 0x62238 +#define ISP_RB_BASE_HI11 0x6223c +#define ISP_RB_SIZE11 0x62240 +#define ISP_RB_RPTR11 0x62244 +#define ISP_RB_WPTR11 0x62248 +#define ISP_RB_BASE_LO12 0x6224c +#define ISP_RB_BASE_HI12 0x62250 +#define ISP_RB_SIZE12 0x62254 +#define ISP_RB_RPTR12 0x62258 +#define ISP_RB_WPTR12 0x6225c + +#define ISP_POWER_STATUS 0x60000 + +/* ISP_SOFT_RESET */ +#define ISP_SOFT_RESET__CCPU_SOFT_RESET_MASK 0x00000001UL + +/* ISP_CCPU_CNTL */ +#define ISP_CCPU_CNTL__CCPU_HOST_SOFT_RST_MASK 0x00040000UL + +/* ISP_STATUS */ +#define ISP_STATUS__CCPU_REPORT_MASK 0x000000feUL + +/* ISP_SYS_INT0_STATUS */ +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT9_INT_MASK 0x00010000UL +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT10_INT_MASK 0x00040000UL +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT11_INT_MASK 0x00100000UL +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT12_INT_MASK 0x00400000UL + +/* ISP_SYS_INT0_EN */ +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT9_EN_MASK 0x00010000UL +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT10_EN_MASK 0x00040000UL +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT11_EN_MASK 0x00100000UL +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT12_EN_MASK 0x00400000UL + +/* ISP_SYS_INT0_ACK */ +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT9_ACK_MASK 0x00010000UL +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT10_ACK_MASK 0x00040000UL +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT11_ACK_MASK 0x00100000UL +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT12_ACK_MASK 0x00400000UL + +/* Helper functions for reading isp registers */ +static inline u32 isp4hw_rreg(void __iomem *base, u32 reg) +{ + return readl(base + reg); +} + +/* Helper functions for writing isp registers */ +static inline void isp4hw_wreg(void __iomem *base, u32 reg, u32 val) +{ + return writel(val, base + reg); +} + +#endif /* _ISP4_HW_REG_H_ */ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_interface.c +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_interface.c @@ -0,0 +1,832 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include + +#include "isp4_debug.h" +#include "isp4_fw_cmd_resp.h" +#include "isp4_hw_reg.h" +#include "isp4_interface.h" + +#define ISP4IF_FW_RESP_RB_IRQ_EN_MASK \ + (ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT9_EN_MASK\ + | ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT12_EN_MASK) + +#define ISP4IF_FW_CMD_TIMEOUT (HZ / 2) + +struct isp4if_rb_config { + const char *name; + u32 index; + u32 reg_rptr; + u32 reg_wptr; + u32 reg_base_lo; + u32 reg_base_hi; + u32 reg_size; + u32 val_size; + u64 base_mc_addr; + void *base_sys_addr; +}; + +/* FW cmd ring buffer configuration */ +static struct isp4if_rb_config isp4if_cmd_rb_config[ISP4IF_STREAM_ID_MAX] = { + { + .name = "CMD_RB_GBL0", + .index = 3, + .reg_rptr = ISP_RB_RPTR4, + .reg_wptr = ISP_RB_WPTR4, + .reg_base_lo = ISP_RB_BASE_LO4, + .reg_base_hi = ISP_RB_BASE_HI4, + .reg_size = ISP_RB_SIZE4, + }, + { + .name = "CMD_RB_STR1", + .index = 0, + .reg_rptr = ISP_RB_RPTR1, + .reg_wptr = ISP_RB_WPTR1, + .reg_base_lo = ISP_RB_BASE_LO1, + .reg_base_hi = ISP_RB_BASE_HI1, + .reg_size = ISP_RB_SIZE1, + }, + { + .name = "CMD_RB_STR2", + .index = 1, + .reg_rptr = ISP_RB_RPTR2, + .reg_wptr = ISP_RB_WPTR2, + .reg_base_lo = ISP_RB_BASE_LO2, + .reg_base_hi = ISP_RB_BASE_HI2, + .reg_size = ISP_RB_SIZE2, + }, + { + .name = "CMD_RB_STR3", + .index = 2, + .reg_rptr = ISP_RB_RPTR3, + .reg_wptr = ISP_RB_WPTR3, + .reg_base_lo = ISP_RB_BASE_LO3, + .reg_base_hi = ISP_RB_BASE_HI3, + .reg_size = ISP_RB_SIZE3, + }, +}; + +/* FW resp ring buffer configuration */ +static struct isp4if_rb_config isp4if_resp_rb_config[ISP4IF_STREAM_ID_MAX] = { + { + .name = "RES_RB_GBL0", + .index = 3, + .reg_rptr = ISP_RB_RPTR12, + .reg_wptr = ISP_RB_WPTR12, + .reg_base_lo = ISP_RB_BASE_LO12, + .reg_base_hi = ISP_RB_BASE_HI12, + .reg_size = ISP_RB_SIZE12, + }, + { + .name = "RES_RB_STR1", + .index = 0, + .reg_rptr = ISP_RB_RPTR9, + .reg_wptr = ISP_RB_WPTR9, + .reg_base_lo = ISP_RB_BASE_LO9, + .reg_base_hi = ISP_RB_BASE_HI9, + .reg_size = ISP_RB_SIZE9, + }, + { + .name = "RES_RB_STR2", + .index = 1, + .reg_rptr = ISP_RB_RPTR10, + .reg_wptr = ISP_RB_WPTR10, + .reg_base_lo = ISP_RB_BASE_LO10, + .reg_base_hi = ISP_RB_BASE_HI10, + .reg_size = ISP_RB_SIZE10, + }, + { + .name = "RES_RB_STR3", + .index = 2, + .reg_rptr = ISP_RB_RPTR11, + .reg_wptr = ISP_RB_WPTR11, + .reg_base_lo = ISP_RB_BASE_LO11, + .reg_base_hi = ISP_RB_BASE_HI11, + .reg_size = ISP_RB_SIZE11, + }, +}; + +/* FW log ring buffer configuration */ +static struct isp4if_rb_config isp4if_log_rb_config = { + .name = "LOG_RB", + .index = 0, + .reg_rptr = ISP_LOG_RB_RPTR0, + .reg_wptr = ISP_LOG_RB_WPTR0, + .reg_base_lo = ISP_LOG_RB_BASE_LO0, + .reg_base_hi = ISP_LOG_RB_BASE_HI0, + .reg_size = ISP_LOG_RB_SIZE0, +}; + +static struct isp4if_gpu_mem_info * +isp4if_gpu_mem_alloc(struct isp4_interface *ispif, u32 mem_size) +{ + struct isp4if_gpu_mem_info *mem_info; + struct device *dev = ispif->dev; + int ret; + + mem_info = kmalloc(sizeof(*mem_info), GFP_KERNEL); + if (!mem_info) + return NULL; + + mem_info->mem_size = mem_size; + ret = isp_kernel_buffer_alloc(dev, mem_info->mem_size, + &mem_info->mem_handle, + &mem_info->gpu_mc_addr, + &mem_info->sys_addr); + if (ret) { + kfree(mem_info); + return NULL; + } + + return mem_info; +} + +static void isp4if_gpu_mem_free(struct isp4_interface *ispif, + struct isp4if_gpu_mem_info **mem_info_ptr) +{ + struct isp4if_gpu_mem_info *mem_info = *mem_info_ptr; + struct device *dev = ispif->dev; + + if (!mem_info) { + dev_err(dev, "invalid mem_info\n"); + return; + } + + *mem_info_ptr = NULL; + isp_kernel_buffer_free(&mem_info->mem_handle, &mem_info->gpu_mc_addr, + &mem_info->sys_addr); + kfree(mem_info); +} + +static void isp4if_dealloc_fw_gpumem(struct isp4_interface *ispif) +{ + isp4if_gpu_mem_free(ispif, &ispif->fw_mem_pool); + isp4if_gpu_mem_free(ispif, &ispif->fw_cmd_resp_buf); + isp4if_gpu_mem_free(ispif, &ispif->fw_log_buf); + + for (unsigned int i = 0; i < ISP4IF_MAX_STREAM_BUF_COUNT; i++) + isp4if_gpu_mem_free(ispif, &ispif->meta_info_buf[i]); +} + +static int isp4if_alloc_fw_gpumem(struct isp4_interface *ispif) +{ + struct device *dev = ispif->dev; + + ispif->fw_mem_pool = isp4if_gpu_mem_alloc(ispif, + ISP4FW_MEMORY_POOL_SIZE); + if (!ispif->fw_mem_pool) + goto error_no_memory; + + ispif->fw_cmd_resp_buf = + isp4if_gpu_mem_alloc(ispif, ISP4IF_RB_PMBMAP_MEM_SIZE); + if (!ispif->fw_cmd_resp_buf) + goto error_no_memory; + + ispif->fw_log_buf = + isp4if_gpu_mem_alloc(ispif, ISP4IF_FW_LOG_RINGBUF_SIZE); + if (!ispif->fw_log_buf) + goto error_no_memory; + + for (unsigned int i = 0; i < ISP4IF_MAX_STREAM_BUF_COUNT; i++) { + ispif->meta_info_buf[i] = + isp4if_gpu_mem_alloc(ispif, ISP4IF_META_INFO_BUF_SIZE); + if (!ispif->meta_info_buf[i]) + goto error_no_memory; + } + + return 0; + +error_no_memory: + dev_err(dev, "failed to allocate gpu memory\n"); + return -ENOMEM; +} + +static u32 isp4if_compute_check_sum(const void *buf, size_t buf_size) +{ + const u8 *surplus_ptr; + const u32 *buffer; + u32 checksum = 0; + size_t i; + + buffer = (const u32 *)buf; + for (i = 0; i < buf_size / sizeof(u32); i++) + checksum += buffer[i]; + + surplus_ptr = (const u8 *)&buffer[i]; + /* add surplus data crc checksum */ + for (i = 0; i < buf_size % sizeof(u32); i++) + checksum += surplus_ptr[i]; + + return checksum; +} + +void isp4if_clear_cmdq(struct isp4_interface *ispif) +{ + struct isp4if_cmd_element *buf_node, *tmp_node; + LIST_HEAD(free_list); + + scoped_guard(spinlock, &ispif->cmdq_lock) + list_splice_init(&ispif->cmdq, &free_list); + + list_for_each_entry_safe(buf_node, tmp_node, &free_list, list) + kfree(buf_node); +} + +static bool isp4if_is_cmdq_rb_full(struct isp4_interface *ispif, + enum isp4if_stream_id stream) +{ + struct isp4if_rb_config *rb_config = &isp4if_cmd_rb_config[stream]; + u32 rreg = rb_config->reg_rptr, wreg = rb_config->reg_wptr; + u32 len = rb_config->val_size; + u32 rd_ptr, wr_ptr; + u32 bytes_free; + + rd_ptr = isp4hw_rreg(ispif->mmio, rreg); + wr_ptr = isp4hw_rreg(ispif->mmio, wreg); + + /* + * Read and write pointers are equal, indicating the ring buffer + * is empty + */ + if (wr_ptr == rd_ptr) + return false; + + if (wr_ptr > rd_ptr) + bytes_free = len - (wr_ptr - rd_ptr); + else + bytes_free = rd_ptr - wr_ptr; + + /* + * Ignore one byte from the bytes free to prevent rd_ptr from equaling + * wr_ptr when the ring buffer is full, because rd_ptr == wr_ptr is + * supposed to indicate that the ring buffer is empty. + */ + return bytes_free <= sizeof(struct isp4fw_cmd); +} + +struct isp4if_cmd_element *isp4if_rm_cmd_from_cmdq(struct isp4_interface *ispif, + u32 seq_num, u32 cmd_id) +{ + struct isp4if_cmd_element *ele; + + guard(spinlock)(&ispif->cmdq_lock); + + list_for_each_entry(ele, &ispif->cmdq, list) { + if (ele->seq_num == seq_num && ele->cmd_id == cmd_id) { + list_del(&ele->list); + return ele; + } + } + + return NULL; +} + +/* Must check that isp4if_is_cmdq_rb_full() == false before calling */ +static int isp4if_insert_isp_fw_cmd(struct isp4_interface *ispif, + enum isp4if_stream_id stream, + const struct isp4fw_cmd *cmd) +{ + struct isp4if_rb_config *rb_config = &isp4if_cmd_rb_config[stream]; + u32 rreg = rb_config->reg_rptr, wreg = rb_config->reg_wptr; + void *mem_sys = rb_config->base_sys_addr; + const u32 cmd_sz = sizeof(*cmd); + struct device *dev = ispif->dev; + u32 len = rb_config->val_size; + const void *src = cmd; + u32 rd_ptr, wr_ptr; + u32 bytes_to_end; + + rd_ptr = isp4hw_rreg(ispif->mmio, rreg); + wr_ptr = isp4hw_rreg(ispif->mmio, wreg); + if (rd_ptr >= len || wr_ptr >= len) { + dev_err(dev, + "rb invalid: stream=%u(%s), rd=%u, wr=%u, len=%u, cmd_sz=%u\n", + stream, isp4dbg_get_if_stream_str(stream), rd_ptr, + wr_ptr, len, cmd_sz); + return -EINVAL; + } + + bytes_to_end = len - wr_ptr; + if (bytes_to_end >= cmd_sz) { + /* FW cmd is just a straight copy to the write pointer */ + memcpy(mem_sys + wr_ptr, src, cmd_sz); + isp4hw_wreg(ispif->mmio, wreg, (wr_ptr + cmd_sz) % len); + } else { + /* + * FW cmd is split because the ring buffer needs to wrap + * around + */ + memcpy(mem_sys + wr_ptr, src, bytes_to_end); + memcpy(mem_sys, src + bytes_to_end, cmd_sz - bytes_to_end); + isp4hw_wreg(ispif->mmio, wreg, cmd_sz - bytes_to_end); + } + + return 0; +} + +static inline enum isp4if_stream_id isp4if_get_fw_stream(u32 cmd_id) +{ + return ISP4IF_STREAM_ID_1; +} + +static int isp4if_send_fw_cmd(struct isp4_interface *ispif, u32 cmd_id, + const void *package, + u32 package_size, bool sync) +{ + enum isp4if_stream_id stream = isp4if_get_fw_stream(cmd_id); + struct isp4if_cmd_element *ele = NULL; + struct device *dev = ispif->dev; + struct isp4fw_cmd cmd; + u32 seq_num; + int ret; + + if (package_size > sizeof(cmd.cmd_param)) { + dev_err(dev, "fail pkgsize(%u) > %zu cmd:0x%x, stream %d\n", + package_size, sizeof(cmd.cmd_param), cmd_id, stream); + return -EINVAL; + } + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&cmd, 0, sizeof(cmd)); + cmd.cmd_id = cmd_id; + switch (stream) { + case ISP4IF_STREAM_ID_GLOBAL: + cmd.cmd_stream_id = ISP4FW_STREAM_ID_INVALID; + break; + case ISP4IF_STREAM_ID_1: + cmd.cmd_stream_id = ISP4FW_STREAM_ID_1; + break; + default: + dev_err(dev, "fail bad stream id %d\n", stream); + return -EINVAL; + } + + /* Allocate the sync command object early and outside of the lock */ + if (sync) { + ele = kmalloc(sizeof(*ele), GFP_KERNEL); + if (!ele) + return -ENOMEM; + + /* Get two references: one for the resp thread, one for us */ + atomic_set(&ele->refcnt, 2); + init_completion(&ele->cmd_done); + } + + if (package && package_size) + memcpy(cmd.cmd_param, package, package_size); + + scoped_guard(mutex, &ispif->isp4if_mutex) { + ret = read_poll_timeout(isp4if_is_cmdq_rb_full, ret, !ret, + ISP4IF_RB_FULL_SLEEP_US, + ISP4IF_RB_FULL_TIMEOUT_US, false, ispif, + stream); + if (ret) { + struct isp4if_rb_config *rb_config = + &isp4if_resp_rb_config[stream]; + u32 rd_ptr = isp4hw_rreg(ispif->mmio, + rb_config->reg_rptr); + u32 wr_ptr = isp4hw_rreg(ispif->mmio, + rb_config->reg_wptr); + + dev_err(dev, + "failed to get free cmdq slot, stream %s(%d),rd %u, wr %u\n", + isp4dbg_get_if_stream_str(stream), stream, + rd_ptr, wr_ptr); + ret = -ETIMEDOUT; + goto free_ele; + } + + seq_num = ispif->host2fw_seq_num++; + cmd.cmd_seq_num = seq_num; + cmd.cmd_check_sum = isp4if_compute_check_sum(&cmd, sizeof(cmd) + - sizeof(u32)); + + /* + * only append the fw cmd to queue when its response needs to + * be waited for, currently there are only two such commands, + * disable channel and stop stream which are only sent after + * close camera + */ + if (ele) { + ele->seq_num = seq_num; + ele->cmd_id = cmd_id; + scoped_guard(spinlock, &ispif->cmdq_lock) + list_add_tail(&ele->list, &ispif->cmdq); + } + + ret = isp4if_insert_isp_fw_cmd(ispif, stream, &cmd); + if (ret) { + dev_err(dev, + "fail for insert_isp_fw_cmd cmd_id %s(0x%08x)\n", + isp4dbg_get_cmd_str(cmd_id), cmd_id); + goto err_dequeue_ele; + } + } + + if (ele) { + ret = wait_for_completion_timeout(&ele->cmd_done, + ISP4IF_FW_CMD_TIMEOUT); + if (!ret) { + ret = -ETIMEDOUT; + goto err_dequeue_ele; + } + + ret = 0; + goto put_ele_ref; + } + + return 0; + +err_dequeue_ele: + /* + * Try to remove the command from the queue. If that fails, then it + * means the response thread is currently using the object, and we need + * to use the refcount to avoid a use-after-free by either side. + */ + if (ele && isp4if_rm_cmd_from_cmdq(ispif, seq_num, cmd_id)) + goto free_ele; + +put_ele_ref: + /* Don't free the command if we didn't put the last reference */ + if (ele && atomic_dec_return(&ele->refcnt)) + ele = NULL; + +free_ele: + kfree(ele); + return ret; +} + +static int isp4if_send_buffer(struct isp4_interface *ispif, + struct isp4if_img_buf_info *buf_info) +{ + struct isp4fw_cmd_send_buffer cmd; + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&cmd, 0, sizeof(cmd)); + cmd.buffer_type = ISP4FW_BUFFER_TYPE_PREVIEW; + cmd.buffer.vmid_space.bit.space = ISP4FW_ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(buf_info->planes[0].mc_addr, + &cmd.buffer.buf_base_a_lo, + &cmd.buffer.buf_base_a_hi); + cmd.buffer.buf_size_a = buf_info->planes[0].len; + + isp4if_split_addr64(buf_info->planes[1].mc_addr, + &cmd.buffer.buf_base_b_lo, + &cmd.buffer.buf_base_b_hi); + cmd.buffer.buf_size_b = buf_info->planes[1].len; + + isp4if_split_addr64(buf_info->planes[2].mc_addr, + &cmd.buffer.buf_base_c_lo, + &cmd.buffer.buf_base_c_hi); + cmd.buffer.buf_size_c = buf_info->planes[2].len; + + return isp4if_send_fw_cmd(ispif, ISP4FW_CMD_ID_SEND_BUFFER, &cmd, + sizeof(cmd), false); +} + +static void isp4if_init_rb_config(struct isp4_interface *ispif, + struct isp4if_rb_config *rb_config) +{ + isp4hw_wreg(ispif->mmio, rb_config->reg_rptr, 0x0); + isp4hw_wreg(ispif->mmio, rb_config->reg_wptr, 0x0); + isp4hw_wreg(ispif->mmio, rb_config->reg_base_lo, + rb_config->base_mc_addr); + isp4hw_wreg(ispif->mmio, rb_config->reg_base_hi, + rb_config->base_mc_addr >> 32); + isp4hw_wreg(ispif->mmio, rb_config->reg_size, rb_config->val_size); +} + +static int isp4if_fw_init(struct isp4_interface *ispif) +{ + u32 aligned_rb_chunk_size = ISP4IF_RB_PMBMAP_MEM_CHUNK & 0xffffffc0; + struct isp4if_rb_config *rb_config; + u32 offset; + unsigned int i; + + /* initialize CMD_RB streams */ + for (i = 0; i < ISP4IF_STREAM_ID_MAX; i++) { + rb_config = (isp4if_cmd_rb_config + i); + offset = aligned_rb_chunk_size * rb_config->index; + + rb_config->val_size = ISP4IF_FW_CMD_BUF_SIZE; + rb_config->base_sys_addr = + ispif->fw_cmd_resp_buf->sys_addr + offset; + rb_config->base_mc_addr = + ispif->fw_cmd_resp_buf->gpu_mc_addr + offset; + + isp4if_init_rb_config(ispif, rb_config); + } + + /* initialize RESP_RB streams */ + for (i = 0; i < ISP4IF_STREAM_ID_MAX; i++) { + rb_config = (isp4if_resp_rb_config + i); + offset = aligned_rb_chunk_size * + (rb_config->index + ISP4IF_RESP_CHAN_TO_RB_OFFSET - 1); + + rb_config->val_size = ISP4IF_FW_CMD_BUF_SIZE; + rb_config->base_sys_addr = + ispif->fw_cmd_resp_buf->sys_addr + offset; + rb_config->base_mc_addr = + ispif->fw_cmd_resp_buf->gpu_mc_addr + offset; + + isp4if_init_rb_config(ispif, rb_config); + } + + /* initialize LOG_RB stream */ + rb_config = &isp4if_log_rb_config; + rb_config->val_size = ISP4IF_FW_LOG_RINGBUF_SIZE; + rb_config->base_mc_addr = ispif->fw_log_buf->gpu_mc_addr; + rb_config->base_sys_addr = ispif->fw_log_buf->sys_addr; + + isp4if_init_rb_config(ispif, rb_config); + + return 0; +} + +static int isp4if_wait_fw_ready(struct isp4_interface *ispif, + u32 isp_status_addr) +{ + struct device *dev = ispif->dev; + u32 timeout_ms = 100; + u32 interval_ms = 1; + u32 reg_val; + + /* wait for FW initialize done! */ + if (!read_poll_timeout(isp4hw_rreg, reg_val, reg_val + & ISP_STATUS__CCPU_REPORT_MASK, + interval_ms * 1000, timeout_ms * 1000, false, + ispif->mmio, isp_status_addr)) + return 0; + + dev_err(dev, "ISP CCPU FW boot failed\n"); + + return -ETIME; +} + +static void isp4if_enable_ccpu(struct isp4_interface *ispif) +{ + u32 reg_val; + + reg_val = isp4hw_rreg(ispif->mmio, ISP_SOFT_RESET); + reg_val &= (~ISP_SOFT_RESET__CCPU_SOFT_RESET_MASK); + isp4hw_wreg(ispif->mmio, ISP_SOFT_RESET, reg_val); + + usleep_range(100, 150); + + reg_val = isp4hw_rreg(ispif->mmio, ISP_CCPU_CNTL); + reg_val &= (~ISP_CCPU_CNTL__CCPU_HOST_SOFT_RST_MASK); + isp4hw_wreg(ispif->mmio, ISP_CCPU_CNTL, reg_val); +} + +static void isp4if_disable_ccpu(struct isp4_interface *ispif) +{ + u32 reg_val; + + reg_val = isp4hw_rreg(ispif->mmio, ISP_CCPU_CNTL); + reg_val |= ISP_CCPU_CNTL__CCPU_HOST_SOFT_RST_MASK; + isp4hw_wreg(ispif->mmio, ISP_CCPU_CNTL, reg_val); + + usleep_range(100, 150); + + reg_val = isp4hw_rreg(ispif->mmio, ISP_SOFT_RESET); + reg_val |= ISP_SOFT_RESET__CCPU_SOFT_RESET_MASK; + isp4hw_wreg(ispif->mmio, ISP_SOFT_RESET, reg_val); +} + +static int isp4if_fw_boot(struct isp4_interface *ispif) +{ + struct device *dev = ispif->dev; + + if (ispif->status != ISP4IF_STATUS_PWR_ON) { + dev_err(dev, "invalid isp power status %d\n", ispif->status); + return -EINVAL; + } + + isp4if_disable_ccpu(ispif); + + isp4if_fw_init(ispif); + + /* clear ccpu status */ + isp4hw_wreg(ispif->mmio, ISP_STATUS, 0x0); + + isp4if_enable_ccpu(ispif); + + if (isp4if_wait_fw_ready(ispif, ISP_STATUS)) { + isp4if_disable_ccpu(ispif); + return -EINVAL; + } + + /* enable interrupts */ + isp4hw_wreg(ispif->mmio, ISP_SYS_INT0_EN, + ISP4IF_FW_RESP_RB_IRQ_EN_MASK); + + ispif->status = ISP4IF_STATUS_FW_RUNNING; + + dev_dbg(dev, "ISP CCPU FW boot success\n"); + + return 0; +} + +int isp4if_f2h_resp(struct isp4_interface *ispif, enum isp4if_stream_id stream, + struct isp4fw_resp *resp) +{ + struct isp4if_rb_config *rb_config = &isp4if_resp_rb_config[stream]; + u32 rreg = rb_config->reg_rptr, wreg = rb_config->reg_wptr; + void *mem_sys = rb_config->base_sys_addr; + const u32 resp_sz = sizeof(*resp); + struct device *dev = ispif->dev; + u32 len = rb_config->val_size; + u32 rd_ptr, wr_ptr; + u32 bytes_to_end; + void *dst = resp; + u32 checksum; + + rd_ptr = isp4hw_rreg(ispif->mmio, rreg); + wr_ptr = isp4hw_rreg(ispif->mmio, wreg); + if (rd_ptr >= len || wr_ptr >= len) + goto err_rb_invalid; + + /* + * Read and write pointers are equal, indicating the ring buffer is + * empty + */ + if (rd_ptr == wr_ptr) + return -ENODATA; + + bytes_to_end = len - rd_ptr; + if (bytes_to_end >= resp_sz) { + /* FW response is just a straight copy from the read pointer */ + if (wr_ptr > rd_ptr && wr_ptr - rd_ptr < resp_sz) + goto err_rb_invalid; + + memcpy(dst, mem_sys + rd_ptr, resp_sz); + isp4hw_wreg(ispif->mmio, rreg, (rd_ptr + resp_sz) % len); + } else { + /* + * FW response is split because the ring buffer wrapped + * around + */ + if (wr_ptr > rd_ptr || wr_ptr < resp_sz - bytes_to_end) + goto err_rb_invalid; + + memcpy(dst, mem_sys + rd_ptr, bytes_to_end); + memcpy(dst + bytes_to_end, mem_sys, resp_sz - bytes_to_end); + isp4hw_wreg(ispif->mmio, rreg, resp_sz - bytes_to_end); + } + + checksum = isp4if_compute_check_sum(resp, resp_sz - sizeof(u32)); + if (checksum != resp->resp_check_sum) { + dev_err(dev, "resp checksum 0x%x,should 0x%x,rptr %u,wptr %u\n", + checksum, resp->resp_check_sum, rd_ptr, wr_ptr); + dev_err(dev, "%s(%u), seqNo %u, resp_id %s(0x%x)\n", + isp4dbg_get_if_stream_str(stream), stream, + resp->resp_seq_num, isp4dbg_get_resp_str(resp->resp_id), + resp->resp_id); + return -EINVAL; + } + + return 0; + +err_rb_invalid: + dev_err(dev, + "rb invalid: stream=%u(%s), rd=%u, wr=%u, len=%u, resp_sz=%u\n", + stream, isp4dbg_get_if_stream_str(stream), rd_ptr, wr_ptr, len, + resp_sz); + return -EINVAL; +} + +int isp4if_send_command(struct isp4_interface *ispif, u32 cmd_id, + const void *package, u32 package_size) +{ + return isp4if_send_fw_cmd(ispif, cmd_id, package, package_size, false); +} + +int isp4if_send_command_sync(struct isp4_interface *ispif, u32 cmd_id, + const void *package, u32 package_size) +{ + return isp4if_send_fw_cmd(ispif, cmd_id, package, package_size, true); +} + +void isp4if_clear_bufq(struct isp4_interface *ispif) +{ + struct isp4if_img_buf_node *buf_node, *tmp_node; + LIST_HEAD(free_list); + + scoped_guard(spinlock, &ispif->bufq_lock) + list_splice_init(&ispif->bufq, &free_list); + + list_for_each_entry_safe(buf_node, tmp_node, &free_list, node) + kfree(buf_node); +} + +void isp4if_dealloc_buffer_node(struct isp4if_img_buf_node *buf_node) +{ + kfree(buf_node); +} + +struct isp4if_img_buf_node * +isp4if_alloc_buffer_node(struct isp4if_img_buf_info *buf_info) +{ + struct isp4if_img_buf_node *node; + + node = kmalloc(sizeof(*node), GFP_KERNEL); + if (node) + node->buf_info = *buf_info; + + return node; +} + +struct isp4if_img_buf_node *isp4if_dequeue_buffer(struct isp4_interface *ispif) +{ + struct isp4if_img_buf_node *buf_node; + + guard(spinlock)(&ispif->bufq_lock); + + buf_node = list_first_entry_or_null(&ispif->bufq, typeof(*buf_node), + node); + if (buf_node) + list_del(&buf_node->node); + + return buf_node; +} + +int isp4if_queue_buffer(struct isp4_interface *ispif, + struct isp4if_img_buf_node *buf_node) +{ + int ret; + + ret = isp4if_send_buffer(ispif, &buf_node->buf_info); + if (ret) + return ret; + + scoped_guard(spinlock, &ispif->bufq_lock) + list_add_tail(&buf_node->node, &ispif->bufq); + + return 0; +} + +int isp4if_stop(struct isp4_interface *ispif) +{ + isp4if_disable_ccpu(ispif); + + isp4if_dealloc_fw_gpumem(ispif); + + return 0; +} + +int isp4if_start(struct isp4_interface *ispif) +{ + int ret; + + ret = isp4if_alloc_fw_gpumem(ispif); + if (ret) + return ret; + + ret = isp4if_fw_boot(ispif); + if (ret) + goto failed_fw_boot; + + return 0; + +failed_fw_boot: + isp4if_dealloc_fw_gpumem(ispif); + return ret; +} + +int isp4if_deinit(struct isp4_interface *ispif) +{ + isp4if_clear_cmdq(ispif); + + isp4if_clear_bufq(ispif); + + mutex_destroy(&ispif->isp4if_mutex); + + return 0; +} + +int isp4if_init(struct isp4_interface *ispif, struct device *dev, + void __iomem *isp_mmio) +{ + ispif->dev = dev; + ispif->mmio = isp_mmio; + + spin_lock_init(&ispif->cmdq_lock); /* used for cmdq access */ + spin_lock_init(&ispif->bufq_lock); /* used for bufq access */ + mutex_init(&ispif->isp4if_mutex); /* used for commands sent to ispfw */ + + INIT_LIST_HEAD(&ispif->cmdq); + INIT_LIST_HEAD(&ispif->bufq); + + return 0; +} --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_interface.h +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_interface.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_INTERFACE_H_ +#define _ISP4_INTERFACE_H_ + +#include +#include +#include +#include + +struct isp4fw_resp; + +#define ISP4IF_RB_MAX 25 +#define ISP4IF_RESP_CHAN_TO_RB_OFFSET 9 +#define ISP4IF_RB_PMBMAP_MEM_SIZE (SZ_16M - 1) +#define ISP4IF_RB_PMBMAP_MEM_CHUNK \ + (ISP4IF_RB_PMBMAP_MEM_SIZE / (ISP4IF_RB_MAX - 1)) +#define ISP4IF_HOST2FW_COMMAND_SIZE sizeof(struct isp4fw_cmd) +#define ISP4IF_MAX_NUM_HOST2FW_COMMAND 40 +#define ISP4IF_FW_CMD_BUF_SIZE \ + (ISP4IF_MAX_NUM_HOST2FW_COMMAND * ISP4IF_HOST2FW_COMMAND_SIZE) +#define ISP4IF_RB_FULL_SLEEP_US (33 * USEC_PER_MSEC) +#define ISP4IF_RB_FULL_TIMEOUT_US (10 * ISP4IF_RB_FULL_SLEEP_US) + +#define ISP4IF_META_INFO_BUF_SIZE ALIGN(sizeof(struct isp4fw_meta_info), 0x8000) +#define ISP4IF_MAX_STREAM_BUF_COUNT 8 + +#define ISP4IF_FW_LOG_RINGBUF_SIZE SZ_2M + +enum isp4if_stream_id { + ISP4IF_STREAM_ID_GLOBAL = 0, + ISP4IF_STREAM_ID_1 = 1, + ISP4IF_STREAM_ID_MAX = 4 +}; + +enum isp4if_status { + ISP4IF_STATUS_PWR_OFF, + ISP4IF_STATUS_PWR_ON, + ISP4IF_STATUS_FW_RUNNING, + ISP4IF_FSM_STATUS_MAX +}; + +struct isp4if_gpu_mem_info { + u64 mem_size; + u64 gpu_mc_addr; + void *sys_addr; + void *mem_handle; +}; + +struct isp4if_img_buf_info { + struct { + void *sys_addr; + u64 mc_addr; + u32 len; + } planes[3]; +}; + +struct isp4if_img_buf_node { + struct list_head node; + struct isp4if_img_buf_info buf_info; +}; + +struct isp4if_cmd_element { + struct list_head list; + u32 seq_num; + u32 cmd_id; + struct completion cmd_done; + atomic_t refcnt; +}; + +struct isp4_interface { + struct device *dev; + void __iomem *mmio; + + spinlock_t cmdq_lock; /* used for cmdq access */ + spinlock_t bufq_lock; /* used for bufq access */ + struct mutex isp4if_mutex; /* used to send fw cmd and read fw log */ + + struct list_head cmdq; /* commands sent to fw */ + struct list_head bufq; /* buffers sent to fw */ + + enum isp4if_status status; + u32 host2fw_seq_num; + + /* ISP fw buffers */ + struct isp4if_gpu_mem_info *fw_log_buf; + struct isp4if_gpu_mem_info *fw_cmd_resp_buf; + struct isp4if_gpu_mem_info *fw_mem_pool; + struct isp4if_gpu_mem_info *meta_info_buf[ISP4IF_MAX_STREAM_BUF_COUNT]; +}; + +static inline void isp4if_split_addr64(u64 addr, u32 *lo, u32 *hi) +{ + if (lo) + *lo = addr & 0xffffffff; + + if (hi) + *hi = addr >> 32; +} + +static inline u64 isp4if_join_addr64(u32 lo, u32 hi) +{ + return (((u64)hi) << 32) | (u64)lo; +} + +int isp4if_f2h_resp(struct isp4_interface *ispif, enum isp4if_stream_id stream, + struct isp4fw_resp *resp); + +int isp4if_send_command(struct isp4_interface *ispif, u32 cmd_id, + const void *package, u32 package_size); + +int isp4if_send_command_sync(struct isp4_interface *ispif, u32 cmd_id, + const void *package, u32 package_size); + +struct isp4if_cmd_element *isp4if_rm_cmd_from_cmdq(struct isp4_interface *ispif, + u32 seq_num, u32 cmd_id); + +void isp4if_clear_cmdq(struct isp4_interface *ispif); + +void isp4if_clear_bufq(struct isp4_interface *ispif); + +void isp4if_dealloc_buffer_node(struct isp4if_img_buf_node *buf_node); + +struct isp4if_img_buf_node * +isp4if_alloc_buffer_node(struct isp4if_img_buf_info *buf_info); + +struct isp4if_img_buf_node *isp4if_dequeue_buffer(struct isp4_interface *ispif); + +int isp4if_queue_buffer(struct isp4_interface *ispif, + struct isp4if_img_buf_node *buf_node); + +int isp4if_stop(struct isp4_interface *ispif); + +int isp4if_start(struct isp4_interface *ispif); + +int isp4if_deinit(struct isp4_interface *ispif); + +int isp4if_init(struct isp4_interface *ispif, struct device *dev, + void __iomem *isp_mmio); + +#endif /* _ISP4_INTERFACE_H_ */ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_subdev.c +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_subdev.c @@ -0,0 +1,1047 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include + +#include "isp4.h" +#include "isp4_debug.h" +#include "isp4_fw_cmd_resp.h" +#include "isp4_interface.h" + +#define ISP4SD_MIN_BUF_CNT_BEF_START_STREAM 4 + +#define ISP4SD_PERFORMANCE_STATE_LOW 0 +#define ISP4SD_PERFORMANCE_STATE_HIGH 1 + +/* align 32KB */ +#define ISP4SD_META_BUF_SIZE ALIGN(sizeof(struct isp4fw_meta_info), 0x8000) + +#define to_isp4_subdev(sd) container_of(sd, struct isp4_subdev, sdev) + +static const char *isp4sd_entity_name = "amd isp4"; + +static const char *isp4sd_thread_name[ISP4SD_MAX_FW_RESP_STREAM_NUM] = { + "amd_isp4_thread_global", + "amd_isp4_thread_stream1", +}; + +static void isp4sd_module_enable(struct isp4_subdev *isp_subdev, bool enable) +{ + if (isp_subdev->enable_gpio) { + gpiod_set_value(isp_subdev->enable_gpio, enable ? 1 : 0); + dev_dbg(isp_subdev->dev, "%s isp_subdev module\n", + enable ? "enable" : "disable"); + } +} + +static int isp4sd_setup_fw_mem_pool(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_send_buffer buf_type; + struct device *dev = isp_subdev->dev; + int ret; + + if (!ispif->fw_mem_pool) { + dev_err(dev, "fail to alloc mem pool\n"); + return -ENOMEM; + } + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&buf_type, 0, sizeof(buf_type)); + buf_type.buffer_type = ISP4FW_BUFFER_TYPE_MEM_POOL; + buf_type.buffer.vmid_space.bit.space = ISP4FW_ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(ispif->fw_mem_pool->gpu_mc_addr, + &buf_type.buffer.buf_base_a_lo, + &buf_type.buffer.buf_base_a_hi); + buf_type.buffer.buf_size_a = ispif->fw_mem_pool->mem_size; + + ret = isp4if_send_command(ispif, ISP4FW_CMD_ID_SEND_BUFFER, + &buf_type, sizeof(buf_type)); + if (ret) { + dev_err(dev, "send fw mem pool 0x%llx(%u) fail %d\n", + ispif->fw_mem_pool->gpu_mc_addr, + buf_type.buffer.buf_size_a, ret); + return ret; + } + + dev_dbg(dev, "send fw mem pool 0x%llx(%u) suc\n", + ispif->fw_mem_pool->gpu_mc_addr, buf_type.buffer.buf_size_a); + + return 0; +} + +static int isp4sd_set_stream_path(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_set_stream_cfg cmd; + struct device *dev = isp_subdev->dev; + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&cmd, 0, sizeof(cmd)); + cmd.stream_cfg.mipi_pipe_path_cfg.isp4fw_sensor_id = + ISP4FW_SENSOR_ID_ON_MIPI0; + cmd.stream_cfg.mipi_pipe_path_cfg.b_enable = true; + cmd.stream_cfg.isp_pipe_path_cfg.isp_pipe_id = + ISP4FW_MIPI0_ISP_PIPELINE_ID; + + cmd.stream_cfg.b_enable_tnr = true; + dev_dbg(dev, "isp4fw_sensor_id %d, pipeId 0x%x EnableTnr %u\n", + cmd.stream_cfg.mipi_pipe_path_cfg.isp4fw_sensor_id, + cmd.stream_cfg.isp_pipe_path_cfg.isp_pipe_id, + cmd.stream_cfg.b_enable_tnr); + + return isp4if_send_command(ispif, ISP4FW_CMD_ID_SET_STREAM_CONFIG, + &cmd, sizeof(cmd)); +} + +static int isp4sd_send_meta_buf(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_send_buffer buf_type; + struct device *dev = isp_subdev->dev; + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&buf_type, 0, sizeof(buf_type)); + for (unsigned int i = 0; i < ISP4IF_MAX_STREAM_BUF_COUNT; i++) { + struct isp4if_gpu_mem_info *meta_info_buf = + isp_subdev->ispif.meta_info_buf[i]; + int ret; + + if (!meta_info_buf) { + dev_err(dev, "fail for no meta info buf(%u)\n", i); + return -ENOMEM; + } + + buf_type.buffer_type = ISP4FW_BUFFER_TYPE_META_INFO; + buf_type.buffer.vmid_space.bit.space = + ISP4FW_ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(meta_info_buf->gpu_mc_addr, + &buf_type.buffer.buf_base_a_lo, + &buf_type.buffer.buf_base_a_hi); + buf_type.buffer.buf_size_a = meta_info_buf->mem_size; + ret = isp4if_send_command(ispif, ISP4FW_CMD_ID_SEND_BUFFER, + &buf_type, sizeof(buf_type)); + if (ret) { + dev_err(dev, "send meta info(%u) fail\n", i); + return ret; + } + } + + dev_dbg(dev, "send meta info suc\n"); + return 0; +} + +static bool isp4sd_get_str_out_prop(struct isp4_subdev *isp_subdev, + struct isp4fw_image_prop *out_prop, + struct v4l2_subdev_state *state, u32 pad) +{ + struct device *dev = isp_subdev->dev; + struct v4l2_mbus_framefmt *format; + + format = v4l2_subdev_state_get_format(state, pad, 0); + if (!format) { + dev_err(dev, "fail get subdev state format\n"); + return false; + } + + switch (format->code) { + case MEDIA_BUS_FMT_YUYV8_1_5X8: + out_prop->image_format = ISP4FW_IMAGE_FORMAT_NV12; + out_prop->width = format->width; + out_prop->height = format->height; + out_prop->luma_pitch = format->width; + out_prop->chroma_pitch = out_prop->width; + break; + case MEDIA_BUS_FMT_YUYV8_1X16: + out_prop->image_format = ISP4FW_IMAGE_FORMAT_YUV422INTERLEAVED; + out_prop->width = format->width; + out_prop->height = format->height; + out_prop->luma_pitch = format->width * 2; + out_prop->chroma_pitch = 0; + break; + default: + dev_err(dev, "fail for bad image format:0x%x\n", + format->code); + return false; + } + + if (!out_prop->width || !out_prop->height) + return false; + + return true; +} + +static int isp4sd_kickoff_stream(struct isp4_subdev *isp_subdev, u32 w, u32 h) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + + if (sensor_info->status == ISP4SD_START_STATUS_STARTED) + return 0; + + if (sensor_info->status == ISP4SD_START_STATUS_START_FAIL) { + dev_err(dev, "fail for previous start fail\n"); + return -EINVAL; + } + + dev_dbg(dev, "w:%u,h:%u\n", w, h); + + if (isp4sd_send_meta_buf(isp_subdev)) { + dev_err(dev, "fail to send meta buf\n"); + sensor_info->status = ISP4SD_START_STATUS_START_FAIL; + return -EINVAL; + } + + sensor_info->status = ISP4SD_START_STATUS_OFF; + + if (!sensor_info->start_stream_cmd_sent && + sensor_info->buf_sent_cnt >= ISP4SD_MIN_BUF_CNT_BEF_START_STREAM) { + int ret = isp4if_send_command(ispif, ISP4FW_CMD_ID_START_STREAM, + NULL, 0); + if (ret) { + dev_err(dev, "fail to start stream\n"); + return ret; + } + + sensor_info->start_stream_cmd_sent = true; + } else { + dev_dbg(dev, + "no send START_STREAM, start_sent %u, buf_sent %u\n", + sensor_info->start_stream_cmd_sent, + sensor_info->buf_sent_cnt); + } + + return 0; +} + +static int isp4sd_setup_output(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_output_info *output_info = + &isp_subdev->sensor_info.output_info; + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_set_out_ch_prop cmd_ch_prop; + struct isp4fw_cmd_enable_out_ch cmd_ch_en; + struct device *dev = isp_subdev->dev; + int ret; + + if (output_info->start_status == ISP4SD_START_STATUS_STARTED) + return 0; + + if (output_info->start_status == ISP4SD_START_STATUS_START_FAIL) { + dev_err(dev, "fail for previous start fail\n"); + return -EINVAL; + } + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&cmd_ch_prop, 0, sizeof(cmd_ch_prop)); + cmd_ch_prop.ch = ISP4FW_ISP_PIPE_OUT_CH_PREVIEW; + + if (!isp4sd_get_str_out_prop(isp_subdev, + &cmd_ch_prop.image_prop, state, pad)) { + dev_err(dev, "fail to get out prop\n"); + return -EINVAL; + } + + dev_dbg(dev, "channel:%s,fmt %s,w:h=%u:%u,lp:%u,cp%u\n", + isp4dbg_get_out_ch_str(cmd_ch_prop.ch), + isp4dbg_get_img_fmt_str(cmd_ch_prop.image_prop.image_format), + cmd_ch_prop.image_prop.width, cmd_ch_prop.image_prop.height, + cmd_ch_prop.image_prop.luma_pitch, + cmd_ch_prop.image_prop.chroma_pitch); + + ret = isp4if_send_command(ispif, ISP4FW_CMD_ID_SET_OUT_CHAN_PROP, + &cmd_ch_prop, sizeof(cmd_ch_prop)); + if (ret) { + output_info->start_status = ISP4SD_START_STATUS_START_FAIL; + dev_err(dev, "fail to set out prop\n"); + return ret; + } + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&cmd_ch_en, 0, sizeof(cmd_ch_en)); + cmd_ch_en.ch = ISP4FW_ISP_PIPE_OUT_CH_PREVIEW; + cmd_ch_en.is_enable = true; + ret = isp4if_send_command(ispif, ISP4FW_CMD_ID_ENABLE_OUT_CHAN, + &cmd_ch_en, sizeof(cmd_ch_en)); + if (ret) { + output_info->start_status = ISP4SD_START_STATUS_START_FAIL; + dev_err(dev, "fail to enable channel\n"); + return ret; + } + + dev_dbg(dev, "enable channel %s\n", + isp4dbg_get_out_ch_str(cmd_ch_en.ch)); + + if (!sensor_info->start_stream_cmd_sent) { + ret = isp4sd_kickoff_stream(isp_subdev, + cmd_ch_prop.image_prop.width, + cmd_ch_prop.image_prop.height); + if (ret) { + dev_err(dev, "kickoff stream fail %d\n", ret); + return ret; + } + /* + * sensor_info->start_stream_cmd_sent will be set to true + * 1. in isp4sd_kickoff_stream, if app first send buffer then + * start stream + * 2. in isp_set_stream_buf, if app first start stream, then + * send buffer because ISP FW has the requirement, host needs + * to send buffer before send start stream cmd + */ + if (sensor_info->start_stream_cmd_sent) { + sensor_info->status = ISP4SD_START_STATUS_STARTED; + output_info->start_status = ISP4SD_START_STATUS_STARTED; + dev_dbg(dev, "kickoff stream suc,start cmd sent\n"); + } + } else { + dev_dbg(dev, "stream running, no need kickoff\n"); + output_info->start_status = ISP4SD_START_STATUS_STARTED; + } + + dev_dbg(dev, "setup output suc\n"); + return 0; +} + +static int isp4sd_init_stream(struct isp4_subdev *isp_subdev) +{ + struct device *dev = isp_subdev->dev; + int ret; + + ret = isp4sd_setup_fw_mem_pool(isp_subdev); + if (ret) { + dev_err(dev, "fail to setup fw mem pool\n"); + return ret; + } + + ret = isp4sd_set_stream_path(isp_subdev); + if (ret) { + dev_err(dev, "fail to setup stream path\n"); + return ret; + } + + return 0; +} + +static void isp4sd_uninit_stream(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4sd_output_info *output_info = &sensor_info->output_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct v4l2_mbus_framefmt *format; + + format = v4l2_subdev_state_get_format(state, pad, 0); + if (!format) { + dev_err(isp_subdev->dev, "fail to get v4l2 format\n"); + } else { + memset(format, 0, sizeof(*format)); + format->code = MEDIA_BUS_FMT_YUYV8_1_5X8; + } + + isp4if_clear_bufq(ispif); + isp4if_clear_cmdq(ispif); + + sensor_info->start_stream_cmd_sent = false; + sensor_info->buf_sent_cnt = 0; + + sensor_info->status = ISP4SD_START_STATUS_OFF; + output_info->start_status = ISP4SD_START_STATUS_OFF; +} + +static void isp4sd_fw_resp_cmd_done(struct isp4_subdev *isp_subdev, + enum isp4if_stream_id stream_id, + struct isp4fw_resp_cmd_done *para) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4if_cmd_element *ele = + isp4if_rm_cmd_from_cmdq(ispif, para->cmd_seq_num, para->cmd_id); + struct device *dev = isp_subdev->dev; + + dev_dbg(dev, "stream %d,cmd %s(0x%08x)(%d),seq %u, ele %p\n", + stream_id, + isp4dbg_get_cmd_str(para->cmd_id), + para->cmd_id, para->cmd_status, para->cmd_seq_num, + ele); + + if (ele) { + complete(&ele->cmd_done); + if (atomic_dec_and_test(&ele->refcnt)) + kfree(ele); + } +} + +static struct isp4fw_meta_info * +isp4sd_get_meta_by_mc(struct isp4_subdev *isp_subdev, u64 mc) +{ + for (unsigned int i = 0; i < ISP4IF_MAX_STREAM_BUF_COUNT; i++) { + struct isp4if_gpu_mem_info *meta_info_buf = + isp_subdev->ispif.meta_info_buf[i]; + + if (meta_info_buf->gpu_mc_addr == mc) + return meta_info_buf->sys_addr; + } + + return NULL; +} + +static void isp4sd_send_meta_info(struct isp4_subdev *isp_subdev, + u64 meta_info_mc) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_send_buffer buf_type; + struct device *dev = isp_subdev->dev; + + if (isp_subdev->sensor_info.status != ISP4SD_START_STATUS_STARTED) { + dev_warn(dev, "not working status %i, meta_info 0x%llx\n", + isp_subdev->sensor_info.status, meta_info_mc); + return; + } + + /* + * The struct will be shared with ISP FW, use memset() to guarantee + * padding bits are zeroed, since this is not guaranteed on all + * compilers. + */ + memset(&buf_type, 0, sizeof(buf_type)); + buf_type.buffer_type = ISP4FW_BUFFER_TYPE_META_INFO; + buf_type.buffer.vmid_space.bit.space = ISP4FW_ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(meta_info_mc, + &buf_type.buffer.buf_base_a_lo, + &buf_type.buffer.buf_base_a_hi); + buf_type.buffer.buf_size_a = ISP4SD_META_BUF_SIZE; + + if (isp4if_send_command(ispif, ISP4FW_CMD_ID_SEND_BUFFER, + &buf_type, sizeof(buf_type))) + dev_err(dev, "fail send meta_info 0x%llx\n", + meta_info_mc); + else + dev_dbg(dev, "resend meta_info 0x%llx\n", meta_info_mc); +} + +static void isp4sd_fw_resp_frame_done(struct isp4_subdev *isp_subdev, + enum isp4if_stream_id stream_id, + struct isp4fw_resp_param_package *para) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + struct isp4if_img_buf_node *prev; + struct isp4fw_meta_info *meta; + u64 mc; + + mc = isp4if_join_addr64(para->package_addr_lo, para->package_addr_hi); + meta = isp4sd_get_meta_by_mc(isp_subdev, mc); + if (!meta) { + dev_err(dev, "fail to get meta from mc %llx\n", mc); + return; + } + + dev_dbg(dev, "ts:%llu,streamId:%d,poc:%u,preview_en:%u,status:%s(%i)\n", + ktime_get_ns(), stream_id, meta->poc, meta->preview.enabled, + isp4dbg_get_buf_done_str(meta->preview.status), + meta->preview.status); + + if (meta->preview.enabled && + (meta->preview.status == ISP4FW_BUFFER_STATUS_SKIPPED || + meta->preview.status == ISP4FW_BUFFER_STATUS_DONE || + meta->preview.status == ISP4FW_BUFFER_STATUS_DIRTY)) { + prev = isp4if_dequeue_buffer(ispif); + if (prev) { + isp4dbg_show_bufmeta_info(dev, "prev", &meta->preview, + &prev->buf_info); + isp4vid_handle_frame_done(&isp_subdev->isp_vdev, + &prev->buf_info); + isp4if_dealloc_buffer_node(prev); + } else { + dev_err(dev, "fail null prev buf\n"); + } + } else if (meta->preview.enabled) { + dev_err(dev, "fail bad preview status %u(%s)\n", + meta->preview.status, + isp4dbg_get_buf_done_str(meta->preview.status)); + } + + if (isp_subdev->sensor_info.status == ISP4SD_START_STATUS_STARTED) + isp4sd_send_meta_info(isp_subdev, mc); + + dev_dbg(dev, "stream_id:%d, status:%d\n", stream_id, + isp_subdev->sensor_info.status); +} + +static void isp4sd_fw_resp_func(struct isp4_subdev *isp_subdev, + enum isp4if_stream_id stream_id) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + struct isp4fw_resp resp; + + if (stream_id == ISP4IF_STREAM_ID_1) + isp_fw_log_print(isp_subdev); + + while (true) { + if (isp4if_f2h_resp(ispif, stream_id, &resp)) { + /* Re-enable the interrupt */ + isp4_intr_enable(isp_subdev, stream_id, true); + /* + * Recheck to see if there is a new response. + * To ensure that an in-flight interrupt is not lost, + * enabling the interrupt must occur _before_ checking + * for a new response, hence a memory barrier is needed. + * Disable the interrupt again if there was a new + * response. + */ + mb(); + if (likely(isp4if_f2h_resp(ispif, stream_id, &resp))) + break; + + isp4_intr_enable(isp_subdev, stream_id, false); + } + + switch (resp.resp_id) { + case ISP4FW_RESP_ID_CMD_DONE: + isp4sd_fw_resp_cmd_done(isp_subdev, stream_id, + &resp.param.cmd_done); + break; + case ISP4FW_RESP_ID_NOTI_FRAME_DONE: + isp4sd_fw_resp_frame_done(isp_subdev, stream_id, + &resp.param.frame_done); + break; + default: + dev_err(dev, "-><- fail respid %s(0x%x)\n", + isp4dbg_get_resp_str(resp.resp_id), + resp.resp_id); + break; + } + } +} + +static s32 isp4sd_fw_resp_thread(void *context) +{ + struct isp4_subdev_thread_param *para = context; + struct isp4_subdev *isp_subdev = para->isp_subdev; + struct isp4sd_thread_handler *thread_ctx = + &isp_subdev->fw_resp_thread[para->idx]; + struct device *dev = isp_subdev->dev; + + dev_dbg(dev, "[%u] fw resp thread started\n", para->idx); + while (true) { + wait_event_interruptible(thread_ctx->waitq, + thread_ctx->resp_ready); + thread_ctx->resp_ready = false; + + if (kthread_should_stop()) { + dev_dbg(dev, "[%u] fw resp thread quit\n", para->idx); + break; + } + + isp4sd_fw_resp_func(isp_subdev, para->idx); + } + + return 0; +} + +static int isp4sd_stop_resp_proc_threads(struct isp4_subdev *isp_subdev) +{ + for (unsigned int i = 0; i < ISP4SD_MAX_FW_RESP_STREAM_NUM; i++) { + struct isp4sd_thread_handler *thread_ctx = + &isp_subdev->fw_resp_thread[i]; + + if (thread_ctx->thread) { + kthread_stop(thread_ctx->thread); + thread_ctx->thread = NULL; + } + } + + return 0; +} + +static int isp4sd_start_resp_proc_threads(struct isp4_subdev *isp_subdev) +{ + struct device *dev = isp_subdev->dev; + + for (unsigned int i = 0; i < ISP4SD_MAX_FW_RESP_STREAM_NUM; i++) { + struct isp4sd_thread_handler *thread_ctx = + &isp_subdev->fw_resp_thread[i]; + + isp_subdev->isp_resp_para[i].idx = i; + isp_subdev->isp_resp_para[i].isp_subdev = isp_subdev; + init_waitqueue_head(&thread_ctx->waitq); + thread_ctx->resp_ready = false; + + thread_ctx->thread = kthread_run(isp4sd_fw_resp_thread, + &isp_subdev->isp_resp_para[i], + isp4sd_thread_name[i]); + if (IS_ERR(thread_ctx->thread)) { + dev_err(dev, "create thread [%d] fail\n", i); + thread_ctx->thread = NULL; + isp4sd_stop_resp_proc_threads(isp_subdev); + return -EINVAL; + } + } + + return 0; +} + +int isp4sd_pwroff_and_deinit(struct v4l2_subdev *sd) +{ + struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + unsigned int perf_state = ISP4SD_PERFORMANCE_STATE_LOW; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + int ret; + + guard(mutex)(&isp_subdev->ops_mutex); + if (sensor_info->status == ISP4SD_START_STATUS_STARTED) { + dev_err(dev, "fail for stream still running\n"); + return -EINVAL; + } + + sensor_info->status = ISP4SD_START_STATUS_OFF; + + if (isp_subdev->irq_enabled) { + for (unsigned int i = 0; i < ISP4SD_MAX_FW_RESP_STREAM_NUM; i++) + disable_irq(isp_subdev->irq[i]); + isp_subdev->irq_enabled = false; + } + + isp4sd_stop_resp_proc_threads(isp_subdev); + dev_dbg(dev, "isp_subdev stop resp proc threads suc\n"); + + isp4if_stop(ispif); + + ret = dev_pm_genpd_set_performance_state(dev, perf_state); + if (ret) + dev_err(dev, + "fail to set isp_subdev performance state %u,ret %d\n", + perf_state, ret); + + /* hold ccpu reset */ + isp4hw_wreg(isp_subdev->mmio, ISP_SOFT_RESET, 0); + isp4hw_wreg(isp_subdev->mmio, ISP_POWER_STATUS, 0); + ret = pm_runtime_put_sync(dev); + if (ret) + dev_err(dev, "power off isp_subdev fail %d\n", ret); + else + dev_dbg(dev, "power off isp_subdev suc\n"); + + ispif->status = ISP4IF_STATUS_PWR_OFF; + isp4if_clear_cmdq(ispif); + isp4sd_module_enable(isp_subdev, false); + + /* + * When opening the camera, isp4sd_module_enable(isp_subdev, true) is + * called. Hardware requires at least a 20ms delay between disabling + * and enabling the module, so a sleep is added to ensure ISP stability + * during quick reopen scenarios. + */ + msleep(20); + + return 0; +} + +int isp4sd_pwron_and_init(struct v4l2_subdev *sd) +{ + struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + int ret; + + guard(mutex)(&isp_subdev->ops_mutex); + if (ispif->status == ISP4IF_STATUS_FW_RUNNING) { + dev_dbg(dev, "camera already opened, do nothing\n"); + return 0; + } + + isp4sd_module_enable(isp_subdev, true); + + if (ispif->status < ISP4IF_STATUS_PWR_ON) { + unsigned int perf_state = ISP4SD_PERFORMANCE_STATE_HIGH; + + ret = pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "fail to power on isp_subdev ret %d\n", + ret); + goto err_deinit; + } + + /* ISPPG ISP Power Status */ + isp4hw_wreg(isp_subdev->mmio, ISP_POWER_STATUS, 0x7FF); + ret = dev_pm_genpd_set_performance_state(dev, perf_state); + if (ret) { + dev_err(dev, + "fail to set performance state %u, ret %d\n", + perf_state, ret); + goto err_deinit; + } + + ispif->status = ISP4IF_STATUS_PWR_ON; + } + + isp_subdev->sensor_info.start_stream_cmd_sent = false; + isp_subdev->sensor_info.buf_sent_cnt = 0; + + ret = isp4if_start(ispif); + if (ret) { + dev_err(dev, "fail to start isp_subdev interface\n"); + goto err_deinit; + } + + if (isp4sd_start_resp_proc_threads(isp_subdev)) { + dev_err(dev, "isp_start_resp_proc_threads fail\n"); + goto err_deinit; + } + + dev_dbg(dev, "create resp threads ok\n"); + + for (unsigned int i = 0; i < ISP4SD_MAX_FW_RESP_STREAM_NUM; i++) + enable_irq(isp_subdev->irq[i]); + isp_subdev->irq_enabled = true; + + return 0; +err_deinit: + isp4sd_pwroff_and_deinit(sd); + return -EINVAL; +} + +static int isp4sd_stop_stream(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4sd_output_info *output_info = &sensor_info->output_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + + guard(mutex)(&isp_subdev->ops_mutex); + dev_dbg(dev, "status %i\n", output_info->start_status); + + if (output_info->start_status == ISP4SD_START_STATUS_STARTED) { + struct isp4fw_cmd_enable_out_ch cmd_ch_disable; + int ret; + + /* + * The struct will be shared with ISP FW, use memset() to + * guarantee padding bits are zeroed, since this is not + * guaranteed on all compilers. + */ + memset(&cmd_ch_disable, 0, sizeof(cmd_ch_disable)); + cmd_ch_disable.ch = ISP4FW_ISP_PIPE_OUT_CH_PREVIEW; + /* `cmd_ch_disable.is_enable` is already false */ + ret = isp4if_send_command_sync(ispif, + ISP4FW_CMD_ID_ENABLE_OUT_CHAN, + &cmd_ch_disable, + sizeof(cmd_ch_disable)); + if (ret) + dev_err(dev, "fail to disable stream\n"); + else + dev_dbg(dev, "wait disable stream suc\n"); + + ret = isp4if_send_command_sync(ispif, ISP4FW_CMD_ID_STOP_STREAM, + NULL, 0); + if (ret) + dev_err(dev, "fail to stop stream\n"); + else + dev_dbg(dev, "wait stop stream suc\n"); + } + + isp4sd_uninit_stream(isp_subdev, state, pad); + + /* + * Return success to ensure the stop process proceeds, + * and disregard any errors since they are not fatal. + */ + return 0; +} + +static int isp4sd_start_stream(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_output_info *output_info = + &isp_subdev->sensor_info.output_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + int ret; + + guard(mutex)(&isp_subdev->ops_mutex); + + if (ispif->status != ISP4IF_STATUS_FW_RUNNING) { + dev_err(dev, "fail, bad fsm %d\n", ispif->status); + return -EINVAL; + } + + switch (output_info->start_status) { + case ISP4SD_START_STATUS_OFF: + break; + case ISP4SD_START_STATUS_STARTED: + dev_dbg(dev, "stream already started, do nothing\n"); + return 0; + case ISP4SD_START_STATUS_START_FAIL: + dev_err(dev, "stream previously failed to start\n"); + return -EINVAL; + } + + ret = isp4sd_init_stream(isp_subdev); + if (ret) { + dev_err(dev, "fail to init isp_subdev stream\n"); + goto err_stop_stream; + } + + ret = isp4sd_setup_output(isp_subdev, state, pad); + if (ret) { + dev_err(dev, "fail to setup output\n"); + goto err_stop_stream; + } + + return 0; + +err_stop_stream: + isp4sd_stop_stream(isp_subdev, state, pad); + return ret; +} + +int isp4sd_ioc_send_img_buf(struct v4l2_subdev *sd, + struct isp4if_img_buf_info *buf_info) +{ + struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4if_img_buf_node *buf_node; + struct device *dev = isp_subdev->dev; + int ret; + + guard(mutex)(&isp_subdev->ops_mutex); + + if (ispif->status != ISP4IF_STATUS_FW_RUNNING) { + dev_err(dev, "fail send img buf for bad fsm %d\n", + ispif->status); + return -EINVAL; + } + + buf_node = isp4if_alloc_buffer_node(buf_info); + if (!buf_node) { + dev_err(dev, "fail alloc sys img buf info node\n"); + return -ENOMEM; + } + + ret = isp4if_queue_buffer(ispif, buf_node); + if (ret) { + dev_err(dev, "fail to queue image buf, %d\n", ret); + goto error_release_buf_node; + } + + if (!isp_subdev->sensor_info.start_stream_cmd_sent) { + isp_subdev->sensor_info.buf_sent_cnt++; + + if (isp_subdev->sensor_info.buf_sent_cnt >= + ISP4SD_MIN_BUF_CNT_BEF_START_STREAM) { + ret = isp4if_send_command(ispif, + ISP4FW_CMD_ID_START_STREAM, + NULL, 0); + if (ret) { + dev_err(dev, "fail to START_STREAM"); + goto error_release_buf_node; + } + isp_subdev->sensor_info.start_stream_cmd_sent = true; + isp_subdev->sensor_info.output_info.start_status = + ISP4SD_START_STATUS_STARTED; + isp_subdev->sensor_info.status = + ISP4SD_START_STATUS_STARTED; + } else { + dev_dbg(dev, + "no send start, required %u, buf sent %u\n", + ISP4SD_MIN_BUF_CNT_BEF_START_STREAM, + isp_subdev->sensor_info.buf_sent_cnt); + } + } + + return 0; + +error_release_buf_node: + isp4if_dealloc_buffer_node(buf_node); + return ret; +} + +static const struct v4l2_subdev_video_ops isp4sd_video_ops = { + .s_stream = v4l2_subdev_s_stream_helper, +}; + +static int isp4sd_set_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct isp4sd_output_info *stream_info = + &(to_isp4_subdev(sd)->sensor_info.output_info); + struct v4l2_mbus_framefmt *fmt; + + fmt = v4l2_subdev_state_get_format(sd_state, format->pad); + + if (!fmt) { + dev_err(sd->dev, "fail to get state format\n"); + return -EINVAL; + } + + *fmt = format->format; + switch (fmt->code) { + case MEDIA_BUS_FMT_YUYV8_1X16: + stream_info->image_size = fmt->width * fmt->height * 2; + break; + case MEDIA_BUS_FMT_YUYV8_1_5X8: + default: + stream_info->image_size = fmt->width * fmt->height * 3 / 2; + break; + } + + if (!stream_info->image_size) { + dev_err(sd->dev, + "fail set pad format,code 0x%x,width %u, height %u\n", + fmt->code, fmt->width, fmt->height); + return -EINVAL; + } + + dev_dbg(sd->dev, "set pad format suc, code:%x w:%u h:%u size:%u\n", + fmt->code, fmt->width, fmt->height, + stream_info->image_size); + + return 0; +} + +static int isp4sd_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); + + return isp4sd_start_stream(isp_subdev, state, pad); +} + +static int isp4sd_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); + + return isp4sd_stop_stream(isp_subdev, state, pad); +} + +static const struct v4l2_subdev_pad_ops isp4sd_pad_ops = { + .get_fmt = v4l2_subdev_get_fmt, + .set_fmt = isp4sd_set_pad_format, + .enable_streams = isp4sd_enable_streams, + .disable_streams = isp4sd_disable_streams, +}; + +static const struct v4l2_subdev_ops isp4sd_subdev_ops = { + .video = &isp4sd_video_ops, + .pad = &isp4sd_pad_ops, +}; + +int isp4sd_init(struct isp4_subdev *isp_subdev, struct v4l2_device *v4l2_dev, + int irq[ISP4SD_MAX_FW_RESP_STREAM_NUM]) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = v4l2_dev->dev; + int ret; + + isp_subdev->dev = dev; + v4l2_subdev_init(&isp_subdev->sdev, &isp4sd_subdev_ops); + isp_subdev->sdev.owner = THIS_MODULE; + isp_subdev->sdev.dev = dev; + snprintf(isp_subdev->sdev.name, sizeof(isp_subdev->sdev.name), "%s", + dev_name(dev)); + + isp_subdev->sdev.entity.name = isp4sd_entity_name; + isp_subdev->sdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_ISP; + isp_subdev->sdev_pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&isp_subdev->sdev.entity, 1, + &isp_subdev->sdev_pad); + if (ret) { + dev_err(dev, "fail to init isp4 subdev entity pad %d\n", ret); + return ret; + } + + ret = v4l2_subdev_init_finalize(&isp_subdev->sdev); + if (ret < 0) { + dev_err(dev, "fail to init finalize isp4 subdev %d\n", + ret); + return ret; + } + + ret = v4l2_device_register_subdev(v4l2_dev, &isp_subdev->sdev); + if (ret) { + dev_err(dev, "fail to register isp4 subdev to V4L2 device %d\n", + ret); + goto err_media_clean_up; + } + + isp4if_init(ispif, dev, isp_subdev->mmio); + + mutex_init(&isp_subdev->ops_mutex); + sensor_info->status = ISP4SD_START_STATUS_OFF; + + /* create ISP enable gpio control */ + isp_subdev->enable_gpio = devm_gpiod_get(isp_subdev->dev, + "enable_isp", + GPIOD_OUT_LOW); + if (IS_ERR(isp_subdev->enable_gpio)) { + ret = PTR_ERR(isp_subdev->enable_gpio); + dev_err(dev, "fail to get gpiod %d\n", ret); + goto err_subdev_unreg; + } + + for (unsigned int i = 0; i < ISP4SD_MAX_FW_RESP_STREAM_NUM; i++) + isp_subdev->irq[i] = irq[i]; + + isp_subdev->host2fw_seq_num = 1; + ispif->status = ISP4IF_STATUS_PWR_OFF; + + ret = isp4vid_dev_init(&isp_subdev->isp_vdev, &isp_subdev->sdev); + if (ret) + goto err_subdev_unreg; + + return 0; + +err_subdev_unreg: + v4l2_device_unregister_subdev(&isp_subdev->sdev); +err_media_clean_up: + v4l2_subdev_cleanup(&isp_subdev->sdev); + media_entity_cleanup(&isp_subdev->sdev.entity); + return ret; +} + +void isp4sd_deinit(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + + isp4vid_dev_deinit(&isp_subdev->isp_vdev); + v4l2_device_unregister_subdev(&isp_subdev->sdev); + media_entity_cleanup(&isp_subdev->sdev.entity); + isp4if_deinit(ispif); + isp4sd_module_enable(isp_subdev, false); + + ispif->status = ISP4IF_STATUS_PWR_OFF; +} --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_subdev.h +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_subdev.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_SUBDEV_H_ +#define _ISP4_SUBDEV_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include "isp4_fw_cmd_resp.h" +#include "isp4_hw_reg.h" +#include "isp4_interface.h" +#include "isp4_video.h" + +/* + * One is for none sensor specific response which is not used now. + * Another is for sensor specific response + */ +#define ISP4SD_MAX_FW_RESP_STREAM_NUM 2 + +/* Indicates the ISP status */ +enum isp4sd_status { + ISP4SD_STATUS_PWR_OFF, + ISP4SD_STATUS_PWR_ON, + ISP4SD_STATUS_FW_RUNNING, + ISP4SD_STATUS_MAX +}; + +/* Indicates sensor and output stream status */ +enum isp4sd_start_status { + ISP4SD_START_STATUS_OFF, + ISP4SD_START_STATUS_STARTED, + ISP4SD_START_STATUS_START_FAIL, +}; + +struct isp4sd_img_buf_node { + struct list_head node; + struct isp4if_img_buf_info buf_info; +}; + +/* This is ISP output after processing Bayer raw sensor input */ +struct isp4sd_output_info { + enum isp4sd_start_status start_status; + u32 image_size; +}; + +/* + * Struct for sensor info used as ISP input or source. + * status: sensor status. + * output_info: ISP output after processing the sensor input. + * start_stream_cmd_sent: indicates if ISP4FW_CMD_ID_START_STREAM was sent + * to firmware. + * buf_sent_cnt: number of buffers sent to receive images. + */ +struct isp4sd_sensor_info { + struct isp4sd_output_info output_info; + enum isp4sd_start_status status; + bool start_stream_cmd_sent; + u32 buf_sent_cnt; +}; + +/* + * The thread is created by the driver to handle firmware responses which will + * be waken up when a firmware-to-driver response interrupt occurs. + */ +struct isp4sd_thread_handler { + struct task_struct *thread; + wait_queue_head_t waitq; + bool resp_ready; +}; + +struct isp4_subdev_thread_param { + u32 idx; + struct isp4_subdev *isp_subdev; +}; + +struct isp4_subdev { + struct v4l2_subdev sdev; + struct isp4_interface ispif; + struct isp4vid_dev isp_vdev; + + struct media_pad sdev_pad; + + enum isp4sd_status isp_status; + /* mutex used to synchronize the operation with firmware */ + struct mutex ops_mutex; + + struct isp4sd_thread_handler + fw_resp_thread[ISP4SD_MAX_FW_RESP_STREAM_NUM]; + + u32 host2fw_seq_num; + + struct isp4sd_sensor_info sensor_info; + + /* gpio descriptor */ + struct gpio_desc *enable_gpio; + struct device *dev; + void __iomem *mmio; + struct isp4_subdev_thread_param + isp_resp_para[ISP4SD_MAX_FW_RESP_STREAM_NUM]; + int irq[ISP4SD_MAX_FW_RESP_STREAM_NUM]; + bool irq_enabled; + /* spin lock to access ISP_SYS_INT0_EN exclusively */ + spinlock_t irq_lock; +#ifdef CONFIG_DEBUG_FS + bool enable_fw_log; + struct dentry *debugfs_dir; + char *fw_log_output; +#endif +}; + +int isp4sd_init(struct isp4_subdev *isp_subdev, struct v4l2_device *v4l2_dev, + int irq[ISP4SD_MAX_FW_RESP_STREAM_NUM]); +void isp4sd_deinit(struct isp4_subdev *isp_subdev); +int isp4sd_ioc_send_img_buf(struct v4l2_subdev *sd, + struct isp4if_img_buf_info *buf_info); +int isp4sd_pwron_and_init(struct v4l2_subdev *sd); +int isp4sd_pwroff_and_deinit(struct v4l2_subdev *sd); + +#endif /* _ISP4_SUBDEV_H_ */ --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_video.c +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_video.c @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include + +#include "isp4_interface.h" +#include "isp4_subdev.h" +#include "isp4_video.h" + +#define ISP4VID_ISP_DRV_NAME "amd_isp_capture" +#define ISP4VID_MAX_PREVIEW_FPS 30 +#define ISP4VID_DEFAULT_FMT isp4vid_formats[0] + +#define ISP4VID_PAD_VIDEO_OUTPUT 0 + +/* time perframe default */ +#define ISP4VID_ISP_TPF_DEFAULT isp4vid_tpfs[0] + +static const char *const isp4vid_video_dev_name = "Preview"; + +/* Sizes must be in increasing order */ +static const struct v4l2_frmsize_discrete isp4vid_frmsize[] = { + {640, 360}, + {640, 480}, + {1280, 720}, + {1280, 960}, + {1920, 1080}, + {1920, 1440}, + {2560, 1440}, + {2880, 1620}, + {2880, 1624}, + {2888, 1808}, +}; + +static const u32 isp4vid_formats[] = { + V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_YUYV +}; + +/* time perframe list */ +static const struct v4l2_fract isp4vid_tpfs[] = { + { 1, ISP4VID_MAX_PREVIEW_FPS } +}; + +void isp4vid_handle_frame_done(struct isp4vid_dev *isp_vdev, + const struct isp4if_img_buf_info *img_buf) +{ + struct isp4vid_capture_buffer *isp4vid_buf; + void *vbuf; + + scoped_guard(mutex, &isp_vdev->buf_list_lock) { + isp4vid_buf = list_first_entry_or_null(&isp_vdev->buf_list, + typeof(*isp4vid_buf), + list); + if (!isp4vid_buf) + return; + + vbuf = vb2_plane_vaddr(&isp4vid_buf->vb2.vb2_buf, 0); + + if (vbuf != img_buf->planes[0].sys_addr) { + dev_err(isp_vdev->dev, "Invalid vbuf\n"); + return; + } + + list_del(&isp4vid_buf->list); + } + + /* Fill the buffer */ + isp4vid_buf->vb2.vb2_buf.timestamp = ktime_get_ns(); + isp4vid_buf->vb2.sequence = isp_vdev->sequence++; + isp4vid_buf->vb2.field = V4L2_FIELD_ANY; + + vb2_set_plane_payload(&isp4vid_buf->vb2.vb2_buf, + 0, isp_vdev->format.sizeimage); + + vb2_buffer_done(&isp4vid_buf->vb2.vb2_buf, VB2_BUF_STATE_DONE); + + dev_dbg(isp_vdev->dev, "call vb2_buffer_done(size=%u)\n", + isp_vdev->format.sizeimage); +} + +static const struct v4l2_pix_format isp4vid_fmt_default = { + .width = 1920, + .height = 1080, + .pixelformat = ISP4VID_DEFAULT_FMT, + .field = V4L2_FIELD_NONE, + .colorspace = V4L2_COLORSPACE_SRGB, +}; + +static void isp4vid_capture_return_all_buffers(struct isp4vid_dev *isp_vdev, + enum vb2_buffer_state state) +{ + struct isp4vid_capture_buffer *vbuf, *node; + + scoped_guard(mutex, &isp_vdev->buf_list_lock) { + list_for_each_entry_safe(vbuf, node, &isp_vdev->buf_list, list) + vb2_buffer_done(&vbuf->vb2.vb2_buf, state); + INIT_LIST_HEAD(&isp_vdev->buf_list); + } + + dev_dbg(isp_vdev->dev, "call vb2_buffer_done(%d)\n", state); +} + +static int isp4vid_vdev_link_validate(struct media_link *link) +{ + return 0; +} + +static const struct media_entity_operations isp4vid_vdev_ent_ops = { + .link_validate = isp4vid_vdev_link_validate, +}; + +static const struct v4l2_file_operations isp4vid_vdev_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, +}; + +static int isp4vid_ioctl_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + strscpy(cap->driver, ISP4VID_ISP_DRV_NAME, sizeof(cap->driver)); + snprintf(cap->card, sizeof(cap->card), "%s", ISP4VID_ISP_DRV_NAME); + cap->capabilities |= V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE; + + dev_dbg(isp_vdev->dev, "%s|capabilities=0x%X\n", isp_vdev->vdev.name, + cap->capabilities); + + return 0; +} + +static int isp4vid_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + f->fmt.pix = isp_vdev->format; + + return 0; +} + +static int isp4vid_fill_buffer_size(struct v4l2_pix_format *fmt) +{ + int ret = 0; + + switch (fmt->pixelformat) { + case V4L2_PIX_FMT_NV12: + fmt->bytesperline = fmt->width; + fmt->sizeimage = fmt->bytesperline * fmt->height * 3 / 2; + break; + case V4L2_PIX_FMT_YUYV: + fmt->bytesperline = fmt->width * 2; + fmt->sizeimage = fmt->bytesperline * fmt->height; + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int isp4vid_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + struct v4l2_pix_format *format = &f->fmt.pix; + const struct v4l2_frmsize_discrete *fsz; + size_t i; + + /* + * Check if the hardware supports the requested format, use the default + * format otherwise. + */ + for (i = 0; i < ARRAY_SIZE(isp4vid_formats); i++) + if (isp4vid_formats[i] == format->pixelformat) + break; + + if (i == ARRAY_SIZE(isp4vid_formats)) + format->pixelformat = ISP4VID_DEFAULT_FMT; + + switch (format->pixelformat) { + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_YUYV: + fsz = v4l2_find_nearest_size(isp4vid_frmsize, + ARRAY_SIZE(isp4vid_frmsize), + width, height, format->width, + format->height); + format->width = fsz->width; + format->height = fsz->height; + break; + default: + dev_err(isp_vdev->dev, "%s|unsupported fmt=%u\n", + isp_vdev->vdev.name, + format->pixelformat); + return -EINVAL; + } + + /* + * There is no need to check the return value, as failure will never + * happen here + */ + isp4vid_fill_buffer_size(format); + + if (format->field == V4L2_FIELD_ANY) + format->field = isp4vid_fmt_default.field; + + if (format->colorspace == V4L2_COLORSPACE_DEFAULT) + format->colorspace = isp4vid_fmt_default.colorspace; + + return 0; +} + +static int isp4vid_set_fmt_2_isp(struct v4l2_subdev *sdev, + struct v4l2_pix_format *pix_fmt) +{ + struct v4l2_subdev_format fmt = {}; + + switch (pix_fmt->pixelformat) { + case V4L2_PIX_FMT_NV12: + fmt.format.code = MEDIA_BUS_FMT_YUYV8_1_5X8; + break; + case V4L2_PIX_FMT_YUYV: + fmt.format.code = MEDIA_BUS_FMT_YUYV8_1X16; + break; + default: + return -EINVAL; + } + fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + fmt.pad = ISP4VID_PAD_VIDEO_OUTPUT; + fmt.format.width = pix_fmt->width; + fmt.format.height = pix_fmt->height; + return v4l2_subdev_call(sdev, pad, set_fmt, NULL, &fmt); +} + +static int isp4vid_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + int ret; + + /* Do not change the format while stream is on */ + if (vb2_is_busy(&isp_vdev->vbq)) + return -EBUSY; + + ret = isp4vid_try_fmt_vid_cap(file, priv, f); + if (ret) + return ret; + + dev_dbg(isp_vdev->dev, "%s|width height:%ux%u->%ux%u\n", + isp_vdev->vdev.name, + isp_vdev->format.width, isp_vdev->format.height, + f->fmt.pix.width, f->fmt.pix.height); + dev_dbg(isp_vdev->dev, "%s|pixelformat:0x%x-0x%x\n", + isp_vdev->vdev.name, isp_vdev->format.pixelformat, + f->fmt.pix.pixelformat); + dev_dbg(isp_vdev->dev, "%s|bytesperline:%u->%u\n", + isp_vdev->vdev.name, isp_vdev->format.bytesperline, + f->fmt.pix.bytesperline); + dev_dbg(isp_vdev->dev, "%s|sizeimage:%u->%u\n", + isp_vdev->vdev.name, isp_vdev->format.sizeimage, + f->fmt.pix.sizeimage); + + isp_vdev->format = f->fmt.pix; + ret = isp4vid_set_fmt_2_isp(isp_vdev->isp_sdev, &isp_vdev->format); + + return ret; +} + +static int isp4vid_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + switch (f->index) { + case 0: + f->pixelformat = V4L2_PIX_FMT_NV12; + break; + case 1: + f->pixelformat = V4L2_PIX_FMT_YUYV; + break; + default: + return -EINVAL; + } + + dev_dbg(isp_vdev->dev, "%s|index=%d, pixelformat=0x%X\n", + isp_vdev->vdev.name, f->index, f->pixelformat); + + return 0; +} + +static int isp4vid_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(isp4vid_formats); i++) { + if (isp4vid_formats[i] == fsize->pixel_format) + break; + } + + if (i == ARRAY_SIZE(isp4vid_formats)) + return -EINVAL; + + if (fsize->index < ARRAY_SIZE(isp4vid_frmsize)) { + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; + fsize->discrete = isp4vid_frmsize[fsize->index]; + dev_dbg(isp_vdev->dev, "%s|size[%d]=%dx%d\n", + isp_vdev->vdev.name, fsize->index, + fsize->discrete.width, fsize->discrete.height); + } else { + return -EINVAL; + } + + return 0; +} + +static int isp4vid_ioctl_enum_frameintervals(struct file *file, void *priv, + struct v4l2_frmivalenum *fival) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + size_t i; + + if (fival->index >= ARRAY_SIZE(isp4vid_tpfs)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(isp4vid_formats); i++) + if (isp4vid_formats[i] == fival->pixel_format) + break; + + if (i == ARRAY_SIZE(isp4vid_formats)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(isp4vid_frmsize); i++) + if (isp4vid_frmsize[i].width == fival->width && + isp4vid_frmsize[i].height == fival->height) + break; + + if (i == ARRAY_SIZE(isp4vid_frmsize)) + return -EINVAL; + + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; + fival->discrete = isp4vid_tpfs[fival->index]; + v4l2_simplify_fraction(&fival->discrete.numerator, + &fival->discrete.denominator, 8, 333); + + dev_dbg(isp_vdev->dev, "%s|interval[%d]=%d/%d\n", + isp_vdev->vdev.name, fival->index, + fival->discrete.numerator, + fival->discrete.denominator); + + return 0; +} + +static int isp4vid_ioctl_g_param(struct file *file, void *priv, + struct v4l2_streamparm *param) +{ + struct v4l2_captureparm *capture = ¶m->parm.capture; + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + capture->capability = V4L2_CAP_TIMEPERFRAME; + capture->timeperframe = isp_vdev->timeperframe; + capture->readbuffers = 0; + + dev_dbg(isp_vdev->dev, "%s|timeperframe=%d/%d\n", isp_vdev->vdev.name, + capture->timeperframe.numerator, + capture->timeperframe.denominator); + + return 0; +} + +static const struct v4l2_ioctl_ops isp4vid_vdev_ioctl_ops = { + .vidioc_querycap = isp4vid_ioctl_querycap, + .vidioc_enum_fmt_vid_cap = isp4vid_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = isp4vid_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = isp4vid_s_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = isp4vid_try_fmt_vid_cap, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + .vidioc_g_parm = isp4vid_ioctl_g_param, + .vidioc_s_parm = isp4vid_ioctl_g_param, + .vidioc_enum_framesizes = isp4vid_enum_framesizes, + .vidioc_enum_frameintervals = isp4vid_ioctl_enum_frameintervals, +}; + +static unsigned int isp4vid_get_image_size(struct v4l2_pix_format *fmt) +{ + switch (fmt->pixelformat) { + case V4L2_PIX_FMT_NV12: + return fmt->width * fmt->height * 3 / 2; + case V4L2_PIX_FMT_YUYV: + return fmt->width * fmt->height * 2; + default: + return 0; + } +} + +static int isp4vid_qops_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vq); + unsigned int q_num_bufs = vb2_get_num_buffers(vq); + + if (*nplanes > 1) { + dev_err(isp_vdev->dev, + "fail to setup queue, no mplane supported %u\n", + *nplanes); + return -EINVAL; + } + + if (*nplanes == 1) { + unsigned int size; + + size = isp4vid_get_image_size(&isp_vdev->format); + if (sizes[0] < size) { + dev_err(isp_vdev->dev, + "fail for small plane size %u, %u expected\n", + sizes[0], size); + return -EINVAL; + } + } + + if (q_num_bufs + *nbuffers < ISP4IF_MAX_STREAM_BUF_COUNT) + *nbuffers = ISP4IF_MAX_STREAM_BUF_COUNT - q_num_bufs; + + switch (isp_vdev->format.pixelformat) { + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_YUYV: { + *nplanes = 1; + sizes[0] = max(sizes[0], isp_vdev->format.sizeimage); + isp_vdev->format.sizeimage = sizes[0]; + } + break; + default: + dev_err(isp_vdev->dev, "%s|unsupported fmt=%u\n", + isp_vdev->vdev.name, isp_vdev->format.pixelformat); + return -EINVAL; + } + + dev_dbg(isp_vdev->dev, "%s|*nbuffers=%u *nplanes=%u sizes[0]=%u\n", + isp_vdev->vdev.name, + *nbuffers, *nplanes, sizes[0]); + + return 0; +} + +static void isp4vid_qops_buffer_queue(struct vb2_buffer *vb) +{ + struct isp4vid_capture_buffer *buf = + container_of(vb, struct isp4vid_capture_buffer, vb2.vb2_buf); + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vb->vb2_queue); + struct isp4if_img_buf_info *img_buf = &buf->img_buf; + void *vaddr = vb2_plane_vaddr(vb, 0); + + dev_dbg(isp_vdev->dev, "queue buf, vaddr %p, gpuva 0x%llx, size %u\n", + vaddr, buf->gpu_addr, vb->planes[0].length); + + switch (isp_vdev->format.pixelformat) { + case V4L2_PIX_FMT_NV12: { + u32 y_size = isp_vdev->format.sizeimage / 3 * 2; + u32 uv_size = isp_vdev->format.sizeimage / 3; + + img_buf->planes[0].len = y_size; + img_buf->planes[0].sys_addr = vaddr; + img_buf->planes[0].mc_addr = buf->gpu_addr; + + dev_dbg(isp_vdev->dev, "img_buf[0]: mc=0x%llx size=%u\n", + img_buf->planes[0].mc_addr, + img_buf->planes[0].len); + + img_buf->planes[1].len = uv_size; + img_buf->planes[1].sys_addr = vaddr + y_size; + img_buf->planes[1].mc_addr = buf->gpu_addr + y_size; + + dev_dbg(isp_vdev->dev, "img_buf[1]: mc=0x%llx size=%u\n", + img_buf->planes[1].mc_addr, + img_buf->planes[1].len); + + img_buf->planes[2].len = 0; + } + break; + case V4L2_PIX_FMT_YUYV: { + img_buf->planes[0].len = isp_vdev->format.sizeimage; + img_buf->planes[0].sys_addr = vaddr; + img_buf->planes[0].mc_addr = buf->gpu_addr; + + dev_dbg(isp_vdev->dev, "img_buf[0]: mc=0x%llx size=%u\n", + img_buf->planes[0].mc_addr, + img_buf->planes[0].len); + + img_buf->planes[1].len = 0; + img_buf->planes[2].len = 0; + } + break; + default: + dev_err(isp_vdev->dev, "%s|unsupported fmt=%u\n", + isp_vdev->vdev.name, isp_vdev->format.pixelformat); + return; + } + + if (isp_vdev->stream_started) + isp4sd_ioc_send_img_buf(isp_vdev->isp_sdev, img_buf); + + scoped_guard(mutex, &isp_vdev->buf_list_lock) + list_add_tail(&buf->list, &isp_vdev->buf_list); +} + +static int isp4vid_qops_start_streaming(struct vb2_queue *vq, + unsigned int count) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vq); + struct isp4vid_capture_buffer *isp4vid_buf; + struct media_entity *entity; + struct v4l2_subdev *subdev; + struct media_pad *pad; + int ret = 0; + + isp_vdev->sequence = 0; + + ret = isp4sd_pwron_and_init(isp_vdev->isp_sdev); + if (ret) { + dev_err(isp_vdev->dev, "power up isp fail %d\n", ret); + goto release_buffers; + } + + entity = &isp_vdev->vdev.entity; + while (1) { + pad = &entity->pads[0]; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) + break; + + pad = media_pad_remote_pad_first(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + + entity = pad->entity; + subdev = media_entity_to_v4l2_subdev(entity); + + ret = v4l2_subdev_call(subdev, video, s_stream, 1); + if (ret < 0 && ret != -ENOIOCTLCMD) { + dev_dbg(isp_vdev->dev, "fail start streaming: %s %d\n", + subdev->name, ret); + goto release_buffers; + } + } + + list_for_each_entry(isp4vid_buf, &isp_vdev->buf_list, list) + isp4sd_ioc_send_img_buf(isp_vdev->isp_sdev, + &isp4vid_buf->img_buf); + + isp_vdev->stream_started = true; + + return 0; + +release_buffers: + isp4vid_capture_return_all_buffers(isp_vdev, VB2_BUF_STATE_QUEUED); + return ret; +} + +static void isp4vid_qops_stop_streaming(struct vb2_queue *vq) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vq); + struct media_entity *entity; + struct v4l2_subdev *subdev; + struct media_pad *pad; + int ret; + + entity = &isp_vdev->vdev.entity; + while (1) { + pad = &entity->pads[0]; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) + break; + + pad = media_pad_remote_pad_first(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + + entity = pad->entity; + subdev = media_entity_to_v4l2_subdev(entity); + + ret = v4l2_subdev_call(subdev, video, s_stream, 0); + + if (ret < 0 && ret != -ENOIOCTLCMD) + dev_dbg(isp_vdev->dev, "fail stop streaming: %s %d\n", + subdev->name, ret); + } + + isp_vdev->stream_started = false; + isp4sd_pwroff_and_deinit(isp_vdev->isp_sdev); + + /* Release all active buffers */ + isp4vid_capture_return_all_buffers(isp_vdev, VB2_BUF_STATE_ERROR); +} + +static int isp4vid_qops_buf_init(struct vb2_buffer *vb) +{ + struct isp4vid_capture_buffer *buf = + container_of(vb, struct isp4vid_capture_buffer, vb2.vb2_buf); + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vb->vb2_queue); + void *mem_priv = vb->planes[0].mem_priv; + struct device *dev = isp_vdev->dev; + u64 gpu_addr; + void *bo; + int ret; + + if (vb->planes[0].dbuf) { + buf->dbuf = vb->planes[0].dbuf; + } else { + /* + * HAS_DMA is a Kconfig dependency so CONFIG_HAS_DMA is always + * defined when this driver is compiled. The #else branch is + * kept as a safeguard in case the dependency is ever removed. + */ +#ifdef CONFIG_HAS_DMA + buf->dbuf = vb2_vmalloc_memops.get_dmabuf(vb, mem_priv, 0); + if (IS_ERR_OR_NULL(buf->dbuf)) { + dev_err(dev, "fail to get dma buf\n"); + return -EINVAL; + } +#else + dev_err(dev, "get dmabuf fail -- CONFIG_HAS_DMA not defined\n"); + buf->dbuf = NULL; + return -EINVAL; +#endif + } + + /* create isp user BO and obtain gpu_addr */ + ret = isp_user_buffer_alloc(dev, buf->dbuf, &bo, &gpu_addr); + if (ret) { + dev_err(dev, "fail to create isp user BO\n"); + if (!vb->planes[0].dbuf) { + dma_buf_put(buf->dbuf); + buf->dbuf = NULL; + } + + return ret; + } + + buf->bo = bo; + buf->gpu_addr = gpu_addr; + return 0; +} + +static void isp4vid_qops_buf_cleanup(struct vb2_buffer *vb) +{ + struct isp4vid_capture_buffer *buf = + container_of(vb, struct isp4vid_capture_buffer, vb2.vb2_buf); + + if (buf->bo) { + isp_user_buffer_free(buf->bo); + buf->bo = NULL; + } + + /* + * Only put dmabufs we obtained ourselves via get_dmabuf, not ones + * provided by the framework for DMABUF import + */ + if (buf->dbuf && buf->dbuf != vb->planes[0].dbuf) + dma_buf_put(buf->dbuf); + + buf->dbuf = NULL; +} + +static const struct vb2_ops isp4vid_qops = { + .queue_setup = isp4vid_qops_queue_setup, + .buf_init = isp4vid_qops_buf_init, + .buf_cleanup = isp4vid_qops_buf_cleanup, + .start_streaming = isp4vid_qops_start_streaming, + .stop_streaming = isp4vid_qops_stop_streaming, + .buf_queue = isp4vid_qops_buffer_queue, +}; + +int isp4vid_dev_init(struct isp4vid_dev *isp_vdev, struct v4l2_subdev *isp_sd) +{ + const char *vdev_name = isp4vid_video_dev_name; + struct v4l2_device *v4l2_dev; + struct video_device *vdev; + struct vb2_queue *q; + int ret; + + if (!isp_vdev || !isp_sd || !isp_sd->v4l2_dev) + return -EINVAL; + + v4l2_dev = isp_sd->v4l2_dev; + vdev = &isp_vdev->vdev; + + isp_vdev->isp_sdev = isp_sd; + isp_vdev->dev = v4l2_dev->dev; + + /* Initialize the vb2_queue struct */ + mutex_init(&isp_vdev->vbq_lock); + q = &isp_vdev->vbq; + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_DMABUF; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->buf_struct_size = sizeof(struct isp4vid_capture_buffer); + q->min_queued_buffers = 2; + q->ops = &isp4vid_qops; + q->drv_priv = isp_vdev; + q->mem_ops = &vb2_vmalloc_memops; + q->lock = &isp_vdev->vbq_lock; + q->dev = v4l2_dev->dev; + ret = vb2_queue_init(q); + if (ret) { + dev_err(v4l2_dev->dev, "vb2_queue_init error:%d\n", ret); + return ret; + } + + /* Initialize buffer list and its lock */ + mutex_init(&isp_vdev->buf_list_lock); + INIT_LIST_HEAD(&isp_vdev->buf_list); + + /* Set default frame format */ + isp_vdev->format = isp4vid_fmt_default; + isp_vdev->timeperframe = ISP4VID_ISP_TPF_DEFAULT; + v4l2_simplify_fraction(&isp_vdev->timeperframe.numerator, + &isp_vdev->timeperframe.denominator, 8, 333); + + ret = isp4vid_fill_buffer_size(&isp_vdev->format); + if (ret) { + dev_err(v4l2_dev->dev, "fail to fill buffer size: %d\n", ret); + goto err_release_vb2_queue; + } + + ret = isp4vid_set_fmt_2_isp(isp_sd, &isp_vdev->format); + if (ret) { + dev_err(v4l2_dev->dev, "fail init format :%d\n", ret); + goto err_release_vb2_queue; + } + + /* Initialize the video_device struct */ + isp_vdev->vdev.entity.name = vdev_name; + isp_vdev->vdev.entity.function = MEDIA_ENT_F_IO_V4L; + isp_vdev->vdev_pad.flags = MEDIA_PAD_FL_SINK; + ret = media_entity_pads_init(&isp_vdev->vdev.entity, 1, + &isp_vdev->vdev_pad); + + if (ret) { + dev_err(v4l2_dev->dev, "init media entity pad fail:%d\n", ret); + goto err_release_vb2_queue; + } + + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; + vdev->entity.ops = &isp4vid_vdev_ent_ops; + vdev->release = video_device_release_empty; + vdev->fops = &isp4vid_vdev_fops; + vdev->ioctl_ops = &isp4vid_vdev_ioctl_ops; + vdev->lock = NULL; + vdev->queue = q; + vdev->v4l2_dev = v4l2_dev; + vdev->vfl_dir = VFL_DIR_RX; + strscpy(vdev->name, vdev_name, sizeof(vdev->name)); + video_set_drvdata(vdev, isp_vdev); + + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) { + dev_err(v4l2_dev->dev, "register video device fail:%d\n", ret); + goto err_entity_cleanup; + } + + return 0; + +err_entity_cleanup: + media_entity_cleanup(&isp_vdev->vdev.entity); +err_release_vb2_queue: + vb2_queue_release(q); + return ret; +} + +void isp4vid_dev_deinit(struct isp4vid_dev *isp_vdev) +{ + vb2_video_unregister_device(&isp_vdev->vdev); +} --- linux-nvidia-7.0.0.orig/drivers/media/platform/amd/isp4/isp4_video.h +++ linux-nvidia-7.0.0/drivers/media/platform/amd/isp4/isp4_video.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_VIDEO_H_ +#define _ISP4_VIDEO_H_ + +#include +#include + +#include "isp4_interface.h" + +struct isp4vid_capture_buffer { + /* + * struct vb2_v4l2_buffer must be the first element + * the videobuf2 framework will allocate this struct based on + * buf_struct_size and use the first sizeof(struct vb2_buffer) bytes of + * memory as a vb2_buffer + */ + struct vb2_v4l2_buffer vb2; + struct isp4if_img_buf_info img_buf; + struct list_head list; + struct dma_buf *dbuf; + void *bo; + u64 gpu_addr; +}; + +struct isp4vid_dev { + struct video_device vdev; + struct media_pad vdev_pad; + struct v4l2_pix_format format; + + /* mutex that protects vbq */ + struct mutex vbq_lock; + struct vb2_queue vbq; + + /* mutex that protects buf_list */ + struct mutex buf_list_lock; + struct list_head buf_list; + + u32 sequence; + bool stream_started; + + struct device *dev; + struct v4l2_subdev *isp_sdev; + struct v4l2_fract timeperframe; +}; + +int isp4vid_dev_init(struct isp4vid_dev *isp_vdev, struct v4l2_subdev *isp_sd); + +void isp4vid_dev_deinit(struct isp4vid_dev *isp_vdev); + +void isp4vid_handle_frame_done(struct isp4vid_dev *isp_vdev, + const struct isp4if_img_buf_info *img_buf); + +#endif /* _ISP4_VIDEO_H_ */ --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/camss/Kconfig +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/camss/Kconfig @@ -7,3 +7,4 @@ select VIDEO_V4L2_SUBDEV_API select VIDEOBUF2_DMA_SG select V4L2_FWNODE + select PHY_QCOM_MIPI_CSI2 --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/camss/camss-csiphy.c +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -7,12 +7,14 @@ * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. * Copyright (C) 2016-2018 Linaro Ltd. */ +#include #include #include #include #include #include #include +#include #include #include #include @@ -131,10 +133,10 @@ } /* - * csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module + * csiphy_set_clock_rates_legacy - Calculate and set clock rates on CSIPHY module * @csiphy: CSIPHY device */ -static int csiphy_set_clock_rates(struct csiphy_device *csiphy) +static int csiphy_set_clock_rates_legacy(struct csiphy_device *csiphy) { struct device *dev = csiphy->camss->dev; s64 link_freq; @@ -200,7 +202,7 @@ * * Return 0 on success or a negative error code otherwise */ -static int csiphy_set_power(struct v4l2_subdev *sd, int on) +static int csiphy_set_power_legacy(struct v4l2_subdev *sd, int on) { struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); struct device *dev = csiphy->camss->dev; @@ -219,7 +221,7 @@ return ret; } - ret = csiphy_set_clock_rates(csiphy); + ret = csiphy_set_clock_rates_legacy(csiphy); if (ret < 0) { regulator_bulk_disable(csiphy->num_supplies, csiphy->supplies); @@ -254,7 +256,7 @@ } /* - * csiphy_stream_on - Enable streaming on CSIPHY module + * csiphy_stream_on_legacy - Enable streaming on CSIPHY module * @csiphy: CSIPHY device * * Helper function to enable streaming on CSIPHY module. @@ -262,7 +264,7 @@ * * Return 0 on success or a negative error code otherwise */ -static int csiphy_stream_on(struct csiphy_device *csiphy) +static int csiphy_stream_on_legacy(struct csiphy_device *csiphy) { struct csiphy_config *cfg = &csiphy->cfg; s64 link_freq; @@ -306,11 +308,86 @@ * * Helper function to disable streaming on CSIPHY module */ -static void csiphy_stream_off(struct csiphy_device *csiphy) +static void csiphy_stream_off_legacy(struct csiphy_device *csiphy) { csiphy->res->hw_ops->lanes_disable(csiphy, &csiphy->cfg); } +/* + * csiphy_stream_on - Enable streaming on CSIPHY module + * @csiphy: CSIPHY device + * + * Helper function to enable streaming on CSIPHY module. + * Main configuration of CSIPHY module is also done here. + * + * Return 0 on success or a negative error code otherwise + */ +static int csiphy_stream_on(struct csiphy_device *csiphy) +{ + u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats, + csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); + u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; + struct phy_configure_opts_mipi_dphy *dphy_cfg; + union phy_configure_opts dphy_opts = { 0 }; + struct device *dev = csiphy->camss->dev; + s64 link_freq; + int ret; + + dphy_cfg = &dphy_opts.mipi_dphy; + + link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + + if (link_freq < 0) { + dev_err(dev, + "Cannot get CSI2 transmitter's link frequency\n"); + return -EINVAL; + } + + phy_mipi_dphy_get_default_config_for_hsclk(link_freq, num_lanes, dphy_cfg); + + phy_set_mode(csiphy->phy, PHY_MODE_MIPI_DPHY); + ret = phy_configure(csiphy->phy, &dphy_opts); + if (ret) { + dev_err(dev, "failed to configure MIPI D-PHY\n"); + goto error; + } + + return phy_power_on(csiphy->phy); + +error: + return ret; +} + +/* + * csiphy_stream_off - Disable streaming on CSIPHY module + * @csiphy: CSIPHY device + * + * Helper function to disable streaming on CSIPHY module + */ +static void csiphy_stream_off(struct csiphy_device *csiphy) +{ + phy_power_off(csiphy->phy); +} + +/* + * csiphy_set_stream - Enable/disable streaming on CSIPHY module + * @sd: CSIPHY V4L2 subdevice + * @enable: Requested streaming state + * + * Return 0 on success or a negative error code otherwise + */ +static int csiphy_set_stream_legacy(struct v4l2_subdev *sd, int enable) +{ + struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); + int ret = 0; + + if (enable) + ret = csiphy_stream_on_legacy(csiphy); + else + csiphy_stream_off_legacy(csiphy); + + return ret; +} /* * csiphy_set_stream - Enable/disable streaming on CSIPHY module @@ -568,16 +645,16 @@ } /* - * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources + * msm_csiphy_subdev_init_legacy - Initialize CSIPHY device structure and resources * @csiphy: CSIPHY device * @res: CSIPHY module resources table * @id: CSIPHY module id * * Return 0 on success or a negative error code otherwise */ -int msm_csiphy_subdev_init(struct camss *camss, - struct csiphy_device *csiphy, - const struct camss_subdev_resources *res, u8 id) +int msm_csiphy_subdev_init_legacy(struct camss *camss, + struct csiphy_device *csiphy, + const struct camss_subdev_resources *res, u8 id) { struct device *dev = camss->dev; struct platform_device *pdev = to_platform_device(dev); @@ -706,6 +783,69 @@ } /* + * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources + * @csiphy: CSIPHY device + * @res: CSIPHY module resources table + * @id: CSIPHY module id + * + * Return 0 on success or a negative error code otherwise + */ +int msm_csiphy_subdev_init(struct camss *camss, + struct csiphy_device *csiphy, + const struct camss_subdev_resources *res, u8 id) +{ + struct device *dev = camss->dev; + struct of_phandle_args args; + u8 combo_mode; + int idx; + int ret; + + snprintf(csiphy->name, ARRAY_SIZE(csiphy->name), "csiphy%d", id); + + idx = of_property_match_string(dev->of_node, "phy-names", csiphy->name); + if (idx < 0) { + dev_err(dev, "%s not found\n", csiphy->name); + return idx; + } + + ret = of_parse_phandle_with_args(dev->of_node, "phys", "#phy-cells", idx, &args); + if (ret < 0) { + dev_err(dev, "unable to parse phys args %s\n", csiphy->name); + return ret; + } + + if (!of_device_is_available(args.np)) + goto put_np; + + combo_mode = args.args[0]; + if (combo_mode != PHY_TYPE_DPHY) { + dev_err(dev, "%s mode %d not supported\n", csiphy->name, combo_mode); + ret = -EOPNOTSUPP; + goto put_np; + } + + csiphy->phy = devm_phy_get(dev, csiphy->name); + if (IS_ERR(csiphy->phy)) { + ret = PTR_ERR(csiphy->phy); + goto put_np; + } + + csiphy->camss = camss; + csiphy->id = id; + csiphy->cfg.combo_mode = combo_mode; + csiphy->res = &res->csiphy; + + ret = phy_init(csiphy->phy); + if (ret) + dev_err(dev, "phy %s init fail %d\n", csiphy->name, ret); + +put_np: + of_node_put(args.np); + + return ret; +} + +/* * csiphy_link_setup - Setup CSIPHY connections * @entity: Pointer to media entity structure * @local: Pointer to local pad @@ -739,8 +879,12 @@ return 0; } -static const struct v4l2_subdev_core_ops csiphy_core_ops = { - .s_power = csiphy_set_power, +static const struct v4l2_subdev_core_ops csiphy_core_ops_legacy = { + .s_power = csiphy_set_power_legacy, +}; + +static const struct v4l2_subdev_video_ops csiphy_video_ops_legacy = { + .s_stream = csiphy_set_stream_legacy, }; static const struct v4l2_subdev_video_ops csiphy_video_ops = { @@ -754,8 +898,13 @@ .set_fmt = csiphy_set_format, }; +static const struct v4l2_subdev_ops csiphy_v4l2_ops_legacy = { + .core = &csiphy_core_ops_legacy, + .video = &csiphy_video_ops_legacy, + .pad = &csiphy_pad_ops, +}; + static const struct v4l2_subdev_ops csiphy_v4l2_ops = { - .core = &csiphy_core_ops, .video = &csiphy_video_ops, .pad = &csiphy_pad_ops, }; @@ -784,7 +933,11 @@ struct device *dev = csiphy->camss->dev; int ret; - v4l2_subdev_init(sd, &csiphy_v4l2_ops); + if (IS_ERR(csiphy->phy)) + v4l2_subdev_init(sd, &csiphy_v4l2_ops_legacy); + else + v4l2_subdev_init(sd, &csiphy_v4l2_ops); + sd->internal_ops = &csiphy_v4l2_internal_ops; sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", @@ -823,6 +976,8 @@ */ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy) { + if (!IS_ERR(csiphy->phy)) + phy_exit(csiphy->phy); v4l2_device_unregister_subdev(&csiphy->subdev); media_entity_cleanup(&csiphy->subdev.entity); } --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/camss/camss-csiphy.h +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -95,6 +96,7 @@ struct csiphy_device { struct camss *camss; + struct phy *phy; u8 id; struct v4l2_subdev subdev; struct media_pad pads[MSM_CSIPHY_PADS_NUM]; @@ -102,6 +104,7 @@ void __iomem *base_clk_mux; u32 irq; char irq_name[30]; + char name[16]; struct camss_clock *clock; bool *rate_set; int nclocks; @@ -116,6 +119,10 @@ struct camss_subdev_resources; +int msm_csiphy_subdev_init_legacy(struct camss *camss, + struct csiphy_device *csiphy, + const struct camss_subdev_resources *res, u8 id); + int msm_csiphy_subdev_init(struct camss *camss, struct csiphy_device *csiphy, const struct camss_subdev_resources *res, u8 id); --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/camss/camss.c +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/camss/camss.c @@ -3895,15 +3895,6 @@ static const struct camss_subdev_resources csiphy_res_x1e80100[] = { /* CSIPHY0 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy0", "csiphy0_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy0" }, - .interrupt = { "csiphy0" }, .csiphy = { .id = 0, .hw_ops = &csiphy_ops_3ph_1_0, @@ -3912,15 +3903,6 @@ }, /* CSIPHY1 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy1", "csiphy1_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy1" }, - .interrupt = { "csiphy1" }, .csiphy = { .id = 1, .hw_ops = &csiphy_ops_3ph_1_0, @@ -3929,15 +3911,6 @@ }, /* CSIPHY2 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy2", "csiphy2_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy2" }, - .interrupt = { "csiphy2" }, .csiphy = { .id = 2, .hw_ops = &csiphy_ops_3ph_1_0, @@ -3946,15 +3919,6 @@ }, /* CSIPHY4 */ { - .regulators = { - { .supply = "vdd-csiphy-0p8", .init_load_uA = 105000 }, - { .supply = "vdd-csiphy-1p2", .init_load_uA = 58900 } - }, - .clock = { "csiphy4", "csiphy4_timer" }, - .clock_rate = { { 300000000, 400000000, 480000000 }, - { 266666667, 400000000 } }, - .reg = { "csiphy4" }, - .interrupt = { "csiphy4" }, .csiphy = { .id = 4, .hw_ops = &csiphy_ops_3ph_1_0, @@ -4450,14 +4414,35 @@ static int camss_parse_ports(struct camss *camss) { struct device *dev = camss->dev; + const struct camss_resources *res = camss->res; struct fwnode_handle *fwnode = dev_fwnode(dev), *ep; int ret; fwnode_graph_for_each_endpoint(fwnode, ep) { struct camss_async_subdev *csd; + struct fwnode_handle *remote; + + if (!fwnode_device_is_available(ep)) + continue; + + if (res->legacy_phy) { + csd = v4l2_async_nf_add_fwnode_remote(&camss->notifier, ep, + typeof(*csd)); + } else { + /* + * For non-legacy PHY, the CSIPHY is a separate device. + * Register the remote endpoint (CSIPHY's endpoint) as + * the async subdev, not the remote port parent. + */ + remote = fwnode_graph_get_remote_endpoint(ep); + if (!remote) + continue; + + csd = v4l2_async_nf_add_fwnode(&camss->notifier, remote, + struct camss_async_subdev); + fwnode_handle_put(remote); + } - csd = v4l2_async_nf_add_fwnode_remote(&camss->notifier, ep, - typeof(*csd)); if (IS_ERR(csd)) { ret = PTR_ERR(csd); goto err_cleanup; @@ -4489,15 +4474,26 @@ unsigned int i; int ret; - for (i = 0; i < camss->res->csiphy_num; i++) { - ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i], - &res->csiphy_res[i], - res->csiphy_res[i].csiphy.id); - if (ret < 0) { - dev_err(camss->dev, - "Failed to init csiphy%d sub-device: %d\n", - i, ret); - return ret; + if (!res->legacy_phy) { + for (i = 0; i < camss->res->csiphy_num; i++) { + ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i], + &res->csiphy_res[i], + res->csiphy_res[i].csiphy.id); + if (ret < 0) + return ret; + } + } else { + for (i = 0; i < camss->res->csiphy_num; i++) { + ret = msm_csiphy_subdev_init_legacy(camss, &camss->csiphy[i], + &res->csiphy_res[i], + res->csiphy_res[i].csiphy.id); + if (ret < 0) { + dev_err(camss->dev, + "Failed to init csiphy%d sub-device: %d\n", + i, ret); + return ret; + } + camss->csiphy[i].phy = ERR_PTR(-ENODEV); } } @@ -4574,6 +4570,9 @@ for (i = 0; i < camss->res->csiphy_num; i++) { for (j = 0; j < camss->res->csid_num; j++) { + if (!camss->csiphy[i].phy) + continue; + ret = media_create_pad_link(&camss->csiphy[i].subdev.entity, MSM_CSIPHY_PAD_SRC, &camss->csid[j].subdev.entity, @@ -4683,6 +4682,9 @@ int ret; for (i = 0; i < camss->res->csiphy_num; i++) { + if (!camss->csiphy[i].phy) + continue; + ret = msm_csiphy_register_entity(&camss->csiphy[i], &camss->v4l2_dev); if (ret < 0) { @@ -4738,8 +4740,10 @@ i = camss->res->csiphy_num; err_reg_csiphy: - for (i--; i >= 0; i--) - msm_csiphy_unregister_entity(&camss->csiphy[i]); + for (i--; i >= 0; i--) { + if (camss->csiphy[i].phy) + msm_csiphy_unregister_entity(&camss->csiphy[i]); + } return ret; } @@ -4754,8 +4758,10 @@ { unsigned int i; - for (i = 0; i < camss->res->csiphy_num; i++) - msm_csiphy_unregister_entity(&camss->csiphy[i]); + for (i = 0; i < camss->res->csiphy_num; i++) { + if (camss->csiphy[i].phy) + msm_csiphy_unregister_entity(&camss->csiphy[i]); + } for (i = 0; i < camss->res->csid_num; i++) msm_csid_unregister_entity(&camss->csid[i]); @@ -5104,6 +5110,7 @@ static const struct camss_resources msm8916_resources = { .version = CAMSS_8x16, + .legacy_phy = true, .csiphy_res = csiphy_res_8x16, .csid_res = csid_res_8x16, .ispif_res = &ispif_res_8x16, @@ -5115,6 +5122,7 @@ static const struct camss_resources msm8939_resources = { .version = CAMSS_8x39, + .legacy_phy = true, .csiphy_res = csiphy_res_8x39, .csid_res = csid_res_8x39, .ispif_res = &ispif_res_8x39, @@ -5126,6 +5134,7 @@ static const struct camss_resources msm8953_resources = { .version = CAMSS_8x53, + .legacy_phy = true, .icc_res = icc_res_8x53, .icc_path_num = ARRAY_SIZE(icc_res_8x53), .csiphy_res = csiphy_res_8x96, @@ -5139,6 +5148,7 @@ static const struct camss_resources msm8996_resources = { .version = CAMSS_8x96, + .legacy_phy = true, .csiphy_res = csiphy_res_8x96, .csid_res = csid_res_8x96, .ispif_res = &ispif_res_8x96, @@ -5150,6 +5160,7 @@ static const struct camss_resources qcm2290_resources = { .version = CAMSS_2290, + .legacy_phy = true, .csiphy_res = csiphy_res_2290, .csid_res = csid_res_2290, .vfe_res = vfe_res_2290, @@ -5163,6 +5174,7 @@ static const struct camss_resources qcs8300_resources = { .version = CAMSS_8300, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_8300, .csid_res = csid_res_8775p, .csid_wrapper_res = &csid_wrapper_res_sm8550, @@ -5177,6 +5189,7 @@ static const struct camss_resources sa8775p_resources = { .version = CAMSS_8775P, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_8775p, .csid_res = csid_res_8775p, .csid_wrapper_res = &csid_wrapper_res_sm8550, @@ -5190,6 +5203,7 @@ static const struct camss_resources sdm660_resources = { .version = CAMSS_660, + .legacy_phy = true, .csiphy_res = csiphy_res_660, .csid_res = csid_res_660, .ispif_res = &ispif_res_660, @@ -5201,6 +5215,7 @@ static const struct camss_resources sdm670_resources = { .version = CAMSS_845, + .legacy_phy = true, .csiphy_res = csiphy_res_670, .csid_res = csid_res_670, .vfe_res = vfe_res_670, @@ -5212,6 +5227,7 @@ static const struct camss_resources sdm845_resources = { .version = CAMSS_845, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_845, .csid_res = csid_res_845, .vfe_res = vfe_res_845, @@ -5223,6 +5239,7 @@ static const struct camss_resources sm6150_resources = { .version = CAMSS_6150, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_sm6150, .csid_res = csid_res_sm6150, .vfe_res = vfe_res_sm6150, @@ -5236,6 +5253,7 @@ static const struct camss_resources sm8250_resources = { .version = CAMSS_8250, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_8250, .csid_res = csid_res_8250, .vfe_res = vfe_res_8250, @@ -5249,6 +5267,7 @@ static const struct camss_resources sc8280xp_resources = { .version = CAMSS_8280XP, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_sc8280xp, .csid_res = csid_res_sc8280xp, .ispif_res = NULL, @@ -5263,6 +5282,7 @@ static const struct camss_resources sc7280_resources = { .version = CAMSS_7280, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_7280, .csid_res = csid_res_7280, .vfe_res = vfe_res_7280, @@ -5276,6 +5296,7 @@ static const struct camss_resources sm8550_resources = { .version = CAMSS_8550, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_8550, .csid_res = csid_res_8550, .vfe_res = vfe_res_8550, @@ -5290,6 +5311,7 @@ static const struct camss_resources sm8650_resources = { .version = CAMSS_8650, .pd_name = "top", + .legacy_phy = true, .csiphy_res = csiphy_res_sm8650, .csid_res = csid_res_sm8650, .csid_wrapper_res = &csid_wrapper_res_sm8550, --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/camss/camss.h +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/camss/camss.h @@ -104,6 +104,7 @@ struct camss_resources { enum camss_version version; const char *pd_name; + const bool legacy_phy; const struct camss_subdev_resources *csiphy_res; const struct camss_subdev_resources *csid_res; const struct camss_subdev_resources *ispif_res; --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/venus/core.c +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/venus/core.c @@ -398,6 +398,15 @@ if (IS_ERR(core->cpucfg_path)) return PTR_ERR(core->cpucfg_path); + core->llcc_path = devm_of_icc_get(dev, "video-llcc"); + if (IS_ERR(core->llcc_path)) { + /* LLCC path is optional */ + if (PTR_ERR(core->llcc_path) == -ENODATA) + core->llcc_path = NULL; + else + return PTR_ERR(core->llcc_path); + } + core->irq = platform_get_irq(pdev, 0); if (core->irq < 0) return core->irq; @@ -594,12 +603,18 @@ if (ret) goto err_cpucfg_path; + ret = icc_set_bw(core->llcc_path, 0, 0); + if (ret) + goto err_llcc_path; + ret = icc_set_bw(core->video_path, 0, 0); if (ret) goto err_video_path; return ret; +err_llcc_path: + icc_set_bw(core->video_path, kbps_to_icc(20000), 0); err_video_path: icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0); err_cpucfg_path: @@ -639,6 +654,10 @@ if (ret) return ret; + ret = icc_set_bw(core->llcc_path, kbps_to_icc(20000), 0); + if (ret) + return ret; + ret = icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0); if (ret) return ret; @@ -1006,6 +1025,44 @@ .enc_nodename = "video-encoder", }; +static const struct reg_val sm8350_reg_preset[] = { + { 0xb0088, 0, 0x11 }, +}; + +static const struct venus_resources sm8350_res = { + .freq_tbl = sm8250_freq_table, + .freq_tbl_size = ARRAY_SIZE(sm8250_freq_table), + .reg_tbl = sm8350_reg_preset, + .reg_tbl_size = ARRAY_SIZE(sm8350_reg_preset), + .bw_tbl_enc = sm8250_bw_table_enc, + .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .clks = { "core", "iface" }, + .clks_num = 2, + .resets = { "core" }, + .resets_num = 1, + .vcodec0_clks = { "vcodec0_core" }, + .vcodec_clks_num = 1, + .vcodec_pmdomains = (const char *[]) { "venus", "vcodec0" }, + .vcodec_pmdomains_num = 2, + .opp_pmdomain = (const char *[]) { "mx", NULL }, + .vcodec_num = 1, + .max_load = 7833600, /* 7680x4320@60fps */ + .hfi_version = HFI_VERSION_6XX, + .vpu_version = VPU_VERSION_IRIS2, + .num_vpp_pipes = 4, + .vmem_id = VIDC_RESOURCE_NONE, + .vmem_size = 0, + .vmem_addr = 0, + .dma_mask = GENMASK(31, 29) - 1, + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + .fwname = "qcom/vpu-2.0/venus.mbn", +}; + static const struct freq_tbl sc7280_freq_table[] = { { 0, 460000000 }, { 0, 424000000 }, @@ -1119,17 +1176,63 @@ .min_fw = &min_fw, }; +static const struct freq_tbl sc8280xp_freq_table[] = { + { 0, 239999999 }, + { 0, 338000000 }, + { 0, 366000000 }, + { 0, 444000000 }, + { 0, 533000000 }, + { 0, 560000000 }, +}; + +static const struct venus_resources sc8280xp_res = { + .freq_tbl = sc8280xp_freq_table, + .freq_tbl_size = ARRAY_SIZE(sc8280xp_freq_table), + .reg_tbl = sm8350_reg_preset, + .reg_tbl_size = ARRAY_SIZE(sm8350_reg_preset), + .bw_tbl_enc = sm8250_bw_table_enc, + .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), + .bw_tbl_dec = sm8250_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), + .clks = { "core", "iface" }, + .clks_num = 2, + .resets = { "core" }, + .resets_num = 1, + .vcodec0_clks = { "vcodec0_core" }, + .vcodec_clks_num = 1, + .vcodec_pmdomains = (const char *[]) { "venus", "vcodec0" }, + .vcodec_pmdomains_num = 2, + .opp_pmdomain = (const char *[]) { "mx", NULL }, + .vcodec_num = 1, + .max_load = 7833600, /* 7680x4320@60fps */ + .hfi_version = HFI_VERSION_6XX, + .vpu_version = VPU_VERSION_IRIS2, + .num_vpp_pipes = 4, + .vmem_id = VIDC_RESOURCE_NONE, + .vmem_size = 0, + .vmem_addr = 0, + .dma_mask = GENMASK(31, 29) - 1, + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + .fwname = "qcom/vpu-2.0/venus.mbn", +}; + + static const struct of_device_id venus_dt_match[] = { - { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, }, - { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, }, - { .compatible = "qcom,msm8998-venus", .data = &msm8998_res, }, - { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res, }, - { .compatible = "qcom,sc7180-venus", .data = &sc7180_res, }, - { .compatible = "qcom,sc7280-venus", .data = &sc7280_res, }, - { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, }, - { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, - { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, }, - { .compatible = "qcom,sm8250-venus", .data = &sm8250_res, }, + { .compatible = "qcom,msm8916-venus", .data = &msm8916_res }, + { .compatible = "qcom,msm8996-venus", .data = &msm8996_res }, + { .compatible = "qcom,msm8998-venus", .data = &msm8998_res }, + { .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res }, + { .compatible = "qcom,sc7180-venus", .data = &sc7180_res }, + { .compatible = "qcom,sc7280-venus", .data = &sc7280_res }, + { .compatible = "qcom,sc8280xp-venus", .data = &sc8280xp_res }, + { .compatible = "qcom,sdm660-venus", .data = &sdm660_res }, + { .compatible = "qcom,sdm845-venus", .data = &sdm845_res }, + { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2 }, + { .compatible = "qcom,sm8250-venus", .data = &sm8250_res }, + { .compatible = "qcom,sm8350-venus", .data = &sm8350_res }, { } }; MODULE_DEVICE_TABLE(of, venus_dt_match); --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/venus/core.h +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/venus/core.h @@ -40,6 +40,7 @@ struct reg_val { u32 reg; u32 value; + u32 mask; }; struct bw_tbl { @@ -72,6 +73,7 @@ unsigned int bw_tbl_enc_size; const struct bw_tbl *bw_tbl_dec; unsigned int bw_tbl_dec_size; + bool has_llcc_path; const struct reg_val *reg_tbl; unsigned int reg_tbl_size; const struct hfi_ubwc_config *ubwc_conf; @@ -144,6 +146,7 @@ * @vcodec1_clks: an array of vcodec1 struct clk pointers * @video_path: an interconnect handle to video to/from memory path * @cpucfg_path: an interconnect handle to cpu configuration path + * @llcc_path: an interconnect handle to video to/from llcc path * @pmdomains: a pointer to a list of pmdomains * @opp_pmdomain: an OPP power-domain * @resets: an array of reset signals @@ -198,6 +201,7 @@ struct clk *vcodec1_clks[VIDC_VCODEC_CLKS_NUM_MAX]; struct icc_path *video_path; struct icc_path *cpucfg_path; + struct icc_path *llcc_path; struct dev_pm_domain_list *pmdomains; struct dev_pm_domain_list *opp_pmdomain; struct reset_control *resets[VIDC_RESETS_NUM_MAX]; --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/venus/hfi_venus.c +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/venus/hfi_venus.c @@ -369,10 +369,19 @@ const struct venus_resources *res = hdev->core->res; const struct reg_val *tbl = res->reg_tbl; unsigned int count = res->reg_tbl_size; - unsigned int i; + unsigned int i, val; - for (i = 0; i < count; i++) - writel(tbl[i].value, hdev->core->base + tbl[i].reg); + for (i = 0; i < count; i++) { + val = tbl[i].value; + + /* In some cases, we only want to update certain bits */ + if (tbl[i].mask) { + val = readl(hdev->core->base + tbl[i].reg); + val = (val & ~tbl[i].mask) | (tbl[i].value & tbl[i].mask); + } + + writel(val, hdev->core->base + tbl[i].reg); + } } static void venus_soft_int(struct venus_hfi_device *hdev) --- linux-nvidia-7.0.0.orig/drivers/media/platform/qcom/venus/pm_helpers.c +++ linux-nvidia-7.0.0/drivers/media/platform/qcom/venus/pm_helpers.c @@ -243,6 +243,9 @@ dev_dbg(core->dev, VDBGL "total: avg_bw: %u, peak_bw: %u\n", total_avg, total_peak); + if (core->res->has_llcc_path) + icc_set_bw(core->llcc_path, total_avg, total_peak); + return icc_set_bw(core->video_path, total_avg, total_peak); } --- linux-nvidia-7.0.0.orig/drivers/mfd/Kconfig +++ linux-nvidia-7.0.0/drivers/mfd/Kconfig @@ -2402,6 +2402,18 @@ under it in the device tree. Additional drivers must be enabled in order to use the functionality of the device. +config MFD_AAEON + tristate "AAEON WMI MFD devices" + depends on ASUS_WMI + depends on UBUNTU_ODM_DRIVERS + help + Say yes here to support mltiple IO devices on Single Board Computers + produced by AAEON. + + This driver leverages the ASUS WMI interface to access device + resources. + + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 --- linux-nvidia-7.0.0.orig/drivers/mfd/Makefile +++ linux-nvidia-7.0.0/drivers/mfd/Makefile @@ -295,6 +295,7 @@ obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o +obj-$(CONFIG_MFD_AAEON) += mfd-aaeon.o obj-$(CONFIG_MFD_QNAP_MCU) += qnap-mcu.o --- linux-nvidia-7.0.0.orig/drivers/mfd/cs42l43-i2c.c +++ linux-nvidia-7.0.0/drivers/mfd/cs42l43-i2c.c @@ -47,6 +47,7 @@ cs42l43->irq = i2c->irq; /* A device on an I2C is always attached by definition. */ cs42l43->attached = true; + cs42l43->variant_id = (long)device_get_match_data(cs42l43->dev); cs42l43->regmap = devm_regmap_init_i2c(i2c, &cs42l43_i2c_regmap); if (IS_ERR(cs42l43->regmap)) @@ -58,7 +59,8 @@ #if IS_ENABLED(CONFIG_OF) static const struct of_device_id cs42l43_of_match[] = { - { .compatible = "cirrus,cs42l43", }, + { .compatible = "cirrus,cs42l43", .data = (void *)CS42L43_DEVID_VAL }, + { .compatible = "cirrus,cs42l43b", .data = (void *)CS42L43B_DEVID_VAL }, {} }; MODULE_DEVICE_TABLE(of, cs42l43_of_match); @@ -66,7 +68,8 @@ #if IS_ENABLED(CONFIG_ACPI) static const struct acpi_device_id cs42l43_acpi_match[] = { - { "CSC4243", 0 }, + { "CSC4243", CS42L43_DEVID_VAL }, + { "CSC2A3B", CS42L43B_DEVID_VAL }, {} }; MODULE_DEVICE_TABLE(acpi, cs42l43_acpi_match); --- linux-nvidia-7.0.0.orig/drivers/mfd/cs42l43-sdw.c +++ linux-nvidia-7.0.0/drivers/mfd/cs42l43-sdw.c @@ -178,6 +178,7 @@ cs42l43->dev = dev; cs42l43->sdw = sdw; + cs42l43->variant_id = (long)id->driver_data; cs42l43->regmap = devm_regmap_init_sdw(sdw, &cs42l43_sdw_regmap); if (IS_ERR(cs42l43->regmap)) @@ -188,7 +189,8 @@ } static const struct sdw_device_id cs42l43_sdw_id[] = { - SDW_SLAVE_ENTRY(0x01FA, 0x4243, 0), + SDW_SLAVE_ENTRY(0x01FA, 0x4243, (void *) CS42L43_DEVID_VAL), + SDW_SLAVE_ENTRY(0x01FA, 0x2A3B, (void *) CS42L43B_DEVID_VAL), {} }; MODULE_DEVICE_TABLE(sdw, cs42l43_sdw_id); --- linux-nvidia-7.0.0.orig/drivers/mfd/cs42l43.c +++ linux-nvidia-7.0.0/drivers/mfd/cs42l43.c @@ -115,9 +115,14 @@ { CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 }, { CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 }, { CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 }, + { CS42L43B_DECIM_HPF_WNF_CTRL5, 0x00000001 }, + { CS42L43B_DECIM_HPF_WNF_CTRL6, 0x00000001 }, { CS42L43_DMIC_PDM_CTRL, 0x00000000 }, { CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 }, { CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 }, + { CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 }, + { CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 }, + { CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 0x20122012 }, { CS42L43_INTP_VOLUME_CTRL1, 0x00000180 }, { CS42L43_INTP_VOLUME_CTRL2, 0x00000180 }, { CS42L43_AMP1_2_VOL_RAMP, 0x00000022 }, @@ -155,8 +160,12 @@ { CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 }, { CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 }, { CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 }, + { CS42L43B_SWIRE_DP3_CH3_INPUT, 0x00000000 }, + { CS42L43B_SWIRE_DP3_CH4_INPUT, 0x00000000 }, { CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 }, { CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 }, + { CS42L43B_SWIRE_DP4_CH3_INPUT, 0x00000000 }, + { CS42L43B_SWIRE_DP4_CH4_INPUT, 0x00000000 }, { CS42L43_ASRC_INT1_INPUT1, 0x00000000 }, { CS42L43_ASRC_INT2_INPUT1, 0x00000000 }, { CS42L43_ASRC_INT3_INPUT1, 0x00000000 }, @@ -169,10 +178,14 @@ { CS42L43_ISRC1INT2_INPUT1, 0x00000000 }, { CS42L43_ISRC1DEC1_INPUT1, 0x00000000 }, { CS42L43_ISRC1DEC2_INPUT1, 0x00000000 }, + { CS42L43B_ISRC1DEC3_INPUT1, 0x00000000 }, + { CS42L43B_ISRC1DEC4_INPUT1, 0x00000000 }, { CS42L43_ISRC2INT1_INPUT1, 0x00000000 }, { CS42L43_ISRC2INT2_INPUT1, 0x00000000 }, { CS42L43_ISRC2DEC1_INPUT1, 0x00000000 }, { CS42L43_ISRC2DEC2_INPUT1, 0x00000000 }, + { CS42L43B_ISRC2DEC3_INPUT1, 0x00000000 }, + { CS42L43B_ISRC2DEC4_INPUT1, 0x00000000 }, { CS42L43_EQ1MIX_INPUT1, 0x00800000 }, { CS42L43_EQ1MIX_INPUT2, 0x00800000 }, { CS42L43_EQ1MIX_INPUT3, 0x00800000 }, @@ -269,6 +282,8 @@ bool cs42l43_readable_register(struct device *dev, unsigned int reg) { + struct cs42l43 *cs42l43 = dev_get_drvdata(dev); + switch (reg) { case CS42L43_DEVID: case CS42L43_REVID: @@ -292,7 +307,6 @@ case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2: case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4: case CS42L43_DMIC_PDM_CTRL: - case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4: case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2: case CS42L43_AMP1_2_VOL_RAMP: case CS42L43_ASP_CTRL: @@ -387,8 +401,16 @@ case CS42L43_BOOT_CONTROL: case CS42L43_BLOCK_EN: case CS42L43_SHUTTER_CONTROL: - case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX: - return true; + case CS42L43B_MCU_SW_REV ... CS42L43B_MCU_RAM_MAX: + return true; // registers present on all variants + case CS42L43_MCU_SW_REV ... CS42L43B_MCU_SW_REV - 1: + case CS42L43B_MCU_RAM_MAX + 1 ... CS42L43_MCU_RAM_MAX: + case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4: + return cs42l43->variant_id == CS42L43_DEVID_VAL; // regs only in CS42L43 variant + case CS42L43B_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43B_DECIM_HPF_WNF_CTRL6: + case CS42L43B_SWIRE_DP3_CH3_INPUT ... CS42L43B_SWIRE_DP4_CH4_INPUT: + case CS42L43B_ISRC1DEC3_INPUT1 ... CS42L43B_ISRC2DEC4_INPUT1: + return cs42l43->variant_id == CS42L43B_DEVID_VAL; // regs only in CS42L43B variant default: return false; } @@ -597,15 +619,27 @@ static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow) { unsigned int need_reg = CS42L43_NEED_CONFIGS; + unsigned int boot_reg; unsigned int val; int ret; - if (shadow) - need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS; + switch (cs42l43->variant_id) { + case CS42L43_DEVID_VAL: + if (shadow) + need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS; + boot_reg = CS42L43_BOOT_STATUS; + break; + case CS42L43B_DEVID_VAL: + need_reg = CS42L43B_NEED_CONFIGS; + boot_reg = CS42L43B_BOOT_STATUS; + break; + default: + return -EINVAL; + } regmap_write(cs42l43->regmap, need_reg, 0); - ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS, + ret = regmap_read_poll_timeout(cs42l43->regmap, boot_reg, val, (val == CS42L43_MCU_BOOT_STAGE3), CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US); if (ret) { @@ -644,13 +678,25 @@ */ static int cs42l43_mcu_disable(struct cs42l43 *cs42l43) { - unsigned int val; + unsigned int val, cfg_reg, ctrl_reg; int ret; - regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG, - CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL); - regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION, - CS42L43_FW_MM_CTRL_MCU_SEL_MASK); + switch (cs42l43->variant_id) { + case CS42L43_DEVID_VAL: + cfg_reg = CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG; + ctrl_reg = CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION; + break; + case CS42L43B_DEVID_VAL: + cfg_reg = CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG; + ctrl_reg = CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION; + break; + default: + return -EINVAL; + } + + regmap_write(cs42l43->regmap, cfg_reg, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL); + regmap_write(cs42l43->regmap, ctrl_reg, CS42L43_FW_MM_CTRL_MCU_SEL_MASK); + regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK); regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0); @@ -740,18 +786,32 @@ { unsigned int mcu_rev, bios_rev, boot_status, secure_cfg; bool patched, shadow; + int boot_status_reg, mcu_sw_rev_reg; int ret; + switch (cs42l43->variant_id) { + case CS42L43_DEVID_VAL: + boot_status_reg = CS42L43_BOOT_STATUS; + mcu_sw_rev_reg = CS42L43_MCU_SW_REV; + break; + case CS42L43B_DEVID_VAL: + boot_status_reg = CS42L43B_BOOT_STATUS; + mcu_sw_rev_reg = CS42L43B_MCU_SW_REV; + break; + default: + return -EINVAL; + } + /* Clear any stale software interrupt bits. */ regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev); - ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status); + ret = regmap_read(cs42l43->regmap, boot_status_reg, &boot_status); if (ret) { dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret); return ret; } - ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev); + ret = regmap_read(cs42l43->regmap, mcu_sw_rev_reg, &mcu_rev); if (ret) { dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret); return ret; @@ -918,6 +978,13 @@ switch (devid) { case CS42L43_DEVID_VAL: + case CS42L43B_DEVID_VAL: + if (devid != cs42l43->variant_id) { + dev_err(cs42l43->dev, + "Device ID (0x%06x) does not match variant ID (0x%06lx)\n", + devid, cs42l43->variant_id); + goto err; + } break; default: dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid); --- linux-nvidia-7.0.0.orig/drivers/mfd/cs42l43.h +++ linux-nvidia-7.0.0/drivers/mfd/cs42l43.h @@ -9,7 +9,7 @@ #ifndef CS42L43_CORE_INT_H #define CS42L43_CORE_INT_H -#define CS42L43_N_DEFAULTS 176 +#define CS42L43_N_DEFAULTS 189 struct dev_pm_ops; struct device; --- linux-nvidia-7.0.0.orig/drivers/mfd/mfd-aaeon.c +++ linux-nvidia-7.0.0/drivers/mfd/mfd-aaeon.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * UP Board main platform driver and FPGA configuration support + * + * Copyright (c) 2021, AAEON Ltd. + * + * Author: Kunyang_Fan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AAEON_WMI_MGMT_GUID "97845ED0-4E6D-11DE-8A39-0800200C9A66" + +#define WMI_REPORT_CAPABILITY_METHOD 0x00000000 +#define MAX_BFPI_VERSION 255 +#define GET_REVISION_ID 0x00 + +struct aaeon_wmi_priv { + const struct mfd_cell *cells; + size_t ncells; +}; + +static const struct mfd_cell aaeon_mfd_cells[] = { + { .name = "gpio-aaeon" }, + { .name = "hwmon-aaeon"}, + { .name = "leds-aaeon"}, + { .name = "wdt-aaeon"}, +}; + +static const struct aaeon_wmi_priv aaeon_wmi_priv_data = { + .cells = aaeon_mfd_cells, + .ncells = ARRAY_SIZE(aaeon_mfd_cells), +}; + +static int aaeon_wmi_check_device(void) +{ + int err; + int retval; + + err = asus_wmi_evaluate_method(WMI_REPORT_CAPABILITY_METHOD, GET_REVISION_ID, 0, + &retval); + if (err) + return -ENODEV; + if (retval < 3 || retval > MAX_BFPI_VERSION) + return -ENODEV; + + return 0; +} + +static int aaeon_wmi_probe(struct wmi_device *wdev, const void *context) +{ + struct aaeon_wmi_priv *priv; + + if (!wmi_has_guid(AAEON_WMI_MGMT_GUID)) { + dev_info(&wdev->dev, "AAEON Management GUID not found\n"); + return -ENODEV; + } + + if (aaeon_wmi_check_device()) + return -ENODEV; + + priv = (struct aaeon_wmi_priv *)context; + dev_set_drvdata(&wdev->dev, priv); + + return devm_mfd_add_devices(&wdev->dev, 0, priv->cells, + priv->ncells, NULL, 0, NULL); +} + +static const struct wmi_device_id aaeon_wmi_id_table[] = { + { AAEON_WMI_MGMT_GUID, (void *)&aaeon_wmi_priv_data }, + {} +}; + +static struct wmi_driver aaeon_wmi_driver = { + .driver = { + .name = "mfd-aaeon", + }, + .id_table = aaeon_wmi_id_table, + .probe = aaeon_wmi_probe, +}; + +module_wmi_driver(aaeon_wmi_driver); + +MODULE_DEVICE_TABLE(wmi, aaeon_wmi_id_table); +MODULE_AUTHOR("Kunyang Fan "); +MODULE_DESCRIPTION("AAEON Board WMI driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("ASUS_WMI"); --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/amazon/ena/ena_com.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/amazon/ena/ena_com.h @@ -48,7 +48,7 @@ /*****************************************************************************/ /* ENA adaptive interrupt moderation settings */ -#define ENA_INTR_INITIAL_TX_INTERVAL_USECS 64 +#define ENA_INTR_INITIAL_TX_INTERVAL_USECS 0 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 20 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1 --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/intel/igc/igc_main.c +++ linux-nvidia-7.0.0/drivers/net/ethernet/intel/igc/igc_main.c @@ -7202,6 +7202,9 @@ memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); + if (pci_is_thunderbolt_attached(pdev)) + msleep(1000); + /* Initialize skew-specific constants */ err = ei->get_invariants(hw); if (err) --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/Kconfig +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/Kconfig @@ -126,4 +126,6 @@ To compile this driver as a module, choose M here: the module will be called rtase. This is recommended. +source "drivers/net/ethernet/realtek/r8127/Kconfig" + endif # NET_VENDOR_REALTEK --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/Makefile +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/Makefile @@ -9,3 +9,4 @@ r8169-$(CONFIG_R8169_LEDS) += r8169_leds.o obj-$(CONFIG_R8169) += r8169.o obj-$(CONFIG_RTASE) += rtase/ +obj-$(CONFIG_R8127) += r8127/ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/Kconfig +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/Kconfig @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ + +################################################################################ +# This product is covered by one or more of the following patents: +# US6,570,884, US6,115,776, and US6,327,625. +################################################################################ + +config R8127 + tristate "RealTek RTL-8127 PCI 10 Gigabit Ethernet Adapter support" + depends on PCI + help + This is a driver for the 10 Gigabit Ethernet PCI network cards based on + the RTL-8127 chips. If you have one of those, say Y here. + + To compile this driver as a module, choose M here: the module + will be called r8127. This is recommended. + --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/Makefile +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/Makefile @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ + +################################################################################ +# This product is covered by one or more of the following patents: +# US6,570,884, US6,115,776, and US6,327,625. +################################################################################ + +ccflags-y += -DCONFIG_SOC_LAN -DCONFIG_R8127_NAPI -DCONFIG_R8127_VLAN -DCONFIG_ASPM -DENABLE_S5WOL -DENABLE_EEE -DENABLE_TX_NO_CLOSE -DENABLE_GIGA_LITE +obj-$(CONFIG_R8127) += r8127.o +r8127-y := r8127_n.o rtl_eeprom.o rtltool.o --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/r8127.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/r8127.h @@ -0,0 +1,3068 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#ifndef __R8127_H +#define __R8127_H + +//#include +#include +#include +#include +#include "r8127_dash.h" +#include "r8127_realwow.h" +#ifdef ENABLE_PTP_SUPPORT +#include "r8127_ptp.h" +#endif +#include "r8127_rss.h" +#ifdef ENABLE_LIB_SUPPORT +#include "r8127_lib.h" +#endif + +#ifndef fallthrough +#define fallthrough +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) +#define netif_xmit_stopped netif_tx_queue_stopped +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0) +#ifndef MDIO_AN_EEE_ADV_100TX +#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ +#endif +#ifndef MDIO_AN_EEE_ADV_1000T +#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) +#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */ +#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */ +#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */ +#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */ +#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ +#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) */ + +static inline u32 mmd_eee_adv_to_ethtool_adv_t(u16 eee_adv) +{ + u32 adv = 0; + + if (eee_adv & MDIO_EEE_100TX) + adv |= ADVERTISED_100baseT_Full; + if (eee_adv & MDIO_EEE_1000T) + adv |= ADVERTISED_1000baseT_Full; + if (eee_adv & MDIO_EEE_10GT) + adv |= ADVERTISED_10000baseT_Full; + if (eee_adv & MDIO_EEE_1000KX) + adv |= ADVERTISED_1000baseKX_Full; + if (eee_adv & MDIO_EEE_10GKX4) + adv |= ADVERTISED_10000baseKX4_Full; + if (eee_adv & MDIO_EEE_10GKR) + adv |= ADVERTISED_10000baseKR_Full; + + return adv; +} + +static inline u16 ethtool_adv_to_mmd_eee_adv_t(u32 adv) +{ + u16 reg = 0; + + if (adv & ADVERTISED_100baseT_Full) + reg |= MDIO_EEE_100TX; + if (adv & ADVERTISED_1000baseT_Full) + reg |= MDIO_EEE_1000T; + if (adv & ADVERTISED_10000baseT_Full) + reg |= MDIO_EEE_10GT; + if (adv & ADVERTISED_1000baseKX_Full) + reg |= MDIO_EEE_1000KX; + if (adv & ADVERTISED_10000baseKX4_Full) + reg |= MDIO_EEE_10GKX4; + if (adv & ADVERTISED_10000baseKR_Full) + reg |= MDIO_EEE_10GKR; + + return reg; +} +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0) +static inline bool skb_transport_header_was_set(const struct sk_buff *skb) +{ + return skb->transport_header != ~0U; +} +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0) +static inline void linkmode_set_bit(int nr, volatile unsigned long *addr) +{ + __set_bit(nr, addr); +} + +static inline void linkmode_clear_bit(int nr, volatile unsigned long *addr) +{ + __clear_bit(nr, addr); +} + +static inline int linkmode_test_bit(int nr, volatile unsigned long *addr) +{ + return test_bit(nr, addr); +} +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0) +static inline void linkmode_mod_bit(int nr, volatile unsigned long *addr, + int set) +{ + if (set) + linkmode_set_bit(nr, addr); + else + linkmode_clear_bit(nr, addr); +} +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,3,0) +static inline +ssize_t strscpy(char *dest, const char *src, size_t count) +{ + long res = 0; + + if (count == 0) + return -E2BIG; + + while (count) { + char c; + + c = src[res]; + dest[res] = c; + if (!c) + return res; + res++; + count--; + } + + /* Hit buffer length without finding a NUL; force NUL-termination. */ + if (res) + dest[res-1] = '\0'; + + return -E2BIG; +} +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)) +static inline unsigned char *skb_checksum_start(const struct sk_buff *skb) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)) + return skb->head + skb->csum_start; +#else /* < 2.6.22 */ + return skb_transport_header(skb); +#endif +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) +static inline void netdev_tx_sent_queue(struct netdev_queue *dev_queue, + unsigned int bytes) +{} +static inline void netdev_tx_completed_queue(struct netdev_queue *dev_queue, + unsigned int pkts, + unsigned int bytes) +{} +static inline void netdev_tx_reset_queue(struct netdev_queue *q) {} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0) +static inline void fsleep(unsigned long usecs) +{ + if (usecs <= 10) + udelay(usecs); + else if (usecs <= 20000) + usleep_range(usecs, 2 * usecs); + else + msleep(DIV_ROUND_UP(usecs, 1000)); +} +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0) +#define netdev_xmit_more() (0) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0) +#define netif_testing_on(dev) +#define netif_testing_off(dev) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) +#define netdev_sw_irq_coalesce_default_on(dev) +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) +typedef int netdev_tx_t; +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0) +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,1,9) +static inline bool page_is_pfmemalloc(struct page *page) +{ + /* + * Page index cannot be this large so this must be + * a pfmemalloc page. + */ + return page->index == -1UL; +} +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4,1,9) */ +static inline bool dev_page_is_reusable(struct page *page) +{ + return likely(page_to_nid(page) == numa_mem_id() && + !page_is_pfmemalloc(page)); +} +#endif + +/* +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)&& !defined(ENABLE_LIB_SUPPORT) +#define RTL_USE_NEW_INTR_API +#endif +*/ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,10,0) +#define dma_map_page_attrs(dev, page, offset, size, dir, attrs) \ + dma_map_page(dev, page, offset, size, dir) +#define dma_unmap_page_attrs(dev, page, size, dir, attrs) \ + dma_unmap_page(dev, page, size, dir) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,10,0) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) +#define page_ref_inc(page) atomic_inc(&page->_count) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,216) +#define page_ref_count(page) atomic_read(&page->_count) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,4,216) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) +#define skb_transport_offset(skb) (skb->h.raw - skb->data) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) +#define device_set_wakeup_enable(dev, val) do {} while (0) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) +static inline void ether_addr_copy(u8 *dst, const u8 *src) +{ + u16 *a = (u16 *)dst; + const u16 *b = (const u16 *)src; + + a[0] = b[0]; + a[1] = b[1]; + a[2] = b[2]; +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) +#define IS_ERR_OR_NULL(ptr) (!ptr) +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0) +#define reinit_completion(x) ((x)->done = 0) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) +#define pm_runtime_mark_last_busy(x) +#define pm_runtime_put_autosuspend(x) pm_runtime_put(x) +#define pm_runtime_put_sync_autosuspend(x) pm_runtime_put_sync(x) + +static inline bool pm_runtime_suspended(struct device *dev) +{ + return dev->power.runtime_status == RPM_SUSPENDED + && !dev->power.disable_depth; +} + +static inline bool pm_runtime_active(struct device *dev) +{ + return dev->power.runtime_status == RPM_ACTIVE + || dev->power.disable_depth; +} +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) +#define queue_delayed_work(long_wq, work, delay) schedule_delayed_work(work, delay) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) +#define netif_printk(priv, type, level, netdev, fmt, args...) \ + do { \ + if (netif_msg_##type(priv)) \ + printk(level "%s: " fmt,(netdev)->name , ##args); \ + } while (0) + +#define netif_emerg(priv, type, netdev, fmt, args...) \ + netif_printk(priv, type, KERN_EMERG, netdev, fmt, ##args) +#define netif_alert(priv, type, netdev, fmt, args...) \ + netif_printk(priv, type, KERN_ALERT, netdev, fmt, ##args) +#define netif_crit(priv, type, netdev, fmt, args...) \ + netif_printk(priv, type, KERN_CRIT, netdev, fmt, ##args) +#define netif_err(priv, type, netdev, fmt, args...) \ + netif_printk(priv, type, KERN_ERR, netdev, fmt, ##args) +#define netif_warn(priv, type, netdev, fmt, args...) \ + netif_printk(priv, type, KERN_WARNING, netdev, fmt, ##args) +#define netif_notice(priv, type, netdev, fmt, args...) \ + netif_printk(priv, type, KERN_NOTICE, netdev, fmt, ##args) +#define netif_info(priv, type, netdev, fmt, args...) \ + netif_printk(priv, type, KERN_INFO, (netdev), fmt, ##args) +#endif +#endif +#endif +#endif +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) +#define setup_timer(_timer, _function, _data) \ +do { \ + (_timer)->function = _function; \ + (_timer)->data = _data; \ + init_timer(_timer); \ +} while (0) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) +#if defined(skb_vlan_tag_present) && !defined(vlan_tx_tag_present) +#define vlan_tx_tag_present skb_vlan_tag_present +#endif +#if defined(skb_vlan_tag_get) && !defined(vlan_tx_tag_get) +#define vlan_tx_tag_get skb_vlan_tag_get +#endif +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) + +#define RTL_ALLOC_SKB_INTR(napi, length) dev_alloc_skb(length) +#define R8127_USE_NAPI_ALLOC_SKB 0 +#ifdef CONFIG_R8127_NAPI +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0) +#undef RTL_ALLOC_SKB_INTR +#define RTL_ALLOC_SKB_INTR(napi, length) napi_alloc_skb(napi, length) +#undef R8127_USE_NAPI_ALLOC_SKB +#define R8127_USE_NAPI_ALLOC_SKB 1 +#endif +#endif + +#define RTL_BUILD_SKB_INTR(data, frag_size) build_skb(data, frag_size) +#ifdef CONFIG_R8127_NAPI +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,12,0) +#undef RTL_BUILD_SKB_INTR +#define RTL_BUILD_SKB_INTR(data, frag_size) napi_build_skb(data, frag_size) +#endif +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) +#define eth_random_addr(addr) random_ether_addr(addr) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) +#define netdev_features_t u32 +#endif +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,5,0) +#define NETIF_F_ALL_CSUM NETIF_F_CSUM_MASK +#else +#ifndef NETIF_F_ALL_CSUM +#define NETIF_F_ALL_CSUM NETIF_F_CSUM_MASK +#endif +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) +#define ENABLE_R8127_PROCFS +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,11,0) +#define ENABLE_R8127_SYSFS +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) +#define NETIF_F_HW_VLAN_RX NETIF_F_HW_VLAN_CTAG_RX +#define NETIF_F_HW_VLAN_TX NETIF_F_HW_VLAN_CTAG_TX +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0) +#define __devinit +#define __devexit +#define __devexit_p(func) func +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +#define CHECKSUM_PARTIAL CHECKSUM_HW +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#define irqreturn_t void +#define IRQ_HANDLED 1 +#define IRQ_NONE 0 +#define IRQ_RETVAL(x) +#endif + +#ifndef NETIF_F_RXALL +#define NETIF_F_RXALL 0 +#endif + +#ifndef NETIF_F_RXFCS +#define NETIF_F_RXFCS 0 +#endif + +#if !defined(HAVE_FREE_NETDEV) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0)) +#define free_netdev(x) kfree(x) +#endif + +#ifndef SET_NETDEV_DEV +#define SET_NETDEV_DEV(net, pdev) +#endif + +#ifndef SET_MODULE_OWNER +#define SET_MODULE_OWNER(dev) +#endif + +#ifndef SA_SHIRQ +#define SA_SHIRQ IRQF_SHARED +#endif + +#ifndef NETIF_F_GSO +#define gso_size tso_size +#define gso_segs tso_segs +#endif + +#ifndef PCI_VENDOR_ID_DLINK +#define PCI_VENDOR_ID_DLINK 0x1186 +#endif + +#ifndef dma_mapping_error +#define dma_mapping_error(a,b) 0 +#endif + +#ifndef netif_err +#define netif_err(a,b,c,d) +#endif + +#ifndef AUTONEG_DISABLE +#define AUTONEG_DISABLE 0x00 +#endif + +#ifndef AUTONEG_ENABLE +#define AUTONEG_ENABLE 0x01 +#endif + +#ifndef BMCR_SPEED1000 +#define BMCR_SPEED1000 0x0040 +#endif + +#ifndef BMCR_SPEED100 +#define BMCR_SPEED100 0x2000 +#endif + +#ifndef BMCR_SPEED10 +#define BMCR_SPEED10 0x0000 +#endif + +#ifndef SPEED_UNKNOWN +#define SPEED_UNKNOWN -1 +#endif + +#ifndef DUPLEX_UNKNOWN +#define DUPLEX_UNKNOWN 0xff +#endif + +#ifndef SUPPORTED_Pause +#define SUPPORTED_Pause (1 << 13) +#endif + +#ifndef SUPPORTED_Asym_Pause +#define SUPPORTED_Asym_Pause (1 << 14) +#endif + +#ifndef MDIO_EEE_100TX +#define MDIO_EEE_100TX 0x0002 +#endif + +#ifndef MDIO_EEE_1000T +#define MDIO_EEE_1000T 0x0004 +#endif + +#ifndef MDIO_EEE_2_5GT +#define MDIO_EEE_2_5GT 0x0001 +#endif + +#ifndef MDIO_EEE_5GT +#define MDIO_EEE_5GT 0x0002 +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,9,0) +#define ethtool_keee ethtool_eee +#define rtl8127_ethtool_adv_to_mmd_eee_adv_cap1_t ethtool_adv_to_mmd_eee_adv_t +static inline u32 rtl8127_ethtool_adv_to_mmd_eee_adv_cap2_t(u32 adv) +{ + u32 result = 0; + + if (adv & SUPPORTED_2500baseX_Full) + result |= MDIO_EEE_2_5GT; + + return result; +} +#else +#define rtl8127_ethtool_adv_to_mmd_eee_adv_cap1_t linkmode_to_mii_eee_cap1_t +#define rtl8127_ethtool_adv_to_mmd_eee_adv_cap2_t linkmode_to_mii_eee_cap2_t +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(6,9,0) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) +#ifdef CONFIG_NET_POLL_CONTROLLER +#define RTL_NET_POLL_CONTROLLER dev->poll_controller=rtl8127_netpoll +#else +#define RTL_NET_POLL_CONTROLLER +#endif + +#ifdef CONFIG_R8127_VLAN +#define RTL_SET_VLAN dev->vlan_rx_register=rtl8127_vlan_rx_register +#else +#define RTL_SET_VLAN +#endif + +#define RTL_NET_DEVICE_OPS(ops) dev->open=rtl8127_open; \ + dev->hard_start_xmit=rtl8127_start_xmit; \ + dev->get_stats=rtl8127_get_stats; \ + dev->stop=rtl8127_close; \ + dev->tx_timeout=rtl8127_tx_timeout; \ + dev->set_multicast_list=rtl8127_set_rx_mode; \ + dev->change_mtu=rtl8127_change_mtu; \ + dev->set_mac_address=rtl8127_set_mac_address; \ + dev->do_ioctl=rtl8127_do_ioctl; \ + RTL_NET_POLL_CONTROLLER; \ + RTL_SET_VLAN; +#else +#define RTL_NET_DEVICE_OPS(ops) dev->netdev_ops=&ops +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef false +#define false 0 +#endif + +#ifndef true +#define true 1 +#endif + +//Hardware will continue interrupt 10 times after interrupt finished. +#define RTK_KEEP_INTERRUPT_COUNT (10) + +//the low 32 bit address of receive buffer must be 8-byte alignment. +#ifndef NET_IP_ALIGN +#define NET_IP_ALIGN 2 +#endif +#define R8127_RX_ALIGN NET_IP_ALIGN + +#ifdef CONFIG_R8127_NAPI +#define NAPI_SUFFIX "-NAPI" +#else +#define NAPI_SUFFIX "" +#endif +#if defined(ENABLE_DASH_PRINTER_SUPPORT) +#define DASH_SUFFIX "-PRINTER" +#elif defined(ENABLE_DASH_SUPPORT) +#define DASH_SUFFIX "-DASH" +#else +#define DASH_SUFFIX "" +#endif + +#if defined(ENABLE_REALWOW_SUPPORT) +#define REALWOW_SUFFIX "-REALWOW" +#else +#define REALWOW_SUFFIX "" +#endif + +#if defined(ENABLE_PTP_SUPPORT) +#define PTP_SUFFIX "-PTP" +#else +#define PTP_SUFFIX "" +#endif + +#if defined(ENABLE_RSS_SUPPORT) +#define RSS_SUFFIX "-RSS" +#else +#define RSS_SUFFIX "" +#endif + +#define RTL8127_VERSION "11.014.00" NAPI_SUFFIX DASH_SUFFIX REALWOW_SUFFIX PTP_SUFFIX RSS_SUFFIX +#define MODULENAME "r8127" +#define PFX MODULENAME ": " + +#define GPL_CLAIM "\ +r8127 Copyright (C) 2025 Realtek NIC software team \n \ +This program comes with ABSOLUTELY NO WARRANTY; for details, please see . \n \ +This is free software, and you are welcome to redistribute it under certain conditions; see . \n" + +#ifdef RTL8127_DEBUG +#define assert(expr) \ + if(!(expr)) { \ + printk("Assertion failed! %s,%s,%s,line=%d\n", \ + #expr,__FILE__,__FUNCTION__,__LINE__); \ + } +#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) +#else +#define assert(expr) do {} while (0) +#define dprintk(fmt, args...) do {} while (0) +#endif /* RTL8127_DEBUG */ + +#define R8127_MSG_DEFAULT \ + (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) + +#ifdef CONFIG_R8127_NAPI +#define rtl8127_rx_hwaccel_skb vlan_hwaccel_receive_skb +#define rtl8127_rx_quota(count, quota) min(count, quota) +#else +#define rtl8127_rx_hwaccel_skb vlan_hwaccel_rx +#define rtl8127_rx_quota(count, quota) count +#endif + +/* MAC address length */ +#ifndef MAC_ADDR_LEN +#define MAC_ADDR_LEN 6 +#endif + +#ifndef MAC_PROTOCOL_LEN +#define MAC_PROTOCOL_LEN 2 +#endif + +#ifndef ETH_FCS_LEN +#define ETH_FCS_LEN 4 +#endif + +#ifndef NETIF_F_TSO6 +#define NETIF_F_TSO6 0 +#endif + +#define Reserved2_data 7 +#define RX_DMA_BURST_unlimited 7 /* Maximum PCI burst, '7' is unlimited */ +#define RX_DMA_BURST_512 5 +#define RX_DMA_BURST_256 4 +#define TX_DMA_BURST_unlimited 7 +#define TX_DMA_BURST_1024 6 +#define TX_DMA_BURST_512 5 +#define TX_DMA_BURST_256 4 +#define TX_DMA_BURST_128 3 +#define TX_DMA_BURST_64 2 +#define TX_DMA_BURST_32 1 +#define TX_DMA_BURST_16 0 +#define Reserved1_data 0x3F +#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ +#define Jumbo_Frame_1k ETH_DATA_LEN +#define Jumbo_Frame_2k (2*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define Jumbo_Frame_3k (3*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define Jumbo_Frame_4k (4*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define Jumbo_Frame_5k (5*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define Jumbo_Frame_6k (6*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define Jumbo_Frame_7k (7*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define Jumbo_Frame_8k (8*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define Jumbo_Frame_9k (9*1024 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN) +#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ +#define RxEarly_off_V1 (0x07 << 11) +#define RxEarly_off_V2 (1 << 11) +#define Rx_Single_fetch_V2 (1 << 14) +#define Rx_Close_Multiple (1 << 21) +#define Rx_Fetch_Number_8 (1 << 30) + +#define R8127_REGS_SIZE (256) +#define R8127_MAC_REGS_SIZE (256) +#define R8127_PHY_REGS_SIZE (16*2) +#define R8127_EPHY_REGS_SIZE (31*2) +#define R8127_ERI_REGS_SIZE (0x100) +#define R8127_REGS_DUMP_SIZE (0x400) +#define R8127_PCI_REGS_SIZE (0x100) +#define R8127_NAPI_WEIGHT 64 + +#define R8127_MAX_MSIX_VEC_8125A 4 +#define R8127_MAX_MSIX_VEC_8125B 32 +#define R8127_MAX_MSIX_VEC_8125D 32 +#define R8127_MIN_MSIX_VEC_8125B 22 +#define R8127_MIN_MSIX_VEC_8125BP 31 +#define R8127_MIN_MSIX_VEC_8125D 20 +#define R8127_MIN_MSIX_VEC_8127 30 +#define R8127_MAX_MSIX_VEC 32 +#define R8127_MAX_RX_QUEUES_VEC_V3 (16) +#define R8127_MAX_RX_QUEUES_VEC_V4 (8) + +#define RTL8127_TX_TIMEOUT (6 * HZ) +#define RTL8127_LINK_TIMEOUT (1 * HZ) +#define RTL8127_ESD_TIMEOUT (2 * HZ) + +#define rtl8127_rx_page_size(order) (PAGE_SIZE << order) + +#define MAX_NUM_TX_DESC 1024 /* Maximum number of Tx descriptor registers */ +#define MAX_NUM_RX_DESC 1024 /* Maximum number of Rx descriptor registers */ + +#define MIN_NUM_TX_DESC 256 /* Minimum number of Tx descriptor registers */ +#define MIN_NUM_RX_DESC 256 /* Minimum number of Rx descriptor registers */ + +#define NUM_TX_DESC MAX_NUM_TX_DESC /* Number of Tx descriptor registers */ +#define NUM_RX_DESC MAX_NUM_RX_DESC /* Number of Rx descriptor registers */ + +#ifdef ENABLE_DOUBLE_VLAN +#define RX_BUF_SIZE 0x05F6 /* 0x05F6(1526) = 1514 + 8(double vlan) + 4(crc) bytes */ +#define RT_VALN_HLEN 8 /* 8(double vlan) bytes */ +#else +#define RX_BUF_SIZE 0x05F2 /* 0x05F2(1522) = 1514 + 4(single vlan) + 4(crc) bytes */ +#define RT_VALN_HLEN 4 /* 4(single vlan) bytes */ +#endif + +#define R8127_MAX_TX_QUEUES (2) +#define R8127_MAX_RX_QUEUES_V2 (4) +#define R8127_MAX_RX_QUEUES_V3 (16) +#define R8127_MAX_RX_QUEUES R8127_MAX_RX_QUEUES_V3 +#define R8127_MAX_QUEUES R8127_MAX_RX_QUEUES + +#define OCP_STD_PHY_BASE 0xa400 + +//Channel Wait Count +#define R8127_CHANNEL_WAIT_COUNT (20000) +#define R8127_CHANNEL_WAIT_TIME (1) // 1us +#define R8127_CHANNEL_EXIT_DELAY_TIME (20) //20us + +#ifdef ENABLE_LIB_SUPPORT +#define R8127_MULTI_RX_Q(tp) 0 +#else +#define R8127_MULTI_RX_Q(tp) (tp->num_rx_rings > 1) +#endif + +#define NODE_ADDRESS_SIZE 6 + +#define SHORT_PACKET_PADDING_BUF_SIZE 256 + +#define RTK_MAGIC_DEBUG_VALUE 0x0badbeef + +/* write/read MMIO register */ +#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) +#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) +#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) +#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) +#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) +#define RTL_R32(tp, reg) ((unsigned long) readl(tp->mmio_addr + (reg))) + +#ifndef DMA_64BIT_MASK +#define DMA_64BIT_MASK 0xffffffffffffffffULL +#endif + +#ifndef DMA_32BIT_MASK +#define DMA_32BIT_MASK 0x00000000ffffffffULL +#endif + +#ifndef NETDEV_TX_OK +#define NETDEV_TX_OK 0 /* driver took care of packet */ +#endif + +#ifndef NETDEV_TX_BUSY +#define NETDEV_TX_BUSY 1 /* driver tx path was busy*/ +#endif + +#ifndef NETDEV_TX_LOCKED +#define NETDEV_TX_LOCKED -1t /* driver tx lock was already taken */ +#endif + +#ifndef ADVERTISED_Pause +#define ADVERTISED_Pause (1 << 13) +#endif + +#ifndef ADVERTISED_Asym_Pause +#define ADVERTISED_Asym_Pause (1 << 14) +#endif + +#ifndef ADVERTISE_PAUSE_CAP +#define ADVERTISE_PAUSE_CAP 0x400 +#endif + +#ifndef ADVERTISE_PAUSE_ASYM +#define ADVERTISE_PAUSE_ASYM 0x800 +#endif + +#ifndef MII_CTRL1000 +#define MII_CTRL1000 0x09 +#endif + +#ifndef ADVERTISE_1000FULL +#define ADVERTISE_1000FULL 0x200 +#endif + +#ifndef ADVERTISE_1000HALF +#define ADVERTISE_1000HALF 0x100 +#endif + +#ifndef BIT_ULL +#define BIT_ULL(nr) (1ULL << (nr)) +#endif + +#ifndef ADVERTISED_2500baseX_Full +#define ADVERTISED_2500baseX_Full 0x8000 +#endif +#define RTK_ADVERTISED_5000baseX_Full BIT_ULL(48) +#define RTK_SUPPORTED_5000baseX_Full BIT_ULL(48) + +#define RTK_ADVERTISE_2500FULL 0x80 +#define RTK_ADVERTISE_5000FULL 0x100 +#define RTK_ADVERTISE_10000FULL 0x1000 +#define RTK_LPA_ADVERTISE_2500FULL 0x20 +#define RTK_LPA_ADVERTISE_5000FULL 0x40 +#define RTK_LPA_ADVERTISE_10000FULL 0x800 + +#define RTK_EEE_ADVERTISE_2500FULL BIT(0) +#define RTK_EEE_ADVERTISE_5000FULL BIT(1) +#define RTK_LPA_EEE_ADVERTISE_2500FULL BIT(0) +#define RTK_LPA_EEE_ADVERTISE_5000FULL BIT(1) + +/* Tx NO CLOSE */ +#define MAX_TX_NO_CLOSE_DESC_PTR_V2 0x10000 +#define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V2 0xFFFF +#define MAX_TX_NO_CLOSE_DESC_PTR_V3 0x100000000 +#define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V3 0xFFFFFFFF +#define MAX_TX_NO_CLOSE_DESC_PTR_V4 0x80000000 +#define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V4 0x7FFFFFFF +#define TX_NO_CLOSE_SW_PTR_MASK_V2 0x1FFFF + +#ifndef ETH_MIN_MTU +#define ETH_MIN_MTU 68 +#endif + +#define D0_SPEED_UP_SPEED_DISABLE 0 +#define D0_SPEED_UP_SPEED_1000 1 +#define D0_SPEED_UP_SPEED_2500 2 +#define D0_SPEED_UP_SPEED_5000 3 +#define D0_SPEED_UP_SPEED_10000 4 + +#define RTL8127_MAC_MCU_PAGE_SIZE 256 //256 words + +#ifndef WRITE_ONCE +#define WRITE_ONCE(var, val) (*((volatile typeof(val) *)(&(var))) = (val)) +#endif +#ifndef READ_ONCE +#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) +#endif + +#ifndef SPEED_5000 +#define SPEED_5000 5000 +#endif + +#ifndef SPEED_10000 +#define SPEED_10000 10000 +#endif + +#define R8127_LINK_STATE_OFF 0 +#define R8127_LINK_STATE_ON 1 +#define R8127_LINK_STATE_UNKNOWN 2 + +/*****************************************************************************/ + +//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27)) || \ + ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3)))) +/* copied from linux kernel 2.6.20 include/linux/netdev.h */ +#define NETDEV_ALIGN 32 +#define NETDEV_ALIGN_CONST (NETDEV_ALIGN - 1) + +static inline void *netdev_priv(struct net_device *dev) +{ + return (char *)dev + ((sizeof(struct net_device) + + NETDEV_ALIGN_CONST) + & ~NETDEV_ALIGN_CONST); +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) + +/*****************************************************************************/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) +#define RTLDEV tp +#else +#define RTLDEV dev +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) +/*****************************************************************************/ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) +typedef struct net_device *napi_ptr; +typedef int *napi_budget; + +#define napi dev +#define RTL_NAPI_CONFIG(ndev, priv, function, weig) ndev->poll=function; \ + ndev->weight=weig; +#define RTL_NAPI_QUOTA(budget, ndev) min(*budget, ndev->quota) +#define RTL_GET_PRIV(stuct_ptr, priv_struct) netdev_priv(stuct_ptr) +#define RTL_GET_NETDEV(priv_ptr) +#define RTL_RX_QUOTA(budget) *budget +#define RTL_NAPI_QUOTA_UPDATE(ndev, work_done, budget) *budget -= work_done; \ + ndev->quota -= work_done; +#define RTL_NETIF_RX_COMPLETE(dev, napi, work_done) netif_rx_complete(dev) +#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(dev) +#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(dev) +#define RTL_NAPI_RETURN_VALUE work_done >= work_to_do +#define RTL_NAPI_ENABLE(dev, napi) netif_poll_enable(dev) +#define RTL_NAPI_DISABLE(dev, napi) netif_poll_disable(dev) +#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) +#else +typedef struct napi_struct *napi_ptr; +typedef int napi_budget; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0) +#define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add_weight(ndev, &priv->napi, function, weight) +#else +#define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add(ndev, &priv->napi, function, weight) +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0) +#define RTL_NAPI_QUOTA(budget, ndev) min(budget, budget) +#define RTL_GET_PRIV(stuct_ptr, priv_struct) container_of(stuct_ptr, priv_struct, stuct_ptr) +#define RTL_GET_NETDEV(priv_ptr) struct net_device *dev = priv_ptr->dev; +#define RTL_RX_QUOTA(budget) budget +#define RTL_NAPI_QUOTA_UPDATE(ndev, work_done, budget) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) +#define RTL_NETIF_RX_COMPLETE(dev, napi, work_done) netif_rx_complete(dev, napi) +#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(dev, napi) +#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(dev, napi) +#endif +#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,29) +#define RTL_NETIF_RX_COMPLETE(dev, napi, work_done) netif_rx_complete(napi) +#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(napi) +#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(napi) +#endif +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0) +#define RTL_NETIF_RX_COMPLETE(dev, napi, work_done) napi_complete_done(napi, work_done) +#else +#define RTL_NETIF_RX_COMPLETE(dev, napi, work_done) napi_complete(napi) +#endif +#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) napi_schedule_prep(napi) +#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __napi_schedule(napi) +#endif +#define RTL_NAPI_RETURN_VALUE work_done +#define RTL_NAPI_ENABLE(dev, napi) napi_enable(napi) +#define RTL_NAPI_DISABLE(dev, napi) napi_disable(napi) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) +#define RTL_NAPI_DEL(priv) +#else +#define RTL_NAPI_DEL(priv) netif_napi_del(&priv->napi) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) + +/*****************************************************************************/ +#ifdef CONFIG_R8127_NAPI +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0) +#define RTL_NAPI_CONSUME_SKB_ANY(skb, budget) napi_consume_skb(skb, budget) +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) +#define RTL_NAPI_CONSUME_SKB_ANY(skb, budget) dev_consume_skb_any(skb); +#else +#define RTL_NAPI_CONSUME_SKB_ANY(skb, budget) dev_kfree_skb_any(skb); +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0) +#else //CONFIG_R8127_NAPI +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) +#define RTL_NAPI_CONSUME_SKB_ANY(skb, budget) dev_consume_skb_any(skb); +#else +#define RTL_NAPI_CONSUME_SKB_ANY(skb, budget) dev_kfree_skb_any(skb); +#endif +#endif //CONFIG_R8127_NAPI + +/*****************************************************************************/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) +#ifdef __CHECKER__ +#define __iomem __attribute__((noderef, address_space(2))) +extern void __chk_io_ptr(void __iomem *); +#define __bitwise __attribute__((bitwise)) +#else +#define __iomem +#define __chk_io_ptr(x) (void)0 +#define __bitwise +#endif +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) + +/*****************************************************************************/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) +#ifdef __CHECKER__ +#define __force __attribute__((force)) +#else +#define __force +#endif +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) + +#ifndef module_param +#define module_param(v,t,p) MODULE_PARM(v, "i"); +#endif + +#ifndef PCI_DEVICE +#define PCI_DEVICE(vend,dev) \ + .vendor = (vend), .device = (dev), \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID +#endif + +/*****************************************************************************/ +/* 2.5.28 => 2.4.23 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28)) + +static inline void _kc_synchronize_irq(void) +{ + synchronize_irq(); +} +#undef synchronize_irq +#define synchronize_irq(X) _kc_synchronize_irq() + +#include +#define work_struct tq_struct +#undef INIT_WORK +#define INIT_WORK(a,b,c) INIT_TQUEUE(a,(void (*)(void *))b,c) +#undef container_of +#define container_of list_entry +#define schedule_work schedule_task +#define flush_scheduled_work flush_scheduled_tasks +#endif /* 2.5.28 => 2.4.17 */ + +/*****************************************************************************/ +/* 2.6.4 => 2.6.0 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4)) +#define MODULE_VERSION(_version) MODULE_INFO(version, _version) +#endif /* 2.6.4 => 2.6.0 */ +/*****************************************************************************/ +/* 2.6.0 => 2.5.28 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) +#define MODULE_INFO(version, _version) +#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT +#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1 +#endif + +#define pci_set_consistent_dma_mask(dev,mask) 1 + +#undef dev_put +#define dev_put(dev) __dev_put(dev) + +#ifndef skb_fill_page_desc +#define skb_fill_page_desc _kc_skb_fill_page_desc +extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size); +#endif + +#ifndef pci_dma_mapping_error +#define pci_dma_mapping_error _kc_pci_dma_mapping_error +static inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr) +{ + return dma_addr == 0; +} +#endif + +#undef ALIGN +#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1)) + +#endif /* 2.6.0 => 2.5.28 */ + +/*****************************************************************************/ +/* 2.4.22 => 2.4.17 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22)) +#define pci_name(x) ((x)->slot_name) +#endif /* 2.4.22 => 2.4.17 */ + +/*****************************************************************************/ +/* 2.6.5 => 2.6.0 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)) +#define pci_dma_sync_single_for_cpu pci_dma_sync_single +#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu +#endif /* 2.6.5 => 2.6.0 */ + +/*****************************************************************************/ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +/* + * initialize a work-struct's func and data pointers: + */ +#define PREPARE_WORK(_work, _func, _data) \ + do { \ + (_work)->func = _func; \ + (_work)->data = _data; \ + } while (0) + +#endif +/*****************************************************************************/ +/* 2.6.4 => 2.6.0 */ +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) && \ + LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22)) || \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4))) +#define ETHTOOL_OPS_COMPAT +#endif /* 2.6.4 => 2.6.0 */ + +/*****************************************************************************/ +/* Installations with ethtool version without eeprom, adapter id, or statistics + * support */ + +#ifndef ETH_GSTRING_LEN +#define ETH_GSTRING_LEN 32 +#endif + +#ifndef ETHTOOL_GSTATS +#define ETHTOOL_GSTATS 0x1d +#undef ethtool_drvinfo +#define ethtool_drvinfo k_ethtool_drvinfo +struct k_ethtool_drvinfo { + u32 cmd; + char driver[32]; + char version[32]; + char fw_version[32]; + char bus_info[32]; + char reserved1[32]; + char reserved2[16]; + u32 n_stats; + u32 testinfo_len; + u32 eedump_len; + u32 regdump_len; +}; + +struct ethtool_stats { + u32 cmd; + u32 n_stats; + u64 data[0]; +}; +#endif /* ETHTOOL_GSTATS */ + +#ifndef ETHTOOL_PHYS_ID +#define ETHTOOL_PHYS_ID 0x1c +#endif /* ETHTOOL_PHYS_ID */ + +#ifndef ETHTOOL_GSTRINGS +#define ETHTOOL_GSTRINGS 0x1b +enum ethtool_stringset { + ETH_SS_TEST = 0, + ETH_SS_STATS, +}; +struct ethtool_gstrings { + u32 cmd; /* ETHTOOL_GSTRINGS */ + u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/ + u32 len; /* number of strings in the string set */ + u8 data[0]; +}; +#endif /* ETHTOOL_GSTRINGS */ + +#ifndef ETHTOOL_TEST +#define ETHTOOL_TEST 0x1a +enum ethtool_test_flags { + ETH_TEST_FL_OFFLINE = (1 << 0), + ETH_TEST_FL_FAILED = (1 << 1), +}; +struct ethtool_test { + u32 cmd; + u32 flags; + u32 reserved; + u32 len; + u64 data[0]; +}; +#endif /* ETHTOOL_TEST */ + +#ifndef ETHTOOL_GEEPROM +#define ETHTOOL_GEEPROM 0xb +#undef ETHTOOL_GREGS +struct ethtool_eeprom { + u32 cmd; + u32 magic; + u32 offset; + u32 len; + u8 data[0]; +}; + +struct ethtool_value { + u32 cmd; + u32 data; +}; +#endif /* ETHTOOL_GEEPROM */ + +#ifndef ETHTOOL_GLINK +#define ETHTOOL_GLINK 0xa +#endif /* ETHTOOL_GLINK */ + +#ifndef ETHTOOL_GREGS +#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */ +#define ethtool_regs _kc_ethtool_regs +/* for passing big chunks of data */ +struct _kc_ethtool_regs { + u32 cmd; + u32 version; /* driver-specific, indicates different chips/revs */ + u32 len; /* bytes */ + u8 data[0]; +}; +#endif /* ETHTOOL_GREGS */ + +#ifndef ETHTOOL_GMSGLVL +#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */ +#endif +#ifndef ETHTOOL_SMSGLVL +#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */ +#endif +#ifndef ETHTOOL_NWAY_RST +#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */ +#endif +#ifndef ETHTOOL_GLINK +#define ETHTOOL_GLINK 0x0000000a /* Get link status */ +#endif +#ifndef ETHTOOL_GEEPROM +#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */ +#endif +#ifndef ETHTOOL_SEEPROM +#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */ +#endif +#ifndef ETHTOOL_GCOALESCE +#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */ +/* for configuring coalescing parameters of chip */ +#define ethtool_coalesce _kc_ethtool_coalesce +struct _kc_ethtool_coalesce { + u32 cmd; /* ETHTOOL_{G,S}COALESCE */ + + /* How many usecs to delay an RX interrupt after + * a packet arrives. If 0, only rx_max_coalesced_frames + * is used. + */ + u32 rx_coalesce_usecs; + + /* How many packets to delay an RX interrupt after + * a packet arrives. If 0, only rx_coalesce_usecs is + * used. It is illegal to set both usecs and max frames + * to zero as this would cause RX interrupts to never be + * generated. + */ + u32 rx_max_coalesced_frames; + + /* Same as above two parameters, except that these values + * apply while an IRQ is being serviced by the host. Not + * all cards support this feature and the values are ignored + * in that case. + */ + u32 rx_coalesce_usecs_irq; + u32 rx_max_coalesced_frames_irq; + + /* How many usecs to delay a TX interrupt after + * a packet is sent. If 0, only tx_max_coalesced_frames + * is used. + */ + u32 tx_coalesce_usecs; + + /* How many packets to delay a TX interrupt after + * a packet is sent. If 0, only tx_coalesce_usecs is + * used. It is illegal to set both usecs and max frames + * to zero as this would cause TX interrupts to never be + * generated. + */ + u32 tx_max_coalesced_frames; + + /* Same as above two parameters, except that these values + * apply while an IRQ is being serviced by the host. Not + * all cards support this feature and the values are ignored + * in that case. + */ + u32 tx_coalesce_usecs_irq; + u32 tx_max_coalesced_frames_irq; + + /* How many usecs to delay in-memory statistics + * block updates. Some drivers do not have an in-memory + * statistic block, and in such cases this value is ignored. + * This value must not be zero. + */ + u32 stats_block_coalesce_usecs; + + /* Adaptive RX/TX coalescing is an algorithm implemented by + * some drivers to improve latency under low packet rates and + * improve throughput under high packet rates. Some drivers + * only implement one of RX or TX adaptive coalescing. Anything + * not implemented by the driver causes these values to be + * silently ignored. + */ + u32 use_adaptive_rx_coalesce; + u32 use_adaptive_tx_coalesce; + + /* When the packet rate (measured in packets per second) + * is below pkt_rate_low, the {rx,tx}_*_low parameters are + * used. + */ + u32 pkt_rate_low; + u32 rx_coalesce_usecs_low; + u32 rx_max_coalesced_frames_low; + u32 tx_coalesce_usecs_low; + u32 tx_max_coalesced_frames_low; + + /* When the packet rate is below pkt_rate_high but above + * pkt_rate_low (both measured in packets per second) the + * normal {rx,tx}_* coalescing parameters are used. + */ + + /* When the packet rate is (measured in packets per second) + * is above pkt_rate_high, the {rx,tx}_*_high parameters are + * used. + */ + u32 pkt_rate_high; + u32 rx_coalesce_usecs_high; + u32 rx_max_coalesced_frames_high; + u32 tx_coalesce_usecs_high; + u32 tx_max_coalesced_frames_high; + + /* How often to do adaptive coalescing packet rate sampling, + * measured in seconds. Must not be zero. + */ + u32 rate_sample_interval; +}; +#endif /* ETHTOOL_GCOALESCE */ + +#ifndef ETHTOOL_SCOALESCE +#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */ +#endif +#ifndef ETHTOOL_GRINGPARAM +#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */ +/* for configuring RX/TX ring parameters */ +#define ethtool_ringparam _kc_ethtool_ringparam +struct _kc_ethtool_ringparam { + u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */ + + /* Read only attributes. These indicate the maximum number + * of pending RX/TX ring entries the driver will allow the + * user to set. + */ + u32 rx_max_pending; + u32 rx_mini_max_pending; + u32 rx_jumbo_max_pending; + u32 tx_max_pending; + + /* Values changeable by the user. The valid values are + * in the range 1 to the "*_max_pending" counterpart above. + */ + u32 rx_pending; + u32 rx_mini_pending; + u32 rx_jumbo_pending; + u32 tx_pending; +}; +#endif /* ETHTOOL_GRINGPARAM */ + +#ifndef ETHTOOL_SRINGPARAM +#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */ +#endif +#ifndef ETHTOOL_GPAUSEPARAM +#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */ +/* for configuring link flow control parameters */ +#define ethtool_pauseparam _kc_ethtool_pauseparam +struct _kc_ethtool_pauseparam { + u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */ + + /* If the link is being auto-negotiated (via ethtool_cmd.autoneg + * being true) the user may set 'autonet' here non-zero to have the + * pause parameters be auto-negotiated too. In such a case, the + * {rx,tx}_pause values below determine what capabilities are + * advertised. + * + * If 'autoneg' is zero or the link is not being auto-negotiated, + * then {rx,tx}_pause force the driver to use/not-use pause + * flow control. + */ + u32 autoneg; + u32 rx_pause; + u32 tx_pause; +}; +#endif /* ETHTOOL_GPAUSEPARAM */ + +#ifndef ETHTOOL_SPAUSEPARAM +#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */ +#endif +#ifndef ETHTOOL_GRXCSUM +#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_SRXCSUM +#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_GTXCSUM +#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_STXCSUM +#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_GSG +#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable +* (ethtool_value) */ +#endif +#ifndef ETHTOOL_SSG +#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable +* (ethtool_value). */ +#endif +#ifndef ETHTOOL_TEST +#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */ +#endif +#ifndef ETHTOOL_GSTRINGS +#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */ +#endif +#ifndef ETHTOOL_PHYS_ID +#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */ +#endif +#ifndef ETHTOOL_GSTATS +#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */ +#endif +#ifndef ETHTOOL_GTSO +#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */ +#endif +#ifndef ETHTOOL_STSO +#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */ +#endif + +#ifndef ETHTOOL_BUSINFO_LEN +#define ETHTOOL_BUSINFO_LEN 32 +#endif + +/*****************************************************************************/ + +enum RTL8127_registers { + MAC0 = 0x00, /* Ethernet hardware address. */ + MAC4 = 0x04, + MAR0 = 0x08, /* Multicast filter. */ + CounterAddrLow = 0x10, + CounterAddrHigh = 0x14, + CustomLED = 0x18, + TxDescStartAddrLow = 0x20, + TxDescStartAddrHigh = 0x24, + TxHDescStartAddrLow = 0x28, + TxHDescStartAddrHigh = 0x2c, + FLASH = 0x30, + INT_CFG0_8125 = 0x34, + ERSR = 0x36, + ChipCmd = 0x37, + TxPoll = 0x38, + IntrMask = 0x3C, + IntrStatus = 0x3E, + TxConfig = 0x40, + RxConfig = 0x44, + TCTR = 0x48, + Cfg9346 = 0x50, + Config0 = 0x51, + Config1 = 0x52, + Config2 = 0x53, + Config3 = 0x54, + Config4 = 0x55, + Config5 = 0x56, + TDFNR = 0x57, + TimeInt0 = 0x58, + TimeInt1 = 0x5C, + PHYAR = 0x60, + CSIDR = 0x64, + CSIAR = 0x68, + PHYstatus = 0x6C, + MACDBG = 0x6D, + GPIO = 0x6E, + PMCH = 0x6F, + ERIDR = 0x70, + ERIAR = 0x74, + INT_CFG1_8125 = 0x7A, + EPHY_RXER_NUM = 0x7C, + EPHYAR = 0x80, + TimeInt2 = 0x8C, + OCPDR = 0xB0, + MACOCP = 0xB0, + OCPAR = 0xB4, + SecMAC0 = 0xB4, + SecMAC4 = 0xB8, + PHYOCP = 0xB8, + DBG_reg = 0xD1, + TwiCmdReg = 0xD2, + MCUCmd_reg = 0xD3, + RxMaxSize = 0xDA, + EFUSEAR = 0xDC, + CPlusCmd = 0xE0, + IntrMitigate = 0xE2, + RxDescAddrLow = 0xE4, + RxDescAddrHigh = 0xE8, + MTPS = 0xEC, + FuncEvent = 0xF0, + PPSW = 0xF2, + FuncEventMask = 0xF4, + TimeInt3 = 0xF4, + FuncPresetState = 0xF8, + CMAC_IBCR0 = 0xF8, + CMAC_IBCR2 = 0xF9, + CMAC_IBIMR0 = 0xFA, + CMAC_IBISR0 = 0xFB, + FuncForceEvent = 0xFC, + //8125 + IMR0_8125 = 0x38, + ISR0_8125 = 0x3C, + TPPOLL_8125 = 0x90, + IMR1_8125 = 0x800, + ISR1_8125 = 0x802, + IMR2_8125 = 0x804, + ISR2_8125 = 0x806, + IMR3_8125 = 0x808, + ISR3_8125 = 0x80A, + BACKUP_ADDR0_8125 = 0x19E0, + BACKUP_ADDR1_8125 = 0X19E4, + TCTR0_8125 = 0x0048, + TCTR1_8125 = 0x004C, + TCTR2_8125 = 0x0088, + TCTR3_8125 = 0x001C, + TIMER_INT0_8125 = 0x0058, + TIMER_INT1_8125 = 0x005C, + TIMER_INT2_8125 = 0x008C, + TIMER_INT3_8125 = 0x00F4, + INT_MITI_V2_0_RX = 0x0A00, + INT_MITI_V2_0_TX = 0x0A02, + INT_MITI_V2_1_RX = 0x0A08, + INT_MITI_V2_1_TX = 0x0A0A, + IMR_V2_CLEAR_REG_8125 = 0x0D00, + ISR_V2_8125 = 0x0D04, + IMR_V2_SET_REG_8125 = 0x0D0C, + TDU_STA_8125 = 0x0D08, + RDU_STA_8125 = 0x0D0A, + IMR_V4_L2_CLEAR_REG_8125 = 0x0D10, + IMR_V4_L2_SET_REG_8125 = 0x0D18, + ISR_V4_L2_8125 = 0x0D14, + SW_TAIL_PTR0_8125BP = 0x0D30, + SW_TAIL_PTR1_8125BP = 0x0D38, + HW_CLO_PTR0_8125BP = 0x0D34, + HW_CLO_PTR1_8125BP = 0x0D3C, + DOUBLE_VLAN_CONFIG = 0x1000, + TX_NEW_CTRL = 0x203E, + TNPDS_Q1_LOW_8125 = 0x2100, + PLA_TXQ0_IDLE_CREDIT = 0x2500, + PLA_TXQ1_IDLE_CREDIT = 0x2504, + SW_TAIL_PTR0_8125 = 0x2800, + HW_CLO_PTR0_8125 = 0x2802, + SW_TAIL_PTR0_8126 = 0x2800, + HW_CLO_PTR0_8126 = 0x2800, + RDSAR_Q1_LOW_8125 = 0x4000, + RSS_CTRL_8125 = 0x4500, + Q_NUM_CTRL_8125 = 0x4800, + RSS_KEY_8125 = 0x4600, + RSS_INDIRECTION_TBL_8125_V2 = 0x4700, + EEE_TXIDLE_TIMER_8125 = 0x6048, + PTP_CTRL_8125 = 0x6800, + PTP_STATUS_8125 = 0x6802, + PTP_ISR_8125 = 0x6804, + PTP_IMR_8125 = 0x6805, + PTP_TIME_CORRECT_CMD_8125 = 0x6806, + PTP_SOFT_CONFIG_Time_NS_8125 = 0x6808, + PTP_SOFT_CONFIG_Time_S_8125 = 0x680C, + PTP_SOFT_CONFIG_Time_Sign = 0x6812, + PTP_LOCAL_Time_SUB_NS_8125 = 0x6814, + PTP_LOCAL_Time_NS_8125 = 0x6818, + PTP_LOCAL_Time_S_8125 = 0x681C, + PTP_Time_SHIFTER_S_8125 = 0x6856, + PPS_RISE_TIME_NS_8125 = 0x68A0, + PPS_RISE_TIME_S_8125 = 0x68A4, + PTP_EGRESS_TIME_BASE_NS_8125 = 0XCF20, + PTP_EGRESS_TIME_BASE_S_8125 = 0XCF24, + PTP_CTL = 0xE400, + PTP_INER = 0xE402, + PTP_INSR = 0xE404, + PTP_SYNCE_CTL = 0xE406, + PTP_GEN_CFG = 0xE408, + PTP_CLK_CFG_8126 = 0xE410, + PTP_CFG_NS_LO_8126 = 0xE412, + PTP_CFG_NS_HI_8126 = 0xE414, + PTP_CFG_S_LO_8126 = 0xE416, + PTP_CFG_S_MI_8126 = 0xE418, + PTP_CFG_S_HI_8126 = 0xE41A, + PTP_TAI_CFG = 0xE420, + PTP_TAI_TS_S_LO = 0xE42A, + PTP_TAI_TS_S_HI = 0xE42C, + PTP_TRX_TS_STA = 0xE430, + PTP_TRX_TS_NS_LO = 0xE446, + PTP_TRX_TS_NS_HI = 0xE448, + PTP_TRX_TS_S_LO = 0xE44A, + PTP_TRX_TS_S_MI = 0xE44C, + PTP_TRX_TS_S_HI = 0xE44E, + + //TCAM + TCAM_NOTVALID_ADDR = 0xA000, + TCAM_VALID_ADDR = 0xA800, + TCAM_MAC_ADDR = 448, + TCAM_VLAN_TAG = 496, + //TCAM V2 + TCAM_NOTVALID_ADDR_V2 = 0xA000, + TCAM_VALID_ADDR_V2 = 0xB000, + TCAM_MAC_ADDR_V2 = 0x00, + TCAM_VLAN_TAG_V2 = 0x03, +}; + +enum RTL8127_register_content { + /* InterruptStatusBits */ + SYSErr = 0x8000, + PCSTimeout = 0x4000, + SWInt = 0x0100, + TxDescUnavail = 0x0080, + RxFIFOOver = 0x0040, + LinkChg = 0x0020, + RxDescUnavail = 0x0010, + TxErr = 0x0008, + TxOK = 0x0004, + RxErr = 0x0002, + RxOK = 0x0001, + RxDU1 = 0x0002, + RxOK1 = 0x0001, + + /* RxStatusDesc */ + RxRWT = (1 << 22), + RxRES = (1 << 21), + RxRUNT = (1 << 20), + RxCRC = (1 << 19), + + RxRWT_V3 = (1 << 18), + RxRES_V3 = (1 << 20), + RxRUNT_V3 = (1 << 19), + RxCRC_V3 = (1 << 17), + + RxRES_V4 = (1 << 22), + RxRUNT_V4 = (1 << 21), + RxCRC_V4 = (1 << 20), + + /* ChipCmdBits */ + StopReq = 0x80, + CmdReset = 0x10, + CmdRxEnb = 0x08, + CmdTxEnb = 0x04, + RxBufEmpty = 0x01, + + /* Cfg9346Bits */ + Cfg9346_EEM_MASK = 0xC0, + Cfg9346_Lock = 0x00, + Cfg9346_Unlock = 0xC0, + Cfg9346_EEDO = (1 << 0), + Cfg9346_EEDI = (1 << 1), + Cfg9346_EESK = (1 << 2), + Cfg9346_EECS = (1 << 3), + Cfg9346_EEM0 = (1 << 6), + Cfg9346_EEM1 = (1 << 7), + + /* rx_mode_bits */ + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0x08, + AcceptMulticast = 0x04, + AcceptMyPhys = 0x02, + AcceptAllPhys = 0x01, + AcceppVlanPhys = 0x8000, + + /* Transmit Priority Polling*/ + HPQ = 0x80, + NPQ = 0x40, + FSWInt = 0x01, + + /* RxConfigBits */ + Reserved2_shift = 13, + RxCfgDMAShift = 8, + EnableRxDescV3 = (1 << 24), + EnableRxDescV4_1 = (1 << 24), + EnableOuterVlan = (1 << 23), + EnableInnerVlan = (1 << 22), + RxCfg_128_int_en = (1 << 15), + RxCfg_fet_multi_en = (1 << 14), + RxCfg_half_refetch = (1 << 13), + RxCfg_pause_slot_en = (1 << 11), + RxCfg_9356SEL = (1 << 6), + EnableRxDescV4_0 = (1 << 1), //not in rcr + + /* TxConfigBits */ + TxInterFrameGapShift = 24, + TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ + TxMACLoopBack = (1 << 17), /* MAC loopback */ + + /* Config1 register */ + LEDS1 = (1 << 7), + LEDS0 = (1 << 6), + Speed_down = (1 << 4), + MEMMAP = (1 << 3), + IOMAP = (1 << 2), + VPD = (1 << 1), + PMEnable = (1 << 0), /* Power Management Enable */ + + /* Config2 register */ + PMSTS_En = (1 << 5), + + /* Config3 register */ + Isolate_en = (1 << 12), /* Isolate enable */ + MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ + LinkUp = (1 << 4), /* This bit is reserved in RTL8125B.*/ + /* Wake up when the cable connection is re-established */ + ECRCEN = (1 << 3), /* This bit is reserved in RTL8125B*/ + Jumbo_En0 = (1 << 2), /* This bit is reserved in RTL8125B*/ + RDY_TO_L23 = (1 << 1), /* This bit is reserved in RTL8125B*/ + Beacon_en = (1 << 0), /* This bit is reserved in RTL8125B*/ + + /* Config4 register */ + Jumbo_En1 = (1 << 1), /* This bit is reserved in RTL8125B*/ + + /* Config5 register */ + BWF = (1 << 6), /* Accept Broadcast wakeup frame */ + MWF = (1 << 5), /* Accept Multicast wakeup frame */ + UWF = (1 << 4), /* Accept Unicast wakeup frame */ + LanWake = (1 << 1), /* LanWake enable/disable */ + PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ + + /* CPlusCmd */ + EnableBist = (1 << 15), + Macdbgo_oe = (1 << 14), + Normal_mode = (1 << 13), + Force_halfdup = (1 << 12), + Force_rxflow_en = (1 << 11), + Force_txflow_en = (1 << 10), + Cxpl_dbg_sel = (1 << 9),//This bit is reserved in RTL8125B + ASF = (1 << 8),//This bit is reserved in RTL8125C + PktCntrDisable = (1 << 7), + RxVlan = (1 << 6), + RxChkSum = (1 << 5), + Macdbgo_sel = 0x001C, + INTT_0 = 0x0000, + INTT_1 = 0x0001, + INTT_2 = 0x0002, + INTT_3 = 0x0003, + + /* rtl8127_PHYstatus */ + PowerSaveStatus = 0x80, + _1000bpsL = 0x80000, + _10000bpsF = 0x4000, + _10000bpsL = 0x2000, + _5000bpsF = 0x1000, + _5000bpsL = 0x800, + _2500bpsF = 0x400, + _2500bpsL = 0x200, + TxFlowCtrl = 0x40, + RxFlowCtrl = 0x20, + _1000bpsF = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LinkStatus = 0x02, + FullDup = 0x01, + + /* DBG_reg */ + Fix_Nak_1 = (1 << 4), + Fix_Nak_2 = (1 << 3), + DBGPIN_E2 = (1 << 0), + + /* ResetCounterCommand */ + CounterReset = 0x1, + /* DumpCounterCommand */ + CounterDump = 0x8, + + /* PHY access */ + PHYAR_Flag = 0x80000000, + PHYAR_Write = 0x80000000, + PHYAR_Read = 0x00000000, + PHYAR_Reg_Mask = 0x1f, + PHYAR_Reg_shift = 16, + PHYAR_Data_Mask = 0xffff, + + /* EPHY access */ + EPHYAR_Flag = 0x80000000, + EPHYAR_Write = 0x80000000, + EPHYAR_Read = 0x00000000, + EPHYAR_Reg_Mask = 0x3f, + EPHYAR_Reg_Mask_v2 = 0x7f, + EPHYAR_Reg_shift = 16, + EPHYAR_Data_Mask = 0xffff, + EPHYAR_EXT_ADDR = 0x0ffe, + + /* CSI access */ + CSIAR_Flag = 0x80000000, + CSIAR_Write = 0x80000000, + CSIAR_Read = 0x00000000, + CSIAR_ByteEn = 0x0f, + CSIAR_ByteEn_shift = 12, + CSIAR_Addr_Mask = 0x0fff, + + /* ERI access */ + ERIAR_Flag = 0x80000000, + ERIAR_Write = 0x80000000, + ERIAR_Read = 0x00000000, + ERIAR_Addr_Align = 4, /* ERI access register address must be 4 byte alignment */ + ERIAR_ExGMAC = 0, + ERIAR_MSIX = 1, + ERIAR_ASF = 2, + ERIAR_OOB = 2, + ERIAR_Type_shift = 16, + ERIAR_ByteEn = 0x0f, + ERIAR_ByteEn_shift = 12, + + /* OCP GPHY access */ + OCPDR_Write = 0x80000000, + OCPDR_Read = 0x00000000, + OCPDR_Reg_Mask = 0xFF, + OCPDR_Data_Mask = 0xFFFF, + OCPDR_GPHY_Reg_shift = 16, + OCPAR_Flag = 0x80000000, + OCPAR_GPHY_Write = 0x8000F060, + OCPAR_GPHY_Read = 0x0000F060, + OCPR_Write = 0x80000000, + OCPR_Read = 0x00000000, + OCPR_Addr_Reg_shift = 16, + OCPR_Flag = 0x80000000, + OCP_STD_PHY_BASE_PAGE = 0x0A40, + + /* MCU Command */ + Now_is_oob = (1 << 7), + Txfifo_empty = (1 << 5), + Rxfifo_empty = (1 << 4), + + /* E-FUSE access */ + EFUSE_WRITE = 0x80000000, + EFUSE_WRITE_OK = 0x00000000, + EFUSE_READ = 0x00000000, + EFUSE_READ_OK = 0x80000000, + EFUSE_WRITE_V3 = 0x40000000, + EFUSE_WRITE_OK_V3 = 0x00000000, + EFUSE_READ_V3 = 0x80000000, + EFUSE_READ_OK_V3 = 0x00000000, + EFUSE_Reg_Mask = 0x03FF, + EFUSE_Reg_Shift = 8, + EFUSE_Check_Cnt = 300, + EFUSE_READ_FAIL = 0xFF, + EFUSE_Data_Mask = 0x000000FF, + + /* GPIO */ + GPIO_en = (1 << 0), + + /* PTP */ + PTP_ISR_TOK = (1 << 1), + PTP_ISR_TER = (1 << 2), + PTP_EXEC_CMD = (1 << 7), + PTP_ADJUST_TIME_NS_NEGATIVE = (1 << 30), + PTP_ADJUST_TIME_S_NEGATIVE = (1ULL << 48), + PTP_SOFT_CONFIG_TIME_NS_NEGATIVE = (1 << 30), + PTP_SOFT_CONFIG_TIME_S_NEGATIVE = (1ULL << 48), + + /* New Interrupt Bits */ + INT_CFG0_ENABLE_8125 = (1 << 0), + INT_CFG0_TIMEOUT0_BYPASS_8125 = (1 << 1), + INT_CFG0_MITIGATION_BYPASS_8125 = (1 << 2), + INT_CFG0_RDU_BYPASS_8126 = (1 << 4), + INT_CFG0_MSIX_ENTRY_NUM_MODE = (1 << 5), + INT_CFG0_AUTO_CLEAR_IMR = (1 << 5), + INT_CFG0_AVOID_MISS_INTR = (1 << 6), + ISRIMR_V2_ROK_Q0 = (1 << 0), + ISRIMR_TOK_Q0 = (1 << 16), + ISRIMR_TOK_Q1 = (1 << 18), + ISRIMR_V2_LINKCHG = (1 << 21), + + ISRIMR_V4_ROK_Q0 = (1 << 0), + ISRIMR_V4_LINKCHG = (1 << 29), + + ISRIMR_V5_ROK_Q0 = (1 << 0), + ISRIMR_V5_TOK_Q0 = (1 << 16), + ISRIMR_V5_TOK_Q1 = (1 << 17), + ISRIMR_V5_LINKCHG = (1 << 18), + + ISRIMR_V6_ROK_Q0 = (1 << 0), + ISRIMR_V6_TOK_Q0 = (1 << 8), + ISRIMR_V6_TOK_Q1 = (1 << 9), + ISRIMR_V6_LINKCHG = (1 << 29), + + /* Magic Number */ + RTL8127_MAGIC_NUMBER = 0x0badbadbadbadbadull, +}; + +enum _DescStatusBit { + DescOwn = (1 << 31), /* Descriptor is owned by NIC */ + RingEnd = (1 << 30), /* End of descriptor ring */ + FirstFrag = (1 << 29), /* First segment of a packet */ + LastFrag = (1 << 28), /* Final segment of a packet */ + + DescOwn_V3 = (DescOwn), /* Descriptor is owned by NIC */ + RingEnd_V3 = (RingEnd), /* End of descriptor ring */ + FirstFrag_V3 = (1 << 25), /* First segment of a packet */ + LastFrag_V3 = (1 << 24), /* Final segment of a packet */ + + DescOwn_V4 = (DescOwn), /* Descriptor is owned by NIC */ + RingEnd_V4 = (RingEnd), /* End of descriptor ring */ + FirstFrag_V4 = (FirstFrag), /* First segment of a packet */ + LastFrag_V4 = (LastFrag), /* Final segment of a packet */ + + /* Tx private */ + /*------ offset 0 of tx descriptor ------*/ + LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ + GiantSendv4 = (1 << 26), /* TCP Giant Send Offload V4 (GSOv4) */ + GiantSendv6 = (1 << 25), /* TCP Giant Send Offload V6 (GSOv6) */ + LargeSend_DP = (1 << 16), /* TCP Large Send Offload (TSO) */ + MSSShift = 16, /* MSS value position */ + MSSMask = 0x7FFU, /* MSS value 11 bits */ + TxIPCS = (1 << 18), /* Calculate IP checksum */ + TxUDPCS = (1 << 17), /* Calculate UDP/IP checksum */ + TxTCPCS = (1 << 16), /* Calculate TCP/IP checksum */ + TxVlanTag = (1 << 17), /* Add VLAN tag */ + + /*@@@@@@ offset 4 of tx descriptor => bits for RTL8125 only begin @@@@@@*/ + TxUDPCS_C = (1 << 31), /* Calculate UDP/IP checksum */ + TxTCPCS_C = (1 << 30), /* Calculate TCP/IP checksum */ + TxIPCS_C = (1 << 29), /* Calculate IP checksum */ + TxIPV6F_C = (1 << 28), /* Indicate it is an IPv6 packet */ + /*@@@@@@ offset 4 of tx descriptor => bits for RTL8125 only end @@@@@@*/ + + + /* Rx private */ + /*------ offset 0 of rx descriptor ------*/ + PID1 = (1 << 18), /* Protocol ID bit 1/2 */ + PID0 = (1 << 17), /* Protocol ID bit 2/2 */ + +#define RxProtoUDP (PID1) +#define RxProtoTCP (PID0) +#define RxProtoIP (PID1 | PID0) +#define RxProtoMask RxProtoIP + + RxIPF = (1 << 16), /* IP checksum failed */ + RxUDPF = (1 << 15), /* UDP/IP checksum failed */ + RxTCPF = (1 << 14), /* TCP/IP checksum failed */ + RxVlanTag = (1 << 16), /* VLAN tag available */ + + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxUDPT = (1 << 18), + RxTCPT = (1 << 17), + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only end @@@@@@*/ + + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxV6F = (1 << 31), + RxV4F = (1 << 30), + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only end @@@@@@*/ + + + PID1_v3 = (1 << 29), /* Protocol ID bit 1/2 */ + PID0_v3 = (1 << 28), /* Protocol ID bit 2/2 */ + +#define RxProtoUDP_v3 (PID1_v3) +#define RxProtoTCP_v3 (PID0_v3) +#define RxProtoIP_v3 (PID1_v3 | PID0_v3) +#define RxProtoMask_v3 RxProtoIP_v3 + + RxIPF_v3 = (1 << 26), /* IP checksum failed */ + RxUDPF_v3 = (1 << 25), /* UDP/IP checksum failed */ + RxTCPF_v3 = (1 << 24), /* TCP/IP checksum failed */ + RxSCTPF_v3 = (1 << 23), /* SCTP checksum failed */ + RxVlanTag_v3 = (RxVlanTag), /* VLAN tag available */ + + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxUDPT_v3 = (1 << 29), + RxTCPT_v3 = (1 << 28), + RxSCTP_v3 = (1 << 27), + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only end @@@@@@*/ + + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxV6F_v3 = (RxV6F), + RxV4F_v3 = (RxV4F), + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only end @@@@@@*/ + + RxIPF_v4 = (1 << 17), /* IP checksum failed */ + RxUDPF_v4 = (1 << 16), /* UDP/IP checksum failed */ + RxTCPF_v4 = (1 << 15), /* TCP/IP checksum failed */ + RxSCTPF_v4 = (1 << 19), /* SCTP checksum failed */ + RxVlanTag_v4 = (RxVlanTag), /* VLAN tag available */ + + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxUDPT_v4 = (1 << 19), + RxTCPT_v4 = (1 << 18), + RxSCTP_v4 = (1 << 19), + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only end @@@@@@*/ + + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxV6F_v4 = (RxV6F), + RxV4F_v4 = (RxV4F), + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only end @@@@@@*/ +}; + +enum features { +// RTL_FEATURE_WOL = (1 << 0), + RTL_FEATURE_MSI = (1 << 1), + RTL_FEATURE_MSIX = (1 << 2), +}; + +enum wol_capability { + WOL_DISABLED = 0, + WOL_ENABLED = 1 +}; + +enum bits { + BIT_0 = (1 << 0), + BIT_1 = (1 << 1), + BIT_2 = (1 << 2), + BIT_3 = (1 << 3), + BIT_4 = (1 << 4), + BIT_5 = (1 << 5), + BIT_6 = (1 << 6), + BIT_7 = (1 << 7), + BIT_8 = (1 << 8), + BIT_9 = (1 << 9), + BIT_10 = (1 << 10), + BIT_11 = (1 << 11), + BIT_12 = (1 << 12), + BIT_13 = (1 << 13), + BIT_14 = (1 << 14), + BIT_15 = (1 << 15), + BIT_16 = (1 << 16), + BIT_17 = (1 << 17), + BIT_18 = (1 << 18), + BIT_19 = (1 << 19), + BIT_20 = (1 << 20), + BIT_21 = (1 << 21), + BIT_22 = (1 << 22), + BIT_23 = (1 << 23), + BIT_24 = (1 << 24), + BIT_25 = (1 << 25), + BIT_26 = (1 << 26), + BIT_27 = (1 << 27), + BIT_28 = (1 << 28), + BIT_29 = (1 << 29), + BIT_30 = (1 << 30), + BIT_31 = (1 << 31) +}; + +#define RTL8127_CP_NUM 4 +#define RTL8127_MAX_SUPPORT_CP_LEN 110 + +enum rtl8127_cp_status { + rtl8127_cp_normal = 0, + rtl8127_cp_short, + rtl8127_cp_open, + rtl8127_cp_mismatch, + rtl8127_cp_unknown +}; + +enum efuse { + EFUSE_NOT_SUPPORT = 0, + EFUSE_SUPPORT_V1, + EFUSE_SUPPORT_V2, + EFUSE_SUPPORT_V3, + EFUSE_SUPPORT_V4, +}; +#define RsvdMask 0x3fffc000 +#define RsvdMaskV3 0x3fff8000 +#define RsvdMaskV4 RsvdMaskV3 + +struct TxDesc { + u32 opts1; + u32 opts2; + u64 addr; + u32 reserved0; + u32 reserved1; + u32 reserved2; + u32 reserved3; +}; + +struct RxDesc { + u32 opts1; + u32 opts2; + u64 addr; +}; + +struct RxDescV3 { + union { + struct { + u32 rsv1; + u32 rsv2; + } RxDescDDWord1; + }; + + union { + struct { + u32 RSSResult; + u16 HeaderBufferLen; + u16 HeaderInfo; + } RxDescNormalDDWord2; + + struct { + u32 rsv5; + u32 rsv6; + } RxDescDDWord2; + }; + + union { + u64 addr; + + struct { + u32 TimeStampLow; + u32 TimeStampHigh; + } RxDescTimeStamp; + + struct { + u32 rsv8; + u32 rsv9; + } RxDescDDWord3; + }; + + union { + struct { + u32 opts2; + u32 opts1; + } RxDescNormalDDWord4; + + struct { + u16 TimeStampHHigh; + u16 rsv11; + u32 opts1; + } RxDescPTPDDWord4; + }; +}; + +struct RxDescV4 { + union { + u64 addr; + + struct { + u32 RSSInfo; + u32 RSSResult; + } RxDescNormalDDWord1; + }; + + struct { + u32 opts2; + u32 opts1; + } RxDescNormalDDWord2; +}; + +enum rxdesc_type { + RXDESC_TYPE_NORMAL=0, + RXDESC_TYPE_NEXT, + RXDESC_TYPE_PTP, + RXDESC_TYPE_MAX +}; + +//Rx Desc Type +enum rx_desc_ring_type { + RX_DESC_RING_TYPE_UNKNOWN=0, + RX_DESC_RING_TYPE_1, + RX_DESC_RING_TYPE_2, + RX_DESC_RING_TYPE_3, + RX_DESC_RING_TYPE_4, + RX_DESC_RING_TYPE_MAX +}; + +enum rx_desc_len { + RX_DESC_LEN_TYPE_1 = (sizeof(struct RxDesc)), + RX_DESC_LEN_TYPE_3 = (sizeof(struct RxDescV3)), + RX_DESC_LEN_TYPE_4 = (sizeof(struct RxDescV4)) +}; + +struct ring_info { + struct sk_buff *skb; + u32 len; + unsigned int bytecount; + unsigned short gso_segs; + u8 __pad[sizeof(void *) - sizeof(u32)]; +}; + +struct pci_resource { + u8 cmd; + u8 cls; + u16 io_base_h; + u16 io_base_l; + u16 mem_base_h; + u16 mem_base_l; + u8 ilr; + u16 resv_0x1c_h; + u16 resv_0x1c_l; + u16 resv_0x20_h; + u16 resv_0x20_l; + u16 resv_0x24_h; + u16 resv_0x24_l; + u16 resv_0x2c_h; + u16 resv_0x2c_l; + u32 pci_sn_l; + u32 pci_sn_h; +}; + +enum r8127_flag { + R8127_FLAG_DOWN = 0, + R8127_FLAG_TASK_RESET_PENDING, + R8127_FLAG_TASK_ESD_CHECK_PENDING, + R8127_FLAG_TASK_LINKCHG_CHECK_PENDING, + R8127_FLAG_MAX +}; + +enum r8127_sysfs_flag { + R8127_SYSFS_RTL_ADV = 0, + R8127_SYSFS_FLAG_MAX +}; + +struct rtl8127_tx_ring { + void* priv; + struct net_device *netdev; + u32 index; + u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ + u32 dirty_tx; + u32 num_tx_desc; /* Number of Tx descriptor registers */ + struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ + dma_addr_t TxPhyAddr; + u32 TxDescAllocSize; + struct ring_info tx_skb[MAX_NUM_TX_DESC]; /* Tx data buffers */ + + u32 NextHwDesCloPtr; + u32 BeginHwDesCloPtr; + + u16 hw_clo_ptr_reg; + u16 sw_tail_ptr_reg; + + u16 tdsar_reg; /* Transmit Descriptor Start Address */ +}; + +struct rtl8127_rx_buffer { + struct page *page; + u32 page_offset; + dma_addr_t dma; + void* data; + struct sk_buff *skb; +}; + +struct rtl8127_rx_ring { + void* priv; + struct net_device *netdev; + u32 index; + u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ + u32 dirty_rx; + u32 num_rx_desc; /* Number of Rx descriptor registers */ + struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ + u32 RxDescAllocSize; + u64 RxDescPhyAddr[MAX_NUM_RX_DESC]; /* Rx desc physical address*/ + dma_addr_t RxPhyAddr; +#ifdef ENABLE_PAGE_REUSE + struct rtl8127_rx_buffer rx_buffer[MAX_NUM_RX_DESC]; + u16 rx_offset; +#else + struct sk_buff *Rx_skbuff[MAX_NUM_RX_DESC]; /* Rx data buffers */ +#endif //ENABLE_PAGE_REUSE + + u16 rdsar_reg; /* Receive Descriptor Start Address */ +}; + +struct r8127_napi { +#ifdef CONFIG_R8127_NAPI +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) + struct napi_struct napi; +#endif +#endif + void* priv; + int index; +}; + +struct r8127_irq { + irq_handler_t handler; + unsigned int vector; + u8 requested; + char name[IFNAMSIZ + 10]; +}; + +#pragma pack(1) +struct rtl8127_regs { + //00 + u8 mac_id[6]; + u16 reg_06; + u8 mar[8]; + //10 + u64 dtccr; + u16 ledsel0; + u16 legreg; + u32 tctr3; + //20 + u32 txq0_dsc_st_addr_0; + u32 txq0_dsc_st_addr_2; + u64 reg_28; + //30 + u16 rit; + u16 ritc; + u16 reg_34; + u8 reg_36; + u8 command; + u32 imr0; + u32 isr0; + //40 + u32 tcr; + u32 rcr; + u32 tctr0; + u32 tctr1; + //50 + u8 cr93c46; + u8 config0; + u8 config1; + u8 config2; + u8 config3; + u8 config4; + u8 config5; + u8 tdfnr; + u32 timer_int0; + u32 timer_int1; + //60 + u32 gphy_mdcmdio; + u32 csidr; + u32 csiar; + u16 phy_status; + u8 config6; + u8 pmch; + //70 + u32 eridr; + u32 eriar; + u16 config7; + u16 reg_7a; + u32 ephy_rxerr_cnt; + //80 + u32 ephy_mdcmdio; + u16 ledsel2; + u16 ledsel1; + u32 tctr2; + u32 timer_int2; + //90 + u8 tppoll0; + u8 reg_91; + u16 reg_92; + u16 led_feature; + u16 ledsel3; + u16 eee_led_config; + u16 reg_9a; + u32 reg_9c; + //a0 + u32 reg_a0; + u32 reg_a4; + u32 reg_a8; + u32 reg_ac; + //b0 + u32 patch_dbg; + u32 reg_b4; + u32 gphy_ocp; + u32 reg_bc; + //c0 + u32 reg_c0; + u32 reg_c4; + u32 reg_c8; + u16 otp_cmd; + u16 otp_pg_config; + //d0 + u16 phy_pwr; + u8 twsi_ctrl; + u8 oob_ctrl; + u16 mac_dbgo; + u16 mac_dbg; + u16 reg_d8; + u16 rms; + u32 efuse_data; + //e0 + u16 cplus_cmd; + u16 reg_e2; + u32 rxq0_dsc_st_addr_0; + u32 rxq0_dsc_st_addr_2; + u16 reg_ec; + u16 tx10midle_cnt; + //f0 + u16 misc0; + u16 misc1; + u32 timer_int3; + u32 cmac_ib; + u16 reg_fc; + u16 sw_rst; +}; +#pragma pack() + +struct rtl8127_regs_save { + union { + u8 mac_io[R8127_MAC_REGS_SIZE]; + + struct rtl8127_regs mac_reg; + }; + u16 pcie_phy[R8127_EPHY_REGS_SIZE/2]; + u16 eth_phy[R8127_PHY_REGS_SIZE/2]; + u32 eri_reg[R8127_ERI_REGS_SIZE/4]; + u32 pci_reg[R8127_PCI_REGS_SIZE/4]; + u16 sw_tail_ptr_reg[R8127_MAX_TX_QUEUES]; + u16 hw_clo_ptr_reg[R8127_MAX_TX_QUEUES]; + + //ktime_t begin_ktime; + //ktime_t end_ktime; + //u64 duration_ns; + + u16 sw0_tail_ptr; + u16 next_hwq0_clo_ptr; + u16 sw1_tail_ptr; + u16 next_hwq1_clo_ptr; + + u16 int_miti_rxq0; + u16 int_miti_txq0; + u16 int_miti_rxq1; + u16 int_miti_txq1; + u8 int_config; + u32 imr_new; + u32 isr_new; + + u8 tdu_status; + u16 rdu_status; + + u16 tc_mode; + + u32 txq1_dsc_st_addr_0; + u32 txq1_dsc_st_addr_2; + + u32 pla_tx_q0_idle_credit; + u32 pla_tx_q1_idle_credit; + + u32 rxq1_dsc_st_addr_0; + u32 rxq1_dsc_st_addr_2; + + u32 rss_ctrl; + u8 rss_key[RTL8127_RSS_KEY_SIZE]; + u8 rss_i_table[RTL8127_MAX_INDIRECTION_TABLE_ENTRIES]; + u16 rss_queue_num_sel_r; +}; + +struct rtl8127_counters { + /* legacy */ + u64 tx_packets; + u64 rx_packets; + u64 tx_errors; + u32 rx_errors; + u16 rx_missed; + u16 align_errors; + u32 tx_one_collision; + u32 tx_multi_collision; + u64 rx_unicast; + u64 rx_broadcast; + u32 rx_multicast; + u16 tx_aborted; + u16 tx_underrun; + + /* extended */ + u64 tx_octets; + u64 rx_octets; + u64 rx_multicast64; + u64 tx_unicast64; + u64 tx_broadcast64; + u64 tx_multicast64; + u32 tx_pause_on; + u32 tx_pause_off; + u32 tx_pause_all; + u32 tx_deferred; + u32 tx_late_collision; + u32 tx_all_collision; + u32 tx_aborted32; + u32 align_errors32; + u32 rx_frame_too_long; + u32 rx_runt; + u32 rx_pause_on; + u32 rx_pause_off; + u32 rx_pause_all; + u32 rx_unknown_opcode; + u32 rx_mac_error; + u32 tx_underrun32; + u32 rx_mac_missed; + u32 rx_tcam_dropped; + u32 tdu; + u32 rdu; +}; + +/* Flow Control Settings */ +enum rtl8127_fc_mode { + rtl8127_fc_none = 0, + rtl8127_fc_rx_pause, + rtl8127_fc_tx_pause, + rtl8127_fc_full, + rtl8127_fc_default +}; + +enum rtl8127_state_t { + __RTL8127_TESTING = 0, + __RTL8127_RESETTING, + __RTL8127_DOWN, + __RTL8127_PTP_TX_IN_PROGRESS, +}; + +#define RTL_FLAG_RX_HWTSTAMP_ENABLED BIT_0 + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) +struct ethtool_eee { + __u32 cmd; + __u32 supported; + __u32 advertised; + __u32 lp_advertised; + __u32 eee_active; + __u32 eee_enabled; + __u32 tx_lpi_enabled; + __u32 tx_lpi_timer; + __u32 reserved[2]; +}; +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) */ + +struct rtl8127_private { + void __iomem *mmio_addr; /* memory map physical address */ + struct pci_dev *pci_dev; /* Index of PCI device */ + struct net_device *dev; + struct r8127_napi r8127napi[R8127_MAX_MSIX_VEC]; + struct r8127_irq irq_tbl[R8127_MAX_MSIX_VEC]; + unsigned int irq_nvecs; + unsigned int max_irq_nvecs; + unsigned int min_irq_nvecs; + unsigned int hw_supp_irq_nvecs; + //struct msix_entry msix_entries[R8127_MAX_MSIX_VEC]; + struct net_device_stats stats; /* statistics of net device */ + unsigned long state; + u32 flags; + + u32 msg_enable; + u32 tx_tcp_csum_cmd; + u32 tx_udp_csum_cmd; + u32 tx_ip_csum_cmd; + u32 tx_ipv6_csum_cmd; + int max_jumbo_frame_size; + int chipset; + u32 mcfg; + //u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ + //u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ + //u32 dirty_rx; + //u32 dirty_tx; + //struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ + //struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ + //dma_addr_t TxPhyAddr; + //dma_addr_t RxPhyAddr; + //struct sk_buff *Rx_skbuff[MAX_NUM_RX_DESC]; /* Rx data buffers */ + //struct ring_info tx_skb[MAX_NUM_TX_DESC]; /* Tx data buffers */ + unsigned rx_buf_sz; +#ifdef ENABLE_PAGE_REUSE + unsigned rx_buf_page_order; + unsigned rx_buf_page_size; + u32 page_reuse_fail_cnt; +#endif //ENABLE_PAGE_REUSE + u16 HwSuppNumTxQueues; + u16 HwSuppNumRxQueues; + unsigned int num_tx_rings; + unsigned int num_rx_rings; + struct rtl8127_tx_ring tx_ring[R8127_MAX_TX_QUEUES]; + struct rtl8127_rx_ring rx_ring[R8127_MAX_RX_QUEUES]; +#ifdef ENABLE_LIB_SUPPORT + struct blocking_notifier_head lib_nh; + struct rtl8127_ring lib_tx_ring[R8127_MAX_TX_QUEUES]; + struct rtl8127_ring lib_rx_ring[R8127_MAX_RX_QUEUES]; +#endif + //struct timer_list esd_timer; + //struct timer_list link_timer; + struct pci_resource pci_cfg_space; + unsigned int esd_flag; + unsigned int pci_cfg_is_read; + unsigned int rtl8127_rx_config; + u16 rms; + u16 cp_cmd; + u32 intr_mask; + u32 timer_intr_mask; + u16 isr_reg[R8127_MAX_MSIX_VEC]; + u16 imr_reg[R8127_MAX_MSIX_VEC]; + int phy_auto_nego_reg; + int phy_1000_ctrl_reg; + int phy_2500_ctrl_reg; + u8 org_mac_addr[NODE_ADDRESS_SIZE]; + struct rtl8127_counters *tally_vaddr; + dma_addr_t tally_paddr; + +#ifdef CONFIG_R8127_VLAN + struct vlan_group *vlgrp; +#endif + u8 wol_enabled; + u32 wol_opts; + u8 efuse_ver; + u8 eeprom_type; + u8 autoneg; + u8 duplex; + u32 speed; + u64 advertising; + enum rtl8127_fc_mode fcpause; + u32 HwSuppMaxPhyLinkSpeed; + u16 eeprom_len; + u16 cur_page; + u32 bios_setting; + + int (*set_speed)(struct net_device *, u8 autoneg, u32 speed, u8 duplex, u64 adv); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + void (*get_settings)(struct net_device *, struct ethtool_cmd *); +#else + void (*get_settings)(struct net_device *, struct ethtool_link_ksettings *); +#endif + void (*phy_reset_enable)(struct net_device *); + unsigned int (*phy_reset_pending)(struct net_device *); + unsigned int (*link_ok)(struct net_device *); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + struct work_struct reset_task; + struct work_struct esd_task; + struct work_struct linkchg_task; +#else + struct delayed_work reset_task; + struct delayed_work esd_task; + struct delayed_work linkchg_task; +#endif + DECLARE_BITMAP(task_flags, R8127_FLAG_MAX); + unsigned features; + + u8 org_pci_offset_99; + u8 org_pci_offset_180; + u8 issue_offset_99_event; + + u8 org_pci_offset_80; + u8 org_pci_offset_81; + u8 use_timer_interrupt; + + u32 keep_intr_cnt; + + u8 HwIcVerUnknown; + u8 NotWrRamCodeToMicroP; + u8 NotWrMcuPatchCode; + u8 HwHasWrRamCodeToMicroP; + + u16 sw_ram_code_ver; + u16 hw_ram_code_ver; + + u8 rtk_enable_diag; + + u8 ShortPacketSwChecksum; + + u8 UseSwPaddingShortPkt; + + u8 RequireAdcBiasPatch; + u16 AdcBiasPatchIoffset; + + u8 RequireAdjustUpsTxLinkPulseTiming; + u16 SwrCnt1msIni; + + u8 HwSuppNowIsOobVer; + + u8 RequiredSecLanDonglePatch; + + u8 RequirePhyMdiSwapPatch; + + u32 HwFiberModeVer; + u32 HwFiberStat; + u8 HwSwitchMdiToFiber; + + u16 NicCustLedValue; + + u8 HwSuppMagicPktVer; + + u8 HwSuppLinkChgWakeUpVer; + + u8 HwSuppCheckPhyDisableModeVer; + + u8 random_mac; + + u16 phy_reg_aner; + u16 phy_reg_anlpar; + u16 phy_reg_gbsr; + u16 phy_reg_status_2500; + + u32 HwPcieSNOffset; + + u32 MaxTxDescPtrMask; + u8 HwSuppTxNoCloseVer; + u8 EnableTxNoClose; + + u8 HwSuppIsrVer; + u8 HwCurrIsrVer; + + u8 HwSuppIntMitiVer; + + u8 HwSuppExtendTallyCounterVer; + + u8 check_keep_link_speed; + u8 resume_not_chg_speed; + + u8 HwSuppD0SpeedUpVer; + u8 D0SpeedUpSpeed; + + u8 ring_lib_enabled; + + const char *fw_name; + struct rtl8127_fw *rtl_fw; + u32 ocp_base; + + //Dash+++++++++++++++++ + u8 HwSuppDashVer; + u8 DASH; + u8 dash_printer_enabled; + u8 HwPkgDet; + u8 AllowAccessDashOcp; + void __iomem *mapped_cmac_ioaddr; /* mapped cmac memory map physical address */ + void __iomem *cmac_ioaddr; /* cmac memory map physical address */ + +#ifdef ENABLE_DASH_SUPPORT + u16 AfterRecvFromFwBufLen; + u8 AfterRecvFromFwBuf[RECV_FROM_FW_BUF_SIZE]; + u16 AfterSendToFwBufLen; + u8 AfterSendToFwBuf[SEND_TO_FW_BUF_SIZE]; + u16 SendToFwBufferLen; + u32 SizeOfSendToFwBuffer; + u32 SizeOfSendToFwBufferMemAlloc; + u32 NumOfSendToFwBuffer; + + u8 OobReq; + u8 OobAck; + u32 OobReqComplete; + u32 OobAckComplete; + + u8 RcvFwReqSysOkEvt; + u8 RcvFwDashOkEvt; + u8 SendFwHostOkEvt; + + u8 DashFwDisableRx; + + void *UnalignedSendToFwBufferVa; + void *SendToFwBuffer; + u64 SendToFwBufferPhy; + u8 SendingToFw; + dma_addr_t UnalignedSendToFwBufferPa; + PTX_DASH_SEND_FW_DESC TxDashSendFwDesc; + u64 TxDashSendFwDescPhy; + u8 *UnalignedTxDashSendFwDescVa; + u32 SizeOfTxDashSendFwDescMemAlloc; + u32 SizeOfTxDashSendFwDesc; + u32 NumTxDashSendFwDesc; + u32 CurrNumTxDashSendFwDesc; + u32 LastSendNumTxDashSendFwDesc; + dma_addr_t UnalignedTxDashSendFwDescPa; + + u32 NumRecvFromFwBuffer; + u32 SizeOfRecvFromFwBuffer; + u32 SizeOfRecvFromFwBufferMemAlloc; + void *RecvFromFwBuffer; + u64 RecvFromFwBufferPhy; + + void *UnalignedRecvFromFwBufferVa; + dma_addr_t UnalignedRecvFromFwBufferPa; + PRX_DASH_FROM_FW_DESC RxDashRecvFwDesc; + u64 RxDashRecvFwDescPhy; + u8 *UnalignedRxDashRecvFwDescVa; + u32 SizeOfRxDashRecvFwDescMemAlloc; + u32 SizeOfRxDashRecvFwDesc; + u32 NumRxDashRecvFwDesc; + u32 CurrNumRxDashRecvFwDesc; + dma_addr_t UnalignedRxDashRecvFwDescPa; + u8 DashReqRegValue; + u16 HostReqValue; + + u32 CmacResetIsrCounter; + u8 CmacResetIntr; + u8 CmacResetting; + u8 CmacOobIssueCmacReset; + u32 CmacResetbyFwCnt; + +#if defined(ENABLE_DASH_PRINTER_SUPPORT) + struct completion fw_ack; + struct completion fw_req; + struct completion fw_host_ok; +#endif + //Dash----------------- +#endif //ENABLE_DASH_SUPPORT + + //Realwow++++++++++++++ + u8 HwSuppKCPOffloadVer; + + u8 EnableDhcpTimeoutWake; + u8 EnableTeredoOffload; + u8 EnableKCPOffload; +#ifdef ENABLE_REALWOW_SUPPORT + u32 DhcpTimeout; + MP_KCP_INFO MpKCPInfo; + //Realwow-------------- +#endif //ENABLE_REALWOW_SUPPORT + + struct ethtool_keee eee; + +#ifdef ENABLE_R8127_PROCFS + //Procfs support + struct proc_dir_entry *proc_dir; + struct proc_dir_entry *proc_dir_debug; + struct proc_dir_entry *proc_dir_test; +#endif +#ifdef ENABLE_R8127_SYSFS + //sysfs support + DECLARE_BITMAP(sysfs_flag, R8127_SYSFS_FLAG_MAX); + u32 testmode; +#endif + u8 HwSuppRxDescType; + u8 InitRxDescType; + u16 RxDescLength; //V1 16 Byte V2 32 Bytes + + spinlock_t phy_lock; + + u8 HwSuppPtpVer; + u8 EnablePtp; +#ifdef ENABLE_PTP_SUPPORT + u32 tx_hwtstamp_timeouts; + u32 tx_hwtstamp_skipped; + struct work_struct ptp_tx_work; + struct sk_buff *ptp_tx_skb; + struct hwtstamp_config hwtstamp_config; + unsigned long ptp_tx_start; + struct ptp_clock_info ptp_clock_info; + struct ptp_clock *ptp_clock; + u8 syncE_en; + u8 pps_enable; + struct hrtimer pps_timer; +#endif + + u8 HwSuppRssVer; + u8 EnableRss; + u16 HwSuppIndirTblEntries; +#ifdef ENABLE_RSS_SUPPORT + u32 rss_flags; + /* Receive Side Scaling settings */ + u8 rss_key[RTL8127_RSS_KEY_SIZE]; + u8 rss_indir_tbl[RTL8127_MAX_INDIRECTION_TABLE_ENTRIES]; + u32 rss_options; +#endif + + u8 HwSuppMacMcuVer; + u16 MacMcuPageSize; + u64 hw_mcu_patch_code_ver; + u64 bin_mcu_patch_code_ver; + + u8 HwSuppTcamVer; + + u16 TcamNotValidReg; + u16 TcamValidReg; + u16 TcamMaAddrcOffset; + u16 TcamVlanTagOffset; +}; + +#ifdef ENABLE_LIB_SUPPORT +static inline unsigned int +rtl8127_num_lib_tx_rings(struct rtl8127_private *tp) +{ + int count, i; + + for (count = 0, i = tp->num_tx_rings; i < tp->HwSuppNumTxQueues; i++) + if(tp->lib_tx_ring[i].enabled) + count++; + + return count; +} + +static inline unsigned int +rtl8127_num_lib_rx_rings(struct rtl8127_private *tp) +{ + int count, i; + + for (count = 0, i = tp->num_rx_rings; i < tp->HwSuppNumRxQueues; i++) + if(tp->lib_rx_ring[i].enabled) + count++; + + return count; +} + +#else +static inline unsigned int +rtl8127_num_lib_tx_rings(struct rtl8127_private *tp) +{ + return 0; +} + +static inline unsigned int +rtl8127_num_lib_rx_rings(struct rtl8127_private *tp) +{ + return 0; +} +#endif + +static inline unsigned int +rtl8127_tot_tx_rings(struct rtl8127_private *tp) +{ + return tp->num_tx_rings + rtl8127_num_lib_tx_rings(tp); +} + +static inline unsigned int +rtl8127_tot_rx_rings(struct rtl8127_private *tp) +{ + return tp->num_rx_rings + rtl8127_num_lib_rx_rings(tp); +} + +static inline struct netdev_queue *txring_txq(const struct rtl8127_tx_ring *ring) +{ + return netdev_get_tx_queue(ring->netdev, ring->index); +} + +enum eetype { + EEPROM_TYPE_NONE=0, + EEPROM_TYPE_93C46, + EEPROM_TYPE_93C56, + EEPROM_TWSI +}; + +enum mcfg { + CFG_METHOD_1=1, + CFG_METHOD_2, + CFG_METHOD_DEFAULT, + CFG_METHOD_MAX +}; + +#define LSO_32K 32000 +#define LSO_64K 64000 + +#define NIC_MIN_PHYS_BUF_COUNT (2) +#define NIC_MAX_PHYS_BUF_COUNT_LSO_64K (24) +#define NIC_MAX_PHYS_BUF_COUNT_LSO2 (16*4) + +#define GTTCPHO_SHIFT 18 +#define GTTCPHO_MAX 0x70U +#define GTPKTSIZE_MAX 0x3ffffU +#define TCPHO_SHIFT 18 +#define TCPHO_MAX 0x3ffU +#define LSOPKTSIZE_MAX 0xffffU +#define MSS_MAX 0x07ffu /* MSS value */ + +#define OOB_CMD_RESET 0x00 +#define OOB_CMD_DRIVER_START 0x05 +#define OOB_CMD_DRIVER_STOP 0x06 +#define OOB_CMD_SET_IPMAC 0x41 + +#define WAKEUP_MAGIC_PACKET_NOT_SUPPORT (0) +#define WAKEUP_MAGIC_PACKET_V1 (1) +#define WAKEUP_MAGIC_PACKET_V2 (2) +#define WAKEUP_MAGIC_PACKET_V3 (3) + +//Ram Code Version +#define NIC_RAMCODE_VERSION_CFG_METHOD_1 (0x0015) +#define NIC_RAMCODE_VERSION_CFG_METHOD_2 (0x0015) + +//hwoptimize +#define HW_PATCH_SOC_LAN (BIT_0) +#define HW_PATCH_SAMSUNG_LAN_DONGLE (BIT_2) + +static const u16 other_q_intr_mask = (RxOK1 | RxDU1); + +void rtl8127_mdio_write(struct rtl8127_private *tp, u16 RegAddr, u16 value); +void rtl8127_mdio_prot_write(struct rtl8127_private *tp, u32 RegAddr, u32 value); +void rtl8127_mdio_prot_direct_write_phy_ocp(struct rtl8127_private *tp, u32 RegAddr, u32 value); +u32 rtl8127_mdio_read(struct rtl8127_private *tp, u16 RegAddr); +u32 rtl8127_mdio_prot_read(struct rtl8127_private *tp, u32 RegAddr); +u32 rtl8127_mdio_prot_direct_read_phy_ocp(struct rtl8127_private *tp, u32 RegAddr); +void rtl8127_ephy_write(struct rtl8127_private *tp, int RegAddr, int value); +void rtl8127_mac_ocp_write(struct rtl8127_private *tp, u16 reg_addr, u16 value); +u16 rtl8127_mac_ocp_read(struct rtl8127_private *tp, u16 reg_addr); +void rtl8127_clear_eth_phy_bit(struct rtl8127_private *tp, u8 addr, u16 mask); +void rtl8127_set_eth_phy_bit(struct rtl8127_private *tp, u8 addr, u16 mask); +void rtl8127_ocp_write(struct rtl8127_private *tp, u16 addr, u8 len, u32 data); +void rtl8127_oob_notify(struct rtl8127_private *tp, u8 cmd); +void rtl8127_init_ring_indexes(struct rtl8127_private *tp); +void rtl8127_oob_mutex_lock(struct rtl8127_private *tp); +u32 rtl8127_ocp_read(struct rtl8127_private *tp, u16 addr, u8 len); +u32 rtl8127_ocp_read_with_oob_base_address(struct rtl8127_private *tp, u16 addr, u8 len, u32 base_address); +u32 rtl8127_ocp_write_with_oob_base_address(struct rtl8127_private *tp, u16 addr, u8 len, u32 value, u32 base_address); +u32 rtl8127_eri_read(struct rtl8127_private *tp, int addr, int len, int type); +u32 rtl8127_eri_read_with_oob_base_address(struct rtl8127_private *tp, int addr, int len, int type, u32 base_address); +int rtl8127_eri_write(struct rtl8127_private *tp, int addr, int len, u32 value, int type); +int rtl8127_eri_write_with_oob_base_address(struct rtl8127_private *tp, int addr, int len, u32 value, int type, u32 base_address); +u16 rtl8127_ephy_read(struct rtl8127_private *tp, int RegAddr); +void rtl8127_wait_txrx_fifo_empty(struct net_device *dev); +void rtl8127_enable_now_is_oob(struct rtl8127_private *tp); +void rtl8127_disable_now_is_oob(struct rtl8127_private *tp); +void rtl8127_oob_mutex_unlock(struct rtl8127_private *tp); +void rtl8127_dash2_disable_tx(struct rtl8127_private *tp); +void rtl8127_dash2_enable_tx(struct rtl8127_private *tp); +void rtl8127_dash2_disable_rx(struct rtl8127_private *tp); +void rtl8127_dash2_enable_rx(struct rtl8127_private *tp); +void rtl8127_hw_disable_mac_mcu_bps(struct net_device *dev); +void rtl8127_mark_to_asic(struct rtl8127_private *tp, struct RxDesc *desc, u32 rx_buf_sz); +void rtl8127_mark_as_last_descriptor(struct rtl8127_private *tp, struct RxDesc *desc); + +static inline void +rtl8127_make_unusable_by_asic(struct rtl8127_private *tp, + struct RxDesc *desc) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + ((struct RxDescV3 *)desc)->addr = RTL8127_MAGIC_NUMBER; + ((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts1 &= ~cpu_to_le32(DescOwn | RsvdMaskV3); + break; + case RX_DESC_RING_TYPE_4: + ((struct RxDescV4 *)desc)->addr = RTL8127_MAGIC_NUMBER; + ((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts1 &= ~cpu_to_le32(DescOwn | RsvdMaskV4); + break; + default: + desc->addr = RTL8127_MAGIC_NUMBER; + desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); + break; + } +} + +static inline struct RxDesc* +rtl8127_get_rxdesc(struct rtl8127_private *tp, struct RxDesc *RxDescBase, u32 const cur_rx) +{ + return (struct RxDesc*)((u8*)RxDescBase + (cur_rx * tp->RxDescLength)); +} + +static inline void +rtl8127_disable_hw_interrupt_v2(struct rtl8127_private *tp, + u32 message_id) +{ + RTL_W32(tp, IMR_V2_CLEAR_REG_8125, BIT(message_id)); +} + +static inline void +rtl8127_enable_hw_interrupt_v2(struct rtl8127_private *tp, u32 message_id) +{ + RTL_W32(tp, IMR_V2_SET_REG_8125, BIT(message_id)); +} + +int rtl8127_open(struct net_device *dev); +int rtl8127_close(struct net_device *dev); +void rtl8127_hw_config(struct net_device *dev); +void rtl8127_hw_set_timer_int(struct rtl8127_private *tp, u32 message_id, u8 timer_intmiti_val); +void rtl8127_set_rx_q_num(struct rtl8127_private *tp, unsigned int num_rx_queues); +void rtl8127_set_tx_q_num(struct rtl8127_private *tp, unsigned int num_tx_queues); +void rtl8127_enable_mcu(struct rtl8127_private *tp, bool enable); +void rtl8127_hw_start(struct net_device *dev); +void rtl8127_hw_reset(struct net_device *dev); +void rtl8127_tx_clear(struct rtl8127_private *tp); +void rtl8127_rx_clear(struct rtl8127_private *tp); +int rtl8127_init_ring(struct net_device *dev); +void rtl8127_hw_set_rx_packet_filter(struct net_device *dev); +void rtl8127_enable_hw_linkchg_interrupt(struct rtl8127_private *tp); +int rtl8127_dump_tally_counter(struct rtl8127_private *tp, dma_addr_t paddr); +void rtl8127_enable_napi(struct rtl8127_private *tp); +void _rtl8127_wait_for_quiescence(struct net_device *dev); + +void rtl8127_mdio_direct_write_phy_ocp(struct rtl8127_private *tp, u16 RegAddr,u16 value); +u32 rtl8127_mdio_direct_read_phy_ocp(struct rtl8127_private *tp, u16 RegAddr); +void rtl8127_clear_and_set_eth_phy_ocp_bit(struct rtl8127_private *tp, u16 addr, u16 clearmask, u16 setmask); +void rtl8127_clear_eth_phy_ocp_bit(struct rtl8127_private *tp, u16 addr, u16 mask); +void rtl8127_set_eth_phy_ocp_bit(struct rtl8127_private *tp, u16 addr, u16 mask); + +void rtl8127_clear_mac_ocp_bit(struct rtl8127_private *tp, u16 addr, u16 mask); + +#ifndef ENABLE_LIB_SUPPORT +static inline void rtl8127_lib_reset_prepare(struct rtl8127_private *tp) { } +static inline void rtl8127_lib_reset_complete(struct rtl8127_private *tp) { } +#endif + +#define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0) +#define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) (((_M)->HwHasWrRamCodeToMicroP == TRUE) ? 1 : 0) +#define HW_SUPPORT_D0_SPEED_UP(_M) ((_M)->HwSuppD0SpeedUpVer > 0) +#define HW_SUPPORT_MAC_MCU(_M) ((_M)->HwSuppMacMcuVer > 0) +#define HW_SUPPORT_TCAM(_M) ((_M)->HwSuppTcamVer > 0) + +#define HW_SUPP_PHY_LINK_SPEED_GIGA(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 1000) +#define HW_SUPP_PHY_LINK_SPEED_2500M(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 2500) +#define HW_SUPP_PHY_LINK_SPEED_5000M(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 5000) +#define HW_SUPP_PHY_LINK_SPEED_10000M(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 10000) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) +#define netdev_mc_count(dev) ((dev)->mc_count) +#define netdev_mc_empty(dev) (netdev_mc_count(dev) == 0) +#define netdev_for_each_mc_addr(mclist, dev) \ + for (mclist = dev->mc_list; mclist; mclist = mclist->next) +#endif + +#endif /* __R8127_H */ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/r8127_dash.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/r8127_dash.h @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#ifndef _LINUX_R8127_DASH_H +#define _LINUX_R8127_DASH_H + +#include + +#define SIOCDEVPRIVATE_RTLDASH SIOCDEVPRIVATE+2 + +enum rtl_dash_cmd { + RTL_DASH_ARP_NS_OFFLOAD = 0, + RTL_DASH_SET_OOB_IPMAC, + RTL_DASH_NOTIFY_OOB, + + RTL_DASH_SEND_BUFFER_DATA_TO_DASH_FW, + RTL_DASH_CHECK_SEND_BUFFER_TO_DASH_FW_COMPLETE, + RTL_DASH_GET_RCV_FROM_FW_BUFFER_DATA, + RTL_DASH_OOB_REQ, + RTL_DASH_OOB_ACK, + RTL_DASH_DETACH_OOB_REQ, + RTL_DASH_DETACH_OOB_ACK, + + RTL_FW_SET_IPV4 = 0x10, + RTL_FW_GET_IPV4, + RTL_FW_SET_IPV6, + RTL_FW_GET_IPV6, + RTL_FW_SET_EXT_SNMP, + RTL_FW_GET_EXT_SNMP, + RTL_FW_SET_WAKEUP_PATTERN, + RTL_FW_GET_WAKEUP_PATTERN, + RTL_FW_DEL_WAKEUP_PATTERN, + + RTLT_DASH_COMMAND_INVALID, +}; + +struct rtl_dash_ip_mac { + struct sockaddr ifru_addr; + struct sockaddr ifru_netmask; + struct sockaddr ifru_hwaddr; +}; + +struct rtl_dash_ioctl_struct { + __u32 cmd; + __u32 offset; + __u32 len; + union { + __u32 data; + void *data_buffer; + }; +}; + +struct settings_ipv4 { + __u32 IPv4addr; + __u32 IPv4mask; + __u32 IPv4Gateway; +}; + +struct settings_ipv6 { + __u32 reserved; + __u32 prefixLen; + __u16 IPv6addr[8]; + __u16 IPv6Gateway[8]; +}; + +struct settings_ext_snmp { + __u16 index; + __u16 oid_get_len; + __u8 oid_for_get[24]; + __u8 reserved0[26]; + __u16 value_len; + __u8 value[256]; + __u8 supported; + __u8 reserved1[27]; +}; + +struct wakeup_pattern { + __u8 index; + __u8 valid; + __u8 start; + __u8 length; + __u8 name[36]; + __u8 mask[16]; + __u8 pattern[128]; + __u32 reserved[2]; +}; + +typedef struct _RX_DASH_FROM_FW_DESC { + u16 length; + u8 statusLowByte; + u8 statusHighByte; + u32 resv; + u64 BufferAddress; +} +RX_DASH_FROM_FW_DESC, *PRX_DASH_FROM_FW_DESC; + +typedef struct _TX_DASH_SEND_FW_DESC { + u16 length; + u8 statusLowByte; + u8 statusHighByte; + u32 resv; + u64 BufferAddress; +} +TX_DASH_SEND_FW_DESC, *PTX_DASH_SEND_FW_DESC; + +typedef struct _OSOOBHdr { + u32 len; + u8 type; + u8 flag; + u8 hostReqV; + u8 res; +} +OSOOBHdr, *POSOOBHdr; + +typedef struct _RX_DASH_BUFFER_TYPE_2 { + OSOOBHdr oobhdr; + u8 RxDataBuffer[0]; +} +RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2; + +#define ALIGN_8 (0x7) +#define ALIGN_16 (0xf) +#define ALIGN_32 (0x1f) +#define ALIGN_64 (0x3f) +#define ALIGN_256 (0xff) +#define ALIGN_4096 (0xfff) + +#define OCP_REG_CONFIG0 (0x10) +#define OCP_REG_CONFIG0_REV_F (0xB8) +#define OCP_REG_DASH_POLL (0x30) +#define OCP_REG_HOST_REQ (0x34) +#define OCP_REG_DASH_REQ (0x35) +#define OCP_REG_CR (0x36) +#define OCP_REG_DMEMSTA (0x38) +#define OCP_REG_GPHYAR (0x60) + + +#define OCP_REG_CONFIG0_DASHEN BIT_15 +#define OCP_REG_CONFIG0_OOBRESET BIT_14 +#define OCP_REG_CONFIG0_APRDY BIT_13 +#define OCP_REG_CONFIG0_FIRMWARERDY BIT_12 +#define OCP_REG_CONFIG0_DRIVERRDY BIT_11 +#define OCP_REG_CONFIG0_OOB_WDT BIT_9 +#define OCP_REG_CONFIG0_DRV_WAIT_OOB BIT_8 +#define OCP_REG_CONFIG0_TLSEN BIT_7 + +#define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0) +#define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1) +#define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2) +#define HW_DASH_SUPPORT_TYPE_3(_M) ((_M)->HwSuppDashVer == 3) + +#define RECV_FROM_FW_BUF_SIZE (1520) +#define SEND_TO_FW_BUF_SIZE (1520) + +#define RX_DASH_FROM_FW_OWN BIT_15 +#define TX_DASH_SEND_FW_OWN BIT_15 +#define TX_DASH_SEND_FW_OWN_HIGHBYTE BIT_7 + +#define TXS_CC3_0 (BIT_0|BIT_1|BIT_2|BIT_3) +#define TXS_EXC BIT_4 +#define TXS_LNKF BIT_5 +#define TXS_OWC BIT_6 +#define TXS_TES BIT_7 +#define TXS_UNF BIT_9 +#define TXS_LGSEN BIT_11 +#define TXS_LS BIT_12 +#define TXS_FS BIT_13 +#define TXS_EOR BIT_14 +#define TXS_OWN BIT_15 + +#define TPPool_HRDY 0x20 + +#define HostReqReg (0xC0) +#define SystemMasterDescStartAddrLow (0xF0) +#define SystemMasterDescStartAddrHigh (0xF4) +#define SystemSlaveDescStartAddrLow (0xF8) +#define SystemSlaveDescStartAddrHigh (0xFC) + +//DASH Request Type +#define WSMANREG 0x01 +#define OSPUSHDATA 0x02 + +#define RXS_OWN BIT_15 +#define RXS_EOR BIT_14 +#define RXS_FS BIT_13 +#define RXS_LS BIT_12 + +#define ISRIMR_DP_DASH_OK BIT_15 +#define ISRIMR_DP_HOST_OK BIT_13 +#define ISRIMR_DP_REQSYS_OK BIT_11 + +#define ISRIMR_DASH_INTR_EN BIT_12 +#define ISRIMR_DASH_INTR_CMAC_RESET BIT_15 + +#define ISRIMR_DASH_TYPE2_ROK BIT_0 +#define ISRIMR_DASH_TYPE2_RDU BIT_1 +#define ISRIMR_DASH_TYPE2_TOK BIT_2 +#define ISRIMR_DASH_TYPE2_TDU BIT_3 +#define ISRIMR_DASH_TYPE2_TX_FIFO_FULL BIT_4 +#define ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE BIT_5 +#define ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE BIT_6 + +#define CMAC_OOB_STOP 0x25 +#define CMAC_OOB_INIT 0x26 +#define CMAC_OOB_RESET 0x2a + +#define NO_BASE_ADDRESS 0x00000000 +#define RTL8168FP_OOBMAC_BASE 0xBAF70000 +#define RTL8168FP_CMAC_IOBASE 0xBAF20000 +#define RTL8168FP_KVM_BASE 0xBAF80400 +#define CMAC_SYNC_REG 0x20 +#define CMAC_RXDESC_OFFSET 0x90 //RX: 0x90 - 0x98 +#define CMAC_TXDESC_OFFSET 0x98 //TX: 0x98 - 0x9F + +/* cmac write/read MMIO register */ +#define RTL_CMAC_W8(tp, reg, val8) writeb ((val8), tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_W16(tp, reg, val16) writew ((val16), tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_W32(tp, reg, val32) writel ((val32), tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_R8(tp, reg) readb (tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_R16(tp, reg) readw (tp->cmac_ioaddr + (reg)) +#define RTL_CMAC_R32(tp, reg) ((unsigned long) readl (tp->cmac_ioaddr + (reg))) + +int rtl8127_dash_ioctl(struct net_device *dev, struct ifreq *ifr); +void HandleDashInterrupt(struct net_device *dev); +int AllocateDashShareMemory(struct net_device *dev); +void FreeAllocatedDashShareMemory(struct net_device *dev); +void DashHwInit(struct net_device *dev); + + +#endif /* _LINUX_R8127_DASH_H */ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/r8127_firmware.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/r8127_firmware.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#ifndef _LINUX_R8127_FIRMWARE_H +#define _LINUX_R8127_FIRMWARE_H + +#include +#include + +struct rtl8127_private; +typedef void (*rtl8127_fw_write_t)(struct rtl8127_private *tp, u16 reg, u16 val); +typedef u32 (*rtl8127_fw_read_t)(struct rtl8127_private *tp, u16 reg); + +#define RTL8127_VER_SIZE 32 + +struct rtl8127_fw { + rtl8127_fw_write_t phy_write; + rtl8127_fw_read_t phy_read; + rtl8127_fw_write_t mac_mcu_write; + rtl8127_fw_read_t mac_mcu_read; + const struct firmware *fw; + const char *fw_name; + struct device *dev; + + char version[RTL8127_VER_SIZE]; + + struct rtl8127_fw_phy_action { + __le32 *code; + size_t size; + } phy_action; +}; + +int rtl8127_fw_request_firmware(struct rtl8127_fw *rtl_fw); +void rtl8127_fw_release_firmware(struct rtl8127_fw *rtl_fw); +void rtl8127_fw_write_firmware(struct rtl8127_private *tp, struct rtl8127_fw *rtl_fw); + +#endif /* _LINUX_R8127_FIRMWARE_H */ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/r8127_n.c +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/r8127_n.c @@ -0,0 +1,17752 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +/* + * This driver is modified from r8169.c in Linux kernel 2.6.18 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) +#include +#include +#endif +#include +#include +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) +#include +#endif +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) +#include +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#define dev_printk(A,B,fmt,args...) printk(A fmt,##args) +#else +#include +#include +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31) +#include +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,10) +#include +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,10) */ + +#include +#include + +#include "r8127.h" +#include "rtl_eeprom.h" +#include "rtltool.h" +#include "r8127_firmware.h" + +#ifdef ENABLE_R8127_PROCFS +#include +#include +#endif + +#define FIRMWARE_8127_1 "rtl_nic/rtl8127-1.fw" +#define FIRMWARE_8127_2 "rtl_nic/rtl8127-2.fw" + +static const struct { + const char *name; + const char *fw_name; +} rtl_chip_fw_infos[] = { + /* PCI-E devices. */ + [CFG_METHOD_1] = {"RTL8127", FIRMWARE_8127_1}, + [CFG_METHOD_2] = {"RTL8127", FIRMWARE_8127_2}, + [CFG_METHOD_DEFAULT] = {"Unknown", }, +}; + +#define _R(NAME,MAC,RCR,MASK,JumFrameSz) \ + { .name = NAME, .mcfg = MAC, .RCR_Cfg = RCR, .RxConfigMask = MASK, .jumbo_frame_sz = JumFrameSz } + +static const struct { + const char *name; + u8 mcfg; + u32 RCR_Cfg; + u32 RxConfigMask; /* Clears the bits supported by this chip */ + u32 jumbo_frame_sz; +} rtl_chip_info[] = { + _R("RTL8127", + CFG_METHOD_1, + Rx_Fetch_Number_8 | Rx_Close_Multiple | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_512 << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_9k), + + _R("RTL8127", + CFG_METHOD_2, + Rx_Fetch_Number_8 | Rx_Close_Multiple | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_512 << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_9k), + + _R("Unknown", + CFG_METHOD_DEFAULT, + (RX_DMA_BURST_512 << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_1k) +}; +#undef _R + + +static struct pci_device_id rtl8127_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8127), }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x0E10), }, + {0,}, +}; + +MODULE_DEVICE_TABLE(pci, rtl8127_pci_tbl); + +static int use_dac = 1; +static int timer_count = 0x2600; +static int timer_count_v2 = (0x2600 / 0x200); + +static struct { + u32 msg_enable; +} debug = { -1 }; + +static unsigned int speed_mode = SPEED_10000; +static unsigned int duplex_mode = DUPLEX_FULL; +static unsigned int autoneg_mode = AUTONEG_ENABLE; +#ifdef CONFIG_ASPM +static int aspm = 1; +#else +static int aspm = 0; +#endif +#ifdef ENABLE_S5WOL +static int s5wol = 1; +#else +static int s5wol = 0; +#endif +#ifdef ENABLE_S5_KEEP_CURR_MAC +static int s5_keep_curr_mac = 1; +#else +static int s5_keep_curr_mac = 0; +#endif +#ifdef ENABLE_EEE +static int eee_enable = 1; +#else +static int eee_enable = 0; +#endif +#ifdef CONFIG_SOC_LAN +static ulong hwoptimize = HW_PATCH_SOC_LAN; +#else +static ulong hwoptimize = 0; +#endif +#ifdef ENABLE_S0_MAGIC_PACKET +static int s0_magic_packet = 1; +#else +static int s0_magic_packet = 0; +#endif +#ifdef ENABLE_TX_NO_CLOSE +static int tx_no_close_enable = 1; +#else +static int tx_no_close_enable = 0; +#endif +#ifdef DISABLE_WOL_SUPPORT +static int disable_wol_support = 1; +#else +static int disable_wol_support = 0; +#endif +#ifdef ENABLE_DOUBLE_VLAN +static int enable_double_vlan = 1; +#else +static int enable_double_vlan = 0; +#endif +#ifdef ENABLE_GIGA_LITE +static int eee_giga_lite = 1; +#else +static int eee_giga_lite = 0; +#endif + +MODULE_AUTHOR("Realtek and the Linux r8127 crew "); +MODULE_DESCRIPTION("Realtek r8127 Ethernet controller driver"); + +module_param(speed_mode, uint, 0); +MODULE_PARM_DESC(speed_mode, "force phy operation. Deprecated by ethtool (8)."); + +module_param(duplex_mode, uint, 0); +MODULE_PARM_DESC(duplex_mode, "force phy operation. Deprecated by ethtool (8)."); + +module_param(autoneg_mode, uint, 0); +MODULE_PARM_DESC(autoneg_mode, "force phy operation. Deprecated by ethtool (8)."); + +module_param(aspm, int, 0); +MODULE_PARM_DESC(aspm, "Enable ASPM."); + +module_param(s5wol, int, 0); +MODULE_PARM_DESC(s5wol, "Enable Shutdown Wake On Lan."); + +module_param(s5_keep_curr_mac, int, 0); +MODULE_PARM_DESC(s5_keep_curr_mac, "Enable Shutdown Keep Current MAC Address."); + +module_param(use_dac, int, 0); +MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); + +module_param(timer_count, int, 0); +MODULE_PARM_DESC(timer_count, "Timer Interrupt Interval."); + +module_param(eee_enable, int, 0); +MODULE_PARM_DESC(eee_enable, "Enable Energy Efficient Ethernet."); + +module_param(hwoptimize, ulong, 0); +MODULE_PARM_DESC(hwoptimize, "Enable HW optimization function."); + +module_param(s0_magic_packet, int, 0); +MODULE_PARM_DESC(s0_magic_packet, "Enable S0 Magic Packet."); + +module_param(tx_no_close_enable, int, 0); +MODULE_PARM_DESC(tx_no_close_enable, "Enable TX No Close."); + +module_param(disable_wol_support, int, 0); +MODULE_PARM_DESC(disable_wol_support, "Disable PM support."); + +module_param(enable_double_vlan, int, 0); +MODULE_PARM_DESC(enable_double_vlan, "Enable Double VLAN."); + +module_param(eee_giga_lite, int, 0); +MODULE_PARM_DESC(eee_giga_lite, "Enable Giga Lite."); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) +module_param_named(debug, debug.msg_enable, int, 0); +MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); +#endif//LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + +MODULE_LICENSE("GPL"); +#ifdef ENABLE_USE_FIRMWARE_FILE +MODULE_FIRMWARE(FIRMWARE_8127_1); +MODULE_FIRMWARE(FIRMWARE_8127_2); +#endif + +MODULE_VERSION(RTL8127_VERSION); + +/* +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) +static void rtl8127_esd_timer(unsigned long __opaque); +#else +static void rtl8127_esd_timer(struct timer_list *t); +#endif +*/ +/* +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) +static void rtl8127_link_timer(unsigned long __opaque); +#else +static void rtl8127_link_timer(struct timer_list *t); +#endif +*/ + +static netdev_tx_t rtl8127_start_xmit(struct sk_buff *skb, struct net_device *dev); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +static irqreturn_t rtl8127_interrupt(int irq, void *dev_instance, struct pt_regs *regs); +#else +static irqreturn_t rtl8127_interrupt(int irq, void *dev_instance); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +static irqreturn_t rtl8127_interrupt_msix(int irq, void *dev_instance, struct pt_regs *regs); +#else +static irqreturn_t rtl8127_interrupt_msix(int irq, void *dev_instance); +#endif +static void rtl8127_set_rx_mode(struct net_device *dev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) +static void rtl8127_tx_timeout(struct net_device *dev, unsigned int txqueue); +#else +static void rtl8127_tx_timeout(struct net_device *dev); +#endif +static int rtl8127_rx_interrupt(struct net_device *, struct rtl8127_private *, struct rtl8127_rx_ring *, napi_budget); +static int rtl8127_tx_interrupt(struct rtl8127_tx_ring *ring, int budget); +static int rtl8127_tx_interrupt_with_vector(struct rtl8127_private *tp, const int message_id, int budget); +static void rtl8127_wait_for_quiescence(struct net_device *dev); +static int rtl8127_change_mtu(struct net_device *dev, int new_mtu); +static void rtl8127_down(struct net_device *dev); + +static int rtl8127_set_mac_address(struct net_device *dev, void *p); +static void rtl8127_rar_set(struct rtl8127_private *tp, const u8 *addr); +static void rtl8127_desc_addr_fill(struct rtl8127_private *); +static void rtl8127_tx_desc_init(struct rtl8127_private *tp); +static void rtl8127_rx_desc_init(struct rtl8127_private *tp); + +static u16 rtl8127_get_hw_phy_mcu_code_ver(struct rtl8127_private *tp); +static void rtl8127_phy_power_up(struct net_device *dev); +static void rtl8127_phy_power_down(struct net_device *dev); +static int rtl8127_set_speed(struct net_device *dev, u8 autoneg, u32 speed, u8 duplex, u64 adv); +static bool rtl8127_set_phy_mcu_patch_request(struct rtl8127_private *tp); +static bool rtl8127_clear_phy_mcu_patch_request(struct rtl8127_private *tp); + +#ifdef CONFIG_R8127_NAPI +static int rtl8127_poll(napi_ptr napi, napi_budget budget); +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8127_reset_task(void *_data); +static void rtl8127_esd_task(void *_data); +static void rtl8127_linkchg_task(void *_data); +#else +static void rtl8127_reset_task(struct work_struct *work); +static void rtl8127_esd_task(struct work_struct *work); +static void rtl8127_linkchg_task(struct work_struct *work); +#endif +static void rtl8127_schedule_reset_work(struct rtl8127_private *tp); +static void rtl8127_schedule_esd_work(struct rtl8127_private *tp); +static void rtl8127_schedule_linkchg_work(struct rtl8127_private *tp); +static void rtl8127_init_all_schedule_work(struct rtl8127_private *tp); +static void rtl8127_cancel_all_schedule_work(struct rtl8127_private *tp); + +static inline struct device *tp_to_dev(struct rtl8127_private *tp) +{ + return &tp->pci_dev->dev; +} + +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) && \ + LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,00))) +void ethtool_convert_legacy_u32_to_link_mode(unsigned long *dst, + u32 legacy_u32) +{ + bitmap_zero(dst, __ETHTOOL_LINK_MODE_MASK_NBITS); + dst[0] = legacy_u32; +} + +bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32, + const unsigned long *src) +{ + bool retval = true; + + /* TODO: following test will soon always be true */ + if (__ETHTOOL_LINK_MODE_MASK_NBITS > 32) { + __ETHTOOL_DECLARE_LINK_MODE_MASK(ext); + + bitmap_zero(ext, __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_fill(ext, 32); + bitmap_complement(ext, ext, __ETHTOOL_LINK_MODE_MASK_NBITS); + if (bitmap_intersects(ext, src, + __ETHTOOL_LINK_MODE_MASK_NBITS)) { + /* src mask goes beyond bit 31 */ + retval = false; + } + } + *legacy_u32 = src[0]; + return retval; +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) + +#ifndef LPA_1000FULL +#define LPA_1000FULL 0x0800 +#endif + +#ifndef LPA_1000HALF +#define LPA_1000HALF 0x0400 +#endif + +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0) +static inline void eth_hw_addr_random(struct net_device *dev) +{ + random_ether_addr(dev->dev_addr); +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#undef ethtool_ops +#define ethtool_ops _kc_ethtool_ops + +struct _kc_ethtool_ops { + int (*get_settings)(struct net_device *, struct ethtool_cmd *); + int (*set_settings)(struct net_device *, struct ethtool_cmd *); + void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *); + int (*get_regs_len)(struct net_device *); + void (*get_regs)(struct net_device *, struct ethtool_regs *, void *); + void (*get_wol)(struct net_device *, struct ethtool_wolinfo *); + int (*set_wol)(struct net_device *, struct ethtool_wolinfo *); + u32 (*get_msglevel)(struct net_device *); + void (*set_msglevel)(struct net_device *, u32); + int (*nway_reset)(struct net_device *); + u32 (*get_link)(struct net_device *); + int (*get_eeprom_len)(struct net_device *); + int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); + int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *); + int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *); + int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *); + void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *); + int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *); + void (*get_pauseparam)(struct net_device *, + struct ethtool_pauseparam*); + int (*set_pauseparam)(struct net_device *, + struct ethtool_pauseparam*); + u32 (*get_rx_csum)(struct net_device *); + int (*set_rx_csum)(struct net_device *, u32); + u32 (*get_tx_csum)(struct net_device *); + int (*set_tx_csum)(struct net_device *, u32); + u32 (*get_sg)(struct net_device *); + int (*set_sg)(struct net_device *, u32); + u32 (*get_tso)(struct net_device *); + int (*set_tso)(struct net_device *, u32); + int (*self_test_count)(struct net_device *); + void (*self_test)(struct net_device *, struct ethtool_test *, u64 *); + void (*get_strings)(struct net_device *, u32 stringset, u8 *); + int (*phys_id)(struct net_device *, u32); + int (*get_stats_count)(struct net_device *); + void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, + u64 *); +} *ethtool_ops = NULL; + +#undef SET_ETHTOOL_OPS +#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops)) + +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) +#ifndef SET_ETHTOOL_OPS +#define SET_ETHTOOL_OPS(netdev,ops) \ + ((netdev)->ethtool_ops = (ops)) +#endif //SET_ETHTOOL_OPS +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) + +//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) +#ifndef netif_msg_init +#define netif_msg_init _kc_netif_msg_init +/* copied from linux kernel 2.6.20 include/linux/netdevice.h */ +static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits) +{ + /* use default */ + if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) + return default_msg_enable_bits; + if (debug_value == 0) /* no output */ + return 0; + /* set low N bits */ + return (1 << debug_value) - 1; +} + +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) +static inline void eth_copy_and_sum (struct sk_buff *dest, + const unsigned char *src, + int len, int base) +{ + skb_copy_to_linear_data(dest, src, len); +} +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) +/* copied from linux kernel 2.6.20 /include/linux/time.h */ +/* Parameters used to convert the timespec values: */ +#define MSEC_PER_SEC 1000L + +/* copied from linux kernel 2.6.20 /include/linux/jiffies.h */ +/* + * Change timeval to jiffies, trying to avoid the + * most obvious overflows.. + * + * And some not so obvious. + * + * Note that we don't want to return MAX_LONG, because + * for various timeout reasons we often end up having + * to wait "jiffies+1" in order to guarantee that we wait + * at _least_ "jiffies" - so "jiffies+1" had better still + * be positive. + */ +#define MAX_JIFFY_OFFSET ((~0UL >> 1)-1) + +/* + * Convert jiffies to milliseconds and back. + * + * Avoid unnecessary multiplications/divisions in the + * two most common HZ cases: + */ +static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j) +{ +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (MSEC_PER_SEC / HZ) * j; +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) + return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC); +#else + return (j * MSEC_PER_SEC) / HZ; +#endif +} + +static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m) +{ + if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET)) + return MAX_JIFFY_OFFSET; +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ); +#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC) + return m * (HZ / MSEC_PER_SEC); +#else + return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC; +#endif +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + +/* copied from linux kernel 2.6.12.6 /include/linux/pm.h */ +typedef int __bitwise pci_power_t; + +/* copied from linux kernel 2.6.12.6 /include/linux/pci.h */ +typedef u32 __bitwise pm_message_t; + +#define PCI_D0 ((pci_power_t __force) 0) +#define PCI_D1 ((pci_power_t __force) 1) +#define PCI_D2 ((pci_power_t __force) 2) +#define PCI_D3hot ((pci_power_t __force) 3) +#define PCI_D3cold ((pci_power_t __force) 4) +#define PCI_POWER_ERROR ((pci_power_t __force) -1) + +/* copied from linux kernel 2.6.12.6 /drivers/pci/pci.c */ +/** + * pci_choose_state - Choose the power state of a PCI device + * @dev: PCI device to be suspended + * @state: target sleep state for the whole system. This is the value + * that is passed to suspend() function. + * + * Returns PCI power state suitable for given device and given system + * message. + */ + +pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) +{ + if (!pci_find_capability(dev, PCI_CAP_ID_PM)) + return PCI_D0; + + switch (state) { + case 0: + return PCI_D0; + case 3: + return PCI_D3hot; + default: + printk("They asked me for state %d\n", state); +// BUG(); + } + return PCI_D0; +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) +/** + * msleep_interruptible - sleep waiting for waitqueue interruptions + * @msecs: Time in milliseconds to sleep for + */ +#define msleep_interruptible _kc_msleep_interruptible +unsigned long _kc_msleep_interruptible(unsigned int msecs) +{ + unsigned long timeout = _kc_msecs_to_jiffies(msecs); + + while (timeout && !signal_pending(current)) { + set_current_state(TASK_INTERRUPTIBLE); + timeout = schedule_timeout(timeout); + } + return _kc_jiffies_to_msecs(timeout); +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) +/* copied from linux kernel 2.6.20 include/linux/sched.h */ +#ifndef __sched +#define __sched __attribute__((__section__(".sched.text"))) +#endif + +/* copied from linux kernel 2.6.20 kernel/timer.c */ +signed long __sched schedule_timeout_uninterruptible(signed long timeout) +{ + __set_current_state(TASK_UNINTERRUPTIBLE); + return schedule_timeout(timeout); +} + +/* copied from linux kernel 2.6.20 include/linux/mii.h */ +#undef if_mii +#define if_mii _kc_if_mii +static inline struct mii_ioctl_data *if_mii(struct ifreq *rq) +{ + return (struct mii_ioctl_data *) &rq->ifr_ifru; +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) + +static u32 rtl8127_read_thermal_sensor(struct rtl8127_private *tp) +{ + u16 ts_digout; + + ts_digout = rtl8127_mdio_direct_read_phy_ocp(tp, 0xBD84); + ts_digout &= 0x3ff; + + return ts_digout; +} + +int rtl8127_dump_tally_counter(struct rtl8127_private *tp, dma_addr_t paddr) +{ + u32 cmd; + u32 WaitCnt; + int retval = -1; + + RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); + cmd = (u64)paddr & DMA_BIT_MASK(32); + RTL_W32(tp, CounterAddrLow, cmd); + RTL_W32(tp, CounterAddrLow, cmd | CounterDump); + + WaitCnt = 0; + while (RTL_R32(tp, CounterAddrLow) & CounterDump) { + udelay(10); + + WaitCnt++; + if (WaitCnt > 20) + break; + } + + if (WaitCnt <= 20) + retval = 0; + + return retval; +} + +static u32 +rtl8127_get_hw_clo_ptr(struct rtl8127_tx_ring *ring) +{ + struct rtl8127_private *tp = ring->priv; + + switch (tp->HwSuppTxNoCloseVer) { + case 3: + return RTL_R16(tp, ring->hw_clo_ptr_reg); + case 4: + case 5: + case 6: + return RTL_R32(tp, ring->hw_clo_ptr_reg); + default: +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + WARN_ON(1); +#endif + return 0; + } +} + +static u32 +rtl8127_get_sw_tail_ptr(struct rtl8127_tx_ring *ring) +{ + struct rtl8127_private *tp = ring->priv; + + switch (tp->HwSuppTxNoCloseVer) { + case 3: + return RTL_R16(tp, ring->sw_tail_ptr_reg); + case 4: + case 5: + case 6: + return RTL_R32(tp, ring->sw_tail_ptr_reg); + default: +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + WARN_ON(1); +#endif + return 0; + } +} + +static u32 +rtl8127_get_phy_status(struct rtl8127_private *tp) +{ + return RTL_R32(tp, PHYstatus); +} + +static bool +rtl8127_sysfs_testmode_on(struct rtl8127_private *tp) +{ +#ifdef ENABLE_R8127_SYSFS + return !!tp->testmode; +#else + return 1; +#endif +} + +static u32 rtl8127_convert_link_speed(u32 status) +{ + u32 speed = SPEED_UNKNOWN; + + if (status & LinkStatus) { + if (status & _10000bpsF) + speed = SPEED_10000; + else if (status & (_5000bpsF | _10000bpsL)) + speed = SPEED_5000; + else if (status & (_2500bpsF | _5000bpsL)) + speed = SPEED_2500; + else if (status & (_1000bpsF | _2500bpsL | _1000bpsL)) + speed = SPEED_1000; + else if (status & _100bps) + speed = SPEED_100; + else if (status & _10bps) + speed = SPEED_10; + } + + return speed; +} + +static void rtl8127_mdi_swap(struct rtl8127_private *tp) +{ + int i; + u16 reg, val, mdi_reverse; + u16 tps_p0, tps_p1, tps_p2, tps_p3, tps_p3_p0; + + switch (tp->mcfg) { + default: + return; + }; + + tps_p3_p0 = rtl8127_mac_ocp_read(tp, 0xD440) & 0xF000; + tps_p3 = !!(tps_p3_p0 & BIT_15); + tps_p2 = !!(tps_p3_p0 & BIT_14); + tps_p1 = !!(tps_p3_p0 & BIT_13); + tps_p0 = !!(tps_p3_p0 & BIT_12); + mdi_reverse = rtl8127_mac_ocp_read(tp, 0xD442); + + if ((mdi_reverse & BIT_5) && tps_p3_p0 == 0xA000) + return; + + if (!(mdi_reverse & BIT_5)) + val = tps_p0 << 8 | + tps_p1 << 9 | + tps_p2 << 10 | + tps_p3 << 11; + else + val = tps_p3 << 8 | + tps_p2 << 9 | + tps_p1 << 10 | + tps_p0 << 11; + + for (i=8; i<12; i++) { + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, reg); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + BIT(i), + val & BIT(i)); + } +} + +static int rtl8127_vcd_test(struct rtl8127_private *tp) +{ + u16 val; + u32 wait_cnt; + int ret = -1; + + rtl8127_mdi_swap(tp); + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA422, BIT(0)); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA422, 0x00F0); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA422, BIT(0)); + + wait_cnt = 0; + do { + mdelay(1); + val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA422); + wait_cnt++; + } while (!(val & BIT_15) && (wait_cnt < 5000)); + + if (wait_cnt == 5000) + goto exit; + + ret = 0; + +exit: + return ret; +} + +static void rtl8127_get_cp_len(struct rtl8127_private *tp, + int cp_len[RTL8127_CP_NUM]) +{ + int i; + u32 status; + int tmp_cp_len; + + status = rtl8127_get_phy_status(tp); + if (status & LinkStatus) { + if (status & _10bps) { + tmp_cp_len = -1; + } else if (status & (_100bps | _1000bpsF)) { + tmp_cp_len = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA880);; + } else if (status & (_10000bpsF | _10000bpsL | _5000bpsF | + _5000bpsL | _2500bpsF | _2500bpsL)) { + tmp_cp_len = rtl8127_mdio_direct_read_phy_ocp(tp, 0xAC2E);; + tmp_cp_len >>= 5; + } else + tmp_cp_len = 0; + } else + tmp_cp_len = 0; + + if (tmp_cp_len > 0) + tmp_cp_len &= 0xff; + for (i=0; i RTL8127_MAX_SUPPORT_CP_LEN) + cp_len[i] = RTL8127_MAX_SUPPORT_CP_LEN; + + return; +} + +static int __rtl8127_get_cp_status(u16 val) +{ + switch (val) { + case 0x0060: + return rtl8127_cp_normal; + case 0x0048: + case 0x0042: + return rtl8127_cp_open; + case 0x0050: + case 0x0044: + return rtl8127_cp_short; + default: + return rtl8127_cp_normal; + } +} + +static int _rtl8127_get_cp_status(struct rtl8127_private *tp, u8 pair_num) +{ + u16 val; + int cp_status = rtl8127_cp_unknown; + + if (pair_num > 3) + goto exit; + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8026 + 4 * pair_num); + val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA438); + + cp_status = __rtl8127_get_cp_status(val); + +exit: + return cp_status; +} + +static const char * rtl8127_get_cp_status_string(int cp_status) +{ + switch(cp_status) { + case rtl8127_cp_normal: + return "normal "; + case rtl8127_cp_short: + return "short "; + case rtl8127_cp_open: + return "open "; + case rtl8127_cp_mismatch: + return "mismatch"; + default: + return "unknown "; + } +} + +static u16 rtl8127_get_cp_pp(struct rtl8127_private *tp, u8 pair_num) +{ + u16 pp = 0; + + if (pair_num > 3) + goto exit; + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8028 + 4 * pair_num); + pp = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA438); + + pp &= 0x3fff; + pp /= 80; + +exit: + return pp; +} + +static void rtl8127_get_cp_status(struct rtl8127_private *tp, + int cp_status[RTL8127_CP_NUM], + bool poe_mode) +{ + u32 status; + int i; + + status = rtl8127_get_phy_status(tp); + if (status & LinkStatus && !(status & (_10bps | _100bps))) { + for (i=0; i= KERNEL_VERSION(3,10,0) +static int proc_get_driver_variable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct rtl8127_private *tp = netdev_priv(dev); + + seq_puts(m, "\nDump Driver Variable\n"); + + rtnl_lock(); + + seq_puts(m, "Variable\tValue\n----------\t-----\n"); + seq_printf(m, "MODULENAME\t%s\n", MODULENAME); + seq_printf(m, "driver version\t%s\n", RTL8127_VERSION); + seq_printf(m, "mcfg\t%d\n", tp->mcfg); + seq_printf(m, "chipset\t%d\n", tp->chipset); + seq_printf(m, "chipset_name\t%s\n", rtl_chip_info[tp->chipset].name); + seq_printf(m, "mtu\t%d\n", dev->mtu); + seq_printf(m, "NUM_RX_DESC\t0x%x\n", tp->rx_ring[0].num_rx_desc); + seq_printf(m, "cur_rx0\t0x%x\n", tp->rx_ring[0].cur_rx); + seq_printf(m, "dirty_rx0\t0x%x\n", tp->rx_ring[0].dirty_rx); + seq_printf(m, "cur_rx1\t0x%x\n", tp->rx_ring[1].cur_rx); + seq_printf(m, "dirty_rx1\t0x%x\n", tp->rx_ring[1].dirty_rx); + seq_printf(m, "cur_rx2\t0x%x\n", tp->rx_ring[2].cur_rx); + seq_printf(m, "dirty_rx2\t0x%x\n", tp->rx_ring[2].dirty_rx); + seq_printf(m, "cur_rx3\t0x%x\n", tp->rx_ring[3].cur_rx); + seq_printf(m, "dirty_rx3\t0x%x\n", tp->rx_ring[3].dirty_rx); + seq_printf(m, "NUM_TX_DESC\t0x%x\n", tp->tx_ring[0].num_tx_desc); + seq_printf(m, "cur_tx0\t0x%x\n", tp->tx_ring[0].cur_tx); + seq_printf(m, "dirty_tx0\t0x%x\n", tp->tx_ring[0].dirty_tx); + seq_printf(m, "cur_tx1\t0x%x\n", tp->tx_ring[1].cur_tx); + seq_printf(m, "dirty_tx1\t0x%x\n", tp->tx_ring[1].dirty_tx); + seq_printf(m, "rx_buf_sz\t0x%x\n", tp->rx_buf_sz); +#ifdef ENABLE_PAGE_REUSE + seq_printf(m, "rx_buf_page_order\t0x%x\n", tp->rx_buf_page_order); + seq_printf(m, "rx_buf_page_size\t0x%x\n", tp->rx_buf_page_size); + seq_printf(m, "page_reuse_fail_cnt\t0x%x\n", tp->page_reuse_fail_cnt); +#endif //ENABLE_PAGE_REUSE + seq_printf(m, "esd_flag\t0x%x\n", tp->esd_flag); + seq_printf(m, "pci_cfg_is_read\t0x%x\n", tp->pci_cfg_is_read); + seq_printf(m, "rtl8127_rx_config\t0x%x\n", tp->rtl8127_rx_config); + seq_printf(m, "cp_cmd\t0x%x\n", tp->cp_cmd); + seq_printf(m, "intr_mask\t0x%x\n", tp->intr_mask); + seq_printf(m, "timer_intr_mask\t0x%x\n", tp->timer_intr_mask); + seq_printf(m, "wol_enabled\t0x%x\n", tp->wol_enabled); + seq_printf(m, "wol_opts\t0x%x\n", tp->wol_opts); + seq_printf(m, "efuse_ver\t0x%x\n", tp->efuse_ver); + seq_printf(m, "eeprom_type\t0x%x\n", tp->eeprom_type); + seq_printf(m, "autoneg\t0x%x\n", tp->autoneg); + seq_printf(m, "duplex\t0x%x\n", tp->duplex); + seq_printf(m, "speed\t%d\n", tp->speed); + seq_printf(m, "advertising\t0x%llx\n", tp->advertising); + seq_printf(m, "eeprom_len\t0x%x\n", tp->eeprom_len); + seq_printf(m, "cur_page\t0x%x\n", tp->cur_page); + seq_printf(m, "features\t0x%x\n", tp->features); + seq_printf(m, "org_pci_offset_99\t0x%x\n", tp->org_pci_offset_99); + seq_printf(m, "org_pci_offset_180\t0x%x\n", tp->org_pci_offset_180); + seq_printf(m, "issue_offset_99_event\t0x%x\n", tp->issue_offset_99_event); + seq_printf(m, "org_pci_offset_80\t0x%x\n", tp->org_pci_offset_80); + seq_printf(m, "org_pci_offset_81\t0x%x\n", tp->org_pci_offset_81); + seq_printf(m, "use_timer_interrupt\t0x%x\n", tp->use_timer_interrupt); + seq_printf(m, "HwIcVerUnknown\t0x%x\n", tp->HwIcVerUnknown); + seq_printf(m, "NotWrRamCodeToMicroP\t0x%x\n", tp->NotWrRamCodeToMicroP); + seq_printf(m, "NotWrMcuPatchCode\t0x%x\n", tp->NotWrMcuPatchCode); + seq_printf(m, "HwHasWrRamCodeToMicroP\t0x%x\n", tp->HwHasWrRamCodeToMicroP); + seq_printf(m, "sw_ram_code_ver\t0x%x\n", tp->sw_ram_code_ver); + seq_printf(m, "hw_ram_code_ver\t0x%x\n", tp->hw_ram_code_ver); + seq_printf(m, "rtk_enable_diag\t0x%x\n", tp->rtk_enable_diag); + seq_printf(m, "ShortPacketSwChecksum\t0x%x\n", tp->ShortPacketSwChecksum); + seq_printf(m, "UseSwPaddingShortPkt\t0x%x\n", tp->UseSwPaddingShortPkt); + seq_printf(m, "RequireAdcBiasPatch\t0x%x\n", tp->RequireAdcBiasPatch); + seq_printf(m, "AdcBiasPatchIoffset\t0x%x\n", tp->AdcBiasPatchIoffset); + seq_printf(m, "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n", tp->RequireAdjustUpsTxLinkPulseTiming); + seq_printf(m, "SwrCnt1msIni\t0x%x\n", tp->SwrCnt1msIni); + seq_printf(m, "HwSuppNowIsOobVer\t0x%x\n", tp->HwSuppNowIsOobVer); + seq_printf(m, "HwFiberModeVer\t0x%x\n", tp->HwFiberModeVer); + seq_printf(m, "HwFiberStat\t0x%x\n", tp->HwFiberStat); + seq_printf(m, "HwSwitchMdiToFiber\t0x%x\n", tp->HwSwitchMdiToFiber); + seq_printf(m, "NicCustLedValue\t0x%x\n", tp->NicCustLedValue); + seq_printf(m, "RequiredSecLanDonglePatch\t0x%x\n", tp->RequiredSecLanDonglePatch); + seq_printf(m, "HwSuppDashVer\t0x%x\n", tp->HwSuppDashVer); + seq_printf(m, "DASH\t0x%x\n", tp->DASH); + seq_printf(m, "dash_printer_enabled\t0x%x\n", tp->dash_printer_enabled); + seq_printf(m, "HwSuppKCPOffloadVer\t0x%x\n", tp->HwSuppKCPOffloadVer); + seq_printf(m, "speed_mode\t0x%x\n", speed_mode); + seq_printf(m, "duplex_mode\t0x%x\n", duplex_mode); + seq_printf(m, "autoneg_mode\t0x%x\n", autoneg_mode); + seq_printf(m, "aspm\t0x%x\n", aspm); + seq_printf(m, "s5wol\t0x%x\n", s5wol); + seq_printf(m, "s5_keep_curr_mac\t0x%x\n", s5_keep_curr_mac); + seq_printf(m, "eee_enable\t0x%x\n", tp->eee.eee_enabled); + seq_printf(m, "hwoptimize\t0x%lx\n", hwoptimize); + seq_printf(m, "proc_init_num\t0x%x\n", proc_init_num); + seq_printf(m, "s0_magic_packet\t0x%x\n", s0_magic_packet); + seq_printf(m, "disable_wol_support\t0x%x\n", disable_wol_support); + seq_printf(m, "enable_double_vlan\t0x%x\n", enable_double_vlan); + seq_printf(m, "eee_giga_lite\t0x%x\n", eee_giga_lite); + seq_printf(m, "HwSuppMagicPktVer\t0x%x\n", tp->HwSuppMagicPktVer); + seq_printf(m, "HwSuppLinkChgWakeUpVer\t0x%x\n", tp->HwSuppLinkChgWakeUpVer); + seq_printf(m, "HwSuppD0SpeedUpVer\t0x%x\n", tp->HwSuppD0SpeedUpVer); + seq_printf(m, "D0SpeedUpSpeed\t0x%x\n", tp->D0SpeedUpSpeed); + seq_printf(m, "HwSuppCheckPhyDisableModeVer\t0x%x\n", tp->HwSuppCheckPhyDisableModeVer); + seq_printf(m, "HwPkgDet\t0x%x\n", tp->HwPkgDet); + seq_printf(m, "HwSuppTxNoCloseVer\t0x%x\n", tp->HwSuppTxNoCloseVer); + seq_printf(m, "EnableTxNoClose\t0x%x\n", tp->EnableTxNoClose); + seq_printf(m, "NextHwDesCloPtr0\t0x%x\n", tp->tx_ring[0].NextHwDesCloPtr); + seq_printf(m, "BeginHwDesCloPtr0\t0x%x\n", tp->tx_ring[0].BeginHwDesCloPtr); + seq_printf(m, "hw_clo_ptr_reg0\t0x%x\n", rtl8127_get_hw_clo_ptr(&tp->tx_ring[0])); + seq_printf(m, "sw_tail_ptr_reg0\t0x%x\n", rtl8127_get_sw_tail_ptr(&tp->tx_ring[0])); + seq_printf(m, "NextHwDesCloPtr1\t0x%x\n", tp->tx_ring[1].NextHwDesCloPtr); + seq_printf(m, "BeginHwDesCloPtr1\t0x%x\n", tp->tx_ring[1].BeginHwDesCloPtr); + seq_printf(m, "hw_clo_ptr_reg1\t0x%x\n", rtl8127_get_hw_clo_ptr(&tp->tx_ring[1])); + seq_printf(m, "sw_tail_ptr_reg1\t0x%x\n", rtl8127_get_sw_tail_ptr(&tp->tx_ring[1])); + seq_printf(m, "InitRxDescType\t0x%x\n", tp->InitRxDescType); + seq_printf(m, "RxDescLength\t0x%x\n", tp->RxDescLength); + seq_printf(m, "num_rx_rings\t0x%x\n", tp->num_rx_rings); + seq_printf(m, "num_tx_rings\t0x%x\n", tp->num_tx_rings); + seq_printf(m, "tot_rx_rings\t0x%x\n", rtl8127_tot_rx_rings(tp)); + seq_printf(m, "tot_tx_rings\t0x%x\n", rtl8127_tot_tx_rings(tp)); + seq_printf(m, "HwSuppNumRxQueues\t0x%x\n", tp->HwSuppNumRxQueues); + seq_printf(m, "HwSuppNumTxQueues\t0x%x\n", tp->HwSuppNumTxQueues); + seq_printf(m, "EnableRss\t0x%x\n", tp->EnableRss); + seq_printf(m, "EnablePtp\t0x%x\n", tp->EnablePtp); + seq_printf(m, "min_irq_nvecs\t0x%x\n", tp->min_irq_nvecs); + seq_printf(m, "irq_nvecs\t0x%x\n", tp->irq_nvecs); + seq_printf(m, "hw_supp_irq_nvecs\t0x%x\n", tp->hw_supp_irq_nvecs); + seq_printf(m, "ring_lib_enabled\t0x%x\n", tp->ring_lib_enabled); + seq_printf(m, "HwSuppIsrVer\t0x%x\n", tp->HwSuppIsrVer); + seq_printf(m, "HwCurrIsrVer\t0x%x\n", tp->HwCurrIsrVer); + seq_printf(m, "HwSuppMacMcuVer\t0x%x\n", tp->HwSuppMacMcuVer); + seq_printf(m, "MacMcuPageSize\t0x%x\n", tp->MacMcuPageSize); + seq_printf(m, "hw_mcu_patch_code_ver\t0x%llx\n", tp->hw_mcu_patch_code_ver); + seq_printf(m, "bin_mcu_patch_code_ver\t0x%llx\n", tp->bin_mcu_patch_code_ver); +#ifdef ENABLE_PTP_SUPPORT + seq_printf(m, "tx_hwtstamp_timeouts\t0x%x\n", tp->tx_hwtstamp_timeouts); + seq_printf(m, "tx_hwtstamp_skipped\t0x%x\n", tp->tx_hwtstamp_skipped); +#endif + seq_printf(m, "random_mac\t0x%x\n", tp->random_mac); + seq_printf(m, "org_mac_addr\t%pM\n", tp->org_mac_addr); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) + seq_printf(m, "perm_addr\t%pM\n", dev->perm_addr); +#endif + seq_printf(m, "dev_addr\t%pM\n", dev->dev_addr); + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_get_tally_counter(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct rtl8127_private *tp = netdev_priv(dev); + struct rtl8127_counters *counters; + dma_addr_t paddr; + + seq_puts(m, "\nDump Tally Counter\n"); + + rtnl_lock(); + + counters = tp->tally_vaddr; + paddr = tp->tally_paddr; + if (!counters) { + seq_puts(m, "\nDump Tally Counter Fail\n"); + goto out_unlock; + } + + rtl8127_dump_tally_counter(tp, paddr); + + seq_puts(m, "Statistics\tValue\n----------\t-----\n"); + seq_printf(m, "tx_packets\t%lld\n", le64_to_cpu(counters->tx_packets)); + seq_printf(m, "rx_packets\t%lld\n", le64_to_cpu(counters->rx_packets)); + seq_printf(m, "tx_errors\t%lld\n", le64_to_cpu(counters->tx_errors)); + seq_printf(m, "rx_errors\t%d\n", le32_to_cpu(counters->rx_errors)); + seq_printf(m, "rx_missed\t%d\n", le16_to_cpu(counters->rx_missed)); + seq_printf(m, "align_errors\t%d\n", le16_to_cpu(counters->align_errors)); + seq_printf(m, "tx_one_collision\t%d\n", le32_to_cpu(counters->tx_one_collision)); + seq_printf(m, "tx_multi_collision\t%d\n", le32_to_cpu(counters->tx_multi_collision)); + seq_printf(m, "rx_unicast\t%lld\n", le64_to_cpu(counters->rx_unicast)); + seq_printf(m, "rx_broadcast\t%lld\n", le64_to_cpu(counters->rx_broadcast)); + seq_printf(m, "rx_multicast\t%d\n", le32_to_cpu(counters->rx_multicast)); + seq_printf(m, "tx_aborted\t%d\n", le16_to_cpu(counters->tx_aborted)); + seq_printf(m, "tx_underrun\t%d\n", le16_to_cpu(counters->tx_underrun)); + + seq_printf(m, "tx_octets\t%lld\n", le64_to_cpu(counters->tx_octets)); + seq_printf(m, "rx_octets\t%lld\n", le64_to_cpu(counters->rx_octets)); + seq_printf(m, "rx_multicast64\t%lld\n", le64_to_cpu(counters->rx_multicast64)); + seq_printf(m, "tx_unicast64\t%lld\n", le64_to_cpu(counters->tx_unicast64)); + seq_printf(m, "tx_broadcast64\t%lld\n", le64_to_cpu(counters->tx_broadcast64)); + seq_printf(m, "tx_multicast64\t%lld\n", le64_to_cpu(counters->tx_multicast64)); + seq_printf(m, "tx_pause_on\t%d\n", le32_to_cpu(counters->tx_pause_on)); + seq_printf(m, "tx_pause_off\t%d\n", le32_to_cpu(counters->tx_pause_off)); + seq_printf(m, "tx_pause_all\t%d\n", le32_to_cpu(counters->tx_pause_all)); + seq_printf(m, "tx_deferred\t%d\n", le32_to_cpu(counters->tx_deferred)); + seq_printf(m, "tx_late_collision\t%d\n", le32_to_cpu(counters->tx_late_collision)); + seq_printf(m, "tx_all_collision\t%d\n", le32_to_cpu(counters->tx_all_collision)); + seq_printf(m, "tx_aborted32\t%d\n", le32_to_cpu(counters->tx_aborted32)); + seq_printf(m, "align_errors32\t%d\n", le32_to_cpu(counters->align_errors32)); + seq_printf(m, "rx_frame_too_long\t%d\n", le32_to_cpu(counters->rx_frame_too_long)); + seq_printf(m, "rx_runt\t%d\n", le32_to_cpu(counters->rx_runt)); + seq_printf(m, "rx_pause_on\t%d\n", le32_to_cpu(counters->rx_pause_on)); + seq_printf(m, "rx_pause_off\t%d\n", le32_to_cpu(counters->rx_pause_off)); + seq_printf(m, "rx_pause_all\t%d\n", le32_to_cpu(counters->rx_pause_all)); + seq_printf(m, "rx_unknown_opcode\t%d\n", le32_to_cpu(counters->rx_unknown_opcode)); + seq_printf(m, "rx_mac_error\t%d\n", le32_to_cpu(counters->rx_mac_error)); + seq_printf(m, "tx_underrun32\t%d\n", le32_to_cpu(counters->tx_underrun32)); + seq_printf(m, "rx_mac_missed\t%d\n", le32_to_cpu(counters->rx_mac_missed)); + seq_printf(m, "rx_tcam_dropped\t%d\n", le32_to_cpu(counters->rx_tcam_dropped)); + seq_printf(m, "tdu\t%d\n", le32_to_cpu(counters->tdu)); + seq_printf(m, "rdu\t%d\n", le32_to_cpu(counters->rdu)); + + seq_putc(m, '\n'); + +out_unlock: + rtnl_unlock(); + + return 0; +} + +static int proc_get_registers(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i, n, max = R8127_MAC_REGS_SIZE; + u8 byte_rd; + struct rtl8127_private *tp = netdev_priv(dev); + void __iomem *ioaddr = tp->mmio_addr; + + seq_puts(m, "\nDump MAC Registers\n"); + seq_puts(m, "Offset\tValue\n------\t-----\n"); + + for (n = 0; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); + + rtnl_lock(); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + + rtnl_unlock(); + } + + rtnl_lock(); + + max = 0xB00; + for (n = 0xA00; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + } + + max = 0xD40; + for (n = 0xD00; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + } + + max = 0x2840; + for (n = 0x2800; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + } + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_get_pcie_phy(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i, n, max = R8127_EPHY_REGS_SIZE/2; + u16 word_rd; + struct rtl8127_private *tp = netdev_priv(dev); + + seq_puts(m, "\nDump PCIE PHY\n"); + seq_puts(m, "\nOffset\tValue\n------\t-----\n "); + + rtnl_lock(); + + for (n = 0; n < max;) { + seq_printf(m, "\n0x%02x:\t", n); + + for (i = 0; i < 8 && n < max; i++, n++) { + word_rd = rtl8127_ephy_read(tp, n); + seq_printf(m, "%04x ", word_rd); + } + } + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_get_eth_phy(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i, n, max = R8127_PHY_REGS_SIZE/2; + unsigned long flags; + u16 word_rd; + struct rtl8127_private *tp = netdev_priv(dev); + + seq_puts(m, "\nDump Ethernet PHY\n"); + seq_puts(m, "\nOffset\tValue\n------\t-----\n "); + + spin_lock_irqsave(&tp->phy_lock, flags); + + seq_puts(m, "\n####################page 0##################\n "); + rtl8127_mdio_write(tp, 0x1f, 0x0000); + for (n = 0; n < max;) { + seq_printf(m, "\n0x%02x:\t", n); + + for (i = 0; i < 8 && n < max; i++, n++) { + word_rd = rtl8127_mdio_read(tp, n); + seq_printf(m, "%04x ", word_rd); + } + } + + seq_puts(m, "\n####################extra reg##################\n "); + n = 0xA400; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 8; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + + n = 0xA410; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + + n = 0xA434; + seq_printf(m, "\n0x%02x:\t", n); + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + + n = 0xA5D0; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 4; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + + n = 0xA61A; + seq_printf(m, "\n0x%02x:\t", n); + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + + n = 0xA6D0; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + + spin_unlock_irqrestore(&tp->phy_lock, flags); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_get_extended_registers(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i, n, max = R8127_ERI_REGS_SIZE; + u32 dword_rd; + struct rtl8127_private *tp = netdev_priv(dev); + + seq_puts(m, "\nDump Extended Registers\n"); + seq_puts(m, "\nOffset\tValue\n------\t-----\n "); + + rtnl_lock(); + + for (n = 0; n < max;) { + seq_printf(m, "\n0x%02x:\t", n); + + for (i = 0; i < 4 && n < max; i++, n+=4) { + dword_rd = rtl8127_eri_read(tp, n, 4, ERIAR_ExGMAC); + seq_printf(m, "%08x ", dword_rd); + } + } + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_get_pci_registers(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i, n, max = R8127_PCI_REGS_SIZE; + u32 dword_rd; + struct rtl8127_private *tp = netdev_priv(dev); + + seq_puts(m, "\nDump PCI Registers\n"); + seq_puts(m, "\nOffset\tValue\n------\t-----\n "); + + rtnl_lock(); + + for (n = 0; n < max;) { + seq_printf(m, "\n0x%03x:\t", n); + + for (i = 0; i < 4 && n < max; i++, n+=4) { + pci_read_config_dword(tp->pci_dev, n, &dword_rd); + seq_printf(m, "%08x ", dword_rd); + } + } + + n = 0x110; + pci_read_config_dword(tp->pci_dev, n, &dword_rd); + seq_printf(m, "\n0x%03x:\t%08x ", n, dword_rd); + n = 0x70c; + pci_read_config_dword(tp->pci_dev, n, &dword_rd); + seq_printf(m, "\n0x%03x:\t%08x ", n, dword_rd); + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_get_temperature(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct rtl8127_private *tp = netdev_priv(dev); + u16 ts_digout, tj, fah; + + seq_puts(m, "\nChip Temperature\n"); + + rtnl_lock(); + + if (!rtl8127_sysfs_testmode_on(tp)) { + seq_puts(m, "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + rtnl_unlock(); + return 0; + } + + netif_testing_on(dev); + ts_digout = rtl8127_read_thermal_sensor(tp); + netif_testing_off(dev); + + rtnl_unlock(); + + tj = ts_digout / 2; + if (ts_digout <= 512) { + tj = ts_digout / 2; + seq_printf(m, "Cel:%d\n", tj); + fah = tj * (9/5) + 32; + seq_printf(m, "Fah:%d\n", fah); + } else { + tj = (512 - ((ts_digout / 2) - 512)) / 2; + seq_printf(m, "Cel:-%d\n", tj); + fah = tj * (9/5) + 32; + seq_printf(m, "Fah:-%d\n", fah); + } + + seq_putc(m, '\n'); + return 0; +} + +static int _proc_get_cable_info(struct seq_file *m, void *v, bool poe_mode) +{ + int i; + u32 status; + int cp_status[RTL8127_CP_NUM]; + int cp_len[RTL8127_CP_NUM] = {0}; + struct net_device *dev = m->private; + struct rtl8127_private *tp = netdev_priv(dev); + const char *pair_str[RTL8127_CP_NUM] = {"1-2", "3-6", "4-5", "7-8"}; + int ret; + + rtnl_lock(); + + if (!rtl8127_sysfs_testmode_on(tp)) { + seq_puts(m, "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + ret = 0; + goto error_unlock; + } + + rtl8127_mdio_write(tp, 0x1F, 0x0000); + if (rtl8127_mdio_read(tp, MII_BMCR) & BMCR_PDOWN) { + ret = -EIO; + goto error_unlock; + } + + netif_testing_on(dev); + + status = rtl8127_get_phy_status(tp); + if (status & LinkStatus) + seq_printf(m, "\nlink speed:%d", + rtl8127_convert_link_speed(status)); + else + seq_puts(m, "\nlink status:off"); + + rtl8127_get_cp_len(tp, cp_len); + + rtl8127_get_cp_status(tp, cp_status, poe_mode); + + seq_puts(m, "\npair\tlength\tstatus \tpp\n"); + + for (i=0; iprivate; + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + rtnl_lock(); + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8127_rx_ring *ring = &tp->rx_ring[i]; + + if (!ring) + continue; + + seq_printf(m, "\ndump rx %d desc:%d\n", i, ring->num_rx_desc); + + _proc_dump_desc(m, (void*)ring->RxDescArray, ring->RxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8127_num_lib_rx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumRxQueues; i++) { + struct rtl8127_ring *lib_ring = &tp->lib_rx_ring[i]; + if (lib_ring->enabled) { + seq_printf(m, "\ndump lib rx %d desc:%d\n", i, + lib_ring->ring_size); + _proc_dump_desc(m, (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_dump_tx_desc(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + rtnl_lock(); + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8127_tx_ring *ring = &tp->tx_ring[i]; + + if (!ring) + continue; + + seq_printf(m, "\ndump tx %d desc:%d\n", i, ring->num_tx_desc); + + _proc_dump_desc(m, (void*)ring->TxDescArray, ring->TxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8127_num_lib_tx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumTxQueues; i++) { + struct rtl8127_ring *lib_ring = &tp->lib_tx_ring[i]; + if (lib_ring->enabled) { + seq_printf(m, "\ndump lib tx %d desc:%d\n", i, + lib_ring->ring_size); + _proc_dump_desc(m, (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_dump_msix_tbl(struct seq_file *m, void *v) +{ + int i, j; + void __iomem *ioaddr; + struct net_device *dev = m->private; + struct rtl8127_private *tp = netdev_priv(dev); + + /* ioremap MMIO region */ + ioaddr = ioremap(pci_resource_start(tp->pci_dev, 4), pci_resource_len(tp->pci_dev, 4)); + if (!ioaddr) + return -EFAULT; + + rtnl_lock(); + + seq_printf(m, "\ndump MSI-X Table. Total Entry %d. \n", tp->hw_supp_irq_nvecs); + + for (i=0; ihw_supp_irq_nvecs; i++) { + seq_printf(m, "\n%04x ", i); + for (j=0; j<4; j++) + seq_printf(m, "%08x ", + readl(ioaddr + i*0x10 + 4*j)); + } + + rtnl_unlock(); + + iounmap(ioaddr); + + seq_putc(m, '\n'); + return 0; +} + +#else //LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + +static int proc_get_driver_variable(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct rtl8127_private *tp = netdev_priv(dev); + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump Driver Driver\n"); + + rtnl_lock(); + + len += snprintf(page + len, count - len, + "Variable\tValue\n----------\t-----\n"); + + len += snprintf(page + len, count - len, + "MODULENAME\t%s\n" + "driver version\t%s\n" + "mcfg\t%d\n" + "chipset\t%d\n" + "chipset_name\t%s\n" + "mtu\t%d\n" + "NUM_RX_DESC\t0x%x\n" + "cur_rx0\t0x%x\n" + "dirty_rx0\t0x%x\n" + "cur_rx1\t0x%x\n" + "dirty_rx1\t0x%x\n" + "cur_rx2\t0x%x\n" + "dirty_rx2\t0x%x\n" + "cur_rx3\t0x%x\n" + "dirty_rx3\t0x%x\n" + "NUM_TX_DESC\t0x%x\n" + "cur_tx0\t0x%x\n" + "dirty_tx0\t0x%x\n" + "cur_tx1\t0x%x\n" + "dirty_tx1\t0x%x\n" + "rx_buf_sz\t0x%x\n" +#ifdef ENABLE_PAGE_REUSE + "rx_buf_page_order\t0x%x\n" + "rx_buf_page_size\t0x%x\n" + "page_reuse_fail_cnt\t0x%x\n" +#endif //ENABLE_PAGE_REUSE + "esd_flag\t0x%x\n" + "pci_cfg_is_read\t0x%x\n" + "rtl8127_rx_config\t0x%x\n" + "cp_cmd\t0x%x\n" + "intr_mask\t0x%x\n" + "timer_intr_mask\t0x%x\n" + "wol_enabled\t0x%x\n" + "wol_opts\t0x%x\n" + "efuse_ver\t0x%x\n" + "eeprom_type\t0x%x\n" + "autoneg\t0x%x\n" + "duplex\t0x%x\n" + "speed\t%d\n" + "advertising\t0x%llx\n" + "eeprom_len\t0x%x\n" + "cur_page\t0x%x\n" + "features\t0x%x\n" + "org_pci_offset_99\t0x%x\n" + "org_pci_offset_180\t0x%x\n" + "issue_offset_99_event\t0x%x\n" + "org_pci_offset_80\t0x%x\n" + "org_pci_offset_81\t0x%x\n" + "use_timer_interrupt\t0x%x\n" + "HwIcVerUnknown\t0x%x\n" + "NotWrRamCodeToMicroP\t0x%x\n" + "NotWrMcuPatchCode\t0x%x\n" + "HwHasWrRamCodeToMicroP\t0x%x\n" + "sw_ram_code_ver\t0x%x\n" + "hw_ram_code_ver\t0x%x\n" + "rtk_enable_diag\t0x%x\n" + "ShortPacketSwChecksum\t0x%x\n" + "UseSwPaddingShortPkt\t0x%x\n" + "RequireAdcBiasPatch\t0x%x\n" + "AdcBiasPatchIoffset\t0x%x\n" + "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n" + "SwrCnt1msIni\t0x%x\n" + "HwSuppNowIsOobVer\t0x%x\n" + "HwFiberModeVer\t0x%x\n" + "HwFiberStat\t0x%x\n" + "HwSwitchMdiToFiber\t0x%x\n" + "NicCustLedValue\t0x%x\n" + "RequiredSecLanDonglePatch\t0x%x\n" + "HwSuppDashVer\t0x%x\n" + "DASH\t0x%x\n" + "dash_printer_enabled\t0x%x\n" + "HwSuppKCPOffloadVer\t0x%x\n" + "speed_mode\t0x%x\n" + "duplex_mode\t0x%x\n" + "autoneg_mode\t0x%x\n" + "aspm\t0x%x\n" + "s5wol\t0x%x\n" + "s5_keep_curr_mac\t0x%x\n" + "eee_enable\t0x%x\n" + "hwoptimize\t0x%lx\n" + "proc_init_num\t0x%x\n" + "s0_magic_packet\t0x%x\n" + "disable_wol_support\t0x%x\n" + "enable_double_vlan\t0x%x\n" + "eee_giga_lite\t0x%x\n" + "HwSuppMagicPktVer\t0x%x\n" + "HwSuppLinkChgWakeUpVer\t0x%x\n" + "HwSuppD0SpeedUpVer\t0x%x\n" + "D0SpeedUpSpeed\t0x%x\n" + "HwSuppCheckPhyDisableModeVer\t0x%x\n" + "HwPkgDet\t0x%x\n" + "HwSuppTxNoCloseVer\t0x%x\n" + "EnableTxNoClose\t0x%x\n" + "NextHwDesCloPtr0\t0x%x\n" + "BeginHwDesCloPtr0\t0x%x\n" + "hw_clo_ptr_reg0\t0x%x\n" + "sw_tail_ptr_reg0\t0x%x\n" + "NextHwDesCloPtr1\t0x%x\n" + "BeginHwDesCloPtr1\t0x%x\n" + "hw_clo_ptr_reg1\t0x%x\n" + "sw_tail_ptr_reg1\t0x%x\n" + "InitRxDescType\t0x%x\n" + "RxDescLength\t0x%x\n" + "num_rx_rings\t0x%x\n" + "num_tx_rings\t0x%x\n" + "tot_rx_rings\t0x%x\n" + "tot_tx_rings\t0x%x\n" + "HwSuppNumRxQueues\t0x%x\n" + "HwSuppNumTxQueues\t0x%x\n" + "EnableRss\t0x%x\n" + "EnablePtp\t0x%x\n" + "min_irq_nvecs\t0x%x\n" + "irq_nvecs\t0x%x\n" + "hw_supp_irq_nvecs\t0x%x\n" + "ring_lib_enabled\t0x%x\n" + "HwSuppIsrVer\t0x%x\n" + "HwCurrIsrVer\t0x%x\n" + "HwSuppMacMcuVer\t0x%x\n" + "MacMcuPageSize\t0x%x\n" + "hw_mcu_patch_code_ver\t0x%llx\n" + "bin_mcu_patch_code_ver\t0x%llx\n" +#ifdef ENABLE_PTP_SUPPORT + "tx_hwtstamp_timeouts\t0x%x\n" + "tx_hwtstamp_skipped\t0x%x\n" +#endif + "random_mac\t0x%x\n" + "org_mac_addr\t%pM\n" +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) + "perm_addr\t%pM\n" +#endif + "dev_addr\t%pM\n", + MODULENAME, + RTL8127_VERSION, + tp->mcfg, + tp->chipset, + rtl_chip_info[tp->chipset].name, + dev->mtu, + tp->rx_ring[0].num_rx_desc, + tp->rx_ring[0].cur_rx, + tp->rx_ring[0].dirty_rx, + tp->rx_ring[1].cur_rx, + tp->rx_ring[1].dirty_rx, + tp->rx_ring[2].cur_rx, + tp->rx_ring[2].dirty_rx, + tp->rx_ring[3].cur_rx, + tp->rx_ring[3].dirty_rx, + tp->tx_ring[0].num_tx_desc, + tp->tx_ring[0].cur_tx, + tp->tx_ring[0].dirty_tx, + tp->tx_ring[1].cur_tx, + tp->tx_ring[1].dirty_tx, + tp->rx_buf_sz, +#ifdef ENABLE_PAGE_REUSE + tp->rx_buf_page_order, + tp->rx_buf_page_size, + tp->page_reuse_fail_cnt, +#endif //ENABLE_PAGE_REUSE + tp->esd_flag, + tp->pci_cfg_is_read, + tp->rtl8127_rx_config, + tp->cp_cmd, + tp->intr_mask, + tp->timer_intr_mask, + tp->wol_enabled, + tp->wol_opts, + tp->efuse_ver, + tp->eeprom_type, + tp->autoneg, + tp->duplex, + tp->speed, + tp->advertising, + tp->eeprom_len, + tp->cur_page, + tp->features, + tp->org_pci_offset_99, + tp->org_pci_offset_180, + tp->issue_offset_99_event, + tp->org_pci_offset_80, + tp->org_pci_offset_81, + tp->use_timer_interrupt, + tp->HwIcVerUnknown, + tp->NotWrRamCodeToMicroP, + tp->NotWrMcuPatchCode, + tp->HwHasWrRamCodeToMicroP, + tp->sw_ram_code_ver, + tp->hw_ram_code_ver, + tp->rtk_enable_diag, + tp->ShortPacketSwChecksum, + tp->UseSwPaddingShortPkt, + tp->RequireAdcBiasPatch, + tp->AdcBiasPatchIoffset, + tp->RequireAdjustUpsTxLinkPulseTiming, + tp->SwrCnt1msIni, + tp->HwSuppNowIsOobVer, + tp->HwFiberModeVer, + tp->HwFiberStat, + tp->HwSwitchMdiToFiber, + tp->NicCustLedValue, + tp->RequiredSecLanDonglePatch, + tp->HwSuppDashVer, + tp->DASH, + tp->dash_printer_enabled, + tp->HwSuppKCPOffloadVer, + speed_mode, + duplex_mode, + autoneg_mode, + aspm, + s5wol, + s5_keep_curr_mac, + tp->eee.eee_enabled, + hwoptimize, + proc_init_num, + s0_magic_packet, + disable_wol_support, + enable_double_vlan, + eee_giga_lite, + tp->HwSuppMagicPktVer, + tp->HwSuppLinkChgWakeUpVer, + tp->HwSuppD0SpeedUpVer, + tp->D0SpeedUpSpeed, + tp->HwSuppCheckPhyDisableModeVer, + tp->HwPkgDet, + tp->HwSuppTxNoCloseVer, + tp->EnableTxNoClose, + tp->tx_ring[0].NextHwDesCloPtr, + tp->tx_ring[0].BeginHwDesCloPtr, + rtl8127_get_hw_clo_ptr(&tp->tx_ring[0]), + rtl8127_get_sw_tail_ptr(&tp->tx_ring[0]), + tp->tx_ring[1].NextHwDesCloPtr, + tp->tx_ring[1].BeginHwDesCloPtr, + rtl8127_get_hw_clo_ptr(&tp->tx_ring[1]), + rtl8127_get_sw_tail_ptr(&tp->tx_ring[1]), + tp->InitRxDescType, + tp->RxDescLength, + tp->num_rx_rings, + tp->num_tx_rings, + rtl8127_tot_rx_rings(tp), + rtl8127_tot_tx_rings(tp), + tp->HwSuppNumRxQueues, + tp->HwSuppNumTxQueues, + tp->EnableRss, + tp->EnablePtp, + tp->min_irq_nvecs, + tp->irq_nvecs, + tp->hw_supp_irq_nvecs, + tp->ring_lib_enabled, + tp->HwSuppIsrVer, + tp->HwCurrIsrVer, + tp->HwSuppMacMcuVer, + tp->MacMcuPageSize, + tp->hw_mcu_patch_code_ver, + tp->bin_mcu_patch_code_ver, +#ifdef ENABLE_PTP_SUPPORT + tp->tx_hwtstamp_timeouts, + tp->tx_hwtstamp_skipped, +#endif + tp->random_mac, + tp->org_mac_addr, +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) + dev->perm_addr, +#endif + dev->dev_addr); + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return len; +} + +static int proc_get_tally_counter(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct rtl8127_private *tp = netdev_priv(dev); + struct rtl8127_counters *counters; + dma_addr_t paddr; + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump Tally Counter\n"); + + rtnl_lock(); + + counters = tp->tally_vaddr; + paddr = tp->tally_paddr; + if (!counters) { + len += snprintf(page + len, count - len, + "\nDump Tally Counter Fail\n"); + goto out_unlock; + } + + rtl8127_dump_tally_counter(tp, paddr); + + len += snprintf(page + len, count - len, + "Statistics\tValue\n----------\t-----\n"); + + len += snprintf(page + len, count - len, + "tx_packets\t%lld\n" + "rx_packets\t%lld\n" + "tx_errors\t%lld\n" + "rx_errors\t%d\n" + "rx_missed\t%d\n" + "align_errors\t%d\n" + "tx_one_collision\t%d\n" + "tx_multi_collision\t%d\n" + "rx_unicast\t%lld\n" + "rx_broadcast\t%lld\n" + "rx_multicast\t%d\n" + "tx_aborted\t%d\n" + "tx_underrun\t%d\n" + + "tx_octets\t%lld\n" + "rx_octets\t%lld\n" + "rx_multicast64\t%lld\n" + "tx_unicast64\t%lld\n" + "tx_broadcast64\t%lld\n" + "tx_multicast64\t%lld\n" + "tx_pause_on\t%d\n" + "tx_pause_off\t%d\n" + "tx_pause_all\t%d\n" + "tx_deferred\t%d\n" + "tx_late_collision\t%d\n" + "tx_all_collision\t%d\n" + "tx_aborted32\t%d\n" + "align_errors32\t%d\n" + "rx_frame_too_long\t%d\n" + "rx_runt\t%d\n" + "rx_pause_on\t%d\n" + "rx_pause_off\t%d\n" + "rx_pause_all\t%d\n" + "rx_unknown_opcode\t%d\n" + "rx_mac_error\t%d\n" + "tx_underrun32\t%d\n" + "rx_mac_missed\t%d\n" + "rx_tcam_dropped\t%d\n" + "tdu\t%d\n" + "rdu\t%d\n", + le64_to_cpu(counters->tx_packets), + le64_to_cpu(counters->rx_packets), + le64_to_cpu(counters->tx_errors), + le32_to_cpu(counters->rx_errors), + le16_to_cpu(counters->rx_missed), + le16_to_cpu(counters->align_errors), + le32_to_cpu(counters->tx_one_collision), + le32_to_cpu(counters->tx_multi_collision), + le64_to_cpu(counters->rx_unicast), + le64_to_cpu(counters->rx_broadcast), + le32_to_cpu(counters->rx_multicast), + le16_to_cpu(counters->tx_aborted), + le16_to_cpu(counters->tx_underrun), + + le64_to_cpu(counters->tx_octets), + le64_to_cpu(counters->rx_octets), + le64_to_cpu(counters->rx_multicast64), + le64_to_cpu(counters->tx_unicast64), + le64_to_cpu(counters->tx_broadcast64), + le64_to_cpu(counters->tx_multicast64), + le32_to_cpu(counters->tx_pause_on), + le32_to_cpu(counters->tx_pause_off), + le32_to_cpu(counters->tx_pause_all), + le32_to_cpu(counters->tx_deferred), + le32_to_cpu(counters->tx_late_collision), + le32_to_cpu(counters->tx_all_collision), + le32_to_cpu(counters->tx_aborted32), + le32_to_cpu(counters->align_errors32), + le32_to_cpu(counters->rx_frame_too_long), + le32_to_cpu(counters->rx_runt), + le32_to_cpu(counters->rx_pause_on), + le32_to_cpu(counters->rx_pause_off), + le32_to_cpu(counters->rx_pause_all), + le32_to_cpu(counters->rx_unknown_opcode), + le32_to_cpu(counters->rx_mac_error), + le32_to_cpu(counters->tx_underrun32), + le32_to_cpu(counters->rx_mac_missed), + le32_to_cpu(counters->rx_tcam_dropped), + le32_to_cpu(counters->tdu), + le32_to_cpu(counters->rdu)); + + len += snprintf(page + len, count - len, "\n"); +out_unlock: + rtnl_unlock(); + + *eof = 1; + return len; +} + +static int proc_get_registers(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + int i, n, max = R8127_MAC_REGS_SIZE; + u8 byte_rd; + struct rtl8127_private *tp = netdev_priv(dev); + void __iomem *ioaddr = tp->mmio_addr; + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump MAC Registers\n" + "Offset\tValue\n------\t-----\n"); + + for (n = 0; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", + n); + + rtnl_lock(); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + + rtnl_unlock(); + } + + rtnl_lock(); + + max = 0xB00; + for (n = 0xA00; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", + n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + } + + max = 0xD40; + for (n = 0xD00; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", + n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + } + + max = 0x2840; + for (n = 0x2800; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", + n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + } + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return len; +} + +static int proc_get_pcie_phy(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + int i, n, max = R8127_EPHY_REGS_SIZE/2; + u16 word_rd; + struct rtl8127_private *tp = netdev_priv(dev); + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump PCIE PHY\n" + "Offset\tValue\n------\t-----\n"); + + rtnl_lock(); + + for (n = 0; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + + for (i = 0; i < 8 && n < max; i++, n++) { + word_rd = rtl8127_ephy_read(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + } + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return len; +} + +static int proc_get_eth_phy(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + int i, n, max = R8127_PHY_REGS_SIZE/2; + u16 word_rd; + struct rtl8127_private *tp = netdev_priv(dev); + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump Ethernet PHY\n" + "Offset\tValue\n------\t-----\n"); + + rtnl_lock(); + + len += snprintf(page + len, count - len, + "\n####################page 0##################\n"); + rtl8127_mdio_write(tp, 0x1f, 0x0000); + for (n = 0; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + + for (i = 0; i < 8 && n < max; i++, n++) { + word_rd = rtl8127_mdio_read(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + } + + len += snprintf(page + len, count - len, + "\n####################extra reg##################\n"); + n = 0xA400; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 8; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + + n = 0xA410; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + + n = 0xA434; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + + n = 0xA5D0; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 4; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + + n = 0xA61A; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + + n = 0xA6D0; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8127_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return len; +} + +static int proc_get_extended_registers(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + int i, n, max = R8127_ERI_REGS_SIZE; + u32 dword_rd; + struct rtl8127_private *tp = netdev_priv(dev); + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump Extended Registers\n" + "Offset\tValue\n------\t-----\n"); + + rtnl_lock(); + + for (n = 0; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + + for (i = 0; i < 4 && n < max; i++, n+=4) { + dword_rd = rtl8127_eri_read(tp, n, 4, ERIAR_ExGMAC); + len += snprintf(page + len, count - len, + "%08x ", + dword_rd); + } + } + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return len; +} + +static int proc_get_pci_registers(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + int i, n, max = R8127_PCI_REGS_SIZE; + u32 dword_rd; + struct rtl8127_private *tp = netdev_priv(dev); + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump PCI Registers\n" + "Offset\tValue\n------\t-----\n"); + + rtnl_lock(); + + for (n = 0; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%03x:\t", + n); + + for (i = 0; i < 4 && n < max; i++, n+=4) { + pci_read_config_dword(tp->pci_dev, n, &dword_rd); + len += snprintf(page + len, count - len, + "%08x ", + dword_rd); + } + } + + n = 0x110; + pci_read_config_dword(tp->pci_dev, n, &dword_rd); + len += snprintf(page + len, count - len, + "\n0x%03x:\t%08x ", + n, + dword_rd); + n = 0x70c; + pci_read_config_dword(tp->pci_dev, n, &dword_rd); + len += snprintf(page + len, count - len, + "\n0x%03x:\t%08x ", + n, + dword_rd); + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return len; +} + +static int proc_get_temperature(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct rtl8127_private *tp = netdev_priv(dev); + u16 ts_digout, tj, fah; + int len = 0; + + len += snprintf(page + len, count - len, + "\nChip Temperature\n"); + + rtnl_lock(); + + if (!rtl8127_sysfs_testmode_on(tp)) { + len += snprintf(page + len, count - len, + "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + goto out_unlock; + } + + ts_digout = rtl8127_read_thermal_sensor(tp); + + tj = ts_digout / 2; + if (ts_digout <= 512) { + tj = ts_digout / 2; + len += snprintf(page + len, count - len, + "Cel:%d\n", + tj); + fah = tj * (9/5) + 32; + len += snprintf(page + len, count - len, + "Fah:%d\n", + fah); + + } else { + tj = (512 - ((ts_digout / 2) - 512)) / 2; + len += snprintf(page + len, count - len, + "Cel:-%d\n", + tj); + fah = tj * (9/5) + 32; + len += snprintf(page + len, count - len, + "Fah:-%d\n", + fah); + } + + len += snprintf(page + len, count - len, "\n"); + +out_unlock: + rtnl_unlock(); + + *eof = 1; + return len; +} + +static int _proc_get_cable_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data, + bool poe_mode) +{ + int i; + u16 status; + int len = 0; + struct net_device *dev = data; + int cp_status[RTL8127_CP_NUM] = {0}; + int cp_len[RTL8127_CP_NUM] = {0}; + struct rtl8127_private *tp = netdev_priv(dev); + const char *pair_str[RTL8127_CP_NUM] = {"1-2", "3-6", "4-5", "7-8"}; + + switch (tp->mcfg) { + default: + return -EOPNOTSUPP; + } + + spin_lock_irqsave(&tp->phy_lock, flags); + + if (!rtl8127_sysfs_testmode_on(tp)) { + len += snprintf(page + len, count - len, + "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + goto out_unlock; + } + + status = RTL_R16(tp, PHYstatus); + if (status & LinkStatus) + len += snprintf(page + len, count - len, + "\nlink speed:%d", + rtl8127_convert_link_speed(status)); + else + len += snprintf(page + len, count - len, + "\nlink status:off"); + + rtl8127_get_cp_len(tp, cp_len); + + rtl8127_get_cp_status(tp, cp_status, poe_mode); + + len += snprintf(page + len, count - len, + "\npair\tlength\tstatus \tpp\n"); + + for (i=0; iphy_lock, flags); + + *eof = 1; + return len; +} + +static int proc_get_cable_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + return _proc_get_cable_info(page, start, offset, count, eof, data, 0); +} + +static int proc_get_poe_cable_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + return _proc_get_cable_info(page, start, offset, count, eof, data, 1); +} + +static void _proc_dump_desc(char *page, int *page_len, int *count, void *desc_base, + u32 alloc_size) +{ + u32 *pdword; + int i, len; + + if (desc_base == NULL || + alloc_size == 0) + return; + + len = *page_len; + pdword = (u32*)desc_base; + for (i=0; i<(alloc_size/4); i++) { + if (!(i % 4)) + len += snprintf(page + len, *count - len, + "\n%04x ", + i); + len += snprintf(page + len, *count - len, + "%08x ", + pdword[i]); + } + + len += snprintf(page + len, *count - len, "\n"); + + *page_len = len; + return; +} + +static int proc_dump_rx_desc(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + int i; + int len = 0; + struct net_device *dev = data; + struct rtl8127_private *tp = netdev_priv(dev); + + rtnl_lock(); + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8127_rx_ring *ring = &tp->rx_ring[i]; + + if (!ring) + continue; + + len += snprintf(page + len, count - len, + "\ndump rx %d desc:%d", + i, ring->num_rx_desc); + + _proc_dump_desc(page, &len, &count, + ring->RxDescArray, + ring->RxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8127_num_lib_rx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumRxQueues; i++) { + struct rtl8127_ring *lib_ring = &tp->lib_rx_ring[i]; + if (lib_ring->enabled) { + len += snprintf(page + len, count - len, + "\ndump lib rx %d desc:%d", + i, + ring->ring_size); + _proc_dump_desc(page, &len, &count, + (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + + return len; +} + +static int proc_dump_tx_desc(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + int len = 0; + struct net_device *dev = data; + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + rtnl_lock(); + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8127_tx_ring *ring = &tp->tx_ring[i]; + + if (!ring) + continue; + + len += snprintf(page + len, count - len, + "\ndump tx desc:%d", + ring->num_tx_desc); + + _proc_dump_desc(page, &len, &count, + ring->TxDescArray, + ring->TxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8127_num_lib_tx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumTxQueues; i++) { + struct rtl8127_ring *lib_ring = &tp->lib_tx_ring[i]; + if (lib_ring->enabled) { + len += snprintf(page + len, count - len, + "\ndump lib tx %d desc:%d", + i, + ring->ring_size); + _proc_dump_desc(page, &len, &count, + (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + + return len; +} + +static int proc_dump_msix_tbl(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + int i, j; + int len = 0; + void __iomem *ioaddr; + struct net_device *dev = data; + struct rtl8127_private *tp = netdev_priv(dev); + + /* ioremap MMIO region */ + ioaddr = ioremap(pci_resource_start(tp->pci_dev, 4), pci_resource_len(tp->pci_dev, 4)); + if (!ioaddr) + return -EFAULT; + + rtnl_lock(); + + len += snprintf(page + len, count - len, + "\ndump MSI-X Table. Total Entry %d. \n", + tp->hw_supp_irq_nvecs); + + for (i=0; ihw_supp_irq_nvecs; i++) { + len += snprintf(page + len, count - len, + "\n%04x ", i); + for (j=0; j<4; j++) + len += snprintf(page + len, count - len, "%08x ", + readl(ioaddr + i*0x10 + 4*j)); + } + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return 0; +} + +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + +static void rtl8127_proc_module_init(void) +{ + //create /proc/net/r8127 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) + rtl8127_proc = proc_mkdir(MODULENAME, init_net.proc_net); +#else + rtl8127_proc = proc_mkdir(MODULENAME, proc_net); +#endif + if (!rtl8127_proc) + dprintk("cannot create %s proc entry \n", MODULENAME); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) +/* + * seq_file wrappers for procfile show routines. + */ +static int rtl8127_proc_open(struct inode *inode, struct file *file) +{ + struct net_device *dev = proc_get_parent_data(inode); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) + int (*show)(struct seq_file *, void *) = pde_data(inode); +#else + int (*show)(struct seq_file *, void *) = PDE_DATA(inode); +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) + + return single_open(file, show, dev); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) +static const struct proc_ops rtl8127_proc_fops = { + .proc_open = rtl8127_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, +}; +#else +static const struct file_operations rtl8127_proc_fops = { + .open = rtl8127_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif + +#endif + +/* + * Table of proc files we need to create. + */ +struct rtl8127_proc_file { + char name[16]; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + int (*show)(struct seq_file *, void *); +#else + int (*show)(char *, char **, off_t, int, int *, void *); +#endif +}; + +static const struct rtl8127_proc_file rtl8127_debug_proc_files[] = { + { "driver_var", &proc_get_driver_variable }, + { "tally", &proc_get_tally_counter }, + { "registers", &proc_get_registers }, + { "pcie_phy", &proc_get_pcie_phy }, + { "eth_phy", &proc_get_eth_phy }, + { "ext_regs", &proc_get_extended_registers }, + { "pci_regs", &proc_get_pci_registers }, + { "tx_desc", &proc_dump_tx_desc }, + { "rx_desc", &proc_dump_rx_desc }, + { "msix_tbl", &proc_dump_msix_tbl }, + { "", NULL } +}; + +static const struct rtl8127_proc_file rtl8127_test_proc_files[] = { + { "temp", &proc_get_temperature }, + { "cdt", &proc_get_cable_info }, + { "cdt_poe", &proc_get_poe_cable_info }, + { "", NULL } +}; + +#define R8127_PROC_DEBUG_DIR "debug" +#define R8127_PROC_TEST_DIR "test" + +static void rtl8127_proc_init(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + const struct rtl8127_proc_file *f; + struct proc_dir_entry *dir; + + if (!rtl8127_proc) + return; + + if (tp->proc_dir_debug || tp->proc_dir_test) + return; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + dir = proc_mkdir_data(dev->name, 0, rtl8127_proc, dev); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s\n", + MODULENAME, dev->name); + return; + } + tp->proc_dir = dir; + proc_init_num++; + + /* create debug entry */ + dir = proc_mkdir_data(R8127_PROC_DEBUG_DIR, 0, tp->proc_dir, dev); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_DEBUG_DIR); + return; + } + + tp->proc_dir_debug = dir; + for (f = rtl8127_debug_proc_files; f->name[0]; f++) { + if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir, + &rtl8127_proc_fops, f->show)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_DEBUG_DIR, + f->name); + return; + } + } + + /* create test entry */ + dir = proc_mkdir_data(R8127_PROC_TEST_DIR, 0, tp->proc_dir, dev); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_TEST_DIR); + return; + } + + tp->proc_dir_test = dir; + for (f = rtl8127_test_proc_files; f->name[0]; f++) { + if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir, + &rtl8127_proc_fops, f->show)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_TEST_DIR, + f->name); + return; + } + } +#else + dir = proc_mkdir(dev->name, rtl8127_proc); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s\n", + MODULENAME, dev->name); + return; + } + + tp->proc_dir = dir; + proc_init_num++; + + /* create debug entry */ + dir = proc_mkdir(R8127_PROC_DEBUG_DIR, tp->proc_dir); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_DEBUG_DIR); + return; + } + + tp->proc_dir_debug = dir; + for (f = rtl8127_debug_proc_files; f->name[0]; f++) { + if (!create_proc_read_entry(f->name, S_IFREG | S_IRUGO, + dir, f->show, dev)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_DEBUG_DIR, + f->name); + return; + } + } + + /* create test entry */ + dir = proc_mkdir(R8127_PROC_TEST_DIR, tp->proc_dir); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_TEST_DIR); + return; + } + + tp->proc_dir_test = dir; + for (f = rtl8127_test_proc_files; f->name[0]; f++) { + if (!create_proc_read_entry(f->name, S_IFREG | S_IRUGO, + dir, f->show, dev)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8127_PROC_TEST_DIR, + f->name); + return; + } + } +#endif +} + +static void rtl8127_proc_remove(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->proc_dir) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + remove_proc_subtree(dev->name, rtl8127_proc); +#else + const struct rtl8127_proc_file *f; + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->proc_dir_debug) { + for (f = rtl8127_debug_proc_files; f->name[0]; f++) + remove_proc_entry(f->name, tp->proc_dir_debug); + remove_proc_entry(R8127_PROC_DEBUG_DIR, tp->proc_dir); + } + + if (tp->proc_dir_test) { + for (f = rtl8127_test_proc_files; f->name[0]; f++) + remove_proc_entry(f->name, tp->proc_dir_test); + remove_proc_entry(R8127_PROC_TEST_DIR, tp->proc_dir); + } + + remove_proc_entry(dev->name, rtl8127_proc); +#endif + proc_init_num--; + + tp->proc_dir_debug = NULL; + tp->proc_dir_test = NULL; + tp->proc_dir = NULL; + } +} + +#endif //ENABLE_R8127_PROCFS + +#ifdef ENABLE_R8127_SYSFS +/**************************************************************************** +* -----------------------------SYSFS STUFF------------------------- +***************************************************************************** +*/ +static ssize_t testmode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct net_device *netdev = to_net_dev(dev); + struct rtl8127_private *tp = netdev_priv(netdev); + + sprintf(buf, "%u\n", tp->testmode); + + return strlen(buf); +} + +static ssize_t testmode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct net_device *netdev = to_net_dev(dev); + struct rtl8127_private *tp = netdev_priv(netdev); + u32 testmode; + + if (sscanf(buf, "%u\n", &testmode) != 1) + return -EINVAL; + + if (tp->testmode != testmode) { + rtnl_lock(); + tp->testmode = testmode; + rtnl_unlock(); + } + + return count; +} + +static DEVICE_ATTR_RW(testmode); + +static struct attribute *rtk_adv_attrs[] = { + &dev_attr_testmode.attr, + NULL +}; + +static struct attribute_group rtk_adv_grp = { + .name = "rtl_adv", + .attrs = rtk_adv_attrs, +}; + +static void rtl8127_sysfs_init(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int ret; + + /* init rtl_adv */ +#ifdef ENABLE_LIB_SUPPORT + tp->testmode = 0; +#else + tp->testmode = 1; +#endif //ENABLE_LIB_SUPPORT + + ret = sysfs_create_group(&dev->dev.kobj, &rtk_adv_grp); + if (ret < 0) + netif_warn(tp, probe, dev, "create rtk_adv_grp fail\n"); + else + set_bit(R8127_SYSFS_RTL_ADV, tp->sysfs_flag); +} + +static void rtl8127_sysfs_remove(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (test_and_clear_bit(R8127_SYSFS_RTL_ADV, tp->sysfs_flag)) + sysfs_remove_group(&dev->dev.kobj, &rtk_adv_grp); +} +#endif //ENABLE_R8127_SYSFS + +static inline u16 map_phy_ocp_addr(u16 PageNum, u8 RegNum) +{ + u16 OcpPageNum = 0; + u8 OcpRegNum = 0; + u16 OcpPhyAddress = 0; + + if (PageNum == 0) { + OcpPageNum = OCP_STD_PHY_BASE_PAGE + (RegNum / 8); + OcpRegNum = 0x10 + (RegNum % 8); + } else { + OcpPageNum = PageNum; + OcpRegNum = RegNum; + } + + OcpPageNum <<= 4; + + if (OcpRegNum < 16) { + OcpPhyAddress = 0; + } else { + OcpRegNum -= 16; + OcpRegNum <<= 1; + + OcpPhyAddress = OcpPageNum + OcpRegNum; + } + + + return OcpPhyAddress; +} + +static void mdio_real_direct_write_phy_ocp(struct rtl8127_private *tp, + u16 RegAddr, + u16 value) +{ + u32 data32; + int i; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) + WARN_ON_ONCE(RegAddr % 2); +#endif + data32 = RegAddr/2; + data32 <<= OCPR_Addr_Reg_shift; + data32 |= OCPR_Write | value; + + RTL_W32(tp, PHYOCP, data32); + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + udelay(R8127_CHANNEL_WAIT_TIME); + + if (!(RTL_R32(tp, PHYOCP) & OCPR_Flag)) + break; + } +} + +void rtl8127_mdio_direct_write_phy_ocp(struct rtl8127_private *tp, + u16 RegAddr, + u16 value) +{ + if (tp->rtk_enable_diag) + return; + + mdio_real_direct_write_phy_ocp(tp, RegAddr, value); +} + +/* +static void rtl8127_mdio_write_phy_ocp(struct rtl8127_private *tp, + u16 PageNum, + u32 RegAddr, + u32 value) +{ + u16 ocp_addr; + + ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); + + rtl8127_mdio_direct_write_phy_ocp(tp, ocp_addr, value); +} +*/ + +static void rtl8127_mdio_real_write_phy_ocp(struct rtl8127_private *tp, + u16 PageNum, + u32 RegAddr, + u32 value) +{ + u16 ocp_addr; + + ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); + + mdio_real_direct_write_phy_ocp(tp, ocp_addr, value); +} + +static void mdio_real_write(struct rtl8127_private *tp, + u16 RegAddr, + u16 value) +{ + if (RegAddr == 0x1F) { + tp->cur_page = value; + return; + } + rtl8127_mdio_real_write_phy_ocp(tp, tp->cur_page, RegAddr, value); +} + +void rtl8127_mdio_write(struct rtl8127_private *tp, + u16 RegAddr, + u16 value) +{ + if (tp->rtk_enable_diag) + return; + + mdio_real_write(tp, RegAddr, value); +} + +void rtl8127_mdio_prot_write(struct rtl8127_private *tp, + u32 RegAddr, + u32 value) +{ + mdio_real_write(tp, RegAddr, value); +} + +void rtl8127_mdio_prot_direct_write_phy_ocp(struct rtl8127_private *tp, + u32 RegAddr, + u32 value) +{ + mdio_real_direct_write_phy_ocp(tp, RegAddr, value); +} + +static u32 mdio_real_direct_read_phy_ocp(struct rtl8127_private *tp, + u16 RegAddr) +{ + u32 data32; + int i, value = 0; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) + WARN_ON_ONCE(RegAddr % 2); +#endif + data32 = RegAddr/2; + data32 <<= OCPR_Addr_Reg_shift; + + RTL_W32(tp, PHYOCP, data32); + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + udelay(R8127_CHANNEL_WAIT_TIME); + + if (RTL_R32(tp, PHYOCP) & OCPR_Flag) + break; + } + value = RTL_R32(tp, PHYOCP) & OCPDR_Data_Mask; + + return value; +} + +u32 rtl8127_mdio_direct_read_phy_ocp(struct rtl8127_private *tp, + u16 RegAddr) +{ + if (tp->rtk_enable_diag) + return 0xffffffff; + + return mdio_real_direct_read_phy_ocp(tp, RegAddr); +} + +/* +static u32 rtl8127_mdio_read_phy_ocp(struct rtl8127_private *tp, + u16 PageNum, + u32 RegAddr) +{ + u16 ocp_addr; + + ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); + + return rtl8127_mdio_direct_read_phy_ocp(tp, ocp_addr); +} +*/ + +static u32 rtl8127_mdio_real_read_phy_ocp(struct rtl8127_private *tp, + u16 PageNum, + u32 RegAddr) +{ + u16 ocp_addr; + + ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); + + return mdio_real_direct_read_phy_ocp(tp, ocp_addr); +} + +static u32 mdio_real_read(struct rtl8127_private *tp, + u16 RegAddr) +{ + return rtl8127_mdio_real_read_phy_ocp(tp, tp->cur_page, RegAddr); +} + +u32 rtl8127_mdio_read(struct rtl8127_private *tp, + u16 RegAddr) +{ + if (tp->rtk_enable_diag) + return 0xffffffff; + + return mdio_real_read(tp, RegAddr); +} + +u32 rtl8127_mdio_prot_read(struct rtl8127_private *tp, + u32 RegAddr) +{ + return mdio_real_read(tp, RegAddr); +} + +u32 rtl8127_mdio_prot_direct_read_phy_ocp(struct rtl8127_private *tp, + u32 RegAddr) +{ + return mdio_real_direct_read_phy_ocp(tp, RegAddr); +} + +static void rtl8127_clear_and_set_eth_phy_bit(struct rtl8127_private *tp, u8 addr, u16 clearmask, u16 setmask) +{ + u16 PhyRegValue; + + PhyRegValue = rtl8127_mdio_read(tp, addr); + PhyRegValue &= ~clearmask; + PhyRegValue |= setmask; + rtl8127_mdio_write(tp, addr, PhyRegValue); +} + +void rtl8127_clear_eth_phy_bit(struct rtl8127_private *tp, u8 addr, u16 mask) +{ + rtl8127_clear_and_set_eth_phy_bit(tp, + addr, + mask, + 0); +} + +void rtl8127_set_eth_phy_bit(struct rtl8127_private *tp, u8 addr, u16 mask) +{ + rtl8127_clear_and_set_eth_phy_bit(tp, + addr, + 0, + mask); +} + +void rtl8127_clear_and_set_eth_phy_ocp_bit(struct rtl8127_private *tp, u16 addr, u16 clearmask, u16 setmask) +{ + u16 PhyRegValue; + + PhyRegValue = rtl8127_mdio_direct_read_phy_ocp(tp, addr); + PhyRegValue &= ~clearmask; + PhyRegValue |= setmask; + rtl8127_mdio_direct_write_phy_ocp(tp, addr, PhyRegValue); +} + +void rtl8127_clear_eth_phy_ocp_bit(struct rtl8127_private *tp, u16 addr, u16 mask) +{ + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + addr, + mask, + 0); +} + +void rtl8127_set_eth_phy_ocp_bit(struct rtl8127_private *tp, u16 addr, u16 mask) +{ + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + addr, + 0, + mask); +} + +void rtl8127_mac_ocp_write(struct rtl8127_private *tp, u16 reg_addr, u16 value) +{ + u32 data32; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) + WARN_ON_ONCE(reg_addr % 2); +#endif + + data32 = reg_addr/2; + data32 <<= OCPR_Addr_Reg_shift; + data32 += value; + data32 |= OCPR_Write; + + RTL_W32(tp, MACOCP, data32); +} + +u16 rtl8127_mac_ocp_read(struct rtl8127_private *tp, u16 reg_addr) +{ + u32 data32; + u16 data16 = 0; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) + WARN_ON_ONCE(reg_addr % 2); +#endif + + data32 = reg_addr/2; + data32 <<= OCPR_Addr_Reg_shift; + + RTL_W32(tp, MACOCP, data32); + data16 = (u16)RTL_R32(tp, MACOCP); + + return data16; +} + +#ifdef ENABLE_USE_FIRMWARE_FILE +static void mac_mcu_write(struct rtl8127_private *tp, u16 reg, u16 value) +{ + if (reg == 0x1f) { + tp->ocp_base = value << 4; + return; + } + + rtl8127_mac_ocp_write(tp, tp->ocp_base + reg, value); +} + +static u32 mac_mcu_read(struct rtl8127_private *tp, u16 reg) +{ + return rtl8127_mac_ocp_read(tp, tp->ocp_base + reg); +} +#endif + +static void +rtl8127_clear_set_mac_ocp_bit( + struct rtl8127_private *tp, + u16 addr, + u16 clearmask, + u16 setmask +) +{ + u16 PhyRegValue; + + PhyRegValue = rtl8127_mac_ocp_read(tp, addr); + PhyRegValue &= ~clearmask; + PhyRegValue |= setmask; + rtl8127_mac_ocp_write(tp, addr, PhyRegValue); +} + +void +rtl8127_clear_mac_ocp_bit( + struct rtl8127_private *tp, + u16 addr, + u16 mask +) +{ + rtl8127_clear_set_mac_ocp_bit(tp, + addr, + mask, + 0); +} + +static void +rtl8127_set_mac_ocp_bit( + struct rtl8127_private *tp, + u16 addr, + u16 mask +) +{ + rtl8127_clear_set_mac_ocp_bit(tp, + addr, + 0, + mask); +} + +u32 rtl8127_ocp_read_with_oob_base_address(struct rtl8127_private *tp, u16 addr, u8 len, const u32 base_address) +{ + return rtl8127_eri_read_with_oob_base_address(tp, addr, len, ERIAR_OOB, base_address); +} + +u32 rtl8127_ocp_read(struct rtl8127_private *tp, u16 addr, u8 len) +{ + u32 value = 0; + + if (!tp->AllowAccessDashOcp) + return 0xffffffff; + + if (HW_DASH_SUPPORT_TYPE_2(tp)) + value = rtl8127_ocp_read_with_oob_base_address(tp, addr, len, NO_BASE_ADDRESS); + else if (HW_DASH_SUPPORT_TYPE_3(tp)) + value = rtl8127_ocp_read_with_oob_base_address(tp, addr, len, RTL8168FP_OOBMAC_BASE); + + return value; +} + +u32 rtl8127_ocp_write_with_oob_base_address(struct rtl8127_private *tp, u16 addr, u8 len, u32 value, const u32 base_address) +{ + return rtl8127_eri_write_with_oob_base_address(tp, addr, len, value, ERIAR_OOB, base_address); +} + +void rtl8127_ocp_write(struct rtl8127_private *tp, u16 addr, u8 len, u32 value) +{ + if (!tp->AllowAccessDashOcp) + return; + + if (HW_DASH_SUPPORT_TYPE_2(tp)) + rtl8127_ocp_write_with_oob_base_address(tp, addr, len, value, NO_BASE_ADDRESS); + else if (HW_DASH_SUPPORT_TYPE_3(tp)) + rtl8127_ocp_write_with_oob_base_address(tp, addr, len, value, RTL8168FP_OOBMAC_BASE); +} + +void rtl8127_oob_mutex_lock(struct rtl8127_private *tp) +{ + u8 reg_16, reg_a0; + u32 wait_cnt_0, wait_Cnt_1; + u16 ocp_reg_mutex_ib; + u16 ocp_reg_mutex_oob; + u16 ocp_reg_mutex_prio; + + if (!tp->DASH) + return; + + switch (tp->mcfg) { + default: + return; + } + + rtl8127_ocp_write(tp, ocp_reg_mutex_ib, 1, BIT_0); + reg_16 = rtl8127_ocp_read(tp, ocp_reg_mutex_oob, 1); + wait_cnt_0 = 0; + while(reg_16) { + reg_a0 = rtl8127_ocp_read(tp, ocp_reg_mutex_prio, 1); + if (reg_a0) { + rtl8127_ocp_write(tp, ocp_reg_mutex_ib, 1, 0x00); + reg_a0 = rtl8127_ocp_read(tp, ocp_reg_mutex_prio, 1); + wait_Cnt_1 = 0; + while(reg_a0) { + reg_a0 = rtl8127_ocp_read(tp, ocp_reg_mutex_prio, 1); + + wait_Cnt_1++; + + if (wait_Cnt_1 > 2000) + break; + }; + rtl8127_ocp_write(tp, ocp_reg_mutex_ib, 1, BIT_0); + + } + reg_16 = rtl8127_ocp_read(tp, ocp_reg_mutex_oob, 1); + + wait_cnt_0++; + + if (wait_cnt_0 > 2000) + break; + }; +} + +void rtl8127_oob_mutex_unlock(struct rtl8127_private *tp) +{ + //u16 ocp_reg_mutex_ib; + //u16 ocp_reg_mutex_oob; + //u16 ocp_reg_mutex_prio; + + if (!tp->DASH) + return; + + switch (tp->mcfg) { + default: + return; + } + + //rtl8127_ocp_write(tp, ocp_reg_mutex_prio, 1, BIT_0); + //rtl8127_ocp_write(tp, ocp_reg_mutex_ib, 1, 0x00); +} + +static bool +rtl8127_is_allow_access_dash_ocp(struct rtl8127_private *tp) +{ + bool allow_access = false; + + if (!HW_DASH_SUPPORT_DASH(tp)) + goto exit; + + allow_access = true; + switch (tp->mcfg) { + default: + goto exit; + } +exit: + return allow_access; +} + +static int rtl8127_check_dash(struct rtl8127_private *tp) +{ + if (!tp->AllowAccessDashOcp) + return 0; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { + if (rtl8127_ocp_read(tp, 0x128, 1) & BIT_0) + return 1; + } + + return 0; +} + +void rtl8127_dash2_disable_tx(struct rtl8127_private *tp) +{ + if (!tp->DASH) + return; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { + u16 WaitCnt; + u8 TmpUchar; + + //Disable oob Tx + RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) & ~(BIT_0)); + WaitCnt = 0; + + //wait oob tx disable + do { + TmpUchar = RTL_CMAC_R8(tp, CMAC_IBISR0); + + if (TmpUchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE) { + break; + } + + fsleep(50); + WaitCnt++; + } while(WaitCnt < 2000); + + //Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE + RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE); + } +} + +void rtl8127_dash2_enable_tx(struct rtl8127_private *tp) +{ + if (!tp->DASH) + return; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) + RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) | BIT_0); +} + +void rtl8127_dash2_disable_rx(struct rtl8127_private *tp) +{ + if (!tp->DASH) + return; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) + RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) & ~(BIT_0)); +} + +void rtl8127_dash2_enable_rx(struct rtl8127_private *tp) +{ + if (!tp->DASH) + return; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) + RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) | BIT_0); +} + +static void rtl8127_dash2_disable_txrx(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { + rtl8127_dash2_disable_tx(tp); + rtl8127_dash2_disable_rx(tp); + } +} + +static int rtl8127_wait_dash_fw_ready(struct rtl8127_private *tp) +{ + int rc = -1; + int timeout; + + if (HW_DASH_SUPPORT_TYPE_2(tp) == FALSE && + HW_DASH_SUPPORT_TYPE_3(tp) == FALSE) + goto out; + + if (!tp->DASH) + goto out; + + for (timeout = 0; timeout < 10; timeout++) { + fsleep(10000); + if (rtl8127_ocp_read(tp, 0x124, 1) & BIT_0) { + rc = 1; + goto out; + } + } + + rc = 0; + +out: + return rc; +} + +static void rtl8127_driver_start(struct rtl8127_private *tp) +{ + u32 tmp_value; + + if (HW_DASH_SUPPORT_TYPE_2(tp) == FALSE && + HW_DASH_SUPPORT_TYPE_3(tp) == FALSE) + return; + + if (!tp->AllowAccessDashOcp) + return; + + rtl8127_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_START); + tmp_value = rtl8127_ocp_read(tp, 0x30, 1); + tmp_value |= BIT_0; + rtl8127_ocp_write(tp, 0x30, 1, tmp_value); + + rtl8127_wait_dash_fw_ready(tp); +} + +static void rtl8127_driver_stop(struct rtl8127_private *tp) +{ + u32 tmp_value; + struct net_device *dev = tp->dev; + + if (HW_DASH_SUPPORT_TYPE_2(tp) == FALSE && + HW_DASH_SUPPORT_TYPE_3(tp) == FALSE) + return; + + if (!tp->AllowAccessDashOcp) + return; + + rtl8127_dash2_disable_txrx(dev); + + rtl8127_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_STOP); + tmp_value = rtl8127_ocp_read(tp, 0x30, 1); + tmp_value |= BIT_0; + rtl8127_ocp_write(tp, 0x30, 1, tmp_value); + + rtl8127_wait_dash_fw_ready(tp); +} + +static void _rtl8127_ephy_write(struct rtl8127_private *tp, int addr, int data) +{ + int i; + + RTL_W32(tp, EPHYAR, + EPHYAR_Write | + (addr & EPHYAR_Reg_Mask_v2) << EPHYAR_Reg_shift | + (data & EPHYAR_Data_Mask)); + + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + fsleep(R8127_CHANNEL_WAIT_TIME); + + /* Check if the RTL8125 has completed EPHY write */ + if (!(RTL_R32(tp, EPHYAR) & EPHYAR_Flag)) + break; + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); +} + +static void rtl8127_set_ephy_ext_addr(struct rtl8127_private *tp, int addr) +{ + _rtl8127_ephy_write(tp, EPHYAR_EXT_ADDR, addr); +} + +static int rtl8127_check_ephy_ext_addr(struct rtl8127_private *tp, int addr) +{ + int data; + + data = ((u16)addr >> 12); + + rtl8127_set_ephy_ext_addr(tp, data); + + return (addr & 0xfff); +} + +void rtl8127_ephy_write(struct rtl8127_private *tp, int addr, int data) +{ + _rtl8127_ephy_write(tp, rtl8127_check_ephy_ext_addr(tp, addr), data); +} + +static u16 _rtl8127_ephy_read(struct rtl8127_private *tp, int addr) +{ + int i; + u16 data = 0xffff; + + RTL_W32(tp, EPHYAR, + EPHYAR_Read | (addr & EPHYAR_Reg_Mask_v2) << EPHYAR_Reg_shift); + + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + fsleep(R8127_CHANNEL_WAIT_TIME); + + /* Check if the RTL8125 has completed EPHY read */ + if (RTL_R32(tp, EPHYAR) & EPHYAR_Flag) { + data = (u16) (RTL_R32(tp, EPHYAR) & EPHYAR_Data_Mask); + break; + } + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); + + return data; +} + +u16 rtl8127_ephy_read(struct rtl8127_private *tp, int addr) +{ + return _rtl8127_ephy_read(tp, rtl8127_check_ephy_ext_addr(tp, addr)); +} + +/* +static void ClearAndSetPCIePhyBit(struct rtl8127_private *tp, u8 addr, u16 clearmask, u16 setmask) +{ + u16 EphyValue; + + EphyValue = rtl8127_ephy_read(tp, addr); + EphyValue &= ~clearmask; + EphyValue |= setmask; + rtl8127_ephy_write(tp, addr, EphyValue); +} + +static void ClearPCIePhyBit(struct rtl8127_private *tp, u8 addr, u16 mask) +{ + ClearAndSetPCIePhyBit(tp, + addr, + mask, + 0); +} + +static void SetPCIePhyBit(struct rtl8127_private *tp, u8 addr, u16 mask) +{ + ClearAndSetPCIePhyBit(tp, + addr, + 0, + mask); +} +*/ + +static u32 +rtl8127_csi_other_fun_read(struct rtl8127_private *tp, + u8 multi_fun_sel_bit, + u32 addr) +{ + u32 cmd; + int i; + u32 value = 0xffffffff; + + cmd = CSIAR_Read | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask); + + if (tp->mcfg == CFG_METHOD_DEFAULT) + multi_fun_sel_bit = 0; + + if (multi_fun_sel_bit > 7) + goto exit; + + cmd |= multi_fun_sel_bit << 16; + + RTL_W32(tp, CSIAR, cmd); + + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + fsleep(R8127_CHANNEL_WAIT_TIME); + + /* Check if the RTL8125 has completed CSI read */ + if (RTL_R32(tp, CSIAR) & CSIAR_Flag) { + value = (u32)RTL_R32(tp, CSIDR); + break; + } + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); + +exit: + return value; +} + +static void +rtl8127_csi_other_fun_write(struct rtl8127_private *tp, + u8 multi_fun_sel_bit, + u32 addr, + u32 value) +{ + u32 cmd; + int i; + + RTL_W32(tp, CSIDR, value); + cmd = CSIAR_Write | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask); + if (tp->mcfg == CFG_METHOD_DEFAULT) + multi_fun_sel_bit = 0; + + if (multi_fun_sel_bit > 7) + return; + + cmd |= multi_fun_sel_bit << 16; + + RTL_W32(tp, CSIAR, cmd); + + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + fsleep(R8127_CHANNEL_WAIT_TIME); + + /* Check if the RTL8125 has completed CSI write */ + if (!(RTL_R32(tp, CSIAR) & CSIAR_Flag)) + break; + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); +} + +static u32 +rtl8127_csi_read(struct rtl8127_private *tp, + u32 addr) +{ + u8 multi_fun_sel_bit; + + multi_fun_sel_bit = 0; + + return rtl8127_csi_other_fun_read(tp, multi_fun_sel_bit, addr); +} + +static void +rtl8127_csi_write(struct rtl8127_private *tp, + u32 addr, + u32 value) +{ + u8 multi_fun_sel_bit; + + multi_fun_sel_bit = 0; + + rtl8127_csi_other_fun_write(tp, multi_fun_sel_bit, addr, value); +} + +static u8 +rtl8127_csi_fun0_read_byte(struct rtl8127_private *tp, + u32 addr) +{ + u8 RetVal = 0; + + if (tp->mcfg == CFG_METHOD_DEFAULT) { + struct pci_dev *pdev = tp->pci_dev; + + pci_read_config_byte(pdev, addr, &RetVal); + } else { + u32 TmpUlong; + u16 RegAlignAddr; + u8 ShiftByte; + + RegAlignAddr = addr & ~(0x3); + ShiftByte = addr & (0x3); + TmpUlong = rtl8127_csi_other_fun_read(tp, 0, RegAlignAddr); + TmpUlong >>= (8*ShiftByte); + RetVal = (u8)TmpUlong; + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); + + return RetVal; +} + +static void +rtl8127_csi_fun0_write_byte(struct rtl8127_private *tp, + u32 addr, + u8 value) +{ + if (tp->mcfg == CFG_METHOD_DEFAULT) { + struct pci_dev *pdev = tp->pci_dev; + + pci_write_config_byte(pdev, addr, value); + } else { + u32 TmpUlong; + u16 RegAlignAddr; + u8 ShiftByte; + + RegAlignAddr = addr & ~(0x3); + ShiftByte = addr & (0x3); + TmpUlong = rtl8127_csi_other_fun_read(tp, 0, RegAlignAddr); + TmpUlong &= ~(0xFF << (8*ShiftByte)); + TmpUlong |= (value << (8*ShiftByte)); + rtl8127_csi_other_fun_write(tp, 0, RegAlignAddr, TmpUlong); + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); +} + +u32 rtl8127_eri_read_with_oob_base_address(struct rtl8127_private *tp, int addr, int len, int type, const u32 base_address) +{ + int i, val_shift, shift = 0; + u32 value1 = 0, value2 = 0, mask; + u32 eri_cmd; + const u32 transformed_base_address = ((base_address & 0x00FFF000) << 6) | (base_address & 0x000FFF); + + if (len > 4 || len <= 0) + return -1; + + while (len > 0) { + val_shift = addr % ERIAR_Addr_Align; + addr = addr & ~0x3; + + eri_cmd = ERIAR_Read | + transformed_base_address | + type << ERIAR_Type_shift | + ERIAR_ByteEn << ERIAR_ByteEn_shift | + (addr & 0x0FFF); + if (addr & 0xF000) { + u32 tmp; + + tmp = addr & 0xF000; + tmp >>= 12; + eri_cmd |= (tmp << 20) & 0x00F00000; + } + + RTL_W32(tp, ERIAR, eri_cmd); + + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + fsleep(R8127_CHANNEL_WAIT_TIME); + + /* Check if the RTL8125 has completed ERI read */ + if (RTL_R32(tp, ERIAR) & ERIAR_Flag) + break; + } + + if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + + value1 = RTL_R32(tp, ERIDR) & mask; + value2 |= (value1 >> val_shift * 8) << shift * 8; + + if (len <= 4 - val_shift) { + len = 0; + } else { + len -= (4 - val_shift); + shift = 4 - val_shift; + addr += 4; + } + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); + + return value2; +} + +u32 rtl8127_eri_read(struct rtl8127_private *tp, int addr, int len, int type) +{ + return rtl8127_eri_read_with_oob_base_address(tp, addr, len, type, 0); +} + +int rtl8127_eri_write_with_oob_base_address(struct rtl8127_private *tp, int addr, int len, u32 value, int type, const u32 base_address) +{ + int i, val_shift, shift = 0; + u32 value1 = 0, mask; + u32 eri_cmd; + const u32 transformed_base_address = ((base_address & 0x00FFF000) << 6) | (base_address & 0x000FFF); + + if (len > 4 || len <= 0) + return -1; + + while (len > 0) { + val_shift = addr % ERIAR_Addr_Align; + addr = addr & ~0x3; + + if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF; + + value1 = rtl8127_eri_read_with_oob_base_address(tp, addr, 4, type, base_address) & ~mask; + value1 |= ((value << val_shift * 8) >> shift * 8); + + RTL_W32(tp, ERIDR, value1); + + eri_cmd = ERIAR_Write | + transformed_base_address | + type << ERIAR_Type_shift | + ERIAR_ByteEn << ERIAR_ByteEn_shift | + (addr & 0x0FFF); + if (addr & 0xF000) { + u32 tmp; + + tmp = addr & 0xF000; + tmp >>= 12; + eri_cmd |= (tmp << 20) & 0x00F00000; + } + + RTL_W32(tp, ERIAR, eri_cmd); + + for (i = 0; i < R8127_CHANNEL_WAIT_COUNT; i++) { + fsleep(R8127_CHANNEL_WAIT_TIME); + + /* Check if the RTL8125 has completed ERI write */ + if (!(RTL_R32(tp, ERIAR) & ERIAR_Flag)) + break; + } + + if (len <= 4 - val_shift) { + len = 0; + } else { + len -= (4 - val_shift); + shift = 4 - val_shift; + addr += 4; + } + } + + fsleep(R8127_CHANNEL_EXIT_DELAY_TIME); + + return 0; +} + +int rtl8127_eri_write(struct rtl8127_private *tp, int addr, int len, u32 value, int type) +{ + return rtl8127_eri_write_with_oob_base_address(tp, addr, len, value, type, NO_BASE_ADDRESS); +} + +static void +rtl8127_enable_rxdvgate(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_3); +} + +static void +rtl8127_disable_rxdvgate(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_3); +} + +static u8 +rtl8127_is_gpio_low(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u8 gpio_low = FALSE; + + switch (tp->HwSuppCheckPhyDisableModeVer) { + case 3: + if (!(rtl8127_mac_ocp_read(tp, 0xDC04) & BIT_13)) + gpio_low = TRUE; + break; + } + + if (gpio_low) + dprintk("gpio is low.\n"); + + return gpio_low; +} + +static u8 +rtl8127_is_phy_disable_mode_enabled(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u8 phy_disable_mode_enabled = FALSE; + + switch (tp->HwSuppCheckPhyDisableModeVer) { + case 3: + if (RTL_R8(tp, 0xF2) & BIT_5) + phy_disable_mode_enabled = TRUE; + break; + } + + if (phy_disable_mode_enabled) + dprintk("phy disable mode enabled.\n"); + + return phy_disable_mode_enabled; +} + +static u8 +rtl8127_is_in_phy_disable_mode(struct net_device *dev) +{ + u8 in_phy_disable_mode = FALSE; + + if (rtl8127_is_phy_disable_mode_enabled(dev) && rtl8127_is_gpio_low(dev)) + in_phy_disable_mode = TRUE; + + if (in_phy_disable_mode) + dprintk("Hardware is in phy disable mode.\n"); + + return in_phy_disable_mode; +} + +static void +rtl8127_stop_all_request(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); + fsleep(200); +} + +static void +rtl8127_clear_stop_all_request(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & (CmdTxEnb | CmdRxEnb)); +} + +void +rtl8127_wait_txrx_fifo_empty(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + /* Txfifo_empty require StopReq been set */ + for (i = 0; i < 3000; i++) { + fsleep(50); + if ((RTL_R8(tp, MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty)) + break; + } + + for (i = 0; i < 3000; i++) { + fsleep(50); + if ((RTL_R16(tp, IntrMitigate) & (BIT_0 | BIT_1 | BIT_8)) == (BIT_0 | BIT_1 | BIT_8)) + break; + } +} + +#ifdef ENABLE_DASH_SUPPORT + +static inline void +rtl8127_enable_dash2_interrupt(struct rtl8127_private *tp) +{ + if (!tp->DASH) + return; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) + RTL_CMAC_W8(tp, CMAC_IBIMR0, (ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE)); +} + +static inline void +rtl8127_disable_dash2_interrupt(struct rtl8127_private *tp) +{ + if (!tp->DASH) + return; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) + RTL_CMAC_W8(tp, CMAC_IBIMR0, 0); +} +#endif + +void +rtl8127_enable_hw_linkchg_interrupt(struct rtl8127_private *tp) +{ + switch (tp->HwCurrIsrVer) { + case 6: + RTL_W32(tp, IMR_V2_SET_REG_8125, ISRIMR_V6_LINKCHG); + break; + case 5: + RTL_W32(tp, IMR_V2_SET_REG_8125, ISRIMR_V5_LINKCHG); + break; + case 4: + RTL_W32(tp, IMR_V2_SET_REG_8125, ISRIMR_V4_LINKCHG); + break; + case 2: + case 3: + RTL_W32(tp, IMR_V2_SET_REG_8125, ISRIMR_V2_LINKCHG); + break; + case 1: + RTL_W32(tp, tp->imr_reg[0], LinkChg | RTL_R32(tp, tp->imr_reg[0])); + break; + } + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + rtl8127_enable_dash2_interrupt(tp); +#endif +} + +static inline void +rtl8127_enable_hw_interrupt(struct rtl8127_private *tp) +{ + switch (tp->HwCurrIsrVer) { + case 2: + case 3: + case 4: + case 5: + case 6: + RTL_W32(tp, IMR_V2_SET_REG_8125, tp->intr_mask); + break; + case 1: + RTL_W32(tp, tp->imr_reg[0], tp->intr_mask); + + if (R8127_MULTI_RX_Q(tp)) { + int i; + for (i=1; inum_rx_rings; i++) + RTL_W16(tp, tp->imr_reg[i], other_q_intr_mask); + } + break; + } + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + rtl8127_enable_dash2_interrupt(tp); +#endif +} + +static inline void rtl8127_clear_hw_isr_v2(struct rtl8127_private *tp, + u32 message_id) +{ + RTL_W32(tp, ISR_V2_8125, BIT(message_id)); +} + +static inline void +rtl8127_disable_hw_interrupt(struct rtl8127_private *tp) +{ + if (tp->HwCurrIsrVer > 1) { + RTL_W32(tp, IMR_V2_CLEAR_REG_8125, 0xFFFFFFFF); + if (tp->HwCurrIsrVer > 3) + RTL_W32(tp, IMR_V4_L2_CLEAR_REG_8125, 0xFFFFFFFF); + } else { + RTL_W32(tp, tp->imr_reg[0], 0x0000); + + if (R8127_MULTI_RX_Q(tp)) { + int i; + for (i=1; inum_rx_rings; i++) + RTL_W16(tp, tp->imr_reg[i], 0); + } + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + rtl8127_disable_dash2_interrupt(tp); +#endif + } +} + +static inline void +rtl8127_switch_to_hw_interrupt(struct rtl8127_private *tp) +{ + RTL_W32(tp, TIMER_INT0_8125, 0x0000); + + rtl8127_enable_hw_interrupt(tp); +} + +static inline void +rtl8127_switch_to_timer_interrupt(struct rtl8127_private *tp) +{ + if (tp->use_timer_interrupt) { + RTL_W32(tp, TIMER_INT0_8125, timer_count); + RTL_W32(tp, TCTR0_8125, timer_count); + RTL_W32(tp, tp->imr_reg[0], tp->timer_intr_mask); + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + rtl8127_enable_dash2_interrupt(tp); +#endif + } else { + rtl8127_switch_to_hw_interrupt(tp); + } +} + +static void +rtl8127_irq_mask_and_ack(struct rtl8127_private *tp) +{ + rtl8127_disable_hw_interrupt(tp); + + if (tp->HwCurrIsrVer > 1) { + RTL_W32(tp, ISR_V2_8125, 0xFFFFFFFF); + if (tp->HwCurrIsrVer > 3) + RTL_W32(tp, ISR_V4_L2_8125, 0xFFFFFFFF); + } else { +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) { + if (tp->dash_printer_enabled) { + RTL_W32(tp, tp->isr_reg[0], RTL_R32(tp, tp->isr_reg[0]) & + ~(ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); + } else { + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { + RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0)); + } + } + } else { + RTL_W32(tp, tp->isr_reg[0], RTL_R32(tp, tp->isr_reg[0])); + } +#else + RTL_W32(tp, tp->isr_reg[0], RTL_R32(tp, tp->isr_reg[0])); +#endif + if (R8127_MULTI_RX_Q(tp)) { + int i; + for (i=1; inum_rx_rings; i++) + RTL_W16(tp, tp->isr_reg[i], RTL_R16(tp, tp->isr_reg[i])); + } + } +} + +static void +rtl8127_disable_rx_packet_filter(struct rtl8127_private *tp) +{ + + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & + ~(AcceptErr | AcceptRunt |AcceptBroadcast | AcceptMulticast | + AcceptMyPhys | AcceptAllPhys)); +} + +static void +rtl8127_nic_reset(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + rtl8127_disable_rx_packet_filter(tp); + + rtl8127_enable_rxdvgate(dev); + + rtl8127_stop_all_request(dev); + + rtl8127_wait_txrx_fifo_empty(dev); + + rtl8127_clear_stop_all_request(dev); + + /* Soft reset the chip. */ + RTL_W8(tp, ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 100; i > 0; i--) { + fsleep(100); + if ((RTL_R8(tp, ChipCmd) & CmdReset) == 0) + break; + } + + /* reset rcr */ + RTL_W32(tp, RxConfig, (RX_DMA_BURST_512 << RxCfgDMAShift)); +} + +static void +rtl8127_hw_set_interrupt_type(struct rtl8127_private *tp, u8 isr_ver) +{ + u8 tmp; + + if (tp->HwSuppIsrVer < 2) + return; + + tmp = RTL_R8(tp, INT_CFG0_8125); + + switch (tp->HwSuppIsrVer) { + case 6: + tmp &= ~INT_CFG0_AVOID_MISS_INTR; + fallthrough; + case 4: + case 5: + if (tp->HwSuppIsrVer == 6) + tmp &= ~INT_CFG0_AUTO_CLEAR_IMR; + else + tmp &= ~INT_CFG0_MSIX_ENTRY_NUM_MODE; + fallthrough; + case 2: + case 3: + tmp &= ~(INT_CFG0_ENABLE_8125); + if (isr_ver > 1) + tmp |= INT_CFG0_ENABLE_8125; + break; + default: + return; + } + + RTL_W8(tp, INT_CFG0_8125, tmp); +} + +static void +rtl8127_hw_clear_timer_int(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + RTL_W32(tp, TIMER_INT0_8125, 0x0000); + RTL_W32(tp, TIMER_INT1_8125, 0x0000); + RTL_W32(tp, TIMER_INT2_8125, 0x0000); + RTL_W32(tp, TIMER_INT3_8125, 0x0000); +} + +static void +rtl8127_hw_clear_int_miti(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + switch (tp->HwSuppIntMitiVer) { + case 3: + case 6: + //IntMITI_0-IntMITI_31 + for (i=0xA00; i<0xB00; i+=4) + RTL_W32(tp, i, 0x0000); + break; + case 4: + case 5: + //IntMITI_0-IntMITI_15 + for (i = 0xA00; i < 0xA80; i += 4) + RTL_W32(tp, i, 0x0000); + + if (tp->HwSuppIntMitiVer == 5) + RTL_W8(tp, INT_CFG0_8125, RTL_R8(tp, INT_CFG0_8125) & + ~(INT_CFG0_TIMEOUT0_BYPASS_8125 | + INT_CFG0_MITIGATION_BYPASS_8125 | + INT_CFG0_RDU_BYPASS_8126)); + else + RTL_W8(tp, INT_CFG0_8125, RTL_R8(tp, INT_CFG0_8125) & + ~(INT_CFG0_TIMEOUT0_BYPASS_8125 | INT_CFG0_MITIGATION_BYPASS_8125)); + + RTL_W16(tp, INT_CFG1_8125, 0x0000); + break; + } +} + +static bool +rtl8127_vec_2_tx_q_num( + struct rtl8127_private *tp, + u32 messageId, + u32 *qnum +) +{ + u32 whichQ = 0xffffffff; + bool rc = false; + + switch (tp->HwSuppIsrVer) { + case 2: + if (messageId == 0x10) + whichQ = 0; + else if (messageId == 0x12 && tp->num_tx_rings > 1) + whichQ = 1; + break; + case 3: + case 4: + if (messageId == 0x00) + whichQ = 0; + else if (messageId == 0x01 && tp->num_tx_rings > 1) + whichQ = 1; + break; + case 5: + if (messageId == 0x10) + whichQ = 0; + else if (messageId == 0x11 && tp->num_tx_rings > 1) + whichQ = 1; + break; + case 6: + if (messageId == 0x08) + whichQ = 0; + else if (messageId == 0x09 && tp->num_tx_rings > 1) + whichQ = 1; + break; + case 7: + if (messageId == 0x1B) + whichQ = 0; + else if (messageId == 0x1C && tp->num_tx_rings > 1) + whichQ = 1; + break; + } + + if (whichQ != 0xffffffff) { + *qnum = whichQ; + rc = true; + } + + return rc; +} + +static bool +rtl8127_vec_2_rx_q_num( + struct rtl8127_private *tp, + u32 messageId, + u32 *qnum +) +{ + u32 whichQ = 0xffffffff; + bool rc = false; + + switch (tp->HwSuppIsrVer) { + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + if (messageId < tp->HwSuppNumRxQueues) + whichQ = messageId; + break; + } + + if (whichQ != 0xffffffff) { + *qnum = whichQ; + rc = true; + } + + return rc; +} + +void +rtl8127_hw_set_timer_int(struct rtl8127_private *tp, + u32 message_id, + u8 timer_intmiti_val) +{ + u32 qnum; + + switch (tp->HwSuppIntMitiVer) { + case 4: + case 5: + case 6: + //ROK + if (rtl8127_vec_2_rx_q_num(tp, message_id, &qnum)) + RTL_W8(tp,INT_MITI_V2_0_RX + 8 * qnum, timer_intmiti_val); + //TOK + if (rtl8127_vec_2_tx_q_num(tp, message_id, &qnum)) + RTL_W8(tp,INT_MITI_V2_0_TX + 8 * qnum, timer_intmiti_val); + break; + } +} + +void +rtl8127_hw_reset(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_lib_reset_prepare(tp); + + /* Disable interrupts */ + rtl8127_irq_mask_and_ack(tp); + + rtl8127_hw_clear_timer_int(dev); + + rtl8127_nic_reset(dev); +} + +static unsigned int +rtl8127_xmii_reset_pending(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned int retval; + unsigned long flags; + + spin_lock_irqsave(&tp->phy_lock, flags); + rtl8127_mdio_write(tp, 0x1f, 0x0000); + retval = rtl8127_mdio_read(tp, MII_BMCR) & BMCR_RESET; + spin_unlock_irqrestore(&tp->phy_lock, flags); + + return retval; +} + +static unsigned int +rtl8127_xmii_link_ok(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u16 status; + + status = RTL_R16(tp, PHYstatus); + if (status == 0xffff) + return 0; + + return (status & LinkStatus) ? 1 : 0; +} + +static int +rtl8127_wait_phy_reset_complete(struct rtl8127_private *tp) +{ + int i, val; + + for (i = 0; i < 2500; i++) { + val = rtl8127_mdio_read(tp, MII_BMCR) & BMCR_RESET; + if (!val) + return 0; + + mdelay(1); + } + + return -1; +} + +static void +rtl8127_xmii_reset_enable(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long flags; + int ret; + + if (rtl8127_is_in_phy_disable_mode(dev)) + return; + + spin_lock_irqsave(&tp->phy_lock, flags); + + rtl8127_mdio_write(tp, 0x1f, 0x0000); + rtl8127_mdio_write(tp, MII_ADVERTISE, rtl8127_mdio_read(tp, MII_ADVERTISE) & + ~(ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL)); + rtl8127_mdio_write(tp, MII_CTRL1000, rtl8127_mdio_read(tp, MII_CTRL1000) & + ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL)); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA5D4, rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5D4) & + ~(RTK_ADVERTISE_2500FULL | RTK_ADVERTISE_5000FULL | + RTK_ADVERTISE_10000FULL)); + rtl8127_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); + + ret = rtl8127_wait_phy_reset_complete(tp); + + spin_unlock_irqrestore(&tp->phy_lock, flags); + + if (ret != 0 && netif_msg_link(tp)) + printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); +} + +void +rtl8127_init_ring_indexes(struct rtl8127_private *tp) +{ + int i; + + for (i = 0; i < tp->HwSuppNumTxQueues; i++) { + struct rtl8127_tx_ring *ring = &tp->tx_ring[i]; + ring->dirty_tx = ring->cur_tx = 0; + ring->NextHwDesCloPtr = 0; + ring->BeginHwDesCloPtr = 0; + ring->index = i; + ring->priv = tp; + ring->netdev = tp->dev; + + /* reset BQL for queue */ + netdev_tx_reset_queue(txring_txq(ring)); + } + + for (i = 0; i < tp->HwSuppNumRxQueues; i++) { + struct rtl8127_rx_ring *ring = &tp->rx_ring[i]; + ring->dirty_rx = ring->cur_rx = 0; + ring->index = i; + ring->priv = tp; + ring->netdev = tp->dev; + } + +#ifdef ENABLE_LIB_SUPPORT + for (i = 0; i < tp->HwSuppNumTxQueues; i++) { + struct rtl8127_ring *ring = &tp->lib_tx_ring[i]; + ring->direction = RTL8127_CH_DIR_TX; + ring->queue_num = i; + ring->private = tp; + } + + for (i = 0; i < tp->HwSuppNumRxQueues; i++) { + struct rtl8127_ring *ring = &tp->lib_rx_ring[i]; + ring->direction = RTL8127_CH_DIR_RX; + ring->queue_num = i; + ring->private = tp; + } +#endif +} + +static void +rtl8127_issue_offset_99_event(struct rtl8127_private *tp) +{ + rtl8127_mac_ocp_write(tp, 0xE09A, rtl8127_mac_ocp_read(tp, 0xE09A) | BIT_0); +} + +#ifdef ENABLE_DASH_SUPPORT +static void +NICChkTypeEnableDashInterrupt(struct rtl8127_private *tp) +{ + if (tp->DASH) { + // + // even disconnected, enable 3 dash interrupt mask bits for in-band/out-band communication + // + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { + rtl8127_enable_dash2_interrupt(tp); + RTL_W16(tp, IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); + } + } +} +#endif + +static int rtl8127_enable_eee_plus(struct rtl8127_private *tp) +{ + rtl8127_mac_ocp_write(tp, 0xE080, rtl8127_mac_ocp_read(tp, 0xE080)|BIT_1); + + return 0; +} + +static int rtl8127_disable_eee_plus(struct rtl8127_private *tp) +{ + rtl8127_mac_ocp_write(tp, 0xE080, rtl8127_mac_ocp_read(tp, 0xE080)&~BIT_1); + + return 0; +} + +static void rtl8127_enable_double_vlan(struct rtl8127_private *tp) +{ + RTL_W16(tp, DOUBLE_VLAN_CONFIG, 0xf002); +} + +static void rtl8127_disable_double_vlan(struct rtl8127_private *tp) +{ + RTL_W16(tp, DOUBLE_VLAN_CONFIG, 0); +} + +static void +rtl8127_link_on_patch(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long flags; + + rtl8127_hw_config(dev); + + if (RTL_R8(tp, PHYstatus) & _10bps) + rtl8127_enable_eee_plus(tp); + + rtl8127_hw_start(dev); + + netif_carrier_on(dev); + + netif_tx_wake_all_queues(dev); + + spin_lock_irqsave(&tp->phy_lock, flags); + tp->phy_reg_aner = rtl8127_mdio_read(tp, MII_EXPANSION); + tp->phy_reg_anlpar = rtl8127_mdio_read(tp, MII_LPA); + tp->phy_reg_gbsr = rtl8127_mdio_read(tp, MII_STAT1000); + tp->phy_reg_status_2500 = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5D6); + spin_unlock_irqrestore(&tp->phy_lock, flags); + +#ifdef ENABLE_PTP_SUPPORT + if (tp->EnablePtp) + rtl8127_set_local_time(tp); +#endif // ENABLE_PTP_SUPPORT +} + +static void +rtl8127_link_down_patch(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + tp->phy_reg_aner = 0; + tp->phy_reg_anlpar = 0; + tp->phy_reg_gbsr = 0; + tp->phy_reg_status_2500 = 0; + + rtl8127_disable_eee_plus(tp); + + netif_carrier_off(dev); + + netif_tx_disable(dev); + + rtl8127_hw_reset(dev); + + rtl8127_tx_clear(tp); + + rtl8127_rx_clear(tp); + + rtl8127_init_ring(dev); + + rtl8127_enable_hw_linkchg_interrupt(tp); + + //rtl8127_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + NICChkTypeEnableDashInterrupt(tp); +#endif +} + +static void +_rtl8127_check_link_status(struct net_device *dev, unsigned int link_state) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (link_state != R8127_LINK_STATE_OFF && + link_state != R8127_LINK_STATE_ON) + link_state = tp->link_ok(dev); + + if (link_state == R8127_LINK_STATE_ON) { + rtl8127_link_on_patch(dev); + + if (netif_msg_ifup(tp)) + printk(KERN_INFO PFX "%s: link up\n", dev->name); + } else { + if (netif_msg_ifdown(tp)) + printk(KERN_INFO PFX "%s: link down\n", dev->name); + + rtl8127_link_down_patch(dev); + } +} + +static void +rtl8127_check_link_status(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned int link_status_on; + + tp->resume_not_chg_speed = 0; + + link_status_on = tp->link_ok(dev); + if (netif_carrier_ok(dev) == link_status_on) + return; + + _rtl8127_check_link_status(dev, link_status_on); +} + +static bool +rtl8127_is_autoneg_mode_valid(u32 autoneg) +{ + switch(autoneg) { + case AUTONEG_ENABLE: + case AUTONEG_DISABLE: + return true; + default: + return false; + } +} + +static bool +rtl8127_is_speed_mode_valid(u32 speed) +{ + switch(speed) { + case SPEED_10000: + case SPEED_5000: + case SPEED_2500: + case SPEED_1000: + case SPEED_100: + case SPEED_10: + return true; + default: + return false; + } +} + +static bool +rtl8127_is_duplex_mode_valid(u8 duplex) +{ + switch(duplex) { + case DUPLEX_FULL: + case DUPLEX_HALF: + return true; + default: + return false; + } +} + +static void +rtl8127_set_link_option(struct rtl8127_private *tp, + u8 autoneg, + u32 speed, + u8 duplex, + enum rtl8127_fc_mode fc) +{ + u64 adv; + + if (!rtl8127_is_speed_mode_valid(speed)) + speed = SPEED_10000; + + if (!rtl8127_is_duplex_mode_valid(duplex)) + duplex = DUPLEX_FULL; + + if (!rtl8127_is_autoneg_mode_valid(autoneg)) + autoneg = AUTONEG_ENABLE; + + speed = min(speed, tp->HwSuppMaxPhyLinkSpeed); + + adv = 0; + switch(speed) { + case SPEED_10000: + adv |= ADVERTISED_10000baseT_Full; + fallthrough; + case SPEED_5000: + adv |= RTK_ADVERTISED_5000baseX_Full; + fallthrough; + case SPEED_2500: + adv |= ADVERTISED_2500baseX_Full; + fallthrough; + default: + adv |= (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | + ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); + break; + } + + tp->autoneg = autoneg; + tp->speed = speed; + tp->duplex = duplex; + tp->advertising = adv; + tp->fcpause = fc; +} + +static void +rtl8127_wait_ll_share_fifo_ready(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + for (i = 0; i < 10; i++) { + fsleep(100); + if (RTL_R16(tp, 0xD2) & BIT_9) + break; + } +} + +static void +rtl8127_disable_pci_offset_99(struct rtl8127_private *tp) +{ + rtl8127_mac_ocp_write(tp, 0xE032, rtl8127_mac_ocp_read(tp, 0xE032) & ~(BIT_0 | BIT_1)); + + rtl8127_csi_fun0_write_byte(tp, 0x99, 0x00); +} + +static void +rtl8127_enable_pci_offset_99(struct rtl8127_private *tp) +{ + u32 csi_tmp; + + rtl8127_csi_fun0_write_byte(tp, 0x99, tp->org_pci_offset_99); + + csi_tmp = rtl8127_mac_ocp_read(tp, 0xE032); + csi_tmp &= ~(BIT_0 | BIT_1); + if (tp->org_pci_offset_99 & (BIT_5 | BIT_6)) + csi_tmp |= BIT_1; + if (tp->org_pci_offset_99 & BIT_2) + csi_tmp |= BIT_0; + rtl8127_mac_ocp_write(tp, 0xE032, csi_tmp); +} + +static void +rtl8127_init_pci_offset_99(struct rtl8127_private *tp) +{ + rtl8127_mac_ocp_write(tp, 0xCDD0, 0x9003); + rtl8127_set_mac_ocp_bit(tp, 0xE034, (BIT_15 | BIT_14)); + rtl8127_mac_ocp_write(tp, 0xCDD2, 0x8C17); + rtl8127_mac_ocp_write(tp, 0xCDD8, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDD4, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDDA, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDD6, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDDC, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDE8, 0x8C08); + rtl8127_mac_ocp_write(tp, 0xCDEA, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDEC, 0x8C12); + rtl8127_mac_ocp_write(tp, 0xCDEE, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDF0, 0x8C2E); + rtl8127_mac_ocp_write(tp, 0xCDF2, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDF4, 0x8892); + rtl8127_mac_ocp_write(tp, 0xCDF6, 0x9003); + rtl8127_mac_ocp_write(tp, 0xCDF4, 0x8849); + rtl8127_mac_ocp_write(tp, 0xCDF6, 0x9003); + rtl8127_set_mac_ocp_bit(tp, 0xE032, BIT_14); + rtl8127_set_mac_ocp_bit(tp, 0xE0A2, BIT_0); + + rtl8127_enable_pci_offset_99(tp); +} + +static void +rtl8127_disable_pci_offset_180(struct rtl8127_private *tp) +{ + rtl8127_clear_mac_ocp_bit(tp, 0xE092, 0x00FF); +} + +static void +rtl8127_enable_pci_offset_180(struct rtl8127_private *tp) +{ + rtl8127_clear_mac_ocp_bit(tp, 0xE094, 0xFF00); + + rtl8127_clear_set_mac_ocp_bit(tp, 0xE092, 0x00FF, BIT_2); +} + +static void +rtl8127_init_pci_offset_180(struct rtl8127_private *tp) +{ + rtl8127_enable_pci_offset_180(tp); +} + +static void +rtl8127_set_pci_99_exit_driver_para(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->org_pci_offset_99 & BIT_2) + rtl8127_issue_offset_99_event(tp); + rtl8127_disable_pci_offset_99(tp); +} + +static void +rtl8127_enable_cfg9346_write(struct rtl8127_private *tp) +{ + RTL_W8(tp, Cfg9346, RTL_R8(tp, Cfg9346) | Cfg9346_Unlock); +} + +static void +rtl8127_disable_cfg9346_write(struct rtl8127_private *tp) +{ + RTL_W8(tp, Cfg9346, RTL_R8(tp, Cfg9346) & ~Cfg9346_Unlock); +} + +static void +rtl8127_enable_exit_l1_mask(struct rtl8127_private *tp) +{ + //(1)ERI(0xD4)(OCP 0xC0AC).bit[7:12]=6'b111111, L1 Mask + rtl8127_set_mac_ocp_bit(tp, 0xC0AC, (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12)); +} + +static void +rtl8127_disable_exit_l1_mask(struct rtl8127_private *tp) +{ + //(1)ERI(0xD4)(OCP 0xC0AC).bit[7:12]=6'b000000, L1 Mask + rtl8127_clear_mac_ocp_bit(tp, 0xC0AC, (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12)); +} + +static void +rtl8127_enable_extend_tally_couter(struct rtl8127_private *tp) +{ + switch (tp->HwSuppExtendTallyCounterVer) { + case 1: + rtl8127_set_mac_ocp_bit(tp, 0xEA84, (BIT_1 | BIT_0)); + break; + } +} + +static void +rtl8127_disable_extend_tally_couter(struct rtl8127_private *tp) +{ + switch (tp->HwSuppExtendTallyCounterVer) { + case 1: + rtl8127_clear_mac_ocp_bit(tp, 0xEA84, (BIT_1 | BIT_0)); + break; + } +} + +static void +rtl8127_enable_force_clkreq(struct rtl8127_private *tp, bool enable) +{ + if (enable) + RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7); + else + RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); +} + +static void +rtl8127_enable_aspm_clkreq_lock(struct rtl8127_private *tp, bool enable) +{ + bool unlock_cfg_wr; + + if ((RTL_R8(tp, Cfg9346) & Cfg9346_EEM_MASK) == Cfg9346_Unlock) + unlock_cfg_wr = false; + else + unlock_cfg_wr = true; + + if (unlock_cfg_wr) + rtl8127_enable_cfg9346_write(tp); + + if (enable) { + RTL_W8(tp, INT_CFG0_8125, RTL_R8(tp, INT_CFG0_8125) | BIT_3); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) | BIT_0); + } else { + RTL_W8(tp, INT_CFG0_8125, RTL_R8(tp, INT_CFG0_8125) & ~BIT_3); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); + } + + if (unlock_cfg_wr) + rtl8127_disable_cfg9346_write(tp); +} + +static void +rtl8127_hw_d3_para(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + RTL_W16(tp, RxMaxSize, RX_BUF_SIZE); + + rtl8127_enable_force_clkreq(tp, 0); + rtl8127_enable_aspm_clkreq_lock(tp, 0); + + rtl8127_disable_exit_l1_mask(tp); + +#ifdef ENABLE_REALWOW_SUPPORT + rtl8127_set_realwow_d3_para(dev); +#endif + + rtl8127_set_pci_99_exit_driver_para(dev); + + rtl8127_disable_rxdvgate(dev); + + rtl8127_disable_extend_tally_couter(tp); +} + +static void +rtl8127_enable_magic_packet(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + switch (tp->HwSuppMagicPktVer) { + case WAKEUP_MAGIC_PACKET_V3: + rtl8127_mac_ocp_write(tp, 0xC0B6, rtl8127_mac_ocp_read(tp, 0xC0B6) | BIT_0); + break; + } +} +static void +rtl8127_disable_magic_packet(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + switch (tp->HwSuppMagicPktVer) { + case WAKEUP_MAGIC_PACKET_V3: + rtl8127_mac_ocp_write(tp, 0xC0B6, rtl8127_mac_ocp_read(tp, 0xC0B6) & ~BIT_0); + break; + } +} + +static void +rtl8127_enable_linkchg_wakeup(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + switch (tp->HwSuppLinkChgWakeUpVer) { + case 3: + RTL_W8(tp, Config3, RTL_R8(tp, Config3) | LinkUp); + rtl8127_clear_set_mac_ocp_bit(tp, 0xE0C6, (BIT_5 | BIT_3 | BIT_2), (BIT_4 | BIT_1 | BIT_0)); + break; + } +} + +static void +rtl8127_disable_linkchg_wakeup(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + switch (tp->HwSuppLinkChgWakeUpVer) { + case 3: + RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~LinkUp); + if (!(rtl8127_mac_ocp_read(tp, 0xE0C6) & BIT_0)) + rtl8127_clear_set_mac_ocp_bit(tp, 0xE0C6, (BIT_5 | BIT_3 | BIT_2 | BIT_1), BIT_4); + break; + } +} + +#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) + +static u32 +rtl8127_get_hw_wol(struct rtl8127_private *tp) +{ + u8 options; + u32 csi_tmp; + u32 wol_opts = 0; + + if (disable_wol_support) + goto out; + + options = RTL_R8(tp, Config1); + if (!(options & PMEnable)) + goto out; + + options = RTL_R8(tp, Config3); + if (options & LinkUp) + wol_opts |= WAKE_PHY; + + switch (tp->HwSuppMagicPktVer) { + case WAKEUP_MAGIC_PACKET_V3: + csi_tmp = rtl8127_mac_ocp_read(tp, 0xC0B6); + if (csi_tmp & BIT_0) + wol_opts |= WAKE_MAGIC; + break; + } + + options = RTL_R8(tp, Config5); + if (options & UWF) + wol_opts |= WAKE_UCAST; + if (options & BWF) + wol_opts |= WAKE_BCAST; + if (options & MWF) + wol_opts |= WAKE_MCAST; + +out: + return wol_opts; +} + +static void +rtl8127_enable_d0_speedup(struct rtl8127_private *tp) +{ + u16 clearmask; + u16 setmask; + + if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) + return; + + if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_DISABLE) + return; + + if (tp->HwSuppD0SpeedUpVer == 1 || tp->HwSuppD0SpeedUpVer == 2) { + //speed up speed + clearmask = (BIT_10 | BIT_9 | BIT_8 | BIT_7); + if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_2500) + setmask = BIT_7; + else if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_5000) + setmask = BIT_8; + else if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_10000) + setmask = BIT_7 | BIT_8; + else + setmask = 0; + rtl8127_clear_set_mac_ocp_bit(tp, 0xE10A, clearmask, setmask); + + //speed up flowcontrol + clearmask = (BIT_15 | BIT_14); + if (tp->HwSuppD0SpeedUpVer == 2) + clearmask |= BIT_13; + + if (tp->fcpause == rtl8127_fc_full) { + setmask = (BIT_15 | BIT_14); + if (tp->HwSuppD0SpeedUpVer == 2) + setmask |= BIT_13; + } else + setmask = 0; + rtl8127_clear_set_mac_ocp_bit(tp, 0xE860, clearmask, setmask); + } + + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_3); +} + +static void +rtl8127_disable_d0_speedup(struct rtl8127_private *tp) +{ + if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) + return; + + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~BIT_3); +} + +static void +rtl8127_set_hw_wol(struct net_device *dev, u32 wolopts) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i,tmp = 0; + static struct { + u32 opt; + u16 reg; + u8 mask; + } cfg[] = { + { WAKE_PHY, Config3, LinkUp }, + { WAKE_UCAST, Config5, UWF }, + { WAKE_BCAST, Config5, BWF }, + { WAKE_MCAST, Config5, MWF }, + { WAKE_ANY, Config5, LanWake }, + { WAKE_MAGIC, Config3, MagicPacket }, + }; + + switch (tp->HwSuppMagicPktVer) { + case WAKEUP_MAGIC_PACKET_V3: + tmp = ARRAY_SIZE(cfg) - 1; + + if (wolopts & WAKE_MAGIC) + rtl8127_enable_magic_packet(dev); + else + rtl8127_disable_magic_packet(dev); + break; + default: + break; + } + + rtl8127_enable_cfg9346_write(tp); + + for (i = 0; i < tmp; i++) { + u8 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; + if (wolopts & cfg[i].opt) + options |= cfg[i].mask; + RTL_W8(tp, cfg[i].reg, options); + } + + switch (tp->HwSuppLinkChgWakeUpVer) { + case 3: + if (wolopts & WAKE_PHY) + rtl8127_enable_linkchg_wakeup(dev); + else + rtl8127_disable_linkchg_wakeup(dev); + break; + } + + rtl8127_disable_cfg9346_write(tp); +} + +static void +rtl8127_phy_restart_nway(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (rtl8127_is_in_phy_disable_mode(dev)) + return; + + rtl8127_mdio_write(tp, 0x1F, 0x0000); + rtl8127_mdio_write(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); +} + +static void +rtl8127_phy_setup_force_mode(struct net_device *dev, u32 speed, u8 duplex) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u16 bmcr_true_force = 0; + + if (rtl8127_is_in_phy_disable_mode(dev)) + return; + + if ((speed == SPEED_10) && (duplex == DUPLEX_HALF)) { + bmcr_true_force = BMCR_SPEED10; + } else if ((speed == SPEED_10) && (duplex == DUPLEX_FULL)) { + bmcr_true_force = BMCR_SPEED10 | BMCR_FULLDPLX; + } else if ((speed == SPEED_100) && (duplex == DUPLEX_HALF)) { + bmcr_true_force = BMCR_SPEED100; + } else if ((speed == SPEED_100) && (duplex == DUPLEX_FULL)) { + bmcr_true_force = BMCR_SPEED100 | BMCR_FULLDPLX; + } else { + netif_err(tp, drv, dev, "Failed to set phy force mode!\n"); + return; + } + + rtl8127_mdio_write(tp, 0x1F, 0x0000); + rtl8127_mdio_write(tp, MII_BMCR, bmcr_true_force); +} + +static void +rtl8127_set_pci_pme(struct rtl8127_private *tp, int set) +{ + struct pci_dev *pdev = tp->pci_dev; + u16 pmc; + + if (!pdev->pm_cap) + return; + + pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); + pmc |= PCI_PM_CTRL_PME_STATUS; + if (set) + pmc |= PCI_PM_CTRL_PME_ENABLE; + else + pmc &= ~PCI_PM_CTRL_PME_ENABLE; + pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); +} + +static void +rtl8127_enable_giga_lite(struct rtl8127_private *tp, u64 adv) +{ + if (adv & ADVERTISED_1000baseT_Full) + rtl8127_set_eth_phy_ocp_bit(tp, 0xA428, BIT_9); + else + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_9); + + if (adv & ADVERTISED_2500baseX_Full) + rtl8127_set_eth_phy_ocp_bit(tp, 0xA5EA, BIT_0); + else + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA5EA, BIT_0); + + if (adv & RTK_ADVERTISED_5000baseX_Full) + rtl8127_set_eth_phy_ocp_bit(tp, 0xA5EA, BIT_1); + else + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA5EA, BIT_1); + + if (adv & ADVERTISED_10000baseT_Full) + rtl8127_set_eth_phy_ocp_bit(tp, 0xA5EA, BIT_2); + else + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA5EA, BIT_2); +} + +static void +rtl8127_disable_giga_lite(struct rtl8127_private *tp) +{ + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_9); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA5EA, BIT_0 | BIT_1 | BIT_2); +} + +static void +rtl8127_set_wol_link_speed(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long flags; + int auto_nego; + int giga_ctrl; + int ctrl_2500; + u64 adv; + u16 anlpar; + u16 gbsr; + u16 status_2500; + u16 aner; + + spin_lock_irqsave(&tp->phy_lock, flags); + + if (tp->autoneg != AUTONEG_ENABLE) + goto exit; + + rtl8127_mdio_write(tp, 0x1F, 0x0000); + + auto_nego = rtl8127_mdio_read(tp, MII_ADVERTISE); + auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL + | ADVERTISE_100HALF | ADVERTISE_100FULL); + + giga_ctrl = rtl8127_mdio_read(tp, MII_CTRL1000); + giga_ctrl &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); + + ctrl_2500 = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5D4); + ctrl_2500 &= ~(RTK_ADVERTISE_2500FULL | RTK_ADVERTISE_5000FULL | + RTK_ADVERTISE_10000FULL); + + aner = tp->phy_reg_aner; + anlpar = tp->phy_reg_anlpar; + gbsr = tp->phy_reg_gbsr; + status_2500 = tp->phy_reg_status_2500; + if (tp->link_ok(dev)) { + aner = rtl8127_mdio_read(tp, MII_EXPANSION); + anlpar = rtl8127_mdio_read(tp, MII_LPA); + gbsr = rtl8127_mdio_read(tp, MII_STAT1000); + status_2500 = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5D6); + } + + adv = tp->advertising; + if ((aner | anlpar | gbsr | status_2500) == 0) { + int auto_nego_tmp = 0; + if (adv & ADVERTISED_10baseT_Half) + auto_nego_tmp |= ADVERTISE_10HALF; + if (adv & ADVERTISED_10baseT_Full) + auto_nego_tmp |= ADVERTISE_10FULL; + if (adv & ADVERTISED_100baseT_Half) + auto_nego_tmp |= ADVERTISE_100HALF; + if (adv & ADVERTISED_100baseT_Full) + auto_nego_tmp |= ADVERTISE_100FULL; + + if (auto_nego_tmp == 0) + goto exit; + + auto_nego |= auto_nego_tmp; + goto skip_check_lpa; + } + if (!(aner & EXPANSION_NWAY)) + goto exit; + + if ((adv & ADVERTISED_10baseT_Half) && (anlpar & LPA_10HALF)) + auto_nego |= ADVERTISE_10HALF; + else if ((adv & ADVERTISED_10baseT_Full) && (anlpar & LPA_10FULL)) + auto_nego |= ADVERTISE_10FULL; + else if ((adv & ADVERTISED_100baseT_Half) && (anlpar & LPA_100HALF)) + auto_nego |= ADVERTISE_100HALF; + else if ((adv & ADVERTISED_100baseT_Full) && (anlpar & LPA_100FULL)) + auto_nego |= ADVERTISE_100FULL; + else if (adv & ADVERTISED_1000baseT_Half && (gbsr & LPA_1000HALF)) + giga_ctrl |= ADVERTISE_1000HALF; + else if (adv & ADVERTISED_1000baseT_Full && (gbsr & LPA_1000FULL)) + giga_ctrl |= ADVERTISE_1000FULL; + else if (adv & ADVERTISED_2500baseX_Full && (status_2500 & RTK_LPA_ADVERTISE_2500FULL)) + ctrl_2500 |= RTK_ADVERTISE_2500FULL; + else if (adv & RTK_ADVERTISED_5000baseX_Full && (status_2500 & RTK_LPA_ADVERTISE_5000FULL)) + ctrl_2500 |= RTK_ADVERTISE_5000FULL; + else if (adv & ADVERTISED_10000baseT_Full && (status_2500 & RTK_LPA_ADVERTISE_10000FULL)) + ctrl_2500 |= RTK_ADVERTISE_10000FULL; + else + goto exit; + +skip_check_lpa: + if (tp->DASH) + auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL); + +#ifdef CONFIG_DOWN_SPEED_100 + auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL); +#endif + + rtl8127_mdio_write(tp, MII_ADVERTISE, auto_nego); + rtl8127_mdio_write(tp, MII_CTRL1000, giga_ctrl); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA5D4, ctrl_2500); + + rtl8127_disable_giga_lite(tp); + + rtl8127_phy_restart_nway(dev); + +exit: + spin_unlock_irqrestore(&tp->phy_lock, flags); + + return; +} + +static bool +rtl8127_keep_wol_link_speed(struct net_device *dev, u8 from_suspend) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (from_suspend && tp->link_ok(dev) && (tp->wol_opts & WAKE_PHY)) + return 1; + + if (!from_suspend && tp->resume_not_chg_speed) + return 1; + + return 0; +} +static void +rtl8127_powerdown_pll(struct net_device *dev, u8 from_suspend) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + /* Reboot not set wol link speed */ + if (system_state == SYSTEM_RESTART) + return; + + tp->check_keep_link_speed = 0; + if (tp->wol_enabled == WOL_ENABLED || tp->DASH || tp->EnableKCPOffload) { + rtl8127_set_hw_wol(dev, tp->wol_opts); + + rtl8127_enable_cfg9346_write(tp); + RTL_W8(tp, Config2, RTL_R8(tp, Config2) | PMSTS_En); + rtl8127_disable_cfg9346_write(tp); + + /* Enable the PME and clear the status */ + rtl8127_set_pci_pme(tp, 1); + + if (rtl8127_keep_wol_link_speed(dev, from_suspend)) { + tp->check_keep_link_speed = 1; + } else { + if (tp->D0SpeedUpSpeed != D0_SPEED_UP_SPEED_DISABLE) { + rtl8127_enable_d0_speedup(tp); + tp->check_keep_link_speed = 1; + } + + rtl8127_set_wol_link_speed(dev); + } + + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); + + return; + } + + if (tp->DASH) + return; + + rtl8127_phy_power_down(dev); + + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_6); +} + +static void rtl8127_powerup_pll(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | BIT_7 | BIT_6); + + if (tp->resume_not_chg_speed) + return; + + rtl8127_phy_power_up(dev); +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +static void +rtl8127_get_wol(struct net_device *dev, + struct ethtool_wolinfo *wol) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u8 options; + + wol->wolopts = 0; + + if (tp->mcfg == CFG_METHOD_DEFAULT || disable_wol_support) { + wol->supported = 0; + return; + } else { + wol->supported = WAKE_ANY; + } + + options = RTL_R8(tp, Config1); + if (!(options & PMEnable)) + return; + + wol->wolopts = tp->wol_opts; +} + +static int +rtl8127_set_wol(struct net_device *dev, + struct ethtool_wolinfo *wol) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->mcfg == CFG_METHOD_DEFAULT || disable_wol_support) + return -EOPNOTSUPP; + + tp->wol_opts = wol->wolopts; + + tp->wol_enabled = (tp->wol_opts) ? WOL_ENABLED : WOL_DISABLED; + + device_set_wakeup_enable(tp_to_dev(tp), wol->wolopts); + + return 0; +} + +static void +rtl8127_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct rtl8127_fw *rtl_fw = tp->rtl_fw; + + strscpy(info->driver, MODULENAME, sizeof(info->driver)); + strscpy(info->version, RTL8127_VERSION, sizeof(info->version)); + strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); + info->regdump_len = R8127_REGS_DUMP_SIZE; + info->eedump_len = tp->eeprom_len; + BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); + if (rtl_fw) + strscpy(info->fw_version, rtl_fw->version, + sizeof(info->fw_version)); +} + +static int +rtl8127_get_regs_len(struct net_device *dev) +{ + return R8127_REGS_DUMP_SIZE; +} +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) + +static void +rtl8127_set_d0_speedup_speed(struct rtl8127_private *tp) +{ + if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) + return; + + tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_DISABLE; + if (tp->autoneg == AUTONEG_ENABLE) { + if (tp->speed == SPEED_10000) + tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_10000; + else if (tp->speed == SPEED_5000) + tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_5000; + else if (tp->speed == SPEED_2500) + tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_2500; + else if (tp->speed == SPEED_1000) + tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_1000; + } +} + +static int +rtl8127_set_speed_xmii(struct net_device *dev, + u8 autoneg, + u32 speed, + u8 duplex, + u64 adv) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long flags; + int auto_nego = 0; + int giga_ctrl = 0; + int ctrl_2500 = 0; + int rc = -EINVAL; + + spin_lock_irqsave(&tp->phy_lock, flags); + + if (!rtl8127_is_speed_mode_valid(speed)) { + speed = SPEED_10000; + duplex = DUPLEX_FULL; + adv |= tp->advertising; + } + + if (eee_giga_lite && (autoneg == AUTONEG_ENABLE)) + rtl8127_enable_giga_lite(tp, adv); + else + rtl8127_disable_giga_lite(tp); + + giga_ctrl = rtl8127_mdio_read(tp, MII_CTRL1000); + giga_ctrl &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); + ctrl_2500 = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5D4); + ctrl_2500 &= ~(RTK_ADVERTISE_2500FULL | RTK_ADVERTISE_5000FULL | + RTK_ADVERTISE_10000FULL); + + if (autoneg == AUTONEG_ENABLE) { + /*n-way force*/ + auto_nego = rtl8127_mdio_read(tp, MII_ADVERTISE); + auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL | + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); + + if (adv & ADVERTISED_10baseT_Half) + auto_nego |= ADVERTISE_10HALF; + if (adv & ADVERTISED_10baseT_Full) + auto_nego |= ADVERTISE_10FULL; + if (adv & ADVERTISED_100baseT_Half) + auto_nego |= ADVERTISE_100HALF; + if (adv & ADVERTISED_100baseT_Full) + auto_nego |= ADVERTISE_100FULL; + if (adv & ADVERTISED_1000baseT_Half) + giga_ctrl |= ADVERTISE_1000HALF; + if (adv & ADVERTISED_1000baseT_Full) + giga_ctrl |= ADVERTISE_1000FULL; + if (adv & ADVERTISED_2500baseX_Full) + ctrl_2500 |= RTK_ADVERTISE_2500FULL; + if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) { + if (adv & RTK_ADVERTISED_5000baseX_Full) + ctrl_2500 |= RTK_ADVERTISE_5000FULL; + } + if (HW_SUPP_PHY_LINK_SPEED_10000M(tp)) { + if (adv & ADVERTISED_10000baseT_Full) + ctrl_2500 |= RTK_ADVERTISE_10000FULL; + } + + //flow control + if (tp->fcpause == rtl8127_fc_full) + auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + + tp->phy_auto_nego_reg = auto_nego; + tp->phy_1000_ctrl_reg = giga_ctrl; + + tp->phy_2500_ctrl_reg = ctrl_2500; + + rtl8127_mdio_write(tp, 0x1f, 0x0000); + rtl8127_mdio_write(tp, MII_ADVERTISE, auto_nego); + rtl8127_mdio_write(tp, MII_CTRL1000, giga_ctrl); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA5D4, ctrl_2500); + rtl8127_phy_restart_nway(dev); + } else { + /*true force*/ + if (speed == SPEED_10 || speed == SPEED_100) + rtl8127_phy_setup_force_mode(dev, speed, duplex); + else + goto out; + } + + tp->autoneg = autoneg; + tp->speed = speed; + tp->duplex = duplex; + tp->advertising = adv; + + rtl8127_set_d0_speedup_speed(tp); + + rc = 0; +out: + spin_unlock_irqrestore(&tp->phy_lock, flags); + + return rc; +} + +static int +rtl8127_set_speed(struct net_device *dev, + u8 autoneg, + u32 speed, + u8 duplex, + u64 adv) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int ret; + + if (tp->resume_not_chg_speed) + return 0; + + ret = tp->set_speed(dev, autoneg, speed, duplex, adv); + + return ret; +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +static int +rtl8127_set_settings(struct net_device *dev, +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + struct ethtool_cmd *cmd +#else + const struct ethtool_link_ksettings *cmd +#endif + ) +{ + int ret; + u8 autoneg; + u32 speed; + u8 duplex; + u64 supported = 0, advertising = 0; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + autoneg = cmd->autoneg; + speed = cmd->speed; + duplex = cmd->duplex; + supported = cmd->supported; + advertising = cmd->advertising; +#else + struct rtl8127_private *tp = netdev_priv(dev); + const struct ethtool_link_settings *base = &cmd->base; + autoneg = base->autoneg; + speed = base->speed; + duplex = base->duplex; + ethtool_convert_link_mode_to_legacy_u32((u32*)&supported, + cmd->link_modes.supported); + ethtool_convert_link_mode_to_legacy_u32((u32*)&advertising, + cmd->link_modes.advertising); + if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + cmd->link_modes.supported)) + supported |= ADVERTISED_2500baseX_Full; + if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + cmd->link_modes.advertising)) + advertising |= ADVERTISED_2500baseX_Full; + if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) { + if (test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + cmd->link_modes.supported)) + supported |= RTK_ADVERTISED_5000baseX_Full; + if (test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + cmd->link_modes.advertising)) + advertising |= RTK_ADVERTISED_5000baseX_Full; + } + if (HW_SUPP_PHY_LINK_SPEED_10000M(tp)) { + if (test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + cmd->link_modes.supported)) + supported |= ADVERTISED_10000baseT_Full; + if (test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + cmd->link_modes.advertising)) + advertising |= ADVERTISED_10000baseT_Full; + } +#endif + if (advertising & ~supported) + return -EINVAL; + + ret = rtl8127_set_speed(dev, autoneg, speed, duplex, advertising); + + return ret; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) +static u32 +rtl8127_get_tx_csum(struct net_device *dev) +{ + u32 ret; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + ret = ((dev->features & NETIF_F_IP_CSUM) != 0); +#else + ret = ((dev->features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) != 0); +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + + return ret; +} + +static u32 +rtl8127_get_rx_csum(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u32 ret; + + ret = tp->cp_cmd & RxChkSum; + + return ret; +} + +static int +rtl8127_set_tx_csum(struct net_device *dev, + u32 data) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->mcfg == CFG_METHOD_DEFAULT) + return -EOPNOTSUPP; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + if (data) + dev->features |= NETIF_F_IP_CSUM; + else + dev->features &= ~NETIF_F_IP_CSUM; +#else + if (data) + dev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); + else + dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + + return 0; +} + +static int +rtl8127_set_rx_csum(struct net_device *dev, + u32 data) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->mcfg == CFG_METHOD_DEFAULT) + return -EOPNOTSUPP; + + if (data) + tp->cp_cmd |= RxChkSum; + else + tp->cp_cmd &= ~RxChkSum; + + RTL_W16(tp, CPlusCmd, tp->cp_cmd); + + return 0; +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) + +static u32 +rtl8127_rx_desc_opts1(struct rtl8127_private *tp, + struct RxDesc *desc) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + return READ_ONCE(((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts1); + case RX_DESC_RING_TYPE_4: + return READ_ONCE(((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts1); + default: + return READ_ONCE(desc->opts1); + } +} + +static u32 +rtl8127_rx_desc_opts2(struct rtl8127_private *tp, + struct RxDesc *desc) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + return ((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts2; + case RX_DESC_RING_TYPE_4: + return ((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts2; + default: + return desc->opts2; + } +} + +#ifdef CONFIG_R8127_VLAN + +static void +rtl8127_clear_rx_desc_opts2(struct rtl8127_private *tp, + struct RxDesc *desc) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + ((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts2 = 0; + break; + case RX_DESC_RING_TYPE_4: + ((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts2 = 0; + break; + default: + desc->opts2 = 0; + break; + } +} + + +static inline u32 +rtl8127_tx_vlan_tag(struct rtl8127_private *tp, + struct sk_buff *skb) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + return (tp->vlgrp && vlan_tx_tag_present(skb)) ? + TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; +#elif LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) + return (vlan_tx_tag_present(skb)) ? + TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; +#else + return (skb_vlan_tag_present(skb)) ? + TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; +#endif + + return 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + +static void +rtl8127_vlan_rx_register(struct net_device *dev, + struct vlan_group *grp) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + tp->vlgrp = grp; + + if (tp->vlgrp) { + tp->rtl8127_rx_config |= (EnableInnerVlan | EnableOuterVlan); + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | (EnableInnerVlan | EnableOuterVlan)) + } else { + tp->rtl8127_rx_config &= ~(EnableInnerVlan | EnableOuterVlan); + RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~(EnableInnerVlan | EnableOuterVlan)) + } +} + +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) +static void +rtl8127_vlan_rx_kill_vid(struct net_device *dev, + unsigned short vid) +{ + struct rtl8127_private *tp = netdev_priv(dev); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) + if (tp->vlgrp) + tp->vlgrp->vlan_devices[vid] = NULL; +#else + vlan_group_set_device(tp->vlgrp, vid, NULL); +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) + +static int +rtl8127_rx_vlan_skb(struct rtl8127_private *tp, + struct RxDesc *desc, + struct sk_buff *skb) +{ + u32 opts2 = le32_to_cpu(rtl8127_rx_desc_opts2(tp, desc)); + int ret = -1; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + if (tp->vlgrp && (opts2 & RxVlanTag)) { + rtl8127_rx_hwaccel_skb(skb, tp->vlgrp, + swab16(opts2 & 0xffff)); + ret = 0; + } +#elif LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) + if (opts2 & RxVlanTag) + __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); +#else + if (opts2 & RxVlanTag) + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); +#endif + + rtl8127_clear_rx_desc_opts2(tp, desc); + return ret; +} + +#else /* !CONFIG_R8127_VLAN */ + +static inline u32 +rtl8127_tx_vlan_tag(struct rtl8127_private *tp, + struct sk_buff *skb) +{ + return 0; +} + +static int +rtl8127_rx_vlan_skb(struct rtl8127_private *tp, + struct RxDesc *desc, + struct sk_buff *skb) +{ + return -1; +} + +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) + +static netdev_features_t rtl8127_fix_features(struct net_device *dev, + netdev_features_t features) +{ + if (dev->mtu > MSS_MAX) + features &= ~NETIF_F_ALL_TSO; + if (dev->mtu > ETH_DATA_LEN) { + features &= ~NETIF_F_ALL_TSO; + features &= ~NETIF_F_ALL_CSUM; + } +#ifndef CONFIG_R8127_VLAN + features &= ~NETIF_F_ALL_CSUM; +#endif + + return features; +} + +static int rtl8127_hw_set_features(struct net_device *dev, + netdev_features_t features) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u32 rx_config; + + rx_config = RTL_R32(tp, RxConfig); + if (features & NETIF_F_RXALL) { + tp->rtl8127_rx_config |= (AcceptErr | AcceptRunt); + rx_config |= (AcceptErr | AcceptRunt); + } else { + tp->rtl8127_rx_config &= ~(AcceptErr | AcceptRunt); + rx_config &= ~(AcceptErr | AcceptRunt); + } + + if (features & NETIF_F_HW_VLAN_RX) { + tp->rtl8127_rx_config |= (EnableInnerVlan | EnableOuterVlan); + rx_config |= (EnableInnerVlan | EnableOuterVlan); + } else { + tp->rtl8127_rx_config &= ~(EnableInnerVlan | EnableOuterVlan); + rx_config &= ~(EnableInnerVlan | EnableOuterVlan); + } + + RTL_W32(tp, RxConfig, rx_config); + + if (features & NETIF_F_RXCSUM) + tp->cp_cmd |= RxChkSum; + else + tp->cp_cmd &= ~RxChkSum; + + RTL_W16(tp, CPlusCmd, tp->cp_cmd); + RTL_R16(tp, CPlusCmd); + + return 0; +} + +static int rtl8127_set_features(struct net_device *dev, + netdev_features_t features) +{ + features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX; + + rtl8127_hw_set_features(dev, features); + + return 0; +} + +#endif + +static u8 rtl8127_get_mdi_status(struct rtl8127_private *tp) +{ + if (!tp->link_ok(tp->dev)) + return ETH_TP_MDI_INVALID; + + if (rtl8127_mdio_direct_read_phy_ocp(tp, 0xA444) & BIT_1) + return ETH_TP_MDI; + else + return ETH_TP_MDI_X; +} + +static void rtl8127_gset_xmii(struct net_device *dev, +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + struct ethtool_cmd *cmd +#else + struct ethtool_link_ksettings *cmd +#endif + ) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u16 aner = tp->phy_reg_aner; + u16 anlpar = tp->phy_reg_anlpar; + u16 gbsr = tp->phy_reg_gbsr; + u16 status_2500 = tp->phy_reg_status_2500; + unsigned long flags; + u64 lpa_adv = 0; + u32 status; + u8 autoneg, duplex; + u32 speed = 0; + u16 bmcr; + u64 supported, advertising; + u8 report_lpa = 0; + + supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full | + SUPPORTED_2500baseX_Full | + RTK_SUPPORTED_5000baseX_Full | + SUPPORTED_10000baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_TP | + SUPPORTED_Pause | + SUPPORTED_Asym_Pause; + + if (!HW_SUPP_PHY_LINK_SPEED_2500M(tp)) + supported &= ~SUPPORTED_2500baseX_Full; + + if (!HW_SUPP_PHY_LINK_SPEED_5000M(tp)) + supported &= ~RTK_SUPPORTED_5000baseX_Full; + + if (!HW_SUPP_PHY_LINK_SPEED_10000M(tp)) + supported &= ~SUPPORTED_10000baseT_Full; + + advertising = tp->advertising; + if (tp->phy_auto_nego_reg || tp->phy_1000_ctrl_reg || + tp->phy_2500_ctrl_reg) { + advertising = 0; + if (tp->phy_auto_nego_reg & ADVERTISE_10HALF) + advertising |= ADVERTISED_10baseT_Half; + if (tp->phy_auto_nego_reg & ADVERTISE_10FULL) + advertising |= ADVERTISED_10baseT_Full; + if (tp->phy_auto_nego_reg & ADVERTISE_100HALF) + advertising |= ADVERTISED_100baseT_Half; + if (tp->phy_auto_nego_reg & ADVERTISE_100FULL) + advertising |= ADVERTISED_100baseT_Full; + if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL) + advertising |= ADVERTISED_1000baseT_Full; + if (tp->phy_2500_ctrl_reg & RTK_ADVERTISE_2500FULL) + advertising |= ADVERTISED_2500baseX_Full; + if (tp->phy_2500_ctrl_reg & RTK_ADVERTISE_5000FULL) + advertising |= RTK_ADVERTISED_5000baseX_Full; + if (tp->phy_2500_ctrl_reg & RTK_ADVERTISE_10000FULL) + advertising |= ADVERTISED_10000baseT_Full; + } + + spin_lock_irqsave(&tp->phy_lock, flags); + rtl8127_mdio_write(tp, 0x1F, 0x0000); + bmcr = rtl8127_mdio_read(tp, MII_BMCR); + spin_unlock_irqrestore(&tp->phy_lock, flags); + if (bmcr & BMCR_ANENABLE) { + autoneg = AUTONEG_ENABLE; + advertising |= ADVERTISED_Autoneg; + } else { + autoneg = AUTONEG_DISABLE; + } + + advertising |= ADVERTISED_TP; + + status = RTL_R32(tp, PHYstatus); + if (netif_running(dev) && (status & LinkStatus)) + report_lpa = 1; + + if (report_lpa) { + /*link on*/ + speed = rtl8127_convert_link_speed(status); + + if (status & TxFlowCtrl) + advertising |= ADVERTISED_Asym_Pause; + + if (status & RxFlowCtrl) + advertising |= ADVERTISED_Pause; + + duplex = ((status & (_1000bpsF | _2500bpsF | _5000bpsF | _10000bpsF)) || + (status & FullDup)) ? + DUPLEX_FULL : DUPLEX_HALF; + + /*link partner*/ + if (aner & EXPANSION_NWAY) + lpa_adv |= ADVERTISED_Autoneg; + if (anlpar & LPA_10HALF) + lpa_adv |= ADVERTISED_10baseT_Half; + if (anlpar & LPA_10FULL) + lpa_adv |= ADVERTISED_10baseT_Full; + if (anlpar & LPA_100HALF) + lpa_adv |= ADVERTISED_100baseT_Half; + if (anlpar & LPA_100FULL) + lpa_adv |= ADVERTISED_100baseT_Full; + if (anlpar & LPA_PAUSE_CAP) + lpa_adv |= ADVERTISED_Pause; + if (anlpar & LPA_PAUSE_ASYM) + lpa_adv |= ADVERTISED_Asym_Pause; + if (gbsr & LPA_1000HALF) + lpa_adv |= ADVERTISED_1000baseT_Half; + if (gbsr & LPA_1000FULL) + lpa_adv |= ADVERTISED_1000baseT_Full; + if (status_2500 & RTK_LPA_ADVERTISE_2500FULL) + lpa_adv |= ADVERTISED_2500baseX_Full; + if (status_2500 & RTK_LPA_ADVERTISE_5000FULL) + lpa_adv |= RTK_ADVERTISED_5000baseX_Full; + if (status_2500 & RTK_LPA_ADVERTISE_10000FULL) + lpa_adv |= ADVERTISED_10000baseT_Full; + } else { + /*link down*/ + speed = SPEED_UNKNOWN; + duplex = DUPLEX_UNKNOWN; + lpa_adv = 0; + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + cmd->supported = (u32)supported; + cmd->advertising = (u32)advertising; + cmd->autoneg = autoneg; + cmd->speed = speed; + cmd->duplex = duplex; + cmd->port = PORT_TP; + cmd->lp_advertising = (u32)lpa_adv; + cmd->eth_tp_mdix = rtl8127_get_mdi_status(tp); +#else + ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, + supported); + ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, + advertising); + ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, + lpa_adv); + + if (supported & SUPPORTED_2500baseX_Full) { + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + cmd->link_modes.supported, 1); + } + if (advertising & ADVERTISED_2500baseX_Full) { + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + cmd->link_modes.advertising, 1); + } + if (supported & RTK_SUPPORTED_5000baseX_Full) { + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + cmd->link_modes.supported, 1); + } + if (advertising & RTK_ADVERTISED_5000baseX_Full) { + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + cmd->link_modes.advertising, 1); + } + if (supported & SUPPORTED_10000baseT_Full) { + linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + cmd->link_modes.supported, 1); + } + if (advertising & ADVERTISED_10000baseT_Full) { + linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + cmd->link_modes.advertising, 1); + } + if (report_lpa) { + if (lpa_adv & ADVERTISED_2500baseX_Full) { + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + cmd->link_modes.lp_advertising, 1); + } + if (lpa_adv & RTK_ADVERTISED_5000baseX_Full) + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + cmd->link_modes.lp_advertising, 1); + if (lpa_adv & ADVERTISED_10000baseT_Full) + linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + cmd->link_modes.lp_advertising, 1); + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0) + /* Use ETHTOOL_LINK_MODE_2500baseT_Full_BIT instead of + ETHTOOL_LINK_MODE_2500baseX_Full_BIT. */ + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, + cmd->link_modes.supported, 0); + + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, + cmd->link_modes.advertising, 0); + + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, + cmd->link_modes.lp_advertising, 0); +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0) */ + + cmd->base.autoneg = autoneg; + cmd->base.speed = speed; + cmd->base.duplex = duplex; + cmd->base.port = PORT_TP; + cmd->base.eth_tp_mdix = rtl8127_get_mdi_status(tp); +#endif +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +static int +rtl8127_get_settings(struct net_device *dev, +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + struct ethtool_cmd *cmd +#else + struct ethtool_link_ksettings *cmd +#endif + ) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + tp->get_settings(dev, cmd); + + return 0; +} + +static void rtl8127_get_regs(struct net_device *dev, struct ethtool_regs *regs, + void *p) +{ + struct rtl8127_private *tp = netdev_priv(dev); + void __iomem *ioaddr = tp->mmio_addr; + unsigned int i; + u8 *data = p; + + if (regs->len < R8127_REGS_DUMP_SIZE) + return /* -EINVAL */; + + memset(p, 0, regs->len); + + for (i = 0; i < R8127_MAC_REGS_SIZE; i++) + *data++ = readb(ioaddr + i); + data = (u8*)p + 256; + + rtl8127_mdio_write(tp, 0x1F, 0x0000); + for (i = 0; i < R8127_PHY_REGS_SIZE/2; i++) { + *(u16*)data = rtl8127_mdio_read(tp, i); + data += 2; + } + data = (u8*)p + 256 * 2; + + for (i = 0; i < R8127_EPHY_REGS_SIZE/2; i++) { + *(u16*)data = rtl8127_ephy_read(tp, i); + data += 2; + } + data = (u8*)p + 256 * 3; + + for (i = 0; i < R8127_ERI_REGS_SIZE; i+=4) { + *(u32*)data = rtl8127_eri_read(tp, i , 4, ERIAR_ExGMAC); + data += 4; + } +} + +static void rtl8127_get_pauseparam(struct net_device *dev, + struct ethtool_pauseparam *pause) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + pause->autoneg = (tp->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); + if (tp->fcpause == rtl8127_fc_rx_pause) + pause->rx_pause = 1; + else if (tp->fcpause == rtl8127_fc_tx_pause) + pause->tx_pause = 1; + else if (tp->fcpause == rtl8127_fc_full) { + pause->rx_pause = 1; + pause->tx_pause = 1; + } +} + +static int rtl8127_set_pauseparam(struct net_device *dev, + struct ethtool_pauseparam *pause) +{ + struct rtl8127_private *tp = netdev_priv(dev); + enum rtl8127_fc_mode newfc; + + if (pause->tx_pause || pause->rx_pause) + newfc = rtl8127_fc_full; + else + newfc = rtl8127_fc_none; + + if (tp->fcpause != newfc) { + tp->fcpause = newfc; + + rtl8127_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); + } + + return 0; + +} + +static u32 +rtl8127_get_msglevel(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + return tp->msg_enable; +} + +static void +rtl8127_set_msglevel(struct net_device *dev, + u32 value) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + tp->msg_enable = value; +} + +static const char rtl8127_gstrings[][ETH_GSTRING_LEN] = { + /* legacy */ + "tx_packets", + "rx_packets", + "tx_errors", + "rx_errors", + "rx_missed", + "align_errors", + "tx_single_collisions", + "tx_multi_collisions", + "unicast", + "broadcast", + "multicast", + "tx_aborted", + "tx_underrun", + + /* extended */ + "tx_octets", + "rx_octets", + "rx_multicast64", + "tx_unicast64", + "tx_broadcast64", + "tx_multicast64", + "tx_pause_on", + "tx_pause_off", + "tx_pause_all", + "tx_deferred", + "tx_late_collision", + "tx_all_collision", + "tx_aborted32", + "align_errors32", + "rx_frame_too_long", + "rx_runt", + "rx_pause_on", + "rx_pause_off", + "rx_pause_all", + "rx_unknown_opcode", + "rx_mac_error", + "tx_underrun32", + "rx_mac_missed", + "rx_tcam_dropped", + "tdu", + "rdu", +}; +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +static int rtl8127_get_stats_count(struct net_device *dev) +{ + return ARRAY_SIZE(rtl8127_gstrings); +} +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +#else +static int rtl8127_get_sset_count(struct net_device *dev, int sset) +{ + switch (sset) { + case ETH_SS_STATS: + return ARRAY_SIZE(rtl8127_gstrings); + default: + return -EOPNOTSUPP; + } +} +#endif + +static void +rtl8127_set_ring_size(struct rtl8127_private *tp, u32 rx, u32 tx) +{ + int i; + + for (i = 0; i < R8127_MAX_RX_QUEUES; i++) + tp->rx_ring[i].num_rx_desc = rx; + + for (i = 0; i < R8127_MAX_TX_QUEUES; i++) + tp->tx_ring[i].num_tx_desc = tx; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) +static void rtl8127_get_ringparam(struct net_device *dev, + struct ethtool_ringparam *ring, + struct kernel_ethtool_ringparam *kernel_ring, + struct netlink_ext_ack *extack) +#else +static void rtl8127_get_ringparam(struct net_device *dev, + struct ethtool_ringparam *ring) +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + ring->rx_max_pending = MAX_NUM_TX_DESC; + ring->tx_max_pending = MAX_NUM_RX_DESC; + ring->rx_pending = tp->rx_ring[0].num_rx_desc; + ring->tx_pending = tp->tx_ring[0].num_tx_desc; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) +static int rtl8127_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *ring, + struct kernel_ethtool_ringparam *kernel_ring, + struct netlink_ext_ack *extack) +#else +static int rtl8127_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *ring) +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u32 new_rx_count, new_tx_count; + int rc = 0; + + if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) + return -EINVAL; + + new_tx_count = clamp_t(u32, ring->tx_pending, + MIN_NUM_TX_DESC, MAX_NUM_TX_DESC); + + new_rx_count = clamp_t(u32, ring->rx_pending, + MIN_NUM_RX_DESC, MAX_NUM_RX_DESC); + + if ((new_rx_count == tp->rx_ring[0].num_rx_desc) && + (new_tx_count == tp->tx_ring[0].num_tx_desc)) { + /* nothing to do */ + return 0; + } + + if (netif_running(dev)) { + rtl8127_wait_for_quiescence(dev); + rtl8127_close(dev); + } + + rtl8127_set_ring_size(tp, new_rx_count, new_tx_count); + + if (netif_running(dev)) + rc = rtl8127_open(dev); + + return rc; +} +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +static void +rtl8127_get_ethtool_stats(struct net_device *dev, + struct ethtool_stats *stats, + u64 *data) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct rtl8127_counters *counters; + dma_addr_t paddr; + + ASSERT_RTNL(); + + counters = tp->tally_vaddr; + paddr = tp->tally_paddr; + if (!counters) + return; + + rtl8127_dump_tally_counter(tp, paddr); + + data[0] = le64_to_cpu(counters->tx_packets); + data[1] = le64_to_cpu(counters->rx_packets); + data[2] = le64_to_cpu(counters->tx_errors); + data[3] = le32_to_cpu(counters->rx_errors); + data[4] = le16_to_cpu(counters->rx_missed); + data[5] = le16_to_cpu(counters->align_errors); + data[6] = le32_to_cpu(counters->tx_one_collision); + data[7] = le32_to_cpu(counters->tx_multi_collision); + data[8] = le64_to_cpu(counters->rx_unicast); + data[9] = le64_to_cpu(counters->rx_broadcast); + data[10] = le32_to_cpu(counters->rx_multicast); + data[11] = le16_to_cpu(counters->tx_aborted); + data[12] = le16_to_cpu(counters->tx_underrun); + + data[13] = le64_to_cpu(counters->tx_octets); + data[14] = le64_to_cpu(counters->rx_octets); + data[15] = le64_to_cpu(counters->rx_multicast64); + data[16] = le64_to_cpu(counters->tx_unicast64); + data[17] = le64_to_cpu(counters->tx_broadcast64); + data[18] = le64_to_cpu(counters->tx_multicast64); + data[19] = le32_to_cpu(counters->tx_pause_on); + data[20] = le32_to_cpu(counters->tx_pause_off); + data[21] = le32_to_cpu(counters->tx_pause_all); + data[22] = le32_to_cpu(counters->tx_deferred); + data[23] = le32_to_cpu(counters->tx_late_collision); + data[24] = le32_to_cpu(counters->tx_all_collision); + data[25] = le32_to_cpu(counters->tx_aborted32); + data[26] = le32_to_cpu(counters->align_errors32); + data[27] = le32_to_cpu(counters->rx_frame_too_long); + data[28] = le32_to_cpu(counters->rx_runt); + data[29] = le32_to_cpu(counters->rx_pause_on); + data[30] = le32_to_cpu(counters->rx_pause_off); + data[31] = le32_to_cpu(counters->rx_pause_all); + data[32] = le32_to_cpu(counters->rx_unknown_opcode); + data[33] = le32_to_cpu(counters->rx_mac_error); + data[34] = le32_to_cpu(counters->tx_underrun32); + data[35] = le32_to_cpu(counters->rx_mac_missed); + data[36] = le32_to_cpu(counters->rx_tcam_dropped); + data[37] = le32_to_cpu(counters->tdu); + data[38] = le32_to_cpu(counters->rdu); +} + +static void +rtl8127_get_strings(struct net_device *dev, + u32 stringset, + u8 *data) +{ + switch (stringset) { + case ETH_SS_STATS: + memcpy(data, rtl8127_gstrings, sizeof(rtl8127_gstrings)); + break; + } +} +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) + +static int rtl_get_eeprom_len(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + return tp->eeprom_len; +} + +static int rtl_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *buf) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i,j,ret; + int start_w, end_w; + int VPD_addr, VPD_data; + u32 *eeprom_buff; + u16 tmp; + + if (tp->eeprom_type == EEPROM_TYPE_NONE) { + dev_printk(KERN_DEBUG, tp_to_dev(tp), "Detect none EEPROM\n"); + return -EOPNOTSUPP; + } else if (eeprom->len == 0 || (eeprom->offset+eeprom->len) > tp->eeprom_len) { + dev_printk(KERN_DEBUG, tp_to_dev(tp), "Invalid parameter\n"); + return -EINVAL; + } + + VPD_addr = 0xD2; + VPD_data = 0xD4; + + start_w = eeprom->offset >> 2; + end_w = (eeprom->offset + eeprom->len - 1) >> 2; + + eeprom_buff = kmalloc(sizeof(u32)*(end_w - start_w + 1), GFP_KERNEL); + if (!eeprom_buff) + return -ENOMEM; + + rtl8127_enable_cfg9346_write(tp); + ret = -EFAULT; + for (i=start_w; i<=end_w; i++) { + pci_write_config_word(tp->pci_dev, VPD_addr, (u16)i*4); + ret = -EFAULT; + for (j = 0; j < 10; j++) { + fsleep(400); + pci_read_config_word(tp->pci_dev, VPD_addr, &tmp); + if (tmp&0x8000) { + ret = 0; + break; + } + } + + if (ret) + break; + + pci_read_config_dword(tp->pci_dev, VPD_data, &eeprom_buff[i-start_w]); + } + rtl8127_disable_cfg9346_write(tp); + + if (!ret) + memcpy(buf, (u8 *)eeprom_buff + (eeprom->offset & 3), eeprom->len); + + kfree(eeprom_buff); + + return ret; +} + +#undef ethtool_op_get_link +#define ethtool_op_get_link _kc_ethtool_op_get_link +static u32 _kc_ethtool_op_get_link(struct net_device *dev) +{ + return netif_carrier_ok(dev) ? 1 : 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) +#undef ethtool_op_get_sg +#define ethtool_op_get_sg _kc_ethtool_op_get_sg +static u32 _kc_ethtool_op_get_sg(struct net_device *dev) +{ +#ifdef NETIF_F_SG + return (dev->features & NETIF_F_SG) != 0; +#else + return 0; +#endif +} + +#undef ethtool_op_set_sg +#define ethtool_op_set_sg _kc_ethtool_op_set_sg +static int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->mcfg == CFG_METHOD_DEFAULT) + return -EOPNOTSUPP; + +#ifdef NETIF_F_SG + if (data) + dev->features |= NETIF_F_SG; + else + dev->features &= ~NETIF_F_SG; +#endif + + return 0; +} +#endif + +static void +rtl8127_set_eee_lpi_timer(struct rtl8127_private *tp) +{ + u16 dev_lpi_timer; + + dev_lpi_timer = tp->eee.tx_lpi_timer; + + RTL_W16(tp, EEE_TXIDLE_TIMER_8125, dev_lpi_timer); +} + +static bool rtl8127_is_adv_eee_enabled(struct rtl8127_private *tp) +{ + if (rtl8127_mdio_direct_read_phy_ocp(tp, 0xA430) & BIT_15) + return true; + else + return false; +} + +static void rtl8127_disable_adv_eee(struct rtl8127_private *tp) +{ + bool lock; + + if (rtl8127_is_adv_eee_enabled(tp)) + lock = true; + else + lock = false; + + if (lock) + rtl8127_set_phy_mcu_patch_request(tp); + + rtl8127_clear_mac_ocp_bit(tp, 0xE052, BIT_0); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA442, BIT_12 | BIT_13); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA430, BIT_15); + + if (lock) + rtl8127_clear_phy_mcu_patch_request(tp); +} + +static int rtl8127_enable_eee(struct rtl8127_private *tp) +{ + struct ethtool_keee *eee = &tp->eee; + u16 eee_adv_cap1_t = rtl8127_ethtool_adv_to_mmd_eee_adv_cap1_t(eee->advertised); + u16 eee_adv_cap2_t = rtl8127_ethtool_adv_to_mmd_eee_adv_cap2_t(eee->advertised); + + rtl8127_set_mac_ocp_bit(tp, 0xE040, (BIT_1|BIT_0)); + + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA5D0, + MDIO_EEE_100TX | MDIO_EEE_1000T | MDIO_EEE_10GT, + eee_adv_cap1_t); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA6D4, + MDIO_EEE_2_5GT | MDIO_EEE_5GT, + eee_adv_cap2_t); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA6D8, BIT_4); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_7); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA4A2, BIT_9); + + /*Advanced EEE*/ + rtl8127_disable_adv_eee(tp); + + return 0; +} + +static int rtl8127_disable_eee(struct rtl8127_private *tp) +{ + rtl8127_clear_mac_ocp_bit(tp, 0xE040, (BIT_1|BIT_0)); + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA5D0, + (MDIO_EEE_100TX | MDIO_EEE_1000T | MDIO_EEE_10GT)); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA6D4, + (MDIO_EEE_2_5GT | MDIO_EEE_5GT)); + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA6D8, BIT_4); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_7); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA4A2, BIT_9); + + /*Advanced EEE*/ + rtl8127_disable_adv_eee(tp); + + return 0; +} + +static int rtl_nway_reset(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int ret, bmcr; + + if (unlikely(tp->rtk_enable_diag)) + return -EBUSY; + + /* if autoneg is off, it's an error */ + rtl8127_mdio_write(tp, 0x1F, 0x0000); + bmcr = rtl8127_mdio_read(tp, MII_BMCR); + + if (bmcr & BMCR_ANENABLE) { + bmcr |= BMCR_ANRESTART; + rtl8127_mdio_write(tp, MII_BMCR, bmcr); + ret = 0; + } else { + ret = -EINVAL; + } + + return ret; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) +static u32 +rtl8127_device_lpi_t_to_ethtool_lpi_t(struct rtl8127_private *tp , u32 lpi_timer) +{ + u32 to_us; + u16 status; + + to_us = lpi_timer * 80; + status = RTL_R16(tp, PHYstatus); + if (status & LinkStatus) { + /*link on*/ + if (HW_SUPP_PHY_LINK_SPEED_10000M(tp)) { + //5G : lpi_timer * 12.8ns + //2.5G : lpi_timer * 25.6ns + //Giga: lpi_timer * 8ns + //100M : lpi_timer * 80ns + if (status & (_10000bpsF)) + to_us = (lpi_timer * 128) / 10; + else if (status & (_5000bpsF)) + to_us = (lpi_timer * 128) / 10; + else if (status & _2500bpsF) + to_us = (lpi_timer * 256) / 10; + else if (status & _1000bpsF) + to_us = lpi_timer * 8; + } else if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) { + //5G : lpi_timer * 12.8ns + //2.5G : lpi_timer * 25.6ns + //Giga: lpi_timer * 8ns + //100M : lpi_timer * 80ns + if (status & (_5000bpsF)) + to_us = (lpi_timer * 128) / 10; + else if (status & _2500bpsF) + to_us = (lpi_timer * 256) / 10; + else if (status & _1000bpsF) + to_us = lpi_timer * 8; + } else { + //2.5G : lpi_timer * 3.2ns + //Giga: lpi_timer * 8ns + //100M : lpi_timer * 80ns + if (status & _2500bpsF) + to_us = (lpi_timer * 32) / 10; + else if (status & _1000bpsF) + to_us = lpi_timer * 8; + } + } + + //ns to us + to_us /= 1000; + + return to_us; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,9,0) +static void +rtl8127_adv_to_linkmode(unsigned long *mode, u64 adv) +{ + linkmode_zero(mode); + + if (adv & ADVERTISED_10baseT_Half) + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mode); + if (adv & ADVERTISED_10baseT_Full) + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mode); + if (adv & ADVERTISED_100baseT_Half) + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode); + if (adv & ADVERTISED_100baseT_Full) + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode); + if (adv & ADVERTISED_1000baseT_Half) + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode); + if (adv & ADVERTISED_1000baseT_Full) + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode); + if (adv & ADVERTISED_2500baseX_Full) + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, mode); + if (adv & RTK_ADVERTISED_5000baseX_Full) + linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, mode); + if (adv & ADVERTISED_10000baseT_Full) + linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode); +} + +static int +rtl_ethtool_get_eee(struct net_device *net, struct ethtool_keee *edata) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(common); + struct rtl8127_private *tp = netdev_priv(net); + struct ethtool_keee *eee = &tp->eee; + u32 tx_lpi_timer; + u16 val; + + if (unlikely(tp->rtk_enable_diag)) + return -EBUSY; + + /* Get LP advertisement EEE */ + val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5D2); + mii_eee_cap1_mod_linkmode_t(edata->lp_advertised, val); + val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA6D0); + mii_eee_cap2_mod_linkmode_sup_t(edata->lp_advertised, val); + + /* Get EEE Tx LPI timer*/ + tx_lpi_timer = rtl8127_device_lpi_t_to_ethtool_lpi_t(tp, eee->tx_lpi_timer); + + val = rtl8127_mac_ocp_read(tp, 0xE040); + val &= BIT_1 | BIT_0; + + edata->eee_enabled = !!val; + linkmode_copy(edata->supported, eee->supported); + linkmode_copy(edata->advertised, eee->advertised); + edata->tx_lpi_enabled = edata->eee_enabled; + edata->tx_lpi_timer = tx_lpi_timer; + linkmode_and(common, edata->advertised, edata->lp_advertised); + edata->eee_active = !linkmode_empty(common); + + return 0; +} + +static int +rtl_ethtool_set_eee(struct net_device *net, struct ethtool_keee *edata) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); + __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp); + struct rtl8127_private *tp = netdev_priv(net); + struct ethtool_keee *eee = &tp->eee; + int rc = 0; + + if (!HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp) || + tp->DASH) + return -EOPNOTSUPP; + + if (unlikely(tp->rtk_enable_diag)) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "Diag Enabled\n"); + rc = -EBUSY; + goto out; + } + + if (tp->autoneg != AUTONEG_ENABLE) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE requires autoneg\n"); + rc = -EINVAL; + goto out; + } + + /* + if (edata->tx_lpi_enabled) { + if (edata->tx_lpi_timer > tp->max_jumbo_frame_size || + edata->tx_lpi_timer < ETH_MIN_MTU) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "Valid LPI timer range is %d to %d. \n", + ETH_MIN_MTU, tp->max_jumbo_frame_size); + rc = -EINVAL; + goto out; + } + } + */ + + rtl8127_adv_to_linkmode(advertising, tp->advertising); + if (linkmode_empty(edata->advertised)) { + linkmode_and(edata->advertised, advertising, eee->supported); + } else if (linkmode_andnot(tmp, edata->advertised, advertising)) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE advertised must be a subset of autoneg advertised speeds\n"); + rc = -EINVAL; + goto out; + } + + if (linkmode_andnot(tmp, edata->advertised, eee->supported)) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE advertised must be a subset of support \n"); + rc = -EINVAL; + goto out; + } + + //tp->eee.eee_enabled = edata->eee_enabled; + //tp->eee_adv_t = rtl8127_ethtool_adv_to_mmd_eee_adv_cap1_t(edata->advertised); + + linkmode_copy(eee->advertised, edata->advertised); + //eee->tx_lpi_enabled = edata->tx_lpi_enabled; + //eee->tx_lpi_timer = edata->tx_lpi_timer; + eee->eee_enabled = edata->eee_enabled; + + if (eee->eee_enabled) + rtl8127_enable_eee(tp); + else + rtl8127_disable_eee(tp); + + rtl_nway_reset(net); + +out: + return rc; +} +#else +static int +rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) +{ + struct rtl8127_private *tp = netdev_priv(net); + struct ethtool_eee *eee = &tp->eee; + u32 lp, adv, tx_lpi_timer, supported = 0; + u16 val; + + if (unlikely(tp->rtk_enable_diag)) + return -EBUSY; + + /* Get Supported EEE */ + //val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5C4); + //supported = mmd_eee_cap_to_ethtool_sup_t(val); + supported = eee->supported; + + /* Get advertisement EEE */ + adv = eee->advertised; + + /* Get LP advertisement EEE */ + val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA5D2); + lp = mmd_eee_adv_to_ethtool_adv_t(val); + val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA6D0); + if (val & RTK_LPA_EEE_ADVERTISE_2500FULL) + lp |= ADVERTISED_2500baseX_Full; + + /* Get EEE Tx LPI timer*/ + tx_lpi_timer = rtl8127_device_lpi_t_to_ethtool_lpi_t(tp, eee->tx_lpi_timer); + + val = rtl8127_mac_ocp_read(tp, 0xE040); + val &= BIT_1 | BIT_0; + + edata->eee_enabled = !!val; + edata->eee_active = !!(supported & adv & lp); + edata->supported = supported; + edata->advertised = adv; + edata->lp_advertised = lp; + edata->tx_lpi_enabled = edata->eee_enabled; + edata->tx_lpi_timer = tx_lpi_timer; + + return 0; +} + +static int +rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) +{ + struct rtl8127_private *tp = netdev_priv(net); + struct ethtool_eee *eee = &tp->eee; + u32 advertising; + int rc = 0; + + if (!HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp) || + tp->DASH) + return -EOPNOTSUPP; + + if (unlikely(tp->rtk_enable_diag)) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "Diag Enabled\n"); + rc = -EBUSY; + goto out; + } + + if (tp->autoneg != AUTONEG_ENABLE) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE requires autoneg\n"); + rc = -EINVAL; + goto out; + } + + /* + if (edata->tx_lpi_enabled) { + if (edata->tx_lpi_timer > tp->max_jumbo_frame_size || + edata->tx_lpi_timer < ETH_MIN_MTU) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "Valid LPI timer range is %d to %d. \n", + ETH_MIN_MTU, tp->max_jumbo_frame_size); + rc = -EINVAL; + goto out; + } + } + */ + + advertising = tp->advertising; + if (!edata->advertised) { + edata->advertised = advertising & eee->supported; + } else if (edata->advertised & ~advertising) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", + edata->advertised, advertising); + rc = -EINVAL; + goto out; + } + + if (edata->advertised & ~eee->supported) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE advertised %x must be a subset of support %x\n", + edata->advertised, eee->supported); + rc = -EINVAL; + goto out; + } + + //tp->eee.eee_enabled = edata->eee_enabled; + //tp->eee_adv_t = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); + + eee->advertised = edata->advertised; + //eee->tx_lpi_enabled = edata->tx_lpi_enabled; + //eee->tx_lpi_timer = edata->tx_lpi_timer; + eee->eee_enabled = edata->eee_enabled; + + if (eee->eee_enabled) + rtl8127_enable_eee(tp); + else + rtl8127_disable_eee(tp); + + rtl_nway_reset(net); + +out: + return rc; +} +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(6,9,0) */ +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) +static void rtl8127_get_channels(struct net_device *dev, + struct ethtool_channels *channel) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + channel->max_rx = tp->HwSuppNumRxQueues; + channel->max_tx = tp->HwSuppNumTxQueues; + channel->rx_count = tp->num_rx_rings; + channel->tx_count = tp->num_tx_rings; +} +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) */ + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) +static const struct ethtool_ops rtl8127_ethtool_ops = { + .get_drvinfo = rtl8127_get_drvinfo, + .get_regs_len = rtl8127_get_regs_len, + .get_link = ethtool_op_get_link, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + .get_ringparam = rtl8127_get_ringparam, + .set_ringparam = rtl8127_set_ringparam, +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) + .get_settings = rtl8127_get_settings, + .set_settings = rtl8127_set_settings, +#else + .get_link_ksettings = rtl8127_get_settings, + .set_link_ksettings = rtl8127_set_settings, +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + .get_pauseparam = rtl8127_get_pauseparam, + .set_pauseparam = rtl8127_set_pauseparam, +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + .get_msglevel = rtl8127_get_msglevel, + .set_msglevel = rtl8127_set_msglevel, +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) + .get_rx_csum = rtl8127_get_rx_csum, + .set_rx_csum = rtl8127_set_rx_csum, + .get_tx_csum = rtl8127_get_tx_csum, + .set_tx_csum = rtl8127_set_tx_csum, + .get_sg = ethtool_op_get_sg, + .set_sg = ethtool_op_set_sg, +#ifdef NETIF_F_TSO + .get_tso = ethtool_op_get_tso, + .set_tso = ethtool_op_set_tso, +#endif //NETIF_F_TSO +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) + .get_regs = rtl8127_get_regs, + .get_wol = rtl8127_get_wol, + .set_wol = rtl8127_set_wol, + .get_strings = rtl8127_get_strings, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) + .get_stats_count = rtl8127_get_stats_count, +#else + .get_sset_count = rtl8127_get_sset_count, +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) + .get_ethtool_stats = rtl8127_get_ethtool_stats, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) +#ifdef ETHTOOL_GPERMADDR + .get_perm_addr = ethtool_op_get_perm_addr, +#endif //ETHTOOL_GPERMADDR +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) + .get_eeprom = rtl_get_eeprom, + .get_eeprom_len = rtl_get_eeprom_len, +#ifdef ENABLE_RSS_SUPPORT + .get_rxnfc = rtl8127_get_rxnfc, + .set_rxnfc = rtl8127_set_rxnfc, + .get_rxfh_indir_size = rtl8127_rss_indir_size, + .get_rxfh_key_size = rtl8127_get_rxfh_key_size, + .get_rxfh = rtl8127_get_rxfh, + .set_rxfh = rtl8127_set_rxfh, +#endif //ENABLE_RSS_SUPPORT +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0) +#ifdef ENABLE_PTP_SUPPORT + .get_ts_info = rtl8127_get_ts_info, +#else + .get_ts_info = ethtool_op_get_ts_info, +#endif //ENABLE_PTP_SUPPORT +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) + .get_eee = rtl_ethtool_get_eee, + .set_eee = rtl_ethtool_set_eee, +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) + .get_channels = rtl8127_get_channels, +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) */ + .nway_reset = rtl_nway_reset, + +}; +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) + +static void rtl8127_get_mac_version(struct rtl8127_private *tp) +{ + u32 reg,val32; + u32 ICVerID; + + val32 = RTL_R32(tp, TxConfig); + reg = val32 & 0x7c800000; + ICVerID = val32 & 0x00700000; + + switch (reg) { + case 0x6C800000: + if (ICVerID == 0x00000000) { + tp->mcfg = CFG_METHOD_1; + } else if (ICVerID == 0x100000) { + tp->mcfg = CFG_METHOD_2; + } else { + tp->mcfg = CFG_METHOD_2; + tp->HwIcVerUnknown = TRUE; + } + + tp->efuse_ver = EFUSE_SUPPORT_V4; + break; + default: + printk("unknown chip version (%x)\n",reg); + tp->mcfg = CFG_METHOD_DEFAULT; + tp->HwIcVerUnknown = TRUE; + tp->efuse_ver = EFUSE_NOT_SUPPORT; + break; + } +} + +static void +rtl8127_print_mac_version(struct rtl8127_private *tp) +{ + int i; + for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { + if (tp->mcfg == rtl_chip_info[i].mcfg) { + dprintk("Realtek %s Ethernet controller mcfg = %04d\n", + MODULENAME, rtl_chip_info[i].mcfg); + return; + } + } + + dprintk("mac_version == Unknown\n"); +} + +static void +rtl8127_tally_counter_addr_fill(struct rtl8127_private *tp) +{ + if (!tp->tally_paddr) + return; + + RTL_W32(tp, CounterAddrHigh, (u64)tp->tally_paddr >> 32); + RTL_W32(tp, CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32))); +} + +static void +rtl8127_tally_counter_clear(struct rtl8127_private *tp) +{ + if (!tp->tally_paddr) + return; + + RTL_W32(tp, CounterAddrHigh, (u64)tp->tally_paddr >> 32); + RTL_W32(tp, CounterAddrLow, ((u64)tp->tally_paddr & (DMA_BIT_MASK(32))) | CounterReset); +} + +static void +rtl8127_clear_phy_ups_reg(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA466, BIT_0); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA468, BIT_3 | BIT_1); +} + +static int +rtl8127_is_ups_resume(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + return (rtl8127_mac_ocp_read(tp, 0xD42C) & BIT_8); +} + +static void +rtl8127_clear_ups_resume_bit(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_clear_mac_ocp_bit(tp, 0xD42C, BIT_8); +} + +static u8 +rtl8127_get_phy_state(struct rtl8127_private *tp) +{ + return (rtl8127_mdio_direct_read_phy_ocp(tp, 0xA420) & 0x7); +} + +static void +rtl8127_wait_phy_ups_resume(struct net_device *dev, u16 PhyState) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + for (i=0; i< 100; i++) { + if (rtl8127_get_phy_state(tp) == PhyState) + break; + else + mdelay(1); + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) + WARN_ON_ONCE(i == 100); +#endif +} + +void +rtl8127_enable_now_is_oob(struct rtl8127_private *tp) +{ + if (tp->HwSuppNowIsOobVer == 1) + RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) | Now_is_oob); +} + +void +rtl8127_disable_now_is_oob(struct rtl8127_private *tp) +{ + if (tp->HwSuppNowIsOobVer == 1) + RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) & ~Now_is_oob); +} + +static void +rtl8127_exit_oob(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u16 data16; + + rtl8127_disable_rx_packet_filter(tp); + + if (HW_DASH_SUPPORT_DASH(tp)) { + rtl8127_driver_start(tp); + rtl8127_dash2_disable_txrx(dev); +#ifdef ENABLE_DASH_SUPPORT + DashHwInit(dev); +#endif + } + +#ifdef ENABLE_REALWOW_SUPPORT + rtl8127_realwow_hw_init(dev); +#else + rtl8127_mac_ocp_write(tp, 0xC0BC, 0x00FF); +#endif //ENABLE_REALWOW_SUPPORT + + rtl8127_nic_reset(dev); + + rtl8127_disable_now_is_oob(tp); + + data16 = rtl8127_mac_ocp_read(tp, 0xE8DE) & ~BIT_14; + rtl8127_mac_ocp_write(tp, 0xE8DE, data16); + rtl8127_wait_ll_share_fifo_ready(dev); + + rtl8127_mac_ocp_write(tp, 0xC0AA, 0x07D0); +#ifdef ENABLE_LIB_SUPPORT + rtl8127_mac_ocp_write(tp, 0xC0A6, 0x04E2); +#else + rtl8127_mac_ocp_write(tp, 0xC0A6, 0x01B5); +#endif + rtl8127_mac_ocp_write(tp, 0xC01E, 0x5555); + + rtl8127_wait_ll_share_fifo_ready(dev); + + //wait ups resume (phy state 2) + if (rtl8127_is_ups_resume(dev)) { + rtl8127_wait_phy_ups_resume(dev, 2); + rtl8127_clear_ups_resume_bit(dev); + rtl8127_clear_phy_ups_reg(dev); + } +} + +void +rtl8127_hw_disable_mac_mcu_bps(struct net_device *dev) +{ + u16 regAddr; + + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_enable_aspm_clkreq_lock(tp, 0); + + rtl8127_mac_ocp_write(tp, 0xFC48, 0x0000); + + for (regAddr = 0xFC28; regAddr < 0xFC48; regAddr += 2) { + rtl8127_mac_ocp_write(tp, regAddr, 0x0000); + } + + fsleep(3000); + + rtl8127_mac_ocp_write(tp, 0xFC26, 0x0000); +} + +#ifndef ENABLE_USE_FIRMWARE_FILE +static void +rtl8127_switch_mac_mcu_ram_code_page(struct rtl8127_private *tp, u16 page) +{ + u16 tmpUshort; + + page &= (BIT_1 | BIT_0); + tmpUshort = rtl8127_mac_ocp_read(tp, 0xE446); + tmpUshort &= ~(BIT_1 | BIT_0); + tmpUshort |= page; + rtl8127_mac_ocp_write(tp, 0xE446, tmpUshort); +} + +static void +_rtl8127_set_hw_mcu_patch_code_ver(struct rtl8127_private *tp, u64 ver) +{ + int i; + + /* Switch to page 2 */ + rtl8127_switch_mac_mcu_ram_code_page(tp, 2); + + for (i = 0; i < 8; i += 2) { + rtl8127_mac_ocp_write(tp, 0xF9F8 + 6 - i, (u16)ver); + ver >>= 16; + } + + /* Switch back to page 0 */ + rtl8127_switch_mac_mcu_ram_code_page(tp, 0); +} + +static void +rtl8127_set_hw_mcu_patch_code_ver(struct rtl8127_private *tp, u64 ver) +{ + _rtl8127_set_hw_mcu_patch_code_ver(tp, ver); + + tp->hw_mcu_patch_code_ver = ver; +} + +static u64 +rtl8127_get_hw_mcu_patch_code_ver(struct rtl8127_private *tp) +{ + u64 ver; + int i; + + /* Switch to page 2 */ + rtl8127_switch_mac_mcu_ram_code_page(tp, 2); + + ver = 0; + for (i = 0; i < 8; i += 2) { + ver <<= 16; + ver |= rtl8127_mac_ocp_read(tp, 0xF9F8 + i); + } + + /* Switch back to page 0 */ + rtl8127_switch_mac_mcu_ram_code_page(tp, 0); + + return ver; +} + +static u64 +rtl8127_get_bin_mcu_patch_code_ver(const u16 *entry, u16 entry_cnt) +{ + u64 ver; + int i; + + if (entry == NULL || entry_cnt == 0 || entry_cnt < 4) + return 0; + + ver = 0; + for (i = 0; i < 4; i++) { + ver <<= 16; + ver |= entry[entry_cnt - 4 + i]; + } + + return ver; +} + +static void +_rtl8127_write_mac_mcu_ram_code(struct rtl8127_private *tp, const u16 *entry, u16 entry_cnt) +{ + u16 i; + + for (i = 0; i < entry_cnt; i++) + rtl8127_mac_ocp_write(tp, 0xF800 + i * 2, entry[i]); +} + +static void +_rtl8127_write_mac_mcu_ram_code_with_page(struct rtl8127_private *tp, const u16 *entry, u16 entry_cnt, u16 page_size) +{ + u16 i; + u16 offset; + + if (page_size == 0) + return; + + for (i = 0; i < entry_cnt; i++) { + offset = i % page_size; + if (offset == 0) { + u16 page = (i / page_size); + rtl8127_switch_mac_mcu_ram_code_page(tp, page); + } + rtl8127_mac_ocp_write(tp, 0xF800 + offset * 2, entry[i]); + } +} + +static void +rtl8127_write_mac_mcu_ram_code(struct rtl8127_private *tp, const u16 *entry, u16 entry_cnt) +{ + if (FALSE == HW_SUPPORT_MAC_MCU(tp)) + return; + + if (entry == NULL || entry_cnt == 0) + return; + + if (tp->MacMcuPageSize > 0) + _rtl8127_write_mac_mcu_ram_code_with_page(tp, entry, entry_cnt, tp->MacMcuPageSize); + else + _rtl8127_write_mac_mcu_ram_code(tp, entry, entry_cnt); + + if (tp->bin_mcu_patch_code_ver > 0) + rtl8127_set_hw_mcu_patch_code_ver(tp, tp->bin_mcu_patch_code_ver); +} + +static void +rtl8127_set_mac_mcu_8127a_tc(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + static const u16 mcu_patch_code[] = { + 0xE010, 0xE019, 0xE01B, 0xE01D, 0xE029, 0xE02C, 0xE0E1, 0xE192, 0xE194, + 0xE196, 0xE198, 0xE19A, 0xE19C, 0xE19E, 0xE1A0, 0xE1A2, 0xC008, 0x7100, + 0x4897, 0x9900, 0xC005, 0xC602, 0xBE00, 0x3D8E, 0xD428, 0xD400, 0xC602, + 0xBE00, 0x0000, 0xC502, 0xBD00, 0x0000, 0x48C3, 0x4847, 0x48C1, 0x8CF8, + 0x74F8, 0x74F8, 0x74F8, 0x4842, 0x8CF8, 0x1E10, 0xC502, 0xBD00, 0x14BA, + 0x1E10, 0xC502, 0xBD00, 0x14EE, 0xC643, 0x76C0, 0x49E1, 0xF13F, 0xC140, + 0x7720, 0x49E0, 0xF003, 0x1B00, 0xE00A, 0x49E2, 0xF003, 0x1B04, 0xE006, + 0x49E4, 0xF003, 0x1B08, 0xE002, 0x1B0C, 0x21B8, 0x1A0E, 0x44DA, 0xE893, + 0x481C, 0xE884, 0xE001, 0x49E0, 0xF003, 0x1B00, 0xE00A, 0x49E2, 0xF003, + 0x1B04, 0xE006, 0x49E4, 0xF003, 0x1B08, 0xE002, 0x1B0C, 0x21B8, 0x1A12, + 0x44DA, 0xE87F, 0x481F, 0xE870, 0xE001, 0x49E0, 0xF003, 0x1B00, 0xE00A, + 0x49E2, 0xF003, 0x1B04, 0xE006, 0x49E4, 0xF003, 0x1B08, 0xE002, 0x1B0C, + 0x21B8, 0x1A1C, 0x44DA, 0xE86B, 0x481F, 0xE85C, 0xE004, 0xE04F, 0xDD98, + 0xD450, 0x49E0, 0xF003, 0x1B00, 0xE00A, 0x49E2, 0xF003, 0x1B04, 0xE006, + 0x49E4, 0xF003, 0x1B08, 0xE002, 0x1B0C, 0x21B8, 0x1A0E, 0x44DA, 0xE854, + 0x489E, 0x481F, 0xE844, 0xE001, 0x1908, 0xE83E, 0x49E0, 0xF003, 0x1B00, + 0xE00A, 0x49E2, 0xF003, 0x1B04, 0xE006, 0x49E4, 0xF003, 0x1B08, 0xE002, + 0x1B0C, 0x21B8, 0x1A8A, 0x44DA, 0xE83D, 0x4813, 0xE82E, 0x49F9, 0xF106, + 0x4838, 0xE837, 0x4813, 0xE828, 0xE001, 0x49E0, 0xF003, 0x1B00, 0xE00A, + 0x49E2, 0xF003, 0x1B04, 0xE006, 0x49E4, 0xF003, 0x1B08, 0xE002, 0x1B0C, + 0x21B8, 0x1A84, 0x44DA, 0xE823, 0x4890, 0x4811, 0xE813, 0x49F9, 0xF106, + 0x4838, 0xE81C, 0x4890, 0x4811, 0xE80C, 0xC207, 0x7440, 0xC602, 0xBE00, + 0x14CC, 0x0FFE, 0xDE20, 0xE092, 0xC3FD, 0xE802, 0xFF80, 0xC0FB, 0x7202, + 0x49AE, 0xF1FE, 0x9900, 0x44D3, 0x4413, 0x482F, 0x9A02, 0x7202, 0x49AE, + 0xF1FE, 0xFF80, 0xC0EE, 0x7202, 0x49AE, 0xF1FE, 0x44D3, 0x4413, 0x48AF, + 0x9A02, 0x7202, 0x49AE, 0xF1FE, 0x7100, 0xFF80, 0xB401, 0xB402, 0xB404, + 0xB407, 0xC61F, 0x76C0, 0x49E1, 0xF164, 0xC11C, 0x7720, 0x1906, 0xE88A, + 0x1B0C, 0x21B8, 0x1A40, 0x44DA, 0xE895, 0x4810, 0xE886, 0x190C, 0xE881, + 0x1B08, 0x21B8, 0x1A26, 0x44DA, 0xE88C, 0x4890, 0x4891, 0xE87C, 0x49F9, + 0xF107, 0x4898, 0x4899, 0xE877, 0xE003, 0xDD98, 0xD450, 0x1908, 0xE86F, + 0x49E0, 0xF003, 0x1B00, 0xE00A, 0x49E2, 0xF003, 0x1B04, 0xE006, 0x49E2, + 0xF003, 0x1B08, 0xE002, 0x1B0C, 0x21B8, 0x1A5C, 0x44DA, 0xE86E, 0x4897, + 0x4898, 0x4819, 0x481A, 0xE85C, 0x49F9, 0xF109, 0x4838, 0xE865, 0x4897, + 0x4898, 0x4819, 0x481A, 0xE853, 0xE001, 0x190A, 0xE84D, 0x1B00, 0xE85B, + 0x44E1, 0x4838, 0xE858, 0x44E9, 0x1908, 0xE845, 0x49E0, 0xF003, 0x1B00, + 0xE00A, 0x49E2, 0xF003, 0x1B04, 0xE006, 0x49E4, 0xF003, 0x1B08, 0xE002, + 0x1B0C, 0x21B8, 0x1A86, 0x44DA, 0xE844, 0x44CC, 0xE835, 0x49F9, 0xF108, + 0x4838, 0xE83E, 0x44CD, 0xE82F, 0xE003, 0xE021, 0xFFC0, 0x190A, 0xE827, + 0x1B00, 0x4839, 0xE834, 0x249A, 0x1C00, 0x44E1, 0x1909, 0xE81F, 0x49E0, + 0xF003, 0x1B00, 0xE00A, 0x49E2, 0xF003, 0x1B04, 0xE006, 0x49E4, 0xF003, + 0x1B08, 0xE002, 0x1B0C, 0x21B8, 0x1A1A, 0x44DA, 0xE81E, 0xC5E4, 0x414D, + 0x418C, 0xE80D, 0xB007, 0xB004, 0xB002, 0xB001, 0xC602, 0xBE00, 0x14B2, + 0x0FFE, 0xDE20, 0xC3FE, 0xE802, 0xFF80, 0xC0FC, 0x7202, 0x49AE, 0xF1FE, + 0x9900, 0x44D3, 0x4413, 0x482F, 0x9A02, 0x7202, 0x49AE, 0xF1FE, 0xFF80, + 0xC0EF, 0x7202, 0x49AE, 0xF1FE, 0x44D3, 0x4413, 0x48AF, 0x9A02, 0x7202, + 0x49AE, 0xF1FE, 0x7100, 0xFF80, 0xC502, 0xBD00, 0x0000, 0xC502, 0xBD00, + 0x0000, 0xC502, 0xBD00, 0x0000, 0xC302, 0xBB00, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC102, 0xB900, 0x0000, 0xC102, 0xB900, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC602, 0xBE00, 0x0000, 0x1332, 0x0018, 0x0C05, 0x140D + }; + + /* Get BIN mac mcu patch code version */ + tp->bin_mcu_patch_code_ver = rtl8127_get_bin_mcu_patch_code_ver(mcu_patch_code, ARRAY_SIZE(mcu_patch_code)); + + if (tp->hw_mcu_patch_code_ver != tp->bin_mcu_patch_code_ver) + rtl8127_write_mac_mcu_ram_code(tp, mcu_patch_code, ARRAY_SIZE(mcu_patch_code)); + + rtl8127_mac_ocp_write(tp, 0xFC26, 0x8000); + + rtl8127_mac_ocp_write(tp, 0xFC2E, 0x14B8); + rtl8127_mac_ocp_write(tp, 0xFC30, 0x14EC); + + rtl8127_mac_ocp_write(tp, 0xFC48, 0x0018); +} + +static void +_rtl8127_set_mac_mcu_8127a_1(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + static const u16 mcu_patch_code[] = { + 0xE010, 0xE014, 0xE018, 0xE01C, 0xE020, 0xE033, 0xE035, 0xE037, 0xE039, + 0xE03B, 0xE03D, 0xE03F, 0xE041, 0xE043, 0xE045, 0xE047, 0x7020, 0x4809, + 0xC502, 0xBD00, 0x1522, 0x7760, 0x4879, 0xC002, 0xB800, 0x41E2, 0x7160, + 0x4819, 0xC302, 0xBB00, 0x508E, 0x7720, 0x4879, 0xC102, 0xB900, 0x50F8, + 0x9F86, 0xB400, 0xB401, 0xB402, 0xB403, 0xC00D, 0x7100, 0xC20C, 0x7340, + 0x418B, 0x9900, 0xB003, 0xB002, 0xB001, 0xB000, 0xC702, 0xBF00, 0x3550, + 0xFC48, 0xD482, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC102, + 0xB900, 0x0000, 0xC302, 0xBB00, 0x0000, 0xC002, 0xB800, 0x0000, 0xC002, + 0xB800, 0x0000, 0xC502, 0xBD00, 0x0000, 0xC102, 0xB900, 0x0000, 0xC102, + 0xB900, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0x6961, + 0x0019, 0x0311, 0x1431 + }; + + /* Get BIN mac mcu patch code version */ + tp->bin_mcu_patch_code_ver = rtl8127_get_bin_mcu_patch_code_ver(mcu_patch_code, ARRAY_SIZE(mcu_patch_code)); + + if (tp->hw_mcu_patch_code_ver != tp->bin_mcu_patch_code_ver) + rtl8127_write_mac_mcu_ram_code(tp, mcu_patch_code, ARRAY_SIZE(mcu_patch_code)); + + rtl8127_mac_ocp_write(tp, 0xFC26, 0x8000); + + rtl8127_mac_ocp_write(tp, 0xFC28, 0x1520); + rtl8127_mac_ocp_write(tp, 0xFC2A, 0x41E0); + rtl8127_mac_ocp_write(tp, 0xFC2C, 0x508C); + rtl8127_mac_ocp_write(tp, 0xFC2E, 0x50F6); + rtl8127_mac_ocp_write(tp, 0xFC30, 0x354E); + + rtl8127_mac_ocp_write(tp, 0xFC48, 0x001F); +} + +static void +rtl8127_set_mac_mcu_8127a_1(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u8 tmp = (u8)rtl8127_mac_ocp_read(tp, 0xD006); + + if (tmp != 0x04) + return; + + _rtl8127_set_mac_mcu_8127a_1(dev); +} + +static void +rtl8127_hw_mac_mcu_config(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (tp->NotWrMcuPatchCode == TRUE) + return; + + rtl8127_hw_disable_mac_mcu_bps(dev); + + /* Get H/W mac mcu patch code version */ + tp->hw_mcu_patch_code_ver = rtl8127_get_hw_mcu_patch_code_ver(tp); + + switch (tp->mcfg) { + case CFG_METHOD_1: + rtl8127_set_mac_mcu_8127a_tc(dev); + break; + case CFG_METHOD_2: + rtl8127_set_mac_mcu_8127a_1(dev); + break; + default: + break; + } +} +#endif + +#ifdef ENABLE_USE_FIRMWARE_FILE +static void rtl8127_release_firmware(struct rtl8127_private *tp) +{ + if (tp->rtl_fw) { + rtl8127_fw_release_firmware(tp->rtl_fw); + kfree(tp->rtl_fw); + tp->rtl_fw = NULL; + } +} + +static void rtl8127_apply_firmware(struct rtl8127_private *tp) +{ + /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ + if (tp->rtl_fw) { + rtl8127_fw_write_firmware(tp, tp->rtl_fw); + /* At least one firmware doesn't reset tp->ocp_base. */ + tp->ocp_base = OCP_STD_PHY_BASE; + + /* PHY soft reset may still be in progress */ + //phy_read_poll_timeout(tp->phydev, MII_BMCR, val, + // !(val & BMCR_RESET), + // 50000, 600000, true); + rtl8127_wait_phy_reset_complete(tp); + + tp->hw_ram_code_ver = rtl8127_get_hw_phy_mcu_code_ver(tp); + tp->sw_ram_code_ver = tp->hw_ram_code_ver; + tp->HwHasWrRamCodeToMicroP = TRUE; + } +} +#endif + +static void +rtl8127_hw_init(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u32 csi_tmp; + + rtl8127_enable_aspm_clkreq_lock(tp, 0); + rtl8127_enable_force_clkreq(tp, 0); + + //Disable UPS + rtl8127_mac_ocp_write(tp, 0xD40A, rtl8127_mac_ocp_read(tp, 0xD40A) & ~(BIT_4)); + +#ifndef ENABLE_USE_FIRMWARE_FILE + if (!tp->rtl_fw) + rtl8127_hw_mac_mcu_config(dev); +#endif + + //Set PCIE uncorrectable error status mask pcie 0x108 + csi_tmp = rtl8127_csi_read(tp, 0x108); + csi_tmp |= BIT_20; + rtl8127_csi_write(tp, 0x108, csi_tmp); + + rtl8127_enable_cfg9346_write(tp); + rtl8127_disable_linkchg_wakeup(dev); + rtl8127_disable_cfg9346_write(tp); + rtl8127_disable_magic_packet(dev); + rtl8127_disable_d0_speedup(tp); + rtl8127_set_pci_pme(tp, 0); + if (s0_magic_packet == 1) + rtl8127_enable_magic_packet(dev); + +#ifdef ENABLE_USE_FIRMWARE_FILE + if (tp->rtl_fw && + !tp->resume_not_chg_speed && + !(HW_DASH_SUPPORT_TYPE_3(tp) && + tp->HwPkgDet == 0x06)) + rtl8127_apply_firmware(tp); +#endif +} + +static void +rtl8127_clear_ephy_ext_addr(struct rtl8127_private *tp) +{ + rtl8127_set_ephy_ext_addr(tp, 0x0000); +} + +static void +rtl8127_hw_ephy_config_8127_1(struct rtl8127_private *tp) +{ + rtl8127_ephy_write(tp, 0x8088, 0x0064); + rtl8127_ephy_write(tp, 0x8488, 0x0064); + rtl8127_ephy_write(tp, 0x8888, 0x0064); + rtl8127_ephy_write(tp, 0x8C88, 0x0064); + rtl8127_ephy_write(tp, 0x8188, 0x0064); + rtl8127_ephy_write(tp, 0x8588, 0x0064); + rtl8127_ephy_write(tp, 0x8988, 0x0064); + rtl8127_ephy_write(tp, 0x8D88, 0x0064); + rtl8127_ephy_write(tp, 0x808C, 0x09B0); + rtl8127_ephy_write(tp, 0x848C, 0x09B0); + rtl8127_ephy_write(tp, 0x888C, 0x0F90); + rtl8127_ephy_write(tp, 0x8C8C, 0x0F90); + rtl8127_ephy_write(tp, 0x818C, 0x09B0); + rtl8127_ephy_write(tp, 0x858C, 0x09B0); + rtl8127_ephy_write(tp, 0x898C, 0x0F90); + rtl8127_ephy_write(tp, 0x8D8C, 0x0F90); + rtl8127_ephy_write(tp, 0x808A, 0x09B8); + rtl8127_ephy_write(tp, 0x848A, 0x09B8); + rtl8127_ephy_write(tp, 0x888A, 0x0F98); + rtl8127_ephy_write(tp, 0x8C8A, 0x0F98); + rtl8127_ephy_write(tp, 0x818A, 0x09B8); + rtl8127_ephy_write(tp, 0x858A, 0x09B8); + rtl8127_ephy_write(tp, 0x898A, 0x0F98); + rtl8127_ephy_write(tp, 0x8D8A, 0x0F98); + rtl8127_ephy_write(tp, 0x9020, 0x0080); + rtl8127_ephy_write(tp, 0x9420, 0x0080); + rtl8127_ephy_write(tp, 0x9820, 0x0080); + rtl8127_ephy_write(tp, 0x9C20, 0x0080); + rtl8127_ephy_write(tp, 0x901E, 0x0190); + rtl8127_ephy_write(tp, 0x941E, 0x0190); + rtl8127_ephy_write(tp, 0x981E, 0x0140); + rtl8127_ephy_write(tp, 0x9C1E, 0x0140); + rtl8127_ephy_write(tp, 0x901C, 0x0190); + rtl8127_ephy_write(tp, 0x941C, 0x0190); + rtl8127_ephy_write(tp, 0x981C, 0x0140); + rtl8127_ephy_write(tp, 0x9C1C, 0x0140); + + /* Clear extended address */ + rtl8127_clear_ephy_ext_addr(tp); +} + +static void +rtl8127_hw_ephy_config(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + switch (tp->mcfg) { + case CFG_METHOD_2: + rtl8127_hw_ephy_config_8127_1(tp); + break; + default: + /* nothing to do */ + break; + } +} + +static u16 +rtl8127_get_hw_phy_mcu_code_ver(struct rtl8127_private *tp) +{ + u16 hw_ram_code_ver; + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); + hw_ram_code_ver = rtl8127_mdio_direct_read_phy_ocp(tp, 0xA438); + + return hw_ram_code_ver; +} + +static int +rtl8127_check_hw_phy_mcu_code_ver(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int ram_code_ver_match = 0; + + tp->hw_ram_code_ver = rtl8127_get_hw_phy_mcu_code_ver(tp); + + if (tp->hw_ram_code_ver == tp->sw_ram_code_ver) { + ram_code_ver_match = 1; + tp->HwHasWrRamCodeToMicroP = TRUE; + } + + return ram_code_ver_match; +} + +bool +rtl8127_set_phy_mcu_patch_request(struct rtl8127_private *tp) +{ + u16 gphy_val; + u16 WaitCount; + bool bSuccess = TRUE; + + rtl8127_set_eth_phy_ocp_bit(tp, 0xB820, BIT_4); + + WaitCount = 0; + do { + gphy_val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xB800); + udelay(100); + WaitCount++; + } while (!(gphy_val & BIT_6) && (WaitCount < 1000)); + + if (!(gphy_val & BIT_6) && (WaitCount == 1000)) + bSuccess = FALSE; + + if (!bSuccess) + dprintk("rtl8127_set_phy_mcu_patch_request fail.\n"); + + return bSuccess; +} + +bool +rtl8127_clear_phy_mcu_patch_request(struct rtl8127_private *tp) +{ + u16 gphy_val; + u16 WaitCount; + bool bSuccess = TRUE; + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB820, BIT_4); + + WaitCount = 0; + do { + gphy_val = rtl8127_mdio_direct_read_phy_ocp(tp, 0xB800); + udelay(100); + WaitCount++; + } while ((gphy_val & BIT_6) && (WaitCount < 1000)); + + if ((gphy_val & BIT_6) && (WaitCount == 1000)) + bSuccess = FALSE; + + if (!bSuccess) + dprintk("rtl8127_clear_phy_mcu_patch_request fail.\n"); + + return bSuccess; +} + +#ifndef ENABLE_USE_FIRMWARE_FILE +static void +rtl8127_write_hw_phy_mcu_code_ver(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, tp->sw_ram_code_ver); + tp->hw_ram_code_ver = tp->sw_ram_code_ver; +} + +static void +rtl8127_set_phy_mcu_ram_code(struct net_device *dev, const u16 *ramcode, u16 codesize) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u16 i; + u16 addr; + u16 val; + + if (ramcode == NULL || codesize % 2) + goto out; + + for (i = 0; i < codesize; i += 2) { + addr = ramcode[i]; + val = ramcode[i + 1]; + if (addr == 0xFFFF && val == 0xFFFF) + break; + rtl8127_mdio_direct_write_phy_ocp(tp, addr, val); + } + +out: + return; +} + +static void +rtl8127_enable_phy_disable_mode(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + switch (tp->HwSuppCheckPhyDisableModeVer) { + case 3: + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_5); + break; + } + + dprintk("enable phy disable mode.\n"); +} + +static void +rtl8127_disable_phy_disable_mode(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + switch (tp->HwSuppCheckPhyDisableModeVer) { + case 3: + RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_5); + break; + } + + mdelay(1); + + dprintk("disable phy disable mode.\n"); +} + +static const u16 phy_mcu_ram_code_8127a_tc_1[] = { + 0xa436, 0x8023, 0xa438, 0x3200, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xBF8E, 0x1410, 0xBF8E, 0x1410, 0xBF90, 0xC20E, 0xBF9E, 0xBFFC, + 0xBFAA, 0x1924, 0xBFB4, 0x0B1E, 0xBFB6, 0x3740, 0xBFB8, 0x460E, + 0xBFBE, 0x000D, 0xBF8A, 0x3FF7, 0xBF9A, 0x0007, 0xBF1E, 0x01FF, + 0xBF1E, 0x01FF, 0xBF1E, 0x01FF, 0xBF2E, 0x454D, 0xbc10, 0xD50C, + 0xbc10, 0x950C, 0xbc10, 0xD50C, 0xbc10, 0x550C, 0xbddE, 0xEF00, + 0xbd32, 0xF000, 0xbd2C, 0x0800, 0xbdc8, 0x04B0, 0xbdc8, 0x0CB0, + 0xBD92, 0x0003, 0xBD94, 0x8000, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xBD92, 0x0016, 0xBD94, 0x1000, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xBD92, 0x0016, 0xBD94, 0x1200, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xBD92, 0x0000, 0xBD94, 0x1F1F, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xBD92, 0x0001, 0xBD94, 0x1F00, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xBD92, 0x0003, 0xBD94, 0x0000, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xBD92, 0x0016, 0xBD94, 0x0000, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xBD92, 0x0000, 0xBD94, 0x0000, 0xBD96, 0x000f, 0xBD96, 0x0000, + 0xbdc8, 0x08B0, 0xbdc8, 0x00B0, 0xbd32, 0x0000, 0xbd2C, 0x0000, + 0xbc10, 0x750C, 0xbc10, 0x650C, 0xbc10, 0x750C, 0xbc10, 0x550C, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x809b, 0xa438, 0x1800, 0xa438, 0x8145, + 0xa438, 0x1800, 0xa438, 0x8197, 0xa438, 0x1800, 0xa438, 0x81d4, + 0xa438, 0x1800, 0xa438, 0x8214, 0xa438, 0x1800, 0xa438, 0x8226, + 0xa438, 0x1800, 0xa438, 0x8232, 0xa438, 0xd707, 0xa438, 0x4141, + 0xa438, 0xd70a, 0xa438, 0x4115, 0xa438, 0xd705, 0xa438, 0x40da, + 0xa438, 0xb808, 0xa438, 0xd028, 0xa438, 0xd1c1, 0xa438, 0x1800, + 0xa438, 0x801e, 0xa438, 0x9808, 0xa438, 0xd07b, 0xa438, 0xd1c5, + 0xa438, 0xbe10, 0xa438, 0xd503, 0xa438, 0xa108, 0xa438, 0xd505, + 0xa438, 0x8103, 0xa438, 0xd504, 0xa438, 0xa002, 0xa438, 0xa302, + 0xa438, 0xd707, 0xa438, 0x4061, 0xa438, 0xd503, 0xa438, 0x8b01, + 0xa438, 0xd500, 0xa438, 0xc48a, 0xa438, 0xd503, 0xa438, 0xcc09, + 0xa438, 0xcd58, 0xa438, 0xaf01, 0xa438, 0xd500, 0xa438, 0x1000, + 0xa438, 0x1764, 0xa438, 0xd719, 0xa438, 0x606c, 0xa438, 0xd704, + 0xa438, 0x645c, 0xa438, 0xd75e, 0xa438, 0x604d, 0xa438, 0xfff8, + 0xa438, 0x9e10, 0xa438, 0x1000, 0xa438, 0x1764, 0xa438, 0xd719, + 0xa438, 0x606c, 0xa438, 0xd704, 0xa438, 0x631c, 0xa438, 0xd75e, + 0xa438, 0x404d, 0xa438, 0xfff8, 0xa438, 0xd504, 0xa438, 0xaa18, + 0xa438, 0xa001, 0xa438, 0xa1e0, 0xa438, 0xd500, 0xa438, 0x1000, + 0xa438, 0x1764, 0xa438, 0xd719, 0xa438, 0x7fac, 0xa438, 0xd504, + 0xa438, 0xa001, 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x1764, + 0xa438, 0xd704, 0xa438, 0x5f5c, 0xa438, 0xd719, 0xa438, 0x3aaf, + 0xa438, 0x8058, 0xa438, 0xf016, 0xa438, 0xd707, 0xa438, 0x6121, + 0xa438, 0x1000, 0xa438, 0x16f8, 0xa438, 0xd503, 0xa438, 0xcd59, + 0xa438, 0xaf01, 0xa438, 0xd500, 0xa438, 0x1800, 0xa438, 0x0e49, + 0xa438, 0xd503, 0xa438, 0x8040, 0xa438, 0xd500, 0xa438, 0x1000, + 0xa438, 0x16f8, 0xa438, 0xd503, 0xa438, 0xcd5a, 0xa438, 0xaf01, + 0xa438, 0xd500, 0xa438, 0x1800, 0xa438, 0x0e2f, 0xa438, 0xd504, + 0xa438, 0xa008, 0xa438, 0xa204, 0xa438, 0xd500, 0xa438, 0x1000, + 0xa438, 0x1764, 0xa438, 0xd701, 0xa438, 0x5fa0, 0xa438, 0xd503, + 0xa438, 0xa082, 0xa438, 0xd500, 0xa438, 0xd71e, 0xa438, 0x4097, + 0xa438, 0xd078, 0xa438, 0xd1aa, 0xa438, 0xf003, 0xa438, 0xd078, + 0xa438, 0xd1aa, 0xa438, 0xd707, 0xa438, 0x4081, 0xa438, 0xd70a, + 0xa438, 0x4055, 0xa438, 0xf014, 0xa438, 0xd706, 0xa438, 0x6065, + 0xa438, 0xcc89, 0xa438, 0xf002, 0xa438, 0xcc8b, 0xa438, 0x1000, + 0xa438, 0x0bb2, 0xa438, 0xd705, 0xa438, 0x2ad0, 0xa438, 0x808f, + 0xa438, 0xf003, 0xa438, 0x1000, 0xa438, 0x0bb8, 0xa438, 0x1000, + 0xa438, 0x0bbe, 0xa438, 0x607a, 0xa438, 0x9c01, 0xa438, 0xf002, + 0xa438, 0xbc01, 0xa438, 0x1000, 0xa438, 0x0cc9, 0xa438, 0x1800, + 0xa438, 0x132f, 0xa438, 0x9a10, 0xa438, 0x9d02, 0xa438, 0xd706, + 0xa438, 0x629a, 0xa438, 0x61bb, 0xa438, 0xd707, 0xa438, 0x60d7, + 0xa438, 0xd70a, 0xa438, 0x6196, 0xa438, 0xd0e5, 0xa438, 0xd1e7, + 0xa438, 0xf012, 0xa438, 0xd70a, 0xa438, 0x5f55, 0xa438, 0xd060, + 0xa438, 0xd1e8, 0xa438, 0xf00d, 0xa438, 0xd056, 0xa438, 0xd1e8, + 0xa438, 0xf00a, 0xa438, 0xd043, 0xa438, 0xd1e8, 0xa438, 0xf007, + 0xa438, 0x609b, 0xa438, 0xd078, 0xa438, 0xd1e9, 0xa438, 0xf003, + 0xa438, 0xd07f, 0xa438, 0xd1e9, 0xa438, 0xd503, 0xa438, 0xab01, + 0xa438, 0xd500, 0xa438, 0xd706, 0xa438, 0x6139, 0xa438, 0xd503, + 0xa438, 0x6065, 0xa438, 0xa7f0, 0xa438, 0xf003, 0xa438, 0x0cf0, + 0xa438, 0x0750, 0xa438, 0x8908, 0xa438, 0xf004, 0xa438, 0xd503, + 0xa438, 0xa908, 0xa438, 0x87f0, 0xa438, 0xd503, 0xa438, 0xa040, + 0xa438, 0xd500, 0xa438, 0xd705, 0xa438, 0x407b, 0xa438, 0x1000, + 0xa438, 0x1ac8, 0xa438, 0xd503, 0xa438, 0x0c07, 0xa438, 0x0902, + 0xa438, 0xa008, 0xa438, 0xd500, 0xa438, 0x9d80, 0xa438, 0xc48c, + 0xa438, 0xd73e, 0xa438, 0x6000, 0xa438, 0xd706, 0xa438, 0x419b, + 0xa438, 0xd503, 0xa438, 0x0c87, 0xa438, 0x0981, 0xa438, 0xd500, + 0xa438, 0xd073, 0xa438, 0xd1b7, 0xa438, 0xc490, 0xa438, 0x1000, + 0xa438, 0x1764, 0xa438, 0xd704, 0xa438, 0x5fbb, 0xa438, 0xd503, + 0xa438, 0xd706, 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0xa438, 0x683e, 0xa436, 0xb88a, 0xa438, 0x6ae6, + 0xa436, 0xb88c, 0xa438, 0x5119, 0xa436, 0xb838, 0xa438, 0x00ff, + 0xb820, 0x0010, 0xa464, 0x0001, 0xa436, 0x8474, 0xa438, 0x0000, + 0xa436, 0x8608, 0xa438, 0xaf86, 0xa438, 0x20af, 0xa438, 0x865e, + 0xa438, 0xaf86, 0xa438, 0xacaf, 0xa438, 0x86b7, 0xa438, 0xaf88, + 0xa438, 0xbdaf, 0xa438, 0x88d4, 0xa438, 0xaf88, 0xa438, 0xe3af, + 0xa438, 0x893f, 0xa438, 0xbf8a, 0xa438, 0x1102, 0xa438, 0x7589, + 0xa438, 0xbf8a, 0xa438, 0x1702, 0xa438, 0x756a, 0xa438, 0xbf8a, + 0xa438, 0x1d02, 0xa438, 0x756a, 0xa438, 0xbf8a, 0xa438, 0x1402, + 0xa438, 0x7589, 0xa438, 0xbf8a, 0xa438, 0x1a02, 0xa438, 0x756a, + 0xa438, 0xbf8a, 0xa438, 0x2002, 0xa438, 0x756a, 0xa438, 0xa200, + 0xa438, 0x08bf, 0xa438, 0x6e23, 0xa438, 0x0275, 0xa438, 0x3eae, + 0xa438, 0x0ca2, 0xa438, 0x0609, 0xa438, 0xe08f, 0xa438, 0x7dad, + 0xa438, 0x2003, 0xa438, 0xaf0f, 0xa438, 0xc9af, 0xa438, 0x0fd5, + 0xa438, 0xe084, 0xa438, 0x68a0, 0xa438, 0x0005, 0xa438, 0x0264, + 0xa438, 0xe6ae, 0xa438, 0x0ba0, 0xa438, 0x0105, 0xa438, 0x0265, + 0xa438, 0xb4ae, 0xa438, 0x0302, 0xa438, 0x8677, 0xa438, 0xaf64, + 0xa438, 0xe1f8, 0xa438, 0xf9e0, 0xa438, 0x8469, 0xa438, 0xe184, + 0xa438, 0x6a14, 0xa438, 0xe484, 0xa438, 0x69e5, 0xa438, 0x846a, + 0xa438, 0xe283, 0xa438, 0xade3, 0xa438, 0x83ae, 0xa438, 0x1b45, + 0xa438, 0x9f11, 0xa438, 0xee84, 0xa438, 0x6900, 0xa438, 0xee84, + 0xa438, 0x6a00, 0xa438, 0xee84, 0xa438, 0x6800, 0xa438, 0x0264, + 0xa438, 0xe6ae, 0xa438, 0x08e0, 0xa438, 0x8043, 0xa438, 0xf626, + 0xa438, 0xe480, 0xa438, 0x43fd, 0xa438, 0xfc04, 0xa438, 0xe080, + 0xa438, 0x43f6, 0xa438, 0x26e4, 0xa438, 0x8043, 0xa438, 0xaf65, + 0xa438, 0xa8ee, 0xa438, 0x8468, 0xa438, 0x0202, 0xa438, 0x86c9, + 0xa438, 0xe080, 0xa438, 0x43f6, 0xa438, 0x26e4, 0xa438, 0x8043, + 0xa438, 0xaf66, 0xa438, 0x0bf8, 0xa438, 0xf9ef, 0xa438, 0x59f9, + 0xa438, 0xfafb, 0xa438, 0xe18f, 0xa438, 0x7ea1, 0xa438, 0x0003, + 0xa438, 0xaf88, 0xa438, 0x64bf, 0xa438, 0x6c43, 0xa438, 0x0275, + 0xa438, 0x89d0, 0xa438, 0x003c, 0xa438, 0x008a, 0xa438, 0xad27, + 0xa438, 0x03af, 0xa438, 0x86fe, 0xa438, 0xee8f, 0xa438, 0x7e00, + 0xa438, 0xee84, 0xa438, 0x6d0f, 0xa438, 0xd401, 0xa438, 0x28d6, + 0xa438, 0x0010, 0xa438, 0x0288, 0xa438, 0x6caf, 0xa438, 0x8864, + 0xa438, 0xee84, 0xa438, 0x6d00, 0xa438, 0xd600, 0xa438, 0x8f02, + 0xa438, 0x889b, 0xa438, 0xee84, 0xa438, 0x6d01, 0xa438, 0xd600, + 0xa438, 0xc002, 0xa438, 0x886c, 0xa438, 0xee84, 0xa438, 0x6d01, + 0xa438, 0xd600, 0xa438, 0x8f02, 0xa438, 0x889b, 0xa438, 0xee84, + 0xa438, 0x6d02, 0xa438, 0xd600, 0xa438, 0xc002, 0xa438, 0x886c, + 0xa438, 0xee84, 0xa438, 0x6d02, 0xa438, 0xd600, 0xa438, 0x8f02, + 0xa438, 0x889b, 0xa438, 0xee84, 0xa438, 0x6d04, 0xa438, 0xd600, + 0xa438, 0xc002, 0xa438, 0x886c, 0xa438, 0xee84, 0xa438, 0x6d03, + 0xa438, 0xd600, 0xa438, 0x8f02, 0xa438, 0x889b, 0xa438, 0xee84, + 0xa438, 0x6d08, 0xa438, 0xd600, 0xa438, 0xc002, 0xa438, 0x886c, + 0xa438, 0xee84, 0xa438, 0x6d00, 0xa438, 0xd600, 0xa438, 0x9002, + 0xa438, 0x889b, 0xa438, 0xee84, 0xa438, 0x6d01, 0xa438, 0xd600, + 0xa438, 0xc102, 0xa438, 0x886c, 0xa438, 0xee84, 0xa438, 0x6d01, + 0xa438, 0xd600, 0xa438, 0x9002, 0xa438, 0x889b, 0xa438, 0xee84, + 0xa438, 0x6d02, 0xa438, 0xd600, 0xa438, 0xc102, 0xa438, 0x886c, + 0xa438, 0xee84, 0xa438, 0x6d02, 0xa438, 0xd600, 0xa438, 0x9002, + 0xa438, 0x889b, 0xa438, 0xee84, 0xa438, 0x6d04, 0xa438, 0xd600, + 0xa438, 0xc102, 0xa438, 0x886c, 0xa438, 0xee84, 0xa438, 0x6d03, + 0xa438, 0xd600, 0xa438, 0x9002, 0xa438, 0x889b, 0xa438, 0xee84, + 0xa438, 0x6d08, 0xa438, 0xd600, 0xa438, 0xc102, 0xa438, 0x886c, + 0xa438, 0xee84, 0xa438, 0x6d00, 0xa438, 0xd600, 0xa438, 0x9102, + 0xa438, 0x889b, 0xa438, 0xee84, 0xa438, 0x6d01, 0xa438, 0xd600, + 0xa438, 0xc202, 0xa438, 0x886c, 0xa438, 0xee84, 0xa438, 0x6d01, + 0xa438, 0xd600, 0xa438, 0x9102, 0xa438, 0x889b, 0xa438, 0xee84, + 0xa438, 0x6d02, 0xa438, 0xd600, 0xa438, 0xc202, 0xa438, 0x886c, + 0xa438, 0xee84, 0xa438, 0x6d02, 0xa438, 0xd600, 0xa438, 0x9102, + 0xa438, 0x889b, 0xa438, 0xee84, 0xa438, 0x6d04, 0xa438, 0xd600, + 0xa438, 0xc202, 0xa438, 0x886c, 0xa438, 0xee84, 0xa438, 0x6d03, + 0xa438, 0xd600, 0xa438, 0x9102, 0xa438, 0x889b, 0xa438, 0xee84, + 0xa438, 0x6d08, 0xa438, 0xd600, 0xa438, 0xc202, 0xa438, 0x886c, + 0xa438, 0xee84, 0xa438, 0x6d0f, 0xa438, 0xd414, 0xa438, 0x00d6, + 0xa438, 0x000d, 0xa438, 0x0288, 0xa438, 0x6cbf, 0xa438, 0x8a2c, + 0xa438, 0x0275, 0xa438, 0x3ebf, 0xa438, 0x8a2f, 0xa438, 0x0275, + 0xa438, 0x3ebf, 0xa438, 0x8a32, 0xa438, 0x0275, 0xa438, 0x3ebf, + 0xa438, 0x8a35, 0xa438, 0x0275, 0xa438, 0x3ebf, 0xa438, 0x8a38, + 0xa438, 0x0275, 0xa438, 0x3ed4, 0xa438, 0x000f, 0xa438, 0xbf71, + 0xa438, 0x5c02, 0xa438, 0x756a, 0xa438, 0xbf71, 0xa438, 0x5f02, + 0xa438, 0x7589, 0xa438, 0xef31, 0xa438, 0xe783, 0xa438, 0x9fa3, + 0xa438, 0x0ff2, 0xa438, 0xd400, 0xa438, 0x00bf, 0xa438, 0x715c, + 0xa438, 0x0275, 0xa438, 0x6abf, 0xa438, 0x8a2c, 0xa438, 0x0275, + 0xa438, 0x47bf, 0xa438, 0x8a2f, 0xa438, 0x0275, 0xa438, 0x47bf, + 0xa438, 0x8a32, 0xa438, 0x0275, 0xa438, 0x47bf, 0xa438, 0x8a35, + 0xa438, 0x0275, 0xa438, 0x47bf, 0xa438, 0x8a38, 0xa438, 0x0275, + 0xa438, 0x47ee, 0xa438, 0x846d, 0xa438, 0x0fd4, 0xa438, 0x1000, + 0xa438, 0xd600, 0xa438, 0x0d02, 0xa438, 0x886c, 0xa438, 0xfffe, + 0xa438, 0xfdef, 0xa438, 0x95fd, 0xa438, 0xfc04, 0xa438, 0xf8f9, + 0xa438, 0xef59, 0xa438, 0xf9fa, 0xa438, 0xef44, 0xa438, 0xbf73, + 0xa438, 0xbf02, 0xa438, 0x756a, 0xa438, 0xef46, 0xa438, 0xbf73, + 0xa438, 0xc202, 0xa438, 0x756a, 0xa438, 0xe184, 0xa438, 0x6dbf, + 0xa438, 0x8a29, 0xa438, 0x0275, 0xa438, 0x6ad4, 0xa438, 0x0000, + 0xa438, 0xbf8a, 0xa438, 0x2902, 0xa438, 0x756a, 0xa438, 0xfefd, + 0xa438, 0xef95, 0xa438, 0xfdfc, 0xa438, 0x04f9, 0xa438, 0xef59, + 0xa438, 0xf9fa, 0xa438, 0xef46, 0xa438, 0xbf73, 0xa438, 0xc202, + 0xa438, 0x756a, 0xa438, 0xe184, 0xa438, 0x6dbf, 0xa438, 0x8a23, + 0xa438, 0x0275, 0xa438, 0x6abf, 0xa438, 0x8a26, 0xa438, 0x0275, + 0xa438, 0x89fe, 0xa438, 0xfdef, 0xa438, 0x95fd, 0xa438, 0x04e4, + 0xa438, 0x8044, 0xa438, 0xee84, 0xa438, 0x6d0f, 0xa438, 0xd401, + 0xa438, 0x20d6, 0xa438, 0x0010, 0xa438, 0x0288, 0xa438, 0x6cee, + 0xa438, 0x8f7e, 0xa438, 0x01af, 0xa438, 0x6879, 0xa438, 0xee84, + 0xa438, 0x6900, 0xa438, 0xee84, 0xa438, 0x6a00, 0xa438, 0xee8f, + 0xa438, 0x7e00, 0xa438, 0xaf64, 0xa438, 0x8702, 0xa438, 0x6a2a, + 0xa438, 0xe384, 0xa438, 0xf302, 0xa438, 0x6a4c, 0xa438, 0xac28, + 0xa438, 0x08e0, 0xa438, 0x84f6, 0xa438, 0xf722, 0xa438, 0xe484, + 0xa438, 0xf602, 0xa438, 0x6af9, 0xa438, 0xbf73, 0xa438, 0x4d02, + 0xa438, 0x753e, 0xa438, 0xbf73, 0xa438, 0x5002, 0xa438, 0x753e, + 0xa438, 0xbf73, 0xa438, 0x5302, 0xa438, 0x753e, 0xa438, 0xbf73, + 0xa438, 0x5602, 0xa438, 0x753e, 0xa438, 0xd500, 0xa438, 0x0002, + 0xa438, 0x6b1d, 0xa438, 0xbf73, 0xa438, 0x4402, 0xa438, 0x7547, + 0xa438, 0xbf73, 0xa438, 0x4702, 0xa438, 0x7547, 0xa438, 0xbf73, + 0xa438, 0x7702, 0xa438, 0x753e, 0xa438, 0xbf73, 0xa438, 0x4a02, + 0xa438, 0x7547, 0xa438, 0xbf73, 0xa438, 0x5302, 0xa438, 0x753e, + 0xa438, 0xbf73, 0xa438, 0x5602, 0xa438, 0x7547, 0xa438, 0xaf69, + 0xa438, 0x4d02, 0xa438, 0x8948, 0xa438, 0x021e, 0xa438, 0x40af, + 0xa438, 0x1e3f, 0xa438, 0xf8fa, 0xa438, 0xef69, 0xa438, 0xe080, + 0xa438, 0x4fac, 0xa438, 0x2417, 0xa438, 0xe080, 0xa438, 0x44ad, + 0xa438, 0x2417, 0xa438, 0x0289, 0xa438, 0x74e0, 0xa438, 0x8044, + 0xa438, 0xac24, 0xa438, 0x0ebf, 0xa438, 0x8a3b, 0xa438, 0x0275, + 0xa438, 0x47ae, 0xa438, 0x0602, 0xa438, 0x8a06, 0xa438, 0x0289, + 0xa438, 0xfbef, 0xa438, 0x96fe, 0xa438, 0xfc04, 0xa438, 0xf8f9, + 0xa438, 0xfaef, 0xa438, 0x69fa, 0xa438, 0xfbd2, 0xa438, 0x00a2, + 0xa438, 0x0403, 0xa438, 0xaf89, 0xa438, 0xeabf, 0xa438, 0x6af1, + 0xa438, 0x0277, 0xa438, 0x24ef, 0xa438, 0x010d, 0xa438, 0x11d0, + 0xa438, 0x00ef, 0xa438, 0x640c, 0xa438, 0x66ef, 0xa438, 0x12bf, + 0xa438, 0x8a23, 0xa438, 0x0275, 0xa438, 0x6ad3, 0xa438, 0x01a3, + 0xa438, 0x4302, 0xa438, 0xae44, 0xa438, 0x1f00, 0xa438, 0xef13, + 0xa438, 0xbf73, 0xa438, 0xc202, 0xa438, 0x756a, 0xa438, 0xbf8a, + 0xa438, 0x3e02, 0xa438, 0x7589, 0xa438, 0xd100, 0xa438, 0x0d01, + 0xa438, 0x0c01, 0xa438, 0x1a46, 0xa438, 0xbf73, 0xa438, 0xbf02, + 0xa438, 0x756a, 0xa438, 0x1f00, 0xa438, 0xef13, 0xa438, 0xbf73, + 0xa438, 0xc202, 0xa438, 0x756a, 0xa438, 0xd101, 0xa438, 0xef02, + 0xa438, 0x10b0, 0xa438, 0x02ae, 0xa438, 0x0449, 0xa438, 0x02ae, + 0xa438, 0xf8bf, 0xa438, 0x73c5, 0xa438, 0x0275, 0xa438, 0x6abf, + 0xa438, 0x73c5, 0xa438, 0x0275, 0xa438, 0x3e13, 0xa438, 0xaeb7, + 0xa438, 0x12af, 0xa438, 0x897d, 0xa438, 0xd500, 0xa438, 0x0102, + 0xa438, 0x6b1d, 0xa438, 0x0289, 0xa438, 0xfbff, 0xa438, 0xfeef, + 0xa438, 0x96fe, 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xe080, + 0xa438, 0x44f6, 0xa438, 0x24e4, 0xa438, 0x8044, 0xa438, 0xfc04, + 0xa438, 0xf8e0, 0xa438, 0x804f, 0xa438, 0xf624, 0xa438, 0xe480, + 0xa438, 0x4ffc, 0xa438, 0x0455, 0xa438, 0xa6fe, 0xa438, 0x44a6, + 0xa438, 0xfe66, 0xa438, 0xa4b6, 0xa438, 0x55a4, 0xa438, 0xb666, + 0xa438, 0xac0e, 0xa438, 0x55ac, 0xa438, 0x0efe, 0xa438, 0xbda4, + 0xa438, 0xf0bd, 0xa438, 0x9830, 0xa438, 0xbd96, 0xa438, 0xffbd, + 0xa438, 0xdeee, 0xa438, 0xbdde, 0xa438, 0xddbd, 0xa438, 0xdebb, + 0xa438, 0xbdde, 0xa438, 0xaabd, 0xa438, 0xde44, 0xa438, 0xac00, + 0xa438, 0xf0bd, 0xa438, 0x9a00, 0xa436, 0xb818, 0xa438, 0x0fb9, + 0xa436, 0xb81a, 0xa438, 0x64c3, 0xa436, 0xb81c, 0xa438, 0x64f1, + 0xa436, 0xb81e, 0xa438, 0x6607, 0xa436, 0xb850, 0xa438, 0x6876, + 0xa436, 0xb852, 0xa438, 0x647f, 0xa436, 0xb878, 0xa438, 0x68e8, + 0xa436, 0xb884, 0xa438, 0x1e3c, 0xa436, 0xb832, 0xa438, 0x00df, + 0xB82E, 0x0000, 0xa436, 0x8023, 0xa438, 0x0000, 0xB820, 0x0000, + 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8127a_1[] = { + 0xa436, 0x8023, 0xa438, 0x6100, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0x1800, 0xa438, 0x801a, + 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0x1800, 0xa438, 0x801a, + 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0x1800, 0xa438, 0x801a, + 0xa438, 0x1800, 0xa438, 0x801a, 0xa438, 0xce00, 0xa438, 0x2941, + 0xa438, 0x8017, 0xa438, 0x2c59, 0xa438, 0x8017, 0xa438, 0x1800, + 0xa438, 0x0e11, 0xa438, 0x8aff, 0xa438, 0x1800, 0xa438, 0x0e11, + 0xa436, 0xA026, 0xa438, 0xffff, 0xa436, 0xA024, 0xa438, 0xffff, + 0xa436, 0xA022, 0xa438, 0xffff, 0xa436, 0xA020, 0xa438, 0xffff, + 0xa436, 0xA006, 0xa438, 0xffff, 0xa436, 0xA004, 0xa438, 0xffff, + 0xa436, 0xA002, 0xa438, 0xffff, 0xa436, 0xA000, 0xa438, 0x0e10, + 0xa436, 0xA008, 0xa438, 0x0100, 0xa436, 0xA016, 0xa438, 0x0000, + 0xa436, 0xA012, 0xa438, 0x0ff8, 0xa436, 0xA014, 0xa438, 0x219a, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa436, 0xA152, + 0xa438, 0x21a4, 0xa436, 0xA154, 0xa438, 0x3fff, 0xa436, 0xA156, + 0xa438, 0x3fff, 0xa436, 0xA158, 0xa438, 0x3fff, 0xa436, 0xA15A, + 0xa438, 0x3fff, 0xa436, 0xA15C, 0xa438, 0x3fff, 0xa436, 0xA15E, + 0xa438, 0x3fff, 0xa436, 0xA160, 0xa438, 0x3fff, 0xa436, 0xA150, + 0xa438, 0x0001, 0xa436, 0xA016, 0xa438, 0x0010, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8014, 0xa438, 0x1800, 0xa438, 0x801a, + 0xa438, 0x1800, 0xa438, 0x801e, 0xa438, 0x1800, 0xa438, 0x8026, + 0xa438, 0x1800, 0xa438, 0x802e, 0xa438, 0x1800, 0xa438, 0x8036, + 0xa438, 0x1800, 0xa438, 0x803a, 0xa438, 0xce01, 0xa438, 0x8208, + 0xa438, 0x1800, 0xa438, 0x0028, 0xa438, 0x1000, 0xa438, 0x02c5, + 0xa438, 0x1000, 0xa438, 0x0304, 0xa438, 0x1800, 0xa438, 0x0119, + 0xa438, 0xce01, 0xa438, 0x8208, 0xa438, 0x1800, 0xa438, 0x009e, + 0xa438, 0xd501, 0xa438, 0xce01, 0xa438, 0xa50f, 0xa438, 0x8208, + 0xa438, 0xd500, 0xa438, 0xaa0f, 0xa438, 0x1800, 0xa438, 0x015b, + 0xa438, 0xd501, 0xa438, 0xce01, 0xa438, 0xa50f, 0xa438, 0x8208, + 0xa438, 0xd500, 0xa438, 0xaa0f, 0xa438, 0x1800, 0xa438, 0x01a9, + 0xa438, 0xd501, 0xa438, 0xce01, 0xa438, 0xa50f, 0xa438, 0x8208, + 0xa438, 0xd500, 0xa438, 0xaa0f, 0xa438, 0x1800, 0xa438, 0x01f4, + 0xa438, 0x8208, 0xa438, 0xd500, 0xa438, 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0xac40, 0xa438, 0x0fbf, + 0xa438, 0x7298, 0xa438, 0x0276, 0xa438, 0xb6e5, 0xa438, 0x83e8, + 0xa438, 0xa10f, 0xa438, 0x28af, 0xa438, 0x8a95, 0xa438, 0xbf8b, + 0xa438, 0xf302, 0xa438, 0x76b6, 0xa438, 0xac28, 0xa438, 0x02ae, + 0xa438, 0x0bbf, 0xa438, 0x8bf9, 0xa438, 0x0276, 0xa438, 0xb6e5, + 0xa438, 0x83e8, 0xa438, 0xae09, 0xa438, 0xbf8b, 0xa438, 0xf602, + 0xa438, 0x76b6, 0xa438, 0xe583, 0xa438, 0xe8a1, 0xa438, 0x0303, + 0xa438, 0xaf8a, 0xa438, 0x95b7, 0xa438, 0xafe2, 0xa438, 0x83ec, + 0xa438, 0xf735, 0xa438, 0xe683, 0xa438, 0xecbf, 0xa438, 0x7295, + 0xa438, 0x0276, 0xa438, 0x6bbf, 0xa438, 0x726b, 0xa438, 0x0276, + 0xa438, 0x74bf, 0xa438, 0x726e, 0xa438, 0x0276, 0xa438, 0x74bf, + 0xa438, 0x7271, 0xa438, 0x0276, 0xa438, 0x74bf, 0xa438, 0x7274, + 0xa438, 0x0276, 0xa438, 0x74bf, 0xa438, 0x7277, 0xa438, 0x0276, + 0xa438, 0x74bf, 0xa438, 0x727a, 0xa438, 0x0276, 0xa438, 0x7402, + 0xa438, 0x8929, 0xa438, 0xd401, 0xa438, 0x28d6, 0xa438, 0x0010, + 0xa438, 0xd20f, 0xa438, 0xe684, 0xa438, 0x7602, 0xa438, 0x6671, + 0xa438, 0x021f, 0xa438, 0xbbff, 0xa438, 0xfefd, 0xa438, 0xef95, + 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xf9ef, 0xa438, 0x59f9, + 0xa438, 0xe080, 0xa438, 0x12ad, 0xa438, 0x230c, 0xa438, 0xbf72, + 0xa438, 0x9e02, 0xa438, 0x766b, 0xa438, 0xbf72, 0xa438, 0x9502, + 0xa438, 0x766b, 0xa438, 0xfdef, 0xa438, 0x95fd, 0xa438, 0xfc04, + 0xa438, 0xbf6e, 0xa438, 0x0602, 0xa438, 0x76b6, 0xa438, 0xef64, + 0xa438, 0xbf6e, 0xa438, 0x0902, 0xa438, 0x76b6, 0xa438, 0x1e64, + 0xa438, 0xbf6e, 0xa438, 0x0f02, 0xa438, 0x76b6, 0xa438, 0x1e64, + 0xa438, 0xac40, 0xa438, 0x0ebf, 0xa438, 0x7298, 0xa438, 0x0276, + 0xa438, 0xb6e5, 0xa438, 0x8478, 0xa438, 0xa10f, 0xa438, 0x26ae, + 0xa438, 0x47bf, 0xa438, 0x8bf3, 0xa438, 0x0276, 0xa438, 0xb6ac, + 0xa438, 0x2802, 0xa438, 0xae0b, 0xa438, 0xbf8b, 0xa438, 0xf902, + 0xa438, 0x76b6, 0xa438, 0xe584, 0xa438, 0x78ae, 0xa438, 0x09bf, + 0xa438, 0x8bf6, 0xa438, 0x0276, 0xa438, 0xb6e5, 0xa438, 0x8478, + 0xa438, 0xa103, 0xa438, 0x02ae, 0xa438, 0x23e0, 0xa438, 0x8474, + 0xa438, 0xe184, 0xa438, 0x75ef, 0xa438, 0x64e0, 0xa438, 0x83fc, + 0xa438, 0xe183, 0xa438, 0xfdef, 0xa438, 0x7402, 0xa438, 0x75d9, + 0xa438, 0xad50, 0xa438, 0x0ae0, 0xa438, 0x83ec, 0xa438, 0xf721, + 0xa438, 0xe483, 0xa438, 0xecae, 0xa438, 0x03af, 0xa438, 0x68e4, + 0xa438, 0xbf72, 0xa438, 0x9502, 0xa438, 0x766b, 0xa438, 0xe083, + 0xa438, 0xebad, 0xa438, 0x2170, 0xa438, 0xbf73, 0xa438, 0x7f02, + 0xa438, 0x766b, 0xa438, 0xd700, 0xa438, 0x64bf, 0xa438, 0x73c4, + 0xa438, 0x0276, 0xa438, 0xb6a4, 0xa438, 0x0000, 0xa438, 0x02ae, + 0xa438, 0x0d87, 0xa438, 0xa700, 0xa438, 0x00ef, 0xa438, 0xe183, + 0xa438, 0xecf7, 0xa438, 0x2ae5, 0xa438, 0x83ec, 0xa438, 0xbf73, + 0xa438, 0xbe02, 0xa438, 0x766b, 0xa438, 0xbf73, 0xa438, 0xb802, + 0xa438, 0x766b, 0xa438, 0xbf73, 0xa438, 0xc102, 0xa438, 0x766b, + 0xa438, 0xbf73, 0xa438, 0xbb02, 0xa438, 0x766b, 0xa438, 0xe084, + 0xa438, 0x9ee1, 0xa438, 0x849f, 0xa438, 0xbf72, 0xa438, 0x7d02, + 0xa438, 0x7697, 0xa438, 0xbf72, 0xa438, 0x8002, 0xa438, 0x7697, + 0xa438, 0xbf72, 0xa438, 0x8302, 0xa438, 0x7697, 0xa438, 0xbf72, + 0xa438, 0x8602, 0xa438, 0x7697, 0xa438, 0xbf72, 0xa438, 0x8902, + 0xa438, 0x7674, 0xa438, 0xbf72, 0xa438, 0x8c02, 0xa438, 0x7674, + 0xa438, 0xbf72, 0xa438, 0x8f02, 0xa438, 0x7674, 0xa438, 0xbf72, + 0xa438, 0x9202, 0xa438, 0x7674, 0xa438, 0xee84, 0xa438, 0x7700, + 0xa438, 0xe080, 0xa438, 0x44f6, 0xa438, 0x21e4, 0xa438, 0x8044, + 0xa438, 0xaf68, 0xa438, 0xe411, 0xa438, 0xd1a4, 0xa438, 0x10bc, + 0xa438, 0x7432, 0xa438, 0xbc74, 0xa438, 0xbbbf, 0xa438, 0x14cc, + 0xa438, 0xbfaa, 0xa438, 0x00bf, 0xa438, 0x9055, 0xa438, 0xbf06, + 0xa438, 0x10bf, 0xa438, 0xb876, 0xa438, 0xbe02, 0xa438, 0x54be, + 0xa438, 0x0232, 0xa438, 0xbe02, 0xa438, 0x10be, 0xa438, 0x0200, + 0xa436, 0x8fe7, 0xa438, 0x1200, 0xa436, 0x8fe9, 0xa438, 0x1200, + 0xa436, 0x8feb, 0xa438, 0x1200, 0xa436, 0x8fed, 0xa438, 0x1200, + 0xa436, 0x8fef, 0xa438, 0x1200, 0xa436, 0x8ff1, 0xa438, 0x1200, + 0xa436, 0x8ff3, 0xa438, 0x1200, 0xa436, 0x8ff5, 0xa438, 0x1200, + 0xa436, 0x8ff7, 0xa438, 0x1200, 0xa436, 0x8ff9, 0xa438, 0x1200, + 0xa436, 0x8ffb, 0xa438, 0x1200, 0xa436, 0x8ffd, 0xa438, 0x1200, + 0xa436, 0xb818, 0xa438, 0x6602, 0xa436, 0xb81a, 0xa438, 0x1f75, + 0xa436, 0xb81c, 0xa438, 0x67eb, 0xa436, 0xb81e, 0xa438, 0xffff, + 0xa436, 0xb850, 0xa438, 0xffff, 0xa436, 0xb852, 0xa438, 0xffff, + 0xa436, 0xb878, 0xa438, 0xffff, 0xa436, 0xb884, 0xa438, 0xffff, + 0xa436, 0xb832, 0xa438, 0x0007, 0xB82E, 0x0000, 0xa436, 0x8023, + 0xa438, 0x0000, 0xB820, 0x0000, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8127a_2[] = { + 0xb892, 0x0000, 0xB88E, 0xc07c, 0xB890, 0x0203, 0xB890, 0x0304, + 0xB890, 0x0405, 0xB890, 0x0607, 0xB890, 0x0809, 0xB890, 0x0B0D, + 0xB890, 0x0F11, 0xB890, 0x1418, 0xB890, 0x1B20, 0xB890, 0x252B, + 0xB890, 0x343E, 0xB890, 0x4854, 0xB890, 0x6203, 0xB890, 0x0304, + 0xB890, 0x0506, 0xB890, 0x080A, 0xB890, 0x0C0E, 0xB890, 0x1216, + 0xB890, 0x1B22, 0xB890, 0x2A34, 0xB890, 0x404F, 0xB890, 0x6171, + 0xB890, 0x7884, 0xB890, 0x9097, 0xB890, 0x0203, 0xB890, 0x0406, + 0xB890, 0x080B, 0xB890, 0x0E13, 0xB890, 0x1820, 0xB890, 0x2A39, + 0xB890, 0x4856, 0xB890, 0xE060, 0xB890, 0xE050, 0xB890, 0xD080, + 0xB890, 0x8070, 0xB890, 0x70A0, 0xB890, 0x1000, 0xB890, 0x60D0, + 0xB890, 0xB010, 0xB890, 0xE0B0, 0xB890, 0x80C0, 0xB890, 0xE000, + 0xB890, 0x2020, 0xB890, 0x1020, 0xB890, 0xE090, 0xB890, 0x80C0, + 0xB890, 0x3020, 0xB890, 0x00E0, 0xB890, 0x40A0, 0xB890, 0xE020, + 0xB890, 0x5060, 0xB890, 0xE0D0, 0xB890, 0xA000, 0xB890, 0x3030, + 0xB890, 0x4070, 0xB890, 0xE0E0, 0xB890, 0xD080, 0xB890, 0xA010, + 0xB890, 0xE040, 0xB890, 0x80B0, 0xB890, 0x50B0, 0xB890, 0x2090, + 0xB820, 0x0000, 0xFFFF, 0xFFFF +}; + +static void +rtl8127_real_set_phy_mcu_8127a_tc_1(struct net_device *dev) +{ + rtl8127_set_phy_mcu_ram_code(dev, + phy_mcu_ram_code_8127a_tc_1, + ARRAY_SIZE(phy_mcu_ram_code_8127a_tc_1)); +} + +static void +rtl8127_set_phy_mcu_8127a_tc(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_set_phy_mcu_patch_request(tp); + + rtl8127_real_set_phy_mcu_8127a_tc_1(dev); + + rtl8127_clear_phy_mcu_patch_request(tp); +} + +static void +rtl8127_real_set_phy_mcu_8127a_1(struct net_device *dev) +{ + rtl8127_set_phy_mcu_ram_code(dev, + phy_mcu_ram_code_8127a_1, + ARRAY_SIZE(phy_mcu_ram_code_8127a_1)); +} + +static void +rtl8127_real_set_phy_mcu_8127a_2(struct net_device *dev) +{ + rtl8127_set_phy_mcu_ram_code(dev, + phy_mcu_ram_code_8127a_2, + ARRAY_SIZE(phy_mcu_ram_code_8127a_2)); +} + +static void +rtl8127_set_phy_mcu_8127a_1(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_set_phy_mcu_patch_request(tp); + + rtl8127_real_set_phy_mcu_8127a_1(dev); + + rtl8127_clear_phy_mcu_patch_request(tp); + + rtl8127_set_phy_mcu_patch_request(tp); + + rtl8127_real_set_phy_mcu_8127a_2(dev); + + rtl8127_clear_phy_mcu_patch_request(tp); +} + +static void +rtl8127_init_hw_phy_mcu(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u8 require_disable_phy_disable_mode = FALSE; + + if (tp->NotWrRamCodeToMicroP == TRUE) + return; + + if (rtl8127_check_hw_phy_mcu_code_ver(dev)) + return; + + if (HW_SUPPORT_CHECK_PHY_DISABLE_MODE(tp) && rtl8127_is_in_phy_disable_mode(dev)) + require_disable_phy_disable_mode = TRUE; + + if (require_disable_phy_disable_mode) + rtl8127_disable_phy_disable_mode(dev); + + switch (tp->mcfg) { + case CFG_METHOD_1: + rtl8127_set_phy_mcu_8127a_tc(dev); + break; + case CFG_METHOD_2: + rtl8127_set_phy_mcu_8127a_1(dev); + break; + default: + break; + } + + if (require_disable_phy_disable_mode) + rtl8127_enable_phy_disable_mode(dev); + + rtl8127_write_hw_phy_mcu_code_ver(dev); + + rtl8127_mdio_write(tp,0x1F, 0x0000); + + tp->HwHasWrRamCodeToMicroP = TRUE; +} +#endif + +static void +rtl8127_enable_phy_aldps(struct rtl8127_private *tp) +{ + //enable aldps + //GPHY OCP 0xA430 bit[2] = 0x1 (en_aldps) + rtl8127_set_eth_phy_ocp_bit(tp, 0xA430, BIT_2); +} + +static void +rtl8127_tgphy_irq_mask_and_ack(struct rtl8127_private *tp) +{ + switch (tp->mcfg) { + case CFG_METHOD_2: + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA4D2, 0x0000); + (void)rtl8127_mdio_direct_read_phy_ocp(tp, 0xA4D4); + break; + default: + break; + } +} + +static void +rtl8127_hw_phy_config_8127a_tc_1(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xa436, 0x815E); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xa438, + 0xFF00, + 0x8600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8169); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xa438, + 0xFF00, + 0x8600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8174); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xa438, + 0xFF00, + 0xA100); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xa436, 0x83BF); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xa438, + 0xFF00, + 0x5A00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xa436, 0x83C5); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xa438, + 0xFF00, + 0x5A00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xa436, 0x83CB); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xa438, + 0xFF00, + 0x8B00); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8238); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xC000, + 0x4000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x823A); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xA000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8148); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xa438, + 0xFF00, + 0x0100); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84AD); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0C00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84B2); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0800); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84B7); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1400); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84BC); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0040); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84C0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00D6); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84BE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00A0); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84AE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0C0C); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84B0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0C0C); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xBD7A, 0xAAAA); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xBCE0, 0x6666); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x85FC); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0AAA); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x85FF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0AAA); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xAC32, BIT_3); + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xAC32, BIT_11); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xADDC, + 0x3FFF, + 0x2000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8111); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0F00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80E9); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0F00); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAEC4, + 0xFF00, + 0x4600); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAC56, + 0x0007, + 0x0005); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x825B); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0D00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8283); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0334); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8289); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xADB8, 0x0190); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAE3A, + 0x00FF, + 0x0026); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAE4A, + 0x0FF0, + 0x0150); + + rtl8127_set_eth_phy_ocp_bit(tp, 0xAEC2, BIT_12); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAE22, 0x0352); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAEC0, 0x00FA); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8188); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xF500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8203); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xF500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x827E); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xF500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81CB); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8246); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x818A); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xF500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8205); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xF500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8280); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xF500); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x83DD); + rtl8127_set_eth_phy_ocp_bit(tp, 0xB87E, BIT_9); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x840B); + rtl8127_set_eth_phy_ocp_bit(tp, 0xB87E, BIT_9); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x83BC); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_10); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x83BE); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_10); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x83C0); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x0700, + 0x0400); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x83C2); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_10); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x83C4); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_10); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x83C6); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x0700, + 0x0400); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84C2); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0xFEFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84C4); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0003); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84C6); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0116); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x84C8); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x6300); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x822A); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x4FFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81AF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x4067); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8134); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x5069); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x822C); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x1A00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81B1); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x3A00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8136); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x810E); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x9000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8114); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x9000); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB63C, BIT_9); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80B4); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xB63B); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80E4); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0700); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80E5); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x7000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80EA); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80EB); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x5000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8291); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0416); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8015); + rtl8127_set_eth_phy_ocp_bit(tp, 0xB87E, BIT_11); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x895E); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x01A0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8960); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x01A0); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x826B); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF0AF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81F0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF0AF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8175); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF0AF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x826D); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0100); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81F2); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0100); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8177); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0100); + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xAC1C, BIT_8 | BIT_7); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xAC1E, BIT_13 | BIT_12); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAD96, 0xAAFF); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD98, + 0x00FF, + 0x00AA); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAE38, + 0x3FFF, + 0x2554); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAE3A, + 0xF000, + 0xA000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8932); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0900); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x892F); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0900); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x892C); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0900); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x85B6); + rtl8127_set_eth_phy_ocp_bit(tp, 0xB87E, 0xFF00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x85B4); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFFFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8905); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB87E, 0xFF00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8853); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x2800); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x884B); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x3F00); + + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xBDE6, 0x3FFF); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xBDE8, 0x3FFF); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xBF0E, 0x0003); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8156); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1600); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80AB); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x7500); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C3); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x090D); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C6); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xC600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BF); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x5500); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8096); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x4500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x809D); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0200); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x809B); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0xE50A); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8099); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9906); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x831F); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x5000); + + + rtl8127_set_eth_phy_ocp_bit(tp, 0xB648, BIT_14); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA4E0, BIT_15); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x849A); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0004); + + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xAC1C, 0x0C00); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA42C, BIT_6); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xACBA, 0xFC00); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8122); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0xC000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8123); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0xC000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80FA); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x2000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x825B); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0xB000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80D2); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0xD000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80D3); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0xD000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80C8); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0200); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80CA); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0300); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80E2); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x2300); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80A9); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x0F00, + 0x0A00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80AA); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x5000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80AB); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0xA000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x805A); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x2000); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8106); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x40CC); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x812C); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x40CC); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8096); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x7500); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x809C); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x6300); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x859E); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x1F00); + + + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8127_enable_phy_aldps(tp); +} + +static void +rtl8127_hw_phy_config_8127a_1(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + rtl8127_tgphy_irq_mask_and_ack(tp); + + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA442, BIT_11); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8415); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x9300); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81A3); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0F00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81AE); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0F00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B9); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xB900); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x83B0); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB87E, 0x0E00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x83C5); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB87E, 0x0E00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x83DA); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB87E, 0x0E00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x83EF); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB87E, 0x0E00); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8173); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8620); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8175); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8671); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x817C); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_13); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8187); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_13); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8192); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_13); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x819D); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_13); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81A8); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_13); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B3); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_13); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81BE); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_13); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x817D); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xA600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8188); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xA600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8193); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xA600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x819E); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xA600); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81A9); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1400); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B4); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1400); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81BF); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xA600); + + + rtl8127_clear_eth_phy_ocp_bit(tp, 0xAEAA, (BIT_5 | BIT_3)); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x84F0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x201C); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x84F2); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x3117); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAEC6, 0x0000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAE20, 0xFFFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAECE, 0xFFFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAED2, 0xFFFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xAEC8, 0x0000); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xAED0, BIT_0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xADB8, 0x0150); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8197); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8231); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x82CB); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x82CD); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5700); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8233); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5700); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8199); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x5700); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x815A); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0150); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81F4); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0150); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x828E); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0150); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81B1); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x824B); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x82E5); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x84F7); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x2800); + rtl8127_set_eth_phy_ocp_bit(tp, 0xAEC2, BIT_12); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x81B3); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xAD00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x824D); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xAD00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x82E7); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xAD00); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xAE4E, + 0x000F, + 0x0001); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x82CE); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xF000, + 0x4000); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x84AC); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x84AE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x84B0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF818); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x84B2); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x6000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FFC); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x6008); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FFE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF450); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8015); + rtl8127_set_eth_phy_ocp_bit(tp, 0xB87E, BIT_9); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8016); + rtl8127_set_eth_phy_ocp_bit(tp, 0xB87E, BIT_11); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FE6); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0800); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FE4); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2114); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8647); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xA7B1); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8649); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xBBCA); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x864B); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0xDC00); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8154); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xC000, + 0x4000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8158); + rtl8127_clear_eth_phy_ocp_bit(tp, 0xB87E, 0xC000); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x826C); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFFFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x826E); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFFFF); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8872); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0E00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8012); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_11); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8012); + rtl8127_set_eth_phy_ocp_bit(tp, 0xA438, BIT_14); + rtl8127_set_eth_phy_ocp_bit(tp, 0xB576, BIT_0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x834A); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0700); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8217); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0x3F00, + 0x2A00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B1); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0B00); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FED); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x4E00); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8370); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8671); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8372); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86C8); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8401); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86C8); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8403); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86DA); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8406); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8408); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x840A); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x840C); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x840E); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8410); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8412); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8414); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8416); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x1800, + 0x1000); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x82BD); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1F40); + + + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xBFB4, + 0x07FF, + 0x0328); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xBFB6, 0x3E14); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81C4); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x003B); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0086); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00B7); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00DB); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00C3); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0078); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0047); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0023); + + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x88D7); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x01A0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x88D9); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x01A0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FFA); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x002A); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FEE); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFFDF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FF0); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFFFF); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FF2); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0A4A); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FF4); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xAA5A); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FF6); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0A4A); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FF8); + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xAA5A); + + rtl8127_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x88D5); + rtl8127_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0200); + + + rtl8127_set_eth_phy_ocp_bit(tp, 0xA430, BIT_1 | BIT_0); + + + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8127_enable_phy_aldps(tp); +} + +static void +rtl8127_hw_phy_config(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long flags; + + if (tp->resume_not_chg_speed) + return; + + tp->phy_reset_enable(dev); + + if (HW_DASH_SUPPORT_TYPE_3(tp) && tp->HwPkgDet == 0x06) + return; + + spin_lock_irqsave(&tp->phy_lock, flags); + +#ifndef ENABLE_USE_FIRMWARE_FILE + if (!tp->rtl_fw) + rtl8127_init_hw_phy_mcu(dev); +#endif + + switch (tp->mcfg) { + case CFG_METHOD_1: + rtl8127_hw_phy_config_8127a_tc_1(dev); + break; + case CFG_METHOD_2: + rtl8127_hw_phy_config_8127a_1(dev); + break; + default: + break; + } + + //legacy force mode(Chap 22) + rtl8127_clear_eth_phy_ocp_bit(tp, 0xA5B4, BIT_15); + + rtl8127_mdio_write(tp, 0x1F, 0x0000); + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + if (tp->eee.eee_enabled) + rtl8127_enable_eee(tp); + else + rtl8127_disable_eee(tp); + } + + spin_unlock_irqrestore(&tp->phy_lock, flags); +} + +static void +rtl8127_up(struct net_device *dev) +{ + rtl8127_hw_init(dev); + rtl8127_hw_reset(dev); + rtl8127_powerup_pll(dev); + rtl8127_hw_ephy_config(dev); + rtl8127_hw_phy_config(dev); + rtl8127_hw_config(dev); +} + +/* +static inline void rtl8127_delete_esd_timer(struct net_device *dev, struct timer_list *timer) +{ + del_timer_sync(timer); +} + +static inline void rtl8127_request_esd_timer(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct timer_list *timer = &tp->esd_timer; +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) + setup_timer(timer, rtl8127_esd_timer, (unsigned long)dev); +#else + timer_setup(timer, rtl8127_esd_timer, 0); +#endif + mod_timer(timer, jiffies + RTL8127_ESD_TIMEOUT); +} +*/ + +/* +static inline void rtl8127_delete_link_timer(struct net_device *dev, struct timer_list *timer) +{ + del_timer_sync(timer); +} + +static inline void rtl8127_request_link_timer(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct timer_list *timer = &tp->link_timer; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) + setup_timer(timer, rtl8127_link_timer, (unsigned long)dev); +#else + timer_setup(timer, rtl8127_link_timer, 0); +#endif + mod_timer(timer, jiffies + RTL8127_LINK_TIMEOUT); +} +*/ + +#ifdef CONFIG_NET_POLL_CONTROLLER +/* + * Polling 'interrupt' - used by things like netconsole to send skbs + * without having to re-enable interrupts. It's not called while + * the interrupt routine is executing. + */ +static void +rtl8127_netpoll(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + for (i = 0; i < tp->irq_nvecs; i++) { + struct r8127_irq *irq = &tp->irq_tbl[i]; + struct r8127_napi *r8127napi = &tp->r8127napi[i]; + + disable_irq(irq->vector); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0) + irq->handler(irq->vector, r8127napi); +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + irq->handler(irq->vector, r8127napi, NULL); +#else + irq->handler(irq->vector, r8127napi); +#endif + + enable_irq(irq->vector); + } +} +#endif //CONFIG_NET_POLL_CONTROLLER + +static void +rtl8127_setup_interrupt_mask(struct rtl8127_private *tp) +{ + int i; + + if (tp->HwCurrIsrVer == 6) { + tp->intr_mask = ISRIMR_V6_LINKCHG | ISRIMR_V6_TOK_Q0; + if (tp->num_tx_rings > 1) + tp->intr_mask |= ISRIMR_V6_TOK_Q1; + for (i = 0; i < tp->num_rx_rings; i++) + tp->intr_mask |= ISRIMR_V6_ROK_Q0 << i; + } else if (tp->HwCurrIsrVer == 5) { + tp->intr_mask = ISRIMR_V5_LINKCHG | ISRIMR_V5_TOK_Q0; + if (tp->num_tx_rings > 1) + tp->intr_mask |= ISRIMR_V5_TOK_Q1; + for (i = 0; i < tp->num_rx_rings; i++) + tp->intr_mask |= ISRIMR_V5_ROK_Q0 << i; + } else if (tp->HwCurrIsrVer == 4) { + tp->intr_mask = ISRIMR_V4_LINKCHG; + for (i = 0; i < tp->num_rx_rings; i++) + tp->intr_mask |= ISRIMR_V4_ROK_Q0 << i; + } else if (tp->HwCurrIsrVer == 3) { + tp->intr_mask = ISRIMR_V2_LINKCHG; + for (i = 0; i < max(tp->num_tx_rings, tp->num_rx_rings); i++) + tp->intr_mask |= ISRIMR_V2_ROK_Q0 << i; + } else if (tp->HwCurrIsrVer == 2) { + tp->intr_mask = ISRIMR_V2_LINKCHG | ISRIMR_TOK_Q0; + if (tp->num_tx_rings > 1) + tp->intr_mask |= ISRIMR_TOK_Q1; + + for (i = 0; i < tp->num_rx_rings; i++) + tp->intr_mask |= ISRIMR_V2_ROK_Q0 << i; + } else { + tp->intr_mask = LinkChg | RxDescUnavail | TxOK | RxOK | SWInt; + tp->timer_intr_mask = LinkChg | PCSTimeout; + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) { + if (HW_DASH_SUPPORT_TYPE_3(tp)) { + tp->timer_intr_mask |= (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); + tp->intr_mask |= (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); + } + } +#endif + } +} + +static void +rtl8127_setup_mqs_reg(struct rtl8127_private *tp) +{ + u16 hw_clo_ptr0_reg, sw_tail_ptr0_reg; + u16 reg_len; + int i; + + //tx + tp->tx_ring[0].tdsar_reg = TxDescStartAddrLow; + for (i = 1; i < tp->HwSuppNumTxQueues; i++) + tp->tx_ring[i].tdsar_reg = (u16)(TNPDS_Q1_LOW_8125 + (i - 1) * 8); + + switch (tp->HwSuppTxNoCloseVer) { + case 4: + case 5: + hw_clo_ptr0_reg = HW_CLO_PTR0_8126; + sw_tail_ptr0_reg = SW_TAIL_PTR0_8126; + reg_len = 4; + break; + case 6: + hw_clo_ptr0_reg = HW_CLO_PTR0_8125BP; + sw_tail_ptr0_reg = SW_TAIL_PTR0_8125BP; + reg_len = 8; + break; + default: + hw_clo_ptr0_reg = HW_CLO_PTR0_8125; + sw_tail_ptr0_reg = SW_TAIL_PTR0_8125; + reg_len = 4; + break; + } + + for (i = 0; i < tp->HwSuppNumTxQueues; i++) { + tp->tx_ring[i].hw_clo_ptr_reg = (u16)(hw_clo_ptr0_reg + i * reg_len); + tp->tx_ring[i].sw_tail_ptr_reg = (u16)(sw_tail_ptr0_reg + i * reg_len); + } + + //rx + tp->rx_ring[0].rdsar_reg = RxDescAddrLow; + for (i = 1; i < tp->HwSuppNumRxQueues; i++) + tp->rx_ring[i].rdsar_reg = (u16)(RDSAR_Q1_LOW_8125 + (i - 1) * 8); + + tp->isr_reg[0] = ISR0_8125; + for (i = 1; i < tp->hw_supp_irq_nvecs; i++) + tp->isr_reg[i] = (u16)(ISR1_8125 + (i - 1) * 4); + + tp->imr_reg[0] = IMR0_8125; + for (i = 1; i < tp->hw_supp_irq_nvecs; i++) + tp->imr_reg[i] = (u16)(IMR1_8125 + (i - 1) * 4); +} + +static void +rtl8127_init_software_variable(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct pci_dev *pdev = tp->pci_dev; + +#ifdef ENABLE_LIB_SUPPORT + tp->ring_lib_enabled = 1; +#endif + + switch (tp->mcfg) { + default: + tp->HwSuppDashVer = 0; + break; + } + tp->AllowAccessDashOcp = rtl8127_is_allow_access_dash_ocp(tp); + + tp->HwPkgDet = rtl8127_mac_ocp_read(tp, 0xDC00); + tp->HwPkgDet = (tp->HwPkgDet >> 3) & 0x07; + + if (HW_DASH_SUPPORT_TYPE_3(tp) && tp->HwPkgDet == 0x06) + eee_enable = 0; + + tp->HwSuppNowIsOobVer = 1; + + tp->HwPcieSNOffset = 0x168; + +#ifdef ENABLE_REALWOW_SUPPORT + rtl8127_get_realwow_hw_version(dev); +#endif //ENABLE_REALWOW_SUPPORT + + if (HW_DASH_SUPPORT_DASH(tp) && rtl8127_check_dash(tp)) + tp->DASH = 1; + else + tp->DASH = 0; + + if (tp->DASH) { + if (HW_DASH_SUPPORT_TYPE_3(tp)) { + u64 CmacMemPhysAddress; + void __iomem *cmac_ioaddr = NULL; + + //map CMAC IO space + CmacMemPhysAddress = rtl8127_csi_other_fun_read(tp, 0, 0x18); + if (!(CmacMemPhysAddress & BIT_0)) { + if (CmacMemPhysAddress & BIT_2) + CmacMemPhysAddress |= (u64)rtl8127_csi_other_fun_read(tp, 0, 0x1C) << 32; + + CmacMemPhysAddress &= 0xFFFFFFF0; + /* ioremap MMIO region */ + cmac_ioaddr = ioremap(CmacMemPhysAddress, R8127_REGS_SIZE); + } + + if (cmac_ioaddr == NULL) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "cannot remap CMAC MMIO, aborting\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + } + + if (cmac_ioaddr == NULL) + tp->DASH = 0; + else + tp->mapped_cmac_ioaddr = cmac_ioaddr; + } + + eee_enable = 0; + } + + if (HW_DASH_SUPPORT_TYPE_3(tp)) + tp->cmac_ioaddr = tp->mapped_cmac_ioaddr; + + if (aspm) { + tp->org_pci_offset_99 = rtl8127_csi_fun0_read_byte(tp, 0x99); + tp->org_pci_offset_99 &= ~(BIT_5|BIT_6); + + tp->org_pci_offset_180 = rtl8127_csi_fun0_read_byte(tp, 0x22c); + } + + pci_read_config_byte(pdev, 0x80, &tp->org_pci_offset_80); + pci_read_config_byte(pdev, 0x81, &tp->org_pci_offset_81); + + tp->use_timer_interrupt = TRUE; + + tp->HwSuppMaxPhyLinkSpeed = 10000; + + if (timer_count == 0 || tp->mcfg == CFG_METHOD_DEFAULT) + tp->use_timer_interrupt = FALSE; + + tp->ShortPacketSwChecksum = TRUE; + tp->UseSwPaddingShortPkt = TRUE; + + tp->HwSuppMagicPktVer = WAKEUP_MAGIC_PACKET_V3; + + tp->HwSuppLinkChgWakeUpVer = 3; + + tp->HwSuppD0SpeedUpVer = 2; + + tp->HwSuppCheckPhyDisableModeVer = 3; + + tp->HwSuppTxNoCloseVer = 6; + + switch (tp->HwSuppTxNoCloseVer) { + case 5: + case 6: + tp->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V4; + break; + case 4: + tp->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V3; + break; + case 3: + tp->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V2; + break; + default: + tx_no_close_enable = 0; + break; + } + + if (tp->HwSuppTxNoCloseVer > 0 && tx_no_close_enable == 1) + tp->EnableTxNoClose = TRUE; + + switch (tp->mcfg) { + case CFG_METHOD_1: + tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_1; + break; + case CFG_METHOD_2: + tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_2; + break; + default: + break; + } + + if (tp->HwIcVerUnknown) { + tp->NotWrRamCodeToMicroP = TRUE; + tp->NotWrMcuPatchCode = TRUE; + } + + tp->HwSuppMacMcuVer = 2; + + tp->MacMcuPageSize = RTL8127_MAC_MCU_PAGE_SIZE; + + tp->HwSuppNumTxQueues = 2; + tp->HwSuppNumRxQueues = 4; + + //init interrupt + tp->HwSuppIsrVer = 6; + + tp->HwCurrIsrVer = tp->HwSuppIsrVer; + if (tp->HwCurrIsrVer > 1) { + if (!(tp->features & RTL_FEATURE_MSIX) || + tp->irq_nvecs < tp->min_irq_nvecs) + tp->HwCurrIsrVer = 1; + } + + tp->num_tx_rings = 1; +#ifdef ENABLE_MULTIPLE_TX_QUEUE +#ifndef ENABLE_LIB_SUPPORT + tp->num_tx_rings = tp->HwSuppNumTxQueues; +#endif +#endif + if (tp->HwCurrIsrVer < 2 || + (tp->HwCurrIsrVer == 2 && tp->irq_nvecs < 19)) + tp->num_tx_rings = 1; + + //RSS + tp->HwSuppRssVer = 5; + tp->HwSuppIndirTblEntries = 128; + + tp->num_rx_rings = 1; +#ifdef ENABLE_RSS_SUPPORT +#ifdef ENABLE_LIB_SUPPORT + if (tp->HwSuppRssVer > 0) + tp->EnableRss = 1; +#else + if (tp->HwSuppRssVer > 0 && tp->HwCurrIsrVer > 1) { + u8 rss_queue_num = netif_get_num_default_rss_queues(); + tp->num_rx_rings = (tp->HwSuppNumRxQueues > rss_queue_num)? + rss_queue_num : tp->HwSuppNumRxQueues; + + if (!(tp->num_rx_rings >= 2 && tp->irq_nvecs >= tp->num_rx_rings)) + tp->num_rx_rings = 1; + + if (tp->num_rx_rings >= 2) + tp->EnableRss = 1; + } +#endif +#endif + + //interrupt mask + rtl8127_setup_interrupt_mask(tp); + + rtl8127_setup_mqs_reg(tp); + + rtl8127_set_ring_size(tp, NUM_RX_DESC, NUM_TX_DESC); + + tp->HwSuppPtpVer = 2; +#ifdef ENABLE_PTP_SUPPORT + if (tp->HwSuppPtpVer > 0) + tp->EnablePtp = 1; +#endif + + tp->HwSuppIntMitiVer = 6; + + tp->HwSuppTcamVer = 2; + + tp->TcamNotValidReg = TCAM_NOTVALID_ADDR_V2; + tp->TcamValidReg = TCAM_VALID_ADDR_V2; + tp->TcamMaAddrcOffset = TCAM_MAC_ADDR_V2; + tp->TcamVlanTagOffset = TCAM_VLAN_TAG_V2; + + tp->HwSuppExtendTallyCounterVer = 1; + + timer_count_v2 = (timer_count / 0x200); + + tp->HwSuppRxDescType = RX_DESC_RING_TYPE_4; + + tp->InitRxDescType = RX_DESC_RING_TYPE_1; + tp->RxDescLength = RX_DESC_LEN_TYPE_1; + switch (tp->HwSuppRxDescType) { + case RX_DESC_RING_TYPE_3: + if (tp->EnableRss) { + tp->InitRxDescType = RX_DESC_RING_TYPE_3; + tp->RxDescLength = RX_DESC_LEN_TYPE_3; + } + break; + case RX_DESC_RING_TYPE_4: + if (tp->EnableRss) { + tp->InitRxDescType = RX_DESC_RING_TYPE_4; + tp->RxDescLength = RX_DESC_LEN_TYPE_4; + } + break; + } + + tp->rtl8127_rx_config = rtl_chip_info[tp->chipset].RCR_Cfg; + if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + tp->rtl8127_rx_config |= EnableRxDescV3; + else if (tp->InitRxDescType == RX_DESC_RING_TYPE_4) + tp->rtl8127_rx_config &= ~EnableRxDescV4_1; + + tp->NicCustLedValue = RTL_R16(tp, CustomLED); + + tp->wol_opts = rtl8127_get_hw_wol(tp); + tp->wol_enabled = (tp->wol_opts) ? WOL_ENABLED : WOL_DISABLED; + + rtl8127_set_link_option(tp, autoneg_mode, speed_mode, duplex_mode, + rtl8127_fc_full); + + tp->max_jumbo_frame_size = rtl_chip_info[tp->chipset].jumbo_frame_sz; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + /* MTU range: 60 - hw-specific max */ + dev->min_mtu = ETH_MIN_MTU; + dev->max_mtu = tp->max_jumbo_frame_size; +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + + if (tp->mcfg != CFG_METHOD_DEFAULT) { + struct ethtool_keee *eee = &tp->eee; + + eee->eee_enabled = eee_enable; +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,9,0) + eee->supported = SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full | + SUPPORTED_2500baseX_Full; + eee->advertised = mmd_eee_adv_to_ethtool_adv_t(MDIO_EEE_1000T | MDIO_EEE_100TX); + eee->advertised |= SUPPORTED_2500baseX_Full; +#else + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, eee->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, eee->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, eee->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, eee->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, eee->advertised); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, eee->advertised); + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->advertised); + linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, eee->advertised); + linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, eee->advertised); +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(6,9,0) */ + eee->tx_lpi_enabled = eee_enable; + eee->tx_lpi_timer = dev->mtu + ETH_HLEN + 0x20; + } + +#ifdef ENABLE_RSS_SUPPORT + if (tp->EnableRss) + rtl8127_init_rss(tp); +#endif +} + +static void +rtl8127_release_board(struct pci_dev *pdev, + struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + void __iomem *ioaddr = tp->mmio_addr; + + rtl8127_rar_set(tp, tp->org_mac_addr); + tp->wol_enabled = WOL_DISABLED; + + if (!tp->DASH) + rtl8127_phy_power_down(dev); + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + FreeAllocatedDashShareMemory(dev); +#endif + + if (tp->mapped_cmac_ioaddr != NULL) + iounmap(tp->mapped_cmac_ioaddr); + + iounmap(ioaddr); + pci_release_regions(pdev); + pci_clear_mwi(pdev); + pci_disable_device(pdev); + free_netdev(dev); +} + +static void +rtl8127_hw_address_set(struct net_device *dev, u8 mac_addr[MAC_ADDR_LEN]) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) + eth_hw_addr_set(dev, mac_addr); +#else + memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) +} + +static int +rtl8127_get_mac_address(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + u8 mac_addr[MAC_ADDR_LEN]; + + for (i = 0; i < MAC_ADDR_LEN; i++) + mac_addr[i] = RTL_R8(tp, MAC0 + i); + + *(u32*)&mac_addr[0] = RTL_R32(tp, BACKUP_ADDR0_8125); + *(u16*)&mac_addr[4] = RTL_R16(tp, BACKUP_ADDR1_8125); + + if (!is_valid_ether_addr(mac_addr)) { + netif_err(tp, probe, dev, "Invalid ether addr %pM\n", + mac_addr); + eth_random_addr(mac_addr); + dev->addr_assign_type = NET_ADDR_RANDOM; + netif_info(tp, probe, dev, "Random ether addr %pM\n", + mac_addr); + tp->random_mac = 1; + } + + rtl8127_hw_address_set(dev, mac_addr); + rtl8127_rar_set(tp, mac_addr); + + /* keep the original MAC address */ + memcpy(tp->org_mac_addr, dev->dev_addr, MAC_ADDR_LEN); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) + memcpy(dev->perm_addr, dev->dev_addr, MAC_ADDR_LEN); +#endif + return 0; +} + +/** + * rtl8127_set_mac_address - Change the Ethernet Address of the NIC + * @dev: network interface device structure + * @p: pointer to an address structure + * + * Return 0 on success, negative on failure + **/ +static int +rtl8127_set_mac_address(struct net_device *dev, + void *p) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct sockaddr *addr = p; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + rtl8127_hw_address_set(dev, addr->sa_data); + + rtl8127_rar_set(tp, dev->dev_addr); + + return 0; +} + +/****************************************************************************** + * rtl8127_rar_set - Puts an ethernet address into a receive address register. + * + * tp - The private data structure for driver + * addr - Address to put into receive address register + *****************************************************************************/ +void +rtl8127_rar_set(struct rtl8127_private *tp, + const u8 *addr) +{ + uint32_t rar_low = 0; + uint32_t rar_high = 0; + + rar_low = ((uint32_t) addr[0] | + ((uint32_t) addr[1] << 8) | + ((uint32_t) addr[2] << 16) | + ((uint32_t) addr[3] << 24)); + + rar_high = ((uint32_t) addr[4] | + ((uint32_t) addr[5] << 8)); + + rtl8127_enable_cfg9346_write(tp); + RTL_W32(tp, MAC0, rar_low); + RTL_W32(tp, MAC4, rar_high); + + rtl8127_disable_cfg9346_write(tp); +} + +#ifdef ETHTOOL_OPS_COMPAT +static int ethtool_get_settings(struct net_device *dev, void *useraddr) +{ + struct ethtool_cmd cmd = { ETHTOOL_GSET }; + int err; + + if (!ethtool_ops->get_settings) + return -EOPNOTSUPP; + + err = ethtool_ops->get_settings(dev, &cmd); + if (err < 0) + return err; + + if (copy_to_user(useraddr, &cmd, sizeof(cmd))) + return -EFAULT; + return 0; +} + +static int ethtool_set_settings(struct net_device *dev, void *useraddr) +{ + struct ethtool_cmd cmd; + + if (!ethtool_ops->set_settings) + return -EOPNOTSUPP; + + if (copy_from_user(&cmd, useraddr, sizeof(cmd))) + return -EFAULT; + + return ethtool_ops->set_settings(dev, &cmd); +} + +static int ethtool_get_drvinfo(struct net_device *dev, void *useraddr) +{ + struct ethtool_drvinfo info; + struct ethtool_ops *ops = ethtool_ops; + + if (!ops->get_drvinfo) + return -EOPNOTSUPP; + + memset(&info, 0, sizeof(info)); + info.cmd = ETHTOOL_GDRVINFO; + ops->get_drvinfo(dev, &info); + + if (ops->self_test_count) + info.testinfo_len = ops->self_test_count(dev); + if (ops->get_stats_count) + info.n_stats = ops->get_stats_count(dev); + if (ops->get_regs_len) + info.regdump_len = ops->get_regs_len(dev); + if (ops->get_eeprom_len) + info.eedump_len = ops->get_eeprom_len(dev); + + if (copy_to_user(useraddr, &info, sizeof(info))) + return -EFAULT; + return 0; +} + +static int ethtool_get_regs(struct net_device *dev, char *useraddr) +{ + struct ethtool_regs regs; + struct ethtool_ops *ops = ethtool_ops; + void *regbuf; + int reglen, ret; + + if (!ops->get_regs || !ops->get_regs_len) + return -EOPNOTSUPP; + + if (copy_from_user(®s, useraddr, sizeof(regs))) + return -EFAULT; + + reglen = ops->get_regs_len(dev); + if (regs.len > reglen) + regs.len = reglen; + + regbuf = kmalloc(reglen, GFP_USER); + if (!regbuf) + return -ENOMEM; + + ops->get_regs(dev, ®s, regbuf); + + ret = -EFAULT; + if (copy_to_user(useraddr, ®s, sizeof(regs))) + goto out; + useraddr += offsetof(struct ethtool_regs, data); + if (copy_to_user(useraddr, regbuf, reglen)) + goto out; + ret = 0; + +out: + kfree(regbuf); + return ret; +} + +static int ethtool_get_wol(struct net_device *dev, char *useraddr) +{ + struct ethtool_wolinfo wol = { ETHTOOL_GWOL }; + + if (!ethtool_ops->get_wol) + return -EOPNOTSUPP; + + ethtool_ops->get_wol(dev, &wol); + + if (copy_to_user(useraddr, &wol, sizeof(wol))) + return -EFAULT; + return 0; +} + +static int ethtool_set_wol(struct net_device *dev, char *useraddr) +{ + struct ethtool_wolinfo wol; + + if (!ethtool_ops->set_wol) + return -EOPNOTSUPP; + + if (copy_from_user(&wol, useraddr, sizeof(wol))) + return -EFAULT; + + return ethtool_ops->set_wol(dev, &wol); +} + +static int ethtool_get_msglevel(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata = { ETHTOOL_GMSGLVL }; + + if (!ethtool_ops->get_msglevel) + return -EOPNOTSUPP; + + edata.data = ethtool_ops->get_msglevel(dev); + + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; +} + +static int ethtool_set_msglevel(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata; + + if (!ethtool_ops->set_msglevel) + return -EOPNOTSUPP; + + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + + ethtool_ops->set_msglevel(dev, edata.data); + return 0; +} + +static int ethtool_nway_reset(struct net_device *dev) +{ + if (!ethtool_ops->nway_reset) + return -EOPNOTSUPP; + + return ethtool_ops->nway_reset(dev); +} + +static int ethtool_get_link(struct net_device *dev, void *useraddr) +{ + struct ethtool_value edata = { ETHTOOL_GLINK }; + + if (!ethtool_ops->get_link) + return -EOPNOTSUPP; + + edata.data = ethtool_ops->get_link(dev); + + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; +} + +static int ethtool_get_eeprom(struct net_device *dev, void *useraddr) +{ + struct ethtool_eeprom eeprom; + struct ethtool_ops *ops = ethtool_ops; + u8 *data; + int ret; + + if (!ops->get_eeprom || !ops->get_eeprom_len) + return -EOPNOTSUPP; + + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) + return -EFAULT; + + /* Check for wrap and zero */ + if (eeprom.offset + eeprom.len <= eeprom.offset) + return -EINVAL; + + /* Check for exceeding total eeprom len */ + if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) + return -EINVAL; + + data = kmalloc(eeprom.len, GFP_USER); + if (!data) + return -ENOMEM; + + ret = -EFAULT; + if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) + goto out; + + ret = ops->get_eeprom(dev, &eeprom, data); + if (ret) + goto out; + + ret = -EFAULT; + if (copy_to_user(useraddr, &eeprom, sizeof(eeprom))) + goto out; + if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) + goto out; + ret = 0; + +out: + kfree(data); + return ret; +} + +static int ethtool_set_eeprom(struct net_device *dev, void *useraddr) +{ + struct ethtool_eeprom eeprom; + struct ethtool_ops *ops = ethtool_ops; + u8 *data; + int ret; + + if (!ops->set_eeprom || !ops->get_eeprom_len) + return -EOPNOTSUPP; + + if (copy_from_user(&eeprom, useraddr, sizeof(eeprom))) + return -EFAULT; + + /* Check for wrap and zero */ + if (eeprom.offset + eeprom.len <= eeprom.offset) + return -EINVAL; + + /* Check for exceeding total eeprom len */ + if (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev)) + return -EINVAL; + + data = kmalloc(eeprom.len, GFP_USER); + if (!data) + return -ENOMEM; + + ret = -EFAULT; + if (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len)) + goto out; + + ret = ops->set_eeprom(dev, &eeprom, data); + if (ret) + goto out; + + if (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len)) + ret = -EFAULT; + +out: + kfree(data); + return ret; +} + +static int ethtool_get_coalesce(struct net_device *dev, void *useraddr) +{ + struct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE }; + + if (!ethtool_ops->get_coalesce) + return -EOPNOTSUPP; + + ethtool_ops->get_coalesce(dev, &coalesce); + + if (copy_to_user(useraddr, &coalesce, sizeof(coalesce))) + return -EFAULT; + return 0; +} + +static int ethtool_set_coalesce(struct net_device *dev, void *useraddr) +{ + struct ethtool_coalesce coalesce; + + if (!ethtool_ops->get_coalesce) + return -EOPNOTSUPP; + + if (copy_from_user(&coalesce, useraddr, sizeof(coalesce))) + return -EFAULT; + + return ethtool_ops->set_coalesce(dev, &coalesce); +} + +static int ethtool_get_ringparam(struct net_device *dev, void *useraddr) +{ + struct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM }; + + if (!ethtool_ops->get_ringparam) + return -EOPNOTSUPP; + + ethtool_ops->get_ringparam(dev, &ringparam); + + if (copy_to_user(useraddr, &ringparam, sizeof(ringparam))) + return -EFAULT; + return 0; +} + +static int ethtool_set_ringparam(struct net_device *dev, void *useraddr) +{ + struct ethtool_ringparam ringparam; + + if (!ethtool_ops->get_ringparam) + return -EOPNOTSUPP; + + if (copy_from_user(&ringparam, useraddr, sizeof(ringparam))) + return -EFAULT; + + return ethtool_ops->set_ringparam(dev, &ringparam); +} + +static int ethtool_get_pauseparam(struct net_device *dev, void *useraddr) +{ + struct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM }; + + if (!ethtool_ops->get_pauseparam) + return -EOPNOTSUPP; + + ethtool_ops->get_pauseparam(dev, &pauseparam); + + if (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam))) + return -EFAULT; + return 0; +} + +static int ethtool_set_pauseparam(struct net_device *dev, void *useraddr) +{ + struct ethtool_pauseparam pauseparam; + + if (!ethtool_ops->get_pauseparam) + return -EOPNOTSUPP; + + if (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam))) + return -EFAULT; + + return ethtool_ops->set_pauseparam(dev, &pauseparam); +} + +static int ethtool_get_rx_csum(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata = { ETHTOOL_GRXCSUM }; + + if (!ethtool_ops->get_rx_csum) + return -EOPNOTSUPP; + + edata.data = ethtool_ops->get_rx_csum(dev); + + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; +} + +static int ethtool_set_rx_csum(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata; + + if (!ethtool_ops->set_rx_csum) + return -EOPNOTSUPP; + + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + + ethtool_ops->set_rx_csum(dev, edata.data); + return 0; +} + +static int ethtool_get_tx_csum(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata = { ETHTOOL_GTXCSUM }; + + if (!ethtool_ops->get_tx_csum) + return -EOPNOTSUPP; + + edata.data = ethtool_ops->get_tx_csum(dev); + + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; +} + +static int ethtool_set_tx_csum(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata; + + if (!ethtool_ops->set_tx_csum) + return -EOPNOTSUPP; + + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + + return ethtool_ops->set_tx_csum(dev, edata.data); +} + +static int ethtool_get_sg(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata = { ETHTOOL_GSG }; + + if (!ethtool_ops->get_sg) + return -EOPNOTSUPP; + + edata.data = ethtool_ops->get_sg(dev); + + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; +} + +static int ethtool_set_sg(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata; + + if (!ethtool_ops->set_sg) + return -EOPNOTSUPP; + + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + + return ethtool_ops->set_sg(dev, edata.data); +} + +static int ethtool_get_tso(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata = { ETHTOOL_GTSO }; + + if (!ethtool_ops->get_tso) + return -EOPNOTSUPP; + + edata.data = ethtool_ops->get_tso(dev); + + if (copy_to_user(useraddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; +} + +static int ethtool_set_tso(struct net_device *dev, char *useraddr) +{ + struct ethtool_value edata; + + if (!ethtool_ops->set_tso) + return -EOPNOTSUPP; + + if (copy_from_user(&edata, useraddr, sizeof(edata))) + return -EFAULT; + + return ethtool_ops->set_tso(dev, edata.data); +} + +static int ethtool_self_test(struct net_device *dev, char *useraddr) +{ + struct ethtool_test test; + struct ethtool_ops *ops = ethtool_ops; + u64 *data; + int ret; + + if (!ops->self_test || !ops->self_test_count) + return -EOPNOTSUPP; + + if (copy_from_user(&test, useraddr, sizeof(test))) + return -EFAULT; + + test.len = ops->self_test_count(dev); + data = kmalloc(test.len * sizeof(u64), GFP_USER); + if (!data) + return -ENOMEM; + + ops->self_test(dev, &test, data); + + ret = -EFAULT; + if (copy_to_user(useraddr, &test, sizeof(test))) + goto out; + useraddr += sizeof(test); + if (copy_to_user(useraddr, data, test.len * sizeof(u64))) + goto out; + ret = 0; + +out: + kfree(data); + return ret; +} + +static int ethtool_get_strings(struct net_device *dev, void *useraddr) +{ + struct ethtool_gstrings gstrings; + struct ethtool_ops *ops = ethtool_ops; + u8 *data; + int ret; + + if (!ops->get_strings) + return -EOPNOTSUPP; + + if (copy_from_user(&gstrings, useraddr, sizeof(gstrings))) + return -EFAULT; + + switch (gstrings.string_set) { + case ETH_SS_TEST: + if (!ops->self_test_count) + return -EOPNOTSUPP; + gstrings.len = ops->self_test_count(dev); + break; + case ETH_SS_STATS: + if (!ops->get_stats_count) + return -EOPNOTSUPP; + gstrings.len = ops->get_stats_count(dev); + break; + default: + return -EINVAL; + } + + data = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER); + if (!data) + return -ENOMEM; + + ops->get_strings(dev, gstrings.string_set, data); + + ret = -EFAULT; + if (copy_to_user(useraddr, &gstrings, sizeof(gstrings))) + goto out; + useraddr += sizeof(gstrings); + if (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN)) + goto out; + ret = 0; + +out: + kfree(data); + return ret; +} + +static int ethtool_phys_id(struct net_device *dev, void *useraddr) +{ + struct ethtool_value id; + + if (!ethtool_ops->phys_id) + return -EOPNOTSUPP; + + if (copy_from_user(&id, useraddr, sizeof(id))) + return -EFAULT; + + return ethtool_ops->phys_id(dev, id.data); +} + +static int ethtool_get_stats(struct net_device *dev, void *useraddr) +{ + struct ethtool_stats stats; + struct ethtool_ops *ops = ethtool_ops; + u64 *data; + int ret; + + if (!ops->get_ethtool_stats || !ops->get_stats_count) + return -EOPNOTSUPP; + + if (copy_from_user(&stats, useraddr, sizeof(stats))) + return -EFAULT; + + stats.n_stats = ops->get_stats_count(dev); + data = kmalloc(stats.n_stats * sizeof(u64), GFP_USER); + if (!data) + return -ENOMEM; + + ops->get_ethtool_stats(dev, &stats, data); + + ret = -EFAULT; + if (copy_to_user(useraddr, &stats, sizeof(stats))) + goto out; + useraddr += sizeof(stats); + if (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64))) + goto out; + ret = 0; + +out: + kfree(data); + return ret; +} + +static int ethtool_ioctl(struct ifreq *ifr) +{ + struct net_device *dev = __dev_get_by_name(ifr->ifr_name); + void *useraddr = (void *) ifr->ifr_data; + u32 ethcmd; + + /* + * XXX: This can be pushed down into the ethtool_* handlers that + * need it. Keep existing behaviour for the moment. + */ + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + if (!dev || !netif_device_present(dev)) + return -ENODEV; + + if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) + return -EFAULT; + + switch (ethcmd) { + case ETHTOOL_GSET: + return ethtool_get_settings(dev, useraddr); + case ETHTOOL_SSET: + return ethtool_set_settings(dev, useraddr); + case ETHTOOL_GDRVINFO: + return ethtool_get_drvinfo(dev, useraddr); + case ETHTOOL_GREGS: + return ethtool_get_regs(dev, useraddr); + case ETHTOOL_GWOL: + return ethtool_get_wol(dev, useraddr); + case ETHTOOL_SWOL: + return ethtool_set_wol(dev, useraddr); + case ETHTOOL_GMSGLVL: + return ethtool_get_msglevel(dev, useraddr); + case ETHTOOL_SMSGLVL: + return ethtool_set_msglevel(dev, useraddr); + case ETHTOOL_NWAY_RST: + return ethtool_nway_reset(dev); + case ETHTOOL_GLINK: + return ethtool_get_link(dev, useraddr); + case ETHTOOL_GEEPROM: + return ethtool_get_eeprom(dev, useraddr); + case ETHTOOL_SEEPROM: + return ethtool_set_eeprom(dev, useraddr); + case ETHTOOL_GCOALESCE: + return ethtool_get_coalesce(dev, useraddr); + case ETHTOOL_SCOALESCE: + return ethtool_set_coalesce(dev, useraddr); + case ETHTOOL_GRINGPARAM: + return ethtool_get_ringparam(dev, useraddr); + case ETHTOOL_SRINGPARAM: + return ethtool_set_ringparam(dev, useraddr); + case ETHTOOL_GPAUSEPARAM: + return ethtool_get_pauseparam(dev, useraddr); + case ETHTOOL_SPAUSEPARAM: + return ethtool_set_pauseparam(dev, useraddr); + case ETHTOOL_GRXCSUM: + return ethtool_get_rx_csum(dev, useraddr); + case ETHTOOL_SRXCSUM: + return ethtool_set_rx_csum(dev, useraddr); + case ETHTOOL_GTXCSUM: + return ethtool_get_tx_csum(dev, useraddr); + case ETHTOOL_STXCSUM: + return ethtool_set_tx_csum(dev, useraddr); + case ETHTOOL_GSG: + return ethtool_get_sg(dev, useraddr); + case ETHTOOL_SSG: + return ethtool_set_sg(dev, useraddr); + case ETHTOOL_GTSO: + return ethtool_get_tso(dev, useraddr); + case ETHTOOL_STSO: + return ethtool_set_tso(dev, useraddr); + case ETHTOOL_TEST: + return ethtool_self_test(dev, useraddr); + case ETHTOOL_GSTRINGS: + return ethtool_get_strings(dev, useraddr); + case ETHTOOL_PHYS_ID: + return ethtool_phys_id(dev, useraddr); + case ETHTOOL_GSTATS: + return ethtool_get_stats(dev, useraddr); + default: + return -EOPNOTSUPP; + } + + return -EOPNOTSUPP; +} +#endif //ETHTOOL_OPS_COMPAT + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0) +static int rtl8127_siocdevprivate(struct net_device *dev, struct ifreq *ifr, + void __user *data, int cmd) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int ret = 0; + + switch (cmd) { +#ifdef ENABLE_DASH_SUPPORT + case SIOCDEVPRIVATE_RTLDASH: + if (!netif_running(dev)) { + ret = -ENODEV; + break; + } + if (!capable(CAP_NET_ADMIN)) { + ret = -EPERM; + break; + } + + ret = rtl8127_dash_ioctl(dev, ifr); + break; +#endif + +#ifdef ENABLE_REALWOW_SUPPORT + case SIOCDEVPRIVATE_RTLREALWOW: + if (!netif_running(dev)) { + ret = -ENODEV; + break; + } + + ret = rtl8127_realwow_ioctl(dev, ifr); + break; +#endif + + case SIOCRTLTOOL: + if (!capable(CAP_NET_ADMIN)) { + ret = -EPERM; + break; + } + + ret = rtl8127_tool_ioctl(tp, ifr); + break; + + default: + ret = -EOPNOTSUPP; + } + + return ret; +} +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0) + +static int +rtl8127_do_ioctl(struct net_device *dev, + struct ifreq *ifr, + int cmd) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct mii_ioctl_data *data = if_mii(ifr); + int ret = 0; + + switch (cmd) { + case SIOCGMIIPHY: + data->phy_id = 32; /* Internal PHY */ + break; + + case SIOCGMIIREG: + rtl8127_mdio_write(tp, 0x1F, 0x0000); + data->val_out = rtl8127_mdio_read(tp, data->reg_num); + break; + + case SIOCSMIIREG: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + rtl8127_mdio_write(tp, 0x1F, 0x0000); + rtl8127_mdio_write(tp, data->reg_num, data->val_in); + break; + +#ifdef ETHTOOL_OPS_COMPAT + case SIOCETHTOOL: + ret = ethtool_ioctl(ifr); + break; +#endif + +#ifdef ENABLE_PTP_SUPPORT + case SIOCSHWTSTAMP: + case SIOCGHWTSTAMP: + if (tp->EnablePtp) + ret = rtl8127_ptp_ioctl(dev, ifr, cmd); + else + ret = -EOPNOTSUPP; + break; +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) +#ifdef ENABLE_DASH_SUPPORT + case SIOCDEVPRIVATE_RTLDASH: + if (!netif_running(dev)) { + ret = -ENODEV; + break; + } + if (!capable(CAP_NET_ADMIN)) { + ret = -EPERM; + break; + } + + ret = rtl8127_dash_ioctl(dev, ifr); + break; +#endif + +#ifdef ENABLE_REALWOW_SUPPORT + case SIOCDEVPRIVATE_RTLREALWOW: + if (!netif_running(dev)) { + ret = -ENODEV; + break; + } + + if (!capable(CAP_NET_ADMIN)) { + ret = -EPERM; + break; + } + + ret = rtl8127_realwow_ioctl(dev, ifr); + break; +#endif + + case SIOCRTLTOOL: + if (!capable(CAP_NET_ADMIN)) { + ret = -EPERM; + break; + } + + ret = rtl8127_tool_ioctl(tp, ifr); + break; +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) + + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static void +rtl8127_phy_power_up(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long flags; + + if (rtl8127_is_in_phy_disable_mode(dev)) + return; + + spin_lock_irqsave(&tp->phy_lock, flags); + + rtl8127_mdio_write(tp, 0x1F, 0x0000); + rtl8127_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); + + //wait ups resume (phy state 3) + rtl8127_wait_phy_ups_resume(dev, 3); + + spin_unlock_irqrestore(&tp->phy_lock, flags); +} + +static void +rtl8127_phy_power_down(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&tp->phy_lock, flags); + rtl8127_mdio_write(tp, 0x1F, 0x0000); + rtl8127_mdio_write(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); + spin_unlock_irqrestore(&tp->phy_lock, flags); +} + +static int __devinit +rtl8127_init_board(struct pci_dev *pdev, + struct net_device **dev_out, + void __iomem **ioaddr_out) +{ + void __iomem *ioaddr; + struct net_device *dev; + struct rtl8127_private *tp; + int rc = -ENOMEM, i, pm_cap; + + assert(ioaddr_out != NULL); + + /* dev zeroed in alloc_etherdev */ + dev = alloc_etherdev_mq(sizeof (*tp), R8127_MAX_QUEUES); + if (dev == NULL) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_drv(&debug)) + dev_err(&pdev->dev, "unable to alloc new ethernet\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + goto err_out; + } + + SET_MODULE_OWNER(dev); + SET_NETDEV_DEV(dev, &pdev->dev); + tp = netdev_priv(dev); + tp->dev = dev; + tp->pci_dev = pdev; + tp->msg_enable = netif_msg_init(debug.msg_enable, R8127_MSG_DEFAULT); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) + if (!aspm) + pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | + PCIE_LINK_STATE_CLKPM); +#endif + + /* enable device (incl. PCI PM wakeup and hotplug setup) */ + rc = pci_enable_device(pdev); + if (rc < 0) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "enable failure\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + goto err_out_free_dev; + } + + if (pci_set_mwi(pdev) < 0) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_drv(&debug)) + dev_info(&pdev->dev, "Mem-Wr-Inval unavailable.\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + } + + /* save power state before pci_enable_device overwrites it */ + pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); + if (pm_cap) { + u16 pwr_command; + + pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command); + } else { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "PowerManagement capability not found.\n"); +#else + printk("PowerManagement capability not found.\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + + } + + /* make sure PCI base addr 1 is MMIO */ + if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + rc = -ENODEV; + goto err_out_mwi; + } + /* check for weird/broken PCI region reporting */ + if (pci_resource_len(pdev, 2) < R8127_REGS_SIZE) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + rc = -ENODEV; + goto err_out_mwi; + } + + rc = pci_request_regions(pdev, MODULENAME); + if (rc < 0) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "could not request regions.\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + goto err_out_mwi; + } + + if ((sizeof(dma_addr_t) > 4) && + use_dac && + !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && + !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { + dev->features |= NETIF_F_HIGHDMA; + } else { + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (rc < 0) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "DMA configuration failed.\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + goto err_out_free_res; + } + } + + /* ioremap MMIO region */ + ioaddr = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2)); + if (ioaddr == NULL) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + rc = -EIO; + goto err_out_free_res; + } + + tp->mmio_addr = ioaddr; + + /* Identify chip attached to board */ + rtl8127_get_mac_version(tp); + + rtl8127_print_mac_version(tp); + + for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { + if (tp->mcfg == rtl_chip_info[i].mcfg) + break; + } + + if (i < 0) { + /* Unknown chip: assume array element #0, original RTL-8125 */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) + dev_printk(KERN_DEBUG, &pdev->dev, "unknown chip version, assuming %s\n", rtl_chip_info[0].name); +#else + printk("Realtek unknown chip version, assuming %s\n", rtl_chip_info[0].name); +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + i++; + } + + tp->chipset = i; + + *ioaddr_out = ioaddr; + *dev_out = dev; +out: + return rc; + +err_out_free_res: + pci_release_regions(pdev); +err_out_mwi: + pci_clear_mwi(pdev); + pci_disable_device(pdev); +err_out_free_dev: + free_netdev(dev); +err_out: + *ioaddr_out = NULL; + *dev_out = NULL; + goto out; +} + +static void +rtl8127_esd_checker(struct rtl8127_private *tp) +{ + struct net_device *dev = tp->dev; + struct pci_dev *pdev = tp->pci_dev; + u8 cmd; + u16 io_base_l; + u16 mem_base_l; + u16 mem_base_h; + u8 ilr; + u16 resv_0x1c_h; + u16 resv_0x1c_l; + u16 resv_0x20_l; + u16 resv_0x20_h; + u16 resv_0x24_l; + u16 resv_0x24_h; + u16 resv_0x2c_h; + u16 resv_0x2c_l; + u32 pci_sn_l; + u32 pci_sn_h; + + if (unlikely(tp->rtk_enable_diag)) + goto exit; + + tp->esd_flag = 0; + + pci_read_config_byte(pdev, PCI_COMMAND, &cmd); + if (cmd != tp->pci_cfg_space.cmd) { + printk(KERN_ERR "%s: cmd = 0x%02x, should be 0x%02x \n.", dev->name, cmd, tp->pci_cfg_space.cmd); + pci_write_config_byte(pdev, PCI_COMMAND, tp->pci_cfg_space.cmd); + tp->esd_flag |= BIT_0; + + pci_read_config_byte(pdev, PCI_COMMAND, &cmd); + if (cmd == 0xff) { + printk(KERN_ERR "%s: pci link is down \n.", dev->name); + goto exit; + } + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_0, &io_base_l); + if (io_base_l != tp->pci_cfg_space.io_base_l) { + printk(KERN_ERR "%s: io_base_l = 0x%04x, should be 0x%04x \n.", dev->name, io_base_l, tp->pci_cfg_space.io_base_l); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_0, tp->pci_cfg_space.io_base_l); + tp->esd_flag |= BIT_1; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_2, &mem_base_l); + if (mem_base_l != tp->pci_cfg_space.mem_base_l) { + printk(KERN_ERR "%s: mem_base_l = 0x%04x, should be 0x%04x \n.", dev->name, mem_base_l, tp->pci_cfg_space.mem_base_l); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_2, tp->pci_cfg_space.mem_base_l); + tp->esd_flag |= BIT_2; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_2 + 2, &mem_base_h); + if (mem_base_h!= tp->pci_cfg_space.mem_base_h) { + printk(KERN_ERR "%s: mem_base_h = 0x%04x, should be 0x%04x \n.", dev->name, mem_base_h, tp->pci_cfg_space.mem_base_h); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_2 + 2, tp->pci_cfg_space.mem_base_h); + tp->esd_flag |= BIT_3; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_3, &resv_0x1c_l); + if (resv_0x1c_l != tp->pci_cfg_space.resv_0x1c_l) { + printk(KERN_ERR "%s: resv_0x1c_l = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x1c_l, tp->pci_cfg_space.resv_0x1c_l); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_3, tp->pci_cfg_space.resv_0x1c_l); + tp->esd_flag |= BIT_4; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_3 + 2, &resv_0x1c_h); + if (resv_0x1c_h != tp->pci_cfg_space.resv_0x1c_h) { + printk(KERN_ERR "%s: resv_0x1c_h = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x1c_h, tp->pci_cfg_space.resv_0x1c_h); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_3 + 2, tp->pci_cfg_space.resv_0x1c_h); + tp->esd_flag |= BIT_5; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_4, &resv_0x20_l); + if (resv_0x20_l != tp->pci_cfg_space.resv_0x20_l) { + printk(KERN_ERR "%s: resv_0x20_l = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x20_l, tp->pci_cfg_space.resv_0x20_l); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_4, tp->pci_cfg_space.resv_0x20_l); + tp->esd_flag |= BIT_6; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_4 + 2, &resv_0x20_h); + if (resv_0x20_h != tp->pci_cfg_space.resv_0x20_h) { + printk(KERN_ERR "%s: resv_0x20_h = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x20_h, tp->pci_cfg_space.resv_0x20_h); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_4 + 2, tp->pci_cfg_space.resv_0x20_h); + tp->esd_flag |= BIT_7; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_5, &resv_0x24_l); + if (resv_0x24_l != tp->pci_cfg_space.resv_0x24_l) { + printk(KERN_ERR "%s: resv_0x24_l = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x24_l, tp->pci_cfg_space.resv_0x24_l); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_5, tp->pci_cfg_space.resv_0x24_l); + tp->esd_flag |= BIT_8; + } + + pci_read_config_word(pdev, PCI_BASE_ADDRESS_5 + 2, &resv_0x24_h); + if (resv_0x24_h != tp->pci_cfg_space.resv_0x24_h) { + printk(KERN_ERR "%s: resv_0x24_h = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x24_h, tp->pci_cfg_space.resv_0x24_h); + pci_write_config_word(pdev, PCI_BASE_ADDRESS_5 + 2, tp->pci_cfg_space.resv_0x24_h); + tp->esd_flag |= BIT_9; + } + + pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &ilr); + if (ilr != tp->pci_cfg_space.ilr) { + printk(KERN_ERR "%s: ilr = 0x%02x, should be 0x%02x \n.", dev->name, ilr, tp->pci_cfg_space.ilr); + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, tp->pci_cfg_space.ilr); + tp->esd_flag |= BIT_10; + } + + pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &resv_0x2c_l); + if (resv_0x2c_l != tp->pci_cfg_space.resv_0x2c_l) { + printk(KERN_ERR "%s: resv_0x2c_l = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x2c_l, tp->pci_cfg_space.resv_0x2c_l); + pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, tp->pci_cfg_space.resv_0x2c_l); + tp->esd_flag |= BIT_11; + } + + pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID + 2, &resv_0x2c_h); + if (resv_0x2c_h != tp->pci_cfg_space.resv_0x2c_h) { + printk(KERN_ERR "%s: resv_0x2c_h = 0x%04x, should be 0x%04x \n.", dev->name, resv_0x2c_h, tp->pci_cfg_space.resv_0x2c_h); + pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID + 2, tp->pci_cfg_space.resv_0x2c_h); + tp->esd_flag |= BIT_12; + } + + if (tp->HwPcieSNOffset > 0) { + pci_sn_l = rtl8127_csi_read(tp, tp->HwPcieSNOffset); + if (pci_sn_l != tp->pci_cfg_space.pci_sn_l) { + printk(KERN_ERR "%s: pci_sn_l = 0x%08x, should be 0x%08x \n.", dev->name, pci_sn_l, tp->pci_cfg_space.pci_sn_l); + rtl8127_csi_write(tp, tp->HwPcieSNOffset, tp->pci_cfg_space.pci_sn_l); + tp->esd_flag |= BIT_13; + } + + pci_sn_h = rtl8127_csi_read(tp, tp->HwPcieSNOffset + 4); + if (pci_sn_h != tp->pci_cfg_space.pci_sn_h) { + printk(KERN_ERR "%s: pci_sn_h = 0x%08x, should be 0x%08x \n.", dev->name, pci_sn_h, tp->pci_cfg_space.pci_sn_h); + rtl8127_csi_write(tp, tp->HwPcieSNOffset + 4, tp->pci_cfg_space.pci_sn_h); + tp->esd_flag |= BIT_14; + } + } + + if (tp->esd_flag != 0) { + printk(KERN_ERR "%s: esd_flag = 0x%04x\n.\n", dev->name, tp->esd_flag); + netif_carrier_off(dev); + netif_tx_disable(dev); + rtl8127_hw_reset(dev); + rtl8127_tx_clear(tp); + rtl8127_rx_clear(tp); + rtl8127_init_ring(dev); + rtl8127_up(dev); + rtl8127_enable_hw_linkchg_interrupt(tp); + rtl8127_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); + tp->esd_flag = 0; + } +exit: + return; +} +/* +static void +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) +rtl8127_esd_timer(unsigned long __opaque) +#else +rtl8127_esd_timer(struct timer_list *t) +#endif +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) + struct net_device *dev = (struct net_device *)__opaque; + struct rtl8127_private *tp = netdev_priv(dev); + struct timer_list *timer = &tp->esd_timer; +#else + struct rtl8127_private *tp = from_timer(tp, t, esd_timer); + //struct net_device *dev = tp->dev; + struct timer_list *timer = t; +#endif + rtl8127_esd_checker(tp); + + mod_timer(timer, jiffies + timeout); +} +*/ + +/* +static void +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) +rtl8127_link_timer(unsigned long __opaque) +#else +rtl8127_link_timer(struct timer_list *t) +#endif +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) + struct net_device *dev = (struct net_device *)__opaque; + struct rtl8127_private *tp = netdev_priv(dev); + struct timer_list *timer = &tp->link_timer; +#else + struct rtl8127_private *tp = from_timer(tp, t, link_timer); + struct net_device *dev = tp->dev; + struct timer_list *timer = t; +#endif + rtl8127_check_link_status(dev); + + mod_timer(timer, jiffies + RTL8127_LINK_TIMEOUT); +} +*/ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) +static int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, + int minvec, int maxvec) +{ + int nvec = maxvec; + int rc; + + if (maxvec < minvec) + return -ERANGE; + + do { + rc = pci_enable_msix(dev, entries, nvec); + if (rc < 0) { + return rc; + } else if (rc > 0) { + if (rc < minvec) + return -ENOSPC; + nvec = rc; + } + } while (rc); + + return nvec; +} +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) */ + +static int rtl8127_enable_msix(struct rtl8127_private *tp) +{ + int i, nvecs = 0; + struct msix_entry msix_ent[R8127_MAX_MSIX_VEC]; + //struct net_device *dev = tp->dev; + //const int len = sizeof(tp->irq_tbl[0].name); + + for (i = 0; i < R8127_MAX_MSIX_VEC; i++) { + msix_ent[i].entry = i; + msix_ent[i].vector = 0; + } + + nvecs = pci_enable_msix_range(tp->pci_dev, msix_ent, + tp->min_irq_nvecs, tp->max_irq_nvecs); + if (nvecs < 0) + goto out; + + for (i = 0; i < nvecs; i++) { + struct r8127_irq *irq = &tp->irq_tbl[i]; + irq->vector = msix_ent[i].vector; + //snprintf(irq->name, len, "%s-%d", dev->name, i); + //irq->handler = rtl8127_interrupt_msix; + } + +out: + return nvecs; +} + +/* Cfg9346_Unlock assumed. */ +static int rtl8127_try_msi(struct rtl8127_private *tp) +{ + struct pci_dev *pdev = tp->pci_dev; + unsigned int hw_supp_irq_nvecs; + unsigned msi = 0; + int nvecs = 1; + + hw_supp_irq_nvecs = R8127_MAX_MSIX_VEC_8125B; + tp->hw_supp_irq_nvecs = clamp_val(hw_supp_irq_nvecs, 1, + R8127_MAX_MSIX_VEC); + + tp->max_irq_nvecs = tp->hw_supp_irq_nvecs; + tp->min_irq_nvecs = R8127_MIN_MSIX_VEC_8127; +#ifdef DISABLE_MULTI_MSIX_VECTOR + tp->max_irq_nvecs = 1; +#endif + +#if defined(RTL_USE_NEW_INTR_API) + if ((nvecs = pci_alloc_irq_vectors(pdev, tp->min_irq_nvecs, tp->max_irq_nvecs, PCI_IRQ_MSIX)) > 0) + msi |= RTL_FEATURE_MSIX; + else if ((nvecs = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES)) > 0 && + pci_dev_msi_enabled(pdev)) + msi |= RTL_FEATURE_MSI; +#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) + if ((nvecs = rtl8127_enable_msix(tp)) > 0) + msi |= RTL_FEATURE_MSIX; + else if (!pci_enable_msi(pdev)) + msi |= RTL_FEATURE_MSI; +#endif + if (!(msi & (RTL_FEATURE_MSI | RTL_FEATURE_MSIX))) + dev_info(&pdev->dev, "no MSI/MSI-X. Back to INTx.\n"); + + if (!(msi & RTL_FEATURE_MSIX) || nvecs < 1) + nvecs = 1; + + tp->irq_nvecs = nvecs; + + tp->features |= msi; + + return nvecs; +} + +static void rtl8127_disable_msi(struct pci_dev *pdev, struct rtl8127_private *tp) +{ +#if defined(RTL_USE_NEW_INTR_API) + if (tp->features & (RTL_FEATURE_MSI | RTL_FEATURE_MSIX)) + pci_free_irq_vectors(pdev); +#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) + if (tp->features & (RTL_FEATURE_MSIX)) + pci_disable_msix(pdev); + else if (tp->features & (RTL_FEATURE_MSI)) + pci_disable_msi(pdev); +#endif + tp->features &= ~(RTL_FEATURE_MSI | RTL_FEATURE_MSIX); +} + +static int rtl8127_get_irq(struct pci_dev *pdev) +{ +#if defined(RTL_USE_NEW_INTR_API) + return pci_irq_vector(pdev, 0); +#else + return pdev->irq; +#endif +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,11,0) +static void +rtl8127_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct rtl8127_counters *counters = tp->tally_vaddr; + dma_addr_t paddr = tp->tally_paddr; + + if (!counters) + return; + + netdev_stats_to_stats64(stats, &dev->stats); + dev_fetch_sw_netstats(stats, dev->tstats); + + /* + * Fetch additional counter values missing in stats collected by driver + * from tally counters. + */ + rtl8127_dump_tally_counter(tp, paddr); + + stats->tx_errors = le64_to_cpu(counters->tx_errors); + stats->collisions = le32_to_cpu(counters->tx_multi_collision); + stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted); + stats->rx_missed_errors = le16_to_cpu(counters->rx_missed); +} +#else +/** + * rtl8127_get_stats - Get rtl8127 read/write statistics + * @dev: The Ethernet Device to get statistics for + * + * Get TX/RX statistics for rtl8127 + */ +static struct +net_device_stats *rtl8127_get_stats(struct net_device *dev) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) + struct rtl8127_private *tp = netdev_priv(dev); +#endif + return &RTLDEV->stats; +} +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +static const struct net_device_ops rtl8127_netdev_ops = { + .ndo_open = rtl8127_open, + .ndo_stop = rtl8127_close, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,11,0) + .ndo_get_stats64 = rtl8127_get_stats64, +#else + .ndo_get_stats = rtl8127_get_stats, +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,11,0) + .ndo_start_xmit = rtl8127_start_xmit, + .ndo_tx_timeout = rtl8127_tx_timeout, + .ndo_change_mtu = rtl8127_change_mtu, + .ndo_set_mac_address = rtl8127_set_mac_address, +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) + .ndo_do_ioctl = rtl8127_do_ioctl, +#else + .ndo_siocdevprivate = rtl8127_siocdevprivate, + .ndo_eth_ioctl = rtl8127_do_ioctl, +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0) +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) + .ndo_set_multicast_list = rtl8127_set_rx_mode, +#else + .ndo_set_rx_mode = rtl8127_set_rx_mode, +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) +#ifdef CONFIG_R8127_VLAN + .ndo_vlan_rx_register = rtl8127_vlan_rx_register, +#endif +#else + .ndo_fix_features = rtl8127_fix_features, + .ndo_set_features = rtl8127_set_features, +#endif +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = rtl8127_netpoll, +#endif +}; +#endif + + +#ifdef CONFIG_R8127_NAPI + +static int rtl8127_poll(napi_ptr napi, napi_budget budget) +{ + struct r8127_napi *r8127napi = RTL_GET_PRIV(napi, struct r8127_napi); + struct rtl8127_private *tp = r8127napi->priv; + RTL_GET_NETDEV(tp) + unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev); + unsigned int work_done = 0; + int i; + + for (i = 0; i < tp->num_tx_rings; i++) + rtl8127_tx_interrupt(&tp->tx_ring[i], budget); + + for (i = 0; i < tp->num_rx_rings; i++) + work_done += rtl8127_rx_interrupt(dev, tp, &tp->rx_ring[i], budget); + + work_done = min(work_done, work_to_do); + + RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget); + + if (work_done < work_to_do) { +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + HandleDashInterrupt(tp->dev); +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; +#else + RTL_NETIF_RX_COMPLETE(dev, napi, work_done); +#endif + /* + * 20040426: the barrier is not strictly required but the + * behavior of the irq handler could be less predictable + * without it. Btw, the lack of flush for the posted pci + * write is safe - FR + */ + smp_wmb(); + + rtl8127_switch_to_timer_interrupt(tp); + } + + return RTL_NAPI_RETURN_VALUE; +} + +static int rtl8127_poll_msix_ring(napi_ptr napi, napi_budget budget) +{ + struct r8127_napi *r8127napi = RTL_GET_PRIV(napi, struct r8127_napi); + struct rtl8127_private *tp = r8127napi->priv; + RTL_GET_NETDEV(tp) + unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev); + unsigned int work_done = 0; + const int message_id = r8127napi->index; + + if (message_id < tp->num_tx_rings) + rtl8127_tx_interrupt_with_vector(tp, message_id, budget); + + if (message_id < tp->num_rx_rings) + work_done += rtl8127_rx_interrupt(dev, tp, &tp->rx_ring[message_id], budget); + + RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget); + + if (work_done < work_to_do) { +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH && message_id == 0) + HandleDashInterrupt(tp->dev); +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; +#else + RTL_NETIF_RX_COMPLETE(dev, napi, work_done); +#endif + /* + * 20040426: the barrier is not strictly required but the + * behavior of the irq handler could be less predictable + * without it. Btw, the lack of flush for the posted pci + * write is safe - FR + */ + smp_wmb(); + + rtl8127_enable_hw_interrupt_v2(tp, message_id); + } + + return RTL_NAPI_RETURN_VALUE; +} + +static int rtl8127_poll_msix_tx(napi_ptr napi, napi_budget budget) +{ + struct r8127_napi *r8127napi = RTL_GET_PRIV(napi, struct r8127_napi); + struct rtl8127_private *tp = r8127napi->priv; + RTL_GET_NETDEV(tp) + unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev); + unsigned int work_done = 0; + const int message_id = r8127napi->index; + + //suppress unused variable + (void)(dev); + + rtl8127_tx_interrupt_with_vector(tp, message_id, budget); + + RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget); + + if (work_done < work_to_do) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; +#else + RTL_NETIF_RX_COMPLETE(dev, napi, work_done); +#endif + /* + * 20040426: the barrier is not strictly required but the + * behavior of the irq handler could be less predictable + * without it. Btw, the lack of flush for the posted pci + * write is safe - FR + */ + smp_wmb(); + + rtl8127_enable_hw_interrupt_v2(tp, message_id); + } + + return RTL_NAPI_RETURN_VALUE; +} + +static int rtl8127_poll_msix_other(napi_ptr napi, napi_budget budget) +{ + struct r8127_napi *r8127napi = RTL_GET_PRIV(napi, struct r8127_napi); + struct rtl8127_private *tp = r8127napi->priv; + RTL_GET_NETDEV(tp) + unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev); + const int message_id = r8127napi->index; + + //suppress unused variable + (void)(dev); + (void)(work_to_do); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + RTL_NETIF_RX_COMPLETE(dev, napi, work_to_do); +#else + RTL_NETIF_RX_COMPLETE(dev, napi, work_to_do); +#endif + + rtl8127_enable_hw_interrupt_v2(tp, message_id); + + return 1; +} + +static int rtl8127_poll_msix_rx(napi_ptr napi, napi_budget budget) +{ + struct r8127_napi *r8127napi = RTL_GET_PRIV(napi, struct r8127_napi); + struct rtl8127_private *tp = r8127napi->priv; + RTL_GET_NETDEV(tp) + unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev); + unsigned int work_done = 0; + const int message_id = r8127napi->index; + + if (message_id < tp->num_rx_rings) + work_done += rtl8127_rx_interrupt(dev, tp, &tp->rx_ring[message_id], budget); + + RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget); + + if (work_done < work_to_do) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; +#else + RTL_NETIF_RX_COMPLETE(dev, napi, work_done); +#endif + /* + * 20040426: the barrier is not strictly required but the + * behavior of the irq handler could be less predictable + * without it. Btw, the lack of flush for the posted pci + * write is safe - FR + */ + smp_wmb(); + + rtl8127_enable_hw_interrupt_v2(tp, message_id); + } + + return RTL_NAPI_RETURN_VALUE; +} + +void rtl8127_enable_napi(struct rtl8127_private *tp) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + int i; + + for (i = 0; i < tp->irq_nvecs; i++) + RTL_NAPI_ENABLE(tp->dev, &tp->r8127napi[i].napi); +#endif +} + +static void rtl8127_disable_napi(struct rtl8127_private *tp) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + int i; + + for (i = 0; i < tp->irq_nvecs; i++) + RTL_NAPI_DISABLE(tp->dev, &tp->r8127napi[i].napi); +#endif +} + +static void rtl8127_del_napi(struct rtl8127_private *tp) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + int i; + + for (i = 0; i < tp->irq_nvecs; i++) + RTL_NAPI_DEL((&tp->r8127napi[i])); +#endif +} +#endif //CONFIG_R8127_NAPI + +static void rtl8127_init_napi(struct rtl8127_private *tp) +{ + int i; + + for (i=0; iirq_nvecs; i++) { + struct r8127_napi *r8127napi = &tp->r8127napi[i]; +#ifdef CONFIG_R8127_NAPI + int (*poll)(struct napi_struct *, int); + + poll = rtl8127_poll; + if (tp->features & RTL_FEATURE_MSIX) { + switch (tp->HwCurrIsrVer) { + case 6: + if (i < R8127_MAX_RX_QUEUES_VEC_V4) + poll = rtl8127_poll_msix_rx; + else if (i == 8 || i == 9) + poll = rtl8127_poll_msix_tx; + else + poll = rtl8127_poll_msix_other; + break; + case 5: + if (i < R8127_MAX_RX_QUEUES_VEC_V3) + poll = rtl8127_poll_msix_rx; + else if (i == 16 || i == 17) + poll = rtl8127_poll_msix_tx; + else + poll = rtl8127_poll_msix_other; + break; + case 2: + if (i < R8127_MAX_RX_QUEUES_VEC_V3) + poll = rtl8127_poll_msix_rx; + else if (i == 16 || i == 18) + poll = rtl8127_poll_msix_tx; + else + poll = rtl8127_poll_msix_other; + break; + case 3: + case 4: + if (i < R8127_MAX_RX_QUEUES_VEC_V3) + poll = rtl8127_poll_msix_ring; + else + poll = rtl8127_poll_msix_other; + break; + } + } + + RTL_NAPI_CONFIG(tp->dev, r8127napi, poll, R8127_NAPI_WEIGHT); +#endif + + r8127napi->priv = tp; + r8127napi->index = i; + } +} + +static int +rtl8127_set_real_num_queue(struct rtl8127_private *tp) +{ + int retval = 0; + + retval = netif_set_real_num_tx_queues(tp->dev, tp->num_tx_rings); + if (retval < 0) + goto exit; + + retval = netif_set_real_num_rx_queues(tp->dev, tp->num_rx_rings); + if (retval < 0) + goto exit; + +exit: + return retval; +} + +static int __devinit +rtl8127_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct net_device *dev = NULL; + struct rtl8127_private *tp; + void __iomem *ioaddr = NULL; + static int board_idx = -1; + + int rc; + + assert(pdev != NULL); + assert(ent != NULL); + + board_idx++; + + if (netif_msg_drv(&debug)) + printk(KERN_INFO "%s Ethernet controller driver %s loaded\n", + MODULENAME, RTL8127_VERSION); + + rc = rtl8127_init_board(pdev, &dev, &ioaddr); + if (rc) + goto out; + + tp = netdev_priv(dev); + assert(ioaddr != NULL); + + spin_lock_init(&tp->phy_lock); + + tp->set_speed = rtl8127_set_speed_xmii; + tp->get_settings = rtl8127_gset_xmii; + tp->phy_reset_enable = rtl8127_xmii_reset_enable; + tp->phy_reset_pending = rtl8127_xmii_reset_pending; + tp->link_ok = rtl8127_xmii_link_ok; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,11,0) + dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, + struct pcpu_sw_netstats); + if (!dev->tstats) + goto err_out_1; +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,11,0) + + rc = rtl8127_try_msi(tp); + if (rc < 0) { + dev_err(&pdev->dev, "Can't allocate interrupt\n"); + goto err_out_1; + } + + rtl8127_init_software_variable(dev); + + RTL_NET_DEVICE_OPS(rtl8127_netdev_ops); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) + SET_ETHTOOL_OPS(dev, &rtl8127_ethtool_ops); +#endif + + dev->watchdog_timeo = RTL8127_TX_TIMEOUT; + dev->irq = rtl8127_get_irq(pdev); + dev->base_addr = (unsigned long) ioaddr; + + rtl8127_init_napi(tp); + +#ifdef CONFIG_R8127_VLAN + if (tp->mcfg != CFG_METHOD_DEFAULT) { + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) + dev->vlan_rx_kill_vid = rtl8127_vlan_rx_kill_vid; +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) + } +#endif + + /* There has been a number of reports that using SG/TSO results in + * tx timeouts. However for a lot of people SG/TSO works fine. + * Therefore disable both features by default, but allow users to + * enable them. Use at own risk! + */ + tp->cp_cmd |= RTL_R16(tp, CPlusCmd); + if (tp->mcfg != CFG_METHOD_DEFAULT) { + dev->features |= NETIF_F_IP_CSUM; +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + tp->cp_cmd |= RxChkSum; +#else + dev->features |= NETIF_F_RXCSUM; + dev->features |= NETIF_F_SG | NETIF_F_TSO; + dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | + NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; + dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | + NETIF_F_HIGHDMA; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,15,0) + dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,15,0) + dev->hw_features |= NETIF_F_RXALL; + dev->hw_features |= NETIF_F_RXFCS; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; + dev->features |= NETIF_F_IPV6_CSUM; + dev->features |= NETIF_F_TSO6; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,19,0) + netif_set_tso_max_size(dev, LSO_64K); + netif_set_tso_max_segs(dev, NIC_MAX_PHYS_BUF_COUNT_LSO2); +#else //LINUX_VERSION_CODE >= KERNEL_VERSION(5,19,0) + netif_set_gso_max_size(dev, LSO_64K); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0) + dev->gso_max_segs = NIC_MAX_PHYS_BUF_COUNT_LSO2; +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) + dev->gso_min_segs = NIC_MIN_PHYS_BUF_COUNT; +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0) +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,19,0) + +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + +#ifdef ENABLE_RSS_SUPPORT + if (tp->EnableRss) { + dev->hw_features |= NETIF_F_RXHASH; + dev->features |= NETIF_F_RXHASH; + } +#endif + } + + netdev_sw_irq_coalesce_default_on(dev); + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) + AllocateDashShareMemory(dev); +#endif + +#ifdef ENABLE_LIB_SUPPORT + BLOCKING_INIT_NOTIFIER_HEAD(&tp->lib_nh); +#endif + rtl8127_init_all_schedule_work(tp); + + rc = rtl8127_set_real_num_queue(tp); + if (rc < 0) + goto err_out; + + rtl8127_exit_oob(dev); + + rtl8127_powerup_pll(dev); + + rtl8127_hw_init(dev); + + rtl8127_hw_reset(dev); + + /* Get production from EEPROM */ + rtl8127_eeprom_type(tp); + + if (tp->eeprom_type == EEPROM_TYPE_93C46 || tp->eeprom_type == EEPROM_TYPE_93C56) + rtl8127_set_eeprom_sel_low(tp); + + rtl8127_get_mac_address(dev); + + tp->fw_name = rtl_chip_fw_infos[tp->mcfg].fw_name; + + tp->tally_vaddr = dma_alloc_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), + &tp->tally_paddr, GFP_KERNEL); + if (!tp->tally_vaddr) { + rc = -ENOMEM; + goto err_out; + } + + rtl8127_tally_counter_clear(tp); + + pci_set_drvdata(pdev, dev); + + rc = register_netdev(dev); + if (rc) + goto err_out; + + printk(KERN_INFO "%s: This product is covered by one or more of the following patents: US6,570,884, US6,115,776, and US6,327,625.\n", MODULENAME); + + rtl8127_disable_rxdvgate(dev); + + device_set_wakeup_enable(&pdev->dev, tp->wol_enabled); + + netif_carrier_off(dev); + +#ifdef ENABLE_R8127_SYSFS + rtl8127_sysfs_init(dev); +#endif /* ENABLE_R8127_SYSFS */ + + printk(KERN_INFO "%s", GPL_CLAIM); + +out: + return rc; + +err_out: + if (tp->tally_vaddr != NULL) { + dma_free_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, + tp->tally_paddr); + + tp->tally_vaddr = NULL; + } +#ifdef CONFIG_R8127_NAPI + rtl8127_del_napi(tp); +#endif + rtl8127_disable_msi(pdev, tp); + +err_out_1: + rtl8127_release_board(pdev, dev); + + goto out; +} + +static void __devexit +rtl8127_remove_one(struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct rtl8127_private *tp = netdev_priv(dev); + + assert(dev != NULL); + assert(tp != NULL); + + set_bit(R8127_FLAG_DOWN, tp->task_flags); + + rtl8127_cancel_all_schedule_work(tp); + + if (HW_DASH_SUPPORT_DASH(tp)) + rtl8127_driver_stop(tp); + + rtl8127_disable_pci_offset_180(tp); + +#ifdef ENABLE_R8127_SYSFS + rtl8127_sysfs_remove(dev); +#endif //ENABLE_R8127_SYSFS + + unregister_netdev(dev); +#ifdef CONFIG_R8127_NAPI + rtl8127_del_napi(tp); +#endif + rtl8127_disable_msi(pdev, tp); +#ifdef ENABLE_R8127_PROCFS + rtl8127_proc_remove(dev); +#endif + if (tp->tally_vaddr != NULL) { + dma_free_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, tp->tally_paddr); + tp->tally_vaddr = NULL; + } + + rtl8127_release_board(pdev, dev); + +#ifdef ENABLE_USE_FIRMWARE_FILE + rtl8127_release_firmware(tp); +#endif + + pci_set_drvdata(pdev, NULL); +} + +#ifdef ENABLE_PAGE_REUSE +static inline unsigned int rtl8127_rx_page_order(unsigned rx_buf_sz, unsigned page_size) +{ + unsigned truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + + SKB_DATA_ALIGN(rx_buf_sz + R8127_RX_ALIGN); + + return get_order(truesize * 2); +} +#endif //ENABLE_PAGE_REUSE + +static void +rtl8127_set_rxbufsize(struct rtl8127_private *tp, + struct net_device *dev) +{ + unsigned int mtu = dev->mtu; + + tp->rms = (mtu > ETH_DATA_LEN) ? + mtu + ETH_HLEN + RT_VALN_HLEN + ETH_FCS_LEN: + RX_BUF_SIZE; + tp->rx_buf_sz = tp->rms; +#ifdef ENABLE_RX_PACKET_FRAGMENT + tp->rx_buf_sz = SKB_DATA_ALIGN(RX_BUF_SIZE); +#endif //ENABLE_RX_PACKET_FRAGMENT +#ifdef ENABLE_PAGE_REUSE + tp->rx_buf_page_order = rtl8127_rx_page_order(tp->rx_buf_sz, PAGE_SIZE); + tp->rx_buf_page_size = rtl8127_rx_page_size(tp->rx_buf_page_order); +#endif //ENABLE_PAGE_REUSE +} + +static void +rtl8127_set_rms(struct rtl8127_private *tp, u16 rms) +{ + RTL_W16(tp, RxMaxSize, rms | AcceppVlanPhys); +} + +static void rtl8127_free_irq(struct rtl8127_private *tp) +{ + int i; + + for (i=0; iirq_nvecs; i++) { + struct r8127_irq *irq = &tp->irq_tbl[i]; + struct r8127_napi *r8127napi = &tp->r8127napi[i]; + + if (irq->requested) { + irq->requested = 0; +#if defined(RTL_USE_NEW_INTR_API) + pci_free_irq(tp->pci_dev, i, r8127napi); +#else + free_irq(irq->vector, r8127napi); +#endif + } + } +} + +static int rtl8127_alloc_irq(struct rtl8127_private *tp) +{ + struct net_device *dev = tp->dev; + int rc = 0; + struct r8127_irq *irq; + struct r8127_napi *r8127napi; + int i = 0; + const int len = sizeof(tp->irq_tbl[0].name); + +#if defined(RTL_USE_NEW_INTR_API) + for (i=0; iirq_nvecs; i++) { + irq = &tp->irq_tbl[i]; + if (tp->features & RTL_FEATURE_MSIX && + tp->HwCurrIsrVer > 1) + irq->handler = rtl8127_interrupt_msix; + else + irq->handler = rtl8127_interrupt; + + r8127napi = &tp->r8127napi[i]; + snprintf(irq->name, len, "%s-%d", dev->name, i); + rc = pci_request_irq(tp->pci_dev, i, irq->handler, NULL, r8127napi, + irq->name); + if (rc) + break; + + irq->vector = pci_irq_vector(tp->pci_dev, i); + irq->requested = 1; + } +#else + unsigned long irq_flags = 0; +#ifdef ENABLE_LIB_SUPPORT + irq_flags |= IRQF_NO_SUSPEND; +#endif + if (tp->features & RTL_FEATURE_MSIX && + tp->HwCurrIsrVer > 1) { + for (i=0; iirq_nvecs; i++) { + irq = &tp->irq_tbl[i]; + irq->handler = rtl8127_interrupt_msix; + r8127napi = &tp->r8127napi[i]; + snprintf(irq->name, len, "%s-%d", dev->name, i); + rc = request_irq(irq->vector, irq->handler, irq_flags, irq->name, r8127napi); + + if (rc) + break; + + irq->requested = 1; + } + } else { + irq = &tp->irq_tbl[0]; + irq->handler = rtl8127_interrupt; + r8127napi = &tp->r8127napi[0]; + snprintf(irq->name, len, "%s-0", dev->name); + if (!(tp->features & RTL_FEATURE_MSIX)) + irq->vector = dev->irq; + irq_flags |= (tp->features & (RTL_FEATURE_MSI | RTL_FEATURE_MSIX)) ? 0 : SA_SHIRQ; + rc = request_irq(irq->vector, irq->handler, irq_flags, irq->name, r8127napi); + + if (rc == 0) + irq->requested = 1; + } +#endif + if (rc) + rtl8127_free_irq(tp); + + return rc; +} + +static int rtl8127_alloc_tx_desc(struct rtl8127_private *tp) +{ + struct rtl8127_tx_ring *ring; + struct pci_dev *pdev = tp->pci_dev; + int i; + + for (i = 0; i < tp->num_tx_rings; i++) { + ring = &tp->tx_ring[i]; + ring->TxDescAllocSize = (ring->num_tx_desc + 1) * sizeof(struct TxDesc); + ring->TxDescArray = dma_alloc_coherent(&pdev->dev, + ring->TxDescAllocSize, + &ring->TxPhyAddr, + GFP_KERNEL); + + if (!ring->TxDescArray) + return -1; + } + + return 0; +} + +static int rtl8127_alloc_rx_desc(struct rtl8127_private *tp) +{ + struct rtl8127_rx_ring *ring; + struct pci_dev *pdev = tp->pci_dev; + int i; + + for (i = 0; i < tp->num_rx_rings; i++) { + ring = &tp->rx_ring[i]; + ring->RxDescAllocSize = (ring->num_rx_desc + 1) * tp->RxDescLength; + ring->RxDescArray = dma_alloc_coherent(&pdev->dev, + ring->RxDescAllocSize, + &ring->RxPhyAddr, + GFP_KERNEL); + + if (!ring->RxDescArray) + return -1; + } + + return 0; +} + +static void rtl8127_free_tx_desc(struct rtl8127_private *tp) +{ + struct rtl8127_tx_ring *ring; + struct pci_dev *pdev = tp->pci_dev; + int i; + + for (i = 0; i < tp->num_tx_rings; i++) { + ring = &tp->tx_ring[i]; + if (ring->TxDescArray) { + dma_free_coherent(&pdev->dev, + ring->TxDescAllocSize, + ring->TxDescArray, + ring->TxPhyAddr); + ring->TxDescArray = NULL; + } + } +} + +static void rtl8127_free_rx_desc(struct rtl8127_private *tp) +{ + struct rtl8127_rx_ring *ring; + struct pci_dev *pdev = tp->pci_dev; + int i; + + for (i = 0; i < tp->num_rx_rings; i++) { + ring = &tp->rx_ring[i]; + if (ring->RxDescArray) { + dma_free_coherent(&pdev->dev, + ring->RxDescAllocSize, + ring->RxDescArray, + ring->RxPhyAddr); + ring->RxDescArray = NULL; + } + } +} + +static void rtl8127_free_alloc_resources(struct rtl8127_private *tp) +{ + rtl8127_free_rx_desc(tp); + + rtl8127_free_tx_desc(tp); +} + +#ifdef ENABLE_USE_FIRMWARE_FILE +static void rtl8127_request_firmware(struct rtl8127_private *tp) +{ + struct rtl8127_fw *rtl_fw; + + /* firmware loaded already or no firmware available */ + if (tp->rtl_fw || !tp->fw_name) + return; + + rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); + if (!rtl_fw) + return; + + rtl_fw->phy_write = rtl8127_mdio_write; + rtl_fw->phy_read = rtl8127_mdio_read; + rtl_fw->mac_mcu_write = mac_mcu_write; + rtl_fw->mac_mcu_read = mac_mcu_read; + rtl_fw->fw_name = tp->fw_name; + rtl_fw->dev = tp_to_dev(tp); + + if (rtl8127_fw_request_firmware(rtl_fw)) + kfree(rtl_fw); + else + tp->rtl_fw = rtl_fw; +} +#endif + +int rtl8127_open(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int retval; + + retval = -ENOMEM; + +#ifdef ENABLE_R8127_PROCFS + rtl8127_proc_init(dev); +#endif + rtl8127_set_rxbufsize(tp, dev); + /* + * Rx and Tx descriptors needs 256 bytes alignment. + * pci_alloc_consistent provides more. + */ + if (rtl8127_alloc_tx_desc(tp) < 0 || rtl8127_alloc_rx_desc(tp) < 0) + goto err_free_all_allocated_mem; + + retval = rtl8127_init_ring(dev); + if (retval < 0) + goto err_free_all_allocated_mem; + + retval = rtl8127_alloc_irq(tp); + if (retval < 0) + goto err_free_all_allocated_mem; + + if (netif_msg_probe(tp)) { + printk(KERN_INFO "%s: 0x%lx, " + "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " + "IRQ %d\n", + dev->name, + dev->base_addr, + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5], dev->irq); + } + +#ifdef ENABLE_USE_FIRMWARE_FILE + rtl8127_request_firmware(tp); +#endif + pci_set_master(tp->pci_dev); + +#ifdef CONFIG_R8127_NAPI + rtl8127_enable_napi(tp); +#endif + + rtl8127_exit_oob(dev); + + rtl8127_up(dev); + +#ifdef ENABLE_PTP_SUPPORT + if (tp->EnablePtp) + rtl8127_ptp_init(tp); +#endif + clear_bit(R8127_FLAG_DOWN, tp->task_flags); + + if (tp->resume_not_chg_speed) + _rtl8127_check_link_status(dev, R8127_LINK_STATE_UNKNOWN); + else + rtl8127_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); + + if (tp->esd_flag == 0) { + //rtl8127_request_esd_timer(dev); + + rtl8127_schedule_esd_work(tp); + } + + //rtl8127_request_link_timer(dev); + + rtl8127_enable_hw_linkchg_interrupt(tp); + +out: + + return retval; + +err_free_all_allocated_mem: + rtl8127_free_alloc_resources(tp); + + goto out; +} + +static void +_rtl8127_set_l1_l0s_entry_latency(struct rtl8127_private *tp, u8 setting) +{ + u32 csi_tmp; + u32 temp; + + temp = setting & 0x3f; + temp <<= 24; + /*set PCI configuration space offset 0x70F to setting*/ + /*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/ + + csi_tmp = rtl8127_csi_read(tp, 0x70c) & 0xc0ffffff; + rtl8127_csi_write(tp, 0x70c, csi_tmp | temp); +} + +static void +rtl8127_set_l1_l0s_entry_latency(struct rtl8127_private *tp) +{ + _rtl8127_set_l1_l0s_entry_latency(tp, 0x27); +} + +static void +_rtl8127_set_mrrs(struct rtl8127_private *tp, u8 setting) +{ + //Set PCI configuration space offset 0x79 to setting + + struct pci_dev *pdev = tp->pci_dev; + u8 device_control; + + pci_read_config_byte(pdev, 0x79, &device_control); + device_control &= ~0x70; + device_control |= setting; + pci_write_config_byte(pdev, 0x79, device_control); +} + +static void +rtl8127_set_mrrs(struct rtl8127_private *tp) +{ + if (hwoptimize & HW_PATCH_SOC_LAN) + return; + + _rtl8127_set_mrrs(tp, 0x40); +} + +static void +rtl8127_disable_l1_timeout(struct rtl8127_private *tp) +{ + rtl8127_csi_write(tp, 0x890, rtl8127_csi_read(tp, 0x890) & ~BIT(0)); +} + +void +rtl8127_hw_set_rx_packet_filter(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + u32 mc_filter[2]; /* Multicast hash filter */ + int rx_mode; + u32 tmp = 0; + + if (dev->flags & IFF_PROMISC) { + /* Unconditionally log net taps. */ + if (netif_msg_link(tp)) + printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", + dev->name); + + rx_mode = + AcceptBroadcast | AcceptMulticast | AcceptMyPhys | + AcceptAllPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + } else if (dev->flags & IFF_ALLMULTI) { + /* accept all multicasts. */ + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + } else { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) + struct dev_mc_list *mclist; + unsigned int i; + + rx_mode = AcceptBroadcast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0; + for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; + i++, mclist = mclist->next) { + int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; + mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); + rx_mode |= AcceptMulticast; + } +#else + struct netdev_hw_addr *ha; + + rx_mode = AcceptBroadcast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0; + netdev_for_each_mc_addr(ha, dev) { + int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; + mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); + rx_mode |= AcceptMulticast; + } +#endif + } + + if (dev->features & NETIF_F_RXALL) + rx_mode |= (AcceptErr | AcceptRunt); + + tmp = mc_filter[0]; + mc_filter[0] = swab32(mc_filter[1]); + mc_filter[1] = swab32(tmp); + + tmp = tp->rtl8127_rx_config | rx_mode | (RTL_R32(tp, RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); + + RTL_W32(tp, RxConfig, tmp); + RTL_W32(tp, MAR0 + 0, mc_filter[0]); + RTL_W32(tp, MAR0 + 4, mc_filter[1]); +} + +static void +rtl8127_set_rx_mode(struct net_device *dev) +{ + rtl8127_hw_set_rx_packet_filter(dev); +} + +void +rtl8127_set_rx_q_num(struct rtl8127_private *tp, + unsigned int num_rx_queues) +{ + u16 q_ctrl; + u16 rx_q_num; + + rx_q_num = (u16)ilog2(num_rx_queues); + rx_q_num &= (BIT_0 | BIT_1 | BIT_2); + rx_q_num <<= 2; + q_ctrl = RTL_R16(tp, Q_NUM_CTRL_8125); + q_ctrl &= ~(BIT_2 | BIT_3 | BIT_4); + q_ctrl |= rx_q_num; + RTL_W16(tp, Q_NUM_CTRL_8125, q_ctrl); +} + +void +rtl8127_set_tx_q_num(struct rtl8127_private *tp, + unsigned int num_tx_queues) +{ + u16 mac_ocp_data; + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xE63E); + mac_ocp_data &= ~(BIT_11 | BIT_10); + mac_ocp_data |= ((ilog2(num_tx_queues) & 0x03) << 10); + rtl8127_mac_ocp_write(tp, 0xE63E, mac_ocp_data); +} + +void +rtl8127_enable_mcu(struct rtl8127_private *tp, bool enable) +{ + if (FALSE == HW_SUPPORT_MAC_MCU(tp)) + return; + + if (enable) + rtl8127_set_mac_ocp_bit(tp, 0xC0B4, BIT_0); + else + rtl8127_clear_mac_ocp_bit(tp, 0xC0B4, BIT_0); +} + +static void +rtl8127_clear_tcam_entries(struct rtl8127_private *tp) +{ + if (FALSE == HW_SUPPORT_TCAM(tp)) + return; + + rtl8127_set_mac_ocp_bit(tp, 0xEB54, BIT_0); + fsleep(1); + rtl8127_clear_mac_ocp_bit(tp, 0xEB54, BIT_0); +} + +static u8 +rtl8127_get_l1off_cap_bits(struct rtl8127_private *tp) +{ + u8 l1offCapBits = 0; + + l1offCapBits = (BIT_0 | BIT_1); + l1offCapBits |= (BIT_2 | BIT_3); + + return l1offCapBits; +} + +void +rtl8127_hw_config(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + struct pci_dev *pdev = tp->pci_dev; + u16 mac_ocp_data; + + rtl8127_disable_rx_packet_filter(tp); + + rtl8127_hw_reset(dev); + + rtl8127_enable_cfg9346_write(tp); + rtl8127_enable_force_clkreq(tp, 0); + rtl8127_enable_aspm_clkreq_lock(tp, 0); + + rtl8127_set_eee_lpi_timer(tp); + + //keep magic packet only + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xC0B6); + mac_ocp_data &= BIT_0; + rtl8127_mac_ocp_write(tp, 0xC0B6, mac_ocp_data); + + rtl8127_tally_counter_addr_fill(tp); + + rtl8127_enable_extend_tally_couter(tp); + + rtl8127_desc_addr_fill(tp); + + /* Set DMA burst size and Interframe Gap Time */ + RTL_W32(tp, TxConfig, (TX_DMA_BURST_unlimited << TxDMAShift) | + (InterFrameGap << TxInterFrameGapShift)); + + if (tp->EnableTxNoClose) + RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) | BIT_6)); + + if (enable_double_vlan) + rtl8127_enable_double_vlan(tp); + else + rtl8127_disable_double_vlan(tp); + + rtl8127_set_l1_l0s_entry_latency(tp); + + rtl8127_set_mrrs(tp); + + rtl8127_disable_l1_timeout(tp); + +#ifdef ENABLE_RSS_SUPPORT + rtl8127_config_rss(tp); +#else + RTL_W32(tp, RSS_CTRL_8125, 0x00); +#endif + rtl8127_set_rx_q_num(tp, rtl8127_tot_rx_rings(tp)); + + RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); + + rtl8127_mac_ocp_write(tp, 0xC140, 0xFFFF); + rtl8127_mac_ocp_write(tp, 0xC142, 0xFFFF); + + //new tx desc format + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xEB58); + mac_ocp_data &= ~(BIT_0 | BIT_1); + mac_ocp_data |= (BIT_0); + rtl8127_mac_ocp_write(tp, 0xEB58, mac_ocp_data); + + if (tp->EnableTxNoClose) + RTL_W8(tp, 0x20E4, RTL_R8(tp, 0x20E4) | BIT_2); + else + RTL_W8(tp, 0x20E4, RTL_R8(tp, 0x20E4) & ~BIT_2); + + if (tp->HwSuppRxDescType == RX_DESC_RING_TYPE_4) { + if (tp->InitRxDescType == RX_DESC_RING_TYPE_4) + RTL_W8(tp, 0xd8, RTL_R8(tp, 0xd8) | + EnableRxDescV4_0); + else + RTL_W8(tp, 0xd8, RTL_R8(tp, 0xd8) & + ~EnableRxDescV4_0); + } + + if (tp->mcfg == CFG_METHOD_2) { + rtl8127_clear_mac_ocp_bit(tp, 0xE00C, BIT_12); + + rtl8127_clear_mac_ocp_bit(tp, 0xC0C2, BIT_6); + } + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xE614); + mac_ocp_data &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8); + mac_ocp_data |= (15 << 8); + rtl8127_mac_ocp_write(tp, 0xE614, mac_ocp_data); + + rtl8127_set_tx_q_num(tp, rtl8127_tot_tx_rings(tp)); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xE63E); + mac_ocp_data &= ~(BIT_5 | BIT_4); + mac_ocp_data |= ((0x02 & 0x03) << 4); + rtl8127_mac_ocp_write(tp, 0xE63E, mac_ocp_data); + + rtl8127_enable_mcu(tp, 0); + rtl8127_enable_mcu(tp, 1); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xC0B4); + mac_ocp_data |= (BIT_3 | BIT_2); + rtl8127_mac_ocp_write(tp, 0xC0B4, mac_ocp_data); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xEB6A); + mac_ocp_data &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); + mac_ocp_data |= (BIT_5 | BIT_4 | BIT_1 | BIT_0); + rtl8127_mac_ocp_write(tp, 0xEB6A, mac_ocp_data); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xEB50); + mac_ocp_data &= ~(BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5); + mac_ocp_data |= (BIT_6); + rtl8127_mac_ocp_write(tp, 0xEB50, mac_ocp_data); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xE056); + mac_ocp_data &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4); + //mac_ocp_data |= (BIT_4 | BIT_5); + rtl8127_mac_ocp_write(tp, 0xE056, mac_ocp_data); + + RTL_W8(tp, TDFNR, 0x10); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xE040); + mac_ocp_data &= ~(BIT_12); + rtl8127_mac_ocp_write(tp, 0xE040, mac_ocp_data); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xEA1C); + mac_ocp_data &= ~(BIT_1 | BIT_0); + mac_ocp_data |= (BIT_0); + rtl8127_mac_ocp_write(tp, 0xEA1C, mac_ocp_data); + + rtl8127_mac_ocp_write(tp, 0xE0C0, 0x4000); + + rtl8127_set_mac_ocp_bit(tp, 0xE052, (BIT_6 | BIT_5)); + rtl8127_clear_mac_ocp_bit(tp, 0xE052, BIT_3 | BIT_7); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xD430); + mac_ocp_data &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); + mac_ocp_data |= 0x45F; + rtl8127_mac_ocp_write(tp, 0xD430, mac_ocp_data); + + //rtl8127_mac_ocp_write(tp, 0xE0C0, 0x4F87); + if (!tp->DASH) + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6 | BIT_7); + else + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~(BIT_6 | BIT_7)); + + rtl8127_disable_eee_plus(tp); + + mac_ocp_data = rtl8127_mac_ocp_read(tp, 0xEA1C); + mac_ocp_data &= ~(BIT_2); + mac_ocp_data &= ~(BIT_9 | BIT_8); + rtl8127_mac_ocp_write(tp, 0xEA1C, mac_ocp_data); + + rtl8127_clear_tcam_entries(tp); + + RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~(BIT_4 | BIT_5)); + + rtl8127_clear_set_mac_ocp_bit(tp, 0xD40C, 0xE038, 0x8020); + + /* csum offload command for RTL8125 */ + tp->tx_tcp_csum_cmd = TxTCPCS_C; + tp->tx_udp_csum_cmd = TxUDPCS_C; + tp->tx_ip_csum_cmd = TxIPCS_C; + tp->tx_ipv6_csum_cmd = TxIPV6F_C; + + /* config interrupt type for RTL8125B */ + if (tp->HwSuppIsrVer > 1) + rtl8127_hw_set_interrupt_type(tp, tp->HwCurrIsrVer); + + //other hw parameters + rtl8127_hw_clear_timer_int(dev); + + rtl8127_hw_clear_int_miti(dev); + + if (tp->use_timer_interrupt && + (tp->HwCurrIsrVer > 1) && + (tp->HwSuppIntMitiVer > 3) && + (tp->features & RTL_FEATURE_MSIX)) { + int i; + for (i = 0; i < tp->irq_nvecs; i++) + rtl8127_hw_set_timer_int(tp, i, timer_count_v2); + } + + rtl8127_enable_exit_l1_mask(tp); + + rtl8127_mac_ocp_write(tp, 0xE098, 0xC302); + + if (aspm && (tp->org_pci_offset_99 & (BIT_2 | BIT_5 | BIT_6))) + rtl8127_init_pci_offset_99(tp); + else + rtl8127_disable_pci_offset_99(tp); + + if (aspm && (tp->org_pci_offset_180 & rtl8127_get_l1off_cap_bits(tp))) + rtl8127_init_pci_offset_180(tp); + else + rtl8127_disable_pci_offset_180(tp); + + tp->cp_cmd &= ~(EnableBist | Macdbgo_oe | Force_halfdup | + Force_rxflow_en | Force_txflow_en | Cxpl_dbg_sel | + ASF | Macdbgo_sel); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) + RTL_W16(tp, CPlusCmd, tp->cp_cmd); +#else + rtl8127_hw_set_features(dev, dev->features); +#endif + rtl8127_set_rms(tp, tp->rms); + + rtl8127_disable_rxdvgate(dev); + + if (!tp->pci_cfg_is_read) { + pci_read_config_byte(pdev, PCI_COMMAND, &tp->pci_cfg_space.cmd); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_0, &tp->pci_cfg_space.io_base_l); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_0 + 2, &tp->pci_cfg_space.io_base_h); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_2, &tp->pci_cfg_space.mem_base_l); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_2 + 2, &tp->pci_cfg_space.mem_base_h); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_3, &tp->pci_cfg_space.resv_0x1c_l); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_3 + 2, &tp->pci_cfg_space.resv_0x1c_h); + pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tp->pci_cfg_space.ilr); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_4, &tp->pci_cfg_space.resv_0x20_l); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_4 + 2, &tp->pci_cfg_space.resv_0x20_h); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_5, &tp->pci_cfg_space.resv_0x24_l); + pci_read_config_word(pdev, PCI_BASE_ADDRESS_5 + 2, &tp->pci_cfg_space.resv_0x24_h); + pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->pci_cfg_space.resv_0x2c_l); + pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID + 2, &tp->pci_cfg_space.resv_0x2c_h); + if (tp->HwPcieSNOffset > 0) { + tp->pci_cfg_space.pci_sn_l = rtl8127_csi_read(tp, tp->HwPcieSNOffset); + tp->pci_cfg_space.pci_sn_h = rtl8127_csi_read(tp, tp->HwPcieSNOffset + 4); + } + + tp->pci_cfg_is_read = 1; + } + + /* Set Rx packet filter */ + rtl8127_hw_set_rx_packet_filter(dev); + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH && !tp->dash_printer_enabled) + NICChkTypeEnableDashInterrupt(tp); +#endif + + rtl8127_enable_aspm_clkreq_lock(tp, aspm ? 1 : 0); + + rtl8127_disable_cfg9346_write(tp); + + fsleep(10); +} + +void +rtl8127_hw_start(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + +#ifdef ENABLE_LIB_SUPPORT + rtl8127_init_lib_ring(tp); +#endif + + RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); + + rtl8127_enable_hw_interrupt(tp); + + rtl8127_lib_reset_complete(tp); +} + +static int +rtl8127_change_mtu(struct net_device *dev, + int new_mtu) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int ret = 0; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,10,0) + if (new_mtu < ETH_MIN_MTU) + return -EINVAL; + else if (new_mtu > tp->max_jumbo_frame_size) + new_mtu = tp->max_jumbo_frame_size; +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,10,0) + + dev->mtu = new_mtu; + + tp->eee.tx_lpi_timer = dev->mtu + ETH_HLEN + 0x20; + + if (!netif_running(dev)) + goto out; + + rtl8127_down(dev); + + rtl8127_set_rxbufsize(tp, dev); + + ret = rtl8127_init_ring(dev); + + if (ret < 0) + goto err_out; + +#ifdef CONFIG_R8127_NAPI + rtl8127_enable_napi(tp); +#endif//CONFIG_R8127_NAPI + + if (tp->link_ok(dev)) + rtl8127_link_on_patch(dev); + else + rtl8127_link_down_patch(dev); + + //mod_timer(&tp->esd_timer, jiffies + RTL8127_ESD_TIMEOUT); + //mod_timer(&tp->link_timer, jiffies + RTL8127_LINK_TIMEOUT); +out: +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) + netdev_update_features(dev); +#endif + +err_out: + return ret; +} + +static inline void +rtl8127_set_desc_dma_addr(struct rtl8127_private *tp, + struct RxDesc *desc, + dma_addr_t mapping) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + ((struct RxDescV3 *)desc)->addr = cpu_to_le64(mapping); + break; + case RX_DESC_RING_TYPE_4: + ((struct RxDescV4 *)desc)->addr = cpu_to_le64(mapping); + break; + default: + desc->addr = cpu_to_le64(mapping); + break; + } +} + +static inline void +rtl8127_mark_to_asic_v1(struct RxDesc *desc, + u32 rx_buf_sz) +{ + u32 eor = le32_to_cpu(desc->opts1) & RingEnd; + + WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | rx_buf_sz)); +} + +static inline void +rtl8127_mark_to_asic_v3(struct RxDescV3 *descv3, + u32 rx_buf_sz) +{ + u32 eor = le32_to_cpu(descv3->RxDescNormalDDWord4.opts1) & RingEnd; + + WRITE_ONCE(descv3->RxDescNormalDDWord4.opts1, cpu_to_le32(DescOwn | eor | rx_buf_sz)); +} + +static inline void +rtl8127_mark_to_asic_v4(struct RxDescV4 *descv4, + u32 rx_buf_sz) +{ + u32 eor = le32_to_cpu(descv4->RxDescNormalDDWord2.opts1) & RingEnd; + + WRITE_ONCE(descv4->RxDescNormalDDWord2.opts1, cpu_to_le32(DescOwn | eor | rx_buf_sz)); +} + +void +rtl8127_mark_to_asic(struct rtl8127_private *tp, + struct RxDesc *desc, + u32 rx_buf_sz) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + rtl8127_mark_to_asic_v3((struct RxDescV3 *)desc, rx_buf_sz); + break; + case RX_DESC_RING_TYPE_4: + rtl8127_mark_to_asic_v4((struct RxDescV4 *)desc, rx_buf_sz); + break; + default: + rtl8127_mark_to_asic_v1(desc, rx_buf_sz); + break; + } +} + +static inline void +rtl8127_map_to_asic(struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + struct RxDesc *desc, + dma_addr_t mapping, + u32 rx_buf_sz, + const u32 cur_rx) +{ + ring->RxDescPhyAddr[cur_rx] = mapping; + rtl8127_set_desc_dma_addr(tp, desc, mapping); + wmb(); + rtl8127_mark_to_asic(tp, desc, rx_buf_sz); +} + +#ifdef ENABLE_PAGE_REUSE + +static int +rtl8127_alloc_rx_page(struct rtl8127_private *tp, struct rtl8127_rx_ring *ring, + struct rtl8127_rx_buffer *rxb) +{ + struct page *page; + dma_addr_t dma; + unsigned int order = tp->rx_buf_page_order; + + //get free page + page = dev_alloc_pages(order); + + if (unlikely(!page)) + return -ENOMEM; + + dma = dma_map_page_attrs(&tp->pci_dev->dev, page, 0, + tp->rx_buf_page_size, + DMA_FROM_DEVICE, + (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)); + + if (unlikely(dma_mapping_error(&tp->pci_dev->dev, dma))) { + __free_pages(page, order); + return -ENOMEM; + } + + rxb->page = page; + rxb->data = page_address(page); + rxb->page_offset = ring->rx_offset; + rxb->dma = dma; + + //after page alloc, page refcount already = 1 + + return 0; +} + +static void +rtl8127_free_rx_page(struct rtl8127_private *tp, struct rtl8127_rx_buffer *rxb) +{ + if (!rxb->page) + return; + + dma_unmap_page_attrs(&tp->pci_dev->dev, rxb->dma, + tp->rx_buf_page_size, + DMA_FROM_DEVICE, + (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)); + __free_pages(rxb->page, tp->rx_buf_page_order); + rxb->page = NULL; +} + +static void +_rtl8127_rx_clear(struct rtl8127_private *tp, struct rtl8127_rx_ring *ring) +{ + int i; + struct rtl8127_rx_buffer *rxb; + + for (i = 0; i < ring->num_rx_desc; i++) { + rxb = &ring->rx_buffer[i]; + if (rxb->skb) { + dev_kfree_skb(rxb->skb); + rxb->skb = NULL; + } + rtl8127_free_rx_page(tp, rxb); + } +} + +static u32 +rtl8127_rx_fill(struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + struct net_device *dev, + u32 start, + u32 end, + u8 in_intr) +{ + u32 cur; + struct rtl8127_rx_buffer *rxb; + + for (cur = start; end - cur > 0; cur++) { + int ret, i = cur % ring->num_rx_desc; + + rxb = &ring->rx_buffer[i]; + if (rxb->page) + continue; + + ret = rtl8127_alloc_rx_page(tp, ring, rxb); + if (ret) + break; + + dma_sync_single_range_for_device(tp_to_dev(tp), + rxb->dma, + rxb->page_offset, + tp->rx_buf_sz, + DMA_FROM_DEVICE); + + rtl8127_map_to_asic(tp, ring, + rtl8127_get_rxdesc(tp, ring->RxDescArray, i), + rxb->dma + rxb->page_offset, + tp->rx_buf_sz, i); + } + return cur - start; +} + +#else //ENABLE_PAGE_REUSE + +static void +rtl8127_free_rx_skb(struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + struct sk_buff **sk_buff, + struct RxDesc *desc, + const u32 cur_rx) +{ + struct pci_dev *pdev = tp->pci_dev; + + dma_unmap_single(&pdev->dev, ring->RxDescPhyAddr[cur_rx], tp->rx_buf_sz, + DMA_FROM_DEVICE); + dev_kfree_skb(*sk_buff); + *sk_buff = NULL; + rtl8127_make_unusable_by_asic(tp, desc); +} + +static int +rtl8127_alloc_rx_skb(struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + struct sk_buff **sk_buff, + struct RxDesc *desc, + int rx_buf_sz, + const u32 cur_rx, + u8 in_intr) +{ + struct sk_buff *skb; + dma_addr_t mapping; + int ret = 0; + + if (in_intr) + skb = RTL_ALLOC_SKB_INTR(&tp->r8127napi[ring->index].napi, rx_buf_sz + R8127_RX_ALIGN); + else + skb = dev_alloc_skb(rx_buf_sz + R8127_RX_ALIGN); + + if (unlikely(!skb)) + goto err_out; + + if (!in_intr || !R8127_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8127_RX_ALIGN); + + mapping = dma_map_single(tp_to_dev(tp), skb->data, rx_buf_sz, + DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(tp_to_dev(tp), mapping))) { + if (unlikely(net_ratelimit())) + netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); + goto err_out; + } + + *sk_buff = skb; + rtl8127_map_to_asic(tp, ring, desc, mapping, rx_buf_sz, cur_rx); +out: + return ret; + +err_out: + if (skb) + dev_kfree_skb(skb); + ret = -ENOMEM; + rtl8127_make_unusable_by_asic(tp, desc); + goto out; +} + +static void +_rtl8127_rx_clear(struct rtl8127_private *tp, struct rtl8127_rx_ring *ring) +{ + int i; + + for (i = 0; i < ring->num_rx_desc; i++) { + if (ring->Rx_skbuff[i]) { + rtl8127_free_rx_skb(tp, + ring, + ring->Rx_skbuff + i, + rtl8127_get_rxdesc(tp, ring->RxDescArray, i), + i); + ring->Rx_skbuff[i] = NULL; + } + } +} + +static u32 +rtl8127_rx_fill(struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + struct net_device *dev, + u32 start, + u32 end, + u8 in_intr) +{ + u32 cur; + + for (cur = start; end - cur > 0; cur++) { + int ret, i = cur % ring->num_rx_desc; + + if (ring->Rx_skbuff[i]) + continue; + + ret = rtl8127_alloc_rx_skb(tp, + ring, + ring->Rx_skbuff + i, + rtl8127_get_rxdesc(tp, ring->RxDescArray, i), + tp->rx_buf_sz, + i, + in_intr); + if (ret < 0) + break; + } + return cur - start; +} + +#endif //ENABLE_PAGE_REUSE + +void +rtl8127_rx_clear(struct rtl8127_private *tp) +{ + int i; + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8127_rx_ring *ring = &tp->rx_ring[i]; + + _rtl8127_rx_clear(tp, ring); + } +} + +static void +rtl8127_mark_as_last_descriptor_v1(struct RxDesc *desc) +{ + desc->opts1 |= cpu_to_le32(RingEnd); +} + +static void +rtl8127_mark_as_last_descriptor_v3(struct RxDescV3 *descv3) +{ + descv3->RxDescNormalDDWord4.opts1 |= cpu_to_le32(RingEnd); +} + +static void +rtl8127_mark_as_last_descriptor_v4(struct RxDescV4 *descv4) +{ + descv4->RxDescNormalDDWord2.opts1 |= cpu_to_le32(RingEnd); +} + +void +rtl8127_mark_as_last_descriptor(struct rtl8127_private *tp, + struct RxDesc *desc) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + rtl8127_mark_as_last_descriptor_v3((struct RxDescV3 *)desc); + break; + case RX_DESC_RING_TYPE_4: + rtl8127_mark_as_last_descriptor_v4((struct RxDescV4 *)desc); + break; + default: + rtl8127_mark_as_last_descriptor_v1(desc); + break; + } +} + +static void +rtl8127_desc_addr_fill(struct rtl8127_private *tp) +{ + int i; + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8127_tx_ring *ring = &tp->tx_ring[i]; + RTL_W32(tp, ring->tdsar_reg, ((u64)ring->TxPhyAddr & DMA_BIT_MASK(32))); + RTL_W32(tp, ring->tdsar_reg + 4, ((u64)ring->TxPhyAddr >> 32)); + } + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8127_rx_ring *ring = &tp->rx_ring[i]; + RTL_W32(tp, ring->rdsar_reg, ((u64)ring->RxPhyAddr & DMA_BIT_MASK(32))); + RTL_W32(tp, ring->rdsar_reg + 4, ((u64)ring->RxPhyAddr >> 32)); + } +} + +static void +rtl8127_tx_desc_init(struct rtl8127_private *tp) +{ + int i = 0; + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8127_tx_ring *ring = &tp->tx_ring[i]; + memset(ring->TxDescArray, 0x0, ring->TxDescAllocSize); + + ring->TxDescArray[ring->num_tx_desc - 1].opts1 = cpu_to_le32(RingEnd); + } +} + +static void +rtl8127_rx_desc_init(struct rtl8127_private *tp) +{ + int i; + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8127_rx_ring *ring = &tp->rx_ring[i]; + memset(ring->RxDescArray, 0x0, ring->RxDescAllocSize); + } +} + +int +rtl8127_init_ring(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + int i; + + rtl8127_init_ring_indexes(tp); + + rtl8127_tx_desc_init(tp); + rtl8127_rx_desc_init(tp); + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8127_tx_ring *ring = &tp->tx_ring[i]; + memset(ring->tx_skb, 0x0, sizeof(ring->tx_skb)); + } + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8127_rx_ring *ring = &tp->rx_ring[i]; +#ifdef ENABLE_PAGE_REUSE + ring->rx_offset = R8127_RX_ALIGN; +#else + memset(ring->Rx_skbuff, 0x0, sizeof(ring->Rx_skbuff)); +#endif //ENABLE_PAGE_REUSE + if (rtl8127_rx_fill(tp, ring, dev, 0, ring->num_rx_desc, 0) != ring->num_rx_desc) + goto err_out; + + rtl8127_mark_as_last_descriptor(tp, rtl8127_get_rxdesc(tp, ring->RxDescArray, ring->num_rx_desc - 1)); + } + + return 0; + +err_out: + rtl8127_rx_clear(tp); + return -ENOMEM; +} + +static void +rtl8127_unmap_tx_skb(struct pci_dev *pdev, + struct ring_info *tx_skb, + struct TxDesc *desc) +{ + unsigned int len = tx_skb->len; + + dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); + + desc->opts1 = cpu_to_le32(RTK_MAGIC_DEBUG_VALUE); + desc->opts2 = 0x00; + desc->addr = RTL8127_MAGIC_NUMBER; + tx_skb->len = 0; +} + +static void +rtl8127_tx_clear_range(struct rtl8127_private *tp, + struct rtl8127_tx_ring *ring, + u32 start, + unsigned int n) +{ + unsigned int i; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + struct net_device *dev = tp->dev; +#endif + + for (i = 0; i < n; i++) { + unsigned int entry = (start + i) % ring->num_tx_desc; + struct ring_info *tx_skb = ring->tx_skb + entry; + unsigned int len = tx_skb->len; + + if (len) { + struct sk_buff *skb = tx_skb->skb; + + rtl8127_unmap_tx_skb(tp->pci_dev, tx_skb, + ring->TxDescArray + entry); + if (skb) { + RTLDEV->stats.tx_dropped++; + dev_kfree_skb_any(skb); + tx_skb->skb = NULL; + } + } + } +} + +void +rtl8127_tx_clear(struct rtl8127_private *tp) +{ + int i; + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8127_tx_ring *ring = &tp->tx_ring[i]; + rtl8127_tx_clear_range(tp, ring, ring->dirty_tx, ring->num_tx_desc); + ring->cur_tx = ring->dirty_tx = 0; + } +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8127_schedule_reset_work(struct rtl8127_private *tp) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + set_bit(R8127_FLAG_TASK_RESET_PENDING, tp->task_flags); + schedule_delayed_work(&tp->reset_task, 4); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) +} + +static void rtl8127_schedule_esd_work(struct rtl8127_private *tp) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + set_bit(R8127_FLAG_TASK_ESD_CHECK_PENDING, tp->task_flags); + schedule_delayed_work(&tp->esd_task, RTL8127_ESD_TIMEOUT); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) +} + +static void rtl8127_schedule_linkchg_work(struct rtl8127_private *tp) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + set_bit(R8127_FLAG_TASK_LINKCHG_CHECK_PENDING, tp->task_flags); + schedule_delayed_work(&tp->linkchg_task, 4); +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) +} + +#define rtl8127_cancel_schedule_reset_work(a) +#define rtl8127_cancel_schedule_esd_work(a) +#define rtl8127_cancel_schedule_linkchg_work(a) + +#else +static void rtl8127_schedule_reset_work(struct rtl8127_private *tp) +{ + set_bit(R8127_FLAG_TASK_RESET_PENDING, tp->task_flags); + schedule_delayed_work(&tp->reset_task, 4); +} + +static void rtl8127_cancel_schedule_reset_work(struct rtl8127_private *tp) +{ + struct work_struct *work = &tp->reset_task.work; + + if (!work->func) + return; + + cancel_delayed_work_sync(&tp->reset_task); +} + +static void rtl8127_schedule_esd_work(struct rtl8127_private *tp) +{ + set_bit(R8127_FLAG_TASK_ESD_CHECK_PENDING, tp->task_flags); + schedule_delayed_work(&tp->esd_task, RTL8127_ESD_TIMEOUT); +} + +static void rtl8127_cancel_schedule_esd_work(struct rtl8127_private *tp) +{ + struct work_struct *work = &tp->esd_task.work; + + if (!work->func) + return; + + cancel_delayed_work_sync(&tp->esd_task); +} + +static void rtl8127_schedule_linkchg_work(struct rtl8127_private *tp) +{ + set_bit(R8127_FLAG_TASK_LINKCHG_CHECK_PENDING, tp->task_flags); + schedule_delayed_work(&tp->linkchg_task, 4); +} + +static void rtl8127_cancel_schedule_linkchg_work(struct rtl8127_private *tp) +{ + struct work_struct *work = &tp->linkchg_task.work; + + if (!work->func) + return; + + cancel_delayed_work_sync(&tp->linkchg_task); +} +#endif + +static void rtl8127_init_all_schedule_work(struct rtl8127_private *tp) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + INIT_WORK(&tp->reset_task, rtl8127_reset_task, dev); + INIT_WORK(&tp->esd_task, rtl8127_esd_task, dev); + INIT_WORK(&tp->linkchg_task, rtl8127_linkchg_task, dev); +#else + INIT_DELAYED_WORK(&tp->reset_task, rtl8127_reset_task); + INIT_DELAYED_WORK(&tp->esd_task, rtl8127_esd_task); + INIT_DELAYED_WORK(&tp->linkchg_task, rtl8127_linkchg_task); +#endif +} + +static void rtl8127_cancel_all_schedule_work(struct rtl8127_private *tp) +{ + rtl8127_cancel_schedule_reset_work(tp); + rtl8127_cancel_schedule_esd_work(tp); + rtl8127_cancel_schedule_linkchg_work(tp); +} + +static void +rtl8127_wait_for_irq_complete(struct rtl8127_private *tp) +{ + if (tp->features & RTL_FEATURE_MSIX) { + int i; + for (i = 0; i < tp->irq_nvecs; i++) + synchronize_irq(tp->irq_tbl[i].vector); + } else { + synchronize_irq(tp->dev->irq); + } +} + +void +_rtl8127_wait_for_quiescence(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + /* Wait for any pending NAPI task to complete */ +#ifdef CONFIG_R8127_NAPI + rtl8127_disable_napi(tp); +#endif//CONFIG_R8127_NAPI + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,67) + /* Give a racing hard_start_xmit a few cycles to complete. */ + synchronize_net(); +#endif + + rtl8127_irq_mask_and_ack(tp); + + rtl8127_wait_for_irq_complete(tp); +} + +static void +rtl8127_wait_for_quiescence(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + //suppress unused variable + (void)(tp); + + _rtl8127_wait_for_quiescence(dev); + +#ifdef CONFIG_R8127_NAPI + rtl8127_enable_napi(tp); +#endif//CONFIG_R8127_NAPI +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8127_reset_task(void *_data) +{ + struct net_device *dev = _data; + struct rtl8127_private *tp = netdev_priv(dev); +#else +static void rtl8127_reset_task(struct work_struct *work) +{ + struct rtl8127_private *tp = + container_of(work, struct rtl8127_private, reset_task.work); + struct net_device *dev = tp->dev; +#endif + int i; + + rtnl_lock(); + + if (!netif_running(dev) || + test_bit(R8127_FLAG_DOWN, tp->task_flags) || + !test_and_clear_bit(R8127_FLAG_TASK_RESET_PENDING, tp->task_flags)) + goto out_unlock; + + netdev_err(dev, "Device reseting!\n"); + + netif_carrier_off(dev); + netif_tx_disable(dev); + _rtl8127_wait_for_quiescence(dev); + rtl8127_hw_reset(dev); + + rtl8127_tx_clear(tp); + + rtl8127_init_ring_indexes(tp); + + rtl8127_tx_desc_init(tp); + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8127_rx_ring *ring; + u32 entry; + + ring = &tp->rx_ring[i]; + for (entry = 0; entry < ring->num_rx_desc; entry++) { + struct RxDesc *desc; + + desc = rtl8127_get_rxdesc(tp, ring->RxDescArray, entry); + rtl8127_mark_to_asic(tp, desc, tp->rx_buf_sz); + } + } + +#ifdef ENABLE_PTP_SUPPORT + rtl8127_ptp_reset(tp); +#endif + +#ifdef CONFIG_R8127_NAPI + rtl8127_enable_napi(tp); +#endif //CONFIG_R8127_NAPI + + if (tp->resume_not_chg_speed) { + _rtl8127_check_link_status(dev, R8127_LINK_STATE_UNKNOWN); + + tp->resume_not_chg_speed = 0; + } else { + rtl8127_enable_hw_linkchg_interrupt(tp); + + rtl8127_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); + } + +out_unlock: + rtnl_unlock(); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8127_esd_task(void *_data) +{ + struct net_device *dev = _data; + struct rtl8127_private *tp = netdev_priv(dev); +#else +static void rtl8127_esd_task(struct work_struct *work) +{ + struct rtl8127_private *tp = + container_of(work, struct rtl8127_private, esd_task.work); + struct net_device *dev = tp->dev; +#endif + rtnl_lock(); + + if (!netif_running(dev) || + test_bit(R8127_FLAG_DOWN, tp->task_flags) || + !test_and_clear_bit(R8127_FLAG_TASK_ESD_CHECK_PENDING, tp->task_flags)) + goto out_unlock; + + rtl8127_esd_checker(tp); + + rtl8127_schedule_esd_work(tp); + +out_unlock: + rtnl_unlock(); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8127_linkchg_task(void *_data) +{ + struct net_device *dev = _data; + //struct rtl8127_private *tp = netdev_priv(dev); +#else +static void rtl8127_linkchg_task(struct work_struct *work) +{ + struct rtl8127_private *tp = + container_of(work, struct rtl8127_private, linkchg_task.work); + struct net_device *dev = tp->dev; +#endif + rtnl_lock(); + + if (!netif_running(dev) || + test_bit(R8127_FLAG_DOWN, tp->task_flags) || + !test_and_clear_bit(R8127_FLAG_TASK_LINKCHG_CHECK_PENDING, tp->task_flags)) + goto out_unlock; + + rtl8127_check_link_status(dev); + +out_unlock: + rtnl_unlock(); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) +static void +rtl8127_tx_timeout(struct net_device *dev, unsigned int txqueue) +#else +static void +rtl8127_tx_timeout(struct net_device *dev) +#endif +{ + struct rtl8127_private *tp = netdev_priv(dev); + + netdev_err(dev, "Transmit timeout reset Device!\n"); + + /* Let's wait a bit while any (async) irq lands on */ + rtl8127_schedule_reset_work(tp); +} + +static u32 +rtl8127_get_txd_opts1(struct rtl8127_tx_ring *ring, + u32 opts1, + u32 len, + unsigned int entry) +{ + u32 status = opts1 | len; + + if (entry == ring->num_tx_desc - 1) + status |= RingEnd; + + return status; +} + +static int +rtl8127_xmit_frags(struct rtl8127_private *tp, + struct rtl8127_tx_ring *ring, + struct sk_buff *skb, + const u32 *opts) +{ + struct skb_shared_info *info = skb_shinfo(skb); + unsigned int cur_frag, entry; + struct TxDesc *txd = NULL; + const unsigned char nr_frags = info->nr_frags; + unsigned long PktLenCnt = 0; + bool LsoPatchEnabled = FALSE; + + entry = ring->cur_tx; + for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) { + skb_frag_t *frag = info->frags + cur_frag; + dma_addr_t mapping; + u32 status, len; + void *addr; + + entry = (entry + 1) % ring->num_tx_desc; + + txd = ring->TxDescArray + entry; +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) + len = frag->size; + addr = ((void *) page_address(frag->page)) + frag->page_offset; +#else + len = skb_frag_size(frag); + addr = skb_frag_address(frag); +#endif + mapping = dma_map_single(tp_to_dev(tp), addr, len, DMA_TO_DEVICE); + + if (unlikely(dma_mapping_error(tp_to_dev(tp), mapping))) { + if (unlikely(net_ratelimit())) + netif_err(tp, drv, tp->dev, + "Failed to map TX fragments DMA!\n"); + goto err_out; + } + + /* anti gcc 2.95.3 bugware (sic) */ + status = rtl8127_get_txd_opts1(ring, opts[0], len, entry); + if (cur_frag == (nr_frags - 1) || LsoPatchEnabled == TRUE) + status |= LastFrag; + + txd->addr = cpu_to_le64(mapping); + + ring->tx_skb[entry].len = len; + + txd->opts2 = cpu_to_le32(opts[1]); + wmb(); + txd->opts1 = cpu_to_le32(status); + + PktLenCnt += len; + } + + return cur_frag; + +err_out: + rtl8127_tx_clear_range(tp, ring, ring->cur_tx + 1, cur_frag); + return -EIO; +} + +static inline +__be16 get_protocol(struct sk_buff *skb) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37) + return vlan_get_protocol(skb); +#else + __be16 protocol; + + if (skb->protocol == htons(ETH_P_8021Q)) + protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; + else + protocol = skb->protocol; + + return protocol; +#endif +} + +static inline +u8 rtl8127_get_l4_protocol(struct sk_buff *skb) +{ + int no = skb_network_offset(skb); + struct ipv6hdr *i6h, _i6h; + struct iphdr *ih, _ih; + u8 ip_protocol = IPPROTO_RAW; + + switch (get_protocol(skb)) { + case __constant_htons(ETH_P_IP): + ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); + if (ih) + ip_protocol = ih->protocol; + break; + case __constant_htons(ETH_P_IPV6): + i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); + if (i6h) + ip_protocol = i6h->nexthdr; + break; + } + + return ip_protocol; +} + +static bool rtl8127_skb_pad_with_len(struct sk_buff *skb, unsigned int len) +{ + if (skb_padto(skb, len)) + return false; + skb_put(skb, len - skb->len); + return true; +} + +static bool rtl8127_skb_pad(struct sk_buff *skb) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0) + return rtl8127_skb_pad_with_len(skb, ETH_ZLEN); +#else + return !eth_skb_pad(skb); +#endif +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) +/* msdn_giant_send_check() + * According to the document of microsoft, the TCP Pseudo Header excludes the + * packet length for IPv6 TCP large packets. + */ +static int msdn_giant_send_check(struct sk_buff *skb) +{ + const struct ipv6hdr *ipv6h; + struct tcphdr *th; + int ret; + + ret = skb_cow_head(skb, 0); + if (ret) + return ret; + + ipv6h = ipv6_hdr(skb); + th = tcp_hdr(skb); + + th->check = 0; + th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); + + return ret; +} +#endif + +static bool rtl8127_require_pad_ptp_pkt(struct rtl8127_private *tp) +{ + return false; +} + +#define MIN_PATCH_LEN (47) +static u32 +rtl8127_get_patch_pad_len(struct rtl8127_private *tp, + struct sk_buff *skb) +{ + u32 pad_len = 0; + int trans_data_len; + u32 hdr_len; + u32 pkt_len = skb->len; + u8 ip_protocol; + bool has_trans = skb_transport_header_was_set(skb); + + if (!rtl8127_require_pad_ptp_pkt(tp)) + goto no_padding; + + if (!(has_trans && (pkt_len < 175))) //128 + MIN_PATCH_LEN + goto no_padding; + + ip_protocol = rtl8127_get_l4_protocol(skb); + if (!(ip_protocol == IPPROTO_TCP || ip_protocol == IPPROTO_UDP)) + goto no_padding; + + trans_data_len = pkt_len - + (skb->transport_header - + skb_headroom(skb)); + if (ip_protocol == IPPROTO_UDP) { + if (trans_data_len > 3 && trans_data_len < MIN_PATCH_LEN) { + u16 dest_port = 0; + + skb_copy_bits(skb, skb->transport_header - skb_headroom(skb) + 2, &dest_port, 2); + dest_port = ntohs(dest_port); + + if (dest_port == 0x13f || + dest_port == 0x140) { + pad_len = MIN_PATCH_LEN - trans_data_len; + goto out; + } + } + } + + hdr_len = 0; + if (ip_protocol == IPPROTO_TCP) + hdr_len = 20; + else if (ip_protocol == IPPROTO_UDP) + hdr_len = 8; + if (trans_data_len < hdr_len) + pad_len = hdr_len - trans_data_len; + +out: + if ((pkt_len + pad_len) < ETH_ZLEN) + pad_len = ETH_ZLEN - pkt_len; + + return pad_len; + +no_padding: + + return 0; +} + +static bool +rtl8127_tso_csum(struct sk_buff *skb, + struct net_device *dev, + u32 *opts, + unsigned int *bytecount, + unsigned short *gso_segs) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned long large_send = 0; + u32 csum_cmd = 0; + u8 sw_calc_csum = false; + u8 check_patch_required = true; + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (dev->features & (NETIF_F_TSO | NETIF_F_TSO6)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) + u32 mss = skb_shinfo(skb)->tso_size; +#else + u32 mss = skb_shinfo(skb)->gso_size; +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) + + /* TCP Segmentation Offload (or TCP Large Send) */ + if (mss) { + union { + struct iphdr *v4; + struct ipv6hdr *v6; + unsigned char *hdr; + } ip; + union { + struct tcphdr *tcp; + struct udphdr *udp; + unsigned char *hdr; + } l4; + u32 l4_offset, hdr_len; + + ip.hdr = skb_network_header(skb); + l4.hdr = skb_checksum_start(skb); + + l4_offset = skb_transport_offset(skb); + assert((l4_offset%2) == 0); + switch (get_protocol(skb)) { + case __constant_htons(ETH_P_IP): + if (l4_offset <= GTTCPHO_MAX) { + opts[0] |= GiantSendv4; + opts[0] |= l4_offset << GTTCPHO_SHIFT; + opts[1] |= min(mss, MSS_MAX) << 18; + large_send = 1; + } + break; + case __constant_htons(ETH_P_IPV6): +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) + if (msdn_giant_send_check(skb)) + return false; +#endif + if (l4_offset <= GTTCPHO_MAX) { + opts[0] |= GiantSendv6; + opts[0] |= l4_offset << GTTCPHO_SHIFT; + opts[1] |= min(mss, MSS_MAX) << 18; + large_send = 1; + } + break; + default: + if (unlikely(net_ratelimit())) + dprintk("tso proto=%x!\n", skb->protocol); + break; + } + + if (large_send == 0) + return false; + + + /* compute length of segmentation header */ + hdr_len = (l4.tcp->doff * 4) + l4_offset; + /* update gso size and bytecount with header size */ + *gso_segs = skb_shinfo(skb)->gso_segs; + *bytecount += (*gso_segs - 1) * hdr_len; + + return true; + } + } +#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + + if (skb->ip_summed == CHECKSUM_PARTIAL) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) + const struct iphdr *ip = skb->nh.iph; + + if (dev->features & NETIF_F_IP_CSUM) { + if (ip->protocol == IPPROTO_TCP) + csum_cmd = tp->tx_ip_csum_cmd | tp->tx_tcp_csum_cmd; + else if (ip->protocol == IPPROTO_UDP) + csum_cmd = tp->tx_ip_csum_cmd | tp->tx_udp_csum_cmd; + else if (ip->protocol == IPPROTO_IP) + csum_cmd = tp->tx_ip_csum_cmd; + } +#else + u8 ip_protocol = IPPROTO_RAW; + + switch (get_protocol(skb)) { + case __constant_htons(ETH_P_IP): + if (dev->features & NETIF_F_IP_CSUM) { + ip_protocol = ip_hdr(skb)->protocol; + csum_cmd = tp->tx_ip_csum_cmd; + } + break; + case __constant_htons(ETH_P_IPV6): + if (dev->features & NETIF_F_IPV6_CSUM) { + if (skb_transport_offset(skb) > 0 && skb_transport_offset(skb) <= TCPHO_MAX) { + ip_protocol = ipv6_hdr(skb)->nexthdr; + csum_cmd = tp->tx_ipv6_csum_cmd; + csum_cmd |= skb_transport_offset(skb) << TCPHO_SHIFT; + } + } + break; + default: + if (unlikely(net_ratelimit())) + dprintk("checksum_partial proto=%x!\n", skb->protocol); + break; + } + + if (ip_protocol == IPPROTO_TCP) + csum_cmd |= tp->tx_tcp_csum_cmd; + else if (ip_protocol == IPPROTO_UDP) + csum_cmd |= tp->tx_udp_csum_cmd; +#endif + if (csum_cmd == 0) { + sw_calc_csum = true; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + WARN_ON(1); /* we need a WARN() */ +#endif + } + + if (ip_protocol == IPPROTO_TCP) + check_patch_required = false; + } + + if (check_patch_required) { + u32 pad_len = rtl8127_get_patch_pad_len(tp, skb); + + if (pad_len > 0) { + if (!rtl8127_skb_pad_with_len(skb, skb->len + pad_len)) + return false; + + if (csum_cmd != 0) + sw_calc_csum = true; + } + } + + if (skb->len < ETH_ZLEN) { + if (tp->UseSwPaddingShortPkt || + (tp->ShortPacketSwChecksum && csum_cmd != 0)) { + if (!rtl8127_skb_pad(skb)) + return false; + + if (csum_cmd != 0) + sw_calc_csum = true; + } + } + + if (sw_calc_csum) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,7) + skb_checksum_help(&skb, 0); +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) + skb_checksum_help(skb, 0); +#else + skb_checksum_help(skb); +#endif + } else + opts[1] |= csum_cmd; + + return true; +} + +static bool rtl8127_tx_slots_avail(struct rtl8127_private *tp, + struct rtl8127_tx_ring *ring) +{ + unsigned int slots_avail = READ_ONCE(ring->dirty_tx) + ring->num_tx_desc + - READ_ONCE(ring->cur_tx); + + /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ + return slots_avail > MAX_SKB_FRAGS; +} + +static inline u32 +rtl8127_fast_mod_mask(const u32 input, const u32 mask) +{ + return input > mask ? input & mask : input; +} + +static void rtl8127_doorbell(struct rtl8127_private *tp, + struct rtl8127_tx_ring *ring) +{ + if (tp->EnableTxNoClose) { + if (tp->HwSuppTxNoCloseVer > 3) + RTL_W32(tp, ring->sw_tail_ptr_reg, ring->cur_tx); + else + RTL_W16(tp, ring->sw_tail_ptr_reg, ring->cur_tx); + } else { + /* set polling bit */ + RTL_W32(tp, TPPOLL_8125, BIT(ring->index)); + } +} + +static netdev_tx_t +rtl8127_start_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + unsigned int bytecount; + unsigned short gso_segs; + struct ring_info *last; + unsigned int last_entry; + unsigned int entry; + struct TxDesc *txd; + dma_addr_t mapping; + u32 len; + u32 opts[2]; + netdev_tx_t ret = NETDEV_TX_OK; + int frags; + u8 EnableTxNoClose = tp->EnableTxNoClose; + const u16 queue_mapping = skb_get_queue_mapping(skb); + struct rtl8127_tx_ring *ring; + bool stop_queue; + + assert(queue_mapping < tp->num_tx_rings); + + ring = &tp->tx_ring[queue_mapping]; + + if (unlikely(!rtl8127_tx_slots_avail(tp, ring))) { + if (netif_msg_drv(tp)) { + printk(KERN_ERR + "%s: BUG! Tx Ring[%d] full when queue awake!\n", + dev->name, + queue_mapping); + } + goto err_stop; + } + + entry = ring->cur_tx % ring->num_tx_desc; + txd = ring->TxDescArray + entry; + + if (!EnableTxNoClose) { + if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) { + if (netif_msg_drv(tp)) { + printk(KERN_ERR + "%s: BUG! Tx Desc is own by hardware!\n", + dev->name); + } + goto err_stop; + } + } + + bytecount = skb->len; + gso_segs = 1; + + opts[0] = DescOwn; + opts[1] = rtl8127_tx_vlan_tag(tp, skb); + + if (unlikely(!rtl8127_tso_csum(skb, dev, opts, &bytecount, &gso_segs))) + goto err_dma_0; + + frags = rtl8127_xmit_frags(tp, ring, skb, opts); + if (unlikely(frags < 0)) + goto err_dma_0; + if (frags) { + len = skb_headlen(skb); + opts[0] |= FirstFrag; + } else { + len = skb->len; + opts[0] |= FirstFrag | LastFrag; + } + + opts[0] = rtl8127_get_txd_opts1(ring, opts[0], len, entry); + mapping = dma_map_single(tp_to_dev(tp), skb->data, len, DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(tp_to_dev(tp), mapping))) { + if (unlikely(net_ratelimit())) + netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); + goto err_dma_1; + } + +#ifdef ENABLE_PTP_SUPPORT + if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { + if (!test_and_set_bit_lock(__RTL8127_PTP_TX_IN_PROGRESS, &tp->state)) { + if (tp->hwtstamp_config.tx_type == HWTSTAMP_TX_ON && + !tp->ptp_tx_skb) { + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; + + tp->ptp_tx_skb = skb_get(skb); + tp->ptp_tx_start = jiffies; + schedule_work(&tp->ptp_tx_work); + } else + tp->tx_hwtstamp_skipped++; + } + } +#endif + /* set first fragment's length */ + ring->tx_skb[entry].len = len; + + /* set skb to last fragment */ + last_entry = (entry + frags) % ring->num_tx_desc; + last = &ring->tx_skb[last_entry]; + last->skb = skb; + last->gso_segs = gso_segs; + last->bytecount = bytecount; + + txd->addr = cpu_to_le64(mapping); + txd->opts2 = cpu_to_le32(opts[1]); + wmb(); + txd->opts1 = cpu_to_le32(opts[0]); + + netdev_tx_sent_queue(txring_txq(ring), bytecount); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) + dev->trans_start = jiffies; +#else + skb_tx_timestamp(skb); +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) + + /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ + smp_wmb(); + + WRITE_ONCE(ring->cur_tx, ring->cur_tx + frags + 1); + + stop_queue = !rtl8127_tx_slots_avail(tp, ring); + if (unlikely(stop_queue)) { + /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must + * not miss a ring update when it notices a stopped queue. + */ + smp_wmb(); + netif_stop_subqueue(dev, queue_mapping); + } + + if (netif_xmit_stopped(txring_txq(ring)) || !netdev_xmit_more()) + rtl8127_doorbell(tp, ring); + + if (unlikely(stop_queue)) { + /* Sync with rtl_tx: + * - publish queue status and cur_tx ring index (write barrier) + * - refresh dirty_tx ring index (read barrier). + * May the current thread have a pessimistic view of the ring + * status and forget to wake up queue, a racing rtl_tx thread + * can't. + */ + smp_mb(); + if (rtl8127_tx_slots_avail(tp, ring)) + netif_start_subqueue(dev, queue_mapping); + } +out: + return ret; +err_dma_1: + rtl8127_tx_clear_range(tp, ring, ring->cur_tx + 1, frags); +err_dma_0: + RTLDEV->stats.tx_dropped++; + dev_kfree_skb_any(skb); + ret = NETDEV_TX_OK; + goto out; +err_stop: + netif_stop_subqueue(dev, queue_mapping); + ret = NETDEV_TX_BUSY; + RTLDEV->stats.tx_dropped++; + goto out; +} + +/* recycle tx no close desc*/ +static int +rtl8127_tx_interrupt_noclose(struct rtl8127_tx_ring *ring, int budget) +{ + unsigned int total_bytes = 0, total_packets = 0; + struct rtl8127_private *tp = ring->priv; + struct net_device *dev = tp->dev; + unsigned int dirty_tx, tx_left; + unsigned int tx_desc_closed; + unsigned int count = 0; + + dirty_tx = ring->dirty_tx; + ring->NextHwDesCloPtr = rtl8127_get_hw_clo_ptr(ring); + tx_desc_closed = rtl8127_fast_mod_mask(ring->NextHwDesCloPtr - + ring->BeginHwDesCloPtr, + tp->MaxTxDescPtrMask); + tx_left = min((READ_ONCE(ring->cur_tx) - dirty_tx), tx_desc_closed); + ring->BeginHwDesCloPtr += tx_left; + + while (tx_left > 0) { + unsigned int entry = dirty_tx % ring->num_tx_desc; + struct ring_info *tx_skb = ring->tx_skb + entry; + + rtl8127_unmap_tx_skb(tp->pci_dev, + tx_skb, + ring->TxDescArray + entry); + + if (tx_skb->skb != NULL) { + /* update the statistics for this packet */ + total_bytes += tx_skb->bytecount; + total_packets += tx_skb->gso_segs; + + RTL_NAPI_CONSUME_SKB_ANY(tx_skb->skb, budget); + tx_skb->skb = NULL; + } + dirty_tx++; + tx_left--; + } + + if (total_packets) { + netdev_tx_completed_queue(txring_txq(ring), + total_packets, total_bytes); + + RTLDEV->stats.tx_bytes += total_bytes; + RTLDEV->stats.tx_packets+= total_packets; + } + + if (ring->dirty_tx != dirty_tx) { + count = dirty_tx - ring->dirty_tx; + WRITE_ONCE(ring->dirty_tx, dirty_tx); + smp_wmb(); + if (__netif_subqueue_stopped(dev, ring->index) && + (rtl8127_tx_slots_avail(tp, ring))) { + netif_start_subqueue(dev, ring->index); + } + } + + return count; +} + +/* recycle tx close desc*/ +static int +rtl8127_tx_interrupt_close(struct rtl8127_tx_ring *ring, int budget) +{ + unsigned int total_bytes = 0, total_packets = 0; + struct rtl8127_private *tp = ring->priv; + struct net_device *dev = tp->dev; + unsigned int dirty_tx, tx_left; + unsigned int count = 0; + + dirty_tx = ring->dirty_tx; + tx_left = READ_ONCE(ring->cur_tx) - dirty_tx; + + while (tx_left > 0) { + unsigned int entry = dirty_tx % ring->num_tx_desc; + struct ring_info *tx_skb = ring->tx_skb + entry; + + if (le32_to_cpu(READ_ONCE(ring->TxDescArray[entry].opts1)) & DescOwn) + break; + + rtl8127_unmap_tx_skb(tp->pci_dev, + tx_skb, + ring->TxDescArray + entry); + + if (tx_skb->skb != NULL) { + /* update the statistics for this packet */ + total_bytes += tx_skb->bytecount; + total_packets += tx_skb->gso_segs; + + RTL_NAPI_CONSUME_SKB_ANY(tx_skb->skb, budget); + tx_skb->skb = NULL; + } + dirty_tx++; + tx_left--; + } + + if (total_packets) { + netdev_tx_completed_queue(txring_txq(ring), + total_packets, total_bytes); + + RTLDEV->stats.tx_bytes += total_bytes; + RTLDEV->stats.tx_packets+= total_packets; + } + + if (ring->dirty_tx != dirty_tx) { + count = dirty_tx - ring->dirty_tx; + WRITE_ONCE(ring->dirty_tx, dirty_tx); + smp_wmb(); + if (__netif_subqueue_stopped(dev, ring->index) && + (rtl8127_tx_slots_avail(tp, ring))) { + netif_start_subqueue(dev, ring->index); + } + + if (READ_ONCE(ring->cur_tx) != dirty_tx) + rtl8127_doorbell(tp, ring); + } + + return count; +} + +static int +rtl8127_tx_interrupt(struct rtl8127_tx_ring *ring, int budget) +{ + struct rtl8127_private *tp = ring->priv; + + if (tp->EnableTxNoClose) + return rtl8127_tx_interrupt_noclose(ring, budget); + else + return rtl8127_tx_interrupt_close(ring, budget); +} + +static int +rtl8127_tx_interrupt_with_vector(struct rtl8127_private *tp, + const int message_id, + int budget) +{ + int count = 0; + + switch (tp->HwCurrIsrVer) { + case 3: + case 4: + if (message_id < tp->num_tx_rings) + count += rtl8127_tx_interrupt(&tp->tx_ring[message_id], budget); + break; + case 5: + if (message_id == 16) + count += rtl8127_tx_interrupt(&tp->tx_ring[0], budget); +#ifdef ENABLE_MULTIPLE_TX_QUEUE + else if (message_id == 17 && tp->num_tx_rings > 1) + count += rtl8127_tx_interrupt(&tp->tx_ring[1], budget); +#endif + break; + case 6: + if (message_id == 8) + count += rtl8127_tx_interrupt(&tp->tx_ring[0], budget); +#ifdef ENABLE_MULTIPLE_TX_QUEUE + else if (message_id == 9 && tp->num_tx_rings > 1) + count += rtl8127_tx_interrupt(&tp->tx_ring[1], budget); +#endif + break; + default: + if (message_id == 16) + count += rtl8127_tx_interrupt(&tp->tx_ring[0], budget); +#ifdef ENABLE_MULTIPLE_TX_QUEUE + else if (message_id == 18 && tp->num_tx_rings > 1) + count += rtl8127_tx_interrupt(&tp->tx_ring[1], budget); +#endif + break; + } + + return count; +} + +static inline int +rtl8127_fragmented_frame(struct rtl8127_private *tp, u32 status) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + return (status & (FirstFrag_V3 | LastFrag_V3)) != (FirstFrag_V3 | LastFrag_V3); + case RX_DESC_RING_TYPE_4: + return (status & (FirstFrag_V4 | LastFrag_V4)) != (FirstFrag_V4 | LastFrag_V4); + default: + return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); + } +} + +static inline int +rtl8127_is_non_eop(struct rtl8127_private *tp, u32 status) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + return !(status & LastFrag_V3); + case RX_DESC_RING_TYPE_4: + return !(status & LastFrag_V4); + default: + return !(status & LastFrag); + } +} + +static inline int +rtl8127_rx_desc_type(u32 status) +{ + return ((status >> 26) & 0x0F); +} + +static inline void +rtl8127_rx_v1_csum(struct rtl8127_private *tp, + struct sk_buff *skb, + struct RxDesc *desc) +{ + u32 opts1 = le32_to_cpu(desc->opts1); + + if (((opts1 & RxTCPT) && !(opts1 & RxTCPF)) || + ((opts1 & RxUDPT) && !(opts1 & RxUDPF))) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else + skb_checksum_none_assert(skb); +} + +static inline void +rtl8127_rx_v3_csum(struct rtl8127_private *tp, + struct sk_buff *skb, + struct RxDescV3 *descv3) +{ + u32 opts2 = le32_to_cpu(descv3->RxDescNormalDDWord4.opts2); + + /* rx csum offload for RTL8125 */ + if (((opts2 & RxTCPT_v3) && !(opts2 & RxTCPF_v3)) || + ((opts2 & RxUDPT_v3) && !(opts2 & RxUDPF_v3))) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else + skb_checksum_none_assert(skb); +} + +static inline void +rtl8127_rx_v4_csum(struct rtl8127_private *tp, + struct sk_buff *skb, + struct RxDescV4 *descv4) +{ + u32 opts1 = le32_to_cpu(descv4->RxDescNormalDDWord2.opts1); + + /* rx csum offload for RTL8125 */ + if (((opts1 & RxTCPT_v4) && !(opts1 & RxTCPF_v4)) || + ((opts1 & RxUDPT_v4) && !(opts1 & RxUDPF_v4))) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else + skb_checksum_none_assert(skb); +} + +static inline void +rtl8127_rx_csum(struct rtl8127_private *tp, + struct sk_buff *skb, + struct RxDesc *desc) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + rtl8127_rx_v3_csum(tp, skb, (struct RxDescV3 *)desc); + break; + case RX_DESC_RING_TYPE_4: + rtl8127_rx_v4_csum(tp, skb, (struct RxDescV4 *)desc); + break; + default: + rtl8127_rx_v1_csum(tp, skb, desc); + break; + } +} + +/* +static inline int +rtl8127_try_rx_copy(struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + struct sk_buff **sk_buff, + int pkt_size, + struct RxDesc *desc, + int rx_buf_sz) +{ + int ret = -1; + + struct sk_buff *skb; + + skb = RTL_ALLOC_SKB_INTR(&tp->r8127napi[ring->index].napi, pkt_size + R8127_RX_ALIGN); + if (skb) { + u8 *data; + + data = sk_buff[0]->data; + if (!R8127_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8127_RX_ALIGN); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) + prefetch(data - R8127_RX_ALIGN); +#endif + eth_copy_and_sum(skb, data, pkt_size, 0); + *sk_buff = skb; + rtl8127_mark_to_asic(tp, desc, rx_buf_sz); + ret = 0; + } + + return ret; +} +*/ + +static inline void +rtl8127_rx_skb(struct rtl8127_private *tp, + struct sk_buff *skb, + u32 ring_index) +{ +#ifdef CONFIG_R8127_NAPI +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) + netif_receive_skb(skb); +#else + napi_gro_receive(&tp->r8127napi[ring_index].napi, skb); +#endif +#else + netif_rx(skb); +#endif +} + +static int +rtl8127_check_rx_desc_error(struct net_device *dev, + struct rtl8127_private *tp, + u32 status) +{ + int ret = 0; + + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + if (unlikely(status & RxRES_V3)) { + if (status & (RxRWT_V3 | RxRUNT_V3)) + RTLDEV->stats.rx_length_errors++; + if (status & RxCRC_V3) + RTLDEV->stats.rx_crc_errors++; + + ret = -1; + } + break; + case RX_DESC_RING_TYPE_4: + if (unlikely(status & RxRES_V4)) { + if (status & RxRUNT_V4) + RTLDEV->stats.rx_length_errors++; + if (status & RxCRC_V4) + RTLDEV->stats.rx_crc_errors++; + + ret = -1; + } + break; + default: + if (unlikely(status & RxRES)) { + if (status & (RxRWT | RxRUNT)) + RTLDEV->stats.rx_length_errors++; + if (status & RxCRC) + RTLDEV->stats.rx_crc_errors++; + + ret = -1; + } + break; + } + + return ret; +} + +#ifdef ENABLE_PAGE_REUSE + +static inline bool +rtl8127_reuse_rx_ok(struct page *page) +{ + /* avoid re-using remote pages */ + if (!dev_page_is_reusable(page)) { + //printk(KERN_INFO "r8127 page pfmemalloc, can't reuse!\n"); + return false; + } + /* if we are only owner of page we can reuse it */ + if (unlikely(page_ref_count(page) != 1)) { + //printk(KERN_INFO "r8127 page refcnt %d, can't reuse!\n", page_ref_count(page)); + return false; + } + + return true; +} + +static void +rtl8127_reuse_rx_buffer(struct rtl8127_private *tp, struct rtl8127_rx_ring *ring, u32 cur_rx, struct rtl8127_rx_buffer *rxb) +{ + struct page *page = rxb->page; + + u32 dirty_rx = ring->dirty_rx; + u32 entry = dirty_rx % ring->num_rx_desc; + struct rtl8127_rx_buffer *nrxb = &ring->rx_buffer[entry]; + + u32 noffset; + + //the page gonna be shared by us and kernel, keep page ref = 2 + page_ref_inc(page); + + //flip the buffer in page to use next + noffset = rxb->page_offset ^ (tp->rx_buf_page_size / 2); //one page, two buffer, ping-pong + + nrxb->dma = rxb->dma; + nrxb->page_offset = noffset; + nrxb->data = rxb->data; + + if (cur_rx != dirty_rx) { + //move the buffer to other slot + nrxb->page = page; + rxb->page = NULL; + } +} + +static void rtl8127_put_rx_buffer(struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + u32 cur_rx, + struct rtl8127_rx_buffer *rxb) +{ + struct rtl8127_rx_buffer *nrxb; + struct page *page = rxb->page; + u32 entry; + + entry = ring->dirty_rx % ring->num_rx_desc; + nrxb = &ring->rx_buffer[entry]; + if (likely(rtl8127_reuse_rx_ok(page))) { + /* hand second half of page back to the ring */ + rtl8127_reuse_rx_buffer(tp, ring, cur_rx, rxb); + } else { + tp->page_reuse_fail_cnt++; + + dma_unmap_page_attrs(&tp->pci_dev->dev, rxb->dma, + tp->rx_buf_page_size, + DMA_FROM_DEVICE, + (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)); + //the page ref is kept 1, uniquely owned by kernel now + rxb->page = NULL; + + return; + } + + dma_sync_single_range_for_device(tp_to_dev(tp), + nrxb->dma, + nrxb->page_offset, + tp->rx_buf_sz, + DMA_FROM_DEVICE); + + rtl8127_map_to_asic(tp, ring, + rtl8127_get_rxdesc(tp, ring->RxDescArray, entry), + nrxb->dma + nrxb->page_offset, + tp->rx_buf_sz, entry); + + ring->dirty_rx++; +} + +#endif //ENABLE_PAGE_REUSE + +static int +rtl8127_rx_interrupt(struct net_device *dev, + struct rtl8127_private *tp, + struct rtl8127_rx_ring *ring, + napi_budget budget) +{ + unsigned int cur_rx, rx_left; + unsigned int delta, count = 0; + unsigned int entry; + struct RxDesc *desc; + struct sk_buff *skb; + u32 status; + u32 rx_quota; + u32 ring_index = ring->index; +#ifdef ENABLE_PAGE_REUSE + struct rtl8127_rx_buffer *rxb; +#else //ENABLE_PAGE_REUSE + u64 rx_buf_phy_addr; +#endif //ENABLE_PAGE_REUSE + unsigned int total_rx_multicast_packets = 0; + unsigned int total_rx_bytes = 0, total_rx_packets = 0; + + assert(dev != NULL); + assert(tp != NULL); + + if (ring->RxDescArray == NULL) + goto rx_out; + + rx_quota = RTL_RX_QUOTA(budget); + cur_rx = ring->cur_rx; + rx_left = ring->num_rx_desc + ring->dirty_rx - cur_rx; + rx_left = rtl8127_rx_quota(rx_left, (u32)rx_quota); + + for (; rx_left > 0; rx_left--, cur_rx++) { +#ifndef ENABLE_PAGE_REUSE + const void *rx_buf; +#endif //!ENABLE_PAGE_REUSE + u32 pkt_size; + + entry = cur_rx % ring->num_rx_desc; + desc = rtl8127_get_rxdesc(tp, ring->RxDescArray, entry); + status = le32_to_cpu(rtl8127_rx_desc_opts1(tp, desc)); + if (status & DescOwn) { + RTL_R8(tp, tp->imr_reg[0]); + status = le32_to_cpu(rtl8127_rx_desc_opts1(tp, desc)); + if (status & DescOwn) + break; + } + + rmb(); + + if (unlikely(rtl8127_check_rx_desc_error(dev, tp, status) < 0)) { + if (netif_msg_rx_err(tp)) { + printk(KERN_INFO + "%s: Rx ERROR. status = %08x\n", + dev->name, status); + } + + RTLDEV->stats.rx_errors++; + + if (!(dev->features & NETIF_F_RXALL)) + goto release_descriptor; + } + pkt_size = status & 0x00003fff; + if (likely(!(dev->features & NETIF_F_RXFCS))) { +#ifdef ENABLE_RX_PACKET_FRAGMENT + if (rtl8127_is_non_eop(tp, status) && + pkt_size == tp->rx_buf_sz) { + struct RxDesc *desc_next; + unsigned int entry_next; + int pkt_size_next; + u32 status_next; + + entry_next = (cur_rx + 1) % ring->num_rx_desc; + desc_next = rtl8127_get_rxdesc(tp, ring->RxDescArray, entry_next); + status_next = le32_to_cpu(rtl8127_rx_desc_opts1(tp, desc_next)); + if (!(status_next & DescOwn)) { + pkt_size_next = status_next & 0x00003fff; + if (pkt_size_next < ETH_FCS_LEN) + pkt_size -= (ETH_FCS_LEN - pkt_size_next); + } + } +#endif //ENABLE_RX_PACKET_FRAGMENT + if (!rtl8127_is_non_eop(tp, status)) { + if (pkt_size < ETH_FCS_LEN) { +#ifdef ENABLE_RX_PACKET_FRAGMENT + pkt_size = 0; +#else + goto drop_packet; +#endif //ENABLE_RX_PACKET_FRAGMENT + } else + pkt_size -= ETH_FCS_LEN; + } + } + + if (unlikely(pkt_size > tp->rx_buf_sz)) + goto drop_packet; + +#if !defined(ENABLE_RX_PACKET_FRAGMENT) || !defined(ENABLE_PAGE_REUSE) + /* + * The driver does not support incoming fragmented + * frames. They are seen as a symptom of over-mtu + * sized frames. + */ + if (unlikely(rtl8127_fragmented_frame(tp, status))) + goto drop_packet; +#endif //!ENABLE_RX_PACKET_FRAGMENT || !ENABLE_PAGE_REUSE + +#ifdef ENABLE_PAGE_REUSE + rxb = &ring->rx_buffer[entry]; + skb = rxb->skb; + rxb->skb = NULL; + if (!skb) { + skb = RTL_BUILD_SKB_INTR(rxb->data + rxb->page_offset - ring->rx_offset, tp->rx_buf_page_size / 2); + if (!skb) { + //netdev_err(tp->dev, "Failed to allocate RX skb!\n"); + goto drop_packet; + } + + skb->dev = dev; + if (!R8127_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8127_RX_ALIGN); + skb_put(skb, pkt_size); +#ifdef ENABLE_RSS_SUPPORT + rtl8127_rx_hash(tp, desc, skb); +#endif + rtl8127_rx_csum(tp, skb, desc); + } else + skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rxb->page, + rxb->page_offset, pkt_size, tp->rx_buf_page_size / 2); + //recycle desc + rtl8127_put_rx_buffer(tp, ring, cur_rx, rxb); + + dma_sync_single_range_for_cpu(tp_to_dev(tp), + rxb->dma, + rxb->page_offset, + tp->rx_buf_sz, + DMA_FROM_DEVICE); +#else //ENABLE_PAGE_REUSE + skb = RTL_ALLOC_SKB_INTR(&tp->r8127napi[ring->index].napi, pkt_size + R8127_RX_ALIGN); + if (!skb) { + //netdev_err(tp->dev, "Failed to allocate RX skb!\n"); + goto drop_packet; + } + + skb->dev = dev; + if (!R8127_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8127_RX_ALIGN); + skb_put(skb, pkt_size); + + rx_buf_phy_addr = ring->RxDescPhyAddr[entry]; + dma_sync_single_for_cpu(tp_to_dev(tp), + rx_buf_phy_addr, tp->rx_buf_sz, + DMA_FROM_DEVICE); + rx_buf = ring->Rx_skbuff[entry]->data; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) + prefetch(rx_buf - R8127_RX_ALIGN); +#endif + eth_copy_and_sum(skb, rx_buf, pkt_size, 0); + + dma_sync_single_for_device(tp_to_dev(tp), rx_buf_phy_addr, + tp->rx_buf_sz, DMA_FROM_DEVICE); +#endif //ENABLE_PAGE_REUSE + +#ifdef ENABLE_PTP_SUPPORT + if (tp->flags & RTL_FLAG_RX_HWTSTAMP_ENABLED) + rtl8127_rx_ptp_timestamp(tp, skb); +#endif // ENABLE_PTP_SUPPORT + +#ifdef ENABLE_RX_PACKET_FRAGMENT + if (rtl8127_is_non_eop(tp, status)) { + unsigned int entry_next; + entry_next = (entry + 1) % ring->num_rx_desc; + rxb = &ring->rx_buffer[entry_next]; + rxb->skb = skb; + continue; + } +#endif //ENABLE_RX_PACKET_FRAGMENT + +#ifndef ENABLE_PAGE_REUSE +#ifdef ENABLE_RSS_SUPPORT + rtl8127_rx_hash(tp, desc, skb); +#endif + rtl8127_rx_csum(tp, skb, desc); +#endif /* !ENABLE_PAGE_REUSE */ + + skb->protocol = eth_type_trans(skb, dev); + + total_rx_bytes += skb->len; + + if (skb->pkt_type == PACKET_MULTICAST) + total_rx_multicast_packets++; + + if (rtl8127_rx_vlan_skb(tp, desc, skb) < 0) + rtl8127_rx_skb(tp, skb, ring_index); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,11,0) + dev->last_rx = jiffies; +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,11,0) + total_rx_packets++; + +#ifdef ENABLE_PAGE_REUSE + rxb->skb = NULL; + continue; +#endif + +release_descriptor: + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + case RX_DESC_RING_TYPE_4: + rtl8127_set_desc_dma_addr(tp, desc, + ring->RxDescPhyAddr[entry]); + wmb(); + break; + } + rtl8127_mark_to_asic(tp, desc, tp->rx_buf_sz); + continue; +drop_packet: + RTLDEV->stats.rx_dropped++; + RTLDEV->stats.rx_length_errors++; + goto release_descriptor; + } + + count = cur_rx - ring->cur_rx; + ring->cur_rx = cur_rx; + + delta = rtl8127_rx_fill(tp, ring, dev, ring->dirty_rx, ring->cur_rx, 1); + if (!delta && count && netif_msg_intr(tp)) + printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); + ring->dirty_rx += delta; + + RTLDEV->stats.rx_bytes += total_rx_bytes; + RTLDEV->stats.rx_packets += total_rx_packets; + RTLDEV->stats.multicast += total_rx_multicast_packets; + + /* + * FIXME: until there is periodic timer to try and refill the ring, + * a temporary shortage may definitely kill the Rx process. + * - disable the asic to try and avoid an overflow and kick it again + * after refill ? + * - how do others driver handle this condition (Uh oh...). + */ + if ((ring->dirty_rx + ring->num_rx_desc == ring->cur_rx) && netif_msg_intr(tp)) + printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); + +rx_out: + return total_rx_packets; +} + +static bool +rtl8127_linkchg_interrupt(struct rtl8127_private *tp, u32 status) +{ + switch (tp->HwCurrIsrVer) { + case 2: + case 3: + return status & ISRIMR_V2_LINKCHG; + case 4: + return status & ISRIMR_V4_LINKCHG; + case 5: + return status & ISRIMR_V5_LINKCHG; + case 6: + return status & ISRIMR_V6_LINKCHG; + default: + return status & LinkChg; + } +} + +static u32 +rtl8127_get_linkchg_message_id(struct rtl8127_private *tp) +{ + switch (tp->HwCurrIsrVer) { + case 4: + case 6: + return 29; + case 5: + return 18; + default: + return 21; + } +} + +/* + *The interrupt handler does all of the Rx thread work and cleans up after + *the Tx thread. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +static irqreturn_t rtl8127_interrupt(int irq, void *dev_instance, struct pt_regs *regs) +#else +static irqreturn_t rtl8127_interrupt(int irq, void *dev_instance) +#endif +{ + struct r8127_napi *r8127napi = dev_instance; + struct rtl8127_private *tp = r8127napi->priv; + struct net_device *dev = tp->dev; + u32 status; + int handled = 0; + + do { + status = RTL_R32(tp, tp->isr_reg[0]); + + if (!(tp->features & (RTL_FEATURE_MSI | RTL_FEATURE_MSIX))) { + /* hotplug/major error/no more work/shared irq */ + if (!status) + break; + + if (status == 0xFFFFFFFF) + break; + + if (!(status & (tp->intr_mask | tp->timer_intr_mask))) + break; + } + + handled = 1; + +#if defined(RTL_USE_NEW_INTR_API) + if (!tp->irq_tbl[0].requested) + break; +#endif + rtl8127_disable_hw_interrupt(tp); + + RTL_W32(tp, tp->isr_reg[0], status&~RxFIFOOver); + + if (rtl8127_linkchg_interrupt(tp, status)) + rtl8127_schedule_linkchg_work(tp); + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) { + if (HW_DASH_SUPPORT_TYPE_3(tp)) { + u8 DashIntType2Status; + + if (status & ISRIMR_DASH_INTR_CMAC_RESET) + tp->CmacResetIntr = TRUE; + + DashIntType2Status = RTL_CMAC_R8(tp, CMAC_IBISR0); + if (DashIntType2Status & ISRIMR_DASH_TYPE2_ROK) + tp->RcvFwDashOkEvt = TRUE; + if (DashIntType2Status & ISRIMR_DASH_TYPE2_TOK) + tp->SendFwHostOkEvt = TRUE; + if (DashIntType2Status & ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE) + tp->DashFwDisableRx = TRUE; + + RTL_CMAC_W8(tp, CMAC_IBISR0, DashIntType2Status); + } + } +#endif + +#ifdef CONFIG_R8127_NAPI + if (status & tp->intr_mask || tp->keep_intr_cnt-- > 0) { + if (status & tp->intr_mask) + tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; + + if (likely(RTL_NETIF_RX_SCHEDULE_PREP(dev, &tp->r8127napi[0].napi))) + __RTL_NETIF_RX_SCHEDULE(dev, &tp->r8127napi[0].napi); + else if (netif_msg_intr(tp)) + printk(KERN_INFO "%s: interrupt %04x in poll\n", + dev->name, status); + } else { + tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; + rtl8127_switch_to_hw_interrupt(tp); + } +#else + if (status & tp->intr_mask || tp->keep_intr_cnt-- > 0) { + u32 budget = ~(u32)0; + int i; + + if (status & tp->intr_mask) + tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; + + for (i = 0; i < tp->num_tx_rings; i++) + rtl8127_tx_interrupt(&tp->tx_ring[i], ~(u32)0); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + rtl8127_rx_interrupt(dev, tp, &tp->rx_ring[0], &budget); +#else + rtl8127_rx_interrupt(dev, tp, &tp->rx_ring[0], budget); +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) { + struct net_device *dev = tp->dev; + + HandleDashInterrupt(dev); + } +#endif + + rtl8127_switch_to_timer_interrupt(tp); + } else { + tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT; + rtl8127_switch_to_hw_interrupt(tp); + } +#endif + } while (false); + + return IRQ_RETVAL(handled); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +static irqreturn_t rtl8127_interrupt_msix(int irq, void *dev_instance, struct pt_regs *regs) +#else +static irqreturn_t rtl8127_interrupt_msix(int irq, void *dev_instance) +#endif +{ + struct r8127_napi *r8127napi = dev_instance; + struct rtl8127_private *tp = r8127napi->priv; + struct net_device *dev = tp->dev; + int message_id = r8127napi->index; +#ifndef CONFIG_R8127_NAPI + u32 budget = ~(u32)0; +#endif + + do { +#if defined(RTL_USE_NEW_INTR_API) + if (!tp->irq_tbl[message_id].requested) + break; +#endif + //link change + if (message_id == rtl8127_get_linkchg_message_id(tp)) { + rtl8127_disable_hw_interrupt_v2(tp, message_id); + rtl8127_clear_hw_isr_v2(tp, message_id); + rtl8127_schedule_linkchg_work(tp); + break; + } + +#ifdef CONFIG_R8127_NAPI + if (likely(RTL_NETIF_RX_SCHEDULE_PREP(dev, &r8127napi->napi))) { + rtl8127_disable_hw_interrupt_v2(tp, message_id); + __RTL_NETIF_RX_SCHEDULE(dev, &r8127napi->napi); + } else if (netif_msg_intr(tp)) + printk(KERN_INFO "%s: interrupt message id %d in poll_msix\n", + dev->name, message_id); + rtl8127_clear_hw_isr_v2(tp, message_id); +#else + rtl8127_disable_hw_interrupt_v2(tp, message_id); + + rtl8127_clear_hw_isr_v2(tp, message_id); + + rtl8127_tx_interrupt_with_vector(tp, message_id, ~(u32)0); + + if (message_id < tp->num_rx_rings) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + rtl8127_rx_interrupt(dev, tp, &tp->rx_ring[message_id], &budget); +#else + rtl8127_rx_interrupt(dev, tp, &tp->rx_ring[message_id], budget); +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + } + + rtl8127_enable_hw_interrupt_v2(tp, message_id); +#endif + + } while (false); + + return IRQ_HANDLED; +} + +static void rtl8127_down(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + //rtl8127_delete_esd_timer(dev, &tp->esd_timer); + + //rtl8127_delete_link_timer(dev, &tp->link_timer); + + netif_carrier_off(dev); + + netif_tx_disable(dev); + + _rtl8127_wait_for_quiescence(dev); + + rtl8127_hw_reset(dev); + + rtl8127_tx_clear(tp); + + rtl8127_rx_clear(tp); +} + +static int rtl8127_resource_freed(struct rtl8127_private *tp) +{ + int i; + + for (i = 0; i < tp->num_tx_rings; i++) + if (tp->tx_ring[i].TxDescArray) + return 0; + + for (i = 0; i < tp->num_rx_rings; i++) + if (tp->rx_ring[i].RxDescArray) + return 0; + + return 1; +} + +int rtl8127_close(struct net_device *dev) +{ + struct rtl8127_private *tp = netdev_priv(dev); + + if (!rtl8127_resource_freed(tp)) { + set_bit(R8127_FLAG_DOWN, tp->task_flags); + + rtl8127_down(dev); + + pci_clear_master(tp->pci_dev); + +#ifdef ENABLE_PTP_SUPPORT + rtl8127_ptp_stop(tp); +#endif + rtl8127_hw_d3_para(dev); + + rtl8127_powerdown_pll(dev, 0); + + rtl8127_free_irq(tp); + + rtl8127_free_alloc_resources(tp); + } else { + rtl8127_hw_d3_para(dev); + + rtl8127_powerdown_pll(dev, 0); + } + + return 0; +} + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11) +static void rtl8127_shutdown(struct pci_dev *pdev) +{ + struct net_device *dev = pci_get_drvdata(pdev); + struct rtl8127_private *tp = netdev_priv(dev); + + rtnl_lock(); + + if (HW_DASH_SUPPORT_DASH(tp)) + rtl8127_driver_stop(tp); + + rtl8127_disable_pci_offset_180(tp); + + if (s5_keep_curr_mac == 0 && tp->random_mac == 0) + rtl8127_rar_set(tp, tp->org_mac_addr); + + if (s5wol == 0) + tp->wol_enabled = WOL_DISABLED; + + rtl8127_close(dev); + rtl8127_disable_msi(pdev, tp); + + rtnl_unlock(); + + if (system_state == SYSTEM_POWER_OFF) { + pci_clear_master(tp->pci_dev); + pci_wake_from_d3(pdev, tp->wol_enabled); + pci_set_power_state(pdev, PCI_D3hot); + } +} +#endif + +#ifdef CONFIG_PM + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static int +rtl8127_suspend(struct pci_dev *pdev, u32 state) +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +static int +rtl8127_suspend(struct device *device) +#else +static int +rtl8127_suspend(struct pci_dev *pdev, pm_message_t state) +#endif +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) + struct pci_dev *pdev = to_pci_dev(device); + struct net_device *dev = pci_get_drvdata(pdev); +#else + struct net_device *dev = pci_get_drvdata(pdev); +#endif + struct rtl8127_private *tp = netdev_priv(dev); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) + u32 pci_pm_state = pci_choose_state(pdev, state); +#endif + rtnl_lock(); + + if (!netif_running(dev)) + goto out; + + set_bit(R8127_FLAG_DOWN, tp->task_flags); + + netif_carrier_off(dev); + + netif_tx_disable(dev); + + netif_device_detach(dev); + +#ifdef ENABLE_PTP_SUPPORT + rtl8127_ptp_suspend(tp); +#endif + rtl8127_hw_reset(dev); + + pci_clear_master(pdev); + + rtl8127_hw_d3_para(dev); + + rtl8127_powerdown_pll(dev, 1); +out: + if (HW_DASH_SUPPORT_DASH(tp)) + rtl8127_driver_stop(tp); + + rtnl_unlock(); + + pci_disable_device(pdev); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) + pci_save_state(pdev, &pci_pm_state); +#else + pci_save_state(pdev); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) + pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled); +#endif + + pci_prepare_to_sleep(pdev); + + return 0; +} + +static int +rtl8127_hw_d3_not_power_off(struct net_device *dev) +{ + return rtl8127_check_hw_phy_mcu_code_ver(dev); +} + +static int rtl8127_wait_phy_nway_complete_sleep(struct rtl8127_private *tp) +{ + int i, val; + + for (i = 0; i < 30; i++) { + val = rtl8127_mdio_read(tp, MII_BMSR) & BMSR_ANEGCOMPLETE; + if (val) + return 0; + + fsleep(100000); + } + + return -1; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) +static int +rtl8127_resume(struct pci_dev *pdev) +#else +static int +rtl8127_resume(struct device *device) +#endif +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) + struct pci_dev *pdev = to_pci_dev(device); + struct net_device *dev = pci_get_drvdata(pdev); +#else + struct net_device *dev = pci_get_drvdata(pdev); +#endif + struct rtl8127_private *tp = netdev_priv(dev); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) + u32 pci_pm_state = PCI_D0; +#endif + u32 err; + + rtnl_lock(); + + err = pci_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n"); + goto out_unlock; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) + pci_restore_state(pdev, &pci_pm_state); +#else + pci_restore_state(pdev); +#endif + pci_enable_wake(pdev, PCI_D0, 0); + + /* restore last modified mac address */ + rtl8127_rar_set(tp, dev->dev_addr); + + tp->resume_not_chg_speed = 0; + if (tp->check_keep_link_speed && + //tp->link_ok(dev) && + rtl8127_hw_d3_not_power_off(dev) && + rtl8127_wait_phy_nway_complete_sleep(tp) == 0) + tp->resume_not_chg_speed = 1; + + if (!netif_running(dev)) + goto out_unlock; + + pci_set_master(pdev); + + rtl8127_exit_oob(dev); + + rtl8127_up(dev); + + clear_bit(R8127_FLAG_DOWN, tp->task_flags); + + rtl8127_schedule_reset_work(tp); + + rtl8127_schedule_esd_work(tp); + + //mod_timer(&tp->esd_timer, jiffies + RTL8127_ESD_TIMEOUT); + //mod_timer(&tp->link_timer, jiffies + RTL8127_LINK_TIMEOUT); +out_unlock: + netif_device_attach(dev); + + rtnl_unlock(); + + return err; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) + +static struct dev_pm_ops rtl8127_pm_ops = { + .suspend = rtl8127_suspend, + .resume = rtl8127_resume, + .freeze = rtl8127_suspend, + .thaw = rtl8127_resume, + .poweroff = rtl8127_suspend, + .restore = rtl8127_resume, +}; + +#define RTL8127_PM_OPS (&rtl8127_pm_ops) + +#endif + +#else /* !CONFIG_PM */ + +#define RTL8127_PM_OPS NULL + +#endif /* CONFIG_PM */ + +static struct pci_driver rtl8127_pci_driver = { + .name = MODULENAME, + .id_table = rtl8127_pci_tbl, + .probe = rtl8127_init_one, + .remove = __devexit_p(rtl8127_remove_one), +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,11) + .shutdown = rtl8127_shutdown, +#endif +#ifdef CONFIG_PM +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) + .suspend = rtl8127_suspend, + .resume = rtl8127_resume, +#else + .driver.pm = RTL8127_PM_OPS, +#endif +#endif +}; + +static int __init +rtl8127_init_module(void) +{ + int ret = 0; +#ifdef ENABLE_R8127_PROCFS + rtl8127_proc_module_init(); +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + + ret = pci_register_driver(&rtl8127_pci_driver); +#else + ret = pci_module_init(&rtl8127_pci_driver); +#endif + + return ret; +} + +static void __exit +rtl8127_cleanup_module(void) +{ + pci_unregister_driver(&rtl8127_pci_driver); + +#ifdef ENABLE_R8127_PROCFS + if (rtl8127_proc) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + remove_proc_subtree(MODULENAME, init_net.proc_net); +#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) + remove_proc_entry(MODULENAME, init_net.proc_net); +#else + remove_proc_entry(MODULENAME, proc_net); +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + rtl8127_proc = NULL; + } +#endif +} + +module_init(rtl8127_init_module); +module_exit(rtl8127_cleanup_module); --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/r8127_realwow.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/r8127_realwow.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#ifndef _LINUX_R8127_REALWOW_H +#define _LINUX_R8127_REALWOW_H + +#define SIOCDEVPRIVATE_RTLREALWOW SIOCDEVPRIVATE+3 + +#define MAX_RealWoW_KCP_SIZE (100) +#define MAX_RealWoW_Payload (64) + +#define KA_TX_PACKET_SIZE (100) +#define KA_WAKEUP_PATTERN_SIZE (120) + +//HwSuppKeepAliveOffloadVer +#define HW_SUPPORT_KCP_OFFLOAD(_M) ((_M)->HwSuppKCPOffloadVer > 0) + +enum rtl_realwow_cmd { + + RTL_REALWOW_SET_KCP_DISABLE=0, + RTL_REALWOW_SET_KCP_INFO, + RTL_REALWOW_SET_KCP_CONTENT, + + RTL_REALWOW_SET_KCP_ACKPKTINFO, + RTL_REALWOW_SET_KCP_WPINFO, + RTL_REALWOW_SET_KCPDHCP_TIMEOUT, + + RTLT_REALWOW_COMMAND_INVALID +}; + +struct rtl_realwow_ioctl_struct { + __u32 cmd; + __u32 offset; + __u32 len; + union { + __u32 data; + void *data_buffer; + }; +}; + +typedef struct _MP_KCPInfo { + u8 DIPv4[4]; + u8 MacID[6]; + u16 UdpPort[2]; + u8 PKTLEN[2]; + + u16 ackLostCnt; + u8 KCP_WakePattern[MAX_RealWoW_Payload]; + u8 KCP_AckPacket[MAX_RealWoW_Payload]; + u32 KCP_interval; + u8 KCP_WakePattern_Len; + u8 KCP_AckPacket_Len; + u8 KCP_TxPacket[2][KA_TX_PACKET_SIZE]; +} MP_KCP_INFO, *PMP_KCP_INFO; + +typedef struct _KCPInfo { + u32 nId; // = id + u8 DIPv4[4]; + u8 MacID[6]; + u16 UdpPort; + u16 PKTLEN; +} KCPInfo, *PKCPInfo; + +typedef struct _KCPContent { + u32 id; // = id + u32 mSec; // = msec + u32 size; // =size + u8 bPacket[MAX_RealWoW_KCP_SIZE]; // put packet here +} KCPContent, *PKCPContent; + +typedef struct _RealWoWAckPktInfo { + u16 ackLostCnt; + u16 patterntSize; + u8 pattern[MAX_RealWoW_Payload]; +} RealWoWAckPktInfo,*PRealWoWAckPktInfo; + +typedef struct _RealWoWWPInfo { + u16 patterntSize; + u8 pattern[MAX_RealWoW_Payload]; +} RealWoWWPInfo,*PRealWoWWPInfo; + +int rtl8127_realwow_ioctl(struct net_device *dev, struct ifreq *ifr); +void rtl8127_realwow_hw_init(struct net_device *dev); +void rtl8127_get_realwow_hw_version(struct net_device *dev); +void rtl8127_set_realwow_d3_para(struct net_device *dev); + +#endif /* _LINUX_R8127_REALWOW_H */ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/r8127_rss.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/r8127_rss.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#ifndef _LINUX_R8127_RSS_H +#define _LINUX_R8127_RSS_H + +#include +#include + +#define RTL8127_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ +#define RTL8127_MAX_INDIRECTION_TABLE_ENTRIES 128 + +enum rtl8127_rss_flag { + RTL_8125_RSS_FLAG_HASH_UDP_IPV4 = (1 << 0), + RTL_8125_RSS_FLAG_HASH_UDP_IPV6 = (1 << 1), +}; + +struct rtl8127_private; +struct RxDesc; + +int rtl8127_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, + u32 *rule_locs); +int rtl8127_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); +u32 rtl8127_get_rxfh_key_size(struct net_device *netdev); +u32 rtl8127_rss_indir_size(struct net_device *netdev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,8,0) +int rtl8127_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh); +int rtl8127_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh, + struct netlink_ext_ack *extack); +#else +int rtl8127_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, + u8 *hfunc); +int rtl8127_set_rxfh(struct net_device *netdev, const u32 *indir, + const u8 *key, const u8 hfunc); +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(6,8,0) */ +void rtl8127_rx_hash(struct rtl8127_private *tp, + struct RxDesc *desc, + struct sk_buff *skb); +void _rtl8127_config_rss(struct rtl8127_private *tp); +void rtl8127_config_rss(struct rtl8127_private *tp); +void rtl8127_init_rss(struct rtl8127_private *tp); +u32 rtl8127_rss_indir_tbl_entries(struct rtl8127_private *tp); +void rtl8127_disable_rss(struct rtl8127_private *tp); + +#endif /* _LINUX_R8127_RSS_H */ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/rtl_eeprom.c +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/rtl_eeprom.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include + +#include "r8127.h" +#include "rtl_eeprom.h" + +//------------------------------------------------------------------- +//rtl8127_eeprom_type(): +// tell the eeprom type +//return value: +// 0: the eeprom type is 93C46 +// 1: the eeprom type is 93C56 or 93C66 +//------------------------------------------------------------------- +void rtl8127_eeprom_type(struct rtl8127_private *tp) +{ + u16 magic = 0; + + if (tp->mcfg == CFG_METHOD_DEFAULT) + goto out_no_eeprom; + + if(RTL_R8(tp, 0xD2)&0x04) { + //not support + //tp->eeprom_type = EEPROM_TWSI; + //tp->eeprom_len = 256; + goto out_no_eeprom; + } else if(RTL_R32(tp, RxConfig) & RxCfg_9356SEL) { + tp->eeprom_type = EEPROM_TYPE_93C56; + tp->eeprom_len = 256; + } else { + tp->eeprom_type = EEPROM_TYPE_93C46; + tp->eeprom_len = 128; + } + + magic = rtl8127_eeprom_read_sc(tp, 0); + +out_no_eeprom: + if ((magic != 0x8129) && (magic != 0x8128)) { + tp->eeprom_type = EEPROM_TYPE_NONE; + tp->eeprom_len = 0; + } +} + +void rtl8127_eeprom_cleanup(struct rtl8127_private *tp) +{ + u8 x; + + x = RTL_R8(tp, Cfg9346); + x &= ~(Cfg9346_EEDI | Cfg9346_EECS); + + RTL_W8(tp, Cfg9346, x); + + rtl8127_raise_clock(tp, &x); + rtl8127_lower_clock(tp, &x); +} + +static int rtl8127_eeprom_cmd_done(struct rtl8127_private *tp) +{ + u8 x; + int i; + + rtl8127_stand_by(tp); + + for (i = 0; i < 50000; i++) { + x = RTL_R8(tp, Cfg9346); + + if (x & Cfg9346_EEDO) { + fsleep(RTL_CLOCK_RATE * 2 * 3); + return 0; + } + fsleep(1); + } + + return -1; +} + +//------------------------------------------------------------------- +//rtl8127_eeprom_read_sc(): +// read one word from eeprom +//------------------------------------------------------------------- +u16 rtl8127_eeprom_read_sc(struct rtl8127_private *tp, u16 reg) +{ + int addr_sz = 6; + u8 x; + u16 data; + + if(tp->eeprom_type == EEPROM_TYPE_NONE) + return -1; + + if (tp->eeprom_type==EEPROM_TYPE_93C46) + addr_sz = 6; + else if (tp->eeprom_type==EEPROM_TYPE_93C56) + addr_sz = 8; + + x = Cfg9346_EEM1 | Cfg9346_EECS; + RTL_W8(tp, Cfg9346, x); + + rtl8127_shift_out_bits(tp, RTL_EEPROM_READ_OPCODE, 3); + rtl8127_shift_out_bits(tp, reg, addr_sz); + + data = rtl8127_shift_in_bits(tp); + + rtl8127_eeprom_cleanup(tp); + + RTL_W8(tp, Cfg9346, 0); + + return data; +} + +//------------------------------------------------------------------- +//rtl8127_eeprom_write_sc(): +// write one word to a specific address in the eeprom +//------------------------------------------------------------------- +void rtl8127_eeprom_write_sc(struct rtl8127_private *tp, u16 reg, u16 data) +{ + u8 x; + int addr_sz = 6; + int w_dummy_addr = 4; + + if(tp->eeprom_type == EEPROM_TYPE_NONE) + return; + + if (tp->eeprom_type==EEPROM_TYPE_93C46) { + addr_sz = 6; + w_dummy_addr = 4; + } else if (tp->eeprom_type==EEPROM_TYPE_93C56) { + addr_sz = 8; + w_dummy_addr = 6; + } + + x = Cfg9346_EEM1 | Cfg9346_EECS; + RTL_W8(tp, Cfg9346, x); + + rtl8127_shift_out_bits(tp, RTL_EEPROM_EWEN_OPCODE, 5); + rtl8127_shift_out_bits(tp, reg, w_dummy_addr); + rtl8127_stand_by(tp); + + rtl8127_shift_out_bits(tp, RTL_EEPROM_ERASE_OPCODE, 3); + rtl8127_shift_out_bits(tp, reg, addr_sz); + if (rtl8127_eeprom_cmd_done(tp) < 0) + return; + rtl8127_stand_by(tp); + + rtl8127_shift_out_bits(tp, RTL_EEPROM_WRITE_OPCODE, 3); + rtl8127_shift_out_bits(tp, reg, addr_sz); + rtl8127_shift_out_bits(tp, data, 16); + if (rtl8127_eeprom_cmd_done(tp) < 0) + return; + rtl8127_stand_by(tp); + + rtl8127_shift_out_bits(tp, RTL_EEPROM_EWDS_OPCODE, 5); + rtl8127_shift_out_bits(tp, reg, w_dummy_addr); + + rtl8127_eeprom_cleanup(tp); + RTL_W8(tp, Cfg9346, 0); +} + +void rtl8127_raise_clock(struct rtl8127_private *tp, u8 *x) +{ + *x = *x | Cfg9346_EESK; + RTL_W8(tp, Cfg9346, *x); + fsleep(RTL_CLOCK_RATE); +} + +void rtl8127_lower_clock(struct rtl8127_private *tp, u8 *x) +{ + + *x = *x & ~Cfg9346_EESK; + RTL_W8(tp, Cfg9346, *x); + fsleep(RTL_CLOCK_RATE); +} + +void rtl8127_shift_out_bits(struct rtl8127_private *tp, int data, int count) +{ + u8 x; + int mask; + + mask = 0x01 << (count - 1); + x = RTL_R8(tp, Cfg9346); + x &= ~(Cfg9346_EEDI | Cfg9346_EEDO); + + do { + if (data & mask) + x |= Cfg9346_EEDI; + else + x &= ~Cfg9346_EEDI; + + RTL_W8(tp, Cfg9346, x); + fsleep(RTL_CLOCK_RATE); + rtl8127_raise_clock(tp, &x); + rtl8127_lower_clock(tp, &x); + mask = mask >> 1; + } while(mask); + + x &= ~Cfg9346_EEDI; + RTL_W8(tp, Cfg9346, x); +} + +u16 rtl8127_shift_in_bits(struct rtl8127_private *tp) +{ + u8 x; + u16 d, i; + + x = RTL_R8(tp, Cfg9346); + x &= ~(Cfg9346_EEDI | Cfg9346_EEDO); + + d = 0; + + for (i = 0; i < 16; i++) { + d = d << 1; + rtl8127_raise_clock(tp, &x); + + x = RTL_R8(tp, Cfg9346); + x &= ~Cfg9346_EEDI; + + if (x & Cfg9346_EEDO) + d |= 1; + + rtl8127_lower_clock(tp, &x); + } + + return d; +} + +void rtl8127_stand_by(struct rtl8127_private *tp) +{ + u8 x; + + x = RTL_R8(tp, Cfg9346); + x &= ~(Cfg9346_EECS | Cfg9346_EESK); + RTL_W8(tp, Cfg9346, x); + fsleep(RTL_CLOCK_RATE); + + x |= Cfg9346_EECS; + RTL_W8(tp, Cfg9346, x); +} + +void rtl8127_set_eeprom_sel_low(struct rtl8127_private *tp) +{ + RTL_W8(tp, Cfg9346, Cfg9346_EEM1); + RTL_W8(tp, Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK); + + fsleep(20); + + RTL_W8(tp, Cfg9346, Cfg9346_EEM1); +} --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/rtl_eeprom.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/rtl_eeprom.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#ifndef _LINUX_RTLEEPROM_H +#define _LINUX_RTLEEPROM_H + +//EEPROM opcodes +#define RTL_EEPROM_READ_OPCODE 06 +#define RTL_EEPROM_WRITE_OPCODE 05 +#define RTL_EEPROM_ERASE_OPCODE 07 +#define RTL_EEPROM_EWEN_OPCODE 19 +#define RTL_EEPROM_EWDS_OPCODE 16 + +#define RTL_CLOCK_RATE 3 + +void rtl8127_eeprom_type(struct rtl8127_private *tp); +void rtl8127_eeprom_cleanup(struct rtl8127_private *tp); +u16 rtl8127_eeprom_read_sc(struct rtl8127_private *tp, u16 reg); +void rtl8127_eeprom_write_sc(struct rtl8127_private *tp, u16 reg, u16 data); +void rtl8127_shift_out_bits(struct rtl8127_private *tp, int data, int count); +u16 rtl8127_shift_in_bits(struct rtl8127_private *tp); +void rtl8127_raise_clock(struct rtl8127_private *tp, u8 *x); +void rtl8127_lower_clock(struct rtl8127_private *tp, u8 *x); +void rtl8127_stand_by(struct rtl8127_private *tp); +void rtl8127_set_eeprom_sel_low(struct rtl8127_private *tp); + +#endif /* _LINUX_RTLEEPROM_H */ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/rtltool.c +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/rtltool.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "r8127.h" +#include "rtl_eeprom.h" +#include "rtltool.h" + +int rtl8127_tool_ioctl(struct rtl8127_private *tp, struct ifreq *ifr) +{ + struct rtltool_cmd my_cmd; + int ret; + + if (copy_from_user(&my_cmd, ifr->ifr_data, sizeof(my_cmd))) + return -EFAULT; + + ret = 0; + switch (my_cmd.cmd) { + case RTLTOOL_READ_MAC: + if ((my_cmd.offset + my_cmd.len) > pci_resource_len(tp->pci_dev, 2)) { + ret = -EINVAL; + break; + } + + if (my_cmd.len==1) + my_cmd.data = readb(tp->mmio_addr+my_cmd.offset); + else if (my_cmd.len==2) + my_cmd.data = readw(tp->mmio_addr+(my_cmd.offset&~1)); + else if (my_cmd.len==4) + my_cmd.data = readl(tp->mmio_addr+(my_cmd.offset&~3)); + else { + ret = -EOPNOTSUPP; + break; + } + + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + break; + + case RTLTOOL_WRITE_MAC: + if ((my_cmd.offset + my_cmd.len) > pci_resource_len(tp->pci_dev, 2)) { + ret = -EINVAL; + break; + } + + if (my_cmd.len==1) + writeb(my_cmd.data, tp->mmio_addr+my_cmd.offset); + else if (my_cmd.len==2) + writew(my_cmd.data, tp->mmio_addr+(my_cmd.offset&~1)); + else if (my_cmd.len==4) + writel(my_cmd.data, tp->mmio_addr+(my_cmd.offset&~3)); + else { + ret = -EOPNOTSUPP; + break; + } + + break; + + case RTLTOOL_READ_PHY: + my_cmd.data = rtl8127_mdio_prot_read(tp, my_cmd.offset); + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + + break; + + case RTLTOOL_WRITE_PHY: + rtl8127_mdio_prot_write(tp, my_cmd.offset, my_cmd.data); + break; + + case RTLTOOL_READ_EPHY: + my_cmd.data = rtl8127_ephy_read(tp, my_cmd.offset); + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + + break; + + case RTLTOOL_WRITE_EPHY: + rtl8127_ephy_write(tp, my_cmd.offset, my_cmd.data); + break; + + case RTLTOOL_READ_ERI: + my_cmd.data = 0; + if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) { + my_cmd.data = rtl8127_eri_read(tp, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC); + } else { + ret = -EOPNOTSUPP; + break; + } + + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + + break; + + case RTLTOOL_WRITE_ERI: + if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) { + rtl8127_eri_write(tp, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC); + } else { + ret = -EOPNOTSUPP; + break; + } + break; + + case RTLTOOL_READ_PCI: + my_cmd.data = 0; + if (my_cmd.len==1) + pci_read_config_byte(tp->pci_dev, my_cmd.offset, + (u8 *)&my_cmd.data); + else if (my_cmd.len==2) + pci_read_config_word(tp->pci_dev, my_cmd.offset, + (u16 *)&my_cmd.data); + else if (my_cmd.len==4) + pci_read_config_dword(tp->pci_dev, my_cmd.offset, + &my_cmd.data); + else { + ret = -EOPNOTSUPP; + break; + } + + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + break; + + case RTLTOOL_WRITE_PCI: + if (my_cmd.len==1) + pci_write_config_byte(tp->pci_dev, my_cmd.offset, + my_cmd.data); + else if (my_cmd.len==2) + pci_write_config_word(tp->pci_dev, my_cmd.offset, + my_cmd.data); + else if (my_cmd.len==4) + pci_write_config_dword(tp->pci_dev, my_cmd.offset, + my_cmd.data); + else { + ret = -EOPNOTSUPP; + break; + } + + break; + + case RTLTOOL_READ_EEPROM: + my_cmd.data = rtl8127_eeprom_read_sc(tp, my_cmd.offset); + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + + break; + + case RTLTOOL_WRITE_EEPROM: + rtl8127_eeprom_write_sc(tp, my_cmd.offset, my_cmd.data); + break; + + case RTL_READ_OOB_MAC: + rtl8127_oob_mutex_lock(tp); + my_cmd.data = rtl8127_ocp_read(tp, my_cmd.offset, 4); + rtl8127_oob_mutex_unlock(tp); + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + break; + + case RTL_WRITE_OOB_MAC: + if (my_cmd.len == 0 || my_cmd.len > 4) + return -EOPNOTSUPP; + + rtl8127_oob_mutex_lock(tp); + rtl8127_ocp_write(tp, my_cmd.offset, my_cmd.len, my_cmd.data); + rtl8127_oob_mutex_unlock(tp); + break; + + case RTL_ENABLE_PCI_DIAG: + tp->rtk_enable_diag = 1; + + dprintk("enable rtk diag\n"); + break; + + case RTL_DISABLE_PCI_DIAG: + tp->rtk_enable_diag = 0; + + dprintk("disable rtk diag\n"); + break; + + case RTL_READ_MAC_OCP: + if (my_cmd.offset % 2) + return -EOPNOTSUPP; + + my_cmd.data = rtl8127_mac_ocp_read(tp, my_cmd.offset); + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + break; + + case RTL_WRITE_MAC_OCP: + if ((my_cmd.offset % 2) || (my_cmd.len != 2)) + return -EOPNOTSUPP; + + rtl8127_mac_ocp_write(tp, my_cmd.offset, (u16)my_cmd.data); + break; + + case RTL_DIRECT_READ_PHY_OCP: + my_cmd.data = rtl8127_mdio_prot_direct_read_phy_ocp(tp, my_cmd.offset); + if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) { + ret = -EFAULT; + break; + } + + break; + + case RTL_DIRECT_WRITE_PHY_OCP: + rtl8127_mdio_prot_direct_write_phy_ocp(tp, my_cmd.offset, my_cmd.data); + break; + + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8127/rtltool.h +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8127/rtltool.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +################################################################################ +# +# r8127 is the Linux device driver released for Realtek 10 Gigabit Ethernet +# controllers with PCI-Express interface. +# +# Copyright(c) 2025 Realtek Semiconductor Corp. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program; if not, see . +# +# Author: +# Realtek NIC software team +# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan +# +################################################################################ +*/ + +/************************************************************************************ + * This product is covered by one or more of the following patents: + * US6,570,884, US6,115,776, and US6,327,625. + ***********************************************************************************/ + +#ifndef _LINUX_RTLTOOL_H +#define _LINUX_RTLTOOL_H + +#define SIOCRTLTOOL SIOCDEVPRIVATE+1 + +enum rtl_cmd { + RTLTOOL_READ_MAC=0, + RTLTOOL_WRITE_MAC, + RTLTOOL_READ_PHY, + RTLTOOL_WRITE_PHY, + RTLTOOL_READ_EPHY, + RTLTOOL_WRITE_EPHY, + RTLTOOL_READ_ERI, + RTLTOOL_WRITE_ERI, + RTLTOOL_READ_PCI, + RTLTOOL_WRITE_PCI, + RTLTOOL_READ_EEPROM, + RTLTOOL_WRITE_EEPROM, + + RTL_READ_OOB_MAC, + RTL_WRITE_OOB_MAC, + + RTL_ENABLE_PCI_DIAG, + RTL_DISABLE_PCI_DIAG, + + RTL_READ_MAC_OCP, + RTL_WRITE_MAC_OCP, + + RTL_DIRECT_READ_PHY_OCP, + RTL_DIRECT_WRITE_PHY_OCP, + + RTLTOOL_INVALID +}; + +struct rtltool_cmd { + __u32 cmd; + __u32 offset; + __u32 len; + __u32 data; +}; + +enum mode_access { + MODE_NONE=0, + MODE_READ, + MODE_WRITE +}; + +#ifdef __KERNEL__ +int rtl8127_tool_ioctl(struct rtl8127_private *tp, struct ifreq *ifr); +#endif + +#endif /* _LINUX_RTLTOOL_H */ --- linux-nvidia-7.0.0.orig/drivers/net/ethernet/realtek/r8169_main.c +++ linux-nvidia-7.0.0/drivers/net/ethernet/realtek/r8169_main.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1268,6 +1269,34 @@ return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); } +/* The quirk reflects RTL8116af SerDes status. */ +static int r8116af_mdio_read_quirk(struct rtl8169_private *tp, int reg) +{ + u8 phyStatus = RTL_R8(tp, PHYstatus); + + if (!(phyStatus & LinkStatus)) + return 0; + + /* BMSR */ + if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMSR) + return BMSR_ANEGCOMPLETE | BMSR_LSTATUS; + + /* PHYSR */ + if (tp->ocp_base == 0xa430 && reg == 0x12) + { if (phyStatus & _1000bpsF) + return 0x0028; + else if (phyStatus & _100bps) + return 0x0018; + } + + return 0; +} + +static int r8116af_mdio_read(struct rtl8169_private *tp, int reg) +{ + return r8168g_mdio_read(tp, reg) | r8116af_mdio_read_quirk(tp, reg); +} + static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) { if (reg == 0x1f) { @@ -1361,6 +1390,13 @@ return value; } +static bool rtl_is_8116af(struct rtl8169_private *tp) +{ + return tp->mac_version == RTL_GIGA_MAC_VER_52 && + (r8168_mac_ocp_read(tp, 0xdc00) & 0x0078) == 0x0030 && + (r8168_mac_ocp_read(tp, 0xd006) & 0x00ff) == 0x0000; +} + static void rtl_writephy(struct rtl8169_private *tp, int location, int val) { switch (tp->mac_version) { @@ -1384,7 +1420,10 @@ case RTL_GIGA_MAC_VER_31: return r8168dp_2_mdio_read(tp, location); case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: - return r8168g_mdio_read(tp, location); + if (rtl_is_8116af(tp)) + return r8116af_mdio_read(tp, location); + else + return r8168g_mdio_read(tp, location); default: return r8169_mdio_read(tp, location); } @@ -5582,6 +5621,36 @@ rtl_rar_set(tp, mac_addr); } +static bool rtl_aspm_new_dell_platforms(void) +{ + const char *family = dmi_get_system_info(DMI_PRODUCT_FAMILY); + static const char * const dell_product_families[] = { + "Alienware", + "Dell Laptops", + "Dell Pro Laptops", + "Dell Pro Max Laptops", + "Dell Desktops", + "Dell Pro Desktops", + "Dell Pro Max Desktops", + "Dell Pro Rugged Laptops", + "Dell Pro Precision", + "Dell Pro Essential", + "Dell Pro Education", + "XPS" + }; + int i; + + if (!family) + return false; + + for (i = 0; i < ARRAY_SIZE(dell_product_families); i++) { + if (str_has_prefix(family, dell_product_families[i])) + return true; + } + + return false; +} + /* register is set if system vendor successfully tested ASPM 1.2 */ static bool rtl_aspm_is_safe(struct rtl8169_private *tp) { @@ -5589,6 +5658,9 @@ r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) return true; + if (rtl_aspm_new_dell_platforms()) + return true; + return false; } --- linux-nvidia-7.0.0.orig/drivers/net/phy/marvell.c +++ linux-nvidia-7.0.0/drivers/net/phy/marvell.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -356,6 +357,16 @@ u8 vct_phase; }; +static const struct dmi_system_id skip_config_led_tbl[] = { + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "Dell EMC"), + DMI_MATCH(DMI_BOARD_NAME, "0d370eed-89ca-4dc0-a365-e9904c4c62bb"), + }, + }, + {} +}; + static int marvell_read_page(struct phy_device *phydev) { return __phy_read(phydev, MII_MARVELL_PHY_PAGE); @@ -845,6 +856,9 @@ u16 def_config; int err; + if (dmi_check_system(skip_config_led_tbl)) + return; + switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) { /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */ case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R): --- linux-nvidia-7.0.0.orig/drivers/net/vxlan/vxlan_core.c +++ linux-nvidia-7.0.0/drivers/net/vxlan/vxlan_core.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +78,170 @@ ip_tunnel_collect_metadata(); } +static struct ip_fan_map *vxlan_fan_find_map(struct vxlan_dev *vxlan, __be32 daddr) +{ + struct ip_fan_map *fan_map; + + rcu_read_lock(); + list_for_each_entry_rcu(fan_map, &vxlan->fan.fan_maps, list) { + if (fan_map->overlay == + (daddr & inet_make_mask(fan_map->overlay_prefix))) { + rcu_read_unlock(); + return fan_map; + } + } + rcu_read_unlock(); + + return NULL; +} + +static void vxlan_fan_flush_map(struct vxlan_dev *vxlan) +{ + struct ip_fan_map *fan_map; + + list_for_each_entry_rcu(fan_map, &vxlan->fan.fan_maps, list) { + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + } +} + +static int vxlan_fan_del_map(struct vxlan_dev *vxlan, __be32 overlay) +{ + struct ip_fan_map *fan_map; + + fan_map = vxlan_fan_find_map(vxlan, overlay); + if (!fan_map) + return -ENOENT; + + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + + return 0; +} + +static int vxlan_fan_add_map(struct vxlan_dev *vxlan, struct ifla_fan_map *map) +{ + __be32 overlay_mask, underlay_mask; + struct ip_fan_map *fan_map; + + overlay_mask = inet_make_mask(map->overlay_prefix); + underlay_mask = inet_make_mask(map->underlay_prefix); + + netdev_dbg(vxlan->dev, "vfam: map: o %x/%d u %x/%d om %x um %x\n", + map->overlay, map->overlay_prefix, + map->underlay, map->underlay_prefix, + overlay_mask, underlay_mask); + + if ((map->overlay & ~overlay_mask) || (map->underlay & ~underlay_mask)) + return -EINVAL; + + if (!(map->overlay & overlay_mask) && (map->underlay & underlay_mask)) + return -EINVAL; + + /* Special case: overlay 0 and underlay 0: flush all mappings */ + if (!map->overlay && !map->underlay) { + vxlan_fan_flush_map(vxlan); + return 0; + } + + /* Special case: overlay set and underlay 0: clear map for overlay */ + if (!map->underlay) + return vxlan_fan_del_map(vxlan, map->overlay); + + if (vxlan_fan_find_map(vxlan, map->overlay)) + return -EEXIST; + + fan_map = kmalloc(sizeof(*fan_map), GFP_KERNEL); + if (!fan_map) + return -ENOMEM; + + fan_map->underlay = map->underlay; + fan_map->overlay = map->overlay; + fan_map->underlay_prefix = map->underlay_prefix; + fan_map->overlay_mask = ntohl(overlay_mask); + fan_map->overlay_prefix = map->overlay_prefix; + + list_add_tail_rcu(&fan_map->list, &vxlan->fan.fan_maps); + + return 0; +} + +static int vxlan_parse_fan_map(struct nlattr *data[], struct vxlan_dev *vxlan) +{ + struct ifla_fan_map *map; + struct nlattr *attr; + int rem, rv; + + nla_for_each_nested(attr, data[IFLA_VXLAN_FAN_MAP], rem) { + map = nla_data(attr); + rv = vxlan_fan_add_map(vxlan, map); + if (rv) + return rv; + } + + return 0; +} + +static int vxlan_fan_build_rdst(struct vxlan_dev *vxlan, struct sk_buff *skb, + struct vxlan_rdst *fan_rdst) +{ + struct ip_fan_map *f_map; + union vxlan_addr *va; + u32 daddr, underlay; + struct arphdr *arp; + void *arp_ptr; + struct ethhdr *eth; + struct iphdr *iph; + + eth = eth_hdr(skb); + switch (eth->h_proto) { + case htons(ETH_P_IP): + iph = ip_hdr(skb); + if (!iph) + return -EINVAL; + daddr = iph->daddr; + break; + case htons(ETH_P_ARP): + arp = arp_hdr(skb); + if (!arp) + return -EINVAL; + arp_ptr = arp + 1; + netdev_dbg(vxlan->dev, + "vfbr: arp sha %pM sip %pI4 tha %pM tip %pI4\n", + arp_ptr, arp_ptr + skb->dev->addr_len, + arp_ptr + skb->dev->addr_len + 4, + arp_ptr + (skb->dev->addr_len * 2) + 4); + arp_ptr += (skb->dev->addr_len * 2) + 4; + memcpy(&daddr, arp_ptr, 4); + break; + default: + netdev_dbg(vxlan->dev, "vfbr: unknown eth p %x\n", eth->h_proto); + return -EINVAL; + } + + f_map = vxlan_fan_find_map(vxlan, daddr); + if (!f_map) + return -EINVAL; + + daddr = ntohl(daddr); + underlay = ntohl(f_map->underlay); + if (!underlay) + return -EINVAL; + + memset(fan_rdst, 0, sizeof(*fan_rdst)); + va = &fan_rdst->remote_ip; + va->sa.sa_family = AF_INET; + fan_rdst->remote_vni = vxlan->default_dst.remote_vni; + va->sin.sin_addr.s_addr = htonl(underlay | + ((daddr & ~f_map->overlay_mask) >> + (32 - f_map->overlay_prefix - + (32 - f_map->underlay_prefix)))); + netdev_dbg(vxlan->dev, "vfbr: daddr %x ul %x dst %x\n", + daddr, underlay, va->sin.sin_addr.s_addr); + + return 0; +} + /* Find VXLAN socket based on network namespace, address family, UDP port, * enabled unshareable flags and socket device binding (see l3mdev with * non-default VRF). @@ -2490,6 +2655,13 @@ if (flags & VXLAN_F_MC_ROUTE) ipcb_flags |= IPSKB_MCROUTE; + if (fan_has_map(&vxlan->fan) && rt->rt_flags & RTCF_LOCAL) { + netdev_dbg(dev, "discard fan to localhost %pI4\n", + &rdst->remote_ip.sin.sin_addr.s_addr); + ip_rt_put(rt); + goto tx_free; + } + if (!info) { /* Bypass encapsulation if the destination is local */ err = encap_bypass_if_local(skb, dev, vxlan, AF_INET, @@ -2644,6 +2816,7 @@ dst_release(ndst); DEV_STATS_INC(dev, tx_errors); vxlan_vnifilter_count(vxlan, vni, NULL, VXLAN_VNI_STATS_TX_ERRORS, 0); +tx_free: kfree_skb_reason(skb, reason); } @@ -2787,6 +2960,20 @@ rcu_read_unlock(); } + if (fan_has_map(&vxlan->fan)) { + struct vxlan_rdst fan_rdst; + + netdev_dbg(vxlan->dev, "vxlan_xmit p %x d %pM\n", + eth->h_proto, eth->h_dest); + if (vxlan_fan_build_rdst(vxlan, skb, &fan_rdst)) { + dev->stats.tx_dropped++; + kfree_skb(skb); + return NETDEV_TX_OK; + } + vxlan_xmit_one(skb, dev, vni, &fan_rdst, 0); + return NETDEV_TX_OK; + } + eth = eth_hdr(skb); rcu_read_lock(); f = vxlan_find_mac_tx(vxlan, eth->h_dest, vni); @@ -3387,6 +3574,8 @@ vxlan->dev = dev; INIT_HLIST_HEAD(&vxlan->fdb_list); + + INIT_LIST_HEAD(&vxlan->fan.fan_maps); } static void vxlan_ether_setup(struct net_device *dev) @@ -3406,6 +3595,22 @@ dev->netdev_ops = &vxlan_netdev_raw_ops; } +/* Validate Ubuntu FAN payload. + * + * This is required to bypass the strict length validation enforced for the + * attribute types >= IFLA_VXLAN_LOCALBYPASS in vxlan_policy. + * + * In this way we can continue to use the same allocated ID for + * IFLA_VXLAN_FAN_MAP, without breaking the existing user-space and also + * future kernel ABIs that may add new attribute types to vxlan_policy. + */ +static int fan_map_validate_entry(const struct nlattr *attr, + struct netlink_ext_ack *extack) +{ + /* Accept any payload for Ubuntu FAN */ + return 0; +} + static const struct nla_policy vxlan_policy[IFLA_VXLAN_MAX + 1] = { [IFLA_VXLAN_UNSPEC] = { .strict_start_type = IFLA_VXLAN_LOCALBYPASS }, [IFLA_VXLAN_ID] = { .type = NLA_U32 }, @@ -3442,6 +3647,9 @@ [IFLA_VXLAN_LABEL_POLICY] = NLA_POLICY_MAX(NLA_U32, VXLAN_LABEL_MAX), [IFLA_VXLAN_RESERVED_BITS] = NLA_POLICY_EXACT_LEN(sizeof(struct vxlanhdr)), [IFLA_VXLAN_MC_ROUTE] = NLA_POLICY_MAX(NLA_U8, 1), + [IFLA_VXLAN_FAN_MAP] = NLA_POLICY_VALIDATE_FN(NLA_BINARY, + fan_map_validate_entry, + sizeof(struct ifla_fan_map) * 256), }; static int vxlan_validate(struct nlattr *tb[], struct nlattr *data[], @@ -4103,6 +4311,12 @@ conf->remote_ip.sa.sa_family = AF_INET6; } + if (data[IFLA_VXLAN_FAN_MAP]) { + err = vxlan_parse_fan_map(data, vxlan); + if (err) + return err; + } + if (data[IFLA_VXLAN_LOCAL]) { if (changelink && (conf->saddr.sa.sa_family != AF_INET)) { NL_SET_ERR_MSG_ATTR(extack, tb[IFLA_VXLAN_LOCAL], "New local address family does not match old"); @@ -4553,6 +4767,7 @@ nla_total_size(sizeof(__u8)) + /* IFLA_VXLAN_VNIFILTER */ /* IFLA_VXLAN_RESERVED_BITS */ nla_total_size(sizeof(struct vxlanhdr)) + + nla_total_size(sizeof(struct ip_fan_map) * 256) + 0; } @@ -4599,6 +4814,26 @@ } } + if (fan_has_map(&vxlan->fan)) { + struct nlattr *fan_nest; + struct ip_fan_map *fan_map; + + fan_nest = nla_nest_start(skb, IFLA_VXLAN_FAN_MAP); + if (!fan_nest) + goto nla_put_failure; + list_for_each_entry_rcu(fan_map, &vxlan->fan.fan_maps, list) { + struct ifla_fan_map map; + + map.underlay = fan_map->underlay; + map.underlay_prefix = fan_map->underlay_prefix; + map.overlay = fan_map->overlay; + map.overlay_prefix = fan_map->overlay_prefix; + if (nla_put(skb, IFLA_FAN_MAPPING, sizeof(map), &map)) + goto nla_put_failure; + } + nla_nest_end(skb, fan_nest); + } + if (nla_put_u8(skb, IFLA_VXLAN_TTL, vxlan->cfg.ttl) || nla_put_u8(skb, IFLA_VXLAN_TTL_INHERIT, !!(vxlan->cfg.flags & VXLAN_F_TTL_INHERIT)) || @@ -4933,6 +5168,29 @@ NULL); } +#ifdef CONFIG_SYSCTL +static struct ctl_table_header *vxlan_fan_header; +static unsigned int vxlan_fan_version = 4; +static unsigned int ifla_vxlan_fan_map = IFLA_VXLAN_FAN_MAP; + +static struct ctl_table vxlan_fan_sysctls[] = { + { + .procname = "vxlan", + .data = &vxlan_fan_version, + .maxlen = sizeof(vxlan_fan_version), + .mode = 0444, + .proc_handler = proc_dointvec, + }, + { + .procname = "IFLA_VXLAN_FAN_MAP", + .data = &ifla_vxlan_fan_map, + .maxlen = sizeof(ifla_vxlan_fan_map), + .mode = 0444, + .proc_handler = proc_dointvec, + }, +}; +#endif /* CONFIG_SYSCTL */ + static void __net_exit vxlan_destroy_tunnels(struct vxlan_net *vn, struct list_head *dev_to_kill) { @@ -4994,7 +5252,22 @@ if (rc) goto out5; +#ifdef CONFIG_SYSCTL + vxlan_fan_header = register_net_sysctl(&init_net, "net/fan", + vxlan_fan_sysctls); + if (!vxlan_fan_header) { + rc = -ENOMEM; + goto sysctl_failed; + } +#endif /* CONFIG_SYSCTL */ + return 0; + +#ifdef CONFIG_SYSCTL +sysctl_failed: + rtnl_link_unregister(&vxlan_link_ops); +#endif /* CONFIG_SYSCTL */ + out5: rtnl_link_unregister(&vxlan_link_ops); out4: @@ -5010,6 +5283,9 @@ static void __exit vxlan_cleanup_module(void) { +#ifdef CONFIG_SYSCTL + unregister_net_sysctl_table(vxlan_fan_header); +#endif /* CONFIG_SYSCTL */ vxlan_vnifilter_uninit(); rtnl_link_unregister(&vxlan_link_ops); unregister_switchdev_notifier(&vxlan_switchdev_notifier_block); --- linux-nvidia-7.0.0.orig/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ linux-nvidia-7.0.0/drivers/net/wireless/intel/iwlwifi/pcie/drv.c @@ -208,6 +208,7 @@ {IWL_PCI_DEVICE(0x088E, 0x446A, iwl6030_mac_cfg)}, {IWL_PCI_DEVICE(0x088E, 0x4860, iwl6030_mac_cfg)}, {IWL_PCI_DEVICE(0x088F, 0x5260, iwl6030_mac_cfg)}, + {IWL_PCI_DEVICE(0x088F, 0x526A, iwl6030_mac_cfg)}, /* 105 Series */ {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_mac_cfg)}, --- linux-nvidia-7.0.0.orig/drivers/net/wireless/marvell/mwifiex/fw.h +++ linux-nvidia-7.0.0/drivers/net/wireless/marvell/mwifiex/fw.h @@ -206,6 +206,7 @@ #define TLV_TYPE_CHANNEL_STATS (PROPRIETARY_TLV_BASE_ID + 198) #define TLV_BTCOEX_WL_AGGR_WINSIZE (PROPRIETARY_TLV_BASE_ID + 202) #define TLV_BTCOEX_WL_SCANTIME (PROPRIETARY_TLV_BASE_ID + 203) +#define TLV_TYPE_LED_CONTROL (PROPRIETARY_TLV_BASE_ID + 205) #define TLV_TYPE_BSS_MODE (PROPRIETARY_TLV_BASE_ID + 206) #define TLV_TYPE_RANDOM_MAC (PROPRIETARY_TLV_BASE_ID + 236) #define TLV_TYPE_CHAN_ATTR_CFG (PROPRIETARY_TLV_BASE_ID + 237) @@ -356,6 +357,7 @@ #define HostCmd_CMD_802_11_AD_HOC_JOIN 0x002c #define HostCmd_CMD_802_11_AD_HOC_STOP 0x0040 #define HostCmd_CMD_802_11_MAC_ADDRESS 0x004D +#define HostCmd_CMD_802_11_LED_CONTROL 0X004E #define HostCmd_CMD_802_11D_DOMAIN_INFO 0x005b #define HostCmd_CMD_802_11_KEY_MATERIAL 0x005e #define HostCmd_CMD_802_11_BG_SCAN_CONFIG 0x006b @@ -1236,6 +1238,16 @@ u8 oper_mode; } __packed; +struct mwifiex_led_param { + __le16 mode; + __le16 on; +} __packed; + +struct mwifiex_ie_types_led_param { + struct mwifiex_ie_types_header header; + struct mwifiex_led_param led_cfg; +} __packed; + struct host_cmd_ds_802_11_ad_hoc_start { u8 ssid[IEEE80211_MAX_SSID_LEN]; u8 bss_mode; @@ -1359,6 +1371,11 @@ } params; } __packed; +struct host_cmd_ds_802_11_led_control { + __le16 action; + __le16 num_led; +} __packed; + enum SNMP_MIB_INDEX { OP_RATE_SET_I = 1, DTIM_PERIOD_I = 3, @@ -2438,6 +2455,7 @@ struct host_cmd_sdio_sp_rx_aggr_cfg sdio_rx_aggr_cfg; struct host_cmd_ds_multi_chan_policy mc_policy; struct host_cmd_ds_robust_coex coex; + struct host_cmd_ds_802_11_led_control led_cfg; struct host_cmd_ds_wakeup_reason hs_wakeup_reason; struct host_cmd_ds_gtk_rekey_params rekey; struct host_cmd_ds_chan_region_cfg reg_cfg; --- linux-nvidia-7.0.0.orig/drivers/net/wireless/marvell/mwifiex/main.c +++ linux-nvidia-7.0.0/drivers/net/wireless/marvell/mwifiex/main.c @@ -731,8 +731,10 @@ static int mwifiex_open(struct net_device *dev) { - netif_carrier_off(dev); + struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev); + netif_carrier_off(dev); + mwifiex_set_led(priv->adapter, MWIFIEX_LED_ON); return 0; } @@ -763,6 +765,7 @@ cfg80211_sched_scan_stopped(priv->wdev.wiphy, 0); } + mwifiex_set_led(priv->adapter, MWIFIEX_LED_OFF); return 0; } --- linux-nvidia-7.0.0.orig/drivers/net/wireless/marvell/mwifiex/main.h +++ linux-nvidia-7.0.0/drivers/net/wireless/marvell/mwifiex/main.h @@ -119,6 +119,10 @@ #define PKT_TYPE_MGMT 0xE5 +#define MWIFIEX_LED_ON 1 +#define MWIFIEX_LED_OFF 0 +#define MWIFIEX_LED_MAX 3 + /* * Do not check for data_received for USB, as data_received * is handled in mwifiex_usb_recv for USB @@ -681,6 +685,7 @@ struct sk_buff_head bypass_txq; struct mwifiex_user_scan_chan hidden_chan[MWIFIEX_USER_SCAN_CHAN_MAX]; bool ht_param_present; + bool is_edge_gateway; }; @@ -1479,6 +1484,7 @@ struct cmd_ctrl_node *cmd_queued); int mwifiex_bss_start(struct mwifiex_private *priv, struct cfg80211_bss *bss, struct cfg80211_ssid *req_ssid); +int mwifiex_set_led(struct mwifiex_adapter *adapter, int on); int mwifiex_cancel_hs(struct mwifiex_private *priv, int cmd_type); int mwifiex_enable_hs(struct mwifiex_adapter *adapter); int mwifiex_disable_auto_ds(struct mwifiex_private *priv); --- linux-nvidia-7.0.0.orig/drivers/net/wireless/marvell/mwifiex/pcie.c +++ linux-nvidia-7.0.0/drivers/net/wireless/marvell/mwifiex/pcie.c @@ -377,6 +377,8 @@ const struct pci_device_id *ent) { struct pcie_service_card *card; + struct mwifiex_private *priv; + struct pci_dev *pdev_host; int ret; pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", @@ -418,6 +420,14 @@ return -1; } + priv = mwifiex_get_priv(card->adapter, MWIFIEX_BSS_ROLE_STA); + pdev_host = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0720, NULL); + if (!pdev_host) + pdev_host = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, 0x1028, 0x0733, NULL); + if (pdev_host) { + priv->is_edge_gateway = true; + pci_dev_put(pdev_host); + } return 0; } --- linux-nvidia-7.0.0.orig/drivers/net/wireless/marvell/mwifiex/sta_cmd.c +++ linux-nvidia-7.0.0/drivers/net/wireless/marvell/mwifiex/sta_cmd.c @@ -401,6 +401,31 @@ return 0; } +static int mwifiex_cmd_802_11_led_cfg(struct mwifiex_private *priv, + struct host_cmd_ds_command *cmd, + u16 cmd_action, + struct mwifiex_led_param *ledcfg_param) +{ + struct host_cmd_ds_802_11_led_control *led_cfg = &cmd->params.led_cfg; + struct mwifiex_ie_types_led_param *led_tlv; + u8 *pos; + + cmd->command = cpu_to_le16(HostCmd_CMD_802_11_LED_CONTROL); + cmd->size = cpu_to_le16(S_DS_GEN); + le16_add_cpu(&cmd->size, sizeof(struct host_cmd_ds_802_11_led_control)); + + led_cfg->action = cpu_to_le16(cmd_action); + led_cfg->num_led = cpu_to_le16(MWIFIEX_LED_MAX); + + pos = (u8 *)led_cfg + sizeof(struct host_cmd_ds_802_11_led_control); + led_tlv = (void *)pos; + led_tlv->header.type = cpu_to_le16(TLV_TYPE_LED_CONTROL); + led_tlv->header.len = cpu_to_le16(sizeof(struct mwifiex_led_param)); + memcpy(&led_tlv->led_cfg, ledcfg_param, sizeof(struct mwifiex_led_param)); + le16_add_cpu(&cmd->size, sizeof(struct mwifiex_ie_types_led_param)); + return 0; +} + /* * This function prepares command to set/get MAC address. * @@ -2093,6 +2118,10 @@ ret = mwifiex_cmd_802_11_hs_cfg(priv, cmd_ptr, cmd_action, (struct mwifiex_hs_config_param *) data_buf); break; + case HostCmd_CMD_802_11_LED_CONTROL: + ret = mwifiex_cmd_802_11_led_cfg(priv, cmd_ptr, cmd_action, + data_buf); + break; case HostCmd_CMD_802_11_SCAN: ret = mwifiex_cmd_802_11_scan(cmd_ptr, data_buf); break; --- linux-nvidia-7.0.0.orig/drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c +++ linux-nvidia-7.0.0/drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c @@ -1424,6 +1424,8 @@ case HostCmd_CMD_ROBUST_COEX: ret = mwifiex_ret_robust_coex(priv, resp, data_buf); break; + case HostCmd_CMD_802_11_LED_CONTROL: + break; case HostCmd_CMD_GTK_REKEY_OFFLOAD_CFG: break; case HostCmd_CMD_CHAN_REGION_CFG: --- linux-nvidia-7.0.0.orig/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c +++ linux-nvidia-7.0.0/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c @@ -610,6 +610,24 @@ } EXPORT_SYMBOL_GPL(mwifiex_enable_hs); +int mwifiex_set_led(struct mwifiex_adapter *adapter, int on) +{ + struct mwifiex_private *priv; + struct mwifiex_led_param ledcfg; + + priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA); + if (!priv->is_edge_gateway) + return -ENODEV; + + memset(&ledcfg, 0, sizeof(struct mwifiex_led_param)); + ledcfg.on = cpu_to_le16(on); + + return mwifiex_send_cmd(priv, + HostCmd_CMD_802_11_LED_CONTROL, + HostCmd_ACT_GEN_SET, 0, + &ledcfg, true); +} + /* * IOCTL request handler to get BSS information. * --- linux-nvidia-7.0.0.orig/drivers/net/wireless/mediatek/mt76/mt7925/main.c +++ linux-nvidia-7.0.0/drivers/net/wireless/mediatek/mt76/mt7925/main.c @@ -245,6 +245,7 @@ { struct wiphy *wiphy = phy->mt76->hw->wiphy; static const u8 ext_capa_sta[] = { + [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, }; @@ -438,6 +439,8 @@ if (phy->chip_cap & MT792x_CHIP_CAP_RSSI_NOTIFY_EVT_EN) vif->driver_flags |= IEEE80211_VIF_SUPPORTS_CQM_RSSI; + INIT_WORK(&mvif->csa_work, mt7925_csa_work); + timer_setup(&mvif->csa_timer, mt792x_csa_timer, 0); out: mt792x_mutex_release(dev); @@ -1749,6 +1752,10 @@ mt7925_add_chanctx(struct ieee80211_hw *hw, struct ieee80211_chanctx_conf *ctx) { + struct mt792x_dev *dev = mt792x_hw_dev(hw); + + dev->new_ctx = ctx; + return 0; } @@ -1756,6 +1763,11 @@ mt7925_remove_chanctx(struct ieee80211_hw *hw, struct ieee80211_chanctx_conf *ctx) { + struct mt792x_dev *dev = mt792x_hw_dev(hw); + + if (dev->new_ctx == ctx) + dev->new_ctx = NULL; + } static void @@ -2144,6 +2156,11 @@ mctx->bss_conf = NULL; mconf->mt76.ctx = NULL; mutex_unlock(&dev->mt76.mutex); + + if (link_conf->csa_active) { + timer_delete_sync(&mvif->csa_timer); + cancel_work_sync(&mvif->csa_work); + } } static void mt7925_rfkill_poll(struct ieee80211_hw *hw) @@ -2158,6 +2175,121 @@ wiphy_rfkill_set_hw_state(hw->wiphy, ret == 0); } +static int mt7925_switch_vif_chanctx(struct ieee80211_hw *hw, + struct ieee80211_vif_chanctx_switch *vifs, + int n_vifs, + enum ieee80211_chanctx_switch_mode mode) +{ + return mt7925_assign_vif_chanctx(hw, vifs->vif, vifs->link_conf, + vifs->new_ctx); +} + +void mt7925_csa_work(struct work_struct *work) +{ + struct mt792x_vif *mvif; + struct mt792x_dev *dev; + struct ieee80211_vif *vif; + struct ieee80211_bss_conf *link_conf; + struct mt792x_bss_conf *mconf; + u8 link_id, roc_rtype; + int ret = 0; + + mvif = (struct mt792x_vif *)container_of(work, struct mt792x_vif, + csa_work); + dev = mvif->phy->dev; + vif = container_of((void *)mvif, struct ieee80211_vif, drv_priv); + + if (ieee80211_vif_is_mld(vif)) + return; + + if (!dev->new_ctx) + return; + + link_id = 0; + mconf = &mvif->bss_conf; + link_conf = &vif->bss_conf; + roc_rtype = MT7925_ROC_REQ_JOIN; + + mt792x_mutex_acquire(dev); + ret = mt7925_set_roc(mvif->phy, mconf, dev->new_ctx->def.chan, + 4000, roc_rtype); + mt792x_mutex_release(dev); + if (!ret) { + mt792x_mutex_acquire(dev); + ret = mt7925_mcu_set_chctx(mvif->phy->mt76, &mconf->mt76, link_conf, + dev->new_ctx); + mt792x_mutex_release(dev); + + mt7925_abort_roc(mvif->phy, mconf); + } + + ieee80211_chswitch_done(vif, !ret, link_id); +} + +static int mt7925_pre_channel_switch(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_channel_switch *chsw) +{ + if (ieee80211_vif_is_mld(vif)) + return -EOPNOTSUPP; + + if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) + return -EOPNOTSUPP; + + if (!cfg80211_chandef_usable(hw->wiphy, &chsw->chandef, + IEEE80211_CHAN_DISABLED)) + return -EOPNOTSUPP; + + return 0; +} + +static void mt7925_channel_switch(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_channel_switch *chsw) +{ + struct mt792x_vif *mvif = (struct mt792x_vif *)vif->drv_priv; + u16 beacon_interval; + + if (ieee80211_vif_is_mld(vif)) + return; + + beacon_interval = vif->bss_conf.beacon_int; + + mvif->csa_timer.expires = TU_TO_EXP_TIME(beacon_interval * chsw->count); + add_timer(&mvif->csa_timer); +} + +static void mt7925_abort_channel_switch(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *link_conf) +{ + struct mt792x_vif *mvif = (struct mt792x_vif *)vif->drv_priv; + + timer_delete_sync(&mvif->csa_timer); + cancel_work_sync(&mvif->csa_work); +} + +static void mt7925_channel_switch_rx_beacon(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_channel_switch *chsw) +{ + struct mt792x_dev *dev = mt792x_hw_dev(hw); + struct mt792x_vif *mvif = (struct mt792x_vif *)vif->drv_priv; + u16 beacon_interval; + + if (ieee80211_vif_is_mld(vif)) + return; + + beacon_interval = vif->bss_conf.beacon_int; + + if (cfg80211_chandef_identical(&chsw->chandef, + &dev->new_ctx->def) && + chsw->count) { + mod_timer(&mvif->csa_timer, + TU_TO_EXP_TIME(beacon_interval * chsw->count)); + } +} + const struct ieee80211_ops mt7925_ops = { .tx = mt792x_tx, .start = mt7925_start, @@ -2221,6 +2353,12 @@ .change_vif_links = mt7925_change_vif_links, .change_sta_links = mt7925_change_sta_links, .rfkill_poll = mt7925_rfkill_poll, + + .switch_vif_chanctx = mt7925_switch_vif_chanctx, + .pre_channel_switch = mt7925_pre_channel_switch, + .channel_switch = mt7925_channel_switch, + .abort_channel_switch = mt7925_abort_channel_switch, + .channel_switch_rx_beacon = mt7925_channel_switch_rx_beacon, }; EXPORT_SYMBOL_GPL(mt7925_ops); --- linux-nvidia-7.0.0.orig/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c +++ linux-nvidia-7.0.0/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c @@ -1330,6 +1330,8 @@ .roc[1].len = cpu_to_le16(sizeof(struct roc_acquire_tlv)) }; + struct wiphy *wiphy = mvif->phy->mt76->hw->wiphy; + if (!mconf || hweight16(vif->valid_links) < 2 || hweight16(sel_links) != 2) return -EPERM; @@ -1352,7 +1354,8 @@ is_AG_band |= links[i].chan->band == NL80211_BAND_2GHZ; } - if (vif->cfg.eml_cap & IEEE80211_EML_CAP_EMLSR_SUPP) + if (!(wiphy->iftype_ext_capab[0].mld_capa_and_ops & + IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS)) type = is_AG_band ? MT7925_ROC_REQ_MLSR_AG : MT7925_ROC_REQ_MLSR_AA; else --- linux-nvidia-7.0.0.orig/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h +++ linux-nvidia-7.0.0/drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h @@ -298,6 +298,7 @@ void mt7925_mlo_pm_work(struct work_struct *work); void mt7925_scan_work(struct work_struct *work); void mt7925_roc_work(struct work_struct *work); +void mt7925_csa_work(struct work_struct *work); int mt7925_mcu_uni_bss_ps(struct mt792x_dev *dev, struct ieee80211_bss_conf *link_conf); void mt7925_coredump_work(struct work_struct *work); --- linux-nvidia-7.0.0.orig/drivers/net/wireless/mediatek/mt76/mt792x_core.c +++ linux-nvidia-7.0.0/drivers/net/wireless/mediatek/mt76/mt792x_core.c @@ -691,9 +691,7 @@ ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); ieee80211_hw_set(hw, SUPPORTS_ONLY_HE_MULTI_BSSID); - if (is_mt7921(&dev->mt76)) { - ieee80211_hw_set(hw, CHANCTX_STA_CSA); - } + ieee80211_hw_set(hw, CHANCTX_STA_CSA); if (dev->pm.enable) ieee80211_hw_set(hw, CONNECTION_MONITOR); --- linux-nvidia-7.0.0.orig/drivers/net/wireless/mediatek/mt76/mt792x_mac.c +++ linux-nvidia-7.0.0/drivers/net/wireless/mediatek/mt76/mt792x_mac.c @@ -375,7 +375,7 @@ } if (!mt792x_mcu_fw_pmctrl(dev)) { - cancel_delayed_work_sync(&mphy->mac_work); + cancel_delayed_work(&mphy->mac_work); return; } out: --- linux-nvidia-7.0.0.orig/drivers/nvme/host/core.c +++ linux-nvidia-7.0.0/drivers/nvme/host/core.c @@ -1303,7 +1303,7 @@ * The host should send Keep Alive commands at half of the Keep Alive Timeout * accounting for transport roundtrip times [..]. */ -static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) +unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) { unsigned long delay = ctrl->kato * HZ / 2; @@ -1317,6 +1317,7 @@ delay /= 2; return delay; } +EXPORT_SYMBOL_GPL(nvme_keep_alive_work_period); static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl) { --- linux-nvidia-7.0.0.orig/drivers/nvme/host/fabrics.c +++ linux-nvidia-7.0.0/drivers/nvme/host/fabrics.c @@ -709,6 +709,7 @@ { NVMF_OPT_TLS, "tls" }, { NVMF_OPT_CONCAT, "concat" }, #endif + { NVMF_OPT_RECOVERY_DELAY, "recovery_delay=%d" }, { NVMF_OPT_ERR, NULL } }; @@ -1064,6 +1065,18 @@ } opts->concat = true; break; + case NVMF_OPT_RECOVERY_DELAY: + if (match_int(args, &token)) { + ret = -EINVAL; + goto out; + } + if (token <= 0) { + pr_err("Invalid recovery_delay %d\n", token); + ret = -EINVAL; + goto out; + } + opts->recovery_delay = token; + break; default: pr_warn("unknown parameter or missing value '%s' in ctrl creation request\n", p); --- linux-nvidia-7.0.0.orig/drivers/nvme/host/fabrics.h +++ linux-nvidia-7.0.0/drivers/nvme/host/fabrics.h @@ -67,6 +67,7 @@ NVMF_OPT_KEYRING = 1 << 26, NVMF_OPT_TLS_KEY = 1 << 27, NVMF_OPT_CONCAT = 1 << 28, + NVMF_OPT_RECOVERY_DELAY = 1 << 29, }; /** @@ -93,6 +94,7 @@ * @queue_size: Number of IO queue elements. * @nr_io_queues: Number of controller IO queues that will be established. * @reconnect_delay: Time between two consecutive reconnect attempts. + * @recovery_delay: Time before error recovery starts after error detection. * @discovery_nqn: indicates if the subsysnqn is the well-known discovery NQN. * @kato: Keep-alive timeout. * @host: Virtual NVMe host, contains the NQN and Host ID. @@ -123,6 +125,7 @@ size_t queue_size; unsigned int nr_io_queues; unsigned int reconnect_delay; + unsigned int recovery_delay; bool discovery_nqn; bool duplicate_connect; unsigned int kato; --- linux-nvidia-7.0.0.orig/drivers/nvme/host/nvme.h +++ linux-nvidia-7.0.0/drivers/nvme/host/nvme.h @@ -896,6 +896,7 @@ void nvme_wait_freeze(struct nvme_ctrl *ctrl); int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); void nvme_start_freeze(struct nvme_ctrl *ctrl); +unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl); static inline enum req_op nvme_req_op(struct nvme_command *cmd) { --- linux-nvidia-7.0.0.orig/drivers/nvme/host/tcp.c +++ linux-nvidia-7.0.0/drivers/nvme/host/tcp.c @@ -194,7 +194,7 @@ struct sockaddr_storage src_addr; struct nvme_ctrl ctrl; - struct work_struct err_work; + struct delayed_work err_work; struct delayed_work connect_work; struct nvme_tcp_request async_req; u32 io_queues[HCTX_MAX_TYPES]; @@ -610,13 +610,25 @@ queue->ddgst_remaining = 0; } +/* + * Error recovery needs to be started after KATO expired, + * always delay until the next KATO interval before + * starting error recovery. + */ static void nvme_tcp_error_recovery(struct nvme_ctrl *ctrl) { + unsigned long delay; + if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) return; - dev_warn(ctrl->device, "starting error recovery\n"); - queue_work(nvme_reset_wq, &to_tcp_ctrl(ctrl)->err_work); + delay = ctrl->opts->recovery_delay * HZ; + if (!delay) + delay = nvme_keep_alive_work_period(ctrl); + + dev_warn(ctrl->device, "starting error recovery in %lu seconds\n", + delay / HZ); + queue_delayed_work(nvme_reset_wq, &to_tcp_ctrl(ctrl)->err_work, delay); } static int nvme_tcp_process_nvme_cqe(struct nvme_tcp_queue *queue, @@ -2473,7 +2485,7 @@ static void nvme_tcp_error_recovery_work(struct work_struct *work) { - struct nvme_tcp_ctrl *tcp_ctrl = container_of(work, + struct nvme_tcp_ctrl *tcp_ctrl = container_of(to_delayed_work(work), struct nvme_tcp_ctrl, err_work); struct nvme_ctrl *ctrl = &tcp_ctrl->ctrl; @@ -2546,7 +2558,7 @@ static void nvme_tcp_stop_ctrl(struct nvme_ctrl *ctrl) { - flush_work(&to_tcp_ctrl(ctrl)->err_work); + flush_delayed_work(&to_tcp_ctrl(ctrl)->err_work); cancel_delayed_work_sync(&to_tcp_ctrl(ctrl)->connect_work); } @@ -2650,6 +2662,14 @@ rq->tag, nvme_cid(rq), pdu->hdr.type, cmd->common.opcode, nvme_fabrics_opcode_str(qid, cmd), qid); + /* + * If the error recovery is started all commands will be + * aborted anyway, and nothing is to be done here. + */ + if (nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING && + delayed_work_pending(&to_tcp_ctrl(ctrl)->err_work)) + return BLK_EH_RESET_TIMER; + if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE) { /* * If we are resetting, connecting or deleting we should @@ -2905,7 +2925,8 @@ INIT_DELAYED_WORK(&ctrl->connect_work, nvme_tcp_reconnect_ctrl_work); - INIT_WORK(&ctrl->err_work, nvme_tcp_error_recovery_work); + INIT_DELAYED_WORK(&ctrl->err_work, + nvme_tcp_error_recovery_work); INIT_WORK(&ctrl->ctrl.reset_work, nvme_reset_ctrl_work); if (!(opts->mask & NVMF_OPT_TRSVCID)) { --- linux-nvidia-7.0.0.orig/drivers/pci/controller/vmd.c +++ linux-nvidia-7.0.0/drivers/pci/controller/vmd.c @@ -739,6 +739,8 @@ if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) return 0; + pdev->aspm_os_control = 1; + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); if (!pos) goto out_state_change; @@ -901,10 +903,15 @@ sd->node = pcibus_to_node(vmd->dev->bus); + pci_lock_rescan_remove(); + vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start, &vmd_ops, sd, &resources); if (!vmd->bus) { pci_bus_release_emul_domain_nr(sd->domain); + + pci_unlock_rescan_remove(); + pci_free_resource_list(&resources); vmd_remove_irq_domain(vmd); return -ENODEV; @@ -962,6 +969,8 @@ pci_bus_add_devices(vmd->bus); vmd_acpi_end(); + + pci_unlock_rescan_remove(); return 0; } --- linux-nvidia-7.0.0.orig/drivers/pci/pcie/aspm.c +++ linux-nvidia-7.0.0/drivers/pci/pcie/aspm.c @@ -1465,8 +1465,12 @@ * the _OSC method), we can't honor that request. */ if (aspm_disabled) { - pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n"); - return -EPERM; + if (aspm_support_enabled && pdev->aspm_os_control) + pci_info(pdev, "BIOS can't program ASPM, let OS control it\n"); + else { + pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n"); + return -EPERM; + } } if (!locked) --- linux-nvidia-7.0.0.orig/drivers/pci/quirks.c +++ linux-nvidia-7.0.0/drivers/pci/quirks.c @@ -317,6 +317,21 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); +/* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed +* by IO resource file, and need to skip the files +*/ +static void quirk_marvell_mask_bar(struct pci_dev *dev) +{ + int i; + + for (i = 0; i < 5; i++) + if (dev->resource[i].start) + dev->resource[i].start = + dev->resource[i].end = 0; +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, + quirk_marvell_mask_bar); + /* * The Mellanox Tavor device gives false positive parity errors. Disable * parity error reporting. --- linux-nvidia-7.0.0.orig/drivers/perf/arm-cmn.c +++ linux-nvidia-7.0.0/drivers/perf/arm-cmn.c @@ -2564,6 +2564,7 @@ struct arm_cmn *cmn; const char *name; static atomic_t id; + struct resource *cfg; int err, rootnode, this_id; cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL); @@ -2579,7 +2580,16 @@ rootnode = arm_cmn600_acpi_probe(pdev, cmn); } else { rootnode = 0; - cmn->base = devm_platform_ioremap_resource(pdev, 0); + + /* + * Avoid requesting resources as the PMUs registers are + * scattered through CMN, and may appear either side of + * registers for other 'devices'. (e.g. the MPAM MSC controls). + */ + cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!cfg) + return -EINVAL; + cmn->base = devm_ioremap(&pdev->dev, cfg->start, resource_size(cfg)); if (IS_ERR(cmn->base)) return PTR_ERR(cmn->base); if (cmn->part == PART_CMN600) --- linux-nvidia-7.0.0.orig/drivers/phy/qualcomm/Kconfig +++ linux-nvidia-7.0.0/drivers/phy/qualcomm/Kconfig @@ -28,6 +28,19 @@ Enable this driver to support the Qualcomm eDP PHY found in various Qualcomm chipsets. +config PHY_QCOM_MIPI_CSI2 + tristate "Qualcomm MIPI CSI2 PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on OF + depends on COMMON_CLK + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY + help + Enable this to support the MIPI CSI2 PHY driver found in various + Qualcomm chipsets. This PHY is used to connect MIPI CSI2 + camera sensors to the CSI Decoder in the Qualcomm Camera Subsystem + CAMSS. + config PHY_QCOM_IPQ4019_USB tristate "Qualcomm IPQ4019 USB PHY driver" depends on OF && (ARCH_QCOM || COMPILE_TEST) --- linux-nvidia-7.0.0.orig/drivers/phy/qualcomm/Makefile +++ linux-nvidia-7.0.0/drivers/phy/qualcomm/Makefile @@ -6,6 +6,11 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o obj-$(CONFIG_PHY_QCOM_M31_EUSB) += phy-qcom-m31-eusb2.o + +phy-qcom-mipi-csi2-objs += phy-qcom-mipi-csi2-core.o \ + phy-qcom-mipi-csi2-3ph-dphy.o +obj-$(CONFIG_PHY_QCOM_MIPI_CSI2) += phy-qcom-mipi-csi2.o + obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o --- linux-nvidia-7.0.0.orig/drivers/phy/qualcomm/phy-qcom-edp.c +++ linux-nvidia-7.0.0/drivers/phy/qualcomm/phy-qcom-edp.c @@ -1315,18 +1315,6 @@ if (ret) return ret; - ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ - if (ret) { - dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); - return ret; - } - - ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ - if (ret) { - dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); - return ret; - } - ret = qcom_edp_clks_register(edp, pdev->dev.of_node); if (ret) return ret; --- linux-nvidia-7.0.0.orig/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ linux-nvidia-7.0.0/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0 + * + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2016-2025 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include "phy-qcom-mipi-csi2.h" + +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) ((offset) + 0x4 * (n)) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL0_PHY_SW_RESET BIT(0) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL10_IRQ_CLEAR_CMD BIT(0) +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n)) + +/* + * 3 phase CSI has 19 common status regs with only 0-10 being used + * and 11-18 being reserved. + */ +#define CSI_COMMON_STATUS_NUM 11 +/* + * There are a number of common control registers + * The offset to clear the CSIPHY IRQ status starts @ 22 + * So to clear CSI_COMMON_STATUS0 this is CSI_COMMON_CONTROL22, STATUS1 is + * CONTROL23 and so on + */ +#define CSI_CTRL_STATUS_INDEX 22 + +/* + * There are 43 COMMON_CTRL registers with regs after # 33 being reserved + */ +#define CSI_CTRL_MAX 33 + +#define CSIPHY_DEFAULT_PARAMS 0 +#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2 +#define CSIPHY_SKEW_CAL 7 + +/* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ +static const struct +mipi_csi2phy_lane_regs lane_regs_x1e80100[] = { + /* Power up lanes 2ph mode */ + {.reg_addr = 0x1014, .reg_data = 0xd5, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x101c, .reg_data = 0x7a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x1018, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + + {.reg_addr = 0x0094, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x00a0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0090, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0098, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0094, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0030, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0000, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0038, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x002c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0034, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x001c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0014, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x003c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0004, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0020, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0008, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0010, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0094, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x005c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0060, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0064, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, + + {.reg_addr = 0x0e94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0ea0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e28, .reg_data = 0x04, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e00, .reg_data = 0x80, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e0c, .reg_data = 0xff, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e38, .reg_data = 0x1f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e2c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e34, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e1c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e3c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e04, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0e08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0e10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, + + {.reg_addr = 0x0494, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x04a0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0490, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0498, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0494, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0430, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0400, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0438, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x042c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0434, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x041c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0414, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x043c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0404, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0420, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0408, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0410, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0494, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x045c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0460, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0464, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, + + {.reg_addr = 0x0894, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x08a0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0890, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0898, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0894, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0830, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0838, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x082c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0834, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x081c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0814, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x083c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0804, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0820, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0808, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0810, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0894, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x085c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0860, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0864, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, + + {.reg_addr = 0x0c94, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0ca0, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c90, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c98, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c94, .reg_data = 0x07, .delay_us = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c30, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c00, .reg_data = 0x8e, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c38, .reg_data = 0xfe, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c2c, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c34, .reg_data = 0x0f, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c1c, .reg_data = 0x0a, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c14, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c3c, .reg_data = 0xb8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c04, .reg_data = 0x0c, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c20, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c08, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0c10, .reg_data = 0x52, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0c94, .reg_data = 0xd7, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0c5c, .reg_data = 0x00, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0c60, .reg_data = 0xbd, .param_type = CSIPHY_SKEW_CAL}, + {.reg_addr = 0x0c64, .reg_data = 0x7f, .param_type = CSIPHY_SKEW_CAL}, +}; + +static inline const struct mipi_csi2phy_device_regs * +csi2phy_dev_to_regs(struct mipi_csi2phy_device *csi2phy) +{ + return &csi2phy->soc_cfg->reg_info; +} + +static void phy_qcom_mipi_csi2_hw_version_read(struct mipi_csi2phy_device *csi2phy) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + u32 tmp; + + writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6)); + + tmp = readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 12)); + csi2phy->hw_version = tmp; + + tmp = readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 13)); + csi2phy->hw_version |= (tmp << 8) & 0xFF00; + + tmp = readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 14)); + csi2phy->hw_version |= (tmp << 16) & 0xFF0000; + + tmp = readl_relaxed(csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 15)); + csi2phy->hw_version |= (tmp << 24) & 0xFF000000; + + dev_dbg_once(csi2phy->dev, "CSIPHY 3PH HW Version = 0x%08x\n", csi2phy->hw_version); +} + +/* + * phy_qcom_mipi_csi2_reset - Perform software reset on CSIPHY module + * @phy_qcom_mipi_csi2: CSIPHY device + */ +static void phy_qcom_mipi_csi2_reset(struct mipi_csi2phy_device *csi2phy) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + + writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL0_PHY_SW_RESET, + csi2phy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 0)); + usleep_range(5000, 8000); + writel(0x0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 0)); +} + +/* + * phy_qcom_mipi_csi2_settle_cnt_calc - Calculate settle count value + * + * Helper function to calculate settle count value. This is + * based on the CSI2 T_hs_settle parameter which in turn + * is calculated based on the CSI2 transmitter link frequency. + * + * Return settle count value or 0 if the CSI2 link frequency + * is not available + */ +static u8 phy_qcom_mipi_csi2_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate) +{ + u32 t_hs_prepare_max_ps; + u32 timer_period_ps; + u32 t_hs_settle_ps; + u8 settle_cnt; + u32 ui_ps; + + if (link_freq <= 0) + return 0; + + ui_ps = div_u64(PSEC_PER_SEC, link_freq); + ui_ps /= 2; + t_hs_prepare_max_ps = 85000 + 6 * ui_ps; + t_hs_settle_ps = t_hs_prepare_max_ps; + + timer_period_ps = div_u64(PSEC_PER_SEC, timer_clk_rate); + settle_cnt = t_hs_settle_ps / timer_period_ps - 6; + + return settle_cnt; +} + +static void +phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy, + u8 settle_cnt) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + const struct mipi_csi2phy_lane_regs *r = regs->init_seq; + int i, array_size = regs->lane_array_size; + u32 val; + + for (i = 0; i < array_size; i++, r++) { + switch (r->param_type) { + case CSIPHY_SETTLE_CNT_LOWER_BYTE: + val = settle_cnt & 0xff; + break; + case CSIPHY_SKEW_CAL: + /* TODO: support application of skew from dt flag */ + continue; + default: + val = r->reg_data; + break; + } + writel(val, csi2phy->base + r->reg_addr); + if (r->delay_us) + udelay(r->delay_us); + } +} + +static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy, + struct mipi_csi2phy_stream_cfg *cfg) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg; + u8 settle_cnt; + u8 val; + int i; + + settle_cnt = phy_qcom_mipi_csi2_settle_cnt_calc(cfg->link_freq, csi2phy->timer_clk_rate); + + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + for (i = 0; i < cfg->num_data_lanes; i++) + val |= BIT(lane_cfg->data[i].pos * 2); + + writel(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5)); + + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; + writel(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6)); + + val = 0x02; + writel(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 7)); + + val = 0x00; + writel(val, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 0)); + + phy_qcom_mipi_csi2_gen2_config_lanes(csi2phy, settle_cnt); + + /* IRQ_MASK registers - disable all interrupts */ + for (i = CSI_COMMON_STATUS_NUM; i < CSI_CTRL_STATUS_INDEX; i++) { + writel(0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, i)); + } + + return 0; +} + +static void +phy_qcom_mipi_csi2_lanes_disable(struct mipi_csi2phy_device *csi2phy, + struct mipi_csi2phy_stream_cfg *cfg) +{ + const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); + + writel(0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5)); + + writel(0, csi2phy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6)); +} + +static const struct mipi_csi2phy_hw_ops phy_qcom_mipi_csi2_ops_3ph_1_0 = { + .hw_version_read = phy_qcom_mipi_csi2_hw_version_read, + .reset = phy_qcom_mipi_csi2_reset, + .lanes_enable = phy_qcom_mipi_csi2_lanes_enable, + .lanes_disable = phy_qcom_mipi_csi2_lanes_disable, +}; + +static const char * const x1e_clks[] = { + "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer" +}; + +static const char * const x1e_supplies[] = { + "vdda-0p8", + "vdda-1p2" +}; + +static const char * const x1e_genpd_names[] = { + "mx", + "mmcx", +}; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info = { + .init_seq = lane_regs_x1e80100, + .lane_array_size = ARRAY_SIZE(lane_regs_x1e80100), + .common_regs_offset = 0x1000, + .generation = GEN2, + }, + .supply_names = (const char **)x1e_supplies, + .num_supplies = ARRAY_SIZE(x1e_supplies), + .clk_names = (const char **)x1e_clks, + .num_clk = ARRAY_SIZE(x1e_clks), + .opp_clk = x1e_clks[2], + .timer_clk = x1e_clks[3], + .genpd_names = (const char **)x1e_genpd_names, + .num_genpd_names = ARRAY_SIZE(x1e_genpd_names), +}; --- linux-nvidia-7.0.0.orig/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ linux-nvidia-7.0.0/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025, Linaro Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-qcom-mipi-csi2.h" + +static int +phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy, + s64 link_freq) +{ + struct device *dev = csi2phy->dev; + unsigned long opp_rate = link_freq / 4; + struct dev_pm_opp *opp; + long timer_rate; + int ret; + + opp = dev_pm_opp_find_freq_ceil(dev, &opp_rate); + if (IS_ERR(opp)) { + dev_err(csi2phy->dev, "Couldn't find ceiling for %lld Hz\n", + link_freq); + return PTR_ERR(opp); + } + + for (int i = 0; i < csi2phy->num_pds; i++) { + unsigned int perf = dev_pm_opp_get_required_pstate(opp, i); + + ret = dev_pm_genpd_set_performance_state(csi2phy->pds[i], perf); + if (ret) { + dev_err(csi2phy->dev, "Couldn't set perf state %u\n", + perf); + dev_pm_opp_put(opp); + return ret; + } + } + dev_pm_opp_put(opp); + + ret = dev_pm_opp_set_rate(dev, opp_rate); + if (ret) { + dev_err(csi2phy->dev, "dev_pm_opp_set_rate() fail\n"); + return ret; + } + + timer_rate = clk_round_rate(csi2phy->timer_clk, link_freq / 4); + if (timer_rate < 0) + return timer_rate; + + ret = clk_set_rate(csi2phy->timer_clk, timer_rate); + if (ret) + return ret; + + csi2phy->timer_clk_rate = timer_rate; + + return 0; +} + +static int phy_qcom_mipi_csi2_configure(struct phy *phy, + union phy_configure_opts *opts) +{ + struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); + struct phy_configure_opts_mipi_dphy *dphy_cfg_opts = &opts->mipi_dphy; + struct mipi_csi2phy_stream_cfg *stream_cfg = &csi2phy->stream_cfg; + int ret; + int i; + + ret = phy_mipi_dphy_config_validate(dphy_cfg_opts); + if (ret) + return ret; + + if (dphy_cfg_opts->lanes < 1 || dphy_cfg_opts->lanes > CSI2_MAX_DATA_LANES) + return -EINVAL; + + stream_cfg->combo_mode = 0; + stream_cfg->link_freq = dphy_cfg_opts->hs_clk_rate; + stream_cfg->num_data_lanes = dphy_cfg_opts->lanes; + + /* + * phy_configure_opts_mipi_dphy.lanes starts from zero to + * the maximum number of enabled lanes. + * + * TODO: add support for bitmask of enabled lanes and polarities + * of those lanes to the phy_configure_opts_mipi_dphy struct. + * For now take the polarities as zero and the position as fixed + * this is fine as no current upstream implementation maps otherwise. + */ + for (i = 0; i < stream_cfg->num_data_lanes; i++) { + stream_cfg->lane_cfg.data[i].pol = 0; + stream_cfg->lane_cfg.data[i].pos = i; + } + + stream_cfg->lane_cfg.clk.pol = 0; + stream_cfg->lane_cfg.clk.pos = 7; + + return 0; +} + +static int phy_qcom_mipi_csi2_power_on(struct phy *phy) +{ + struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); + const struct mipi_csi2phy_hw_ops *ops = csi2phy->soc_cfg->ops; + struct device *dev = &phy->dev; + int ret; + + ret = regulator_bulk_enable(csi2phy->soc_cfg->num_supplies, + csi2phy->supplies); + if (ret) + return ret; + + ret = phy_qcom_mipi_csi2_set_clock_rates(csi2phy, csi2phy->stream_cfg.link_freq); + if (ret) + goto poweroff_phy; + + ret = clk_bulk_prepare_enable(csi2phy->soc_cfg->num_clk, + csi2phy->clks); + if (ret) { + dev_err(dev, "failed to enable clocks, %d\n", ret); + goto poweroff_phy; + } + + ops->reset(csi2phy); + + ops->hw_version_read(csi2phy); + + return ops->lanes_enable(csi2phy, &csi2phy->stream_cfg); + +poweroff_phy: + regulator_bulk_disable(csi2phy->soc_cfg->num_supplies, + csi2phy->supplies); + + return ret; +} + +static int phy_qcom_mipi_csi2_power_off(struct phy *phy) +{ + struct mipi_csi2phy_device *csi2phy = phy_get_drvdata(phy); + int i; + + for (int i = 0; i < csi2phy->num_pds; i++) + dev_pm_genpd_set_performance_state(csi2phy->pds[i], 0); + + clk_bulk_disable_unprepare(csi2phy->soc_cfg->num_clk, + csi2phy->clks); + regulator_bulk_disable(csi2phy->soc_cfg->num_supplies, + csi2phy->supplies); + + return 0; +} + +static const struct phy_ops phy_qcom_mipi_csi2_ops = { + .configure = phy_qcom_mipi_csi2_configure, + .power_on = phy_qcom_mipi_csi2_power_on, + .power_off = phy_qcom_mipi_csi2_power_off, + .owner = THIS_MODULE, +}; + +static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) +{ + unsigned int i, num_clk, num_supplies, num_pds; + struct mipi_csi2phy_device *csi2phy; + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct phy *generic_phy; + int ret; + + csi2phy = devm_kzalloc(dev, sizeof(*csi2phy), GFP_KERNEL); + if (!csi2phy) + return -ENOMEM; + + csi2phy->dev = dev; + csi2phy->soc_cfg = device_get_match_data(&pdev->dev); + + if (!csi2phy->soc_cfg) + return -EINVAL; + + num_clk = csi2phy->soc_cfg->num_clk; + csi2phy->clks = devm_kzalloc(dev, sizeof(*csi2phy->clks) * num_clk, GFP_KERNEL); + if (!csi2phy->clks) + return -ENOMEM; + + num_pds = csi2phy->soc_cfg->num_genpd_names; + if (!num_pds) + return -EINVAL; + + csi2phy->pds = devm_kzalloc(dev, sizeof(*csi2phy->pds) * num_pds, GFP_KERNEL); + if (!csi2phy->pds) + return -ENOMEM; + + for (i = 0; i < num_pds; i++) { + csi2phy->pds[i] = dev_pm_domain_attach_by_name(dev, + csi2phy->soc_cfg->genpd_names[i]); + if (IS_ERR(csi2phy->pds[i])) { + return dev_err_probe(dev, PTR_ERR(csi2phy->pds[i]), + "Failed to attach %s\n", + csi2phy->soc_cfg->genpd_names[i]); + } + } + csi2phy->num_pds = num_pds; + + for (i = 0; i < num_clk; i++) + csi2phy->clks[i].id = csi2phy->soc_cfg->clk_names[i]; + + ret = devm_clk_bulk_get(dev, num_clk, csi2phy->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + csi2phy->timer_clk = devm_clk_get(dev, csi2phy->soc_cfg->timer_clk); + if (IS_ERR(csi2phy->timer_clk)) { + return dev_err_probe(dev, PTR_ERR(csi2phy->timer_clk), + "Failed to get timer clock\n"); + } + + ret = devm_pm_opp_set_clkname(dev, csi2phy->soc_cfg->opp_clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to set opp clkname\n"); + + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) + return dev_err_probe(dev, ret, "invalid OPP table in device tree\n"); + + num_supplies = csi2phy->soc_cfg->num_supplies; + csi2phy->supplies = devm_kzalloc(dev, sizeof(*csi2phy->supplies) * num_supplies, + GFP_KERNEL); + if (!csi2phy->supplies) + return -ENOMEM; + + for (i = 0; i < num_supplies; i++) + csi2phy->supplies[i].supply = csi2phy->soc_cfg->supply_names[i]; + + ret = devm_regulator_bulk_get(dev, num_supplies, csi2phy->supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); + + csi2phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(csi2phy->base)) + return PTR_ERR(csi2phy->base); + + generic_phy = devm_phy_create(dev, NULL, &phy_qcom_mipi_csi2_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + return dev_err_probe(dev, ret, "failed to create phy\n"); + } + csi2phy->phy = generic_phy; + + phy_set_drvdata(generic_phy, csi2phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_dbg(dev, "Registered MIPI CSI2 PHY device\n"); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = { + { .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e }, + { } +}; +MODULE_DEVICE_TABLE(of, phy_qcom_mipi_csi2_of_match_table); + +static struct platform_driver phy_qcom_mipi_csi2_driver = { + .probe = phy_qcom_mipi_csi2_probe, + .driver = { + .name = "qcom-mipi-csi2-phy", + .of_match_table = phy_qcom_mipi_csi2_of_match_table, + }, +}; + +module_platform_driver(phy_qcom_mipi_csi2_driver); + +MODULE_DESCRIPTION("Qualcomm MIPI CSI2 PHY driver"); +MODULE_AUTHOR("Bryan O'Donoghue "); +MODULE_LICENSE("GPL"); --- linux-nvidia-7.0.0.orig/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ linux-nvidia-7.0.0/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * + * Qualcomm MIPI CSI2 CPHY/DPHY driver + * + * Copyright (C) 2025 Linaro Ltd. + */ +#ifndef __PHY_QCOM_MIPI_CSI2_H__ +#define __PHY_QCOM_MIPI_CSI2_H__ + +#include + +#define CSI2_MAX_DATA_LANES 4 + +struct mipi_csi2phy_lane { + u8 pos; + u8 pol; +}; + +struct mipi_csi2phy_lanes_cfg { + struct mipi_csi2phy_lane data[CSI2_MAX_DATA_LANES]; + struct mipi_csi2phy_lane clk; +}; + +struct mipi_csi2phy_stream_cfg { + u8 combo_mode; + s64 link_freq; + u8 num_data_lanes; + struct mipi_csi2phy_lanes_cfg lane_cfg; +}; + +struct mipi_csi2phy_device; + +struct mipi_csi2phy_hw_ops { + void (*hw_version_read)(struct mipi_csi2phy_device *csi2phy_dev); + void (*reset)(struct mipi_csi2phy_device *csi2phy_dev); + int (*lanes_enable)(struct mipi_csi2phy_device *csi2phy_dev, + struct mipi_csi2phy_stream_cfg *cfg); + void (*lanes_disable)(struct mipi_csi2phy_device *csi2phy_dev, + struct mipi_csi2phy_stream_cfg *cfg); +}; + +struct mipi_csi2phy_lane_regs { + const s32 reg_addr; + const s32 reg_data; + const u32 delay_us; + const u32 param_type; +}; + +struct mipi_csi2phy_device_regs { + const struct mipi_csi2phy_lane_regs *init_seq; + const int lane_array_size; + const u32 common_regs_offset; + enum { + GEN1 = 0, + GEN1_660, + GEN1_670, + GEN2, + } generation; +}; + +struct mipi_csi2phy_soc_cfg { + const struct mipi_csi2phy_hw_ops *ops; + const struct mipi_csi2phy_device_regs reg_info; + + const char ** const supply_names; + const unsigned int num_supplies; + + const char ** const clk_names; + const unsigned int num_clk; + + const char * const opp_clk; + const char * const timer_clk; + + const char ** const genpd_names; + const unsigned int num_genpd_names; +}; + +struct mipi_csi2phy_device { + struct device *dev; + + struct phy *phy; + void __iomem *base; + + struct clk_bulk_data *clks; + struct clk *timer_clk; + u32 timer_clk_rate; + + struct regulator_bulk_data *supplies; + struct device **pds; + unsigned int num_pds; + + const struct mipi_csi2phy_soc_cfg *soc_cfg; + struct mipi_csi2phy_stream_cfg stream_cfg; + + u32 hw_version; +}; + +extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; + +#endif /* __PHY_QCOM_MIPI_CSI2_H__ */ --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/Kconfig +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/Kconfig @@ -281,6 +281,18 @@ In MTK platform, we support virtual gpio and use it to map specific eint which doesn't have real gpio pin. +config PINCTRL_MT8901 + bool "MediaTek MT8901 pin control" + depends on ACPI + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on MediaTek MT8901 SoC. + In MTK platform, we support virtual gpio and use it to + map specific eint which doesn't have real gpio pin. + config PINCTRL_MT8192 bool "MediaTek MT8192 pin control" depends on OF --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/Makefile +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o +obj-$(CONFIG_PINCTRL_MT8901) += pinctrl-mt8901.o --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/mtk-eint.c +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/mtk-eint.c @@ -71,6 +71,10 @@ }; EXPORT_SYMBOL_GPL(debounce_time_mt6878); +const unsigned int debounce_time_mt8901[] = { + 156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0}; +EXPORT_SYMBOL_GPL(debounce_time_mt8901); + static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, unsigned int eint_num, unsigned int offset) --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/mtk-eint.h +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/mtk-eint.h @@ -53,6 +53,7 @@ extern const unsigned int debounce_time_mt6765[]; extern const unsigned int debounce_time_mt6795[]; extern const unsigned int debounce_time_mt6878[]; +extern const unsigned int debounce_time_mt8901[]; struct mtk_eint; --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/pinctrl-mt8901.c +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/pinctrl-mt8901.c @@ -0,0 +1,1460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + */ + +#include +#include +#include "pinctrl-mtk-mt8901.h" +#include "pinctrl-paris.h" + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0) +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt8901_pin_mode_range[] = { + PIN_FIELD(0, 181, 0x0300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8901_pin_dir_range[] = { + PIN_FIELD(0, 181, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_di_range[] = { + PIN_FIELD(0, 181, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_do_range[] = { + PIN_FIELD(0, 181, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 8, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 8, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 8, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 8, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, 8, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, 8, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(8, 8, 2, 0x0120, 0x10, 13, 1), + PIN_FIELD_BASE(9, 9, 2, 0x0120, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 2, 0x0120, 0x10, 15, 1), + PIN_FIELD_BASE(11, 11, 2, 0x0120, 0x10, 16, 1), + PIN_FIELD_BASE(12, 12, 1, 0x0140, 0x10, 17, 1), + PIN_FIELD_BASE(13, 13, 1, 0x0140, 0x10, 18, 1), + PIN_FIELD_BASE(14, 14, 1, 0x0140, 0x10, 14, 1), + PIN_FIELD_BASE(15, 15, 1, 0x0140, 0x10, 16, 1), + PIN_FIELD_BASE(16, 16, 1, 0x0140, 0x10, 19, 1), + PIN_FIELD_BASE(17, 17, 1, 0x0140, 0x10, 20, 1), + PIN_FIELD_BASE(18, 18, 1, 0x0140, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 1, 0x0140, 0x10, 27, 1), + PIN_FIELD_BASE(20, 20, 1, 0x0140, 0x10, 28, 1), + PIN_FIELD_BASE(21, 21, 1, 0x0140, 0x10, 26, 1), + PIN_FIELD_BASE(22, 22, 1, 0x0140, 0x10, 25, 1), + PIN_FIELD_BASE(23, 23, 1, 0x0140, 0x10, 0, 1), + PIN_FIELD_BASE(24, 24, 1, 0x0140, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 1, 0x0140, 0x10, 2, 1), + PIN_FIELD_BASE(26, 26, 1, 0x0140, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 1, 0x0140, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 1, 0x0140, 0x10, 5, 1), + PIN_FIELD_BASE(29, 29, 1, 0x0140, 0x10, 6, 1), + PIN_FIELD_BASE(30, 30, 1, 0x0140, 0x10, 7, 1), + PIN_FIELD_BASE(31, 31, 1, 0x0140, 0x10, 8, 1), + PIN_FIELD_BASE(32, 32, 9, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0140, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0140, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0140, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 9, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(39, 39, 1, 0x0140, 0x10, 12, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0120, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0120, 0x10, 2, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0120, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, 2, 0x0120, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 2, 0x0120, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0140, 0x10, 13, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0140, 0x10, 15, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0120, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0120, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0120, 0x10, 9, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0120, 0x10, 10, 1), + PIN_FIELD_BASE(52, 52, 2, 0x0120, 0x10, 11, 1), + PIN_FIELD_BASE(53, 53, 2, 0x0120, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0120, 0x10, 10, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0120, 0x10, 11, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0140, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 1, 0x0140, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 1, 0x0140, 0x10, 24, 1), + PIN_FIELD_BASE(59, 59, 2, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, 9, 0x0100, 0x10, 1, 1), + PIN_FIELD_BASE(61, 61, 9, 0x0100, 0x10, 2, 1), + PIN_FIELD_BASE(62, 62, 9, 0x0100, 0x10, 3, 1), + PIN_FIELD_BASE(63, 63, 9, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(64, 64, 9, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(65, 65, 9, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(66, 66, 5, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(67, 67, 5, 0x0120, 0x10, 1, 1), + PIN_FIELD_BASE(68, 68, 9, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(69, 69, 7, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, 7, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(71, 71, 7, 0x0110, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 7, 0x0110, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 7, 0x0110, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 7, 0x0110, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 7, 0x0110, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 7, 0x0110, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 7, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 7, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 7, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(80, 80, 7, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(81, 81, 7, 0x0110, 0x10, 12, 1), + PIN_FIELD_BASE(82, 82, 7, 0x0110, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 7, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 7, 0x0110, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 7, 0x0110, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 7, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 7, 0x0110, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 7, 0x0110, 0x10, 19, 1), + PIN_FIELD_BASE(89, 89, 7, 0x0110, 0x10, 20, 1), + PIN_FIELD_BASE(90, 90, 7, 0x0110, 0x10, 21, 1), + PIN_FIELD_BASE(91, 91, 7, 0x0110, 0x10, 22, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0130, 0x10, 16, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0130, 0x10, 17, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0130, 0x10, 18, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0130, 0x10, 19, 1), + PIN_FIELD_BASE(96, 96, 3, 0x0130, 0x10, 20, 1), + PIN_FIELD_BASE(97, 97, 3, 0x0130, 0x10, 21, 1), + PIN_FIELD_BASE(98, 98, 3, 0x0130, 0x10, 22, 1), + PIN_FIELD_BASE(99, 99, 3, 0x0130, 0x10, 23, 1), + PIN_FIELD_BASE(100, 100, 3, 0x0130, 0x10, 24, 1), + PIN_FIELD_BASE(101, 101, 3, 0x0130, 0x10, 25, 1), + PIN_FIELD_BASE(102, 102, 3, 0x0130, 0x10, 26, 1), + PIN_FIELD_BASE(103, 103, 3, 0x0130, 0x10, 27, 1), + PIN_FIELD_BASE(104, 104, 3, 0x0130, 0x10, 28, 1), + PIN_FIELD_BASE(105, 105, 3, 0x0130, 0x10, 29, 1), + PIN_FIELD_BASE(106, 106, 8, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(107, 107, 8, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(108, 108, 8, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 8, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(110, 110, 8, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(111, 111, 8, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0120, 0x10, 15, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0120, 0x10, 16, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0120, 0x10, 19, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0110, 0x10, 12, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0110, 0x10, 13, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0110, 0x10, 15, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0110, 0x10, 16, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0120, 0x10, 6, 1), + PIN_FIELD_BASE(127, 127, 5, 0x0120, 0x10, 7, 1), + PIN_FIELD_BASE(128, 128, 5, 0x0120, 0x10, 8, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0120, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0110, 0x10, 18, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0110, 0x10, 19, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0110, 0x10, 20, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0130, 0x10, 0, 1), + PIN_FIELD_BASE(135, 135, 3, 0x0130, 0x10, 1, 1), + PIN_FIELD_BASE(136, 136, 3, 0x0130, 0x10, 2, 1), + PIN_FIELD_BASE(137, 137, 3, 0x0130, 0x10, 3, 1), + PIN_FIELD_BASE(138, 138, 3, 0x0130, 0x10, 4, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0130, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0130, 0x10, 6, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0130, 0x10, 7, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0130, 0x10, 8, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0130, 0x10, 9, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0130, 0x10, 10, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0130, 0x10, 12, 1), + PIN_FIELD_BASE(147, 147, 3, 0x0130, 0x10, 13, 1), + PIN_FIELD_BASE(148, 148, 3, 0x0130, 0x10, 14, 1), + PIN_FIELD_BASE(149, 149, 3, 0x0130, 0x10, 15, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0110, 0x10, 21, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0110, 0x10, 26, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0110, 0x10, 25, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0110, 0x10, 24, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0110, 0x10, 22, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0110, 0x10, 23, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 4, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 4, 0x0110, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 4, 0x0110, 0x10, 3, 1), + PIN_FIELD_BASE(160, 160, 4, 0x0110, 0x10, 4, 1), + PIN_FIELD_BASE(161, 161, 4, 0x0110, 0x10, 5, 1), + PIN_FIELD_BASE(162, 162, 4, 0x0110, 0x10, 6, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0110, 0x10, 7, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0120, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 5, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 5, 0x0120, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 5, 0x0120, 0x10, 2, 1), + PIN_FIELD_BASE(168, 168, 5, 0x0120, 0x10, 13, 1), + PIN_FIELD_BASE(169, 169, 5, 0x0120, 0x10, 14, 1), + PIN_FIELD_BASE(170, 170, 5, 0x0120, 0x10, 5, 1), + PIN_FIELD_BASE(171, 171, 6, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(172, 172, 6, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(173, 173, 6, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(174, 174, 6, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 6, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 6, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 6, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(178, 178, 6, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(179, 179, 6, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(180, 180, 6, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(181, 181, 10, 0x0080, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(8, 8, 2, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(9, 9, 2, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 2, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(11, 11, 2, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(12, 12, 1, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(13, 13, 1, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(14, 14, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(15, 15, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(16, 16, 1, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(17, 17, 1, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(18, 18, 1, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 1, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(20, 20, 1, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(21, 21, 1, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(22, 22, 1, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(23, 23, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(24, 24, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(26, 26, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(29, 29, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(30, 30, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(31, 31, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(32, 32, 9, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 9, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(39, 39, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, 2, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 2, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(52, 52, 2, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(53, 53, 2, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 1, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 1, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(59, 59, 2, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, 9, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(61, 61, 9, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(62, 62, 9, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(63, 63, 9, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(64, 64, 9, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(65, 65, 9, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(66, 66, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(67, 67, 5, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(68, 68, 9, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(69, 69, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(71, 71, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 7, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 7, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 7, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(80, 80, 7, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(81, 81, 7, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(82, 82, 7, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 7, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 7, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 7, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 7, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 7, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 7, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(89, 89, 7, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(90, 90, 7, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(91, 91, 7, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(96, 96, 3, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(97, 97, 3, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(98, 98, 3, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(99, 99, 3, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(100, 100, 3, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(101, 101, 3, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(102, 102, 3, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(103, 103, 3, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(104, 104, 3, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(105, 105, 3, 0x0080, 0x10, 29, 1), + PIN_FIELD_BASE(106, 106, 8, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(107, 107, 8, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(108, 108, 8, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 8, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(110, 110, 8, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(111, 111, 8, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(127, 127, 5, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(128, 128, 5, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(135, 135, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(136, 136, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(137, 137, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(138, 138, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(147, 147, 3, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(148, 148, 3, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(149, 149, 3, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 4, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 4, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 4, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(160, 160, 4, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(161, 161, 4, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(162, 162, 4, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 5, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 5, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(168, 168, 5, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(169, 169, 5, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(170, 170, 5, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(171, 171, 6, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(172, 172, 6, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(173, 173, 6, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(181, 181, 10, 0x0020, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(14, 14, 1, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(15, 15, 1, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(16, 16, 1, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(19, 19, 1, 0x00c0, 0x10, 21, 1), + PIN_FIELD_BASE(20, 20, 1, 0x00c0, 0x10, 22, 1), + PIN_FIELD_BASE(21, 21, 1, 0x00c0, 0x10, 20, 1), + PIN_FIELD_BASE(22, 22, 1, 0x00c0, 0x10, 19, 1), + PIN_FIELD_BASE(23, 23, 1, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(24, 24, 1, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 1, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(26, 26, 1, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 1, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 1, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(29, 29, 1, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(30, 30, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(31, 31, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(32, 32, 9, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(33, 33, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 9, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(37, 37, 2, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(40, 40, 2, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 2, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 2, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(43, 43, 2, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(44, 44, 2, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(45, 45, 2, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(46, 46, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(47, 47, 1, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(48, 48, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(50, 50, 2, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(51, 51, 2, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 1, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(62, 62, 9, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(63, 63, 9, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(64, 64, 9, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(65, 65, 9, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(68, 68, 9, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(74, 74, 7, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(75, 75, 7, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(76, 76, 7, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(77, 77, 7, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(78, 78, 7, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(79, 79, 7, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(80, 80, 7, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(81, 81, 7, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(82, 82, 7, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(83, 83, 7, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 7, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(85, 85, 7, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(86, 86, 7, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(87, 87, 7, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(90, 90, 7, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(91, 91, 7, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(94, 94, 3, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(95, 95, 3, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(96, 96, 3, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(97, 97, 3, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(98, 98, 3, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(99, 99, 3, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(100, 100, 3, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(101, 101, 3, 0x00c0, 0x10, 19, 1), + PIN_FIELD_BASE(102, 102, 3, 0x00c0, 0x10, 20, 1), + PIN_FIELD_BASE(103, 103, 3, 0x00c0, 0x10, 21, 1), + PIN_FIELD_BASE(104, 104, 3, 0x00c0, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, 3, 0x00c0, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, 8, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(107, 107, 8, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(108, 108, 8, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 8, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(110, 110, 8, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(111, 111, 8, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(113, 113, 5, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(116, 116, 5, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(130, 130, 4, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(131, 131, 4, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 4, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 4, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, 3, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(147, 147, 3, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(148, 148, 3, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(149, 149, 3, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(150, 150, 4, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(151, 151, 4, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(152, 152, 4, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(153, 153, 4, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(154, 154, 4, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(155, 155, 4, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(156, 156, 4, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 4, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 4, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 4, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(160, 160, 4, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(161, 161, 4, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(162, 162, 4, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(163, 163, 4, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(167, 167, 5, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(168, 168, 5, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(169, 169, 5, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(170, 170, 5, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(171, 171, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(172, 172, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(173, 173, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(14, 14, 1, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(15, 15, 1, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(16, 16, 1, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(19, 19, 1, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(20, 20, 1, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(21, 21, 1, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(22, 22, 1, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(23, 23, 1, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(24, 24, 1, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 1, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(26, 26, 1, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 1, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 1, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(29, 29, 1, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(30, 30, 1, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(31, 31, 1, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(32, 32, 9, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(33, 33, 1, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 9, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(37, 37, 2, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 1, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(40, 40, 2, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 2, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 2, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(43, 43, 2, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(44, 44, 2, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(45, 45, 2, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(46, 46, 1, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(47, 47, 1, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(48, 48, 2, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 2, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(50, 50, 2, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(51, 51, 2, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 1, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(62, 62, 9, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(63, 63, 9, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(64, 64, 9, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(65, 65, 9, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(68, 68, 9, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(74, 74, 7, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(75, 75, 7, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(76, 76, 7, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(77, 77, 7, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(78, 78, 7, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(79, 79, 7, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(80, 80, 7, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(81, 81, 7, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(82, 82, 7, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(83, 83, 7, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 7, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(85, 85, 7, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(86, 86, 7, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(90, 90, 7, 0x00d0, 0x10, 14, 1), + PIN_FIELD_BASE(91, 91, 7, 0x00d0, 0x10, 15, 1), + PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(96, 96, 3, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(97, 97, 3, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(98, 98, 3, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(99, 99, 3, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(100, 100, 3, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(101, 101, 3, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(102, 102, 3, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(103, 103, 3, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(104, 104, 3, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, 3, 0x00e0, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, 8, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(107, 107, 8, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(108, 108, 8, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 8, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(110, 110, 8, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(111, 111, 8, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(113, 113, 5, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(116, 116, 5, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(130, 130, 4, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(131, 131, 4, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 4, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 4, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, 3, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(147, 147, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(148, 148, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(149, 149, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(150, 150, 4, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(151, 151, 4, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(152, 152, 4, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(153, 153, 4, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(154, 154, 4, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(155, 155, 4, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(156, 156, 4, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 4, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 4, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 4, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(160, 160, 4, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(161, 161, 4, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(162, 162, 4, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(163, 163, 4, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(167, 167, 5, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(168, 168, 5, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(169, 169, 5, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(170, 170, 5, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(171, 171, 6, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(172, 172, 6, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(173, 173, 6, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0090, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 8, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 8, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 8, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 8, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, 8, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, 8, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(14, 14, 1, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(15, 15, 1, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(16, 16, 1, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(19, 19, 1, 0x00f0, 0x10, 21, 1), + PIN_FIELD_BASE(20, 20, 1, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(21, 21, 1, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(22, 22, 1, 0x00f0, 0x10, 19, 1), + PIN_FIELD_BASE(23, 23, 1, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(24, 24, 1, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 1, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(26, 26, 1, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 1, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 1, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(29, 29, 1, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(30, 30, 1, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(31, 31, 1, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(32, 32, 9, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(33, 33, 1, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 9, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(37, 37, 2, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(40, 40, 2, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 2, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 2, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(43, 43, 2, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(44, 44, 2, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(45, 45, 2, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(46, 46, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(47, 47, 1, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(48, 48, 2, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 2, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(50, 50, 2, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(51, 51, 2, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 1, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(62, 62, 9, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(63, 63, 9, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(64, 64, 9, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(65, 65, 9, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(68, 68, 9, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(74, 74, 7, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(75, 75, 7, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(76, 76, 7, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(77, 77, 7, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(78, 78, 7, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(79, 79, 7, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(80, 80, 7, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(81, 81, 7, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(82, 82, 7, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(83, 83, 7, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 7, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(87, 87, 7, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(90, 90, 7, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(91, 91, 7, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(94, 94, 3, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(95, 95, 3, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(96, 96, 3, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(97, 97, 3, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(98, 98, 3, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(99, 99, 3, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(100, 100, 3, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(101, 101, 3, 0x00f0, 0x10, 19, 1), + PIN_FIELD_BASE(102, 102, 3, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(103, 103, 3, 0x00f0, 0x10, 21, 1), + PIN_FIELD_BASE(104, 104, 3, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, 3, 0x00f0, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, 8, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(107, 107, 8, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(108, 108, 8, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 8, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(110, 110, 8, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(111, 111, 8, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(113, 113, 5, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(116, 116, 5, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(130, 130, 4, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(131, 131, 4, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 4, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, 3, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(147, 147, 3, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(148, 148, 3, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(149, 149, 3, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(150, 150, 4, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(151, 151, 4, 0x00d0, 0x10, 18, 1), + PIN_FIELD_BASE(152, 152, 4, 0x00d0, 0x10, 17, 1), + PIN_FIELD_BASE(153, 153, 4, 0x00d0, 0x10, 16, 1), + PIN_FIELD_BASE(154, 154, 4, 0x00d0, 0x10, 14, 1), + PIN_FIELD_BASE(155, 155, 4, 0x00d0, 0x10, 15, 1), + PIN_FIELD_BASE(156, 156, 4, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 4, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 4, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 4, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(160, 160, 4, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(161, 161, 4, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(162, 162, 4, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(163, 163, 4, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(167, 167, 5, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(168, 168, 5, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(169, 169, 5, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(170, 170, 5, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(171, 171, 6, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(172, 172, 6, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(173, 173, 6, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(174, 174, 6, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 6, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(176, 176, 6, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(177, 177, 6, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(178, 178, 6, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(179, 179, 6, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(180, 180, 6, 0x00a0, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_pu_range[] = { + PIN_FIELD_BASE(8, 8, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(9, 9, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(10, 10, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(11, 11, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(12, 12, 1, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(13, 13, 1, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 1, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(18, 18, 1, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(54, 54, 5, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(55, 55, 5, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(56, 56, 1, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(57, 57, 1, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(59, 59, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, 9, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(61, 61, 9, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(67, 67, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(69, 69, 7, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, 7, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(71, 71, 7, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 7, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 7, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(88, 88, 7, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(89, 89, 7, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 3, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(93, 93, 3, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(117, 117, 4, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(126, 126, 5, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(127, 127, 5, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(128, 128, 5, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(129, 129, 5, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(135, 135, 3, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(136, 136, 3, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(137, 137, 3, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(165, 165, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(166, 166, 5, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(181, 181, 10, 0x0060, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_pd_range[] = { + PIN_FIELD_BASE(8, 8, 2, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(9, 9, 2, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(10, 10, 2, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(11, 11, 2, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(12, 12, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(13, 13, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 1, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(18, 18, 1, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, 2, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 2, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(56, 56, 1, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(57, 57, 1, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(59, 59, 2, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(60, 60, 9, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(61, 61, 9, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(67, 67, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(69, 69, 7, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, 7, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(71, 71, 7, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 7, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 7, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(88, 88, 7, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(89, 89, 7, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 3, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(93, 93, 3, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(127, 127, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(128, 128, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(135, 135, 3, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(136, 136, 3, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(137, 137, 3, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(165, 165, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(166, 166, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(181, 181, 10, 0x0050, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8901_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(2, 2, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(3, 3, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(4, 4, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(5, 5, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(6, 6, 8, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(7, 7, 8, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(8, 8, 2, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(9, 9, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(10, 10, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(11, 11, 2, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(12, 12, 1, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(13, 13, 1, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(14, 14, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(15, 15, 1, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(16, 16, 1, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(17, 17, 1, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(18, 18, 1, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(19, 19, 1, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(20, 20, 1, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(21, 21, 1, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(22, 22, 1, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(23, 23, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(25, 25, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(26, 26, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(27, 27, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(28, 28, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(29, 29, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(30, 30, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(31, 31, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(32, 32, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(33, 33, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(34, 34, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(36, 36, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(37, 37, 2, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(38, 38, 2, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(39, 39, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(45, 45, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(46, 46, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(47, 47, 1, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(51, 51, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(52, 52, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(53, 53, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(55, 55, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 1, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(57, 57, 1, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(58, 58, 1, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(59, 59, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(60, 60, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(61, 61, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(62, 62, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(63, 63, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(64, 64, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(65, 65, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(66, 66, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(67, 67, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(68, 68, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(69, 69, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(70, 70, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(71, 71, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(72, 72, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(73, 73, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(74, 74, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(75, 75, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(76, 76, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(77, 77, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(78, 78, 7, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(79, 79, 7, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(80, 80, 7, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(81, 81, 7, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(82, 82, 7, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(83, 83, 7, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(84, 84, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(85, 85, 7, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(86, 86, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(87, 87, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(88, 88, 7, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(89, 89, 7, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(90, 90, 7, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(91, 91, 7, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(96, 96, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(97, 97, 3, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(98, 98, 3, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(99, 99, 3, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(100, 100, 3, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(101, 101, 3, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(102, 102, 3, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(103, 103, 3, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(104, 104, 3, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(105, 105, 3, 0x0020, 0x10, 27, 3), + PIN_FIELD_BASE(106, 106, 8, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(107, 107, 8, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(108, 108, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(109, 109, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(110, 110, 8, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(111, 111, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(112, 112, 5, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(113, 113, 5, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(114, 114, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(115, 115, 5, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(116, 116, 5, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(117, 117, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(118, 118, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(119, 119, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(120, 120, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(121, 121, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(125, 125, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(127, 127, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(128, 128, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(129, 129, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(130, 130, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(131, 131, 4, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(132, 132, 4, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(133, 133, 4, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(134, 134, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(135, 135, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(136, 136, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(137, 137, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(138, 138, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(139, 139, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(140, 140, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(143, 143, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(144, 144, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(145, 145, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(146, 146, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(147, 147, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(148, 148, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(149, 149, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(157, 157, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(158, 158, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(159, 159, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(160, 160, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(161, 161, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(162, 162, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(163, 163, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(164, 164, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(165, 165, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(166, 166, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(167, 167, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(168, 168, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(169, 169, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(171, 171, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(172, 172, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(173, 173, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(181, 181, 10, 0x0000, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt8901_pin_drv_adv_range[] = { + PIN_FIELD_BASE(8, 8, 2, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, 2, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(10, 10, 2, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(11, 11, 2, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(12, 12, 1, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(13, 13, 1, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(17, 17, 1, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(18, 18, 1, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(52, 52, 2, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(53, 53, 2, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(54, 54, 5, 0x0030, 0x10, 24, 3), + PIN_FIELD_BASE(55, 55, 5, 0x0030, 0x10, 27, 3), + PIN_FIELD_BASE(56, 56, 1, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(57, 57, 1, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(60, 60, 9, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(61, 61, 9, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(66, 66, 5, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(67, 67, 5, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, 7, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, 7, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(72, 72, 7, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(73, 73, 7, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(88, 88, 7, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(89, 89, 7, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(117, 117, 4, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(118, 118, 4, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(119, 119, 4, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(120, 120, 4, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(121, 121, 4, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 18, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0030, 0x10, 21, 3), + PIN_FIELD_BASE(126, 126, 5, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(127, 127, 5, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(128, 128, 5, 0x0030, 0x10, 18, 3), + PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 21, 3), + PIN_FIELD_BASE(134, 134, 3, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(135, 135, 3, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(136, 136, 3, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(137, 137, 3, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(165, 165, 5, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(166, 166, 5, 0x0030, 0x10, 9, 3), +}; + +static const struct mtk_pin_field_calc mt8901_pin_rsel_range[] = { + PIN_FIELD_BASE(8, 8, 2, 0x0110, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, 2, 0x0110, 0x10, 9, 3), + PIN_FIELD_BASE(10, 10, 2, 0x0110, 0x10, 12, 3), + PIN_FIELD_BASE(11, 11, 2, 0x0110, 0x10, 15, 3), + PIN_FIELD_BASE(12, 12, 1, 0x0130, 0x10, 0, 1), + PIN_FIELD_BASE(13, 13, 1, 0x0130, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 1, 0x0130, 0x10, 2, 1), + PIN_FIELD_BASE(18, 18, 1, 0x0130, 0x10, 3, 1), + PIN_FIELD_BASE(52, 52, 2, 0x0110, 0x10, 0, 3), + PIN_FIELD_BASE(53, 53, 2, 0x0110, 0x10, 3, 3), + PIN_FIELD_BASE(54, 54, 5, 0x0110, 0x10, 12, 3), + PIN_FIELD_BASE(55, 55, 5, 0x0110, 0x10, 15, 3), + PIN_FIELD_BASE(56, 56, 1, 0x0130, 0x10, 4, 1), + PIN_FIELD_BASE(57, 57, 1, 0x0130, 0x10, 5, 1), + PIN_FIELD_BASE(60, 60, 9, 0x00f0, 0x10, 0, 3), + PIN_FIELD_BASE(61, 61, 9, 0x00f0, 0x10, 3, 3), + PIN_FIELD_BASE(66, 66, 5, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(67, 67, 5, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 7, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, 7, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(72, 72, 7, 0x0100, 0x10, 6, 3), + PIN_FIELD_BASE(73, 73, 7, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(88, 88, 7, 0x0100, 0x10, 12, 3), + PIN_FIELD_BASE(89, 89, 7, 0x0100, 0x10, 15, 3), + PIN_FIELD_BASE(92, 92, 3, 0x0120, 0x10, 12, 3), + PIN_FIELD_BASE(93, 93, 3, 0x0120, 0x10, 15, 3), + PIN_FIELD_BASE(117, 117, 4, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(118, 118, 4, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(119, 119, 4, 0x0100, 0x10, 6, 3), + PIN_FIELD_BASE(120, 120, 4, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(121, 121, 4, 0x0100, 0x10, 12, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0100, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0100, 0x10, 18, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0100, 0x10, 21, 3), + PIN_FIELD_BASE(126, 126, 5, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(127, 127, 5, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(128, 128, 5, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0120, 0x10, 0, 3), + PIN_FIELD_BASE(135, 135, 3, 0x0120, 0x10, 3, 3), + PIN_FIELD_BASE(136, 136, 3, 0x0120, 0x10, 6, 3), + PIN_FIELD_BASE(137, 137, 3, 0x0120, 0x10, 9, 3), + PIN_FIELD_BASE(165, 165, 5, 0x0110, 0x10, 2, 3), + PIN_FIELD_BASE(166, 166, 5, 0x0110, 0x10, 5, 3), +}; + +static const struct mtk_pin_rsel mt8901_pin_rsel_val_range[] = { + 0 +}; + +static const unsigned int mt8901_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE, /*0*/ + MTK_PULL_PUPD_R1R0_TYPE, /*1*/ + MTK_PULL_PUPD_R1R0_TYPE, /*2*/ + MTK_PULL_PUPD_R1R0_TYPE, /*3*/ + MTK_PULL_PUPD_R1R0_TYPE, /*4*/ + MTK_PULL_PUPD_R1R0_TYPE, /*5*/ + MTK_PULL_PUPD_R1R0_TYPE, /*6*/ + MTK_PULL_PUPD_R1R0_TYPE, /*7*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*8*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*9*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*10*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*11*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*12*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*13*/ + MTK_PULL_PUPD_R1R0_TYPE, /*14*/ + MTK_PULL_PUPD_R1R0_TYPE, /*15*/ + MTK_PULL_PUPD_R1R0_TYPE, /*16*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*17*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*18*/ + MTK_PULL_PUPD_R1R0_TYPE, /*19*/ + MTK_PULL_PUPD_R1R0_TYPE, /*20*/ + MTK_PULL_PUPD_R1R0_TYPE, /*21*/ + MTK_PULL_PUPD_R1R0_TYPE, /*22*/ + MTK_PULL_PUPD_R1R0_TYPE, /*23*/ + MTK_PULL_PUPD_R1R0_TYPE, /*24*/ + MTK_PULL_PUPD_R1R0_TYPE, /*25*/ + MTK_PULL_PUPD_R1R0_TYPE, /*26*/ + MTK_PULL_PUPD_R1R0_TYPE, /*27*/ + MTK_PULL_PUPD_R1R0_TYPE, /*28*/ + MTK_PULL_PUPD_R1R0_TYPE, /*29*/ + MTK_PULL_PUPD_R1R0_TYPE, /*30*/ + MTK_PULL_PUPD_R1R0_TYPE, /*31*/ + MTK_PULL_PUPD_R1R0_TYPE, /*32*/ + MTK_PULL_PUPD_R1R0_TYPE, /*33*/ + MTK_PULL_PUPD_R1R0_TYPE, /*34*/ + MTK_PULL_PUPD_R1R0_TYPE, /*35*/ + MTK_PULL_PUPD_R1R0_TYPE, /*36*/ + MTK_PULL_PUPD_R1R0_TYPE, /*37*/ + MTK_PULL_PUPD_R1R0_TYPE, /*38*/ + MTK_PULL_PUPD_R1R0_TYPE, /*39*/ + MTK_PULL_PUPD_R1R0_TYPE, /*40*/ + MTK_PULL_PUPD_R1R0_TYPE, /*41*/ + MTK_PULL_PUPD_R1R0_TYPE, /*42*/ + MTK_PULL_PUPD_R1R0_TYPE, /*43*/ + MTK_PULL_PUPD_R1R0_TYPE, /*44*/ + MTK_PULL_PUPD_R1R0_TYPE, /*45*/ + MTK_PULL_PUPD_R1R0_TYPE, /*46*/ + MTK_PULL_PUPD_R1R0_TYPE, /*47*/ + MTK_PULL_PUPD_R1R0_TYPE, /*48*/ + MTK_PULL_PUPD_R1R0_TYPE, /*49*/ + MTK_PULL_PUPD_R1R0_TYPE, /*50*/ + MTK_PULL_PUPD_R1R0_TYPE, /*51*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*52*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*53*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*54*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*55*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*56*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*57*/ + MTK_PULL_PUPD_R1R0_TYPE, /*58*/ + MTK_PULL_PU_PD_TYPE, /*59*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*60*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*61*/ + MTK_PULL_PUPD_R1R0_TYPE, /*62*/ + MTK_PULL_PUPD_R1R0_TYPE, /*63*/ + MTK_PULL_PUPD_R1R0_TYPE, /*64*/ + MTK_PULL_PUPD_R1R0_TYPE, /*65*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*66*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*67*/ + MTK_PULL_PUPD_R1R0_TYPE, /*68*/ + MTK_PULL_PU_PD_TYPE, /*69*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*70*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*71*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*72*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*73*/ + MTK_PULL_PUPD_R1R0_TYPE, /*74*/ + MTK_PULL_PUPD_R1R0_TYPE, /*75*/ + MTK_PULL_PUPD_R1R0_TYPE, /*76*/ + MTK_PULL_PUPD_R1R0_TYPE, /*77*/ + MTK_PULL_PUPD_R1R0_TYPE, /*78*/ + MTK_PULL_PUPD_R1R0_TYPE, /*79*/ + MTK_PULL_PUPD_R1R0_TYPE, /*80*/ + MTK_PULL_PUPD_R1R0_TYPE, /*81*/ + MTK_PULL_PUPD_R1R0_TYPE, /*82*/ + MTK_PULL_PUPD_R1R0_TYPE, /*83*/ + MTK_PULL_PUPD_R1R0_TYPE, /*84*/ + MTK_PULL_PUPD_R1R0_TYPE, /*85*/ + MTK_PULL_PUPD_R1R0_TYPE, /*86*/ + MTK_PULL_PUPD_R1R0_TYPE, /*87*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*88*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*89*/ + MTK_PULL_PUPD_R1R0_TYPE, /*90*/ + MTK_PULL_PUPD_R1R0_TYPE, /*91*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*92*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*93*/ + MTK_PULL_PUPD_R1R0_TYPE, /*94*/ + MTK_PULL_PUPD_R1R0_TYPE, /*95*/ + MTK_PULL_PUPD_R1R0_TYPE, /*96*/ + MTK_PULL_PUPD_R1R0_TYPE, /*97*/ + MTK_PULL_PUPD_R1R0_TYPE, /*98*/ + MTK_PULL_PUPD_R1R0_TYPE, /*99*/ + MTK_PULL_PUPD_R1R0_TYPE, /*100*/ + MTK_PULL_PUPD_R1R0_TYPE, /*101*/ + MTK_PULL_PUPD_R1R0_TYPE, /*102*/ + MTK_PULL_PUPD_R1R0_TYPE, /*103*/ + MTK_PULL_PUPD_R1R0_TYPE, /*104*/ + MTK_PULL_PUPD_R1R0_TYPE, /*105*/ + MTK_PULL_PUPD_R1R0_TYPE, /*106*/ + MTK_PULL_PUPD_R1R0_TYPE, /*107*/ + MTK_PULL_PUPD_R1R0_TYPE, /*108*/ + MTK_PULL_PUPD_R1R0_TYPE, /*109*/ + MTK_PULL_PUPD_R1R0_TYPE, /*110*/ + MTK_PULL_PUPD_R1R0_TYPE, /*111*/ + MTK_PULL_PUPD_R1R0_TYPE, /*112*/ + MTK_PULL_PUPD_R1R0_TYPE, /*113*/ + MTK_PULL_PUPD_R1R0_TYPE, /*114*/ + MTK_PULL_PUPD_R1R0_TYPE, /*115*/ + MTK_PULL_PUPD_R1R0_TYPE, /*116*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*117*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*118*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*119*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*120*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*121*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*122*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*123*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*124*/ + MTK_PULL_PUPD_R1R0_TYPE, /*125*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*126*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*127*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*128*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*129*/ + MTK_PULL_PUPD_R1R0_TYPE, /*130*/ + MTK_PULL_PUPD_R1R0_TYPE, /*131*/ + MTK_PULL_PUPD_R1R0_TYPE, /*132*/ + MTK_PULL_PUPD_R1R0_TYPE, /*133*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*134*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*135*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*136*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*137*/ + MTK_PULL_PUPD_R1R0_TYPE, /*138*/ + MTK_PULL_PUPD_R1R0_TYPE, /*139*/ + MTK_PULL_PUPD_R1R0_TYPE, /*140*/ + MTK_PULL_PUPD_R1R0_TYPE, /*141*/ + MTK_PULL_PUPD_R1R0_TYPE, /*142*/ + MTK_PULL_PUPD_R1R0_TYPE, /*143*/ + MTK_PULL_PUPD_R1R0_TYPE, /*144*/ + MTK_PULL_PUPD_R1R0_TYPE, /*145*/ + MTK_PULL_PUPD_R1R0_TYPE, /*146*/ + MTK_PULL_PUPD_R1R0_TYPE, /*147*/ + MTK_PULL_PUPD_R1R0_TYPE, /*148*/ + MTK_PULL_PUPD_R1R0_TYPE, /*149*/ + MTK_PULL_PUPD_R1R0_TYPE, /*150*/ + MTK_PULL_PUPD_R1R0_TYPE, /*151*/ + MTK_PULL_PUPD_R1R0_TYPE, /*152*/ + MTK_PULL_PUPD_R1R0_TYPE, /*153*/ + MTK_PULL_PUPD_R1R0_TYPE, /*154*/ + MTK_PULL_PUPD_R1R0_TYPE, /*155*/ + MTK_PULL_PUPD_R1R0_TYPE, /*156*/ + MTK_PULL_PUPD_R1R0_TYPE, /*157*/ + MTK_PULL_PUPD_R1R0_TYPE, /*158*/ + MTK_PULL_PUPD_R1R0_TYPE, /*159*/ + MTK_PULL_PUPD_R1R0_TYPE, /*160*/ + MTK_PULL_PUPD_R1R0_TYPE, /*161*/ + MTK_PULL_PUPD_R1R0_TYPE, /*162*/ + MTK_PULL_PUPD_R1R0_TYPE, /*163*/ + MTK_PULL_PUPD_R1R0_TYPE, /*164*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*165*/ + MTK_PULL_PU_PD_RSEL_TYPE, /*166*/ + MTK_PULL_PUPD_R1R0_TYPE, /*167*/ + MTK_PULL_PUPD_R1R0_TYPE, /*168*/ + MTK_PULL_PUPD_R1R0_TYPE, /*169*/ + MTK_PULL_PUPD_R1R0_TYPE, /*170*/ + MTK_PULL_PUPD_R1R0_TYPE, /*171*/ + MTK_PULL_PUPD_R1R0_TYPE, /*172*/ + MTK_PULL_PUPD_R1R0_TYPE, /*173*/ + MTK_PULL_PUPD_R1R0_TYPE, /*174*/ + MTK_PULL_PUPD_R1R0_TYPE, /*175*/ + MTK_PULL_PUPD_R1R0_TYPE, /*176*/ + MTK_PULL_PUPD_R1R0_TYPE, /*177*/ + MTK_PULL_PUPD_R1R0_TYPE, /*178*/ + MTK_PULL_PUPD_R1R0_TYPE, /*179*/ + MTK_PULL_PUPD_R1R0_TYPE, /*180*/ + MTK_PULL_PU_PD_TYPE, /*181*/ +}; + +static const struct mtk_pin_reg_calc mt8901_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8901_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8901_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8901_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8901_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8901_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8901_pin_ies_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8901_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8901_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8901_pin_r1_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8901_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8901_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8901_pin_drv_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8901_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8901_pin_rsel_range), +}; + +static const char * const mt8901_pinctrl_register_base_name[] = { + "iocfg0", "iocfg_lt2", "iocfg_lt3", "iocfg_rt1", "iocfg_rt2", "iocfg_rt3", + "iocfg_tr", "iocfg_rt0", "iocfg_lt1", "iocfg_lb", "iocfg_rb", +}; + +static const struct mtk_eint_hw mt8901_eint_hw = { + .port_mask = 0xf, + .ports = 7, + .ap_num = 209, + .db_cnt = 32, + .db_time = debounce_time_mt8901, +}; + +static const struct mtk_pin_soc mt8901_data = { + .reg_cal = mt8901_reg_cals, + .pins = mtk_pins_mt8901, + .npins = ARRAY_SIZE(mtk_pins_mt8901), + .ngrps = ARRAY_SIZE(mtk_pins_mt8901), + .eint_hw = &mt8901_eint_hw, + .eint_pin = eint_pins_mt8901, + .nfuncs = 8, + .gpio_m = 0, + .base_names = mt8901_pinctrl_register_base_name, + .nbase_names = ARRAY_SIZE(mt8901_pinctrl_register_base_name), + .pull_type = mt8901_pull_type, + .pin_rsel = mt8901_pin_rsel_val_range, + .npin_rsel = ARRAY_SIZE(mt8901_pin_rsel_val_range), /*numsel*/ + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, +}; + +static const struct acpi_device_id mt8901_pinctrl_acpi_match[] = { + {"NVDA9221", (kernel_ulong_t)&mt8901_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, mt8901_pinctrl_acpi_match); + +static struct platform_driver mt8901_pinctrl_driver = { + .driver = { + .name = "mt8901-pinctrl", + .acpi_match_table = ACPI_PTR(mt8901_pinctrl_acpi_match), + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops) + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt8901_pinctrl_init(void) +{ + return platform_driver_register(&mt8901_pinctrl_driver); +} + +arch_initcall(mt8901_pinctrl_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek MT8901 Pinctrl Driver"); --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2018-2025 MediaTek Inc. * * Author: Sean Wang * @@ -369,18 +369,30 @@ { struct device_node *np = pdev->dev.of_node; int ret, i, j, count_reg_names; + struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev); + struct resource *res; if (!IS_ENABLED(CONFIG_EINT_MTK)) return 0; - if (!of_property_read_bool(np, "interrupt-controller")) + if (is_of_node(fwnode) && !of_property_read_bool(np, "interrupt-controller")) return -ENODEV; hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); if (!hw->eint) return -ENOMEM; - count_reg_names = of_property_count_strings(np, "reg-names"); + if (is_of_node(fwnode)) { + count_reg_names = of_property_count_strings(np, "reg-names"); + } else { + count_reg_names = 0; + for (i = 0; i < pdev->num_resources; i++) { + struct resource *r = &pdev->resource[i]; + + if (resource_type(r) == IORESOURCE_MEM) + count_reg_names++; + } + } if (count_reg_names < 0) return -EINVAL; @@ -396,14 +408,18 @@ } for (i = hw->soc->nbase_names, j = 0; i < count_reg_names; i++, j++) { - hw->eint->base[j] = of_iomap(np, i); + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + hw->eint->base[j] = is_of_node(fwnode) ? of_iomap(np, i) : + ioremap(res->start, resource_size(res)); if (IS_ERR(hw->eint->base[j])) { ret = PTR_ERR(hw->eint->base[j]); goto err_free_eint; } } - hw->eint->irq = irq_of_parse_and_map(np, 0); + hw->eint->irq = is_of_node(fwnode) + ? irq_of_parse_and_map(np, 0) + : platform_get_irq(pdev, 0); if (!hw->eint->irq) { ret = -EINVAL; goto err_free_eint; --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -302,6 +302,7 @@ spinlock_t lock; /* identify rsel setting by si unit or rsel define in dts node */ bool rsel_si_unit; + struct pinctrl_gpio_range range; }; void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h @@ -0,0 +1,2130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 MediaTek Inc. + * + */ + +#ifndef __PINCTRL_MTK_MT8901_H +#define __PINCTRL_MTK_MT8901_H + +#include "pinctrl-paris.h" + +#define INVALID_BASE 0xFF + +static const struct mtk_pin_desc mtk_pins_mt8901[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "B:GPIO0"), + MTK_FUNCTION(1, "O:ESPI_SCK") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO1"), + MTK_FUNCTION(1, "B1_ESPI_IO0") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO2"), + MTK_FUNCTION(1, "B1_ESPI_IO1") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO3"), + MTK_FUNCTION(1, "B1_ESPI_IO2") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO4"), + MTK_FUNCTION(1, "B1_ESPI_IO3") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO5"), + MTK_FUNCTION(1, "O_ESPI_CSN") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO6"), + MTK_FUNCTION(1, "O_ESPI_RESET_O"), + MTK_FUNCTION(2, "I1_ESPI_RESET_I") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO7"), + MTK_FUNCTION(1, "I1_ESPI_ALERT") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO8"), + MTK_FUNCTION(1, "B1_I2C_SCL3"), + MTK_FUNCTION(2, "B1_DISP_SCL2"), + MTK_FUNCTION(4, "O_PMSR_SMAP"), + MTK_FUNCTION(6, "O_MD32_0_TXD"), + MTK_FUNCTION(7, "O_MD32_1_TXD") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO9"), + MTK_FUNCTION(1, "B1_I2C_SDA3"), + MTK_FUNCTION(2, "B1_DISP_SDA2"), + MTK_FUNCTION(4, "O_PMSR_SMAP_MAX"), + MTK_FUNCTION(6, "I1_MD32_0_RXD"), + MTK_FUNCTION(7, "I1_MD32_1_RXD") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO10"), + MTK_FUNCTION(1, "B1_I2C_SCL4"), + MTK_FUNCTION(2, "B1_DISP_SCL2"), + MTK_FUNCTION(4, "O_PMSR_SMAP_MAX_W"), + MTK_FUNCTION(6, "O_MD32_0_GPIO0"), + MTK_FUNCTION(7, "O_MD32_1_GPIO0") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO11"), + MTK_FUNCTION(1, "B1_I2C_SDA4"), + MTK_FUNCTION(2, "B1_DISP_SDA2") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO12"), + MTK_FUNCTION(1, "B0_SPMI_M_SCL"), + MTK_FUNCTION(2, "B0_TP_GPIO31_AO") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO13"), + MTK_FUNCTION(1, "B0_SPMI_M_SDA"), + MTK_FUNCTION(2, "B0_TP_GPIO6_AO") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO14"), + MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_2"), + MTK_FUNCTION(7, "O_DBG_MON_A0") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO15"), + MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_3"), + MTK_FUNCTION(2, "B0_TP_GPIO25_AO"), + MTK_FUNCTION(7, "O_DBG_MON_A1") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO16"), + MTK_FUNCTION(1, "O_USB4_L_TCPC_RESET"), + MTK_FUNCTION(7, "O_DBG_MON_A18") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO17"), + MTK_FUNCTION(1, "B0_SPMI_P_SCL") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO18"), + MTK_FUNCTION(1, "B0_SPMI_P_SDA") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO19"), + MTK_FUNCTION(1, "B0_TP_GPIO29_AO") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO20"), + MTK_FUNCTION(1, "B0_TP_GPIO30_AO") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO21"), + MTK_FUNCTION(1, "B1_PROCHOT") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO22"), + MTK_FUNCTION(1, "I0_RTC32K_CK") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO23"), + MTK_FUNCTION(1, "B0_TP_GPIO0_AO") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO24"), + MTK_FUNCTION(2, "B0_TP_GPIO1_AO"), + MTK_FUNCTION(3, "O_CMMCLK1"), + MTK_FUNCTION(4, "O_SROOT_GPIO_O"), + MTK_FUNCTION(5, "O_MD32_10_TXD"), + MTK_FUNCTION(6, "O_MD32_11_TXD"), + MTK_FUNCTION(7, "O_DBG_MON_A3") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO25"), + MTK_FUNCTION(1, "B0_TP_GPIO2_AO"), + MTK_FUNCTION(2, "I0_VBUSVALID_0P"), + MTK_FUNCTION(4, "I0_SROOT_GPIO_I"), + MTK_FUNCTION(5, "I1_MD32_10_RXD"), + MTK_FUNCTION(6, "I1_MD32_11_RXD"), + MTK_FUNCTION(7, "O_DBG_MON_A4") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO26"), + MTK_FUNCTION(1, "B0_TP_GPIO3_AO"), + MTK_FUNCTION(5, "O_MD32_12_TXD"), + MTK_FUNCTION(6, "O_MD32_13_TXD"), + MTK_FUNCTION(7, "O_DBG_MON_A5") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO27"), + MTK_FUNCTION(1, "B0_TP_GPIO4_AO"), + MTK_FUNCTION(5, "I1_MD32_12_RXD"), + MTK_FUNCTION(6, "I1_MD32_13_RXD"), + MTK_FUNCTION(7, "O_DBG_MON_A6") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO28"), + MTK_FUNCTION(1, "B0_TP_GPIO5_AO"), + MTK_FUNCTION(5, "O_MD32_12_GPIO0"), + MTK_FUNCTION(6, "O_MD32_13_GPIO0"), + MTK_FUNCTION(7, "O_DBG_MON_A7") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO29"), + MTK_FUNCTION(1, "B1_THERMTRIP") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO30"), + MTK_FUNCTION(1, "B0_TP_GPIO7_AO"), + MTK_FUNCTION(2, "O_CMMCLK0"), + MTK_FUNCTION(4, "I0_CLUSTER0_SLV_CPUEB_JTAG_TRSTN"), + MTK_FUNCTION(5, "I0_CLUSTER1_SLV_CPUEB_JTAG_TRSTN"), + MTK_FUNCTION(6, "I0_OSROOT_GPIO_I"), + MTK_FUNCTION(7, "O_DBG_MON_A8") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO31"), + MTK_FUNCTION(1, "B0_TP_GPIO8_AO"), + MTK_FUNCTION(2, "O_CMMCLK1"), + MTK_FUNCTION(4, "I1_CLUSTER0_SLV_CPUEB_JTAG_TMS"), + MTK_FUNCTION(5, "I1_CLUSTER1_SLV_CPUEB_JTAG_TMS"), + MTK_FUNCTION(6, "O_OSROOT_GPIO_O"), + MTK_FUNCTION(7, "O_DBG_MON_A9") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO32"), + MTK_FUNCTION(1, "B0_TP_GPIO9_AO"), + MTK_FUNCTION(5, "O_SROOT_UTX"), + MTK_FUNCTION(6, "I1_TP_UCTS1_VLP"), + MTK_FUNCTION(7, "O_DBG_MON_A10") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO33"), + MTK_FUNCTION(1, "B0_TP_GPIO10_AO"), + MTK_FUNCTION(2, "O_CMMCLK2"), + MTK_FUNCTION(3, "I0_VBUSVALID_1P"), + MTK_FUNCTION(4, "I1_CLUSTER0_SLV_CPUEB_JTAG_TCK"), + MTK_FUNCTION(5, "I1_CLUSTER1_SLV_CPUEB_JTAG_TCK"), + MTK_FUNCTION(6, "I0_SROOT_TCK"), + MTK_FUNCTION(7, "I0_OSROOT_TCK") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO34"), + MTK_FUNCTION(1, "B0_TP_GPIO11_AO"), + MTK_FUNCTION(2, "O_CMMCLK4"), + MTK_FUNCTION(3, "I0_VBUSVALID_3P"), + MTK_FUNCTION(4, "I1_CLUSTER0_SLV_CPUEB_JTAG_TDI"), + MTK_FUNCTION(5, "I1_CLUSTER1_SLV_CPUEB_JTAG_TDI"), + MTK_FUNCTION(6, "I0_SROOT_TDI"), + MTK_FUNCTION(7, "I0_OSROOT_TDI") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO35"), + MTK_FUNCTION(1, "B0_TP_GPIO12_AO"), + MTK_FUNCTION(2, "O_SCP_PWM_1_VLP"), + MTK_FUNCTION(4, "O_CLUSTER0_SLV_CPUEB_JTAG_TDO"), + MTK_FUNCTION(5, "O_CLUSTER1_SLV_CPUEB_JTAG_TDO"), + MTK_FUNCTION(6, "O_SROOT_TDO"), + MTK_FUNCTION(7, "O_OSROOT_TDO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO36"), + MTK_FUNCTION(1, "B0_TP_GPIO22_AO"), + MTK_FUNCTION(5, "I1_SROOT_URX"), + MTK_FUNCTION(6, "O_TP_URTS1_VLP"), + MTK_FUNCTION(7, "O_DBG_MON_A31") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO37"), + MTK_FUNCTION(1, "B0_TP_GPIO23_AO"), + MTK_FUNCTION(2, "O_CMMCLK3"), + MTK_FUNCTION(4, "O_SCP_PWM_2_VLP"), + MTK_FUNCTION(6, "O_MD32_5_GPIO0"), + MTK_FUNCTION(7, "O_DBG_MON_A11") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO38"), + MTK_FUNCTION(1, "B0_TP_GPIO24_AO"), + MTK_FUNCTION(2, "O_SCP_VREQ_VAO") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO39"), + MTK_FUNCTION(1, "B0_TP_GPIO13_AO"), + MTK_FUNCTION(2, "O_SCP_PWM_2_VLP"), + MTK_FUNCTION(3, "O_CMMCLK0"), + MTK_FUNCTION(4, "I0_VBUSVALID_2P"), + MTK_FUNCTION(5, "O_MD32_10_GPIO0"), + MTK_FUNCTION(6, "I0_SROOT_TMS"), + MTK_FUNCTION(7, "I0_OSROOT_TMS") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO40"), + MTK_FUNCTION(1, "B0_TP_GPIO14_AO"), + MTK_FUNCTION(2, "I0_VBUSVALID_1P"), + MTK_FUNCTION(3, "O_URTS2"), + MTK_FUNCTION(4, "O_TP_URTS2_VLP"), + MTK_FUNCTION(5, "O_SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(6, "I1_MD32_5_RXD"), + MTK_FUNCTION(7, "O_DBG_MON_A13") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO41"), + MTK_FUNCTION(1, "B0_TP_GPIO15_AO"), + MTK_FUNCTION(2, "I0_VBUSVALID_0P"), + MTK_FUNCTION(3, "I1_UCTS2"), + MTK_FUNCTION(4, "I1_TP_UCTS2_VLP"), + MTK_FUNCTION(5, "O_SPMI_S_TRIG_FLAG"), + MTK_FUNCTION(6, "O_MD32_5_TXD"), + MTK_FUNCTION(7, "O_DBG_MON_A12") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO42"), + MTK_FUNCTION(1, "B0_TP_GPIO16_AO"), + MTK_FUNCTION(2, "O_CMMCLK3"), + MTK_FUNCTION(3, "O_UTXD2"), + MTK_FUNCTION(4, "O_TP_UTXD2_VLP"), + MTK_FUNCTION(5, "O_SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(6, "I0_SROOT_NTRST"), + MTK_FUNCTION(7, "I0_OSROOT_NTRST") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO43"), + MTK_FUNCTION(1, "B0_TP_GPIO17_AO"), + MTK_FUNCTION(2, "O_CMMCLK4"), + MTK_FUNCTION(3, "I1_URXD2"), + MTK_FUNCTION(4, "I1_TP_URXD2_VLP"), + MTK_FUNCTION(5, "O_MD32_4_TXD"), + MTK_FUNCTION(6, "O_MD32PCM_UTXD_AO_VLP") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO44"), + MTK_FUNCTION(1, "B0_TP_GPIO18_AO"), + MTK_FUNCTION(2, "I1_TP_UCTS2_VLP"), + MTK_FUNCTION(3, "I1_UCTS2"), + MTK_FUNCTION(5, "I1_MD32_4_RXD"), + MTK_FUNCTION(6, "I1_MD32PCM_URXD_AO_VLP") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO45"), + MTK_FUNCTION(1, "B0_TP_GPIO19_AO"), + MTK_FUNCTION(2, "O_TP_URTS2_VLP"), + MTK_FUNCTION(3, "O_URTS2"), + MTK_FUNCTION(5, "O_MD32_4_GPIO0"), + MTK_FUNCTION(6, "O_MD32_11_GPIO0") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO46"), + MTK_FUNCTION(1, "B0_TP_GPIO20_AO"), + MTK_FUNCTION(2, "I0_VBUSVALID_2P"), + MTK_FUNCTION(3, "O_SCP_VREQ_VAO"), + MTK_FUNCTION(4, "O_SCP_PWM_1_VLP"), + MTK_FUNCTION(5, "O_SROOT_GPIO_O"), + MTK_FUNCTION(6, "O_OSROOT_GPIO_O") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO47"), + MTK_FUNCTION(1, "B0_TP_GPIO21_AO"), + MTK_FUNCTION(2, "I0_VBUSVALID_3P"), + MTK_FUNCTION(3, "O_CMMCLK2"), + MTK_FUNCTION(5, "I0_SROOT_GPIO_I"), + MTK_FUNCTION(6, "I0_OSROOT_GPIO_I"), + MTK_FUNCTION(7, "O_DBG_MON_A2") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO48"), + MTK_FUNCTION(1, "O_UTXD0"), + MTK_FUNCTION(2, "O_TP_UTXD1_VLP"), + MTK_FUNCTION(6, "O_ADSP_UTXD0"), + MTK_FUNCTION(7, "O_DBG_MON_A19") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO49"), + MTK_FUNCTION(1, "I1_URXD0"), + MTK_FUNCTION(2, "I1_TP_URXD1_VLP"), + MTK_FUNCTION(6, "I1_ADSP_URXD0"), + MTK_FUNCTION(7, "O_DBG_MON_A20") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO50"), + MTK_FUNCTION(1, "O_TP_UTXD2_VLP"), + MTK_FUNCTION(2, "O_UTXD2"), + MTK_FUNCTION(4, "B0_TP_GPIO26_AO"), + MTK_FUNCTION(5, "O_TP_UTXD1_VLP"), + MTK_FUNCTION(7, "O_SROOT_UTX") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO51"), + MTK_FUNCTION(1, "I1_TP_URXD2_VLP"), + MTK_FUNCTION(2, "I1_URXD2"), + MTK_FUNCTION(4, "B0_TP_GPIO27_AO"), + MTK_FUNCTION(5, "I1_TP_URXD1_VLP"), + MTK_FUNCTION(7, "I1_SROOT_URX") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO52"), + MTK_FUNCTION(1, "B1_USB4_L_PD_SCL"), + MTK_FUNCTION(7, "O_ADSP_UTXD0") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO53"), + MTK_FUNCTION(1, "B1_USB4_L_PD_SDA"), + MTK_FUNCTION(5, "O_MD32_7_TXD"), + MTK_FUNCTION(6, "O_MD32_6_TXD"), + MTK_FUNCTION(7, "I1_ADSP_URXD0") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO54"), + MTK_FUNCTION(1, "B1_USB4_R_PD_SCL"), + MTK_FUNCTION(4, "I1_CKM_SCL"), + MTK_FUNCTION(5, "I1_MD32_7_RXD"), + MTK_FUNCTION(6, "I1_USB4_L_PAR_SCL"), + MTK_FUNCTION(7, "O_PBUD_CTRL_UTXD_AO_VLP") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO55"), + MTK_FUNCTION(1, "B1_USB4_R_PD_SDA"), + MTK_FUNCTION(4, "B1_CKM_SDA"), + MTK_FUNCTION(5, "O_MD32_7_GPIO0"), + MTK_FUNCTION(6, "B1_USB4_L_PAR_SDA"), + MTK_FUNCTION(7, "I1_PBUD_CTRL_URXD_AO_VLP") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO56"), + MTK_FUNCTION(1, "B0_SPMI_S_SCL") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO57"), + MTK_FUNCTION(1, "B0_SPMI_S_SDA") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO58"), + MTK_FUNCTION(1, "O_WATCHDOG") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO59"), + MTK_FUNCTION(1, "B0_PAD_RESET_DRAM_0") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO60"), + MTK_FUNCTION(1, "B1_I2C_SCL0"), + MTK_FUNCTION(5, "O_MD32_2_TXD"), + MTK_FUNCTION(6, "O_MD32_3_TXD") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO61"), + MTK_FUNCTION(1, "B1_I2C_SDA0"), + MTK_FUNCTION(5, "I1_MD32_2_RXD"), + MTK_FUNCTION(6, "I1_MD32_3_RXD") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO62"), + MTK_FUNCTION(1, "I0_DMIC0_DAT"), + MTK_FUNCTION(6, "O_TP_UTXD1_VLP"), + MTK_FUNCTION(7, "O_DBG_MON_B0") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO63"), + MTK_FUNCTION(1, "O_DMIC0_CLK"), + MTK_FUNCTION(6, "I1_TP_URXD1_VLP"), + MTK_FUNCTION(7, "O_DBG_MON_B1") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO64"), + MTK_FUNCTION(1, "I0_DMIC1_DAT"), + MTK_FUNCTION(5, "O_MD32_2_GPIO0"), + MTK_FUNCTION(6, "O_MD32_3_GPIO0"), + MTK_FUNCTION(7, "O_DBG_MON_B2") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO65"), + MTK_FUNCTION(1, "O_DMIC1_CLK"), + MTK_FUNCTION(7, "O_DBG_MON_B3") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO66"), + MTK_FUNCTION(1, "O_SOUNDWIRE0_CK"), + MTK_FUNCTION(3, "I1_TP_UCTS0_VLP"), + MTK_FUNCTION(4, "O_SPI_HID_IRQ_S_MON0"), + MTK_FUNCTION(7, "O_VADSP_UTXD0") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO67"), + MTK_FUNCTION(1, "B0_SOUNDWIRE0_D0"), + MTK_FUNCTION(3, "O_TP_URTS0_VLP"), + MTK_FUNCTION(7, "I1_VADSP_URXD0") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO68"), + MTK_FUNCTION(1, "O_SCP_PWM_0_VLP"), + MTK_FUNCTION(2, "O_PWM_VLP"), + MTK_FUNCTION(3, "B0_TP_GPIO28_AO") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO69"), + MTK_FUNCTION(1, "B0_PAD_RESET_DRAM_8") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO70"), + MTK_FUNCTION(1, "B1_SCP_SCL0"), + MTK_FUNCTION(4, "I0_VADSP_JTAG0_TCK"), + MTK_FUNCTION(5, "I1_PCIE4_USB3_PAR_SCL"), + MTK_FUNCTION(6, "I1_SCP_JTAG0_TCK_VLP"), + MTK_FUNCTION(7, "B1_SROOT_SCL") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO71"), + MTK_FUNCTION(1, "B1_SCP_SDA0"), + MTK_FUNCTION(4, "I1_VADSP_JTAG0_TMS"), + MTK_FUNCTION(5, "B1_PCIE4_USB3_PAR_SDA"), + MTK_FUNCTION(6, "B1_SCP_JTAG0_TMS_VLP"), + MTK_FUNCTION(7, "B1_SROOT_SDA") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO72"), + MTK_FUNCTION(1, "B1_SCP_SCL2"), + MTK_FUNCTION(2, "B1_I3C_HCI_AO_SCL"), + MTK_FUNCTION(4, "I1_VADSP_JTAG0_TDI"), + MTK_FUNCTION(5, "I1_PCIE5_PAR_SCL"), + MTK_FUNCTION(6, "I1_SCP_JTAG0_TDI_VLP"), + MTK_FUNCTION(7, "O_OSROOT_UTX") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO73"), + MTK_FUNCTION(1, "B1_SCP_SDA2"), + MTK_FUNCTION(2, "B1_I3C_HCI_AO_SDA"), + MTK_FUNCTION(4, "O_VADSP_JTAG0_TDO"), + MTK_FUNCTION(5, "B1_PCIE5_PAR_SDA"), + MTK_FUNCTION(6, "O_SCP_JTAG0_TDO_VLP"), + MTK_FUNCTION(7, "I1_OSROOT_URX") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO74"), + MTK_FUNCTION(1, "I0_SCP_SPIS0_SCL"), + MTK_FUNCTION(2, "O_SPI2_CLK"), + MTK_FUNCTION(3, "O_SCP_SPIM0_CK"), + MTK_FUNCTION(4, "I1_SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(5, "I1_SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TCK_VLP"), + MTK_FUNCTION(7, "I0_OSROOT_TCK") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO75"), + MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO0"), + MTK_FUNCTION(2, "B0_SPI2_MI"), + MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO0"), + MTK_FUNCTION(4, "I1_SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(5, "I1_SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TDI_VLP"), + MTK_FUNCTION(7, "I0_OSROOT_TDI") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO76"), + MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO1"), + MTK_FUNCTION(2, "B0_SPI2_MO"), + MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO1"), + MTK_FUNCTION(4, "B1_SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(5, "O_SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(6, "O_PBUD_CTRL_JTAG_TDO_VLP"), + MTK_FUNCTION(7, "O_OSROOT_TDO") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO77"), + MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO2"), + MTK_FUNCTION(2, "B0_SPI2_WP"), + MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO2"), + MTK_FUNCTION(4, "I1_SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(5, "I1_SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TMS_VLP"), + MTK_FUNCTION(7, "I0_OSROOT_TMS") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO78"), + MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO3"), + MTK_FUNCTION(2, "B0_SPI2_HOLD"), + MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO3"), + MTK_FUNCTION(4, "I0_SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(5, "I0_SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(6, "I0_PBUD_CTRL_JTAG_TRSTN_VLP"), + MTK_FUNCTION(7, "I0_OSROOT_NTRST") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO79"), + MTK_FUNCTION(1, "I1_SCP_SPIS0_CS"), + MTK_FUNCTION(2, "O_SPI2_CSB"), + MTK_FUNCTION(3, "O_SCP_SPIM0_CS"), + MTK_FUNCTION(4, "I1_VADSP_JTAG0_TRSTN"), + MTK_FUNCTION(6, "I0_SCP_JTAG0_TRSTN_VLP") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO80"), + MTK_FUNCTION(1, "O_SPI0_CLK"), + MTK_FUNCTION(2, "B0_SPI0_OSROOT_CLK"), + MTK_FUNCTION(4, "I1_SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(5, "I0_VADSP_JTAG0_TCK"), + MTK_FUNCTION(6, "I1_SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(7, "I1_SCP_JTAG0_TCK_VLP") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO81"), + MTK_FUNCTION(1, "B0_SPI0_MI"), + MTK_FUNCTION(2, "I0_SPI0_OSROOT_MI"), + MTK_FUNCTION(4, "I1_SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(5, "I1_VADSP_JTAG0_TDI"), + MTK_FUNCTION(6, "I1_SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(7, "I1_SCP_JTAG0_TDI_VLP") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO82"), + MTK_FUNCTION(1, "B0_SPI0_MO"), + MTK_FUNCTION(2, "O_SPI0_OSROOT_MO"), + MTK_FUNCTION(4, "O_SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(5, "O_VADSP_JTAG0_TDO"), + MTK_FUNCTION(6, "B1_SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(7, "O_SCP_JTAG0_TDO_VLP") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO83"), + MTK_FUNCTION(1, "O_SPI0_CSB0"), + MTK_FUNCTION(2, "O_SPI0_OSROOT_CSB"), + MTK_FUNCTION(4, "I1_SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(5, "I1_VADSP_JTAG0_TMS"), + MTK_FUNCTION(6, "I1_SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(7, "B1_SCP_JTAG0_TMS_VLP") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO84"), + MTK_FUNCTION(1, "O_SPI0_CSB1"), + MTK_FUNCTION(4, "I0_SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(5, "I1_VADSP_JTAG0_TRSTN"), + MTK_FUNCTION(6, "I0_SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(7, "I0_SCP_JTAG0_TRSTN_VLP") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO85"), + MTK_FUNCTION(1, "O_DISP_PWM"), + MTK_FUNCTION(4, "B1_U4CP_JTAG_TMS"), + MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_1"), + MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_1"), + MTK_FUNCTION(7, "O_DBG_MON_A21") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO86"), + MTK_FUNCTION(1, "O_DISP_BL_EN"), + MTK_FUNCTION(4, "I1_U4CP_JTAG_TDI"), + MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_1"), + MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_1"), + MTK_FUNCTION(7, "O_DBG_MON_A22") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO87"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N_1"), + MTK_FUNCTION(4, "O_U4CP_JTAG_TDO"), + MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_2"), + MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_2"), + MTK_FUNCTION(7, "O_DBG_MON_A23") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO88"), + MTK_FUNCTION(1, "B1_DISP_SCL1"), + MTK_FUNCTION(4, "I1_U4CP_JTAG_TCK"), + MTK_FUNCTION(5, "I1_EDP0_SCL"), + MTK_FUNCTION(6, "I1_HDMITX_DBG_I2C_SCL") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO89"), + MTK_FUNCTION(1, "B1_DISP_SDA1"), + MTK_FUNCTION(4, "I0_U4CP_JTAG_TRSTN"), + MTK_FUNCTION(5, "B1_EDP0_SDA"), + MTK_FUNCTION(6, "B1_HDMITX_DBG_I2C_SDA") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO90"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N2"), + MTK_FUNCTION(4, "O_CLKM0_C"), + MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_2"), + MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_2"), + MTK_FUNCTION(7, "O_DBG_MON_A24") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO91"), + MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_4"), + MTK_FUNCTION(4, "O_CLKM1_C"), + MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_3"), + MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_3"), + MTK_FUNCTION(7, "O_DBG_MON_A25") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO92"), + MTK_FUNCTION(1, "B1_I2C_SCL5"), + MTK_FUNCTION(2, "O_TP_UTXD0_VLP"), + MTK_FUNCTION(3, "O_SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(4, "O_TSFDC_FOUT"), + MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_3"), + MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_3"), + MTK_FUNCTION(7, "O_DBG_MON_A26") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO93"), + MTK_FUNCTION(1, "B1_I2C_SDA5"), + MTK_FUNCTION(2, "I1_TP_URXD0_VLP"), + MTK_FUNCTION(3, "I1_SSPM_URXD_AO_VLP"), + MTK_FUNCTION(4, "O_TSFDC_SDO"), + MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_4"), + MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_4"), + MTK_FUNCTION(7, "O_DBG_MON_A27") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO94"), + MTK_FUNCTION(1, "O_CMFLASH0"), + MTK_FUNCTION(4, "I0_TSFDC_26M"), + MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_4"), + MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_4"), + MTK_FUNCTION(7, "O_DBG_MON_A28") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO95"), + MTK_FUNCTION(1, "O_CMFLASH1"), + MTK_FUNCTION(4, "I0_TSFDC_SCF"), + MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_5"), + MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_5"), + MTK_FUNCTION(7, "O_DBG_MON_A29") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO96"), + MTK_FUNCTION(1, "O_CMVREF0"), + MTK_FUNCTION(2, "O_CMFLASH1"), + MTK_FUNCTION(4, "I0_TSFDC_SCK"), + MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_5"), + MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_5"), + MTK_FUNCTION(7, "O_DBG_MON_A30") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO97"), + MTK_FUNCTION(1, "O_CMVREF1"), + MTK_FUNCTION(2, "O_CMFLASH0"), + MTK_FUNCTION(4, "I0_TSFDC_SDI"), + MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_6"), + MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_6"), + MTK_FUNCTION(7, "O_U4CP_UTXD") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO98"), + MTK_FUNCTION(2, "O_CMFLASH2"), + MTK_FUNCTION(4, "I0_RG_TSFDC_LDO_EN"), + MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_6"), + MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_6"), + MTK_FUNCTION(7, "I1_U4CP_URXD") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO99"), + MTK_FUNCTION(1, "I0_MCU_M_PMIC_POC_I"), + MTK_FUNCTION(4, "I0_DA_TSFDC_LDO_MODE"), + MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_7"), + MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_7"), + MTK_FUNCTION(7, "O_U4CP_URTS") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO100"), + MTK_FUNCTION(1, "I0_MCU_B_PMIC_POC_I"), + MTK_FUNCTION(4, "I0_RG_TSFDC_LDO_REFSEL1"), + MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_7"), + MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_7"), + MTK_FUNCTION(7, "I1_U4CP_UCTS") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO101"), + MTK_FUNCTION(1, "O_CMFLASH2"), + MTK_FUNCTION(2, "O_CMVREF1"), + MTK_FUNCTION(3, "I1_UCTS0"), + MTK_FUNCTION(4, "I0_RG_TSFDC_LDO_REFSEL0"), + MTK_FUNCTION(5, "I1_U4CP_JTAG_TCK"), + MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TCK_VCORE"), + MTK_FUNCTION(7, "O_CLKM0_A") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO102"), + MTK_FUNCTION(1, "O_CMFLASH3"), + MTK_FUNCTION(2, "O_CMVREF0"), + MTK_FUNCTION(3, "O_URTS0"), + MTK_FUNCTION(4, "O_TSFDC_BG_COMP"), + MTK_FUNCTION(5, "B1_U4CP_JTAG_TMS"), + MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TMS_VCORE"), + MTK_FUNCTION(7, "O_CLKM1_A") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO103"), + MTK_FUNCTION(1, "O_CMVREF2"), + MTK_FUNCTION(2, "O_UTXD0"), + MTK_FUNCTION(4, "O_CLKM2_B"), + MTK_FUNCTION(5, "I1_U4CP_JTAG_TDI"), + MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TDI_VCORE"), + MTK_FUNCTION(7, "O_CLKM2_A") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO104"), + MTK_FUNCTION(1, "O_CMVREF3"), + MTK_FUNCTION(2, "I1_URXD0"), + MTK_FUNCTION(4, "O_CLKM3_B"), + MTK_FUNCTION(5, "O_U4CP_JTAG_TDO"), + MTK_FUNCTION(6, "O_PBUD_CTRL_JTAG_TDO_VCORE"), + MTK_FUNCTION(7, "O_CLKM3_A") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO105"), + MTK_FUNCTION(2, "O_CMFLASH3"), + MTK_FUNCTION(4, "O_CLKM0_B"), + MTK_FUNCTION(5, "I0_U4CP_JTAG_TRSTN"), + MTK_FUNCTION(6, "I0_PBUD_CTRL_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(7, "O_PMSR_SMAP") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO106"), + MTK_FUNCTION(1, "B0_SPINOR_CK") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO107"), + MTK_FUNCTION(1, "B0_SPINOR_IO0") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO108"), + MTK_FUNCTION(1, "B0_SPINOR_IO1") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO109"), + MTK_FUNCTION(1, "B0_SPINOR_IO2") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO110"), + MTK_FUNCTION(1, "B0_SPINOR_IO3") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO111"), + MTK_FUNCTION(1, "B1_SPINOR_CS") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO112"), + MTK_FUNCTION(1, "O_SPI1_CLK"), + MTK_FUNCTION(5, "I1_HFRP_JTAG1_TCK") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO113"), + MTK_FUNCTION(1, "B0_SPI1_MI"), + MTK_FUNCTION(5, "I1_HFRP_JTAG1_TMS") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO114"), + MTK_FUNCTION(1, "B0_SPI1_MO"), + MTK_FUNCTION(5, "I1_HFRP_JTAG1_TDI") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO115"), + MTK_FUNCTION(1, "O_SPI1_CSB0"), + MTK_FUNCTION(5, "O_HFRP_JTAG1_TDO") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO116"), + MTK_FUNCTION(1, "O_SPI1_CSB1"), + MTK_FUNCTION(5, "I0_HFRP_JTAG1_TRSTN") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO117"), + MTK_FUNCTION(1, "B1_I2C_SCL1"), + MTK_FUNCTION(2, "B1_OSROOT_SCL"), + MTK_FUNCTION(4, "O_SPI_CS_S_MON0"), + MTK_FUNCTION(5, "I1_USB4_L_PAR_SCL"), + MTK_FUNCTION(6, "I1_CKM_SCL"), + MTK_FUNCTION(7, "I1_USB4_R_PAR_SCL") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO118"), + MTK_FUNCTION(1, "B1_I2C_SDA1"), + MTK_FUNCTION(2, "B1_OSROOT_SDA"), + MTK_FUNCTION(4, "O_SPI_SCL_S_MON0"), + MTK_FUNCTION(5, "B1_USB4_L_PAR_SDA"), + MTK_FUNCTION(6, "B1_CKM_SDA"), + MTK_FUNCTION(7, "B1_USB4_R_PAR_SDA") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO119"), + MTK_FUNCTION(1, "B1_I2C_SCL2"), + MTK_FUNCTION(4, "I1_HDMITX_DBG_I2C_SCL"), + MTK_FUNCTION(5, "O_CLUSTER0_MBISTREADEN_TRIGGER"), + MTK_FUNCTION(6, "O_CLUSTER1_MBISTREADEN_TRIGGER"), + MTK_FUNCTION(7, "O_PMSR_SMAP_MAX") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO120"), + MTK_FUNCTION(1, "B1_I2C_SDA2+J130_S133"), + MTK_FUNCTION(4, "B1_HDMITX_DBG_I2C_SDA"), + MTK_FUNCTION(5, "O_CLUSTER0_MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(6, "O_CLUSTER1_MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(7, "O_PMSR_SMAP_MAX_W") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO121"), + MTK_FUNCTION(1, "B1_I3C_SCL0"), + MTK_FUNCTION(2, "B1_I3C_HCI_0_AO_SCL"), + MTK_FUNCTION(4, "I1_PCIE5_PAR_SCL"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST0"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST0"), + MTK_FUNCTION(7, "I1_USB4_R_PAR_SCL") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO122"), + MTK_FUNCTION(1, "B1_I3C_SDA0"), + MTK_FUNCTION(2, "B1_I3C_HCI_0_AO_SDA"), + MTK_FUNCTION(4, "B1_PCIE5_PAR_SDA"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST1"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST1"), + MTK_FUNCTION(7, "B1_USB4_R_PAR_SDA") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO123"), + MTK_FUNCTION(1, "B1_I3C_SCL1"), + MTK_FUNCTION(2, "B1_I3C_HCI_1_AO_SCL"), + MTK_FUNCTION(4, "I1_PCIE4_USB3_PAR_SCL"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST2"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST2"), + MTK_FUNCTION(7, "O_VADSP_UTXD0") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO124"), + MTK_FUNCTION(1, "B1_I3C_SDA1"), + MTK_FUNCTION(2, "B1_I3C_HCI_1_AO_SDA"), + MTK_FUNCTION(4, "B1_PCIE4_USB3_PAR_SDA"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST3"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST3"), + MTK_FUNCTION(7, "I1_VADSP_URXD0") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO125"), + MTK_FUNCTION(1, "O_I2SIN_1_MCK"), + MTK_FUNCTION(4, "I0_TSFDC_SCK"), + MTK_FUNCTION(6, "O_CLKM2_C") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO126"), + MTK_FUNCTION(1, "O_SOUNDWIRE1_CK"), + MTK_FUNCTION(2, "O_I2SIN_1_BCK"), + MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST4"), + MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST4"), + MTK_FUNCTION(6, "I0_ADSP_JTAG0_TCK"), + MTK_FUNCTION(7, "I1_HFRP_JTAG0_TCK") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO127"), + MTK_FUNCTION(1, "B0_SOUNDWIRE1_D0"), + MTK_FUNCTION(2, "O_I2SOUT1_DO"), + MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST5"), + MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST5"), + MTK_FUNCTION(6, "I1_ADSP_JTAG0_TMS"), + MTK_FUNCTION(7, "B1_HFRP_JTAG0_TMS") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO128"), + MTK_FUNCTION(1, "B0_SOUNDWIRE1_D1"), + MTK_FUNCTION(2, "I0_I2SIN_1_DI"), + MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST6"), + MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST6"), + MTK_FUNCTION(6, "I1_ADSP_JTAG0_TDI"), + MTK_FUNCTION(7, "I1_HFRP_JTAG0_TDI") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO129"), + MTK_FUNCTION(1, "B0_SOUNDWIRE1_D2"), + MTK_FUNCTION(2, "O_I2SIN_1_LRCK"), + MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST7"), + MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST7"), + MTK_FUNCTION(6, "O_ADSP_JTAG0_TDO"), + MTK_FUNCTION(7, "O_HFRP_JTAG0_TDO") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO130"), + MTK_FUNCTION(1, "B0_I2SIN0_BCK"), + MTK_FUNCTION(3, "O_DISP_CLKM0"), + MTK_FUNCTION(4, "I0_TSFDC_26M"), + MTK_FUNCTION(5, "I0_RG_TSFDC_LDO_EN"), + MTK_FUNCTION(6, "O_CCU0_URTS"), + MTK_FUNCTION(7, "O_DBG_MON_B4") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO131"), + MTK_FUNCTION(1, "I0_I2SIN0_DI"), + MTK_FUNCTION(3, "O_DISP_CLKM1"), + MTK_FUNCTION(4, "O_TSFDC_FOUT"), + MTK_FUNCTION(5, "I0_DA_TSFDC_LDO_MODE"), + MTK_FUNCTION(6, "I1_CCU0_UCTS"), + MTK_FUNCTION(7, "O_DBG_MON_B5") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO132"), + MTK_FUNCTION(1, "O_I2SOUT0_DO"), + MTK_FUNCTION(3, "O_DISP_CLKM2"), + MTK_FUNCTION(4, "O_TSFDC_SDO"), + MTK_FUNCTION(5, "I0_RG_TSFDC_LDO_REFSEL1"), + MTK_FUNCTION(6, "O_CCU1_URTS"), + MTK_FUNCTION(7, "O_DBG_MON_B6") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO133"), + MTK_FUNCTION(1, "B0_I2SIN0_LRCK"), + MTK_FUNCTION(3, "O_DISP_CLKM3"), + MTK_FUNCTION(4, "I0_TSFDC_SCF"), + MTK_FUNCTION(5, "I0_RG_TSFDC_LDO_REFSEL0"), + MTK_FUNCTION(6, "I1_CCU1_UCTS"), + MTK_FUNCTION(7, "O_DBG_MON_B7") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO134"), + MTK_FUNCTION(1, "B1_SCP_SCL1"), + MTK_FUNCTION(2, "B1_VADSP_SCL0"), + MTK_FUNCTION(3, "B1_SROOT_SCL"), + MTK_FUNCTION(4, "O_SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "O_SPI_HID_IRQ_S_MON0"), + MTK_FUNCTION(6, "I1_ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(7, "O_DBG_MON_B8") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO135"), + MTK_FUNCTION(1, "B1_SCP_SDA1"), + MTK_FUNCTION(2, "B1_VADSP_SDA0"), + MTK_FUNCTION(3, "B1_SROOT_SDA"), + MTK_FUNCTION(4, "I1_SSPM_URXD_AO_VLP"), + MTK_FUNCTION(7, "O_DBG_MON_B9") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO136"), + MTK_FUNCTION(1, "O_CMVREF2"), + MTK_FUNCTION(2, "B1_SCP_SCL3"), + MTK_FUNCTION(3, "B1_VADSP_SCL0"), + MTK_FUNCTION(4, "B1_SCP_SCL1"), + MTK_FUNCTION(5, "I1_MD32_8_RXD"), + MTK_FUNCTION(6, "I1_MD32_9_RXD"), + MTK_FUNCTION(7, "O_DBG_MON_B10") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO137"), + MTK_FUNCTION(1, "O_CMVREF3"), + MTK_FUNCTION(2, "B1_SCP_SDA3"), + MTK_FUNCTION(3, "B1_VADSP_SDA0"), + MTK_FUNCTION(4, "B1_SCP_SDA1"), + MTK_FUNCTION(5, "O_MD32_8_GPIO0"), + MTK_FUNCTION(6, "O_MD32_9_GPIO0"), + MTK_FUNCTION(7, "O_DBG_MON_B11") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO138"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N3"), + MTK_FUNCTION(2, "I0_DISP_LSPII"), + MTK_FUNCTION(4, "O_CLKM1_B"), + MTK_FUNCTION(5, "O_MD32_8_TXD"), + MTK_FUNCTION(6, "O_MD32_9_TXD"), + MTK_FUNCTION(7, "O_DBG_MON_B12") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO139"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N4"), + MTK_FUNCTION(2, "O_DISP_HSYNC0"), + MTK_FUNCTION(3, "O_DISP_HSYNC1"), + MTK_FUNCTION(4, "O_CLKM0_A"), + MTK_FUNCTION(5, "O_CLKM0_B"), + MTK_FUNCTION(6, "O_CLKM0_C"), + MTK_FUNCTION(7, "O_DBG_MON_B13") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO140"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N5"), + MTK_FUNCTION(2, "O_DISP_VSYNC0"), + MTK_FUNCTION(3, "O_DISP_VSYNC1"), + MTK_FUNCTION(4, "O_CLKM1_A"), + MTK_FUNCTION(5, "O_CLKM1_B"), + MTK_FUNCTION(6, "O_CLKM1_C"), + MTK_FUNCTION(7, "O_DBG_MON_A14") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO141"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N6"), + MTK_FUNCTION(2, "O_DISP_HSYNC2"), + MTK_FUNCTION(3, "O_DISP_HSYNC3"), + MTK_FUNCTION(4, "O_CLKM2_A"), + MTK_FUNCTION(5, "O_CLKM2_B"), + MTK_FUNCTION(6, "O_CLKM2_C"), + MTK_FUNCTION(7, "O_DBG_MON_A15") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO142"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N7"), + MTK_FUNCTION(2, "O_DISP_VSYNC2"), + MTK_FUNCTION(3, "O_DISP_VSYNC3"), + MTK_FUNCTION(4, "O_CLKM3_A"), + MTK_FUNCTION(5, "O_CLKM3_B"), + MTK_FUNCTION(6, "O_CLKM3_C"), + MTK_FUNCTION(7, "O_DBG_MON_A16") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO143"), + MTK_FUNCTION(1, "I0_MCU_M_PMIC_POC_I"), + MTK_FUNCTION(2, "I0_JTCK_SEL1"), + MTK_FUNCTION(3, "O_JTAGAP_JTCK"), + MTK_FUNCTION(4, "I0_ADSP_JTAG1_TCK"), + MTK_FUNCTION(5, "I0_ADSP_JTAG0_TCK"), + MTK_FUNCTION(6, "I0_CLUSTER0_UDI_TCK"), + MTK_FUNCTION(7, "I0_CLUSTER1_UDI_TCK") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO144"), + MTK_FUNCTION(1, "I0_MCU_B_PMIC_POC_I"), + MTK_FUNCTION(2, "B1_JTMS_SEL1"), + MTK_FUNCTION(3, "O_JTAGAP_JTMS"), + MTK_FUNCTION(4, "I1_ADSP_JTAG1_TMS"), + MTK_FUNCTION(5, "I1_ADSP_JTAG0_TMS"), + MTK_FUNCTION(6, "I0_CLUSTER0_UDI_TMS"), + MTK_FUNCTION(7, "I0_CLUSTER1_UDI_TMS") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO145"), + MTK_FUNCTION(1, "I1_UCTS0"), + MTK_FUNCTION(2, "I1_JTDI_SEL1"), + MTK_FUNCTION(3, "O_JTAGAP_JTDI"), + MTK_FUNCTION(4, "I1_ADSP_JTAG1_TDI"), + MTK_FUNCTION(5, "I1_ADSP_JTAG0_TDI"), + MTK_FUNCTION(6, "I0_CLUSTER0_UDI_TDI_0"), + MTK_FUNCTION(7, "I0_CLUSTER1_UDI_TDI_0") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO146"), + MTK_FUNCTION(1, "O_URTS0"), + MTK_FUNCTION(2, "O_JTDO_SEL1"), + MTK_FUNCTION(3, "I0_JTAGAP_JTDO"), + MTK_FUNCTION(4, "O_ADSP_JTAG1_TDO"), + MTK_FUNCTION(5, "O_ADSP_JTAG0_TDO"), + MTK_FUNCTION(6, "O_CLUSTER0_UDI_TDO_0"), + MTK_FUNCTION(7, "O_CLUSTER1_UDI_TDO_0") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO147"), + MTK_FUNCTION(2, "I1_JTRSTn_SEL1"), + MTK_FUNCTION(3, "O_JTAGAP_JTRSTn"), + MTK_FUNCTION(4, "I1_ADSP_JTAG1_TRSTN"), + MTK_FUNCTION(5, "I1_ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(6, "I0_CLUSTER0_UDI_NTRST"), + MTK_FUNCTION(7, "I0_CLUSTER1_UDI_NTRST") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO148"), + MTK_FUNCTION(1, "O_SRCLKENA0") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO149"), + MTK_FUNCTION(1, "O_SRCLKENA1") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO150"), + MTK_FUNCTION(2, "O_NVJTAG_SEL"), + MTK_FUNCTION(4, "I0_TSFDC_SDI"), + MTK_FUNCTION(5, "O_TSFDC_BG_COMP"), + MTK_FUNCTION(6, "O_CLKM3_C"), + MTK_FUNCTION(7, "I0_HFRP_JTAG0_TRSTN") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO151"), + MTK_FUNCTION(1, "I1_JTRSTn_SEL1"), + MTK_FUNCTION(2, "O_JTAGAP_JTRSTn"), + MTK_FUNCTION(6, "I0_HFRP_JTAG1_TRSTN"), + MTK_FUNCTION(7, "I1_ADSP_JTAG1_TRSTN") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO152"), + MTK_FUNCTION(1, "B1_JTMS_SEL1"), + MTK_FUNCTION(2, "O_JTAGAP_JTMS"), + MTK_FUNCTION(6, "I1_HFRP_JTAG1_TMS"), + MTK_FUNCTION(7, "I1_ADSP_JTAG1_TMS") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO153"), + MTK_FUNCTION(1, "O_JTDO_SEL1"), + MTK_FUNCTION(2, "I0_JTAGAP_JTDO"), + MTK_FUNCTION(6, "O_HFRP_JTAG1_TDO"), + MTK_FUNCTION(7, "O_ADSP_JTAG1_TDO") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO154"), + MTK_FUNCTION(1, "I0_JTCK_SEL1"), + MTK_FUNCTION(2, "O_JTAGAP_JTCK"), + MTK_FUNCTION(6, "I1_HFRP_JTAG1_TCK"), + MTK_FUNCTION(7, "I0_ADSP_JTAG1_TCK") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO155"), + MTK_FUNCTION(1, "I1_JTDI_SEL1"), + MTK_FUNCTION(2, "O_JTAGAP_JTDI"), + MTK_FUNCTION(6, "I1_HFRP_JTAG1_TDI"), + MTK_FUNCTION(7, "I1_ADSP_JTAG1_TDI") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO156"), + MTK_FUNCTION(1, "O_TP_UTXD0_VLP"), + MTK_FUNCTION(2, "O_UTXD3"), + MTK_FUNCTION(3, "O_VADSP_UTXD1"), + MTK_FUNCTION(4, "O_SPI_SIO0_S_MON0"), + MTK_FUNCTION(5, "O_ADSP_UTXD1"), + MTK_FUNCTION(6, "I0_SROOT_TCK"), + MTK_FUNCTION(7, "O_OSROOT_UTX") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO157"), + MTK_FUNCTION(1, "I1_TP_URXD0_VLP"), + MTK_FUNCTION(2, "I1_URXD3"), + MTK_FUNCTION(3, "I1_VADSP_URXD1"), + MTK_FUNCTION(4, "O_SPI_SIO1_S_MON0"), + MTK_FUNCTION(5, "I1_ADSP_URXD1"), + MTK_FUNCTION(6, "I0_SROOT_TDI"), + MTK_FUNCTION(7, "I1_OSROOT_URX") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO158"), + MTK_FUNCTION(1, "O_TP_URTS0_VLP"), + MTK_FUNCTION(2, "O_URTS3"), + MTK_FUNCTION(3, "O_VADSP_URTS1"), + MTK_FUNCTION(4, "O_SPI_SIO2_S_MON0"), + MTK_FUNCTION(5, "O_ADSP_URTX1"), + MTK_FUNCTION(6, "O_SROOT_TDO"), + MTK_FUNCTION(7, "O_PBUD_CTRL_UTXD_AO_VLP") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO159"), + MTK_FUNCTION(1, "I1_TP_UCTS0_VLP"), + MTK_FUNCTION(2, "I1_UCTS3"), + MTK_FUNCTION(3, "I1_VADSP_UCTS1"), + MTK_FUNCTION(4, "O_SPI_SIO3_S_MON0"), + MTK_FUNCTION(5, "I1_ADSP_UCTS1"), + MTK_FUNCTION(6, "I0_SROOT_TMS"), + MTK_FUNCTION(7, "I1_PBUD_CTRL_URXD_AO_VLP") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO160"), + MTK_FUNCTION(1, "O_UTXD1"), + MTK_FUNCTION(2, "O_ADSP_UTXD1"), + MTK_FUNCTION(3, "O_HFRP_UTXD1"), + MTK_FUNCTION(4, "O_CCU1_UTXD"), + MTK_FUNCTION(5, "O_PBUD_CTRL_UTXD_AO_VCORE"), + MTK_FUNCTION(6, "O_U4CP_UTXD"), + MTK_FUNCTION(7, "O_DBG_MON_B14") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO161"), + MTK_FUNCTION(1, "I1_URXD1"), + MTK_FUNCTION(2, "I1_ADSP_URXD1"), + MTK_FUNCTION(3, "I1_HFRP_URXD1"), + MTK_FUNCTION(4, "I1_CCU1_URXD"), + MTK_FUNCTION(5, "I1_PBUD_CTRL_URXD_AO_VCORE"), + MTK_FUNCTION(6, "I1_U4CP_URXD"), + MTK_FUNCTION(7, "O_DBG_MON_B15") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO162"), + MTK_FUNCTION(1, "O_URTS1"), + MTK_FUNCTION(2, "O_ADSP_URTX1"), + MTK_FUNCTION(3, "O_HFRP_URTS1"), + MTK_FUNCTION(4, "O_CCU0_UTXD"), + MTK_FUNCTION(5, "O_PBUD_CTRL_UTXD_AO_VCORE"), + MTK_FUNCTION(6, "O_U4CP_URTS"), + MTK_FUNCTION(7, "O_DBG_MON_B16") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO163"), + MTK_FUNCTION(1, "I1_UCTS1"), + MTK_FUNCTION(2, "I1_ADSP_UCTS1"), + MTK_FUNCTION(3, "I1_HFRP_UCTS1"), + MTK_FUNCTION(4, "I1_CCU0_URXD"), + MTK_FUNCTION(5, "I1_PBUD_CTRL_URXD_AO_VCORE"), + MTK_FUNCTION(6, "I1_U4CP_UCTS"), + MTK_FUNCTION(7, "O_DBG_MON_B17") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO164"), + MTK_FUNCTION(1, "O_HDMITX_DC_CTRL"), + MTK_FUNCTION(6, "I0_SROOT_NTRST"), + MTK_FUNCTION(7, "O_DBG_MON_B18") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO165"), + MTK_FUNCTION(1, "B1_DISP_SCL0"), + MTK_FUNCTION(4, "I1_EDP0_SCL"), + MTK_FUNCTION(5, "O_CCU0_URTS"), + MTK_FUNCTION(6, "O_CCU1_URTS"), + MTK_FUNCTION(7, "I1_MD32_6_RXD") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO166"), + MTK_FUNCTION(1, "B1_DISP_SDA0"), + MTK_FUNCTION(4, "B1_EDP0_SDA"), + MTK_FUNCTION(5, "I1_CCU0_UCTS"), + MTK_FUNCTION(6, "I1_CCU1_UCTS"), + MTK_FUNCTION(7, "O_MD32_6_GPIO0") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO167"), + MTK_FUNCTION(1, "B0_DISP_GPIO_N0"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST0"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST0"), + MTK_FUNCTION(7, "O_DBG_MON_B19") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO168"), + MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_0"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST1"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST1"), + MTK_FUNCTION(7, "O_DBG_MON_B20") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO169"), + MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_1"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST3"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST3"), + MTK_FUNCTION(7, "O_DBG_MON_B21") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO170"), + MTK_FUNCTION(1, "O_USB4_R_TCPC_RESET"), + MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST2"), + MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST2"), + MTK_FUNCTION(7, "O_DBG_MON_A17") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO171"), + MTK_FUNCTION(1, "O_PCIE_PERSTN"), + MTK_FUNCTION(4, "O_MD32_14_GPIO0"), + MTK_FUNCTION(7, "O_DBG_MON_B22") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO172"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_0P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_0P"), + MTK_FUNCTION(5, "O_HFRP_UTXD1"), + MTK_FUNCTION(6, "O_CCU0_UTXD"), + MTK_FUNCTION(7, "O_DBG_MON_B23") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO173"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_1P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_1P"), + MTK_FUNCTION(5, "I1_HFRP_URXD1"), + MTK_FUNCTION(6, "I1_CCU0_URXD"), + MTK_FUNCTION(7, "O_DBG_MON_B24") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO174"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_2P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_2P"), + MTK_FUNCTION(4, "O_MD32PCM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "O_HFRP_URTS1"), + MTK_FUNCTION(6, "O_CCU1_UTXD"), + MTK_FUNCTION(7, "O_DBG_MON_B25") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO175"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_3P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_3P"), + MTK_FUNCTION(4, "I1_MD32PCM_URXD_AO_VLP"), + MTK_FUNCTION(5, "I1_HFRP_UCTS1"), + MTK_FUNCTION(6, "I1_CCU1_URXD"), + MTK_FUNCTION(7, "O_DBG_MON_B26") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO176"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_4P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_4P"), + MTK_FUNCTION(4, "O_MD32_14_TXD"), + MTK_FUNCTION(7, "O_DBG_MON_B27") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO177"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_5P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_5P"), + MTK_FUNCTION(4, "I1_MD32_14_RXD"), + MTK_FUNCTION(7, "O_DBG_MON_B28") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO178"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_6P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_6P"), + MTK_FUNCTION(4, "O_MD32_15_TXD"), + MTK_FUNCTION(7, "O_DBG_MON_B29") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO179"), + MTK_FUNCTION(1, "B1_PCIE_CLKREQN_7P"), + MTK_FUNCTION(2, "I1_PCIE_PRSNT_7P"), + MTK_FUNCTION(4, "I1_MD32_15_RXD"), + MTK_FUNCTION(7, "O_DBG_MON_B30") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO180"), + MTK_FUNCTION(1, "I1_PCIE_WAKEN"), + MTK_FUNCTION(4, "O_MD32_15_GPIO0"), + MTK_FUNCTION(7, "O_DBG_MON_B31") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "B_GPIO181"), + MTK_FUNCTION(1, "O_GPU_PWRGOOD") + ), +}; + +static struct mtk_eint_pin eint_pins_mt8901[] = { + MTK_EINT_PIN(0, 0, 16, 0), + MTK_EINT_PIN(1, 0, 17, 0), + MTK_EINT_PIN(2, 0, 18, 0), + MTK_EINT_PIN(3, 0, 19, 0), + MTK_EINT_PIN(4, 0, 20, 0), + MTK_EINT_PIN(5, 0, 21, 0), + MTK_EINT_PIN(6, 0, 22, 0), + MTK_EINT_PIN(7, 0, 23, 0), + MTK_EINT_PIN(8, 0, 24, 0), + MTK_EINT_PIN(9, 0, 25, 0), + MTK_EINT_PIN(10, 0, 26, 0), + MTK_EINT_PIN(11, 0, 27, 0), + MTK_EINT_PIN(12, INVALID_BASE, 0, 0), + MTK_EINT_PIN(13, INVALID_BASE, 0, 0), + MTK_EINT_PIN(14, 0, 28, 0), + MTK_EINT_PIN(15, 0, 29, 0), + MTK_EINT_PIN(16, 0, 30, 0), + MTK_EINT_PIN(17, INVALID_BASE, 0, 0), + MTK_EINT_PIN(18, INVALID_BASE, 0, 0), + MTK_EINT_PIN(19, 0, 31, 0), + MTK_EINT_PIN(20, 0, 0, 1), + MTK_EINT_PIN(21, 0, 1, 1), + MTK_EINT_PIN(22, INVALID_BASE, 0, 0), + MTK_EINT_PIN(23, 0, 2, 1), + MTK_EINT_PIN(24, 0, 3, 1), + MTK_EINT_PIN(25, 0, 4, 1), + MTK_EINT_PIN(26, 0, 5, 1), + MTK_EINT_PIN(27, 0, 6, 1), + MTK_EINT_PIN(28, 0, 7, 1), + MTK_EINT_PIN(29, 0, 8, 1), + MTK_EINT_PIN(30, 0, 9, 1), + MTK_EINT_PIN(31, 0, 10, 1), + MTK_EINT_PIN(32, 1, 0, 1), + MTK_EINT_PIN(33, 0, 32, 0), + MTK_EINT_PIN(34, 0, 33, 0), + MTK_EINT_PIN(35, 0, 34, 0), + MTK_EINT_PIN(36, 1, 1, 1), + MTK_EINT_PIN(37, 0, 11, 1), + MTK_EINT_PIN(38, 0, 12, 1), + MTK_EINT_PIN(39, 0, 35, 0), + MTK_EINT_PIN(40, 0, 36, 0), + MTK_EINT_PIN(41, 0, 37, 0), + MTK_EINT_PIN(42, 0, 13, 1), + MTK_EINT_PIN(43, 0, 14, 1), + MTK_EINT_PIN(44, 0, 38, 0), + MTK_EINT_PIN(45, 0, 39, 0), + MTK_EINT_PIN(46, 0, 40, 0), + MTK_EINT_PIN(47, 0, 15, 1), + MTK_EINT_PIN(48, 0, 41, 0), + MTK_EINT_PIN(49, 0, 42, 0), + MTK_EINT_PIN(50, 0, 43, 0), + MTK_EINT_PIN(51, 0, 44, 0), + MTK_EINT_PIN(52, 0, 45, 0), + MTK_EINT_PIN(53, 0, 46, 0), + MTK_EINT_PIN(54, 2, 13, 0), + MTK_EINT_PIN(55, 2, 14, 0), + MTK_EINT_PIN(56, INVALID_BASE, 0, 0), + MTK_EINT_PIN(57, INVALID_BASE, 0, 0), + MTK_EINT_PIN(58, INVALID_BASE, 0, 0), + MTK_EINT_PIN(59, INVALID_BASE, 0, 0), + MTK_EINT_PIN(60, 1, 3, 0), + MTK_EINT_PIN(61, 1, 4, 0), + MTK_EINT_PIN(62, 1, 5, 0), + MTK_EINT_PIN(63, 1, 6, 0), + MTK_EINT_PIN(64, 1, 7, 0), + MTK_EINT_PIN(65, 1, 8, 0), + MTK_EINT_PIN(66, 2, 15, 0), + MTK_EINT_PIN(67, 2, 16, 0), + MTK_EINT_PIN(68, 1, 2, 1), + MTK_EINT_PIN(69, INVALID_BASE, 0, 0), + MTK_EINT_PIN(70, 2, 17, 0), + MTK_EINT_PIN(71, 2, 18, 0), + MTK_EINT_PIN(72, 2, 19, 0), + MTK_EINT_PIN(73, 2, 20, 0), + MTK_EINT_PIN(74, 2, 21, 0), + MTK_EINT_PIN(75, 2, 22, 0), + MTK_EINT_PIN(76, 2, 23, 0), + MTK_EINT_PIN(77, 2, 24, 0), + MTK_EINT_PIN(78, 2, 25, 0), + MTK_EINT_PIN(79, 2, 26, 0), + MTK_EINT_PIN(80, 2, 27, 0), + MTK_EINT_PIN(81, 2, 28, 0), + MTK_EINT_PIN(82, 2, 29, 1), + MTK_EINT_PIN(83, 2, 30, 1), + MTK_EINT_PIN(84, 2, 31, 1), + MTK_EINT_PIN(85, 2, 32, 1), + MTK_EINT_PIN(86, 2, 33, 0), + MTK_EINT_PIN(87, 2, 34, 0), + MTK_EINT_PIN(88, 2, 35, 0), + MTK_EINT_PIN(89, 2, 36, 0), + MTK_EINT_PIN(90, 2, 37, 0), + MTK_EINT_PIN(91, 2, 38, 0), + MTK_EINT_PIN(92, 2, 39, 0), + MTK_EINT_PIN(93, 2, 40, 0), + MTK_EINT_PIN(94, 2, 0, 1), + MTK_EINT_PIN(95, 2, 1, 1), + MTK_EINT_PIN(96, 2, 2, 1), + MTK_EINT_PIN(97, 2, 3, 1), + MTK_EINT_PIN(98, 2, 41, 0), + MTK_EINT_PIN(99, 2, 4, 1), + MTK_EINT_PIN(100, 2, 5, 1), + MTK_EINT_PIN(101, 2, 6, 1), + MTK_EINT_PIN(102, 2, 7, 1), + MTK_EINT_PIN(103, 2, 8, 1), + MTK_EINT_PIN(104, 2, 9, 1), + MTK_EINT_PIN(105, 2, 10, 1), + MTK_EINT_PIN(106, 0, 47, 0), + MTK_EINT_PIN(107, 0, 48, 0), + MTK_EINT_PIN(108, 0, 49, 0), + MTK_EINT_PIN(109, 0, 50, 0), + MTK_EINT_PIN(110, 0, 51, 0), + MTK_EINT_PIN(111, 0, 52, 0), + MTK_EINT_PIN(112, 2, 42, 0), + MTK_EINT_PIN(113, 2, 43, 0), + MTK_EINT_PIN(114, 2, 44, 0), + MTK_EINT_PIN(115, 2, 45, 0), + MTK_EINT_PIN(116, 2, 46, 0), + MTK_EINT_PIN(117, 2, 47, 0), + MTK_EINT_PIN(118, 2, 48, 0), + MTK_EINT_PIN(119, 2, 49, 0), + MTK_EINT_PIN(120, 2, 50, 0), + MTK_EINT_PIN(121, 2, 51, 0), + MTK_EINT_PIN(122, 2, 52, 0), + MTK_EINT_PIN(123, 2, 53, 0), + MTK_EINT_PIN(124, 2, 54, 0), + MTK_EINT_PIN(125, 2, 55, 0), + MTK_EINT_PIN(126, 2, 56, 0), + MTK_EINT_PIN(127, 2, 57, 0), + MTK_EINT_PIN(128, 2, 58, 0), + MTK_EINT_PIN(129, 2, 59, 0), + MTK_EINT_PIN(130, 2, 60, 0), + MTK_EINT_PIN(131, 2, 61, 0), + MTK_EINT_PIN(132, 2, 62, 0), + MTK_EINT_PIN(133, 2, 63, 0), + MTK_EINT_PIN(134, 2, 64, 0), + MTK_EINT_PIN(135, 2, 65, 0), + MTK_EINT_PIN(136, 2, 66, 0), + MTK_EINT_PIN(137, 2, 67, 0), + MTK_EINT_PIN(138, 2, 11, 1), + MTK_EINT_PIN(139, 2, 12, 1), + MTK_EINT_PIN(140, 2, 68, 0), + MTK_EINT_PIN(141, 2, 69, 0), + MTK_EINT_PIN(142, 2, 70, 0), + MTK_EINT_PIN(143, 2, 71, 0), + MTK_EINT_PIN(144, 2, 72, 0), + MTK_EINT_PIN(145, 2, 73, 0), + MTK_EINT_PIN(146, 2, 74, 0), + MTK_EINT_PIN(147, 2, 75, 0), + MTK_EINT_PIN(148, INVALID_BASE, 0, 0), + MTK_EINT_PIN(149, INVALID_BASE, 0, 0), + MTK_EINT_PIN(150, 2, 76, 0), + MTK_EINT_PIN(151, 2, 77, 0), + MTK_EINT_PIN(152, 2, 78, 0), + MTK_EINT_PIN(153, 2, 79, 0), + MTK_EINT_PIN(154, 2, 80, 0), + MTK_EINT_PIN(155, 2, 81, 0), + MTK_EINT_PIN(156, 2, 82, 0), + MTK_EINT_PIN(157, 2, 83, 0), + MTK_EINT_PIN(158, 2, 84, 0), + MTK_EINT_PIN(159, 2, 85, 0), + MTK_EINT_PIN(160, 2, 86, 0), + MTK_EINT_PIN(161, 2, 87, 0), + MTK_EINT_PIN(162, 2, 88, 0), + MTK_EINT_PIN(163, 2, 89, 0), + MTK_EINT_PIN(164, 2, 90, 0), + MTK_EINT_PIN(165, 2, 91, 0), + MTK_EINT_PIN(166, 2, 92, 0), + MTK_EINT_PIN(167, 2, 93, 0), + MTK_EINT_PIN(168, 2, 94, 0), + MTK_EINT_PIN(169, 2, 95, 0), + MTK_EINT_PIN(170, 2, 96, 0), + MTK_EINT_PIN(171, 2, 97, 0), + MTK_EINT_PIN(172, 2, 98, 0), + MTK_EINT_PIN(173, 2, 99, 0), + MTK_EINT_PIN(174, 2, 100, 0), + MTK_EINT_PIN(175, 2, 101, 0), + MTK_EINT_PIN(176, 2, 102, 0), + MTK_EINT_PIN(177, 2, 103, 0), + MTK_EINT_PIN(178, 2, 104, 0), + MTK_EINT_PIN(179, 2, 105, 0), + MTK_EINT_PIN(180, 2, 106, 0), + MTK_EINT_PIN(181, 3, 0, 0), + MTK_EINT_PIN(182, 3, 1, 0), + MTK_EINT_PIN(183, 3, 2, 0), + MTK_EINT_PIN(184, 3, 3, 0), + MTK_EINT_PIN(185, 3, 4, 0), + MTK_EINT_PIN(186, 3, 5, 0), + MTK_EINT_PIN(187, 3, 6, 0), + MTK_EINT_PIN(188, 3, 7, 0), + MTK_EINT_PIN(189, 3, 8, 0), + MTK_EINT_PIN(190, 3, 9, 0), + MTK_EINT_PIN(191, 3, 10, 0), + MTK_EINT_PIN(192, 3, 11, 0), + MTK_EINT_PIN(193, 3, 12, 0), + MTK_EINT_PIN(194, 3, 13, 0), + MTK_EINT_PIN(195, 3, 14, 0), + MTK_EINT_PIN(196, 3, 15, 0), + MTK_EINT_PIN(197, 3, 16, 0), + MTK_EINT_PIN(198, 3, 17, 0), + MTK_EINT_PIN(199, 3, 18, 0), + MTK_EINT_PIN(200, 3, 19, 0), + MTK_EINT_PIN(201, 3, 20, 0), + MTK_EINT_PIN(202, 3, 21, 0), + MTK_EINT_PIN(203, 3, 22, 0), + MTK_EINT_PIN(204, 3, 23, 0), + MTK_EINT_PIN(205, 3, 24, 0), + MTK_EINT_PIN(206, 3, 25, 0), + MTK_EINT_PIN(207, 3, 26, 0), + MTK_EINT_PIN(208, 3, 27, 0), +}; + +#endif /* __PINCTRL__MTK_MT8901_H */ --- linux-nvidia-7.0.0.orig/drivers/pinctrl/mediatek/pinctrl-paris.c +++ linux-nvidia-7.0.0/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -3,7 +3,7 @@ * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin * bindings for MediaTek SoC. * - * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2018-2025 MediaTek Inc. * Author: Sean Wang * Zhiyong Tao * Hongzhou.Yang @@ -936,6 +936,15 @@ return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); } +static void mtk_pinctrl_gpio_range_init(struct mtk_pinctrl *hw, struct gpio_chip *chip) +{ + hw->range.name = "mtk_pinctrl_gpio_range"; + hw->range.id = 0; + hw->range.pin_base = 0; + hw->range.base = chip->base; + hw->range.npins = hw->soc->npins; +} + static int mtk_build_gpiochip(struct mtk_pinctrl *hw) { struct gpio_chip *chip = &hw->chip; @@ -959,6 +968,8 @@ if (ret < 0) return ret; + mtk_pinctrl_gpio_range_init(hw, chip); + return 0; } @@ -997,6 +1008,7 @@ struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; + struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev); int err, i; hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); @@ -1021,16 +1033,20 @@ return -ENOMEM; for (i = 0; i < hw->soc->nbase_names; i++) { - hw->base[i] = devm_platform_ioremap_resource_byname(pdev, - hw->soc->base_names[i]); + hw->base[i] = is_of_node(fwnode) + ? devm_platform_ioremap_resource_byname(pdev, hw->soc->base_names[i]) + : devm_platform_get_and_ioremap_resource(pdev, i, NULL); if (IS_ERR(hw->base[i])) return PTR_ERR(hw->base[i]); } hw->nbase = hw->soc->nbase_names; - hw->rsel_si_unit = of_property_read_bool(hw->dev->of_node, + if (is_of_node(fwnode)) + hw->rsel_si_unit = of_property_read_bool(hw->dev->of_node, "mediatek,rsel-resistance-in-si-unit"); + else + hw->rsel_si_unit = false; spin_lock_init(&hw->lock); @@ -1077,6 +1093,8 @@ if (err) return dev_err_probe(dev, err, "Failed to add gpio_chip\n"); + pinctrl_add_gpio_range(hw->pctrl, &hw->range); + platform_set_drvdata(pdev, hw); return 0; --- linux-nvidia-7.0.0.orig/drivers/platform/arm64/Kconfig +++ linux-nvidia-7.0.0/drivers/platform/arm64/Kconfig @@ -90,4 +90,31 @@ Say M or Y here to include this support. +config EC_LENOVO_YOGA_SLIM7X + tristate "Lenovo Yoga Slim 7x Embedded Controller driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on I2C + help + Select this option to enable driver for the EC found in the Lenovo + Yoga Slim 7x. + + This driver currently supports reporting input event for microphone + mute button, and reporting device suspend to the EC so it can take + appropriate actions. + +config NVIDIA_FFA_EC + tristate "NVIDIA FFA EC services driver" + depends on ARM_FFA_TRANSPORT || COMPILE_TEST + depends on ACPI + depends on ACPI_FFH + help + Enable NVIDIA FFA EC services. + For GB10 and other similar SOC’s, to communicate with embedded controller, a new + specification is being defined. It is currently in draft stage and maintained in + https://github.com/OpenDevicePartnership/documentation/blob/main/bookshelf/Shelf%204%20Specifications/EC%20Interface/src/secure-ec-services-overview.md + + Say M or Y here to include this support. + +source "drivers/platform/arm64/nvidia/Kconfig" + endif # ARM64_PLATFORM_DEVICES --- linux-nvidia-7.0.0.orig/drivers/platform/arm64/Makefile +++ linux-nvidia-7.0.0/drivers/platform/arm64/Makefile @@ -9,3 +9,6 @@ obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o +obj-$(CONFIG_EC_LENOVO_YOGA_SLIM7X) += lenovo-yoga-slim7x.o +obj-$(CONFIG_NVIDIA_FFA_EC) += nvidia-ffa-ec.o +obj-y += nvidia/ --- linux-nvidia-7.0.0.orig/drivers/platform/arm64/lenovo-yoga-slim7x.c +++ linux-nvidia-7.0.0/drivers/platform/arm64/lenovo-yoga-slim7x.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Maya Matuszczyk + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include + +// These are the registers that i know about available from SMBUS +#define EC_IRQ_REASON_REG 0x05 +#define EC_SUSPEND_RESUME_REG 0x23 +#define EC_IRQ_ENABLE_REG 0x35 +#define EC_BACKLIGHT_STATUS_REG 0x83 +#define EC_MIC_MUTE_LED_REG 0x84 +#define EC_AC_STATUS_REG 0x90 + +// Valid values for EC_SUSPEND_RESUME_REG +#define EC_NOTIFY_SUSPEND_ENTER 0x01 +#define EC_NOTIFY_SUSPEND_EXIT 0x00 +#define EC_NOTIFY_SCREEN_OFF 0x03 +#define EC_NOTIFY_SCREEN_ON 0x04 + +// These are the values in EC_IRQ_REASON_REG that i could find in DSDT +#define EC_IRQ_MICMUTE_BUTTON 0x04 +#define EC_IRQ_FAN1_STATUS_CHANGE 0x30 +#define EC_IRQ_FAN2_STATUS_CHANGE 0x31 +#define EC_IRQ_FAN1_SPEED_CHANGE 0x32 +#define EC_IRQ_FAN2_SPEED_CHANGE 0x33 +#define EC_IRQ_COMPLETED_LUT_UPDATE 0x34 +#define EC_IRQ_COMPLETED_FAN_PROFILE_SWITCH 0x35 +#define EC_IRQ_THERMISTOR_1_TEMP_THRESHOLD_CROSS 0x36 +#define EC_IRQ_THERMISTOR_2_TEMP_THRESHOLD_CROSS 0x37 +#define EC_IRQ_THERMISTOR_3_TEMP_THRESHOLD_CROSS 0x38 +#define EC_IRQ_THERMISTOR_4_TEMP_THRESHOLD_CROSS 0x39 +#define EC_IRQ_THERMISTOR_5_TEMP_THRESHOLD_CROSS 0x3a +#define EC_IRQ_THERMISTOR_6_TEMP_THRESHOLD_CROSS 0x3b +#define EC_IRQ_THERMISTOR_7_TEMP_THRESHOLD_CROSS 0x3c +#define EC_IRQ_RECOVERED_FROM_RESET 0x3d +#define EC_IRQ_LENOVO_SUPPORT_KEY 0x90 +#define EC_IRQ_FN_Q 0x91 +#define EC_IRQ_FN_M 0x92 +#define EC_IRQ_FN_SPACE 0x93 +#define EC_IRQ_FN_R 0x94 +#define EC_IRQ_FNLOCK_ON 0x95 +#define EC_IRQ_FNLOCK_OFF 0x96 +#define EC_IRQ_FN_N 0x97 +#define EC_IRQ_AI 0x9a +#define EC_IRQ_NPU 0x9b + +struct yoga_slim7x_ec { + struct i2c_client *client; + struct input_dev *idev; + struct mutex lock; +}; + +static irqreturn_t yoga_slim7x_ec_irq(int irq, void *data) +{ + struct yoga_slim7x_ec *ec = data; + struct device *dev = &ec->client->dev; + int val; + + guard(mutex)(&ec->lock); + + val = i2c_smbus_read_byte_data(ec->client, EC_IRQ_REASON_REG); + if (val < 0) { + dev_err(dev, "Failed to get EC IRQ reason: %d\n", val); + return IRQ_HANDLED; + } + + switch (val) { + case EC_IRQ_MICMUTE_BUTTON: + input_report_key(ec->idev, KEY_MICMUTE, 1); + input_sync(ec->idev); + input_report_key(ec->idev, KEY_MICMUTE, 0); + input_sync(ec->idev); + break; + default: + dev_info(dev, "Unhandled EC IRQ reason: %d\n", val); + } + + return IRQ_HANDLED; +} + +static int yoga_slim7x_ec_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct yoga_slim7x_ec *ec; + int ret; + + ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL); + if (!ec) + return -ENOMEM; + + mutex_init(&ec->lock); + ec->client = client; + + ec->idev = devm_input_allocate_device(dev); + if (!ec->idev) + return -ENOMEM; + ec->idev->name = "yoga-slim7x-ec"; + ec->idev->phys = "yoga-slim7x-ec/input0"; + input_set_capability(ec->idev, EV_KEY, KEY_MICMUTE); + + ret = input_register_device(ec->idev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to register input device\n"); + + ret = devm_request_threaded_irq(dev, client->irq, + NULL, yoga_slim7x_ec_irq, + IRQF_ONESHOT, "yoga_slim7x_ec", ec); + if (ret < 0) + return dev_err_probe(dev, ret, "Unable to request irq\n"); + + ret = i2c_smbus_write_byte_data(client, EC_IRQ_ENABLE_REG, 0x01); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable interrupts\n"); + + return 0; +} + +static void yoga_slim7x_ec_remove(struct i2c_client *client) +{ + struct device *dev = &client->dev; + int ret; + + ret = i2c_smbus_write_byte_data(client, EC_IRQ_ENABLE_REG, 0x00); + if (ret < 0) + dev_err(dev, "Failed to disable interrupts: %d\n", ret); +} + +static int yoga_slim7x_ec_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + int ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SCREEN_OFF); + if (ret) + return ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SUSPEND_ENTER); + if (ret) + return ret; + + return 0; +} + +static int yoga_slim7x_ec_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + int ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SUSPEND_EXIT); + if (ret) + return ret; + + ret = i2c_smbus_write_byte_data(client, EC_SUSPEND_RESUME_REG, EC_NOTIFY_SCREEN_ON); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id yoga_slim7x_ec_of_match[] = { + { .compatible = "lenovo,yoga-slim7x-ec" }, + {} +}; +MODULE_DEVICE_TABLE(of, yoga_slim7x_ec_of_match); + +static const struct i2c_device_id yoga_slim7x_ec_i2c_id_table[] = { + { "yoga-slim7x-ec", }, + {} +}; +MODULE_DEVICE_TABLE(i2c, yoga_slim7x_ec_i2c_id_table); + +static DEFINE_SIMPLE_DEV_PM_OPS(yoga_slim7x_ec_pm_ops, + yoga_slim7x_ec_suspend, + yoga_slim7x_ec_resume); + +static struct i2c_driver yoga_slim7x_ec_i2c_driver = { + .driver = { + .name = "yoga-slim7x-ec", + .of_match_table = yoga_slim7x_ec_of_match, + .pm = &yoga_slim7x_ec_pm_ops + }, + .probe = yoga_slim7x_ec_probe, + .remove = yoga_slim7x_ec_remove, + .id_table = yoga_slim7x_ec_i2c_id_table, +}; +module_i2c_driver(yoga_slim7x_ec_i2c_driver); + +MODULE_DESCRIPTION("Lenovo Yoga Slim 7x Embedded Controller"); +MODULE_LICENSE("GPL"); --- linux-nvidia-7.0.0.orig/drivers/platform/arm64/nvidia-ffa-ec.c +++ linux-nvidia-7.0.0/drivers/platform/arm64/nvidia-ffa-ec.c @@ -0,0 +1,829 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "nvidia-ffa-ec" + +/* platform device for FFA ACPI device (HID MSFT000C) */ +static struct platform_device *ffa_pdev; + +/* FFA device for EC notification service */ +static struct ffa_device *notify_ffa_dev; + +static const uuid_t nvidia_ec_notify_service_uuid = + UUID_INIT(0xb510b3a3, 0x59f6, 0x4054, 0xba, 0x7a, 0xff, 0x2e, 0xb1, 0xea, 0xc7, 0x65); + +static const uuid_t nvidia_ec_managment_service_uuid = + UUID_INIT(0x330c1273, 0xfde5, 0x4757, 0x98, 0x19, 0x5b, 0x65, 0x39, 0x03, 0x75, 0x02); + +static const uuid_t nvidia_ec_power_service_uuid = + UUID_INIT(0x7157addf, 0x2fbe, 0x4c63, 0xae, 0x95, 0xef, 0xac, 0x16, 0xe3, 0xb0, 0x1c); + +static const uuid_t nvidia_ec_battery_service_uuid = + UUID_INIT(0x25cb5207, 0xac36, 0x427d, 0xaa, 0xef, 0x3a, 0xa7, 0x88, 0x77, 0xd2, 0x7e); + +static const uuid_t nvidia_ec_thermal_service_uuid = + UUID_INIT(0x31f56da7, 0x593c, 0x4d72, 0xa4, 0xb3, 0x8f, 0xc7, 0x17, 0x1a, 0xc0, 0x73); + +static const uuid_t nvidia_ec_fan_service_uuid = + UUID_INIT(0x7697530c, 0xd079, 0x4ec1, 0xa4, 0xc4, 0xcf, 0x0d, 0x2b, 0xdc, 0x93, 0xfa); + +static const uuid_t nvidia_ec_ucsi_service_uuid = + UUID_INIT(0x65467f50, 0x827f, 0x4e4f, 0x87, 0x70, 0xdb, 0xf4, 0xc3, 0xf7, 0x7f, 0x45); + +static const uuid_t nvidia_ec_input_service_uuid = + UUID_INIT(0xe3168a99, 0x4a57, 0x4a2b, 0x8c, 0x5e, 0x11, 0xbc, 0xfe, 0xc7, 0x34, 0x06); + +static const uuid_t nvidia_ec_time_alarm_service_uuid = + UUID_INIT(0x23ea63ed, 0xb593, 0x46ea, 0xb0, 0x27, 0x89, 0x24, 0xdf, 0x88, 0xe9, 0x2f); + +static const guid_t nvidia_notify_bind_guid = + GUID_INIT(0xdaffd814, 0x6eba, 0x4d8c, 0x8a, 0x91, 0xbc, 0x9b, 0xbf, 0x4a, 0xa3, 0x01); + +static const guid_t nvidia_notify_dsm_guid = + GUID_INIT(0x7681541e, 0x8827, 0x4239, 0x8d, 0x9d, 0x36, 0xbe, 0x7f, 0xe1, 0x25, 0x42); + +#define NVIDIA_FFA_MAX_NOTIFICATIONS 64 + +/* EC service FFA device structure */ +struct nvidia_ec_ffa_device { + struct ffa_device *ffa_dev; + u8 notification_count; + u8 notification_id[NVIDIA_FFA_MAX_NOTIFICATIONS]; + struct list_head list; +}; + +/* List to contain all EC services FFA device */ +static LIST_HEAD(nvidia_ec_ffa_dev_head); + +/* Lock to serialize EC services FFA device list access */ +static DEFINE_MUTEX(nvidia_ffa_lock); + +/* EC secure services FFA packet structure sent via ACPI */ +struct nvidia_ec_ffa_packet { + u8 status; + u8 length; + u8 uuid[UUID_SIZE]; + u8 rawdata[]; +} __packed; + +/* + * ACPI ASL code uses ToUUID() macro which encodes it in mixed-endian format. + * Convert the AML UUID buffer into FFA UUID format. + */ +static uuid_t nvidia_get_uuid_from_aml_buf(const u8 *buf) +{ + return (uuid_t) {{ buf[3], buf[2], buf[1], buf[0], + buf[5], buf[4], buf[7], buf[6], + buf[8], buf[9], buf[10], buf[11], + buf[12], buf[13], buf[14], buf[15] }}; +} + +/* + * ACPI ASL code uses ToUUID() macro which encodes it in mixed-endian format. + * Convert UUID buffer to AML UUID. + */ +static void nvidia_uuid_to_aml_uuid_buf(const uuid_t *uuid, u8 *buf) +{ + const u8 *src = (u8 *)uuid; + + buf[0] = src[3]; + buf[1] = src[2]; + buf[2] = src[1]; + buf[3] = src[0]; + + buf[4] = src[5]; + buf[5] = src[4]; + buf[6] = src[7]; + buf[7] = src[6]; + + memcpy(buf + 8, src + 8, 8); +} + +static int nvidia_ffa_rescan_acpi_device(struct device *dev, void *data) +{ + struct acpi_device *adev = to_acpi_device(dev); + + if (acpi_dev_hid_uid_match(adev, data, NULL)) { + acpi_bus_scan(adev->handle); + return 1; + } + + return 0; +} + +static const char *nvidia_get_acpi_id_from_uuid(uuid_t *uuid) +{ + if (uuid_equal(uuid, &nvidia_ec_battery_service_uuid)) + return "PNP0C0A"; + + if (uuid_equal(uuid, &nvidia_ec_time_alarm_service_uuid)) + return "ACPI000E"; + + if (uuid_equal(uuid, &nvidia_ec_fan_service_uuid)) + return "PNP0C0B"; + + if (uuid_equal(uuid, &nvidia_ec_ucsi_service_uuid)) + return "PNP0CA0"; + + return NULL; +} + +/* + * Fill the virtual notification IDs array supported by the current FFA device. + * ACPI _DSD object contains notification mapping. It uses nexted package + * acpi object. + * + * From the example given in + * https://github.com/OpenDevicePartnership/documentation/blob/main/bookshelf/Shelf%204%20Specifications/EC%20Interface/src/secure-ec-services-overview.md#register-notification + * + * pkg1 Name(_DSD, Package() { + * pkg1_guid ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Prop UUID + * pkg2 Package() { + * pkg3 Package(2) { + * pkg3_prop "arm-arml0002-ffa-ntf-bind", + * pkg4 Package() { + * pkg4_rev 1, // Revision + * pkg4_count 1, // Count of following packages + * pkg5 Package () { + * pkg5_uuid ToUUID("330c1273-fde5-4757-9819-5b6539037502"), // Service1 UUID + * pkg6 Package () { + * pkg6_notify_id[] 0x01, // Cookie1 (UINT32) + * 0x07, // Cookie2 + * } + * }, + * } + * } + * } + * }) // _DSD() + * + * The variable names in this function are according to above. + */ +static int nvidia_ffa_fill_notification_map(struct nvidia_ec_ffa_device *ec_ffa_dev) +{ + struct acpi_device *adev = ACPI_COMPANION(&ffa_pdev->dev); + struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object *pkg1, *pkg1_guid; + union acpi_object *pkg2; + union acpi_object *pkg3, *pkg3_prop; + union acpi_object *pkg4, *pkg4_rev, *pkg4_count; + acpi_status status; + int i; + + status = acpi_evaluate_object_typed(adev->handle, "_DSD", NULL, + &output, ACPI_TYPE_PACKAGE); + if (ACPI_FAILURE(status)) { + dev_err(&ffa_pdev->dev, "ACPI _DSD object not found\n"); + return -ENODEV; + } + + pkg1 = output.pointer; + + /* + * _DSD returns a Package() with one or more pairs of elements. + * The first element of each pair is a Universal Unique Identifier (UUID). + * The second element of each pair is another Package() Data Structure. + * + * The _DSD for FFA device will have only one pair of elements so + * pkg1 elements count should be 2. + */ + if (pkg1->package.count != 2) { + kfree(output.pointer); + return -EINVAL; + } + + pkg1_guid = &pkg1->package.elements[0]; + pkg2 = &pkg1->package.elements[1]; + if (pkg1_guid->type != ACPI_TYPE_BUFFER || + pkg1_guid->buffer.length != UUID_SIZE || + pkg2->type != ACPI_TYPE_PACKAGE) { + kfree(output.pointer); + return -EINVAL; + } + + /* Check if GUID macthes with notify device prop GUID */ + if (!guid_equal((guid_t *)pkg1_guid->buffer.pointer, + &nvidia_notify_bind_guid)) { + kfree(output.pointer); + return -EINVAL; + } + + /* pkg3 should conatin 1 element with package type */ + if (pkg2->package.count != 1) { + kfree(output.pointer); + return -EINVAL; + } + + pkg3 = &pkg2->package.elements[0]; + if (pkg3->type != ACPI_TYPE_PACKAGE) { + kfree(output.pointer); + return -EINVAL; + } + + pkg3_prop = &pkg3->package.elements[0]; + if (pkg3_prop->type != ACPI_TYPE_STRING || + strncmp(pkg3_prop->string.pointer, + "arm-arml0002-ffa-ntf-bind", + pkg3_prop->string.length)) { + kfree(output.pointer); + return -EINVAL; + } + + pkg4 = &pkg3->package.elements[1]; + /* + * pkg4 should have minimum 3 elements (revision, count and minimum + * one notification map package) + */ + if (pkg4->type != ACPI_TYPE_PACKAGE || + pkg4->package.count < 3) { + kfree(output.pointer); + return -EINVAL; + } + + pkg4_rev = &pkg4->package.elements[0]; + pkg4_count = &pkg4->package.elements[1]; + + /* Check if revision is 1 */ + if (pkg4_rev->type != ACPI_TYPE_INTEGER || + pkg4_rev->integer.value != 1) { + kfree(output.pointer); + return -EINVAL; + } + + /* + * The pkg4_count represents the count of following packages. + * pkg4_count + 1 (for revision) + 1 (for pkg4_count itself) should + * match total number of elements in pkg4. + */ + if (pkg4_count->type != ACPI_TYPE_INTEGER || + (pkg4_count->integer.value + 2) != pkg4->package.count) { + kfree(output.pointer); + return -EINVAL; + } + + /* + * Traverse the array of notification map packages. + * Each notification map package contains 2 elements, UUID + * and notification ID array package. Check if there is a notification + * map for the FFA device by comparing UUID and update the + * notification_id[] and notification_count. + */ + for (i = 2; i < pkg4->package.count; i++) { + union acpi_object *pkg5_uuid, *pkg5 = &pkg4->package.elements[2]; + union acpi_object *pkg6; + uuid_t uuid; + int j; + + if (pkg5->type != ACPI_TYPE_PACKAGE && + pkg5->package.count != 2) { + kfree(output.pointer); + return -EINVAL; + } + + pkg5_uuid = &pkg5->package.elements[0]; + pkg6 = &pkg5->package.elements[1]; + if (pkg5_uuid->type != ACPI_TYPE_BUFFER || + pkg5_uuid->buffer.length != UUID_SIZE || + pkg6->type != ACPI_TYPE_PACKAGE) { + kfree(output.pointer); + return -EINVAL; + } + + uuid = nvidia_get_uuid_from_aml_buf(pkg5_uuid->buffer.pointer); + if (!uuid_equal(&uuid, &ec_ffa_dev->ffa_dev->uuid)) + continue; + + for (j = 0; j < pkg6->package.count; j++) { + union acpi_object *pkg6_notify_id = &pkg6->package.elements[j]; + + if (pkg6_notify_id->type != ACPI_TYPE_INTEGER) { + kfree(output.pointer); + return -EINVAL; + } + + ec_ffa_dev->notification_id[j] = pkg6_notify_id->integer.value; + } + + ec_ffa_dev->notification_count = pkg6->package.count; + kfree(output.pointer); + return 0; + } + + kfree(output.pointer); + return 0; +} + +/* + * Notification EC service callback. + * Get the ffa device from callback data and invoke notification _DSM with + * notify_id. + * + * The details regarding _DSM is documented in + * https://github.com/OpenDevicePartnership/documentation/tree/main/bookshelf/Shelf%204%20Specifications#notification-events + */ +static void nvidia_ffa_ec_service_notif_callback(int notify_id, void *cb_data) +{ + struct acpi_device *adev = ACPI_COMPANION(&ffa_pdev->dev); + struct ffa_device *ffa_dev = (struct ffa_device *)cb_data; + union acpi_object args[2], input_pkg; + union acpi_object *output; + u8 uuid[UUID_SIZE]; + + nvidia_uuid_to_aml_uuid_buf(&ffa_dev->uuid, uuid); + + args[0].type = ACPI_TYPE_BUFFER; + args[0].buffer.length = sizeof(uuid); + args[0].buffer.pointer = uuid; + + args[1].type = ACPI_TYPE_INTEGER; + args[1].integer.value = notify_id; + + input_pkg.type = ACPI_TYPE_PACKAGE; + input_pkg.package.count = 2; + input_pkg.package.elements = args; + + output = acpi_evaluate_dsm(adev->handle, &nvidia_notify_dsm_guid, + 1, 1, &input_pkg); + if (!output) + dev_err(&ffa_pdev->dev, "Failed to execute notify\n"); + else + ACPI_FREE(output); +} + +/* + * Create notification setup for the notification_id. + * + * The details regarding notification setup is documented in + * https://github.com/OpenDevicePartnership/documentation/tree/main/bookshelf/Shelf%204%20Specifications#register-notification + * + * This function setup 1:1 mapping between hardware notification ID and + * virtual notification ID. + */ +static int nvidia_ffa_notification_setup(struct nvidia_ec_ffa_device *ec_ffa_dev, + u8 notification_id) +{ + struct ffa_send_direct_data2 ffa_data = { 0 }; + u8 *uuid = (u8 *)&ec_ffa_dev->ffa_dev->uuid; + int ret; + + /* X4 register, function 1 */ + ffa_data.data[0] = 1; + + BUILD_BUG_ON(UUID_SIZE != 16); + BUILD_BUG_ON(sizeof(ffa_data.data[1]) < 8); + + /* X5 and X6 registers contain UUID */ + memcpy(&ffa_data.data[1], uuid, 8); + memcpy(&ffa_data.data[2], uuid + 8, 8); + + /* X7 register, the number of notification mappings */ + ffa_data.data[3] = 1; + + /* X7 register, notification ID and notification bitmap bit number */ + ffa_data.data[4] = ((u64)notification_id << 32) | notification_id; + + if (!notify_ffa_dev->ops || + !notify_ffa_dev->ops->msg_ops || + !notify_ffa_dev->ops->msg_ops->sync_send_receive2) { + return -EINVAL; + } + + ret = notify_ffa_dev->ops->msg_ops->sync_send_receive2(notify_ffa_dev, + &ffa_data); + if (ret) { + dev_err(&ec_ffa_dev->ffa_dev->dev, + "Failed to send NOTIFY_SETUP id=%d error=%d\n", + notification_id, ret); + return ret; + } + + if (ffa_data.data[0]) { + dev_err(&ec_ffa_dev->ffa_dev->dev, + "NOTIFY_SETUP returned failure id=%d error=%ld\n", + notification_id, ffa_data.data[0]); + + /* + * TODO: destroy operation is not yet implemented in the firmware + * So, if driver is reloaded, then the previous notification + * still exists and failure will be returned. Once destroy + * is implemented in firmware, update code here to return error + */ + } + + return 0; +} + +/* Destroy notification setup for the notification_id */ +static void nvidia_ffa_notification_destroy(struct nvidia_ec_ffa_device *ec_ffa_dev, + u8 notification_id) +{ + /* + * TODO: destroy operation is not yet implemented in the firmware. + * Once implemented in firmware, update code here. + */ +} + +/* + * Create notifications for the FFA device. + * + * 1. Get notification map array for FFA device. + * 2. For each notification, setup notification with notify service and + * then invoke notify_request method to enable notification for FFA device. + */ +static int nvidia_ffa_create_notifications(struct nvidia_ec_ffa_device *ec_ffa_dev) +{ + int i, ret = 0; + + if (!ec_ffa_dev->ffa_dev->ops || + !ec_ffa_dev->ffa_dev->ops->notifier_ops || + !ec_ffa_dev->ffa_dev->ops->notifier_ops->notify_request || + !ec_ffa_dev->ffa_dev->ops->notifier_ops->notify_relinquish) { + return -EOPNOTSUPP; + } + + ret = nvidia_ffa_fill_notification_map(ec_ffa_dev); + if (ret) { + dev_err(&ffa_pdev->dev, "Error in filling notification map error=%d\n", ret); + return ret; + } + + for (i = 0; i < ec_ffa_dev->notification_count; i++) { + ret = nvidia_ffa_notification_setup(ec_ffa_dev, + ec_ffa_dev->notification_id[i]); + if (ret) { + dev_err(&ec_ffa_dev->ffa_dev->dev, + "Failed to setup notification id=%d error=%d\n", + ec_ffa_dev->notification_id[i], ret); + break; + } + + ret = ec_ffa_dev->ffa_dev->ops->notifier_ops->notify_request( + ec_ffa_dev->ffa_dev, false, + nvidia_ffa_ec_service_notif_callback, + ec_ffa_dev->ffa_dev, ec_ffa_dev->notification_id[i]); + if (ret) { + nvidia_ffa_notification_destroy(ec_ffa_dev, + ec_ffa_dev->notification_id[i]); + dev_err(&ec_ffa_dev->ffa_dev->dev, + "Failed to request notification id=%d error=%d\n", + ec_ffa_dev->notification_id[i], ret); + break; + } + } + + /* Remove already setup notification in case of error */ + if (ret) { + int j; + + for (j = 0; j < i; j++) { + ec_ffa_dev->ffa_dev->ops->notifier_ops->notify_relinquish( + ec_ffa_dev->ffa_dev, + ec_ffa_dev->notification_id[j]); + nvidia_ffa_notification_destroy(ec_ffa_dev, + ec_ffa_dev->notification_id[j]); + } + + ec_ffa_dev->notification_count = 0; + } + + return ret; +} + +/* Remove notifications for the FFA device. */ +static void nvidia_ffa_remove_notifications(struct nvidia_ec_ffa_device *ec_ffa_dev) +{ + int i; + + for (i = 0; i < ec_ffa_dev->notification_count; i++) { + ec_ffa_dev->ffa_dev->ops->notifier_ops->notify_relinquish( + ec_ffa_dev->ffa_dev, + ec_ffa_dev->notification_id[i]); + nvidia_ffa_notification_destroy(ec_ffa_dev, + ec_ffa_dev->notification_id[i]); + } +} + +/* + * Handler function for FFH operation region offset 4. + * When ACPI interpreter runs code with FFH operation region offset 4, + * then this data is meant for EC secure services. The FFH buffer has + * data in 'struct nvidia_ec_ffa_packet' format. In this packet, it has UUID + * for EC secure service and then the service specific raw data. + * + * 1. Extract the UUID from this packet and get ffa_device for it. + * 2. Fill raw data in 'struct ffa_send_direct_data2' and + * invoke sync_send_receive2() routine for the ffa_device. + * 3. From response, fill the data in 'struct ffa_send_direct_data2' + * and return. + */ +static int nvidia_ffh_handler(struct acpi_ffh_info *info, acpi_integer *value, void *region_context) +{ + struct ffa_send_direct_data2 ffa_data = { 0 }; + struct nvidia_ec_ffa_packet *ffa_packet = (struct nvidia_ec_ffa_packet *)value; + struct nvidia_ec_ffa_device *cur, *ec_dev = NULL; + int ret; + unsigned int ffh_copy_len; + uuid_t uuid; + + /* Only offset 4 is supported */ + if (info->offset != 4) + return -EOPNOTSUPP; + + /* Length should not be less than header length */ + if (info->length < offsetof(struct nvidia_ec_ffa_packet, rawdata)) + return -EINVAL; + + /* Length should not be less than actual packet length */ + if (info->length < + ffa_packet->length + offsetof(struct nvidia_ec_ffa_packet, rawdata)) { + ffa_packet->status = 1; + return -EINVAL; + } + + /* Packet length should not greater than FFA supported data length */ + if (ffa_packet->length > sizeof(ffa_data.data)) { + ffa_packet->status = 1; + return -EINVAL; + } + + /* Convert AML UUID to FFA UUID */ + uuid = nvidia_get_uuid_from_aml_buf((u8 *)ffa_packet->uuid); + + mutex_lock(&nvidia_ffa_lock); + /* Get nvidia_ec_ffa_device for the current UUID */ + list_for_each_entry(cur, &nvidia_ec_ffa_dev_head, list) { + if (uuid_equal(&uuid, &cur->ffa_dev->uuid)) { + ec_dev = cur; + break; + } + } + mutex_unlock(&nvidia_ffa_lock); + + if (!ec_dev) { + ffa_packet->status = 1; + return -EINVAL; + } + + /* Copy the ACPI FFH packet data into FFA data */ + memcpy(ffa_data.data, ffa_packet->rawdata, ffa_packet->length); + + if (!ec_dev->ffa_dev->ops || + !ec_dev->ffa_dev->ops->msg_ops || + !ec_dev->ffa_dev->ops->msg_ops->sync_send_receive2) { + return -EINVAL; + } + + ret = ec_dev->ffa_dev->ops->msg_ops->sync_send_receive2(ec_dev->ffa_dev, + &ffa_data); + if (ret) { + dev_err(&ec_dev->ffa_dev->dev, + "Failed to send FFA messages error=%d\n", ret); + ffa_packet->status = 1; + return ret; + } + + /* Set the status as success */ + ffa_packet->status = 0; + + /* + * Copy the ACPI FFA data back into ACPI FFH packet. + * + * ACPI FFH packet raw data length can't be fetched here, so copy + * all bytes from ffa_data.data + */ + ffh_copy_len = min(sizeof(ffa_data.data), + info->length - offsetof(struct nvidia_ec_ffa_packet, rawdata)); + + memcpy(ffa_packet->rawdata, ffa_data.data, ffh_copy_len); + return 0; +} + +static int nvidia_ffa_ec_service_probe(struct ffa_device *ffa_dev) +{ + struct nvidia_ec_ffa_device *nvidia_ec_ffa_dev; + const char *acpi_id = NULL; + int ret; + + if (!ffa_pdev || !notify_ffa_dev) { + dev_err(&ffa_dev->dev, "nvidia ffa or notify device not available\n"); + return -ENODEV; + } + + nvidia_ec_ffa_dev = devm_kzalloc(&ffa_dev->dev, + sizeof(*nvidia_ec_ffa_dev), + GFP_KERNEL); + if (!nvidia_ec_ffa_dev) { + dev_err(&ffa_dev->dev, "Failed to allocate memory\n"); + return -ENOMEM; + } + + nvidia_ec_ffa_dev->ffa_dev = ffa_dev; + INIT_LIST_HEAD(&nvidia_ec_ffa_dev->list); + + ret = nvidia_ffa_create_notifications(nvidia_ec_ffa_dev); + if (ret) { + dev_info(&ffa_dev->dev, + "Failed to create ffa notifications error=%d\n", + ret); + devm_kfree(&ffa_dev->dev, nvidia_ec_ffa_dev); + return ret; + } + + mutex_lock(&nvidia_ffa_lock); + list_add(&nvidia_ec_ffa_dev->list, &nvidia_ec_ffa_dev_head); + mutex_unlock(&nvidia_ffa_lock); + + /* + * When acpi subsystem probe all ACPI devices, then it execute _STA + * method for each device. The _STA method fails at that time since + * custom FFA driver won't be ready. Get ACPI ID from UUID and + * rescan the device again. + */ + acpi_id = nvidia_get_acpi_id_from_uuid(&ffa_dev->uuid); + if (acpi_id) { + acpi_bus_for_each_dev(nvidia_ffa_rescan_acpi_device, + (void *)acpi_id); + } + + return 0; +} + +static void nvidia_ffa_ec_service_remove(struct ffa_device *ffa_dev) +{ + struct nvidia_ec_ffa_device *cur, *tmp; + + mutex_lock(&nvidia_ffa_lock); + list_for_each_entry_safe(cur, tmp, &nvidia_ec_ffa_dev_head, list) { + if (cur->ffa_dev == ffa_dev) { + list_del(&cur->list); + nvidia_ffa_remove_notifications(cur); + devm_kfree(&ffa_dev->dev, cur); + break; + } + } + mutex_unlock(&nvidia_ffa_lock); +} + +static const struct ffa_device_id nvidia_ffa_ec_service_ids[] = { + { nvidia_ec_managment_service_uuid }, + { nvidia_ec_power_service_uuid }, + { nvidia_ec_battery_service_uuid }, + { nvidia_ec_thermal_service_uuid }, + { nvidia_ec_fan_service_uuid }, + { nvidia_ec_ucsi_service_uuid }, + { nvidia_ec_input_service_uuid }, + { nvidia_ec_time_alarm_service_uuid }, + {} +}; + +static struct ffa_driver nvidia_ffa_ec_service_driver = { + .name = DRV_NAME, + .probe = nvidia_ffa_ec_service_probe, + .remove = nvidia_ffa_ec_service_remove, + .id_table = nvidia_ffa_ec_service_ids, +}; + +static int nvidia_ffa_notify_service_probe(struct ffa_device *ffa_dev) +{ + int ret; + + if (!ffa_pdev) { + dev_err(&ffa_dev->dev, "nvidia ffa device not available\n"); + return -ENODEV; + } + + notify_ffa_dev = ffa_dev; + + ret = ffa_driver_register(&nvidia_ffa_ec_service_driver, THIS_MODULE, DRV_NAME); + if (ret) { + dev_err(&ffa_dev->dev, + "Failed to register ec service driver error=%d\n", ret); + notify_ffa_dev = NULL; + return ret; + } + + return 0; +} + +static void nvidia_ffa_notify_service_remove(struct ffa_device *ffa_dev) +{ + ffa_driver_unregister(&nvidia_ffa_ec_service_driver); + notify_ffa_dev = NULL; +} + +static const struct ffa_device_id nvidia_ffa_notify_service_ids[] = { + { nvidia_ec_notify_service_uuid }, + {} +}; + +static struct ffa_driver nvidia_ffa_notify_service_driver = { + .name = "nvidia-ffa-notify", + .probe = nvidia_ffa_notify_service_probe, + .remove = nvidia_ffa_notify_service_remove, + .id_table = nvidia_ffa_notify_service_ids, +}; + +static const struct acpi_device_id nvidia_ffa_device_ids[] = { + /* + * Please refer + * https://github.com/OpenDevicePartnership/documentation/blob/main/bookshelf/Shelf%204%20Specifications/EC%20Interface/src/secure-ec-services-overview.md#hid-definition + * where MSFT000C is documented. + * + * The _HID 'MSFT000C' is reserved for FFA device which uses + * FFA interface for secure EC communication. + */ + {"MSFT000C", 0}, + {"", 0}, +}; + +MODULE_DEVICE_TABLE(acpi, nvidia_ffa_device_ids); + +static int nvidia_ffa_probe(struct platform_device *pdev) +{ + struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); + acpi_status status; + unsigned long long data = 0; + int ret; + + if (ffa_pdev) { + dev_err(&pdev->dev, "FFA device already registered\n"); + return -EINVAL; + } + + if (!adev) { + dev_err(&pdev->dev, "No ACPI companion found\n"); + return -ENODEV; + } + + status = acpi_evaluate_integer(adev->handle, "AVAL", NULL, &data); + if (ACPI_FAILURE(status)) { + dev_err(&pdev->dev, "Failed to execute AVAL method\n"); + return -ENODEV; + } + + if (data != 1) { + dev_err(&pdev->dev, "FFA not available\n"); + return -ENODEV; + } + + ret = acpi_arm64_ffh_update_custom_offset_handler(nvidia_ffh_handler); + if (ret) { + dev_err(&pdev->dev, + "Failed to register custom offset handler error=%d\n", ret); + return ret; + } + + ffa_pdev = pdev; + + ret = ffa_driver_register(&nvidia_ffa_notify_service_driver, THIS_MODULE, DRV_NAME); + if (ret) { + dev_err(&pdev->dev, + "Failed to register notify service driver error=%d\n", ret); + acpi_arm64_ffh_update_custom_offset_handler(NULL); + ffa_pdev = NULL; + return ret; + } + + return 0; +} + +static void nvidia_ffa_remove(struct platform_device *pdev) +{ + ffa_driver_unregister(&nvidia_ffa_notify_service_driver); + ffa_pdev = NULL; + acpi_arm64_ffh_update_custom_offset_handler(NULL); +} + +static struct platform_driver nvidia_ffa_driver = { + .probe = nvidia_ffa_probe, + .remove = nvidia_ffa_remove, + .driver = { + .name = "nvidia-ffa", + .acpi_match_table = nvidia_ffa_device_ids, + }, +}; + +static int __init nvidia_ffa_init(void) +{ + return platform_driver_register(&nvidia_ffa_driver); +} +module_init(nvidia_ffa_init); + +static void __exit nvidia_ffa_exit(void) +{ + platform_driver_unregister(&nvidia_ffa_driver); +} +module_exit(nvidia_ffa_exit); + +MODULE_SOFTDEP("pre: arm-ffa"); +MODULE_AUTHOR("NVIDIA CORPORATION"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("NVIDIA FFA EC services driver"); --- linux-nvidia-7.0.0.orig/drivers/platform/arm64/nvidia/Kconfig +++ linux-nvidia-7.0.0/drivers/platform/arm64/nvidia/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# NVIDIA ARM64 Platform-Specific Device Drivers +# + +config MTK_PCIE_HOTPLUG + tristate "CX7 PCIe Hotplug Driver" + depends on EINT_MTK + depends on PCI && ACPI + help + Say Y here to support PCIe device plug in/out detection. + It will disable PCIe link when plug out and enable + PCIe link after plug in. + + This is particularly useful for GB10 SoC. + + If unsure, say N. --- linux-nvidia-7.0.0.orig/drivers/platform/arm64/nvidia/Makefile +++ linux-nvidia-7.0.0/drivers/platform/arm64/nvidia/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for NVIDIA ARM64 platform-specific drivers +# +# CX7 PCIe Hotplug Driver +# Provides hotplug support for CX7 PCIe devices on GB10 SoC-based systems +# + +obj-$(CONFIG_MTK_PCIE_HOTPLUG) += mtk-pcie-hotplug.o --- linux-nvidia-7.0.0.orig/drivers/platform/arm64/nvidia/mtk-pcie-hotplug.c +++ linux-nvidia-7.0.0/drivers/platform/arm64/nvidia/mtk-pcie-hotplug.c @@ -0,0 +1,2324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2025 MediaTek Inc. + * Copyright (c) 2025-2026 NVIDIA Corporation + * + * CX7 PCIe Hotplug Driver + * + * Manages PCIe device hotplug using GPIO interrupts and ACPI resources. + * Supports cable insertion/removal detection and device power management. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HP_PORT_MAX 3 +#define HP_POLL_CNT_MAX 200 +#define MAX_VENDOR_DATA_LEN 16 +#define CX7_HP_MMIO_REGION_COUNT 5 /* TOP, PROTECT, CKM, MAC Port 0, MAC Port 1 */ +#define CX7_HP_MIN_GPIO_COUNT 4 /* Minimum required: BOOT, PRSNT, PERST, EN */ +#define PINCTRL_MAPPING_ENTRY_SIZE 5 /* dev_name, state, ctrl_dev, group, function */ +/* Indices for pinctrl mapping entry strings */ +#define PINCTRL_IDX_DEV_NAME 0 +#define PINCTRL_IDX_STATE 1 +#define PINCTRL_IDX_CTRL_DEV 2 +#define PINCTRL_IDX_GROUP 3 +#define PINCTRL_IDX_FUNCTION 4 + +/* Hardware timing requirements (in microseconds unless noted) */ +#define CX7_HP_DELAY_SHORT_US 10 /* Short delay for register writes */ +#define CX7_HP_DELAY_STANDARD_US 10000 /* Standard delay (10ms) */ +#define CX7_HP_DELAY_BUS_PROTECT_US 5000 /* Bus protection setup delay */ +#define CX7_HP_DELAY_PHY_RESET_US 3000 /* PHY reset delay */ +#define CX7_HP_DELAY_LINK_STABLE_MS 100 /* Link stabilization delay (ms) */ +#define CX7_HP_POLL_SLEEP_US 10000 /* Polling loop sleep interval */ + +#define PLUG_IN_EVT "HOTPLUG_STATE=plugin" +#define REMOVAL_EVT "HOTPLUG_STATE=removal" + +/* Bus protection stages to prevent PCIe core reset glitches */ +#define BUS_PROTECT_INIT 0 +#define BUS_PROTECT_CABLE_REMOVAL 1 +#define BUS_PROTECT_CABLE_PLUGIN 2 +#define BUS_PROTECT_CLEANUP 3 + +enum cx7_hp_state { + STATE_READY = 0, + STATE_PLUG_OUT, /* Cable plug-out */ + STATE_DEV_POWER_OFF, /* Device is powered off */ + STATE_PLUG_IN, /* Cable plug-in detected */ + STATE_DEV_POWER_ON, /* Device is powered on */ + STATE_DEV_FW_START, /* Device firmware is running */ + STATE_RESCAN, /* Device ready, can perform bus rescan */ + STATE_UNKNOWN +}; + +enum pcie_pin_index { + PCIE_PIN_BOOT = 0, /* Device boot status pin */ + PCIE_PIN_PRSNT, /* Presence detection pin */ + PCIE_PIN_PERST, /* PCIe reset pin */ + PCIE_PIN_EN, /* Power enable pin */ + PCIE_PIN_CLQ0, /* Clock request pin 0 */ + PCIE_PIN_CLQ1, /* Clock request pin 1 */ + PCIE_PIN_MAX +}; + +struct pcie_port_info { + int domain; + int bus; + int devfn; +}; + +struct rp_bus_mmio_top { + u32 ctrl; + u32 port_bits[HP_PORT_MAX]; + u32 update_bit; +}; + +struct rp_bus_mmio_protect { + u32 mode; + u32 enable; + u32 port_bits[HP_PORT_MAX]; +}; + +struct rp_bus_mmio_mac { + u32 init_ctrl; + u32 ltssm_bit; + u32 phy_rst_bit; +}; + +struct rp_bus_mmio_ckm { + u32 ctrl; + u32 disable_bit; +}; + +struct rp_bus_mmio_info { + struct rp_bus_mmio_top top; + struct rp_bus_mmio_protect protect; + struct rp_bus_mmio_mac mac; + struct rp_bus_mmio_ckm ckm; +}; + +struct gpio_acpi_context { + struct device *dev; + unsigned int debounce_timeout_us; + int pin; + int wake_capable; + int triggering; + int polarity; + unsigned long irq_flags; + int valid; + unsigned int connection_type; + char vendor_data[MAX_VENDOR_DATA_LEN + 1]; +}; + +struct cx7_hp_dev; + +/** + * struct cx7_hp_plat_data - Platform configuration data parsed from ACPI + * + * Platform-specific configuration parsed from ACPI devices: + * - RES0 device (PNP0C02): PCIe configuration and MMIO register offsets via _DSD + * - PEDE device (MTKP0001): Pinctrl mappings via _DSD + */ +struct cx7_hp_plat_data { + int port_nums; + struct pcie_port_info ports[HP_PORT_MAX]; + u32 vendor_id; + u32 device_id; + int num_devices; + struct rp_bus_mmio_info rp_bus_mmio; + u32 ltssm_reg; + u32 ltssm_l0_state; + int pin_nums; + struct pinctrl_map *parsed_pinmap; +}; + +struct cx7_hp_gpio_ctx { + struct gpio_desc *desc; + struct gpio_acpi_context *ctx; + struct cx7_hp_dev *hp_dev; +}; + +struct acpi_gpio_parse_context { + struct gpio_acpi_context *ctx; + struct cx7_hp_dev *hp_dev; +}; + +struct acpi_gpio_walk_context { + struct device *dev; + struct gpio_info { + unsigned int pin; + unsigned int connection_type; + unsigned int triggering; + unsigned int polarity; + unsigned int debounce_timeout; + unsigned int wake_capable; + char vendor_data[MAX_VENDOR_DATA_LEN + 1]; + char resource_source[16]; + unsigned int resource_source_index; + } gpios[PCIE_PIN_MAX]; + int count; +}; + +struct cx7_hp_acpi_mmio { + struct acpi_resource_fixed_memory32 + mmio_regions[CX7_HP_MMIO_REGION_COUNT]; + int count; + struct device *dev; +}; + +enum cx7_hp_debug_val { + CX7_HP_DEBUG_PLUG_OUT = 0, + CX7_HP_DEBUG_PLUG_IN, + CX7_HP_DEBUG_MAX_VAL +}; + +struct cx7_hp_mmio_runtime { + void __iomem *top_base; + void __iomem *protect_base; + void __iomem *ckm_base; + void __iomem *mac_port_base[HP_PORT_MAX]; +}; + +/** + * cx7_hp_dev - Hotplug device structure + * + * ACPI resource sources: + * - MMIO addresses: RES0 device (PNP0C02) _CRS, stored in mmio field + * - GPIO resources: PEDE device (MTKP0001) _CRS, stored in pins field + */ +struct cx7_hp_dev { + struct cx7_hp_gpio_ctx *pins; + struct cx7_hp_plat_data *pd; + struct platform_device *pdev; + enum cx7_hp_state state; + int gpio_count; + int boot_pin; + int prsnt_pin; + enum cx7_hp_debug_val debug_state; + bool hotplug_enabled; + spinlock_t lock; + struct pci_dev *cached_root_ports[HP_PORT_MAX]; + struct cx7_hp_mmio_runtime mmio; + struct gpio_device *gdev; + struct notifier_block pci_notifier; +}; + +/* ACPI _DSD device properties GUID: daffd814-6eba-4d8c-8a91-bc9bbf4aa301 */ +static const guid_t device_properties_guid = +GUID_INIT(0xdaffd814, 0x6eba, 0x4d8c, + 0x8a, 0x91, 0xbc, 0x9b, + 0xbf, 0x4a, 0xa3, 0x01); + +/** + * cx7_hp_parse_pinctrl_config_dsd - Parse pinctrl configuration from PEDE device _DSD + * @hp_dev: hotplug device + * + * Parses pin-nums and pinctrl-mappings from _DSD. + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_parse_pinctrl_config_dsd(struct cx7_hp_dev *hp_dev) +{ + struct acpi_device *adev; + struct device *dev = &hp_dev->pdev->dev; + const union acpi_object *mappings_pkg, *mapping_entry; + struct pinctrl_map *pinmap; + u32 pin_nums = 0; + int k; + const char *strings[PINCTRL_MAPPING_ENTRY_SIZE]; + + adev = ACPI_COMPANION(dev); + if (!adev) { + dev_err(dev, "Failed to get ACPI companion device\n"); + return -ENODEV; + } + + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + acpi_status status; + const union acpi_object *dsd_pkg, *props_pkg = NULL; + int i, j; + + status = acpi_evaluate_object_typed(adev->handle, "_DSD", NULL, &buffer, + ACPI_TYPE_PACKAGE); + if (ACPI_FAILURE(status)) { + dev_err(dev, "Failed to evaluate _DSD: %s\n", + acpi_format_exception(status)); + return -ENODEV; + } + + dsd_pkg = buffer.pointer; + if (!dsd_pkg || dsd_pkg->type != ACPI_TYPE_PACKAGE) { + dev_err(dev, "Invalid _DSD package\n"); + ACPI_FREE(buffer.pointer); + return -EINVAL; + } + /* Find Device Properties GUID package */ + for (i = 0; i + 1 < dsd_pkg->package.count; i += 2) { + const union acpi_object *guid = &dsd_pkg->package.elements[i]; + const union acpi_object *pkg = + &dsd_pkg->package.elements[i + 1]; + + /* Verify GUID matches Device Properties GUID */ + if (guid->type == ACPI_TYPE_BUFFER && guid->buffer.length == 16 && + pkg->type == ACPI_TYPE_PACKAGE && + guid_equal((guid_t *)guid->buffer.pointer, + &device_properties_guid)) { + props_pkg = pkg; + break; + } + } + + if (!props_pkg) { + dev_err(dev, + "Device Properties GUID package not found in _DSD\n"); + ACPI_FREE(buffer.pointer); + return -EINVAL; + } + + for (j = 0; j < props_pkg->package.count; j++) { + const union acpi_object *prop = &props_pkg->package.elements[j]; + + if (prop->type != ACPI_TYPE_PACKAGE || + prop->package.count != 2 || + prop->package.elements[0].type != ACPI_TYPE_STRING) + continue; + + const char *prop_name = + prop->package.elements[0].string.pointer; + const union acpi_object *prop_value = + &prop->package.elements[1]; + + if (!strcmp(prop_name, "pin-nums")) { + if (prop_value->type == ACPI_TYPE_INTEGER) { + pin_nums = prop_value->integer.value; + } + } else if (!strcmp(prop_name, "pinctrl-mappings")) { + if (prop_value->type == ACPI_TYPE_PACKAGE) + mappings_pkg = prop_value; + } + } + + if (pin_nums == 0) { + hp_dev->pd->pin_nums = 0; + ACPI_FREE(buffer.pointer); + return 0; + } + + if (!mappings_pkg) { + dev_err(dev, + "Missing required _DSD property: pinctrl-mappings\n"); + ACPI_FREE(buffer.pointer); + return -EINVAL; + } + + if (mappings_pkg->package.count != pin_nums) { + dev_err(dev, + "pinctrl-mappings count mismatch: expected %u, got %u\n", + pin_nums, mappings_pkg->package.count); + ACPI_FREE(buffer.pointer); + return -EINVAL; + } + + /* Allocate pinmap array */ + pinmap = devm_kcalloc(dev, pin_nums, sizeof(*pinmap), GFP_KERNEL); + if (!pinmap) { + ACPI_FREE(buffer.pointer); + return -ENOMEM; + } + + /* Parse each mapping entry */ + for (k = 0; k < pin_nums; k++) { + mapping_entry = &mappings_pkg->package.elements[k]; + if (mapping_entry->type != ACPI_TYPE_PACKAGE || + mapping_entry->package.count != ARRAY_SIZE(strings)) { + dev_err(dev, + "Invalid pinctrl mapping entry %d: expected Package(%zu), " + "got %s(count=%u)\n", + k, ARRAY_SIZE(strings), + mapping_entry->type == ACPI_TYPE_PACKAGE ? + "Package" : "non-Package", + mapping_entry->type == ACPI_TYPE_PACKAGE ? + mapping_entry->package.count : 0); + ACPI_FREE(buffer.pointer); + return -EINVAL; + } + + /* Extract strings: dev_name, state, ctrl_dev, group, function */ + for (int l = 0; l < ARRAY_SIZE(strings); l++) { + if (mapping_entry->package.elements[l].type != + ACPI_TYPE_STRING) { + dev_err(dev, + "Mapping entry %d element %d is not a string\n", + k, l); + ACPI_FREE(buffer.pointer); + return -EINVAL; + } + strings[l] = + mapping_entry->package.elements[l].string.pointer; + } + + /* Populate pinctrl_map structure */ + pinmap[k].dev_name = + devm_kstrdup(dev, strings[PINCTRL_IDX_DEV_NAME], + GFP_KERNEL); + pinmap[k].name = + devm_kstrdup(dev, strings[PINCTRL_IDX_STATE], GFP_KERNEL); + pinmap[k].type = PIN_MAP_TYPE_MUX_GROUP; + pinmap[k].ctrl_dev_name = + devm_kstrdup(dev, strings[PINCTRL_IDX_CTRL_DEV], + GFP_KERNEL); + pinmap[k].data.mux.group = + devm_kstrdup(dev, strings[PINCTRL_IDX_GROUP], GFP_KERNEL); + pinmap[k].data.mux.function = + devm_kstrdup(dev, strings[PINCTRL_IDX_FUNCTION], + GFP_KERNEL); + + if (!pinmap[k].dev_name || !pinmap[k].name || + !pinmap[k].ctrl_dev_name || !pinmap[k].data.mux.group || + !pinmap[k].data.mux.function) { + dev_err(dev, + "Failed to allocate memory for mapping %d\n", + k); + ACPI_FREE(buffer.pointer); + return -ENOMEM; + } + } + + hp_dev->pd->pin_nums = pin_nums; + hp_dev->pd->parsed_pinmap = pinmap; + ACPI_FREE(buffer.pointer); + dev_dbg(dev, "Successfully parsed %u pinctrl mappings from ACPI\n", + pin_nums); + return 0; +} + +/** + * cx7_hp_pinctrl_init - Register pinctrl mappings for the device + * @hp_dev: hotplug device + * + * Parses pinctrl mappings from _DSD and registers them. + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_pinctrl_init(struct cx7_hp_dev *hp_dev) +{ + int ret; + + ret = cx7_hp_parse_pinctrl_config_dsd(hp_dev); + if (ret) { + dev_err(&hp_dev->pdev->dev, + "Failed to parse pinctrl configuration from ACPI: %d\n", + ret); + return ret; + } + + if (!hp_dev->pd->pin_nums) + return 0; + + ret = + pinctrl_register_mappings(hp_dev->pd->parsed_pinmap, + hp_dev->pd->pin_nums); + if (ret) { + dev_err(&hp_dev->pdev->dev, + "Failed to register pinctrl mappings\n"); + return ret; + } + + dev_dbg(&hp_dev->pdev->dev, "Registered %u pinctrl mappings\n", + hp_dev->pd->pin_nums); + return 0; +} + +/** + * cx7_hp_pinctrl_remove - Unregister pinctrl mappings + * @hp_dev: hotplug device + */ +static void cx7_hp_pinctrl_remove(struct cx7_hp_dev *hp_dev) +{ + if (!hp_dev->pd->pin_nums) + return; + + pinctrl_unregister_mappings(hp_dev->pd->parsed_pinmap); +} + +/** + * cx7_hp_change_pinctrl_state - Change pinctrl state + * @hp_dev: hotplug device + * @new_state: new pinctrl state name + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_change_pinctrl_state(struct cx7_hp_dev *hp_dev, + const char *new_state) +{ + struct pinctrl *pinctrl; + struct pinctrl_state *state; + int ret; + + pinctrl = devm_pinctrl_get(&hp_dev->pdev->dev); + if (IS_ERR(pinctrl)) { + dev_err(&hp_dev->pdev->dev, "Failed to get pinctrl\n"); + return PTR_ERR(pinctrl); + } + + state = pinctrl_lookup_state(pinctrl, new_state); + if (IS_ERR(state)) { + dev_err(&hp_dev->pdev->dev, "Failed to lookup state:%s\n", + new_state); + return PTR_ERR(state); + } + + ret = pinctrl_select_state(pinctrl, state); + if (ret) { + dev_err(&hp_dev->pdev->dev, + "Failed to select pinctrl state:%s\n", new_state); + return ret; + } + + return 0; +} + +/** + * cx7_hp_send_uevent - Send uevent to userspace + * @hp_dev: hotplug device + * @msg: uevent message string + */ +static void cx7_hp_send_uevent(struct cx7_hp_dev *hp_dev, const char *msg) +{ + char *uevent = NULL; + char *envp[2]; + + uevent = kasprintf(GFP_KERNEL, msg); + if (!uevent) { + dev_err(&hp_dev->pdev->dev, + "Failed to allocate uevent string\n"); + return; + } + + envp[0] = uevent; + envp[1] = NULL; + + if (kobject_uevent_env(&hp_dev->pdev->dev.kobj, KOBJ_CHANGE, envp)) + dev_err(&hp_dev->pdev->dev, "Failed to send uevent\n"); + + kfree(uevent); +} + +/** + * cx7_hp_reg_update_bits - Update specific bits in a register + * @base: MMIO base address + * @offset: Register offset + * @mask: Bits to modify + * @set: true to set bits, false to clear bits + */ +static inline void cx7_hp_reg_update_bits(void __iomem *base, u32 offset, + u32 mask, bool set) +{ + u32 val = readl(base + offset); + + if (set) + val |= mask; + else + val &= ~mask; + + writel(val, base + offset); +} + +/** + * cx7_hp_toggle_update_bit - Toggle control register update bit + * @base: MMIO base address + * @ctrl_offset: Control register offset + * @bits: Bits to set/clear before toggling update + * @update_bit: Update bit mask + * @set: true to set bits, false to clear bits + * + * Performs the sequence: modify bits, clear update bit, set update bit + */ +static void cx7_hp_toggle_update_bit(void __iomem *base, u32 ctrl_offset, + u32 bits, u32 update_bit, bool set) +{ + cx7_hp_reg_update_bits(base, ctrl_offset, bits, set); + cx7_hp_reg_update_bits(base, ctrl_offset, update_bit, false); + cx7_hp_reg_update_bits(base, ctrl_offset, update_bit, true); +} + +/** + * cx7_hp_bus_protect_enable - Enable bus protection for a port + * @dev: hotplug device + * @port_idx: Port index + */ +static void cx7_hp_bus_protect_enable(struct cx7_hp_dev *dev, int port_idx) +{ + struct rp_bus_mmio_info *mmio_info = &dev->pd->rp_bus_mmio; + u32 port_bit = mmio_info->protect.port_bits[port_idx]; + + cx7_hp_reg_update_bits(dev->mmio.protect_base, + mmio_info->protect.mode, port_bit, true); + cx7_hp_reg_update_bits(dev->mmio.protect_base, + mmio_info->protect.enable, port_bit, true); +} + +/** + * cx7_hp_bus_protect_disable - Disable bus protection for a port + * @dev: hotplug device + * @port_idx: Port index + */ +static void cx7_hp_bus_protect_disable(struct cx7_hp_dev *dev, int port_idx) +{ + struct rp_bus_mmio_info *mmio_info = &dev->pd->rp_bus_mmio; + u32 port_bit = mmio_info->protect.port_bits[port_idx]; + + cx7_hp_reg_update_bits(dev->mmio.protect_base, + mmio_info->protect.enable, port_bit, false); + cx7_hp_reg_update_bits(dev->mmio.protect_base, + mmio_info->protect.mode, port_bit, false); +} + +/** + * cx7_hp_ckm_control - Control clock module + * @dev: hotplug device + * @disable: true to disable clock, false to enable + */ +static void cx7_hp_ckm_control(struct cx7_hp_dev *dev, bool disable) +{ + struct rp_bus_mmio_info *mmio_info = &dev->pd->rp_bus_mmio; + + if (!dev->mmio.ckm_base) + return; + + cx7_hp_reg_update_bits(dev->mmio.ckm_base, mmio_info->ckm.ctrl, + mmio_info->ckm.disable_bit, disable); +} + +/** + * cx7_hp_parse_mmio_resources - ACPI resource callback for parsing MMIO from _CRS + * @ares: ACPI resource being processed + * @data: pointer to cx7_hp_acpi_mmio structure + * + * Returns: AE_OK to continue iteration, AE_ERROR on error + */ +static acpi_status cx7_hp_parse_mmio_resources(struct acpi_resource *ares, + void *data) +{ + struct cx7_hp_acpi_mmio *parsed = data; + + switch (ares->type) { + case ACPI_RESOURCE_TYPE_FIXED_MEMORY32: + if (parsed->count >= CX7_HP_MMIO_REGION_COUNT) { + dev_warn(parsed->dev, + "More than %d MMIO regions found in platform configuration device, ignoring extras\n", + CX7_HP_MMIO_REGION_COUNT); + break; + } + parsed->mmio_regions[parsed->count] = ares->data.fixed_memory32; + parsed->count++; + break; + default: + break; + } + + return AE_OK; +} + +/** + * cx7_hp_find_pcie_config_device - Find PCIe configuration device by HID + * + * Finds the ACPI device that provides PCIe configuration via _DSD properties + * and MMIO resources via _CRS. + * + * Returns: acpi_device pointer on success (with reference), NULL on failure + */ +static struct acpi_device *cx7_hp_find_pcie_config_device(void) +{ + return acpi_dev_get_first_match_dev("PNP0C02", NULL, -1); +} + +/** + * cx7_hp_parse_pcie_config_dsd - Parse PCIe configuration from _DSD + * @pdev: platform device + * @pd: platform data to populate + * + * Parses PCIe MMIO register offsets, bit positions, port configuration, and PCIe device + * identification from PCIe configuration device _DSD. + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_parse_pcie_config_dsd(struct platform_device *pdev, + struct cx7_hp_plat_data *pd) +{ + struct acpi_device *config_adev; + struct device *dev = &pdev->dev; + u32 val, bit1; + + config_adev = cx7_hp_find_pcie_config_device(); + if (!config_adev) { + dev_err(dev, + "Platform configuration device (PNP0C02) not found - _DSD is required\n"); + return -ENODEV; + } + + if (!acpi_dev_has_props(config_adev)) { + dev_err(dev, + "Platform configuration device has no _DSD properties. Check DSDT.\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "mac-init-ctrl-offset", &val)) { + dev_err(dev, + "Missing required _DSD property: mac-init-ctrl-offset\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.mac.init_ctrl = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "mac-ltssm-bit", &val)) { + dev_err(dev, "Missing required _DSD property: mac-ltssm-bit\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.mac.ltssm_bit = BIT(val); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "mac-phy-rst-bit", &val)) { + dev_err(dev, + "Missing required _DSD property: mac-phy-rst-bit\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.mac.phy_rst_bit = BIT(val); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "top-ctrl-offset", &val)) { + dev_err(dev, + "Missing required _DSD property: top-ctrl-offset\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.top.ctrl = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "top-update-bit", &val)) { + dev_err(dev, + "Missing required _DSD property: top-update-bit\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.top.update_bit = BIT(val); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "top-port0-bit", &val)) { + dev_err(dev, "Missing required _DSD property: top-port0-bit\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.top.port_bits[0] = BIT(val); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "top-port1-bit", &val)) { + dev_err(dev, "Missing required _DSD property: top-port1-bit\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.top.port_bits[1] = BIT(val); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "protect-mode-offset", &val)) { + dev_err(dev, + "Missing required _DSD property: protect-mode-offset\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.protect.mode = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "protect-enable-offset", &val)) { + dev_err(dev, + "Missing required _DSD property: protect-enable-offset\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.protect.enable = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "protect-port0-bit", &val)) { + dev_err(dev, + "Missing required _DSD property: protect-port0-bit\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.protect.port_bits[0] = BIT(val); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "protect-port1-bit", &val)) { + dev_err(dev, + "Missing required _DSD property: protect-port1-bit\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.protect.port_bits[1] = BIT(val); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "ckm-ctrl-offset", &val)) { + dev_err(dev, + "Missing required _DSD property: ckm-ctrl-offset\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.ckm.ctrl = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "ckm-disable-bit0", &val)) { + dev_err(dev, + "Missing required _DSD property: ckm-disable-bit0\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "ckm-disable-bit1", &bit1)) { + dev_err(dev, + "Missing required _DSD property: ckm-disable-bit1\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->rp_bus_mmio.ckm.disable_bit = BIT(val) | BIT(bit1); + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "ltssm-reg-offset", &val)) { + dev_err(dev, + "Missing required _DSD property: ltssm-reg-offset\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ltssm_reg = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "ltssm-l0-state", &val)) { + dev_err(dev, + "Missing required _DSD property: ltssm-l0-state\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ltssm_l0_state = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "port-nums", &val)) { + dev_err(dev, "Missing required _DSD property: port-nums\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + if (val == 0 || val > HP_PORT_MAX) { + dev_err(dev, + "Invalid _DSD property port-nums: %u (must be 1-%d)\n", + val, HP_PORT_MAX); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->port_nums = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "port0-domain", &val)) { + dev_err(dev, "Missing required _DSD property: port0-domain\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ports[0].domain = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "port0-bus", &val)) { + dev_err(dev, "Missing required _DSD property: port0-bus\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ports[0].bus = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "port0-devfn", &val)) { + dev_err(dev, "Missing required _DSD property: port0-devfn\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ports[0].devfn = val; + + if (pd->port_nums >= 2) { + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "port1-domain", &val)) { + dev_err(dev, + "Missing required _DSD property: port1-domain\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ports[1].domain = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "port1-bus", &val)) { + dev_err(dev, + "Missing required _DSD property: port1-bus\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ports[1].bus = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "port1-devfn", &val)) { + dev_err(dev, + "Missing required _DSD property: port1-devfn\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->ports[1].devfn = val; + } + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "vendor-id", &val)) { + dev_err(dev, "Missing required _DSD property: vendor-id\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->vendor_id = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "device-id", &val)) { + dev_err(dev, "Missing required _DSD property: device-id\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->device_id = val; + + if (fwnode_property_read_u32 + (acpi_fwnode_handle(config_adev), "num-devices", &val)) { + dev_err(dev, "Missing required _DSD property: num-devices\n"); + acpi_dev_put(config_adev); + return -EINVAL; + } + pd->num_devices = val; + + dev_dbg(dev, "Successfully parsed all required _DSD properties\n"); + + acpi_dev_put(config_adev); + return 0; +} + +/** + * cx7_hp_parse_mmio_resources_from_acpi - Parse MMIO regions from _CRS + * @dev: hotplug device + * @parsed: pointer to parsed MMIO structure + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_parse_mmio_resources_from_acpi(struct cx7_hp_dev *dev, + struct cx7_hp_acpi_mmio + *parsed) +{ + struct acpi_device *config_adev; + acpi_status status; + int ret = 0; + + if (!dev || !dev->pdev) { + return -EINVAL; + } + + config_adev = cx7_hp_find_pcie_config_device(); + if (!config_adev) + return -ENODEV; + + parsed->count = 0; + memset(parsed->mmio_regions, 0, sizeof(parsed->mmio_regions)); + + status = + acpi_walk_resources(config_adev->handle, METHOD_NAME__CRS, + cx7_hp_parse_mmio_resources, parsed); + if (ACPI_FAILURE(status)) { + dev_err(&dev->pdev->dev, + "Failed to walk platform configuration resources: %s\n", + acpi_format_exception(status)); + ret = -ENODEV; + goto out; + } + + if (parsed->count < CX7_HP_MMIO_REGION_COUNT) { + dev_warn(&dev->pdev->dev, + "Expected %d MMIO regions from platform configuration device, found %d\n", + CX7_HP_MMIO_REGION_COUNT, parsed->count); + ret = -ENODEV; + goto out; + } + +out: + acpi_dev_put(config_adev); + return ret; +} + +/** + * cx7_hp_map_mmio_resources - Map all MMIO regions from ACPI _CRS + * @dev: hotplug device + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_map_mmio_resources(struct cx7_hp_dev *dev) +{ + struct platform_device *pdev = dev->pdev; + struct cx7_hp_acpi_mmio parsed = {.count = 0, .dev = &pdev->dev }; + int ret; + int i; + + ret = cx7_hp_parse_mmio_resources_from_acpi(dev, &parsed); + if (ret) { + dev_err(&pdev->dev, + "Failed to get MMIO regions from platform configuration device\n"); + return ret; + } + + dev_dbg(&pdev->dev, "Found %d MMIO regions in _CRS, mapping...\n", + parsed.count); + + int mapped_count = 0; + for (i = 0; i < parsed.count; i++) { + void __iomem *base = NULL; + u32 addr = parsed.mmio_regions[i].address; + u32 size = parsed.mmio_regions[i].address_length; + + switch (i) { + case 0: + if (dev->pd->port_nums >= 1) { + base = devm_ioremap(&pdev->dev, addr, size); + if (!base) { + dev_err(&pdev->dev, + "Failed to map MAC Port 0 region (0x%08x)\n", + addr); + return -ENOMEM; + } + dev->mmio.mac_port_base[0] = base; + mapped_count++; + } + break; + case 1: + if (dev->pd->port_nums >= 2) { + base = devm_ioremap(&pdev->dev, addr, size); + if (!base) { + dev_err(&pdev->dev, + "Failed to map MAC Port 1 region (0x%08x)\n", + addr); + return -ENOMEM; + } + dev->mmio.mac_port_base[1] = base; + mapped_count++; + } + break; + case 2: + base = devm_ioremap(&pdev->dev, addr, size); + if (!base) { + dev_err(&pdev->dev, + "Failed to map TOP region (0x%08x)\n", + addr); + return -ENOMEM; + } + dev->mmio.top_base = base; + mapped_count++; + break; + case 3: + base = devm_ioremap(&pdev->dev, addr, size); + if (!base) { + dev_err(&pdev->dev, + "Failed to map PROTECT region (0x%08x)\n", + addr); + return -ENOMEM; + } + dev->mmio.protect_base = base; + mapped_count++; + break; + case 4: + base = devm_ioremap(&pdev->dev, addr, size); + if (!base) { + dev_err(&pdev->dev, + "Failed to map CKM region (0x%08x)\n", + addr); + return -ENOMEM; + } + dev->mmio.ckm_base = base; + mapped_count++; + break; + default: + dev_warn(&pdev->dev, + "Unexpected MMIO region at 0x%08x (size 0x%x), skipping\n", + addr, size); + break; + } + } + + if (!dev->mmio.top_base || !dev->mmio.protect_base + || !dev->mmio.ckm_base || (dev->pd->port_nums >= 1 + && !dev->mmio.mac_port_base[0]) + || (dev->pd->port_nums >= 2 && !dev->mmio.mac_port_base[1])) { + dev_err(&pdev->dev, + "Required MMIO regions not mapped from ACPI _CRS (mapped %d)\n", + mapped_count); + if (!dev->mmio.top_base) + dev_err(&pdev->dev, " Missing: TOP\n"); + if (!dev->mmio.protect_base) + dev_err(&pdev->dev, " Missing: PROTECT\n"); + if (!dev->mmio.ckm_base) + dev_err(&pdev->dev, " Missing: CKM\n"); + if (dev->pd->port_nums >= 1 && !dev->mmio.mac_port_base[0]) + dev_err(&pdev->dev, + " Missing: MAC Port 0 (port_nums=%d)\n", + dev->pd->port_nums); + if (dev->pd->port_nums >= 2 && !dev->mmio.mac_port_base[1]) + dev_err(&pdev->dev, + " Missing: MAC Port 1 (port_nums=%d)\n", + dev->pd->port_nums); + dev->mmio.top_base = NULL; + dev->mmio.protect_base = NULL; + dev->mmio.ckm_base = NULL; + for (i = 0; i < HP_PORT_MAX; i++) + dev->mmio.mac_port_base[i] = NULL; + return -ENODEV; + } + + dev_dbg(&pdev->dev, + "Successfully mapped all MMIO regions from ACPI _CRS\n"); + return 0; +} + +/** + * cx7_hp_rp_bus_protect - Bus protection handler + * @dev: hotplug device + * @port_idx: port index (0-based) + * @stage: protection stage (BUS_PROTECT_INIT, BUS_PROTECT_CLEANUP, etc.) + */ +static void cx7_hp_rp_bus_protect(struct cx7_hp_dev *dev, int port_idx, + int stage) +{ + switch (stage) { + case BUS_PROTECT_INIT: + { + int ret; + + ret = cx7_hp_map_mmio_resources(dev); + if (ret) { + dev_err(&dev->pdev->dev, + "Failed to map MMIO resources during bus init: %d\n", + ret); + return; + } + } + return; + + case BUS_PROTECT_CLEANUP: + { + int i; + + for (i = 0; i < HP_PORT_MAX; i++) { + if (dev->mmio.mac_port_base[i]) + dev->mmio.mac_port_base[i] = NULL; + } + if (dev->mmio.top_base) + dev->mmio.top_base = NULL; + if (dev->mmio.protect_base) + dev->mmio.protect_base = NULL; + if (dev->mmio.ckm_base) + dev->mmio.ckm_base = NULL; + } + return; + + case BUS_PROTECT_CABLE_REMOVAL: + case BUS_PROTECT_CABLE_PLUGIN: + { + struct rp_bus_mmio_info *mmio_info = + &dev->pd->rp_bus_mmio; + void __iomem *mac_base; + + if (port_idx >= dev->pd->port_nums) + return; + + mac_base = dev->mmio.mac_port_base[port_idx]; + if (!mac_base) + return; + + if (stage == BUS_PROTECT_CABLE_REMOVAL) { + cx7_hp_reg_update_bits(mac_base, + mmio_info->mac.init_ctrl, + mmio_info->mac.ltssm_bit, + false); + cx7_hp_reg_update_bits(mac_base, + mmio_info->mac.init_ctrl, + mmio_info->mac. + phy_rst_bit, false); + return; + } + + cx7_hp_toggle_update_bit(dev->mmio.top_base, + mmio_info->top.ctrl, + mmio_info->top. + port_bits[port_idx], + mmio_info->top.update_bit, + false); + udelay(CX7_HP_DELAY_SHORT_US); + + cx7_hp_bus_protect_enable(dev, port_idx); + usleep_range(CX7_HP_DELAY_BUS_PROTECT_US, + CX7_HP_DELAY_BUS_PROTECT_US + 1000); + + cx7_hp_reg_update_bits(mac_base, + mmio_info->mac.init_ctrl, + mmio_info->mac.phy_rst_bit, + true); + cx7_hp_reg_update_bits(mac_base, + mmio_info->mac.init_ctrl, + mmio_info->mac.ltssm_bit, true); + usleep_range(CX7_HP_DELAY_PHY_RESET_US, + CX7_HP_DELAY_PHY_RESET_US + 1000); + + cx7_hp_bus_protect_disable(dev, port_idx); + + cx7_hp_toggle_update_bit(dev->mmio.top_base, + mmio_info->top.ctrl, + mmio_info->top. + port_bits[port_idx], + mmio_info->top.update_bit, + true); + } + break; + + default: + dev_warn(&dev->pdev->dev, "Unknown bus protect stage: %d\n", + stage); + break; + } +} + +/** + * retrain_pcie_link - Retrain PCIe link + * @dev: PCI device + */ +static void retrain_pcie_link(struct pci_dev *dev) +{ + u16 link_control, lnksta; + int pos, i = 0; + + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pos) { + dev_err(&dev->dev, "PCIe capability not found\n"); + return; + } + + pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &link_control); + link_control |= PCI_EXP_LNKCTL_RL; + + pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, link_control); + + while (i < HP_POLL_CNT_MAX) { + i++; + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + if (lnksta & PCI_EXP_LNKSTA_DLLLA) + break; + usleep_range(CX7_HP_POLL_SLEEP_US, CX7_HP_POLL_SLEEP_US + 1000); + } + + pcie_capability_write_word(dev, PCI_EXP_LNKSTA, PCI_EXP_LNKSTA_LBMS); +} + +/** + * get_port_root_port - Get PCI root port device for a port + * @hp_dev: hotplug device + * @port_idx: port index + * + * Returns cached or newly found root port, or NULL if not found. + */ +static struct pci_dev *get_port_root_port(struct cx7_hp_dev *hp_dev, + int port_idx) +{ + struct pcie_port_info *port; + + if (!hp_dev->pd || port_idx >= hp_dev->pd->port_nums) + return NULL; + + port = &hp_dev->pd->ports[port_idx]; + + if (!hp_dev->cached_root_ports[port_idx]) { + hp_dev->cached_root_ports[port_idx] = + pci_get_domain_bus_and_slot(port->domain, + port->bus, port->devfn); + if (!hp_dev->cached_root_ports[port_idx]) { + dev_warn(&hp_dev->pdev->dev, + "Root port not found for domain %d bus %d\n", + port->domain, port->bus); + return NULL; + } + } + + return hp_dev->cached_root_ports[port_idx]; +} + +/** + * remove_device - Remove PCIe devices and power down hardware + * @dev: hotplug device + */ +static void remove_device(struct cx7_hp_dev *dev) +{ + int i; + + dev_info(&dev->pdev->dev, "Cable removal\n"); + + for (i = 0; i < dev->pd->port_nums; i++) + cx7_hp_rp_bus_protect(dev, i, BUS_PROTECT_CABLE_REMOVAL); + + gpiod_set_value(dev->pins[PCIE_PIN_PERST].desc, 0); + cx7_hp_change_pinctrl_state(dev, "default"); + cx7_hp_ckm_control(dev, true); + gpiod_set_value(dev->pins[PCIE_PIN_EN].desc, 0); +} + +/** + * polling_link_to_l0 - Poll until all PCIe ports reach L0 state + * @dev: hotplug device + * + * Returns: 0 on success, negative error code on failure + */ +static int polling_link_to_l0(struct cx7_hp_dev *dev) +{ + struct pci_dev *pci_dev; + u32 ltssm_reg; + u32 l0_state; + u32 ltssm_vals[HP_PORT_MAX] = { 0 }; + int count = 0; + int i; + bool all_l0; + + ltssm_reg = dev->pd->ltssm_reg; + l0_state = dev->pd->ltssm_l0_state; + + if (!ltssm_reg || !l0_state) + return 0; /* Skip if not configured */ + + /* Poll until all ports reach L0 state */ + all_l0 = false; + while (!all_l0) { + all_l0 = true; + + for (i = 0; i < dev->pd->port_nums; i++) { + pci_dev = get_port_root_port(dev, i); + if (!pci_dev) { + all_l0 = false; + continue; + } + + pci_read_config_dword(pci_dev, ltssm_reg, + <ssm_vals[i]); + if ((ltssm_vals[i] & l0_state) != l0_state) + all_l0 = false; + } + + if (all_l0) + break; + + usleep_range(CX7_HP_POLL_SLEEP_US, CX7_HP_POLL_SLEEP_US + 1000); + count++; + + if (count > HP_POLL_CNT_MAX) { + dev_err(&dev->pdev->dev, + "Timeout waiting for link to reach L0 (reached max count)\n"); + break; + } + } + + if (count > HP_POLL_CNT_MAX) { + return -ETIMEDOUT; + } + + return 0; +} + +/** + * rescan_device - Rescan PCIe bus to discover devices + * @dev: hotplug device + * + * Returns: 0 on success, negative error code on failure + */ +static int rescan_device(struct cx7_hp_dev *dev) +{ + struct pci_dev *pci_dev; + int i, err; + + err = cx7_hp_change_pinctrl_state(dev, "clkreqn"); + if (err) + return err; + + cx7_hp_ckm_control(dev, false); + usleep_range(CX7_HP_DELAY_STANDARD_US, CX7_HP_DELAY_STANDARD_US + 1000); + + for (i = 0; i < dev->pd->port_nums; i++) { + pci_dev = get_port_root_port(dev, i); + if (!pci_dev) + continue; + + err = pm_runtime_resume_and_get(&pci_dev->dev); + if (err < 0) { + dev_err(&dev->pdev->dev, + "Runtime resume failed for %s: %d\n", + pci_name(pci_dev), err); + } + } + + gpiod_set_value(dev->pins[PCIE_PIN_PERST].desc, 1); + + for (i = 0; i < dev->pd->port_nums; i++) + cx7_hp_rp_bus_protect(dev, i, BUS_PROTECT_CABLE_PLUGIN); + + err = polling_link_to_l0(dev); + if (err) + return err; + + for (i = 0; i < dev->pd->port_nums; i++) { + pci_dev = get_port_root_port(dev, i); + if (pci_dev) + retrain_pcie_link(pci_dev); + } + + msleep(CX7_HP_DELAY_LINK_STABLE_MS); + + return 0; +} + +/** + * cx7_hp_work - Work queue handler for hotplug state machine + * @irq: interrupt number + * @dev_id: GPIO context pointer + * + * Processes hotplug state transitions based on current state. + */ +static irqreturn_t cx7_hp_work(int irq, void *dev_id) +{ + struct cx7_hp_gpio_ctx *app_ctx = dev_id; + struct cx7_hp_dev *hp_dev; + enum cx7_hp_state state; + unsigned long flags; + int ret; + + if (!app_ctx || !app_ctx->hp_dev) + return IRQ_NONE; + + hp_dev = app_ctx->hp_dev; + + spin_lock_irqsave(&hp_dev->lock, flags); + if (!hp_dev->hotplug_enabled) { + spin_unlock_irqrestore(&hp_dev->lock, flags); + return IRQ_HANDLED; + } + state = hp_dev->state; + spin_unlock_irqrestore(&hp_dev->lock, flags); + + switch (state) { + case STATE_PLUG_OUT: + remove_device(hp_dev); + break; + case STATE_PLUG_IN: + dev_info(&hp_dev->pdev->dev, "Cable plugin\n"); + gpiod_set_value(hp_dev->pins[PCIE_PIN_EN].desc, 1); + break; + case STATE_DEV_POWER_OFF: + case STATE_DEV_POWER_ON: + case STATE_DEV_FW_START: + break; + case STATE_RESCAN: + ret = rescan_device(hp_dev); + spin_lock_irqsave(&hp_dev->lock, flags); + if (ret) + dev_err(app_ctx->ctx->dev, "Rescan failed: %d\n", ret); + else + hp_dev->state = STATE_READY; + spin_unlock_irqrestore(&hp_dev->lock, flags); + break; + default: + dev_err(app_ctx->ctx->dev, "Unknown state: %d\n", state); + break; + } + + return IRQ_HANDLED; +} + +/** + * hotplug_irq_handler - GPIO interrupt handler for hotplug events + * @irq: interrupt number + * @dev_id: GPIO context pointer + * + * Handles presence detection and boot status GPIO interrupts. + */ +static irqreturn_t hotplug_irq_handler(int irq, void *dev_id) +{ + struct cx7_hp_gpio_ctx *app_ctx = dev_id; + struct cx7_hp_dev *hp_dev = app_ctx->hp_dev; + struct gpio_acpi_context *gpio_ctx = app_ctx->ctx; + unsigned long flags; + int value; + enum cx7_hp_state state; + + value = gpiod_get_value(app_ctx->desc); + + if (gpio_ctx->pin == hp_dev->prsnt_pin) { + if (value) { + cx7_hp_send_uevent(hp_dev, REMOVAL_EVT); + } else { + cx7_hp_send_uevent(hp_dev, PLUG_IN_EVT); + } + return IRQ_HANDLED; + } + + spin_lock_irqsave(&hp_dev->lock, flags); + if (!hp_dev->hotplug_enabled) { + spin_unlock_irqrestore(&hp_dev->lock, flags); + return IRQ_HANDLED; + } + state = hp_dev->state; + + if (gpio_ctx->pin == hp_dev->boot_pin) { + if (value && state == STATE_PLUG_IN) { + hp_dev->state = STATE_DEV_POWER_ON; + } else if (value && state == STATE_DEV_FW_START) { + hp_dev->state = STATE_RESCAN; + } else if (!value && state == STATE_DEV_POWER_ON) { + hp_dev->state = STATE_DEV_FW_START; + } else if (!value && state == STATE_PLUG_OUT) { + hp_dev->state = STATE_DEV_POWER_OFF; + } else { + spin_unlock_irqrestore(&hp_dev->lock, flags); + return IRQ_HANDLED; + } + spin_unlock_irqrestore(&hp_dev->lock, flags); + return IRQ_WAKE_THREAD; + } + + dev_err(gpio_ctx->dev, + "Unknown GPIO pin event: pin=%d irq=%d value=%d\n", + gpio_ctx->pin, irq, value); + spin_unlock_irqrestore(&hp_dev->lock, flags); + return IRQ_HANDLED; +} + +/** + * acpi_gpio_collect_handler - ACPI resource handler to collect all GPIO resources + * @ares: ACPI resource structure + * @context: Pointer to acpi_gpio_walk_context + * + * Returns: AE_OK to continue iteration + */ +static acpi_status acpi_gpio_collect_handler(struct acpi_resource *ares, + void *context) +{ + struct acpi_gpio_walk_context *walk_ctx = context; + struct acpi_resource_gpio *agpio; + int length; + + if (ares->type != ACPI_RESOURCE_TYPE_GPIO) + return AE_OK; + + if (walk_ctx->count >= PCIE_PIN_MAX) { + dev_warn(walk_ctx->dev, + "Too many GPIO resources, truncating at %d\n", + PCIE_PIN_MAX); + return AE_OK; + } + + agpio = &ares->data.gpio; + + if (!agpio->pin_table || agpio->pin_table_length == 0) { + dev_warn(walk_ctx->dev, "GPIO resource has no pin table\n"); + return AE_OK; + } + + walk_ctx->gpios[walk_ctx->count].pin = agpio->pin_table[0]; + walk_ctx->gpios[walk_ctx->count].connection_type = + agpio->connection_type; + walk_ctx->gpios[walk_ctx->count].triggering = agpio->triggering; + walk_ctx->gpios[walk_ctx->count].polarity = agpio->polarity; + walk_ctx->gpios[walk_ctx->count].debounce_timeout = + agpio->debounce_timeout; + walk_ctx->gpios[walk_ctx->count].wake_capable = agpio->wake_capable; + + if (agpio->vendor_length && agpio->vendor_data) { + length = min_t(int, agpio->vendor_length, MAX_VENDOR_DATA_LEN); + memcpy(walk_ctx->gpios[walk_ctx->count].vendor_data, + agpio->vendor_data, length); + walk_ctx->gpios[walk_ctx->count].vendor_data[length] = '\0'; + } else { + walk_ctx->gpios[walk_ctx->count].vendor_data[0] = '\0'; + } + + if (agpio->resource_source.string_ptr) { + length = min_t(int, agpio->resource_source.string_length, 15); + memcpy(walk_ctx->gpios[walk_ctx->count].resource_source, + agpio->resource_source.string_ptr, length); + walk_ctx->gpios[walk_ctx->count].resource_source[length] = '\0'; + } else { + walk_ctx->gpios[walk_ctx->count].resource_source[0] = '\0'; + } + walk_ctx->gpios[walk_ctx->count].resource_source_index = + agpio->resource_source.index; + walk_ctx->count++; + return AE_OK; +} + +/** + * cx7_hp_walk_acpi_gpios - Walk ACPI _CRS to collect all GPIO resources + * @pdev: Platform device + * @walk_ctx: Context structure to fill with GPIO information + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_walk_acpi_gpios(struct platform_device *pdev, + struct acpi_gpio_walk_context *walk_ctx) +{ + struct acpi_device *adev; + acpi_status status; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) { + dev_err(&pdev->dev, "Failed to get ACPI companion device\n"); + return -ENODEV; + } + + memset(walk_ctx, 0, sizeof(*walk_ctx)); + walk_ctx->dev = &pdev->dev; + + status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS, + acpi_gpio_collect_handler, walk_ctx); + if (ACPI_FAILURE(status)) { + dev_err(&pdev->dev, "Failed to walk ACPI GPIO resources: %s\n", + acpi_format_exception(status)); + return -EIO; + } + + dev_dbg(&pdev->dev, "Found %d GPIO resources via ACPI walk\n", + walk_ctx->count); + + if (walk_ctx->count == 0) { + dev_err(&pdev->dev, "No GPIO resources found in ACPI _CRS\n"); + return -ENODEV; + } + + return 0; +} + +/** + * acpi_gpio_lookup_handler - ACPI resource handler to look up a specific GPIO pin + * @ares: ACPI resource being processed + * @context: Pointer to acpi_gpio_parse_context + * + * Returns: AE_OK to continue iteration + */ +static acpi_status acpi_gpio_lookup_handler(struct acpi_resource *ares, + void *context) +{ + struct acpi_gpio_parse_context *parse_ctx = context; + struct gpio_acpi_context *ctx = parse_ctx->ctx; + struct cx7_hp_dev *hp_dev = parse_ctx->hp_dev; + struct acpi_resource_gpio *agpio; + int length; + + if (ares->type != ACPI_RESOURCE_TYPE_GPIO) + return AE_OK; + + agpio = &ares->data.gpio; + + if (ctx->pin != agpio->pin_table[0]) + return AE_OK; + + ctx->valid = 1; + ctx->debounce_timeout_us = agpio->debounce_timeout * 10; + ctx->wake_capable = agpio->wake_capable; + ctx->triggering = agpio->triggering; + ctx->polarity = agpio->polarity; + ctx->connection_type = agpio->connection_type; + + if (agpio->vendor_length && agpio->vendor_data && hp_dev) { + length = min_t(int, agpio->vendor_length, MAX_VENDOR_DATA_LEN); + memcpy(&ctx->vendor_data[0], agpio->vendor_data, length); + ctx->vendor_data[length] = '\0'; + + if (!strncmp("BOOT", ctx->vendor_data, strlen("BOOT"))) + hp_dev->boot_pin = ctx->pin; + else if (!strncmp("PRSNT", ctx->vendor_data, strlen("PRSNT"))) + hp_dev->prsnt_pin = ctx->pin; + } + + if (agpio->triggering == ACPI_EDGE_SENSITIVE) { + if (agpio->polarity == ACPI_ACTIVE_LOW) + ctx->irq_flags = IRQF_TRIGGER_FALLING; + else if (agpio->polarity == ACPI_ACTIVE_HIGH) + ctx->irq_flags = IRQF_TRIGGER_RISING; + else + ctx->irq_flags = + (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING); + } else { + if (agpio->polarity == ACPI_ACTIVE_LOW) + ctx->irq_flags = IRQF_TRIGGER_LOW; + else + ctx->irq_flags = IRQF_TRIGGER_HIGH; + } + + return AE_OK; +} + +/** + * pci_devices_present_on_domain() - Check if PCI devices exist on a domain + * @domain: PCI domain number to check + * + * Returns: true if any PCI devices are present on the specified domain, + * false otherwise. This is used as a safety check before hardware shutdown. + */ +static bool pci_devices_present_on_domain(int domain) +{ + struct pci_bus *bus; + struct pci_dev *dev; + bool has_endpoint_devices = false; + + bus = pci_find_bus(domain, 1); + if (!bus) + return false; + + list_for_each_entry(dev, &bus->devices, bus_list) { + has_endpoint_devices = true; + break; + } + + return has_endpoint_devices; +} + +static ssize_t debug_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cx7_hp_dev *hp_dev = dev_get_drvdata(dev); + + if (!hp_dev) + return -EINVAL; + + return scnprintf(buf, PAGE_SIZE, "%d\n", hp_dev->debug_state); +} + +static ssize_t debug_state_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cx7_hp_dev *hp_dev = dev_get_drvdata(dev); + unsigned long val, flags; + int err, i; + + if (!hp_dev || !hp_dev->pd) + return -EINVAL; + + err = kstrtoul(buf, 10, &val); + if (err) + return err; + + spin_lock_irqsave(&hp_dev->lock, flags); + if (!hp_dev->hotplug_enabled) { + spin_unlock_irqrestore(&hp_dev->lock, flags); + dev_info(dev, "Hotplug is disabled.\n"); + return -EPERM; + } + spin_unlock_irqrestore(&hp_dev->lock, flags); + + switch (val) { + case CX7_HP_DEBUG_PLUG_OUT: + /* Safety check: Verify no devices on the bus before hardware shutdown. */ + for (i = 0; i < hp_dev->pd->port_nums; i++) { + if (pci_devices_present_on_domain + (hp_dev->pd->ports[i].domain)) { + dev_err(dev, + "PCI devices still present, remove them first\n"); + return -EBUSY; + } + } + + spin_lock_irqsave(&hp_dev->lock, flags); + hp_dev->state = STATE_PLUG_OUT; + hp_dev->debug_state = val; + spin_unlock_irqrestore(&hp_dev->lock, flags); + remove_device(hp_dev); + return count; + + case CX7_HP_DEBUG_PLUG_IN: + for (i = 0; i < hp_dev->pd->port_nums; i++) { + if (pci_devices_present_on_domain + (hp_dev->pd->ports[i].domain)) { + dev_err(dev, + "PCI devices already present, cannot reinitialize hardware\n"); + return -EBUSY; + } + } + + spin_lock_irqsave(&hp_dev->lock, flags); + hp_dev->state = STATE_PLUG_IN; + hp_dev->debug_state = val; + spin_unlock_irqrestore(&hp_dev->lock, flags); + dev_info(dev, "Cable plugin\n"); + gpiod_set_value(hp_dev->pins[PCIE_PIN_EN].desc, 1); + return count; + + default: + return -EINVAL; + } + + return count; +} + +DEVICE_ATTR_RW(debug_state); + +static ssize_t hotplug_enabled_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cx7_hp_dev *hp_dev = dev_get_drvdata(dev); + + if (!hp_dev) + return -EINVAL; + + return scnprintf(buf, PAGE_SIZE, "%d\n", hp_dev->hotplug_enabled ? 1 : 0); +} + +static ssize_t hotplug_enabled_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cx7_hp_dev *hp_dev = dev_get_drvdata(dev); + unsigned long val; + int err; + + if (!hp_dev) + return -EINVAL; + + err = kstrtoul(buf, 10, &val); + if (err) + return err; + + hp_dev->hotplug_enabled = (val != 0); + dev_info(dev, "Hotplug %s\n", hp_dev->hotplug_enabled ? "enabled" : "disabled"); + + return count; +} + +DEVICE_ATTR_RW(hotplug_enabled); + +static struct attribute *cx7_hp_attrs[] = { + &dev_attr_debug_state.attr, + &dev_attr_hotplug_enabled.attr, + NULL +}; + +static const struct attribute_group cx7_hp_attr_group = { + .name = "pcie_hotplug", + .attrs = cx7_hp_attrs +}; + +/** + * gpio_acpi_setup - Setup GPIO ACPI context from _CRS + * @pdev: platform device + * @desc: GPIO descriptor + * @hp_dev: hotplug device + * @gpio_index: GPIO index + * + * Returns: GPIO ACPI context on success, NULL on failure + */ +static struct gpio_acpi_context *gpio_acpi_setup(struct platform_device *pdev, + struct gpio_desc *desc, + struct cx7_hp_dev *hp_dev, + int gpio_index) +{ + struct acpi_gpio_parse_context parse_ctx; + struct gpio_acpi_context *ctx; + struct acpi_device *adev; + acpi_status status; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) { + dev_err(&pdev->dev, "Failed to get ACPI companion device\n"); + return NULL; + } + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return NULL; + + ctx->pin = + desc_to_gpio(desc) - + gpio_device_get_base(gpiod_to_gpio_device(desc)); + ctx->dev = &pdev->dev; + + parse_ctx.ctx = ctx; + parse_ctx.hp_dev = hp_dev; + + status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS, + acpi_gpio_lookup_handler, &parse_ctx); + if (ACPI_FAILURE(status)) { + devm_kfree(&pdev->dev, ctx); + return NULL; + } + + if (ctx->valid) { + if (gpio_index == PCIE_PIN_BOOT && hp_dev->boot_pin == -1) { + hp_dev->boot_pin = ctx->pin; + } else if (gpio_index == PCIE_PIN_PRSNT + && hp_dev->prsnt_pin == -1) { + hp_dev->prsnt_pin = ctx->pin; + } + return ctx; + } + + devm_kfree(&pdev->dev, ctx); + return NULL; +} + +/** + * cx7_hp_setup_irq - Setup IRQ for GPIO + * @app_ctx: GPIO context + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_setup_irq(struct cx7_hp_gpio_ctx *app_ctx) +{ + struct gpio_acpi_context *ctx = app_ctx->ctx; + int irq, ret; + + irq = gpiod_to_irq(app_ctx->desc); + if (irq < 0) { + dev_err(ctx->dev, "Failed to get IRQ for GPIO\n"); + return irq; + } + + if (ctx->wake_capable) + enable_irq_wake(irq); + + ret = devm_request_threaded_irq(ctx->dev, irq, + hotplug_irq_handler, cx7_hp_work, + ctx->irq_flags | IRQF_ONESHOT, + "pcie_hotplug", app_ctx); + if (ret) + dev_err(ctx->dev, "Failed to request IRQ %d: %d\n", irq, ret); + + return ret; +} + +/** + * cx7_hp_put_gpio_device - Release GPIO device reference + * @data: GPIO device pointer + */ +static void cx7_hp_put_gpio_device(void *data) +{ + struct gpio_device *gdev = data; + + gpio_device_put(gdev); +} + +/** + * cx7_hp_discover_pcie_devices - Discover existing PCI devices on managed ports + * @pdev: platform device + * @pd: platform data + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_discover_pcie_devices(struct platform_device *pdev, + struct cx7_hp_plat_data *pd) +{ + struct pci_dev *pci_dev = NULL; + int device_count = 0; + int i; + + if (!pd->vendor_id || !pd->device_id) + return 0; + + while ((pci_dev = pci_get_device(pd->vendor_id, + pd->device_id, pci_dev)) != NULL) { + if (!pci_dev->state_saved) { + pci_dev_put(pci_dev); + return -EPROBE_DEFER; + } + + for (i = 0; i < pd->port_nums; i++) { + if (pci_domain_nr(pci_dev->bus) == pd->ports[i].domain) + break; + } + + if (i == pd->port_nums) { + dev_err(&pdev->dev, + "Device %s found on unexpected domain %d\n", + pci_name(pci_dev), pci_domain_nr(pci_dev->bus)); + pci_dev_put(pci_dev); + return -ENODEV; + } + + device_count++; + } + + if (pd->num_devices && device_count != pd->num_devices) { + dev_err(&pdev->dev, + "Required number of devices not found. Expected=%d Actual=%d\n", + pd->num_devices, device_count); + return -ENODEV; + } + + return 0; +} + +/** + * cx7_hp_init_pcie_data - Initialize PCIe data from _DSD and discover devices + * @pdev: platform device + * @pd: platform data to populate + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_init_pcie_data(struct platform_device *pdev, + struct cx7_hp_plat_data *pd) +{ + int ret; + + ret = cx7_hp_parse_pcie_config_dsd(pdev, pd); + if (ret) { + dev_err(&pdev->dev, + "Failed to parse PCIe configuration _DSD properties: %d\n", + ret); + return ret; + } + + if (pd->port_nums == 0 || pd->port_nums >= HP_PORT_MAX) { + dev_err(&pdev->dev, + "Invalid port count from _DSD: %d (must be 1-%d)\n", + pd->port_nums, HP_PORT_MAX - 1); + return -EINVAL; + } + + ret = cx7_hp_discover_pcie_devices(pdev, pd); + if (ret) { + dev_dbg(&pdev->dev, "Device discovery failed: %d\n", ret); + return ret; + } + + return 0; +} + +/** + * cx7_hp_enumerate_gpios - Enumerate GPIOs from ACPI + * @pdev: Platform device + * @hp_dev: Hotplug device structure + * + * Returns: Number of GPIOs found, or negative error code + */ +static int cx7_hp_enumerate_gpios(struct platform_device *pdev, + struct cx7_hp_dev *hp_dev) +{ + struct acpi_gpio_walk_context walk_ctx; + struct fwnode_handle *gpio_fwnode = NULL; + struct acpi_device *gpio_adev = NULL; + acpi_handle gpio_handle; + acpi_status status; + int ret, i; + + ret = cx7_hp_walk_acpi_gpios(pdev, &walk_ctx); + if (ret) { + dev_err(&pdev->dev, "Failed to walk ACPI GPIO resources: %d\n", + ret); + return ret; + } + + if (walk_ctx.count < CX7_HP_MIN_GPIO_COUNT) { + dev_err(&pdev->dev, + "Insufficient GPIOs from ACPI: required at least %d, got %d\n", + CX7_HP_MIN_GPIO_COUNT, walk_ctx.count); + return -ENODEV; + } + + /* Find GPIO device using resource_source from first GPIO */ + if (walk_ctx.count == 0 || walk_ctx.gpios[0].resource_source[0] == '\0') { + dev_err(&pdev->dev, + "No resource_source in ACPI GPIO resources\n"); + return -ENODEV; + } + + status = + acpi_get_handle(NULL, walk_ctx.gpios[0].resource_source, + &gpio_handle); + if (ACPI_FAILURE(status)) { + dev_err(&pdev->dev, + "Failed to get ACPI handle for GPIO controller %s\n", + walk_ctx.gpios[0].resource_source); + return -ENODEV; + } + + gpio_adev = acpi_fetch_acpi_dev(gpio_handle); + if (!gpio_adev) { + dev_err(&pdev->dev, + "Failed to get ACPI device for GPIO controller %s\n", + walk_ctx.gpios[0].resource_source); + return -ENODEV; + } + + gpio_fwnode = acpi_fwnode_handle(gpio_adev); + hp_dev->gdev = gpio_device_find_by_fwnode(gpio_fwnode); + if (!hp_dev->gdev) { + return dev_err_probe(&pdev->dev, -EPROBE_DEFER, + "GPIO controller not available\n"); + } + + /* Successfully found GPIO device - manage reference */ + ret = devm_add_action_or_reset(&pdev->dev, cx7_hp_put_gpio_device, + hp_dev->gdev); + if (ret) { + gpio_device_put(hp_dev->gdev); + hp_dev->gdev = NULL; + dev_err(&pdev->dev, "Failed to register GPIO device cleanup\n"); + return ret; + } + + hp_dev->gpio_count = walk_ctx.count; + + hp_dev->pins = devm_kzalloc(&pdev->dev, + sizeof(struct cx7_hp_gpio_ctx) * + hp_dev->gpio_count, GFP_KERNEL); + if (!hp_dev->pins) { + dev_err(&pdev->dev, "Failed to allocate memory for GPIOs\n"); + return -ENOMEM; + } + + for (i = 0; i < hp_dev->gpio_count; i++) { + struct cx7_hp_gpio_ctx *app_ctx = &hp_dev->pins[i]; + + app_ctx->desc = + gpio_device_get_desc(hp_dev->gdev, walk_ctx.gpios[i].pin); + if (IS_ERR(app_ctx->desc)) { + dev_err(&pdev->dev, + "Failed to get GPIO descriptor for ACPI pin %u (index %d): %ld\n", + walk_ctx.gpios[i].pin, i, + PTR_ERR(app_ctx->desc)); + return PTR_ERR(app_ctx->desc); + } + + app_ctx->hp_dev = hp_dev; + } + + return hp_dev->gpio_count; +} + +/** + * cx7_hp_pci_notifier - PCI bus notifier to configure MPS for CX7 devices + * @nb: notifier block + * @action: bus notification action + * @data: pointer to device being added/removed + * + * Returns: NOTIFY_OK on success, NOTIFY_DONE if not a CX7 device + */ +static int cx7_hp_pci_notifier(struct notifier_block *nb, unsigned long action, + void *data) +{ + struct device *dev = data; + struct pci_dev *pdev = to_pci_dev(dev); + struct cx7_hp_dev *hp_dev; + unsigned long flags; + + if (action != BUS_NOTIFY_ADD_DEVICE) + return NOTIFY_DONE; + + hp_dev = container_of(nb, struct cx7_hp_dev, pci_notifier); + if (!hp_dev || !hp_dev->pd) + return NOTIFY_DONE; + + spin_lock_irqsave(&hp_dev->lock, flags); + if (!hp_dev->hotplug_enabled) { + spin_unlock_irqrestore(&hp_dev->lock, flags); + return NOTIFY_DONE; + } + spin_unlock_irqrestore(&hp_dev->lock, flags); + + if (!pdev || !hp_dev->pd->vendor_id || !hp_dev->pd->device_id) + return NOTIFY_DONE; + + if (pdev->vendor != hp_dev->pd->vendor_id || + pdev->device != hp_dev->pd->device_id) + return NOTIFY_DONE; + + if (pdev->bus) + pcie_bus_configure_settings(pdev->bus); + + return NOTIFY_OK; +} + +/** + * cx7_hp_probe - Platform device probe function + * @pdev: platform device + * + * Initializes the PCIe hotplug driver, parses ACPI resources, and sets up + * GPIO interrupts and sysfs interface. + * + * Returns: 0 on success, negative error code on failure + */ +static int cx7_hp_probe(struct platform_device *pdev) +{ + struct cx7_hp_plat_data *pd; + struct cx7_hp_gpio_ctx *app_ctx; + struct cx7_hp_dev *hp_dev; + int ret, i; + + pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); + if (!pd) { + dev_err(&pdev->dev, + "Failed to allocate memory for platform data\n"); + return -ENOMEM; + } + + ret = cx7_hp_init_pcie_data(pdev, pd); + if (ret) + return ret; + + hp_dev = devm_kzalloc(&pdev->dev, sizeof(*hp_dev), GFP_KERNEL); + if (!hp_dev) { + dev_err(&pdev->dev, + "Failed to allocate memory for hotplug device\n"); + return -ENOMEM; + } + + hp_dev->pdev = pdev; + hp_dev->pd = pd; + hp_dev->state = STATE_READY; + hp_dev->boot_pin = -1; + hp_dev->prsnt_pin = -1; + hp_dev->hotplug_enabled = false; + spin_lock_init(&hp_dev->lock); + + for (i = 0; i < HP_PORT_MAX; i++) + hp_dev->cached_root_ports[i] = NULL; + + ret = cx7_hp_enumerate_gpios(pdev, hp_dev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to enumerate GPIOs from ACPI: %d\n", + ret); + return ret; + } + + for (i = 0; i < hp_dev->gpio_count; i++) { + app_ctx = &hp_dev->pins[i]; + + app_ctx->ctx = gpio_acpi_setup(pdev, app_ctx->desc, hp_dev, i); + if (!app_ctx->ctx) { + dev_err(&pdev->dev, "Failed to setup GPIO %d\n", i); + return -ENODEV; + } + + gpiod_set_debounce(app_ctx->desc, + app_ctx->ctx->debounce_timeout_us); + + if (app_ctx->ctx->connection_type == + ACPI_RESOURCE_GPIO_TYPE_INT) { + ret = cx7_hp_setup_irq(app_ctx); + if (ret) { + dev_err(&pdev->dev, + "Failed to setup IRQ for GPIO %d\n", i); + return ret; + } + } + } + + platform_set_drvdata(pdev, hp_dev); + + ret = cx7_hp_pinctrl_init(hp_dev); + if (ret) { + dev_err(&pdev->dev, "Pinmux init failed, ret: %d\n", ret); + return ret; + } + + ret = sysfs_create_group(&pdev->dev.kobj, &cx7_hp_attr_group); + if (ret) { + dev_err(&pdev->dev, "Sysfs creation failed: %d\n", ret); + goto pinctrl_remove; + } + + cx7_hp_rp_bus_protect(hp_dev, 0, BUS_PROTECT_INIT); + + hp_dev->pci_notifier.notifier_call = cx7_hp_pci_notifier; + ret = bus_register_notifier(&pci_bus_type, &hp_dev->pci_notifier); + if (ret) { + dev_err(&pdev->dev, "Failed to register PCI bus notifier: %d\n", + ret); + goto sysfs_remove; + } + + if (gpiod_get_value(hp_dev->pins[PCIE_PIN_PRSNT].desc)) { + hp_dev->debug_state = CX7_HP_DEBUG_PLUG_OUT; + cx7_hp_send_uevent(hp_dev, REMOVAL_EVT); + } else { + hp_dev->debug_state = CX7_HP_DEBUG_PLUG_IN; + cx7_hp_send_uevent(hp_dev, PLUG_IN_EVT); + } + + dev_info(&pdev->dev, "PCIe hotplug driver initialized successfully\n"); + return 0; + +sysfs_remove: + sysfs_remove_group(&pdev->dev.kobj, &cx7_hp_attr_group); +pinctrl_remove: + cx7_hp_pinctrl_remove(hp_dev); + return ret; +} + +/** + * cx7_hp_remove - Platform device remove function + * @pdev: platform device + * + * Cleans up GPIO pins, pinctrl, sysfs interface, and bus protection. + */ +static void cx7_hp_remove(struct platform_device *pdev) +{ + struct cx7_hp_dev *hp_dev = platform_get_drvdata(pdev); + int i; + + if (!hp_dev) + return; + + sysfs_remove_group(&pdev->dev.kobj, &cx7_hp_attr_group); + + bus_unregister_notifier(&pci_bus_type, &hp_dev->pci_notifier); + + cx7_hp_rp_bus_protect(hp_dev, 0, BUS_PROTECT_CLEANUP); + + cx7_hp_pinctrl_remove(hp_dev); + + for (i = 0; i < hp_dev->pd->port_nums; i++) { + if (hp_dev->cached_root_ports[i]) + pci_dev_put(hp_dev->cached_root_ports[i]); + } + + platform_set_drvdata(pdev, NULL); +} + +static const struct acpi_device_id cx7_hp_acpi_match[] = { + {"MTKP0001", 0}, + {} +}; + +MODULE_DEVICE_TABLE(acpi, cx7_hp_acpi_match); + +static struct platform_driver cx7_hp_driver = { + .probe = cx7_hp_probe, + .remove = cx7_hp_remove, + .driver = { + .name = "cx7-pcie-hotplug", + .acpi_match_table = ACPI_PTR(cx7_hp_acpi_match), + }, +}; + +module_platform_driver(cx7_hp_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CX7 PCIe Hotplug Driver for NVIDIA DGX Systems"); --- linux-nvidia-7.0.0.orig/drivers/platform/x86/intel_ips.c +++ linux-nvidia-7.0.0/drivers/platform/x86/intel_ips.c @@ -1416,6 +1416,14 @@ DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook"), }, }, + { + .callback = ips_blacklist_callback, + .ident = "G60JX", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "G60JX"), + }, + }, { } /* terminating entry */ }; --- linux-nvidia-7.0.0.orig/drivers/resctrl/Kconfig +++ linux-nvidia-7.0.0/drivers/resctrl/Kconfig @@ -1,6 +1,7 @@ menuconfig ARM64_MPAM_DRIVER bool "MPAM driver" - depends on ARM64 && ARM64_MPAM && EXPERT + depends on ARM64 && ARM64_MPAM + select ACPI_MPAM if ACPI help Memory System Resource Partitioning and Monitoring (MPAM) driver for System IP, e.g. caches and memory controllers. @@ -22,3 +23,10 @@ If unsure, say N. endif + +config ARM64_MPAM_RESCTRL_FS + bool + default y if ARM64_MPAM_DRIVER && RESCTRL_FS + select RESCTRL_RMID_DEPENDS_ON_CLOSID + select RESCTRL_ASSIGN_FIXED + select RESCTRL_IOMMU if ARM_SMMU_V3 --- linux-nvidia-7.0.0.orig/drivers/resctrl/Makefile +++ linux-nvidia-7.0.0/drivers/resctrl/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_ARM64_MPAM_DRIVER) += mpam.o -mpam-y += mpam_devices.o +mpam-y += mpam_devices.o mpam_fb.o +mpam-$(CONFIG_ARM64_MPAM_RESCTRL_FS) += mpam_resctrl.o ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) += -DDEBUG --- linux-nvidia-7.0.0.orig/drivers/resctrl/mpam_devices.c +++ linux-nvidia-7.0.0/drivers/resctrl/mpam_devices.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -20,16 +21,29 @@ #include #include #include +#include #include #include #include #include #include #include +#include + +#include #include "mpam_internal.h" +#include "mpam_fb.h" -DEFINE_STATIC_KEY_FALSE(mpam_enabled); /* This moves to arch code */ +/* Values for the T241 errata workaround */ +#define T241_CHIPS_MAX 4 +#define T241_CHIP_NSLICES 12 +#define T241_SPARE_REG0_OFF 0x1b0000 +#define T241_SPARE_REG1_OFF 0x1c0000 +#define T241_CHIP_ID(phys) FIELD_GET(GENMASK_ULL(44, 43), phys) +#define T241_SHADOW_REG_OFF(sidx, pid) (0x360048 + (sidx) * 0x10000 + (pid) * 8) +#define SMCCC_SOC_ID_T241 0x036b0241 +static void __iomem *t241_scratch_regs[T241_CHIPS_MAX]; /* * mpam_list_lock protects the SRCU lists when writing. Once the @@ -57,6 +71,8 @@ u16 mpam_partid_max; u8 mpam_pmg_max; static bool partid_max_init, partid_max_published; +static u16 mpam_cmdline_partid_max; +static bool mpam_cmdline_partid_max_overridden; static DEFINE_SPINLOCK(partid_max_lock); /* @@ -75,6 +91,16 @@ /* When mpam is disabled, the printed reason to aid debugging */ static char *mpam_disable_reason; +static struct dentry *mpam_debugfs; + +/* + * Whether has been setup. Used by cpuhp in preference to mpam_is_enabled() + * the disable call after an error interrupt makes mpam_is_enabled() false before + * the cpuhp callbacks are made. + * Reads/writes should hold mpam_cpuhp_state_lock, (or be cpuhp callbacks). + */ +static bool mpam_resctrl_enabled; + /* * An MSC is a physical container for controls and monitors, each identified by * their RIS index. These share a base-address, interrupts and some MMIO @@ -159,6 +185,16 @@ { WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); + if (msc->iface == MPAM_IFACE_SCMI) { + u32 ret; + + mpam_fb_send_read_request(&msc->mpam_fb_chan, + msc->mpam_fb_msc_id, reg, &ret); + return ret; + } + + WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz); + return readl_relaxed(msc->mapped_hwpage + reg); } @@ -172,10 +208,15 @@ static void __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val) { - WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); - writel_relaxed(val, msc->mapped_hwpage + reg); + if (msc->iface == MPAM_IFACE_SCMI) { + mpam_fb_send_write_request(&msc->mpam_fb_chan, + msc->mpam_fb_msc_id, reg, val); + } else { + WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz); + writel_relaxed(val, msc->mapped_hwpage + reg); + } } static inline void _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, u32 val) @@ -284,6 +325,9 @@ return -EBUSY; } + if (mpam_cmdline_partid_max_overridden) + mpam_partid_max = min(mpam_cmdline_partid_max, mpam_partid_max); + return 0; } EXPORT_SYMBOL(mpam_register_requestor); @@ -317,6 +361,8 @@ { lockdep_assert_held(&mpam_list_lock); + debugfs_remove_recursive(class->debugfs); + class->debugfs = NULL; list_del_rcu(&class->classes_list); add_to_garbage(class); } @@ -337,7 +383,7 @@ } static struct mpam_component * -mpam_component_alloc(struct mpam_class *class, int id) +mpam_component_alloc(struct mpam_class *class, u32 id) { struct mpam_component *comp; @@ -369,6 +415,8 @@ __destroy_component_cfg(comp); + debugfs_remove_recursive(comp->debugfs); + comp->debugfs = NULL; list_del_rcu(&comp->class_list); add_to_garbage(comp); @@ -377,7 +425,7 @@ } static struct mpam_component * -mpam_component_find(struct mpam_class *class, int id) +mpam_component_find(struct mpam_class *class, u32 id) { struct mpam_component *comp; @@ -419,6 +467,8 @@ lockdep_assert_held(&mpam_list_lock); + debugfs_remove_recursive(vmsc->debugfs); + vmsc->debugfs = NULL; list_del_rcu(&vmsc->comp_list); add_to_garbage(vmsc); @@ -441,6 +491,89 @@ return mpam_vmsc_alloc(comp, msc); } +static DEFINE_XARRAY(mpam_pcc_channels); + +struct mpam_pcc_chan { + u32 refs; + u32 subspace_id; + struct pcc_mbox_chan *channel; + struct mbox_client pcc_cl; + + struct mpam_garbage garbage; +}; + +static struct mpam_pcc_chan *__mpam_pcc_alloc(u8 subspace_id, gfp_t gfp) +{ + struct mpam_pcc_chan *chan __free(kfree) = kzalloc(sizeof(*chan), gfp); + + lockdep_assert_held(&mpam_list_lock); + + if (!chan) + return ERR_PTR(-ENOMEM); + + chan->refs = 1; + chan->subspace_id = subspace_id; + /* + * TODO is the device important - these subspace_id can be re-used, so + * there is no one device to put here ... + */ + chan->pcc_cl.rx_callback = mpam_pcc_rx_callback; + chan->pcc_cl.tx_block = false; + chan->pcc_cl.tx_tout = 1000; /* 1s */ + chan->pcc_cl.knows_txdone = false; + + chan->channel = pcc_mbox_request_channel(&chan->pcc_cl, subspace_id); + if (IS_ERR(chan->channel)) + return ERR_CAST(chan->channel); + + init_garbage(&chan->garbage); + xa_store(&mpam_pcc_channels, subspace_id, chan, gfp); + + return_ptr(chan); +} + +static struct pcc_mbox_chan *mpam_pcc_alloc(u8 subspace_id, gfp_t gfp) +{ + struct mpam_pcc_chan *chan = __mpam_pcc_alloc(subspace_id, gfp); + return IS_ERR(chan) ? ERR_CAST(chan) : chan->channel; +} + +static struct pcc_mbox_chan *mpam_pcc_get(u8 subspace_id, bool alloc, gfp_t gfp) +{ + struct mpam_pcc_chan *chan; + + lockdep_assert_held(&mpam_list_lock); + + chan = xa_load(&mpam_pcc_channels, subspace_id); + if (chan) { + chan->refs++; + return chan->channel; + } + + if (!alloc) + return ERR_PTR(-ENOENT); + + return mpam_pcc_alloc(subspace_id, gfp); +} + +static void mpam_pcc_put(u8 subspace_id) +{ + struct mpam_pcc_chan *chan; + + lockdep_assert_held(&mpam_list_lock); + + chan = xa_load(&mpam_pcc_channels, subspace_id); + if (!chan) + return; + + chan->refs--; + if (!chan->refs) { + xa_erase(&mpam_pcc_channels, subspace_id); + pcc_mbox_free_channel(chan->channel); + add_to_garbage(chan); + } +} + /* * The cacheinfo structures are only populated when CPUs are online. * This helper walks the acpi tables to include offline CPUs too. @@ -501,7 +634,7 @@ static int mpam_ris_create_locked(struct mpam_msc *msc, u8 ris_idx, enum mpam_class_types type, u8 class_id, - int component_id) + u32 component_id) { int err; struct mpam_vmsc *vmsc; @@ -572,12 +705,20 @@ lockdep_assert_held(&mpam_list_lock); /* + * Once a RIS has been removed from a class, it can no longer be used + * by resctrl, even though the class has yet to be removed. + */ + mpam_resctrl_teardown_class(class); + + /* * It is assumed affinities don't overlap. If they do the class becomes * unusable immediately. */ cpumask_andnot(&class->affinity, &class->affinity, &ris->affinity); cpumask_andnot(&comp->affinity, &comp->affinity, &ris->affinity); clear_bit(ris->ris_idx, &msc->ris_idxs); + debugfs_remove_recursive(ris->debugfs); + ris->debugfs = NULL; list_del_rcu(&ris->msc_list); list_del_rcu(&ris->vmsc_list); add_to_garbage(ris); @@ -587,10 +728,13 @@ } int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, - enum mpam_class_types type, u8 class_id, int component_id) + enum mpam_class_types type, u8 class_id, u32 component_id) { int err; + if (mpam_force_unknown_msc_test(msc)) + type = MPAM_CLASS_UNKNOWN; + mutex_lock(&mpam_list_lock); err = mpam_ris_create_locked(msc, ris_idx, type, class_id, component_id); @@ -624,6 +768,80 @@ return ERR_PTR(-ENOENT); } +static void mpam_enable_quirk_nvidia_t241(struct mpam_msc *msc, + const struct mpam_quirk *quirk) +{ + s32 soc_id = arm_smccc_get_soc_id_version(); + struct resource *r; + phys_addr_t phys; + + /* + * A mapping to a device other than the MSC is needed, check + * SOC_ID is NVIDIA T241 chip (036b:0241) + */ + if (soc_id < 0 || soc_id != SMCCC_SOC_ID_T241) + return; + + r = platform_get_resource(msc->pdev, IORESOURCE_MEM, 0); + if (!r) + return; + + /* Find the internal registers base addr from the CHIP ID */ + msc->t241_id = T241_CHIP_ID(r->start); + phys = FIELD_PREP(GENMASK_ULL(45, 44), msc->t241_id) | 0x19000000ULL; + + t241_scratch_regs[msc->t241_id] = ioremap(phys, SZ_8M); + if (WARN_ON_ONCE(!t241_scratch_regs[msc->t241_id])) + return; + + mpam_set_quirk(quirk->workaround, msc); + pr_info_once("Enabled workaround for NVIDIA T241 erratum T241-MPAM-1\n"); +} + +static const struct mpam_quirk mpam_quirks[] = { + { + /* NVIDIA t241 erratum T241-MPAM-1 */ + .init = mpam_enable_quirk_nvidia_t241, + .iidr = IIDR_PROD(0x241) | IIDR_VAR(0) | IIDR_REV(0) | IIDR_IMP(0x36b), + .iidr_mask = IIDR_MATCH_ONE, + .workaround = T241_SCRUB_SHADOW_REGS, + }, + { + /* NVIDIA t241 erratum T241-MPAM-4 */ + .iidr = IIDR_PROD(0x241) | IIDR_VAR(0) | IIDR_REV(0) | IIDR_IMP(0x36b), + .iidr_mask = IIDR_MATCH_ONE, + .workaround = T241_FORCE_MBW_MIN_TO_ONE, + }, + { + /* NVIDIA t241 erratum T241-MPAM-6 */ + .iidr = IIDR_PROD(0x241) | IIDR_VAR(0) | IIDR_REV(0) | IIDR_IMP(0x36b), + .iidr_mask = IIDR_MATCH_ONE, + .workaround = T241_MBW_COUNTER_SCALE_64, + }, + { + /* ARM CMN-650 CSU erratum 3642720 */ + .iidr = IIDR_PROD(0) | IIDR_VAR(0) | IIDR_REV(0) | IIDR_IMP(0x43b), + .iidr_mask = IIDR_MATCH_ONE, + .workaround = IGNORE_CSU_NRDY, + }, + { NULL }, /* Sentinel */ +}; + +static void mpam_enable_quirks(struct mpam_msc *msc) +{ + const struct mpam_quirk *quirk; + + for (quirk = &mpam_quirks[0]; quirk->iidr_mask; quirk++) { + if (quirk->iidr != (msc->iidr & quirk->iidr_mask)) + continue; + + if (quirk->init) + quirk->init(msc, quirk); + else + mpam_set_quirk(quirk->workaround, msc); + } +} + /* * IHI009A.a has this nugget: "If a monitor does not support automatic behaviour * of NRDY, software can use this bit for any purpose" - so hardware might not @@ -639,7 +857,7 @@ bool can_set, can_clear; struct mpam_msc *msc = ris->vmsc->msc; - if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + if (WARN_ON_ONCE(!mpam_mon_sel_inner_lock(msc))) return false; mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, 0) | @@ -653,7 +871,7 @@ _mpam_write_monsel_reg(msc, mon_reg, 0); now = _mpam_read_monsel_reg(msc, mon_reg); can_clear = !(now & MSMON___NRDY); - mpam_mon_sel_unlock(msc); + mpam_mon_sel_inner_unlock(msc); return (!can_set || !can_clear); } @@ -674,32 +892,32 @@ /* Cache Capacity Partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_CCAP_PART, ris->idr)) { - u32 ccap_features = mpam_read_partsel_reg(msc, CCAP_IDR); + ris->ccap_idr = mpam_read_partsel_reg(msc, CCAP_IDR); - props->cmax_wd = FIELD_GET(MPAMF_CCAP_IDR_CMAX_WD, ccap_features); + props->cmax_wd = FIELD_GET(MPAMF_CCAP_IDR_CMAX_WD, ris->ccap_idr); if (props->cmax_wd && - FIELD_GET(MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM, ccap_features)) + FIELD_GET(MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM, ris->ccap_idr)) mpam_set_feature(mpam_feat_cmax_softlim, props); if (props->cmax_wd && - !FIELD_GET(MPAMF_CCAP_IDR_NO_CMAX, ccap_features)) + !FIELD_GET(MPAMF_CCAP_IDR_NO_CMAX, ris->ccap_idr)) mpam_set_feature(mpam_feat_cmax_cmax, props); if (props->cmax_wd && - FIELD_GET(MPAMF_CCAP_IDR_HAS_CMIN, ccap_features)) + FIELD_GET(MPAMF_CCAP_IDR_HAS_CMIN, ris->ccap_idr)) mpam_set_feature(mpam_feat_cmax_cmin, props); - props->cassoc_wd = FIELD_GET(MPAMF_CCAP_IDR_CASSOC_WD, ccap_features); + props->cassoc_wd = FIELD_GET(MPAMF_CCAP_IDR_CASSOC_WD, ris->ccap_idr); if (props->cassoc_wd && - FIELD_GET(MPAMF_CCAP_IDR_HAS_CASSOC, ccap_features)) + FIELD_GET(MPAMF_CCAP_IDR_HAS_CASSOC, ris->ccap_idr)) mpam_set_feature(mpam_feat_cmax_cassoc, props); } /* Cache Portion partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_CPOR_PART, ris->idr)) { - u32 cpor_features = mpam_read_partsel_reg(msc, CPOR_IDR); + ris->cpor_idr = mpam_read_partsel_reg(msc, CPOR_IDR); - props->cpbm_wd = FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, cpor_features); + props->cpbm_wd = FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, ris->cpor_idr); if (props->cpbm_wd) mpam_set_feature(mpam_feat_cpor_part, props); } @@ -715,6 +933,13 @@ mpam_set_feature(mpam_feat_mbw_part, props); props->bwa_wd = FIELD_GET(MPAMF_MBW_IDR_BWA_WD, mbw_features); + + /* + * The BWA_WD field can represent 0-63, but the control fields it + * describes have a maximum of 16 bits. + */ + props->bwa_wd = min(props->bwa_wd, 16); + if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MAX, mbw_features)) mpam_set_feature(mpam_feat_mbw_max, props); @@ -770,7 +995,9 @@ mpam_set_feature(mpam_feat_msmon_csu_xcl, props); /* Is NRDY hardware managed? */ + mpam_mon_sel_outer_lock(msc); hw_managed = mpam_ris_hw_probe_hw_nrdy(ris, CSU); + mpam_mon_sel_outer_unlock(msc); if (hw_managed) mpam_set_feature(mpam_feat_msmon_csu_hw_nrdy, props); } @@ -804,7 +1031,9 @@ } /* Is NRDY hardware managed? */ + mpam_mon_sel_outer_lock(msc); hw_managed = mpam_ris_hw_probe_hw_nrdy(ris, MBWU); + mpam_mon_sel_outer_unlock(msc); if (hw_managed) mpam_set_feature(mpam_feat_msmon_mbwu_hw_nrdy, props); @@ -851,8 +1080,11 @@ /* Grab an IDR value to find out how many RIS there are */ mutex_lock(&msc->part_sel_lock); idr = mpam_msc_read_idr(msc); + msc->iidr = mpam_read_partsel_reg(msc, IIDR); mutex_unlock(&msc->part_sel_lock); + mpam_enable_quirks(msc); + msc->ris_max = FIELD_GET(MPAMF_IDR_RIS_MAX, idr); /* Use these values so partid/pmg always starts with a valid value */ @@ -903,6 +1135,7 @@ enum mpam_device_features type; u64 *val; int err; + bool waited_timeout; }; static bool mpam_ris_has_mbwu_long_counter(struct mpam_msc_ris *ris) @@ -1069,7 +1302,7 @@ static void __ris_msmon_read(void *arg) { - u64 now; + u64 now, overflow_val; bool nrdy = false; bool config_mismatch; bool overflow = false; @@ -1082,7 +1315,7 @@ struct mpam_msc *msc = m->ris->vmsc->msc; u32 mon_sel, ctl_val, flt_val, cur_ctl, cur_flt; - if (!mpam_mon_sel_lock(msc)) { + if (!mpam_mon_sel_inner_lock(msc)) { m->err = -EIO; return; } @@ -1137,6 +1370,10 @@ if (mpam_has_feature(mpam_feat_msmon_csu_hw_nrdy, rprops)) nrdy = now & MSMON___NRDY; now = FIELD_GET(MSMON___VALUE, now); + + if (mpam_has_quirk(IGNORE_CSU_NRDY, msc) && m->waited_timeout) + nrdy = false; + break; case mpam_feat_msmon_mbwu_31counter: case mpam_feat_msmon_mbwu_44counter: @@ -1157,13 +1394,23 @@ now = FIELD_GET(MSMON___VALUE, now); } + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc)) + now *= 64; + if (nrdy) break; mbwu_state = &ris->mbwu_state[ctx->mon]; - if (overflow) - mbwu_state->correction += mpam_msmon_overflow_val(m->type); + if (overflow) { + overflow_val = mpam_msmon_overflow_val(m->type); + + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc) && + m->type != mpam_feat_msmon_mbwu_63counter) + overflow_val *= 64; + + mbwu_state->correction += overflow_val; + } /* * Include bandwidth consumed before the last hardware reset and @@ -1174,10 +1421,12 @@ default: m->err = -EINVAL; } - mpam_mon_sel_unlock(msc); + mpam_mon_sel_inner_unlock(msc); - if (nrdy) + if (nrdy) { + msc->nrdy_retry_count++; m->err = -EBUSY; + } if (m->err) return; @@ -1196,6 +1445,7 @@ struct mpam_msc *msc = vmsc->msc; struct mpam_msc_ris *ris; + mpam_mon_sel_outer_lock(msc); list_for_each_entry_srcu(ris, &vmsc->ris, vmsc_list, srcu_read_lock_held(&mpam_srcu)) { arg->ris = ris; @@ -1214,6 +1464,7 @@ if (err) any_err = err; } + mpam_mon_sel_outer_unlock(msc); } return any_err; @@ -1270,6 +1521,7 @@ .ctx = ctx, .type = type, .val = val, + .waited_timeout = true, }; *val = 0; @@ -1279,6 +1531,41 @@ return err; } +void mpam_msmon_reset_all_mbwu(struct mpam_component *comp) +{ + int idx, i; + struct mpam_msc *msc; + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + + if (!mpam_is_enabled()) + return; + + idx = srcu_read_lock(&mpam_srcu); + list_for_each_entry_rcu(vmsc, &comp->vmsc, comp_list) { + if (!mpam_has_feature(mpam_feat_msmon_mbwu, &vmsc->props)) + continue; + + msc = vmsc->msc; + mpam_mon_sel_outer_lock(msc); + list_for_each_entry_rcu(ris, &msc->ris, vmsc_list) { + if (!mpam_has_feature(mpam_feat_msmon_mbwu, &ris->props)) + continue; + + if (WARN_ON_ONCE(!mpam_mon_sel_inner_lock(msc))) + continue; + + for (i = 0; i < ris->props.num_mbwu_mon; i++) { + ris->mbwu_state[i].correction = 0; + ris->mbwu_state[i].reset_on_next_read = true; + } + mpam_mon_sel_inner_unlock(msc); + } + mpam_mon_sel_outer_unlock(msc); + } + srcu_read_unlock(&mpam_srcu, idx); +} + void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx) { struct mpam_msc *msc; @@ -1295,18 +1582,20 @@ continue; msc = vmsc->msc; + mpam_mon_sel_outer_lock(msc); list_for_each_entry_srcu(ris, &vmsc->ris, vmsc_list, srcu_read_lock_held(&mpam_srcu)) { if (!mpam_has_feature(mpam_feat_msmon_mbwu, &ris->props)) continue; - if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + if (WARN_ON_ONCE(!mpam_mon_sel_inner_lock(msc))) continue; ris->mbwu_state[ctx->mon].correction = 0; ris->mbwu_state[ctx->mon].reset_on_next_read = true; - mpam_mon_sel_unlock(msc); + mpam_mon_sel_inner_unlock(msc); } + mpam_mon_sel_outer_unlock(msc); } } @@ -1338,6 +1627,44 @@ __mpam_write_reg(msc, reg, bm); } +static void mpam_apply_t241_erratum(struct mpam_msc_ris *ris, u16 partid) +{ + int sidx, i, lcount = 1000; + void __iomem *regs; + u64 val0, val; + + regs = t241_scratch_regs[ris->vmsc->msc->t241_id]; + + for (i = 0; i < lcount; i++) { + /* Read the shadow register at index 0 */ + val0 = readq_relaxed(regs + T241_SHADOW_REG_OFF(0, partid)); + + /* Check if all the shadow registers have the same value */ + for (sidx = 1; sidx < T241_CHIP_NSLICES; sidx++) { + val = readq_relaxed(regs + + T241_SHADOW_REG_OFF(sidx, partid)); + if (val != val0) + break; + } + if (sidx == T241_CHIP_NSLICES) + break; + } + + if (i == lcount) + pr_warn_once("t241: inconsistent values in shadow regs"); + + /* Write a value zero to spare registers to take effect of MBW conf */ + writeq_relaxed(0, regs + T241_SPARE_REG0_OFF); + writeq_relaxed(0, regs + T241_SPARE_REG1_OFF); +} + +static void mpam_quirk_post_config_change(struct mpam_msc_ris *ris, u16 partid, + struct mpam_config *cfg) +{ + if (mpam_has_quirk(T241_SCRUB_SHADOW_REGS, ris->vmsc->msc)) + mpam_apply_t241_erratum(ris, partid); +} + /* Called via IPI. Call while holding an SRCU reference */ static void mpam_reprogram_ris_partid(struct mpam_msc_ris *ris, u16 partid, struct mpam_config *cfg) @@ -1382,7 +1709,7 @@ if (mpam_has_feature(mpam_feat_mbw_min, rprops) && mpam_has_feature(mpam_feat_mbw_min, cfg)) - mpam_write_partsel_reg(msc, MBW_MIN, 0); + mpam_write_partsel_reg(msc, MBW_MIN, cfg->mbw_min); if (mpam_has_feature(mpam_feat_mbw_max, rprops) && mpam_has_feature(mpam_feat_mbw_max, cfg)) { @@ -1396,11 +1723,25 @@ mpam_has_feature(mpam_feat_mbw_prop, cfg)) mpam_write_partsel_reg(msc, MBW_PROP, 0); - if (mpam_has_feature(mpam_feat_cmax_cmax, rprops)) - mpam_write_partsel_reg(msc, CMAX, cmax); + if (mpam_has_feature(mpam_feat_cmax_cmax, rprops)) { + if (mpam_has_feature(mpam_feat_cmax_cmax, cfg)) { + u32 cmax_val = cfg->cmax; + + if (cfg->cmax_softlim) + cmax_val |= MPAMCFG_CMAX_SOFTLIM; + mpam_write_partsel_reg(msc, CMAX, cmax_val); + } else { + mpam_write_partsel_reg(msc, CMAX, cmax); + } + } - if (mpam_has_feature(mpam_feat_cmax_cmin, rprops)) - mpam_write_partsel_reg(msc, CMIN, 0); + if (mpam_has_feature(mpam_feat_cmax_cmin, rprops)) { + if (mpam_has_feature(mpam_feat_cmax_cmin, cfg)) { + mpam_write_partsel_reg(msc, CMIN, cfg->cmin); + } else { + mpam_write_partsel_reg(msc, CMIN, 0); + } + } if (mpam_has_feature(mpam_feat_cmax_cassoc, rprops)) mpam_write_partsel_reg(msc, CASSOC, MPAMCFG_CASSOC_CASSOC); @@ -1421,6 +1762,8 @@ mpam_write_partsel_reg(msc, PRI, pri_val); } + mpam_quirk_post_config_change(ris, partid, cfg); + mutex_unlock(&msc->part_sel_lock); } @@ -1431,8 +1774,11 @@ u64 val; struct mon_read mwbu_arg; struct mpam_msc_ris *ris = _ris; + struct mpam_msc *msc = ris->vmsc->msc; struct mpam_class *class = ris->vmsc->comp->class; + mpam_mon_sel_outer_lock(msc); + for (i = 0; i < ris->props.num_mbwu_mon; i++) { if (ris->mbwu_state[i].enabled) { mwbu_arg.ris = ris; @@ -1444,10 +1790,12 @@ } } + mpam_mon_sel_outer_unlock(msc); + return 0; } -/* Call with MSC cfg_lock held */ +/* Call with MSC cfg_lock and outer mon_sel lock held */ static int mpam_save_mbwu_state(void *arg) { int i; @@ -1462,7 +1810,7 @@ mbwu_state = &ris->mbwu_state[i]; cfg = &mbwu_state->cfg; - if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + if (WARN_ON_ONCE(!mpam_mon_sel_inner_lock(msc))) return -EIO; mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) | @@ -1487,7 +1835,7 @@ cfg->partid = FIELD_GET(MSMON_CFG_x_FLT_PARTID, cur_flt); mbwu_state->correction += val; mbwu_state->enabled = FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl); - mpam_mon_sel_unlock(msc); + mpam_mon_sel_inner_unlock(msc); } return 0; @@ -1504,6 +1852,22 @@ } /* + * This is not part of mpam_init_reset_cfg() as high level callers have the + * class, and low level callers a ris. + */ +static void mpam_wa_t241_force_mbw_min_to_one(struct mpam_config *cfg, + struct mpam_props *props) +{ + u16 max_hw_value, min_hw_granule, res0_bits; + + res0_bits = 16 - props->bwa_wd; + max_hw_value = ((1 << props->bwa_wd) - 1) << res0_bits; + min_hw_granule = ~max_hw_value; + + cfg->mbw_min = min_hw_granule + 1; +} + +/* * Called via smp_call_on_cpu() to prevent migration, while still being * pre-emptible. Caller must hold mpam_srcu. */ @@ -1512,11 +1876,14 @@ u16 partid, partid_max; struct mpam_config reset_cfg; struct mpam_msc_ris *ris = arg; + struct mpam_msc *msc = ris->vmsc->msc; if (ris->in_reset_state) return 0; mpam_init_reset_cfg(&reset_cfg); + if (mpam_has_quirk(T241_FORCE_MBW_MIN_TO_ONE, msc)) + mpam_wa_t241_force_mbw_min_to_one(&reset_cfg, &ris->props); spin_lock(&partid_max_lock); partid_max = mpam_partid_max; @@ -1632,6 +1999,9 @@ mpam_reprogram_msc(msc); } + if (mpam_resctrl_enabled) + mpam_resctrl_online_cpu(cpu); + return 0; } @@ -1688,6 +2058,8 @@ struct mpam_msc_ris *ris; mutex_lock(&msc->cfg_lock); + + mpam_mon_sel_outer_lock(msc); list_for_each_entry_srcu(ris, &msc->ris, msc_list, srcu_read_lock_held(&mpam_srcu)) { mpam_touch_msc(msc, &mpam_reset_ris, ris); @@ -1701,10 +2073,15 @@ if (mpam_is_enabled()) mpam_touch_msc(msc, &mpam_save_mbwu_state, ris); } + mpam_mon_sel_outer_unlock(msc); + mutex_unlock(&msc->cfg_lock); } } + if (mpam_resctrl_enabled) + mpam_resctrl_offline_cpu(cpu); + return 0; } @@ -1801,9 +2178,20 @@ list_del_rcu(&msc->all_msc_list); platform_set_drvdata(pdev, NULL); + debugfs_remove_recursive(msc->debugfs); + msc->debugfs = NULL; + + if (msc->iface == MPAM_IFACE_PCC) + mpam_pcc_put(msc->pcc_subspace_id); + add_to_garbage(msc); } +void mpam_pcc_rx_callback(struct mbox_client *cl, void *msg) +{ + /* TODO: wake up tasks blocked on this MSC's PCC channel */ +} + static void mpam_msc_drv_remove(struct platform_device *pdev) { struct mpam_msc *msc = platform_get_drvdata(pdev); @@ -1818,9 +2206,9 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev) { int err; - u32 tmp; + char name[20]; struct mpam_msc *msc; - struct resource *msc_res; + struct of_phandle_args of_args; struct device *dev = &pdev->dev; lockdep_assert_held(&mpam_list_lock); @@ -1863,13 +2251,20 @@ if (err) return ERR_PTR(err); - if (device_property_read_u32(&pdev->dev, "pcc-channel", &tmp)) - msc->iface = MPAM_IFACE_MMIO; - else + if (!device_property_read_u32(&pdev->dev, "pcc-channel", + &msc->pcc_subspace_id)) { msc->iface = MPAM_IFACE_PCC; + } else if (!of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "mpam-fb", 1, 0, + &of_args)) { + msc->iface = MPAM_IFACE_SCMI; + } else { + msc->iface = MPAM_IFACE_MMIO; + } if (msc->iface == MPAM_IFACE_MMIO) { void __iomem *io; + struct resource *msc_res; io = devm_platform_get_and_ioremap_resource(pdev, 0, &msc_res); @@ -1879,6 +2274,22 @@ } msc->mapped_hwpage_sz = msc_res->end - msc_res->start; msc->mapped_hwpage = io; + } else if (msc->iface == MPAM_IFACE_PCC) { + msc->pcc_chan = mpam_pcc_get(msc->pcc_subspace_id, true, GFP_KERNEL); + if (IS_ERR(msc->pcc_chan)) { + pr_err("Failed to request MSC PCC channel\n"); + return (void *)msc->pcc_chan; + } + } else if (msc->iface == MPAM_IFACE_SCMI) { + err = mpam_fb_connect_channel(of_args.np, + &msc->mpam_fb_chan); + if (err < 0) + return ERR_PTR(err); + + if (of_args.args_count > 0) + msc->mpam_fb_msc_id = of_args.args[0]; + else + msc->mpam_fb_msc_id = 0; } else { return ERR_PTR(-EINVAL); } @@ -1886,6 +2297,10 @@ list_add_rcu(&msc->all_msc_list, &mpam_all_msc); platform_set_drvdata(pdev, msc); + snprintf(name, sizeof(name), "msc.%u", msc->id); + msc->debugfs = debugfs_create_dir(name, mpam_debugfs); + debugfs_create_x32("max_nrdy_usec", 0400, msc->debugfs, &msc->nrdy_usec); + return msc; } @@ -2090,6 +2505,7 @@ * nobble the class feature, as we can't configure all the resources. * e.g. The L3 cache is composed of two resources with 13 and 17 portion * bitmaps respectively. + * Quirks on an MSC will apply to all MSC in that class. */ static void __class_props_mismatch(struct mpam_class *class, struct mpam_vmsc *vmsc) @@ -2103,6 +2519,9 @@ dev_dbg(dev, "Merging features for class:0x%lx &= vmsc:0x%lx\n", (long)cprops->features, (long)vprops->features); + /* Merge quirks */ + class->quirks |= vmsc->msc->quirks; + /* Take the safe value for any common features */ __props_mismatch(cprops, vprops, false); } @@ -2383,18 +2802,21 @@ list_for_each_entry(vmsc, &comp->vmsc, comp_list) { msc = vmsc->msc; - if (mpam_mon_sel_lock(msc)) { + mpam_mon_sel_outer_lock(msc); + if (mpam_mon_sel_inner_lock(msc)) { list_for_each_entry(ris, &vmsc->ris, vmsc_list) add_to_garbage(ris->mbwu_state); - mpam_mon_sel_unlock(msc); + mpam_mon_sel_inner_unlock(msc); } + mpam_mon_sel_outer_unlock(msc); } } static void mpam_reset_component_cfg(struct mpam_component *comp) { int i; - struct mpam_props *cprops = &comp->class->props; + struct mpam_class *class = comp->class; + struct mpam_props *cprops = &class->props; mpam_assert_partid_sizes_fixed(); @@ -2409,6 +2831,9 @@ comp->cfg[i].mbw_pbm = GENMASK(cprops->mbw_pbm_bits - 1, 0); if (cprops->bwa_wd) comp->cfg[i].mbw_max = GENMASK(15, 16 - cprops->bwa_wd); + if (mpam_has_quirk(T241_FORCE_MBW_MIN_TO_ONE, class)) + mpam_wa_t241_force_mbw_min_to_one(&comp->cfg[i], + &class->props); } } @@ -2434,6 +2859,7 @@ mpam_reset_component_cfg(comp); list_for_each_entry(vmsc, &comp->vmsc, comp_list) { + int err = 0; struct mpam_msc *msc; struct mpam_msc_ris *ris; struct msmon_mbwu_state *mbwu_state; @@ -2442,6 +2868,7 @@ continue; msc = vmsc->msc; + mpam_mon_sel_outer_lock(msc); list_for_each_entry(ris, &vmsc->ris, vmsc_list) { if (!ris->props.num_mbwu_mon) continue; @@ -2450,16 +2877,21 @@ ris->props.num_mbwu_mon); if (!mbwu_state) { __destroy_component_cfg(comp); - return -ENOMEM; + err = -ENOMEM; + break; } init_garbage(&mbwu_state[0].garbage); - if (mpam_mon_sel_lock(msc)) { + if (mpam_mon_sel_inner_lock(msc)) { ris->mbwu_state = mbwu_state; - mpam_mon_sel_unlock(msc); + mpam_mon_sel_inner_unlock(msc); } } + mpam_mon_sel_outer_unlock(msc); + + if (err) + return err; } return 0; @@ -2483,6 +2915,130 @@ return 0; } +static void mpam_debugfs_setup_ris(struct mpam_msc_ris *ris) +{ + char name[40]; + struct dentry *d; + struct mpam_props *rprops = &ris->props; + + snprintf(name, sizeof(name), "ris.%u", ris->ris_idx); + d = debugfs_create_dir(name, ris->vmsc->msc->debugfs); + debugfs_create_x64("mpamf_idr", 0400, d, &ris->idr); + debugfs_create_x32("mpamf_cpor_idr", 0400, d, &ris->cpor_idr); + debugfs_create_x32("mpamf_ccap_idr", 0400, d, &ris->ccap_idr); + debugfs_create_ulong("features", 0400, d, &rprops->features[0]); + debugfs_create_x16("cpbm_wd", 0400, d, &rprops->cpbm_wd); + debugfs_create_x16("mbw_pbm_bits", 0400, d, &rprops->mbw_pbm_bits); + debugfs_create_x16("num_csu_mon", 0400, d, &rprops->num_csu_mon); + debugfs_create_x16("num_mbwu_mon", 0400, d, &rprops->num_mbwu_mon); + debugfs_create_cpumask("affinity", 0400, d, &ris->affinity); + ris->debugfs = d; +} + +static void mpam_debugfs_setup_vmsc(struct mpam_component *comp, + struct mpam_vmsc *vmsc) +{ + u8 ris_idx; + char name[40]; + char path[40]; + struct dentry *d; + struct mpam_msc_ris *ris; + int msc_id = vmsc->msc->id; + + snprintf(name, sizeof(name), "vmsc.%u", msc_id); + d = debugfs_create_dir(name, comp->debugfs); + debugfs_create_ulong("features", 0400, d, &vmsc->props.features[0]); + vmsc->debugfs = d; + + list_for_each_entry_rcu(ris, &vmsc->ris, vmsc_list) { + ris_idx = ris->ris_idx; + + snprintf(name, sizeof(name), "msc.%u_ris.%u", msc_id, + ris_idx); + snprintf(path, sizeof(path), "../../../msc.%u/ris.%u", + msc_id, ris_idx); + debugfs_create_symlink(name, d, path); + } +} + +static void mpam_debugfs_setup_comp(struct mpam_class *class, + struct mpam_component *comp) +{ + char name[40]; + struct dentry *d; + struct mpam_vmsc *vmsc; + + snprintf(name, sizeof(name), "comp.%u", comp->comp_id); + d = debugfs_create_dir(name, class->debugfs); + comp->debugfs = d; + + list_for_each_entry_rcu(vmsc, &comp->vmsc, comp_list) + mpam_debugfs_setup_vmsc(comp, vmsc); +} + +static void mpam_debugfs_setup(void) +{ + char name[40]; + struct dentry *d; + struct mpam_msc *msc; + struct mpam_class *class; + struct mpam_msc_ris *ris; + struct mpam_component *comp; + + lockdep_assert_held(&mpam_list_lock); + + list_for_each_entry(msc, &mpam_all_msc, all_msc_list) { + d = msc->debugfs; + debugfs_create_u32("fw_id", 0400, d, &msc->pdev->id); + debugfs_create_x32("iface", 0400, d, &msc->iface); + debugfs_create_x32("mpamf_iidr", 0400, d, &msc->iidr); + debugfs_create_x64("nrdy_retry_count", 0400, d, &msc->nrdy_retry_count); + list_for_each_entry(ris, &msc->ris, msc_list) + mpam_debugfs_setup_ris(ris); + } + + list_for_each_entry_rcu(class, &mpam_classes, classes_list) { + snprintf(name, sizeof(name), "class.%u", class->level); + d = debugfs_create_dir(name, mpam_debugfs); + debugfs_create_ulong("features", 0400, d, &class->props.features[0]); + debugfs_create_x32("nrdy_usec", 0400, d, &class->nrdy_usec); + debugfs_create_x16("quirks", 0400, d, &class->quirks); + debugfs_create_x8("level", 0400, d, &class->level); + debugfs_create_cpumask("affinity", 0400, d, &class->affinity); + class->debugfs = d; + + list_for_each_entry_rcu(comp, &class->components, class_list) + mpam_debugfs_setup_comp(class, comp); + } +} + +static int mpam_force_disable_show(struct seq_file *s, void *data) +{ + seq_puts(s, "Write 1 to this file to trigger an MPAM error.\n"); + return 0; +} + +static ssize_t mpam_force_disable_write(struct file *file, + const char __user *userbuf, size_t count, + loff_t *ppos) +{ + u32 user_val; + int err; + + err = kstrtou32_from_user(userbuf, count, 10, &user_val); + if (err) + return err; + + if (user_val == 1) { + mpam_disable_reason = "debugfs trigger"; + mpam_disable(NULL); + } + + return count; +} + +DEFINE_SHOW_STORE_ATTRIBUTE(mpam_force_disable); + static void mpam_enable_once(void) { int err; @@ -2516,10 +3072,21 @@ pr_err("Failed to allocate configuration arrays.\n"); break; } + + mpam_debugfs_setup(); } while (0); mutex_unlock(&mpam_list_lock); cpus_read_unlock(); + debugfs_create_file("force_disable", 0600, mpam_debugfs, NULL, + &mpam_force_disable_fops); + + if (!err) { + err = mpam_resctrl_setup(); + if (err) + pr_err("Failed to initialise resctrl: %d\n", err); + } + if (err) { mpam_disable_reason = "Failed to enable."; schedule_work(&mpam_broken_work); @@ -2527,6 +3094,7 @@ } static_branch_enable(&mpam_enabled); + mpam_resctrl_enabled = true; mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline, "mpam:online"); @@ -2535,7 +3103,7 @@ mpam_partid_max + 1, mpam_pmg_max + 1); } -static void mpam_reset_component_locked(struct mpam_component *comp) +void mpam_reset_component_locked(struct mpam_component *comp) { struct mpam_vmsc *vmsc; @@ -2559,7 +3127,7 @@ } } -static void mpam_reset_class_locked(struct mpam_class *class) +void mpam_reset_class_locked(struct mpam_class *class) { struct mpam_component *comp; @@ -2571,7 +3139,7 @@ mpam_reset_component_locked(comp); } -static void mpam_reset_class(struct mpam_class *class) +void mpam_reset_class(struct mpam_class *class) { cpus_read_lock(); mpam_reset_class_locked(class); @@ -2586,17 +3154,26 @@ void mpam_disable(struct work_struct *ignored) { int idx; + bool do_resctrl_exit; struct mpam_class *class; struct mpam_msc *msc, *tmp; + if (mpam_is_enabled()) + static_branch_disable(&mpam_enabled); + mutex_lock(&mpam_cpuhp_state_lock); if (mpam_cpuhp_state) { cpuhp_remove_state(mpam_cpuhp_state); mpam_cpuhp_state = 0; } + + /* mpam_cpu_offline() tells resctrl all the CPUs are offline. */ + do_resctrl_exit = mpam_resctrl_enabled; + mpam_resctrl_enabled = false; mutex_unlock(&mpam_cpuhp_state_lock); - static_branch_disable(&mpam_enabled); + if (do_resctrl_exit) + mpam_resctrl_exit(); mpam_unregister_irqs(); @@ -2659,26 +3236,85 @@ bool has_changes = false; maybe_update_config(cfg, mpam_feat_cpor_part, newcfg, cpbm, has_changes); + maybe_update_config(cfg, mpam_feat_cmax_cmax, newcfg, cmax, has_changes); maybe_update_config(cfg, mpam_feat_mbw_part, newcfg, mbw_pbm, has_changes); maybe_update_config(cfg, mpam_feat_mbw_max, newcfg, mbw_max, has_changes); + maybe_update_config(cfg, mpam_feat_mbw_min, newcfg, mbw_min, has_changes); return has_changes; } +static void mpam_extend_config(struct mpam_class *class, struct mpam_config *cfg) +{ + struct mpam_props *cprops = &class->props; + u16 min, min_hw_granule, delta; + u16 max_hw_value, res0_bits; + + /* + * Calculate the values the 'min' control can hold. + * e.g. on a platform with bwa_wd = 8, min_hw_granule is 0x00ff because + * those bits are RES0. Configurations of this value are effectively + * zero. But configurations need to saturate at min_hw_granule on + * systems with mismatched bwa_wd, where the 'less than 0' values are + * implemented on some MSC, but not others. + */ + res0_bits = 16 - cprops->bwa_wd; + max_hw_value = ((1 << cprops->bwa_wd) - 1) << res0_bits; + min_hw_granule = ~max_hw_value; + + /* + * MAX and MIN should be set together. If only one is provided, + * generate a configuration for the other. If only one control + * type is supported, the other value will be ignored. + * + * Resctrl can only configure the MAX. + */ + if (mpam_has_feature(mpam_feat_mbw_max, cfg) && + !mpam_has_feature(mpam_feat_mbw_min, cfg)) { + delta = ((5 * MPAMCFG_MBW_MAX_MAX) / 100) - 1; + if (cfg->mbw_max > delta) + min = cfg->mbw_max - delta; + else + min = 0; + + cfg->mbw_min = max(min, min_hw_granule); + mpam_set_feature(mpam_feat_mbw_min, cfg); + } + + if (mpam_has_quirk(T241_FORCE_MBW_MIN_TO_ONE, class) && + cfg->mbw_min <= min_hw_granule) { + cfg->mbw_min = min_hw_granule + 1; + mpam_set_feature(mpam_feat_mbw_min, cfg); + } +} + int mpam_apply_config(struct mpam_component *comp, u16 partid, - struct mpam_config *cfg) + struct mpam_config *user_cfg) { struct mpam_write_config_arg arg; struct mpam_msc_ris *ris; + struct mpam_config cfg; struct mpam_vmsc *vmsc; struct mpam_msc *msc; lockdep_assert_cpus_held(); + /* Don't pass in the current config! */ - WARN_ON_ONCE(&comp->cfg[partid] == cfg); + WARN_ON_ONCE(&comp->cfg[partid] == user_cfg); + + /* + * Copy the config to avoid writing back the 'extended' version to + * the caller. + * This avoids mpam_devices.c setting a mbm_min that mpam_resctrl.c + * is unaware of ... when it then changes mbm_max to be lower than + * mbm_min. + */ + cfg = *user_cfg; + + mpam_extend_config(comp->class, &cfg); - if (!mpam_update_config(&comp->cfg[partid], cfg)) + if (!mpam_update_config(&comp->cfg[partid], &cfg)) return 0; arg.comp = comp; @@ -2714,12 +3350,105 @@ return -EINVAL; } + mpam_debugfs = debugfs_create_dir("mpam", NULL); + return platform_driver_register(&mpam_msc_driver); } /* Must occur after arm64_mpam_register_cpus() from arch_initcall() */ subsys_initcall(mpam_msc_driver_init); +static int mpam_cmdline_partid_max_set(const char *arg, + const struct kernel_param *kp) +{ + int ret; + + spin_lock(&partid_max_lock); + ret = kstrtou16(arg, 10, &mpam_cmdline_partid_max); + if (!ret) + mpam_cmdline_partid_max_overridden = true; + spin_unlock(&partid_max_lock); + + return 0; +} +static int mpam_cmdline_partid_max_get(char *buffer, + const struct kernel_param *kp) +{ + u16 val = 0xffff; + + spin_lock(&partid_max_lock); + if (mpam_cmdline_partid_max_overridden) + val = mpam_cmdline_partid_max; + spin_unlock(&partid_max_lock); + + return sprintf(buffer, "%u\n", val); +} +static const struct kernel_param_ops mpam_cmdline_partid_max_ops = { + .set = mpam_cmdline_partid_max_set, + .get = mpam_cmdline_partid_max_get, +}; +module_param_cb(partid_max, &mpam_cmdline_partid_max_ops, NULL, 0644); +MODULE_PARM_DESC(partid_max, "Override for reducing the number of PARTID."); + +static DEFINE_XARRAY(mpam_force_unkown_msc); + +static void mpam_force_unknown_msc_add(u32 msc_id, gfp_t gfp) +{ + xa_store(&mpam_force_unkown_msc, msc_id, xa_mk_value(msc_id), gfp); +} + +bool mpam_force_unknown_msc_test(struct mpam_msc *msc) +{ + return !!xa_load(&mpam_force_unkown_msc, msc->pdev->id); +} + +static int mpam_force_unknown_msc_set(const char *_str, + const struct kernel_param *kp) +{ + int err; + u32 val; + char *tok, *iter; + char *str __free(kfree) = kstrdup(_str, GFP_KERNEL); + + iter = str; + do { + tok = strsep(&iter, ","); + err = kstrtou32(tok, 10, &val); + if (err) { + pr_err("Failed to parse commandline: %d\n", err); + break; + } + mpam_force_unknown_msc_add(val, GFP_KERNEL); + } while (iter); + + return 0; +} +static int mpam_force_unknown_msc_get(char *buffer, + const struct kernel_param *kp) +{ + unsigned long index, count = 0; + int result = 0; + void *entry; + + xa_for_each(&mpam_force_unkown_msc, index, entry) { + if (count) + result += sprintf(buffer + result, ","); + + result += sprintf(buffer + result, "%lu", index); + count += 1; + } + + result += sprintf(buffer + result, "\n"); + + return result; +} +static const struct kernel_param_ops mpam_force_unknown_msc_ops = { + .set = mpam_force_unknown_msc_set, + .get = mpam_force_unknown_msc_get, +}; +subsys_param_cb(force_unknown_msc, &mpam_force_unknown_msc_ops, NULL, 0644); +MODULE_PARM_DESC(force_unknown_msc, "Disabling a set of probed MSC."); + #ifdef CONFIG_MPAM_KUNIT_TEST #include "test_mpam_devices.c" #endif --- linux-nvidia-7.0.0.orig/drivers/resctrl/mpam_fb.c +++ linux-nvidia-7.0.0/drivers/resctrl/mpam_fb.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2024 Arm Ltd. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "mpam_fb.h" + +#define MPAM_MSC_ATTRIBUTES 0x3 +#define MPAM_MSC_READ 0x4 +#define MPAM_MSC_WRITE 0x5 + +static const struct scmi_mpam_proto_ops *mpam_scmi_ops; + +static DEFINE_MUTEX(scmi_agent_list_mutex); +static LIST_HEAD(smci_agent_list); + +struct scmi_mpam_agent { + struct list_head list; + struct device_node *of_node; + struct scmi_protocol_handle *ph_handle; +}; + +#define SCMI_BUF_LENGTH_IDX 4 +#define SCMI_BUF_HEADER_IDX 5 +#define SCMI_BUF_PAYLOAD_IDX 6 +#define SCMI_READ_MSG_SIZE 9 +#define SCMI_WRITE_MSG_SIZE 10 + +static int mpam_fb_build_read_message(int msc_id, int reg, u32 *msg_buf) +{ + memset(msg_buf, 0, SCMI_READ_MSG_SIZE * sizeof(u32)); + + msg_buf[SCMI_BUF_LENGTH_IDX] = SCMI_READ_MSG_SIZE * sizeof(u32); + msg_buf[SCMI_BUF_HEADER_IDX] = MPAM_MSC_READ | (0x1a << 10); + msg_buf[SCMI_BUF_PAYLOAD_IDX + 0] = msc_id; + msg_buf[SCMI_BUF_PAYLOAD_IDX + 2] = reg; + + return SCMI_READ_MSG_SIZE * sizeof(u32); +} + +static int mpam_fb_build_write_message(int msc_id, int reg, u32 val, + u32 *msg_buf) +{ + memset(msg_buf, 0, SCMI_WRITE_MSG_SIZE * sizeof(u32)); + + msg_buf[SCMI_BUF_LENGTH_IDX] = SCMI_WRITE_MSG_SIZE * sizeof(u32); + msg_buf[SCMI_BUF_HEADER_IDX] = MPAM_MSC_WRITE | (0x1a << 10); + msg_buf[SCMI_BUF_PAYLOAD_IDX + 0] = msc_id; + msg_buf[SCMI_BUF_PAYLOAD_IDX + 2] = reg; + msg_buf[SCMI_BUF_PAYLOAD_IDX + 3] = val; + + return SCMI_WRITE_MSG_SIZE * sizeof(u32); +} + +static struct scmi_protocol_handle *scmi_agent_get_ph(const struct device_node *np) +{ + struct scmi_mpam_agent *agent; + struct scmi_protocol_handle *ph = NULL; + + mutex_lock(&scmi_agent_list_mutex); + + list_for_each_entry(agent, &smci_agent_list, list) { + if (np == agent->of_node) { + ph = agent->ph_handle; + break; + } + } + + mutex_unlock(&scmi_agent_list_mutex); + + return ph; +} + +int mpam_fb_connect_channel(const struct device_node *of_node, + struct mpam_fb_channel *chan) +{ + int msc_id = 0; + + chan->ph_handle = scmi_agent_get_ph(of_node); + if (!chan->ph_handle) + return -EPROBE_DEFER; + + chan->use_scmi = true; + + return msc_id; +} + +int mpam_fb_send_read_request(struct mpam_fb_channel *chan, int msc_id, + u16 reg, u32 *result) +{ + u32 msg_buf[12]; + int msg_len; + + msg_len = mpam_fb_build_read_message(msc_id, reg, msg_buf); + + if (chan->use_scmi) { + /* The SCMI layer adds the shared memory header itself. */ + msg_len -= SCMI_BUF_PAYLOAD_IDX * sizeof(u32); + + mpam_scmi_ops->mpam_transfer_buf(chan->ph_handle, + MPAM_MSC_READ, + msg_buf + SCMI_BUF_PAYLOAD_IDX, + msg_len, result); + + return 0; + } + + if (msg_len < chan->pcc_shmem_size) + return -EINVAL; + + memcpy(chan->pcc_shmem, msg_buf, msg_len); + mbox_send_message(chan->pcc_mbox, NULL); + + return 0; +} + +int mpam_fb_send_write_request(struct mpam_fb_channel *chan, int msc_id, + u16 reg, u32 value) +{ + u32 msg_buf[12]; + int msg_len; + + msg_len = mpam_fb_build_write_message(msc_id, reg, value, msg_buf); + if (msg_len < 0) + return msg_len; + + if (chan->use_scmi) { + /* The SCMI layer adds the shared memory header itself. */ + msg_len -= SCMI_BUF_PAYLOAD_IDX * sizeof(u32); + + mpam_scmi_ops->mpam_transfer_buf(chan->ph_handle, + MPAM_MSC_WRITE, + msg_buf + SCMI_BUF_PAYLOAD_IDX, + msg_len, NULL); + + return 0; + } + + if (msg_len < chan->pcc_shmem_size) + return -EINVAL; + + memcpy(chan->pcc_shmem, msg_buf, msg_len); + mbox_send_message(chan->pcc_mbox, NULL); + + return 0; +} + +static int scmi_mpam_probe(struct scmi_device *sdev) +{ + const struct scmi_handle *handle = sdev->handle; + struct scmi_protocol_handle *ph; + struct scmi_mpam_agent *agent; + + if (!handle) + return -ENODEV; + + mpam_scmi_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_MPAM, &ph); + if (IS_ERR(mpam_scmi_ops)) + return PTR_ERR(mpam_scmi_ops); + + agent = devm_kzalloc(&sdev->dev, sizeof(*agent), GFP_KERNEL); + if (!agent) + return -ENOMEM; + + agent->of_node = sdev->dev.of_node; + agent->ph_handle = ph; + + mutex_lock(&scmi_agent_list_mutex); + list_add(&agent->list, &smci_agent_list); + mutex_unlock(&scmi_agent_list_mutex); + + return 0; +} + +static void scmi_mpam_remove(struct scmi_device *sdev) +{ +} + +static const struct scmi_device_id scmi_id_table[] = { + { SCMI_PROTOCOL_MPAM, "mpam" }, + {}, +}; +MODULE_DEVICE_TABLE(scmi, scmi_id_table); + +static struct scmi_driver scmi_mpam_driver = { + .name = "scmi-mpam-driver", + .probe = scmi_mpam_probe, + .remove = scmi_mpam_remove, + .id_table = scmi_id_table, +}; +module_scmi_driver(scmi_mpam_driver); --- linux-nvidia-7.0.0.orig/drivers/resctrl/mpam_fb.h +++ linux-nvidia-7.0.0/drivers/resctrl/mpam_fb.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (C) 2024 Arm Ltd. + +#ifndef MPAM_FB_H_ +#define MPAM_FB_H_ + +#include +#include +#include + +struct mpam_fb_channel { + bool use_scmi; + struct scmi_protocol_handle *ph_handle; + void __iomem *pcc_shmem; + size_t pcc_shmem_size; + struct mbox_chan *pcc_mbox; +}; + +int mpam_fb_connect_channel(const struct device_node *of_node, + struct mpam_fb_channel *chan); +int mpam_fb_send_read_request(struct mpam_fb_channel *chan, int msc_id, + u16 reg, u32 *result); +int mpam_fb_send_write_request(struct mpam_fb_channel *chan, int msc_id, + u16 reg, u32 value); + +#endif --- linux-nvidia-7.0.0.orig/drivers/resctrl/mpam_internal.h +++ linux-nvidia-7.0.0/drivers/resctrl/mpam_internal.h @@ -8,14 +8,21 @@ #include #include #include +#include #include #include #include +#include #include +#include #include #include #include +#include + +#include "mpam_fb.h" + #define MPAM_MSC_MAX_NUM_RIS 16 struct platform_device; @@ -28,6 +35,20 @@ #define PACKED_FOR_KUNIT #endif +/* + * This 'mon' values must not alias an actual monitor, so must be larger than + * U16_MAX, but not be confused with an errno value, so smaller than + * (u32)-SZ_4K. + * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor. + */ +#define USE_PRE_ALLOCATED (U16_MAX + 1) + +/* + * Only these event configuration bits are supported. MPAM can't know if + * data is being written back, these will show up as a write. + */ +#define MPAM_RESTRL_EVT_CONFIG_VALID (READS_TO_LOCAL_MEM | NON_TEMP_WRITE_TO_LOCAL_MEM) + static inline bool mpam_is_enabled(void) { return static_branch_likely(&mpam_enabled); @@ -57,7 +78,12 @@ /* Not modified after mpam_is_enabled() becomes true */ enum mpam_msc_iface iface; + u32 pcc_subspace_id; + struct pcc_mbox_chan *pcc_chan; + struct mpam_fb_channel mpam_fb_chan; + int mpam_fb_msc_id; /* in its own name space */ u32 nrdy_usec; + u64 nrdy_retry_count; cpumask_t accessibility; bool has_extd_esr; @@ -76,6 +102,8 @@ u8 pmg_max; unsigned long ris_idxs; u32 ris_max; + u32 iidr; + u16 quirks; /* * error_irq_lock is taken when registering/unregistering the error @@ -105,47 +133,82 @@ /* * mon_sel_lock protects access to the MSC hardware registers that are * affected by MPAMCFG_MON_SEL, and the mbwu_state. - * Access to mon_sel is needed from both process and interrupt contexts, - * but is complicated by firmware-backed platforms that can't make any - * access unless they can sleep. - * Always use the mpam_mon_sel_lock() helpers. - * Accesses to mon_sel need to be able to fail if they occur in the wrong - * context. + * Both the 'inner' and 'outer' must be taken. + * For real MMIO MSC, the outer lock is unnecessary - but keeps the + * code common with: + * Firmware backed MSC need to sleep when accessing the MSC, which + * means some code-paths will always fail. For these MSC the outer + * lock is providing the protection, and the inner lock fails to + * be taken if the task is unable to sleep. + * * If needed, take msc->probe_lock first. */ - raw_spinlock_t _mon_sel_lock; - unsigned long _mon_sel_flags; + struct mutex outer_mon_sel_lock; + bool outer_lock_held; + raw_spinlock_t inner_mon_sel_lock; + unsigned long inner_mon_sel_flags; void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; + struct dentry *debugfs; + + /* Values only used on some platforms for quirks */ + u32 t241_id; + struct mpam_garbage garbage; }; -/* Returning false here means accesses to mon_sel must fail and report an error. */ -static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) +static inline bool __must_check mpam_mon_sel_inner_lock(struct mpam_msc *msc) { - /* Locking will require updating to support a firmware backed interface */ - if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) - return false; + /* + * The outer lock may be taken by a CPU that then issues an IPI to run + * a helper that takes the inner lock. lockdep can't help us here. + */ + WARN_ON_ONCE(!READ_ONCE(msc->outer_lock_held)); - raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); - return true; + if (msc->iface == MPAM_IFACE_MMIO) { + raw_spin_lock_irqsave(&msc->inner_mon_sel_lock, msc->inner_mon_sel_flags); + return true; + } + + /* Accesses must fail if we are not pre-emptible */ + return !!preemptible(); } -static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) +static inline void mpam_mon_sel_inner_unlock(struct mpam_msc *msc) { - raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); + WARN_ON_ONCE(!READ_ONCE(msc->outer_lock_held)); + + if (msc->iface == MPAM_IFACE_MMIO) + raw_spin_unlock_irqrestore(&msc->inner_mon_sel_lock, msc->inner_mon_sel_flags); +} + +static inline void mpam_mon_sel_outer_lock(struct mpam_msc *msc) +{ + mutex_lock(&msc->outer_mon_sel_lock); + msc->outer_lock_held = true; +} + +static inline void mpam_mon_sel_outer_unlock(struct mpam_msc *msc) +{ + msc->outer_lock_held = false; + mutex_unlock(&msc->outer_mon_sel_lock); } static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) { - lockdep_assert_held_once(&msc->_mon_sel_lock); + WARN_ON_ONCE(!READ_ONCE(msc->outer_lock_held)); + if (msc->iface == MPAM_IFACE_MMIO) + lockdep_assert_held_once(&msc->inner_mon_sel_lock); + else + lockdep_assert_preemption_enabled(); } static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) { - raw_spin_lock_init(&msc->_mon_sel_lock); + raw_spin_lock_init(&msc->inner_mon_sel_lock); + mutex_init(&msc->outer_mon_sel_lock); } /* Bits for mpam features bitmaps */ @@ -197,7 +260,7 @@ * removed, and will false-positive if the compiler introduces padding that * isn't cleared during sanitisation. */ -} PACKED_FOR_KUNIT; +} PACKED_FOR_KUNIT __aligned(__alignof__(unsigned long)); #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) /* @@ -207,6 +270,34 @@ #define mpam_set_feature(_feat, x) __set_bit(_feat, (x)->features) #define mpam_clear_feature(_feat, x) __clear_bit(_feat, (x)->features) +/* Workaround bits for msc->quirks */ +enum mpam_device_quirks { + T241_SCRUB_SHADOW_REGS, + T241_FORCE_MBW_MIN_TO_ONE, + T241_MBW_COUNTER_SCALE_64, + IGNORE_CSU_NRDY, + MPAM_QUIRK_LAST, +}; + +#define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks)) +#define mpam_set_quirk(_quirk, x) ((x)->quirks |= (1 << (_quirk))) + +struct mpam_quirk { + void (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk); + + u32 iidr; + u32 iidr_mask; + + enum mpam_device_quirks workaround; +}; + +#define IIDR_PROD(x) ((x) << MPAMF_IIDR_PRODUCTID_SHIFT) +#define IIDR_VAR(x) ((x) << MPAMF_IIDR_VARIANT_SHIFT) +#define IIDR_REV(x) ((x) << MPAMF_IIDR_REVISION_SHIFT) +#define IIDR_IMP(x) ((x) << MPAMF_IIDR_IMPLEMENTER_SHIFT) + +#define IIDR_MATCH_ONE (IIDR_PROD(0xfff) | IIDR_VAR(0xf) | IIDR_REV(0xf) | IIDR_IMP(0xfff)) + /* The values for MSMON_CFG_MBWU_FLT.RWBW */ enum mon_filter_options { COUNT_BOTH = 0, @@ -215,7 +306,11 @@ }; struct mon_cfg { - u16 mon; + /* + * mon must be large enough to hold out of range values like + * USE_RMID_IDX + */ + u32 mon; u8 pmg; bool match_pmg; bool csu_exclude_clean; @@ -246,6 +341,7 @@ struct mpam_props props; u32 nrdy_usec; + u16 quirks; u8 level; enum mpam_class_types type; @@ -255,6 +351,7 @@ struct ida ida_csu_mon; struct ida ida_mbwu_mon; + struct dentry *debugfs; struct mpam_garbage garbage; }; @@ -265,6 +362,11 @@ u32 cpbm; u32 mbw_pbm; u16 mbw_max; + u16 mbw_min; + u16 cmax; + u16 cmin; + + bool cmax_softlim; bool reset_cpbm; bool reset_mbw_pbm; @@ -293,6 +395,7 @@ /* parent: */ struct mpam_class *class; + struct dentry *debugfs; struct mpam_garbage garbage; }; @@ -311,12 +414,15 @@ /* parent: */ struct mpam_component *comp; + struct dentry *debugfs; struct mpam_garbage garbage; }; struct mpam_msc_ris { u8 ris_idx; u64 idr; + u32 cpor_idr; + u32 ccap_idr; struct mpam_props props; bool in_reset_state; @@ -334,9 +440,50 @@ /* msmon mbwu configuration is preserved over reset */ struct msmon_mbwu_state *mbwu_state; + struct dentry *debugfs; struct mpam_garbage garbage; }; +struct mpam_resctrl_dom { + struct mpam_component *ctrl_comp; + + /* + * There is no single mon_comp because different events may be backed + * by different class/components. mon_comp is indexed by the event + * number. + */ + struct mpam_component *mon_comp[QOS_NUM_EVENTS]; + + struct rdt_ctrl_domain resctrl_ctrl_dom; + struct rdt_l3_mon_domain resctrl_mon_dom; + + u32 mbm_local_evt_cfg; +}; + +struct mpam_resctrl_res { + struct mpam_class *class; + struct rdt_resource resctrl_res; +}; + +struct mpam_resctrl_mon { + struct mpam_class *class; + + /* + * Array of allocated MBWU monitors, indexed by (closid, rmid). + * When ABMC is not in use, this array directly maps (closid, rmid) + * to the allocated monitor. Otherwise this array is sparse, and + * un-assigned (closid, rmid) are -1. + */ + int *mbwu_idx_to_mon; + + /* + * Array of assigned MBWU monitors, indexed by idx argument. + * When ABMC is not in use, this array can be NULL. Otherwise + * it maps idx to the allocated monitor. + */ + int *assigned_counters; +}; + static inline int mpam_alloc_csu_mon(struct mpam_class *class) { struct mpam_props *cprops = &class->props; @@ -381,16 +528,42 @@ void mpam_enable(struct work_struct *work); void mpam_disable(struct work_struct *work); +/* Reset all the RIS in a class, optionally while holding cpus_read_lock() */ +void mpam_reset_class_locked(struct mpam_class *class); +void mpam_reset_class(struct mpam_class *class); + +/* Reset all the RIS in a component under cpus_read_lock() */ +void mpam_reset_component_locked(struct mpam_component *comp); + int mpam_apply_config(struct mpam_component *comp, u16 partid, struct mpam_config *cfg); int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, enum mpam_device_features, u64 *val); void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx); +void mpam_msmon_reset_all_mbwu(struct mpam_component *comp); int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); +bool mpam_force_unknown_msc_test(struct mpam_msc *msc); + +void mpam_pcc_rx_callback(struct mbox_client *cl, void *msg); + +#ifdef CONFIG_RESCTRL_FS +int mpam_resctrl_setup(void); +void mpam_resctrl_exit(void); +int mpam_resctrl_online_cpu(unsigned int cpu); +int mpam_resctrl_offline_cpu(unsigned int cpu); +void mpam_resctrl_teardown_class(struct mpam_class *class); +#else +static inline int mpam_resctrl_setup(void) { return 0; } +static inline void mpam_resctrl_exit(void) { } +static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; } +static inline int mpam_resctrl_offline_cpu(unsigned int cpu) { return 0; } +static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { } +#endif /* CONFIG_RESCTRL_FS */ + /* * MPAM MSCs have the following register layout. See: * Arm Memory System Resource Partitioning and Monitoring (MPAM) System @@ -518,6 +691,11 @@ #define MPAMF_IIDR_VARIANT GENMASK(19, 16) #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) +#define MPAMF_IIDR_IMPLEMENTER_SHIFT 0 +#define MPAMF_IIDR_REVISION_SHIFT 12 +#define MPAMF_IIDR_VARIANT_SHIFT 16 +#define MPAMF_IIDR_PRODUCTID_SHIFT 20 + /* MPAMF_AIDR - MPAM architecture ID register */ #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) @@ -547,6 +725,7 @@ * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration * register */ +#define MPAMCFG_MBW_MAX_MAX_NR_BITS 16 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) --- linux-nvidia-7.0.0.orig/drivers/resctrl/mpam_resctrl.c +++ linux-nvidia-7.0.0/drivers/resctrl/mpam_resctrl.c @@ -0,0 +1,2522 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2025 Arm Ltd. + +#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "mpam_internal.h" + +DECLARE_WAIT_QUEUE_HEAD(resctrl_mon_ctx_waiters); + +/* + * The classes we've picked to map to resctrl resources, wrapped + * in with their resctrl structure. + * Class pointer may be NULL. + */ +static struct mpam_resctrl_res mpam_resctrl_controls[RDT_NUM_RESOURCES]; + +/* The lock for modifying resctrl's domain lists from cpuhp callbacks. */ +static DEFINE_MUTEX(domain_list_lock); + +/* + * The classes we've picked to map to resctrl events. + * Resctrl believes all the worlds a Xeon, and these are all on the L3. This + * array lets us find the actual class backing the event counters. e.g. + * the only memory bandwidth counters may be on the memory controller, but to + * make use of them, we pretend they are on L3. + * Class pointer may be NULL. + */ +static struct mpam_resctrl_mon mpam_resctrl_counters[QOS_NUM_EVENTS]; + +static bool exposed_alloc_capable; +static bool exposed_mon_capable; + +/* + * MPAM emulates CDP by setting different PARTID in the I/D fields of MPAM0_EL1. + * This applies globally to all traffic the CPU generates. + */ +static bool cdp_enabled; + +/* + * To support CPU-less NUMA nodes, user-space needs to opt in to the MB + * domain IDs being the NUMA nid instead of the corresponding CPU's L3 + * cache-id. + */ +static bool mb_uses_numa_nid; +static bool mb_numa_nid_possible; +static bool mb_l3_cache_id_possible; +/* + * If resctrl_init() succeeded, resctrl_exit() can be used to remove support + * for the filesystem in the event of an error. + */ +static bool resctrl_enabled; + +/* + * mpam_resctrl_pick_caches() needs to know the size of the caches. cacheinfo + * populates this from a device_initcall(). mpam_resctrl_setup() must wait. + */ +static bool cacheinfo_ready; +static DECLARE_WAIT_QUEUE_HEAD(wait_cacheinfo_ready); + +/* + * L3 local/total may come from different classes - what is the number of MBWU + * 'on L3'? + */ +static unsigned int l3_num_allocated_mbwu = ~0; + +/* Whether this num_mbw_mon could result in a free_running system */ +static int __mpam_monitors_free_running(u16 num_mbwu_mon) +{ + if (num_mbwu_mon >= resctrl_arch_system_num_rmid_idx()) + return resctrl_arch_system_num_rmid_idx(); + return 0; +} + +/* + * If l3_num_allocated_mbwu is forced below PARTID * PMG, then the counters + * are not free running, and ABMC's user-interface must be used to assign them. + */ +static bool mpam_resctrl_abmc_enabled(void) +{ + return l3_num_allocated_mbwu < resctrl_arch_system_num_rmid_idx(); +} + +bool resctrl_arch_alloc_capable(void) +{ + return exposed_alloc_capable; +} + +bool resctrl_arch_mon_capable(void) +{ + return exposed_mon_capable; +} + +bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) +{ + switch (rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + return cdp_enabled; + case RDT_RESOURCE_MBA: + default: + /* + * x86's MBA control doesn't support CDP, so user-space doesn't + * expect it. + */ + return false; + } +} + +/** + * resctrl_reset_task_closids() - Reset the PARTID/PMG values for all tasks. + * + * At boot, all existing tasks use partid zero for D and I. + * To enable/disable CDP emulation, all these tasks need relabelling. + */ +static void resctrl_reset_task_closids(void) +{ + struct task_struct *p, *t; + + read_lock(&tasklist_lock); + for_each_process_thread(p, t) { + resctrl_arch_set_closid_rmid(t, RESCTRL_RESERVED_CLOSID, + RESCTRL_RESERVED_RMID); + } + read_unlock(&tasklist_lock); +} + +static void mpam_resctrl_monitor_sync_abmc_vals(struct rdt_resource *l3) +{ + l3->mon.num_mbm_cntrs = l3_num_allocated_mbwu; + if (cdp_enabled) + l3->mon.num_mbm_cntrs /= 2; + + if (l3->mon.num_mbm_cntrs) { + l3->mon.mbm_cntr_assignable = mpam_resctrl_abmc_enabled(); + l3->mon.mbm_assign_on_mkdir = mpam_resctrl_abmc_enabled(); + } else { + l3->mon.mbm_cntr_assignable = false; + l3->mon.mbm_assign_on_mkdir = false; + } +} + +int resctrl_arch_set_cdp_enabled(enum resctrl_res_level ignored, bool enable) +{ + struct mpam_resctrl_res *res = &mpam_resctrl_controls[RDT_RESOURCE_L3]; + struct rdt_resource *l3 = &res->resctrl_res; + u32 partid, partid_i, partid_d; + u64 regval; + + cdp_enabled = enable; + + partid = RESCTRL_RESERVED_CLOSID; + + if (enable) { + partid_d = resctrl_get_config_index(partid, CDP_CODE); + partid_i = resctrl_get_config_index(partid, CDP_DATA); + regval = FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d) | + FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i); + } else { + regval = FIELD_PREP(MPAM0_EL1_PARTID_D, partid) | + FIELD_PREP(MPAM0_EL1_PARTID_I, partid); + } + + resctrl_reset_task_closids(); + mpam_resctrl_monitor_sync_abmc_vals(l3); + + WRITE_ONCE(arm64_mpam_global_default, regval); + + return 0; +} + +static bool mpam_resctrl_hide_cdp(enum resctrl_res_level rid) +{ + return cdp_enabled && !resctrl_arch_get_cdp_enabled(rid); +} + +/* + * MSC may raise an error interrupt if it sees an out or range partid/pmg, + * and go on to truncate the value. Regardless of what the hardware supports, + * only the system wide safe value is safe to use. + */ +u32 resctrl_arch_get_num_closid(struct rdt_resource *ignored) +{ + return mpam_partid_max + 1; +} + +u32 resctrl_arch_system_num_rmid_idx(void) +{ + u8 closid_shift = fls(mpam_pmg_max); + u32 num_partid = resctrl_arch_get_num_closid(NULL); + + return num_partid << closid_shift; +} + +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid) +{ + u8 closid_shift = fls(mpam_pmg_max); + + WARN_ON_ONCE(closid_shift > 8); + + return (closid << closid_shift) | rmid; +} + +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid) +{ + u8 closid_shift = fls(mpam_pmg_max); + u32 pmg_mask = ~(~0 << closid_shift); + + WARN_ON_ONCE(closid_shift > 8); + + *closid = idx >> closid_shift; + *rmid = idx & pmg_mask; +} + +void resctrl_arch_sched_in(struct task_struct *tsk) +{ + lockdep_assert_preemption_disabled(); + + mpam_thread_switch(tsk); +} + +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmid) +{ + WARN_ON_ONCE(closid > U16_MAX); + WARN_ON_ONCE(rmid > U8_MAX); + + if (!cdp_enabled) { + mpam_set_cpu_defaults(cpu, closid, closid, rmid, rmid); + } else { + /* + * When CDP is enabled, resctrl halves the closid range and we + * use odd/even partid for one closid. + */ + u32 partid_d = resctrl_get_config_index(closid, CDP_DATA); + u32 partid_i = resctrl_get_config_index(closid, CDP_CODE); + + mpam_set_cpu_defaults(cpu, partid_d, partid_i, rmid, rmid); + } +} + +void resctrl_arch_sync_cpu_closid_rmid(void *info) +{ + struct resctrl_cpu_defaults *r = info; + + lockdep_assert_preemption_disabled(); + + if (r) { + resctrl_arch_set_cpu_default_closid_rmid(smp_processor_id(), + r->closid, r->rmid); + } + + resctrl_arch_sched_in(current); +} + +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32 rmid) +{ + WARN_ON_ONCE(closid > U16_MAX); + WARN_ON_ONCE(rmid > U8_MAX); + + if (!cdp_enabled) { + mpam_set_task_partid_pmg(tsk, closid, closid, rmid, rmid); + } else { + u32 partid_d = resctrl_get_config_index(closid, CDP_DATA); + u32 partid_i = resctrl_get_config_index(closid, CDP_CODE); + + mpam_set_task_partid_pmg(tsk, partid_d, partid_i, rmid, rmid); + } +} + +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid) +{ + u64 regval = mpam_get_regval(tsk); + u32 tsk_closid = FIELD_GET(MPAM0_EL1_PARTID_D, regval); + + if (cdp_enabled) + tsk_closid >>= 1; + + return tsk_closid == closid; +} + +/* The task's pmg is not unique, the partid must be considered too */ +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid) +{ + u64 regval = mpam_get_regval(tsk); + u32 tsk_closid = FIELD_GET(MPAM0_EL1_PARTID_D, regval); + u32 tsk_rmid = FIELD_GET(MPAM0_EL1_PMG_D, regval); + + if (cdp_enabled) + tsk_closid >>= 1; + + return (tsk_closid == closid) && (tsk_rmid == rmid); +} + +int resctrl_arch_set_iommu_closid_rmid(struct iommu_group *group, u32 closid, + u32 rmid) +{ + u16 partid; + + if (!IS_ENABLED(CONFIG_RESCTRL_IOMMU)) + return 0; + + if (cdp_enabled) + partid = closid << 1; + else + partid = closid; + + return iommu_group_set_qos_params(group, partid, rmid); +} + +bool resctrl_arch_match_iommu_closid(struct iommu_group *group, u32 closid) +{ + u16 partid; + int err = iommu_group_get_qos_params(group, &partid, NULL); + + if (!IS_ENABLED(CONFIG_RESCTRL_IOMMU)) + return false; + + if (err) + return false; + + if (cdp_enabled) + partid >>= 1; + + return (partid == closid); +} + +bool resctrl_arch_match_iommu_closid_rmid(struct iommu_group *group, + u32 closid, u32 rmid) +{ + u8 pmg; + u16 partid; + int err = iommu_group_get_qos_params(group, &partid, &pmg); + + if (!IS_ENABLED(CONFIG_RESCTRL_IOMMU)) + return false; + + if (err) + return false; + + if (cdp_enabled) + partid >>= 1; + + return (partid == closid) && (rmid == pmg); +} + +struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) +{ + if (l >= RDT_NUM_RESOURCES) + return NULL; + + return &mpam_resctrl_controls[l].resctrl_res; +} + +static int resctrl_arch_mon_ctx_alloc_no_wait(enum resctrl_event_id evtid) +{ + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[evtid]; + + if (!mpam_is_enabled()) + return -EINVAL; + + if (!mon->class) + return -EINVAL; + + switch (evtid) { + case QOS_L3_OCCUP_EVENT_ID: + /* With CDP, one monitor gets used for both code/data reads */ + return mpam_alloc_csu_mon(mon->class); + case QOS_L3_MBM_LOCAL_EVENT_ID: + case QOS_L3_MBM_TOTAL_EVENT_ID: + return USE_PRE_ALLOCATED; + default: + return -EOPNOTSUPP; + } +} + +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, + enum resctrl_event_id evtid) +{ + DEFINE_WAIT(wait); + int *ret; + + ret = kmalloc(sizeof(*ret), GFP_KERNEL); + if (!ret) + return ERR_PTR(-ENOMEM); + + do { + prepare_to_wait(&resctrl_mon_ctx_waiters, &wait, + TASK_INTERRUPTIBLE); + *ret = resctrl_arch_mon_ctx_alloc_no_wait(evtid); + if (*ret == -ENOSPC) + schedule(); + } while (*ret == -ENOSPC && !signal_pending(current)); + finish_wait(&resctrl_mon_ctx_waiters, &wait); + + return ret; +} + +static void resctrl_arch_mon_ctx_free_no_wait(enum resctrl_event_id evtid, + u32 mon_idx) +{ + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[evtid]; + + if (!mpam_is_enabled()) + return; + + if (!mon->class) + return; + + if (evtid == QOS_L3_OCCUP_EVENT_ID) + mpam_free_csu_mon(mon->class, mon_idx); + + wake_up(&resctrl_mon_ctx_waiters); +} + +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, + enum resctrl_event_id evtid, void *arch_mon_ctx) +{ + u32 mon_idx = *(u32 *)arch_mon_ctx; + + kfree(arch_mon_ctx); + arch_mon_ctx = NULL; + + resctrl_arch_mon_ctx_free_no_wait(evtid, mon_idx); +} + +static bool __resctrl_arch_mon_can_overflow(enum resctrl_event_id eventid) +{ + struct mpam_props *cprops; + struct mpam_class *class = mpam_resctrl_counters[eventid].class; + + if (!class) + return false; + + /* No need to worry about a 63 bit counter overflowing */ + cprops = &class->props; + return !mpam_has_feature(mpam_feat_msmon_mbwu_63counter, cprops); +} + +bool resctrl_arch_mon_can_overflow(void) +{ + if (__resctrl_arch_mon_can_overflow(QOS_L3_MBM_LOCAL_EVENT_ID)) + return true; + + return __resctrl_arch_mon_can_overflow(QOS_L3_MBM_TOTAL_EVENT_ID); +} + +static int +__read_mon(struct mpam_resctrl_mon *mon, struct mpam_component *mon_comp, + enum mpam_device_features mon_type, enum mon_filter_options mon_opts, + int mon_idx, + enum resctrl_conf_type cdp_type, u32 closid, u32 rmid, u64 *val) +{ + struct mon_cfg cfg = { }; + + if (!mpam_is_enabled()) + return -EINVAL; + + /* Shift closid to account for CDP */ + closid = resctrl_get_config_index(closid, cdp_type); + + if (mon_idx == USE_PRE_ALLOCATED) { + int mbwu_idx = resctrl_arch_rmid_idx_encode(closid, rmid); + mon_idx = mon->mbwu_idx_to_mon[mbwu_idx]; + if (mon_idx == -1) { + if (mpam_resctrl_abmc_enabled()) { + /* Report Unassigned */ + return -ENOENT; + } + /* Report Unavailable */ + return -EINVAL; + } + } + + cfg.mon = mon_idx; + cfg.match_pmg = true; + cfg.partid = closid; + cfg.pmg = rmid; + cfg.opts = mon_opts; + + if (irqs_disabled()) { + /* Check if we can access this domain without an IPI */ + return -EIO; + } + + return mpam_msmon_read(mon_comp, &cfg, mon_type, val); +} + +static int read_mon_cdp_safe(struct mpam_resctrl_mon *mon, struct mpam_component *mon_comp, + enum mpam_device_features mon_type, enum mon_filter_options mon_opts, + int mon_idx, u32 closid, u32 rmid, u64 *val) +{ + if (cdp_enabled) { + u64 cdp_val = 0; + int err; + + err = __read_mon(mon, mon_comp, mon_type, mon_opts, mon_idx, + CDP_CODE, closid, rmid, &cdp_val); + if (err) + return err; + + err = __read_mon(mon, mon_comp, mon_type, mon_opts, mon_idx, + CDP_DATA, closid, rmid, &cdp_val); + if (!err) + *val += cdp_val; + return err; + } + + return __read_mon(mon, mon_comp, mon_type, mon_idx, mon_opts, + CDP_NONE, closid, rmid, val); +} + +static enum mon_filter_options resctrl_evt_config_to_mpam(u32 local_evt_cfg) +{ + switch (local_evt_cfg) { + case READS_TO_LOCAL_MEM: + return COUNT_READ; + case NON_TEMP_WRITE_TO_LOCAL_MEM: + return COUNT_WRITE; + default: + return COUNT_BOTH; + } +} + +/* MBWU when not in ABMC mode, and CSU counters. */ +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr, + u32 closid, u32 rmid, enum resctrl_event_id eventid, + void *arch_priv, u64 *val, void *arch_mon_ctx) +{ + struct rdt_l3_mon_domain *d; + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + enum mon_filter_options mon_opts; + u32 mon_idx = *(u32 *)arch_mon_ctx; + enum mpam_device_features mon_type; + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[eventid]; + + resctrl_arch_rmid_read_context_check(); + + if (!mpam_is_enabled()) + return -EINVAL; + + if (eventid >= QOS_NUM_EVENTS || !mon->class) + return -EINVAL; + + if (!domain_header_is_valid(hdr, RESCTRL_MON_DOMAIN, RDT_RESOURCE_L3)) + return -EINVAL; + + d = container_of(hdr, struct rdt_l3_mon_domain, hdr); + l3_dom = container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp = l3_dom->mon_comp[eventid]; + mon_opts = resctrl_evt_config_to_mpam(l3_dom->mbm_local_evt_cfg); + + switch (eventid) { + case QOS_L3_OCCUP_EVENT_ID: + mon_type = mpam_feat_msmon_csu; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + case QOS_L3_MBM_TOTAL_EVENT_ID: + mon_type = mpam_feat_msmon_mbwu; + break; + default: + return -EINVAL; + } + + return read_mon_cdp_safe(mon, mon_comp, mon_type, mon_opts, mon_idx, + closid, rmid, val); +} + +/* MBWU counters when in ABMC mode */ +int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_l3_mon_domain *d, + u32 closid, u32 rmid, int mon_idx, + enum resctrl_event_id eventid, u64 *val) +{ + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[eventid]; + enum mon_filter_options mon_opts; + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + + if (!mpam_is_enabled()) + return -EINVAL; + + if (eventid == QOS_L3_OCCUP_EVENT_ID || !mon->class) + return -EINVAL; + + l3_dom = container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp = l3_dom->mon_comp[eventid]; + mon_opts = resctrl_evt_config_to_mpam(l3_dom->mbm_local_evt_cfg); + + return read_mon_cdp_safe(mon, mon_comp, mpam_feat_msmon_mbwu, mon_idx, + mon_opts, closid, rmid, val); +} + +static void __reset_mon(struct mpam_resctrl_mon *mon, struct mpam_component *mon_comp, + int mon_idx, + enum resctrl_conf_type cdp_type, u32 closid, u32 rmid) +{ + struct mon_cfg cfg = { }; + + if (!mpam_is_enabled()) + return; + + /* Shift closid to account for CDP */ + closid = resctrl_get_config_index(closid, cdp_type); + + if (mon_idx == USE_PRE_ALLOCATED) { + int mbwu_idx = resctrl_arch_rmid_idx_encode(closid, rmid); + mon_idx = mon->mbwu_idx_to_mon[mbwu_idx]; + } + + if (mon_idx == -1) + return; + cfg.mon = mon_idx; + mpam_msmon_reset_mbwu(mon_comp, &cfg); +} + +static void reset_mon_cdp_safe(struct mpam_resctrl_mon *mon, struct mpam_component *mon_comp, + int mon_idx, u32 closid, u32 rmid) +{ + if (cdp_enabled) { + __reset_mon(mon, mon_comp, mon_idx, CDP_CODE, closid, rmid); + __reset_mon(mon, mon_comp, mon_idx, CDP_DATA, closid, rmid); + } else { + __reset_mon(mon, mon_comp, mon_idx, CDP_NONE, closid, rmid); + } +} + +/* Called via IPI. Call with read_cpus_lock() held. */ +void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_l3_mon_domain *d, + u32 closid, u32 rmid, enum resctrl_event_id eventid) +{ + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[eventid]; + + if (!mpam_is_enabled()) + return; + + /* Only MBWU counters are relevant, and for supported event types. */ + if (eventid == QOS_L3_OCCUP_EVENT_ID || !mon->class) + return; + + l3_dom = container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp = l3_dom->mon_comp[eventid]; + + reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); +} + +/* Reset an assigned counter */ +void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_l3_mon_domain *d, + u32 closid, u32 rmid, int cntr_id, + enum resctrl_event_id eventid) +{ + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[eventid]; + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + + if (!mpam_is_enabled()) + return; + + if (eventid == QOS_L3_OCCUP_EVENT_ID || !mon->class) + return; + + l3_dom = container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp = l3_dom->mon_comp[eventid]; + + reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); +} + +/* + * The rmid realloc threshold should be for the smallest cache exposed to + * resctrl. + */ +static void update_rmid_limits(unsigned int size) +{ + u32 num_unique_pmg = resctrl_arch_system_num_rmid_idx(); + + if (WARN_ON_ONCE(!size)) + return; + + if (resctrl_rmid_realloc_limit && size > resctrl_rmid_realloc_limit) + return; + + resctrl_rmid_realloc_limit = size; + resctrl_rmid_realloc_threshold = size / num_unique_pmg; +} + +static bool cache_has_usable_cpor(struct mpam_class *class) +{ + struct mpam_props *cprops = &class->props; + + if (!mpam_has_feature(mpam_feat_cpor_part, cprops)) + return false; + + /* TODO: Scaling is not yet supported */ + /* resctrl uses u32 for all bitmap configurations */ + return (class->props.cpbm_wd <= 32); +} + +static bool cache_has_usable_cmax(struct mpam_class *class) +{ + struct mpam_props *cprops = &class->props; + + return mpam_has_feature(mpam_feat_cmax_cmax, cprops); +} + +static bool mba_class_use_mbw_part(struct mpam_props *cprops) +{ + if (!mpam_has_feature(mpam_feat_mbw_part, cprops) || + cprops->mbw_pbm_bits < 1) + return false; + + /* u32 is used to represent MBW PBM bitmaps in the driver, for now: */ + return cprops->mbw_pbm_bits <= 32; +} + +static bool mba_class_use_mbw_max(struct mpam_props *cprops) +{ + return (mpam_has_feature(mpam_feat_mbw_max, cprops) && + cprops->bwa_wd); +} + +static bool class_has_usable_mba(struct mpam_props *cprops) +{ + return mba_class_use_mbw_part(cprops) || mba_class_use_mbw_max(cprops); +} + +static bool cache_has_usable_csu(struct mpam_class *class) +{ + struct mpam_props *cprops; + + if (!class) + return false; + + cprops = &class->props; + + if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) + return false; + + /* + * CSU counters settle on the value, so we can get away with + * having only one. + */ + if (!cprops->num_csu_mon) + return false; + + return (mpam_partid_max > 1) || (mpam_pmg_max != 0); +} + +static bool class_has_usable_mbwu(struct mpam_class *class) +{ + struct mpam_props *cprops = &class->props; + + if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) + return false; + + /* + * resctrl expects the bandwidth counters to be free running, + * which means we need as many monitors as resctrl has + * control/monitor groups. + */ + if (__mpam_monitors_free_running(cprops->num_mbwu_mon)) { + pr_debug("monitors usable in free-running mode\n"); + return true; + } + + if (cprops->num_mbwu_mon) { + pr_debug("monitors usable via ABMC assignment\n"); + return true; + } + + return false; +} + +/* + * Calculate the worst-case percentage change from each implemented step + * in the control. + */ +static u32 get_mba_granularity(struct mpam_props *cprops) +{ + if (mba_class_use_mbw_part(cprops)) { + return DIV_ROUND_UP(MAX_MBA_BW, cprops->mbw_pbm_bits); + } else if (mba_class_use_mbw_max(cprops)) { + /* + * bwa_wd is the number of bits implemented in the 0.xxx + * fixed point fraction. 1 bit is 50%, 2 is 25% etc. + */ + return DIV_ROUND_UP(MAX_MBA_BW, 1 << cprops->bwa_wd); + } + + return 0; +} + +static u32 mbw_pbm_to_percent(const unsigned long mbw_pbm, + struct mpam_props *cprops) +{ + u32 val = bitmap_weight(&mbw_pbm, (unsigned int)cprops->mbw_pbm_bits); + + if (cprops->mbw_pbm_bits == 0) + return 0; + + val *= MAX_MBA_BW; + val = DIV_ROUND_CLOSEST(val, cprops->mbw_pbm_bits); + + return val; +} + +static u32 percent_to_mbw_pbm(u8 pc, struct mpam_props *cprops) +{ + u32 val = pc; + unsigned long ret = 0; + + if (cprops->mbw_pbm_bits == 0) + return 0; + + val *= cprops->mbw_pbm_bits; + val = DIV_ROUND_CLOSEST(val, MAX_MBA_BW); + + /* TODO: pick bits at random to avoid contention */ + bitmap_set(&ret, 0, val); + return ret; +} + +/* + * Each fixed-point hardware value architecturally represents a range + * of values: the full range 0% - 100% is split contiguously into + * (1 << cprops->bwa_wd) equal bands. + * Find the nearest percentage value to the upper bound of the selected band: + */ +static u32 fract16_to_percent(u16 fract, u8 wd) +{ + u32 val = fract; + + val >>= 16 - wd; + val += 1; + val *= MAX_MBA_BW; + val = DIV_ROUND_CLOSEST(val, 1 << wd); + + return val; +} + +/* + * Find the band whose upper bound is closest to the specified percentage. + * + * A round-to-nearest policy is followed here as a balanced compromise + * between unexpected under-commit of the resource (where the total of + * a set of resource allocations after conversion is less than the + * expected total, due to rounding of the individual converted + * percentages) and over-commit (where the total of the converted + * allocations is greater than expected). + */ +static u16 percent_to_fract16(u8 pc, u8 wd) +{ + u32 val = pc; + + val <<= wd; + val = DIV_ROUND_CLOSEST(val, MAX_MBA_BW); + val = max(val, 1) - 1; + val <<= 16 - wd; + + return val; +} + +static u32 mbw_max_to_percent(u16 mbw_max, struct mpam_props *cprops) +{ + return fract16_to_percent(mbw_max, cprops->bwa_wd); +} + +static u16 percent_to_mbw_max(u8 pc, struct mpam_props *cprops) +{ + return percent_to_fract16(pc, cprops->bwa_wd); +} + +static u16 percent_to_cmax(u8 pc, struct mpam_props *cprops) +{ + return percent_to_fract16(pc, cprops->cmax_wd); +} + +static u32 get_mba_min(struct mpam_props *cprops) +{ + u32 val = 0; + + if (mba_class_use_mbw_part(cprops)) + val = mbw_pbm_to_percent(val, cprops); + else if (mba_class_use_mbw_max(cprops)) + val = mbw_max_to_percent(val, cprops); + else + WARN_ON_ONCE(1); + + return val; +} + +/* Find the L3 cache that has affinity with this CPU */ +static int find_l3_equivalent_bitmask(int cpu, cpumask_var_t tmp_cpumask) +{ + int err; + u32 cache_id = get_cpu_cacheinfo_id(cpu, 3); + + lockdep_assert_cpus_held(); + + err = mpam_get_cpumask_from_cache_id(cache_id, 3, tmp_cpumask); + return err; +} + +/* + * topology_matches_l3() - Is the provided class the same shape as L3 + * @victim: The class we'd like to pretend is L3. + * + * resctrl expects all the worlds a Xeon, and all counters are on the + * L3. We play fast and loose with this, mapping counters on other + * classes - provided the CPU->domain mapping is the same kind of shape. + * + * Using cacheinfo directly would make this work even if resctrl can't + * use the L3 - but cacheinfo can't tell us anything about offline CPUs. + * Using the L3 resctrl domain list also depends on CPUs being online. + * Using the mpam_class we picked for L3 so we can use its domain list + * assumes that there are MPAM controls on the L3. + * Instead, this path eventually uses the mpam_get_cpumask_from_cache_id() + * helper. This relies on at least one CPU per L3 cache being online at + * boot. + * + * Walk the two component lists and compare the affinity masks. The topology + * matches if each victim:component has a corresponding L3:component with the + * same affinity mask. These lists/masks are computed from firmware tables so + * don't change at runtime. + */ +static bool topology_matches_l3(struct mpam_class *victim) +{ + int cpu, err; + struct mpam_component *victim_iter; + cpumask_var_t __free(free_cpumask_var) tmp_cpumask; + + if (!alloc_cpumask_var(&tmp_cpumask, GFP_KERNEL)) + return false; + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(victim_iter, &victim->components, class_list, + srcu_read_lock_held(&mpam_srcu)) { + if (cpumask_empty(&victim_iter->affinity)) { + pr_debug("class %u has CPU-less component %u - can't match L3!\n", + victim->level, victim_iter->comp_id); + return false; + } + + cpu = cpumask_any(&victim_iter->affinity); + if (WARN_ON_ONCE(cpu >= nr_cpu_ids)) + return false; + + cpumask_clear(tmp_cpumask); + err = find_l3_equivalent_bitmask(cpu, tmp_cpumask); + if (err) { + pr_debug("Failed to find L3's equivalent component to class %u component %u\n", + victim->level, victim_iter->comp_id); + return false; + } + + /* Any differing bits in the affinity mask? */ + if (!cpumask_equal(tmp_cpumask, &victim_iter->affinity)) { + pr_debug("class %u component %u has Mismatched CPU mask with L3 equivalent\n" + "L3:%*pbl != victim:%*pbl\n", + victim->level, victim_iter->comp_id, + cpumask_pr_args(tmp_cpumask), + cpumask_pr_args(&victim_iter->affinity)); + + return false; + } + } + + return true; +} + +static bool topology_matches_numa(struct mpam_class *victim) +{ + /* + * For now, check this is a memory class, in which case component + * id are already NUMA nid. + */ + return (victim->type == MPAM_CLASS_MEMORY); +} + +/* Test whether we can export MPAM_CLASS_CACHE:{2,3}? */ +static void mpam_resctrl_pick_caches(void) +{ + bool has_cpor, has_cmax; + struct mpam_class *class; + struct mpam_resctrl_res *res; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(class, &mpam_classes, classes_list, + srcu_read_lock_held(&mpam_srcu)) { + if (class->type != MPAM_CLASS_CACHE) { + pr_debug("class %u is not a cache\n", class->level); + continue; + } + + if (class->level != 2 && class->level != 3) { + pr_debug("class %u is not L2 or L3\n", class->level); + continue; + } + + has_cpor = cache_has_usable_cpor(class); + has_cmax = cache_has_usable_cmax(class); + if (!has_cpor && !has_cmax) { + pr_debug("class %u cache misses CPOR\n", class->level); + continue; + } + + if (!cpumask_equal(&class->affinity, cpu_possible_mask)) { + pr_debug("class %u Class has missing CPUs\n", class->level); + pr_debug("class %u mask %*pb != %*pb\n", class->level, + cpumask_pr_args(&class->affinity), + cpumask_pr_args(cpu_possible_mask)); + continue; + } + + if (has_cpor) { + pr_debug("pick_caches: Class has CPOR\n"); + if (class->level == 2) + res = &mpam_resctrl_controls[RDT_RESOURCE_L2]; + else + res = &mpam_resctrl_controls[RDT_RESOURCE_L3]; + res->class = class; + exposed_alloc_capable = true; + } + if (has_cmax) { + pr_debug("pick_caches: Class has CMAX\n"); + if (class->level == 2) + res = &mpam_resctrl_controls[RDT_RESOURCE_L2_MAX]; + else + res = &mpam_resctrl_controls[RDT_RESOURCE_L3_MAX]; + res->class = class; + exposed_alloc_capable = true; + } + } +} + +static void mpam_resctrl_pick_mba(void) +{ + struct mpam_class *class, *candidate_class = NULL; + struct mpam_resctrl_res *res; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(class, &mpam_classes, classes_list, + srcu_read_lock_held(&mpam_srcu)) { + struct mpam_props *cprops = &class->props; + bool l3_cache_id_possible = false; + bool numa_nid_possible = false; + + if (class->level < 3) { + pr_debug("class %u is before L3\n", class->level); + continue; + } + + if (!class_has_usable_mba(cprops)) { + pr_debug("class %u has no bandwidth control\n", class->level); + continue; + } + + if (!cpumask_equal(&class->affinity, cpu_possible_mask)) { + pr_debug("class %u has missing CPUs\n", class->level); + continue; + } + + if (topology_matches_numa(class)) { + pr_debug("class %u topology matches NUMA domains\n", class->level); + numa_nid_possible = true; + } + + if (topology_matches_l3(class)) { + pr_debug("class %u topology matches L3\n", class->level); + l3_cache_id_possible = true; + } + + if (!l3_cache_id_possible && !numa_nid_possible) { + pr_debug("class %u has no matching topology for MB\n", class->level); + continue; + } + + /* + * mba_sc reads the mbm_local counter, and waggles the MBA controls. + * mbm_local is implicitly part of the L3, pick a resource to be MBA + * that as close as possible to the L3. + */ + if (!candidate_class || class->level < candidate_class->level) { + /* + * Refuse to pick a closer class if it would prevent cache-id + * being used as domain-id by default. + */ + if (!candidate_class || l3_cache_id_possible) { + candidate_class = class; + mb_l3_cache_id_possible = l3_cache_id_possible; + mb_numa_nid_possible = numa_nid_possible; + } + } + } + + if (candidate_class) { + pr_debug("selected class %u to back MBA\n", candidate_class->level); + res = &mpam_resctrl_controls[RDT_RESOURCE_MBA]; + res->class = candidate_class; + exposed_alloc_capable = true; + } +} + +static void __free_mbwu_mon(struct mpam_class *class, int *array, + u16 num_mbwu_mon) +{ + for (int i = 0; i < num_mbwu_mon; i++) { + if (array[i] < 0) + continue; + + mpam_free_mbwu_mon(class, array[i]); + array[i] = ~0; + } +} + +static int __alloc_mbwu_mon(struct mpam_class *class, int *array, + u16 num_mbwu_mon) +{ + for (int i = 0; i < num_mbwu_mon; i++) { + int mbwu_mon = mpam_alloc_mbwu_mon(class); + + if (mbwu_mon < 0) { + __free_mbwu_mon(class, array, num_mbwu_mon); + return mbwu_mon; + } + array[i] = mbwu_mon; + } + + l3_num_allocated_mbwu = min(l3_num_allocated_mbwu, num_mbwu_mon); + + return 0; +} + +static int *__alloc_mbwu_array(struct mpam_class *class, u16 num_mbwu_mon) +{ + int err; + size_t array_size = num_mbwu_mon * sizeof(int); + int *array __free(kfree) = kmalloc(array_size, GFP_KERNEL); + + if (!array) + return ERR_PTR(-ENOMEM); + + memset(array, -1, array_size); + + err = __alloc_mbwu_mon(class, array, num_mbwu_mon); + if (err) + return ERR_PTR(err); + return_ptr(array); +} + +static void counter_update_class(enum resctrl_event_id evt_id, + struct mpam_class *class) +{ + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[evt_id]; + struct mpam_class *existing_class = mon->class; + u16 num_mbwu_mon = class->props.num_mbwu_mon; + int *existing_array = mon->mbwu_idx_to_mon; + + if (existing_class) { + if (class->level == 3) { + pr_debug("Existing class is L3 - L3 wins\n"); + return; + } else if (existing_class->level < class->level) { + pr_debug("Existing class is closer to L3, %u versus %u - closer is better\n", + existing_class->level, class->level); + return; + } + } + + pr_debug("Updating event %u to use class %u\n", evt_id, class->level); + mon->class = class; + exposed_mon_capable = true; + + if (evt_id == QOS_L3_OCCUP_EVENT_ID) + return; + + /* Might not need all the monitors */ + num_mbwu_mon = __mpam_monitors_free_running(num_mbwu_mon); + if (!num_mbwu_mon) { + pr_debug("Not pre-allocating free-running counters\n"); + return; + } + + /* + * This is the pre-allocated free-running monitors path. It always + * allocates one monitor per PARTID * PMG. + */ + WARN_ON_ONCE(num_mbwu_mon != resctrl_arch_system_num_rmid_idx()); + + mon->mbwu_idx_to_mon = __alloc_mbwu_array(class, num_mbwu_mon); + if (IS_ERR(mon->mbwu_idx_to_mon)) { + pr_debug("Failed to allocate MBWU array\n"); + mon->class = existing_class; + mon->mbwu_idx_to_mon = existing_array; + return; + } + + if (existing_array) { + pr_debug("Releasing previous class %u's monitors\n", + existing_class->level); + __free_mbwu_mon(existing_class, existing_array, num_mbwu_mon); + kfree(existing_array); + } +} + +static void mpam_resctrl_pick_counters(void) +{ + struct mpam_class *class; + unsigned int cache_size; + bool has_csu, has_mbwu; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(class, &mpam_classes, classes_list, + srcu_read_lock_held(&mpam_srcu)) { + struct mpam_props *cprops = &class->props; + + if (class->level < 3) { + pr_debug("class %u is before L3", class->level); + continue; + } + + if (!cpumask_equal(&class->affinity, cpu_possible_mask)) { + pr_debug("class %u does not cover all CPUs", class->level); + continue; + } + + has_csu = cache_has_usable_csu(class); + if (has_csu && topology_matches_l3(class)) { + pr_debug("class %u has usable CSU, and matches L3 topology", class->level); + + /* CSU counters only make sense on a cache. */ + switch (class->type) { + case MPAM_CLASS_CACHE: + /* Assume cache levels are the same size for all CPUs... */ + cache_size = get_cpu_cacheinfo_size(smp_processor_id(), + class->level); + if (!cache_size) { + pr_debug("Could not read cache size for class %u\n", + class->level); + continue; + } + + if (mpam_has_feature(mpam_feat_msmon_csu, cprops)) + update_rmid_limits(cache_size); + + counter_update_class(QOS_L3_OCCUP_EVENT_ID, class); + return; + default: + return; + } + } + + has_mbwu = class_has_usable_mbwu(class); + if (has_mbwu && topology_matches_l3(class)) { + pr_debug("class %u has usable MBWU, and matches L3 topology", class->level); + + /* + * MBWU counters may be 'local' or 'total' depending on + * where they are in the topology. Counters on caches + * are assumed to be local. If it's on the memory + * controller, its assumed to be global. + * TODO: check mbm_local matches NUMA boundaries... + */ + switch (class->type) { + case MPAM_CLASS_CACHE: + counter_update_class(QOS_L3_MBM_LOCAL_EVENT_ID, + class); + break; + case MPAM_CLASS_MEMORY: + counter_update_class(QOS_L3_MBM_TOTAL_EVENT_ID, + class); + break; + default: + break; + } + } + } + + /* Allocation of MBWU monitors assumes that the class is unique... */ + if (mpam_resctrl_counters[QOS_L3_MBM_LOCAL_EVENT_ID].class) + WARN_ON_ONCE(mpam_resctrl_counters[QOS_L3_MBM_LOCAL_EVENT_ID].class == + mpam_resctrl_counters[QOS_L3_MBM_TOTAL_EVENT_ID].class); +} + +bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) +{ + struct mpam_class *class; + struct mpam_props *cprops; + + class = mpam_resctrl_counters[evt].class; + if (!class) + return false; + + cprops = &class->props; + + return mpam_has_feature(mpam_feat_msmon_mbwu_rwbw, cprops); +} + +void resctrl_arch_mon_event_config_read(void *info) +{ + struct mpam_resctrl_dom *dom; + struct resctrl_mon_config_info *mon_info = info; + + if (!mpam_is_enabled()) { + mon_info->mon_config = 0; + return; + } + + dom = container_of(mon_info->d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_info->mon_config = dom->mbm_local_evt_cfg & MAX_EVT_CONFIG_BITS; +} + +void resctrl_arch_mon_event_config_write(void *info) +{ + struct mpam_resctrl_dom *dom; + struct resctrl_mon_config_info *mon_info = info; + + WARN_ON_ONCE(mon_info->mon_config & ~MPAM_RESTRL_EVT_CONFIG_VALID); + + dom = container_of(mon_info->d, struct mpam_resctrl_dom, resctrl_mon_dom); + + if (!mpam_is_enabled()) { + dom->mbm_local_evt_cfg = 0; + return; + } + + dom->mbm_local_evt_cfg = mon_info->mon_config & MPAM_RESTRL_EVT_CONFIG_VALID; +} + +void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_l3_mon_domain *d) +{ + int i; + struct mpam_resctrl_dom *dom; + struct mpam_resctrl_mon *mon; + struct mpam_component *mon_comp; + + dom = container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + if (!mpam_is_enabled()) { + dom->mbm_local_evt_cfg = 0; + return; + } + dom->mbm_local_evt_cfg = MPAM_RESTRL_EVT_CONFIG_VALID; + + /* + * Monitors may be backed by different classes of MSC, all + * possible components need to be reset... + */ + for (i = 0; i < QOS_NUM_EVENTS; i++) { + mon = &mpam_resctrl_counters[i]; + if (!mon->class) + continue; // dummy resource + + mon_comp = dom->mon_comp[i]; + if (!mon_comp) + continue; + + mpam_msmon_reset_all_mbwu(mon_comp); + } +} + +static void __config_cntr(struct mpam_resctrl_mon *mon, u32 cntr_id, + enum resctrl_conf_type cdp_type, u32 closid, u32 rmid, + bool assign) +{ + u32 mbwu_idx, mon_idx = resctrl_get_config_index(cntr_id, cdp_type); + + closid = resctrl_get_config_index(closid, cdp_type); + mbwu_idx = resctrl_arch_rmid_idx_encode(closid, rmid); + WARN_ON_ONCE(mon_idx > l3_num_allocated_mbwu); + + if (assign) + mon->mbwu_idx_to_mon[mbwu_idx] = mon->assigned_counters[mon_idx]; + else + mon->mbwu_idx_to_mon[mbwu_idx] = -1; +} + +void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_l3_mon_domain *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ + struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[evtid]; + + if (!mon->mbwu_idx_to_mon || !mon->assigned_counters) { + pr_debug("monitor arrays not allocated\n"); + return; + } + + if (cdp_enabled) { + __config_cntr(mon, cntr_id, CDP_CODE, closid, rmid, assign); + __config_cntr(mon, cntr_id, CDP_DATA, closid, rmid, assign); + } else { + __config_cntr(mon, cntr_id, CDP_NONE, closid, rmid, assign); + } + + resctrl_arch_reset_rmid(r, d, closid, rmid, evtid); +} + +bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) +{ + if (r != &mpam_resctrl_controls[RDT_RESOURCE_L3].resctrl_res) + return false; + + return mpam_resctrl_abmc_enabled(); +} + +int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable) +{ + lockdep_assert_cpus_held(); + + WARN_ON_ONCE(1); + + return 0; +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + return -EOPNOTSUPP; +} + +bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) +{ + return false; +} + +void resctrl_arch_pre_mount(void) +{ +} + +static int mpam_resctrl_control_init(struct mpam_resctrl_res *res, + enum resctrl_res_level type) +{ + struct mpam_class *class = res->class; + struct mpam_props *cprops = &class->props; + struct rdt_resource *r = &res->resctrl_res; + + switch (res->resctrl_res.rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + r->alloc_capable = true; + r->schema_fmt = RESCTRL_SCHEMA_BITMAP; + r->cache.arch_has_sparse_bitmasks = true; + + /* TODO: Scaling is not yet supported */ + r->cache.cbm_len = class->props.cpbm_wd; + /* mpam_devices will reject empty bitmaps */ + r->cache.min_cbm_bits = 1; + + if (r->rid == RDT_RESOURCE_L2) { + r->name = "L2"; + r->ctrl_scope = RESCTRL_L2_CACHE; + } else { + r->name = "L3"; + r->ctrl_scope = RESCTRL_L3_CACHE; + } + + /* + * Which bits are shared with other ...things... + * Unknown devices use partid-0 which uses all the bitmap + * fields. Until we configured the SMMU and GIC not to do this + * 'all the bits' is the correct answer here. + */ + r->cache.shareable_bits = resctrl_get_resource_default_ctrl(r); + break; + case RDT_RESOURCE_L2_MAX: + case RDT_RESOURCE_L3_MAX: + r->alloc_capable = true; + r->schema_fmt = RESCTRL_SCHEMA_PERCENT; + r->membw.min_bw = max(100 / (1 << cprops->cmax_wd), 1); + r->membw.bw_gran = max(100 / (1 << cprops->cmax_wd), 1); + r->membw.max_bw = 100; + + if (r->rid == RDT_RESOURCE_L2_MAX) { + r->name = "L2_MAX"; + r->ctrl_scope = RESCTRL_L2_CACHE; + } else { + r->name = "L3_MAX"; + r->ctrl_scope = RESCTRL_L3_CACHE; + } + + break; + case RDT_RESOURCE_MBA: + /* Domain ID is the L3 cache-id by default */ + if (mb_l3_cache_id_possible) + r->alloc_capable = true; + + r->schema_fmt = RESCTRL_SCHEMA_PERCENT; + r->ctrl_scope = RESCTRL_L3_CACHE; + + r->mba.delay_linear = true; + r->mba.throttle_mode = THREAD_THROTTLE_UNDEFINED; + r->membw.min_bw = get_mba_min(cprops); + r->membw.max_bw = MAX_MBA_BW; + r->membw.bw_gran = get_mba_granularity(cprops); + + r->name = "MB"; + + break; + default: + break; + } + + return 0; +} + +static int mpam_resctrl_pick_domain_id(int cpu, struct mpam_component *comp) +{ + bool is_mb; + struct mpam_class *class = comp->class; + + is_mb = (mpam_resctrl_controls[RDT_RESOURCE_MBA].class == class); + + if (is_mb && mb_uses_numa_nid && topology_matches_numa(class)) + return comp->comp_id; + + if (class->type == MPAM_CLASS_CACHE) + return comp->comp_id; + + if (topology_matches_l3(class)) { + /* Use the corresponding L3 component ID as the domain ID */ + int id = get_cpu_cacheinfo_id(cpu, 3); + + /* Implies topology_matches_l3() made a mistake */ + if (WARN_ON_ONCE(id == -1)) + return comp->comp_id; + + return id; + } + + /* + * Otherwise, expose the ID used by the firmware table code. + */ + return comp->comp_id; +} + +/* + * This must run after all event counters have been picked so that any free + * running counters have already been allocated. + */ +static int mpam_resctrl_monitor_init_abmc(struct mpam_resctrl_mon *mon) +{ + struct mpam_resctrl_res *res = &mpam_resctrl_controls[RDT_RESOURCE_L3]; + size_t array_size = resctrl_arch_system_num_rmid_idx() * sizeof(int); + int *rmid_array __free(kfree) = kmalloc(array_size, GFP_KERNEL); + struct rdt_resource *l3 = &res->resctrl_res; + struct mpam_class *class = mon->class; + u16 num_mbwu_mon; + + if (mon->mbwu_idx_to_mon) { + pr_debug("monitors free running\n"); + return 0; + } + + if (!rmid_array) { + pr_debug("Failed to allocate RMID array\n"); + return -ENOMEM; + } + memset(rmid_array, -1, array_size); + + num_mbwu_mon = class->props.num_mbwu_mon; + mon->assigned_counters = __alloc_mbwu_array(mon->class, num_mbwu_mon); + if (IS_ERR(mon->assigned_counters)) + return PTR_ERR(mon->assigned_counters); + mon->mbwu_idx_to_mon = no_free_ptr(rmid_array); + + mpam_resctrl_monitor_sync_abmc_vals(l3); + + return 0; +} + +bool resctrl_arch_get_mb_uses_numa_nid(void) +{ + return mb_uses_numa_nid; +} + +int resctrl_arch_set_mb_uses_numa_nid(bool enabled) +{ + struct rdt_resource *r; + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + struct rdt_ctrl_domain *ctrl_d; + + lockdep_assert_cpus_held(); + lockdep_assert_mems_held(); + + if (!mb_numa_nid_possible) + return -EOPNOTSUPP; + + if (mb_uses_numa_nid == enabled) + return 0; + + /* Domain IDs as NUMA nid is only defined for MBA */ + res = &mpam_resctrl_controls[RDT_RESOURCE_MBA]; + if (!res->class) + return -EOPNOTSUPP; + r = &res->resctrl_res; + + /* repaint the domain IDs */ + mb_uses_numa_nid = enabled; + list_for_each_entry(ctrl_d, &r->ctrl_domains, hdr.list) { + int cpu = cpumask_any(&ctrl_d->hdr.cpu_mask); + + dom = container_of(ctrl_d, struct mpam_resctrl_dom, resctrl_ctrl_dom); + ctrl_d->hdr.id = mpam_resctrl_pick_domain_id(cpu, dom->ctrl_comp); + } + + /* monitor domains are unaffected and should continue to use the L3 */ + + if (!enabled && mb_l3_cache_id_possible) + r->alloc_capable = true; + else if (enabled && mb_numa_nid_possible) + r->alloc_capable = true; + else + r->alloc_capable = false; + + return 0; +} + +static void mpam_resctrl_monitor_init(struct mpam_resctrl_mon *mon, + enum resctrl_event_id type) +{ + struct mpam_resctrl_res *res = &mpam_resctrl_controls[RDT_RESOURCE_L3]; + struct rdt_resource *l3 = &res->resctrl_res; + + lockdep_assert_cpus_held(); + + /* There also needs to be an L3 cache present */ + if (get_cpu_cacheinfo_id(smp_processor_id(), 3) == -1) + return; + + /* + * If there are no MPAM resources on L3, force it into existence. + * topology_matches_l3() already ensures this looks like the L3. + * The domain-ids will be fixed up by mpam_resctrl_domain_hdr_init(). + */ + if (!res->class) { + pr_warn_once("Faking L3 MSC to enable counters.\n"); + res->class = mpam_resctrl_counters[type].class; + } + + /* Called multiple times!, once per event type */ + if (exposed_mon_capable) { + l3->mon_capable = true; + + /* Setting name is necessary on monitor only platforms */ + l3->name = "L3"; + l3->mon_scope = RESCTRL_L3_CACHE; + + resctrl_enable_mon_event(type, false, 0, NULL); + + /* + * Unfortunately, num_rmid doesn't mean anything for + * mpam, and its exposed to user-space! + * + * num-rmid is supposed to mean the minimum number of + * monitoring groups that can exist simultaneously, including + * the default monitoring group for each control group. + * + * For mpam, each control group has its own pmg/rmid space, so + * it is not appropriate to advertise the whole rmid_idx space + * here. But the pmgs corresponding to the parent control + * group can be allocated freely: + */ + l3->mon.num_rmid = mpam_pmg_max + 1;; + + switch (type) { + case QOS_L3_MBM_LOCAL_EVENT_ID: + case QOS_L3_MBM_TOTAL_EVENT_ID: + mpam_resctrl_monitor_init_abmc(mon); + l3->mon.mbm_cfg_mask = MPAM_RESTRL_EVT_CONFIG_VALID; + + return; + default: + return; + } + } +} + +u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain *d, + u32 closid, enum resctrl_conf_type type) +{ + u32 partid; + struct mpam_config *cfg; + struct mpam_props *cprops; + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + enum mpam_device_features configured_by; + + lockdep_assert_cpus_held(); + + if (!mpam_is_enabled()) + goto err; + + res = container_of(r, struct mpam_resctrl_res, resctrl_res); + dom = container_of(d, struct mpam_resctrl_dom, resctrl_ctrl_dom); + cprops = &res->class->props; + + /* + * When CDP is enabled, but the resource doesn't support it, + * the control is cloned across both partids. + * Pick one at random to read: + */ + if (mpam_resctrl_hide_cdp(r->rid)) + type = CDP_DATA; + + partid = resctrl_get_config_index(closid, type); + cfg = &dom->ctrl_comp->cfg[partid]; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + configured_by = mpam_feat_cpor_part; + break; + case RDT_RESOURCE_L2_MAX: + case RDT_RESOURCE_L3_MAX: + configured_by = mpam_feat_cmax_cmax; + break; + case RDT_RESOURCE_MBA: + if (mba_class_use_mbw_part(cprops)) { + configured_by = mpam_feat_mbw_part; + break; + } else if (mpam_has_feature(mpam_feat_mbw_max, cprops)) { + configured_by = mpam_feat_mbw_max; + break; + } + fallthrough; + default: + goto err; + } + + if (!r->alloc_capable || partid >= resctrl_arch_get_num_closid(r) || + !mpam_has_feature(configured_by, cfg)) + goto err; + + switch (configured_by) { + case mpam_feat_cpor_part: + /* TODO: Scaling is not yet supported */ + return cfg->cpbm; + case mpam_feat_cmax_cmax: + return fract16_to_percent(cfg->cmax, cprops->cmax_wd); + case mpam_feat_mbw_part: + /* TODO: Scaling is not yet supported */ + return mbw_pbm_to_percent(cfg->mbw_pbm, cprops); + case mpam_feat_mbw_max: + return mbw_max_to_percent(cfg->mbw_max, cprops); + default: + goto err; + } + +err: + return resctrl_get_resource_default_ctrl(r); +} + +int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain *d, + u32 closid, enum resctrl_conf_type t, u32 cfg_val) +{ + int err; + u32 partid; + struct mpam_config cfg; + struct mpam_props *cprops; + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + + lockdep_assert_cpus_held(); + lockdep_assert_irqs_enabled(); + + if (!mpam_is_enabled()) + return -EINVAL; + + /* + * NOTE: don't check the CPU as mpam_apply_config() doesn't care, + * and resctrl_arch_update_domains() depends on this. + */ + res = container_of(r, struct mpam_resctrl_res, resctrl_res); + dom = container_of(d, struct mpam_resctrl_dom, resctrl_ctrl_dom); + cprops = &res->class->props; + + partid = resctrl_get_config_index(closid, t); + if (!r->alloc_capable || partid >= resctrl_arch_get_num_closid(r)) { + pr_debug("Not alloc capable or computed PARTID out of range\n"); + return -EINVAL; + } + + /* + * Copy the current config to avoid clearing other resources when the + * same component is exposed multiple times through resctrl. + */ + cfg = dom->ctrl_comp->cfg[partid]; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + /* TODO: Scaling is not yet supported */ + cfg.cpbm = cfg_val; + mpam_set_feature(mpam_feat_cpor_part, &cfg); + break; + case RDT_RESOURCE_L2_MAX: + case RDT_RESOURCE_L3_MAX: + cfg.cmax = percent_to_cmax(cfg_val, cprops); + mpam_set_feature(mpam_feat_cmax_cmax, &cfg); + break; + case RDT_RESOURCE_MBA: + if (mba_class_use_mbw_part(cprops)) { + cfg.mbw_pbm = percent_to_mbw_pbm(cfg_val, cprops); + mpam_set_feature(mpam_feat_mbw_part, &cfg); + break; + } else if (mpam_has_feature(mpam_feat_mbw_max, cprops)) { + cfg.mbw_max = percent_to_mbw_max(cfg_val, cprops); + mpam_set_feature(mpam_feat_mbw_max, &cfg); + break; + } + fallthrough; + default: + return -EINVAL; + } + + /* + * When CDP is enabled, but the resource doesn't support it, we need to + * apply the same configuration to the other partid. + */ + if (mpam_resctrl_hide_cdp(r->rid)) { + partid = resctrl_get_config_index(closid, CDP_CODE); + err = mpam_apply_config(dom->ctrl_comp, partid, &cfg); + if (err) + return err; + + partid = resctrl_get_config_index(closid, CDP_DATA); + return mpam_apply_config(dom->ctrl_comp, partid, &cfg); + + } else { + return mpam_apply_config(dom->ctrl_comp, partid, &cfg); + } +} + +/* TODO: this is IPI heavy */ +int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid) +{ + int err = 0; + enum resctrl_conf_type t; + struct rdt_ctrl_domain *d; + struct resctrl_staged_config *cfg; + + lockdep_assert_cpus_held(); + lockdep_assert_irqs_enabled(); + + if (!mpam_is_enabled()) + return -EINVAL; + + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + for (t = 0; t < CDP_NUM_TYPES; t++) { + cfg = &d->staged_config[t]; + if (!cfg->have_new_ctrl) + continue; + + err = resctrl_arch_update_one(r, d, closid, t, + cfg->new_ctrl); + if (err) + return err; + } + } + + return err; +} + +void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) +{ + struct mpam_resctrl_res *res; + + lockdep_assert_cpus_held(); + + if (!mpam_is_enabled()) + return; + + res = container_of(r, struct mpam_resctrl_res, resctrl_res); + mpam_reset_class_locked(res->class); +} + +/** + * mpam_resctrl_domain_hdr_init() - Bring a subset of a domain online. + * @onlined_cpus: The set of CPUs that are online from the domain's + * perspective. + * @comp: The mpam component being brought online. + * @hdr: The header representing the domain. + * + * Adds @onlined_cpus to @hdr's cpu_mask, and sets the @hdr id. + * For NUMA nodes, @onlined_cpus will be cpu_possible_mask. + */ +static void mpam_resctrl_domain_hdr_init(const struct cpumask *onlined_cpus, + struct mpam_component *comp, + struct rdt_domain_hdr *hdr) +{ + int cpu = cpumask_any(onlined_cpus); + + lockdep_assert_cpus_held(); + + INIT_LIST_HEAD(&hdr->list); + hdr->id = mpam_resctrl_pick_domain_id(cpu, comp); + cpumask_and(&hdr->cpu_mask, &hdr->cpu_mask, onlined_cpus); +} + +/** + * mpam_resctrl_offline_domain_hdr() - Take a subset of a domain offline. + * @offlined_cpus: The set of CPUs that are offline from the domain's + * perspective. + * @hdr: The domain's header. + * + * Removes @offlined_cpus from @hdr's cpu_mask. If the list is empty, + * the domain header is removed from its parent list and true is returned, + * indicating the parent structure can be freed. + * If there are other CPUs in the domain, returns false. + * + * For NUMA nodes, @offlined_cpus will be cpu_possible_mask. + */ +static bool mpam_resctrl_offline_domain_hdr(const struct cpumask *offlined_cpus, + struct rdt_domain_hdr *hdr) +{ + cpumask_andnot(&hdr->cpu_mask, &hdr->cpu_mask, offlined_cpus); + if (cpumask_empty(&hdr->cpu_mask)) { + list_del(&hdr->list); + return true; + } + + return false; +} + +static struct mpam_component *find_component(struct mpam_class *victim, + const struct cpumask *onlined_cpus) +{ + struct mpam_component *victim_comp; + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(victim_comp, &victim->components, class_list, + srcu_read_lock_held(&mpam_srcu)) { + struct cpumask tmp; + + cpumask_andnot(&tmp, onlined_cpus, &victim_comp->affinity); + if (cpumask_empty(&tmp)) + return victim_comp; + } + + return NULL; +} + +static void mpam_resctrl_domain_insert(struct list_head *list, + struct rdt_domain_hdr *new) +{ + struct rdt_domain_hdr *err; + struct list_head *pos = NULL; + + lockdep_assert_held(&domain_list_lock); + + err = resctrl_find_domain(list, new->id, &pos); + if (WARN_ON_ONCE(err)) + return; + + list_add_tail_rcu(&new->list, pos); +} + +static struct mpam_resctrl_dom * +mpam_resctrl_alloc_domain(const struct cpumask *onlined_cpus, int nid, + struct mpam_component *ctrl_comp, + struct mpam_resctrl_res *res) +{ + int err; + struct mpam_resctrl_dom *dom; + struct rdt_l3_mon_domain *mon_d; + struct rdt_ctrl_domain *ctrl_d; + struct rdt_resource *r = &res->resctrl_res; + + lockdep_assert_held(&domain_list_lock); + + dom = kzalloc_node(sizeof(*dom), GFP_KERNEL, nid); + if (!dom) + return ERR_PTR(-ENOMEM); + + if (exposed_alloc_capable) { + dom->ctrl_comp = ctrl_comp; + + ctrl_d = &dom->resctrl_ctrl_dom; + mpam_resctrl_domain_hdr_init(onlined_cpus, ctrl_comp, &ctrl_d->hdr); + ctrl_d->hdr.type = RESCTRL_CTRL_DOMAIN; + mpam_resctrl_domain_insert(&r->ctrl_domains, &ctrl_d->hdr); + err = resctrl_online_ctrl_domain(r, ctrl_d); + if (err) { + dom = ERR_PTR(err); + goto offline_ctrl_domain; + } + } else { + pr_debug("Skipped control domain online - no controls\n"); + } + + if (exposed_mon_capable) { + int i; + struct mpam_component *mon_comp, *any_mon_comp; + + /* + * Even if the monitor domain is backed by a different component, + * the L3 component IDs need to be used... only there may be no + * ctrl_comp for the L3. + * Search each event's class list for a component with overlapping + * CPUs and set up the dom->mon_comp array. + */ + for (i = 0; i < QOS_NUM_EVENTS; i++) { + struct mpam_resctrl_mon *mon; + + mon = &mpam_resctrl_counters[i]; + if (!mon->class) + continue; // dummy resource + + mon_comp = find_component(mon->class, onlined_cpus); + dom->mon_comp[i] = mon_comp; + if (mon_comp) + any_mon_comp = mon_comp; + } + WARN_ON_ONCE(!any_mon_comp); + + dom->mbm_local_evt_cfg = MPAM_RESTRL_EVT_CONFIG_VALID; + + mon_d = &dom->resctrl_mon_dom; + mpam_resctrl_domain_hdr_init(onlined_cpus, any_mon_comp, + &mon_d->hdr); + mon_d->hdr.type = RESCTRL_MON_DOMAIN; + mpam_resctrl_domain_insert(&r->mon_domains, &mon_d->hdr); + err = resctrl_online_mon_domain(r, &mon_d->hdr); + if (err) { + dom = ERR_PTR(err); + goto offline_mon_hdr; + } + } else { + pr_debug("Skipped monitor domain online - no monitors\n"); + } + goto out; + +offline_mon_hdr: + mpam_resctrl_offline_domain_hdr(onlined_cpus, &ctrl_d->hdr); + +offline_ctrl_domain: + resctrl_offline_ctrl_domain(r, ctrl_d); +out: + return dom; +} + +/* + * We know all the monitors are associated with the L3, even if there are no + * controls and therefore no control component. Find the cache-id for the CPU + * and use that to search for existing resctrl domains. + * This relies on mpam_resctrl_pick_domain_id() using the L3 cache-id + * for anything that is not a cache. + */ +static struct mpam_resctrl_dom *mpam_resctrl_get_mon_domain_from_cpu(int cpu) +{ + u32 cache_id; + struct rdt_l3_mon_domain *mon_d; + struct mpam_resctrl_dom *dom; + struct mpam_resctrl_res *l3 = &mpam_resctrl_controls[RDT_RESOURCE_L3]; + + if (!l3->class) + return NULL; + /* TODO: how does this order with cacheinfo updates under cpuhp? */ + cache_id = get_cpu_cacheinfo_id(cpu, 3); + if (cache_id == ~0) + return NULL; + + list_for_each_entry(mon_d, &l3->resctrl_res.mon_domains, hdr.list) { + dom = container_of(mon_d, struct mpam_resctrl_dom, resctrl_mon_dom); + + if (mon_d->hdr.id == cache_id) + return dom; + } + + return NULL; +} + +/** + * mpam_resctrl_get_domain_from_cpu() - find the mpam domain structure + * @cpu: The CPU that is going online/offline. + * @res: The resctrl resource the domain should belong to. + * + * The component structures must be used to identify the CPU may be marked + * offline in the resctrl structures. However the resctrl domain list is + * used to search as this is also used to determine if resctrl thinks the + * domain is online. + * For platforms with controls, this is easy as each resource has one control + * component. + * For the monitors, we need to search the list of events... + */ +static struct mpam_resctrl_dom * +mpam_resctrl_alloc_domain_cpu(int cpu, struct mpam_resctrl_res *res) +{ + struct mpam_component *comp_iter, *ctrl_comp; + struct mpam_class *class = res->class; + int idx; + + ctrl_comp = NULL; + idx = srcu_read_lock(&mpam_srcu); + list_for_each_entry_srcu(comp_iter, &class->components, class_list, + srcu_read_lock_held(&mpam_srcu)) { + if (cpumask_test_cpu(cpu, &comp_iter->affinity)) { + ctrl_comp = comp_iter; + break; + } + } + srcu_read_unlock(&mpam_srcu, idx); + + /* cpu with unknown exported component? */ + if (WARN_ON_ONCE(!ctrl_comp)) + return ERR_PTR(-EINVAL); + + return mpam_resctrl_alloc_domain(cpumask_of(cpu), cpu_to_node(cpu), + ctrl_comp, res); +} + +static struct mpam_resctrl_dom * +mpam_resctrl_alloc_domain_nid(int nid, struct mpam_resctrl_res *res) +{ + struct mpam_component *comp_iter, *ctrl_comp; + struct mpam_class *class = res->class; + int idx; + + /* Only the memory class uses comp_id as nid */ + if (class->type != MPAM_CLASS_MEMORY) + return ERR_PTR(-EINVAL); + + ctrl_comp = NULL; + idx = srcu_read_lock(&mpam_srcu); + list_for_each_entry_srcu(comp_iter, &class->components, class_list, + srcu_read_lock_held(&mpam_srcu)) { + if (comp_iter->comp_id == nid) { + ctrl_comp = comp_iter; + break; + } + } + srcu_read_unlock(&mpam_srcu, idx); + + /* cpu with unknown exported component? */ + if (WARN_ON_ONCE(!ctrl_comp)) + return ERR_PTR(-EINVAL); + + return mpam_resctrl_alloc_domain(cpu_possible_mask, nid, ctrl_comp, res); +} + +static struct mpam_resctrl_dom * +mpam_resctrl_get_domain_from_cpu(int cpu, struct mpam_resctrl_res *res) +{ + struct mpam_resctrl_dom *dom; + struct rdt_ctrl_domain *ctrl_d; + struct rdt_resource *r = &res->resctrl_res; + + lockdep_assert_cpus_held(); + + list_for_each_entry(ctrl_d, &r->ctrl_domains, hdr.list) { + dom = container_of(ctrl_d, struct mpam_resctrl_dom, resctrl_ctrl_dom); + + if (cpumask_test_cpu(cpu, &dom->ctrl_comp->affinity)) + return dom; + } + + if (r->rid != RDT_RESOURCE_L3) + return NULL; + + /* Search the mon domain list too - needed on monitor only platforms. */ + return mpam_resctrl_get_mon_domain_from_cpu(cpu); +} + +static struct mpam_resctrl_dom * +mpam_get_domain_from_nid(int nid, struct mpam_resctrl_res *res) +{ + struct rdt_ctrl_domain *d; + struct mpam_resctrl_dom *dom; + + list_for_each_entry(d, &res->resctrl_res.ctrl_domains, hdr.list) { + dom = container_of(d, struct mpam_resctrl_dom, resctrl_ctrl_dom); + + /* Only the memory class uses comp_id as nid */ + if (dom->ctrl_comp->class->type != MPAM_CLASS_MEMORY) + continue; + + if (dom->ctrl_comp->comp_id == nid) + return dom; + } + + return NULL; +} + +int mpam_resctrl_online_cpu(unsigned int cpu) +{ + int i, err = 0; + struct mpam_resctrl_dom *dom; + struct mpam_resctrl_res *res; + + mutex_lock(&domain_list_lock); + for (i = 0; i < RDT_NUM_RESOURCES; i++) { + res = &mpam_resctrl_controls[i]; + if (!res->class) + continue; // dummy_resource; + + dom = mpam_resctrl_get_domain_from_cpu(cpu, res); + if (!dom) + dom = mpam_resctrl_alloc_domain_cpu(cpu, res); + if (IS_ERR(dom)) { + err = PTR_ERR(dom); + break; + } + + cpumask_set_cpu(cpu, &dom->resctrl_ctrl_dom.hdr.cpu_mask); + cpumask_set_cpu(cpu, &dom->resctrl_mon_dom.hdr.cpu_mask); + } + mutex_unlock(&domain_list_lock); + + if (!err) + resctrl_online_cpu(cpu); + + return err; +} + +int mpam_resctrl_offline_cpu(unsigned int cpu) +{ + int i; + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + struct rdt_l3_mon_domain *mon_d; + struct rdt_ctrl_domain *ctrl_d; + bool ctrl_dom_empty, mon_dom_empty; + + resctrl_offline_cpu(cpu); + + mutex_lock(&domain_list_lock); + for (i = 0; i < RDT_NUM_RESOURCES; i++) { + res = &mpam_resctrl_controls[i]; + if (!res->class) + continue; // dummy resource + + dom = mpam_resctrl_get_domain_from_cpu(cpu, res); + if (WARN_ON_ONCE(!dom)) + continue; + + ctrl_dom_empty = true; + if (exposed_alloc_capable) { + mpam_reset_component_locked(dom->ctrl_comp); + + ctrl_d = &dom->resctrl_ctrl_dom; + ctrl_dom_empty = mpam_resctrl_offline_domain_hdr(cpumask_of(cpu), + &ctrl_d->hdr); + if (ctrl_dom_empty) + resctrl_offline_ctrl_domain(&res->resctrl_res, ctrl_d); + } + + mon_dom_empty = true; + if (exposed_mon_capable) { + mon_d = &dom->resctrl_mon_dom; + mon_dom_empty = mpam_resctrl_offline_domain_hdr(cpumask_of(cpu), + &mon_d->hdr); + if (mon_dom_empty) + resctrl_offline_mon_domain(&res->resctrl_res, &mon_d->hdr); + } + + if (ctrl_dom_empty && mon_dom_empty) + kfree(dom); + } + mutex_unlock(&domain_list_lock); + + return 0; +} + +static int mpam_resctrl_online_node(unsigned int nid) +{ + struct mpam_resctrl_dom *dom; + struct mpam_resctrl_res *res; + + /* Domain IDs as NUMA nid is only defined for MBA */ + res = &mpam_resctrl_controls[RDT_RESOURCE_MBA]; + if (!res->class) + return 0; // dummy_resource; + + dom = mpam_get_domain_from_nid(nid, res); + if (!dom) + dom = mpam_resctrl_alloc_domain_nid(nid, res); + if (IS_ERR(dom)) + return PTR_ERR(dom); + + return 0; +} + +static int mpam_resctrl_offline_node(unsigned int nid) +{ + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + struct rdt_l3_mon_domain *mon_d; + struct rdt_ctrl_domain *ctrl_d; + + /* Domain IDs as NUMA nid is only defined for MBA */ + res = &mpam_resctrl_controls[RDT_RESOURCE_MBA]; + if (!res->class) + return 0; // dummy_resource; + + dom = mpam_get_domain_from_nid(nid, res); + if (WARN_ON_ONCE(!dom)) + return 0; + + ctrl_d = &dom->resctrl_ctrl_dom; + resctrl_offline_ctrl_domain(&res->resctrl_res, ctrl_d); + if (!mpam_resctrl_offline_domain_hdr(cpu_possible_mask, &ctrl_d->hdr)) + return 0; + + // TODO: skip monitor domains if there are no monitors for this resource + mon_d = &dom->resctrl_mon_dom; + resctrl_offline_mon_domain(&res->resctrl_res, &mon_d->hdr); + if (!mpam_resctrl_offline_domain_hdr(cpu_possible_mask, &mon_d->hdr)) + return 0; + + kfree(dom); + + return 0; +} + +static int mpam_resctrl_node_notifier(struct notifier_block *self, + unsigned long action, void *arg) +{ + struct node_notify *nn = arg; + + if (nn->nid < 0 || !mb_uses_numa_nid) + return NOTIFY_OK; + + /* + * Ignore nid that have CPUs. Resctrl needs to see the cpu offline + * call for each CPU to update the CPUs in control groups. Moving + * the overflow handler isn't an issue as only L3 can be mon_capable, + * and NUMA nid used as domain-id are only an option for MBA. + */ + if (!cpumask_empty(cpumask_of_node(nn->nid))) + return NOTIFY_OK; + + switch (action) { + case NODE_ADDED_FIRST_MEMORY: + mpam_resctrl_online_node(nn->nid); + break; + case NODE_REMOVED_LAST_MEMORY: + mpam_resctrl_offline_node(nn->nid); + break; + default: + /* don't care */ + } + + return NOTIFY_OK; +} + +int mpam_resctrl_setup(void) +{ + int err = 0; + enum resctrl_event_id j; + enum resctrl_res_level i; + struct mpam_resctrl_res *res; + struct mpam_resctrl_mon *mon; + + wait_event(wait_cacheinfo_ready, cacheinfo_ready); + + cpus_read_lock(); + for (i = 0; i < RDT_NUM_RESOURCES; i++) { + res = &mpam_resctrl_controls[i]; + INIT_LIST_HEAD(&res->resctrl_res.ctrl_domains); + INIT_LIST_HEAD(&res->resctrl_res.mon_domains); + res->resctrl_res.rid = i; + } + + /* Find some classes to use for controls */ + mpam_resctrl_pick_caches(); + mpam_resctrl_pick_mba(); + + /* Initialise the resctrl structures from the classes */ + for (i = 0; i < RDT_NUM_RESOURCES; i++) { + res = &mpam_resctrl_controls[i]; + if (!res->class) + continue; // dummy resource + + err = mpam_resctrl_control_init(res, i); + if (err) { + pr_debug("Failed to initialise rid %u\n", i); + break; + } + } + + /* Find some classes to use for monitors */ + mpam_resctrl_pick_counters(); + + for (j = 0; j < QOS_NUM_EVENTS; j++) { + mon = &mpam_resctrl_counters[j]; + if (!mon->class) + continue; // dummy resource + + mpam_resctrl_monitor_init(mon, j); + } + + if (mb_numa_nid_possible) { + hotplug_node_notifier(mpam_resctrl_node_notifier, + RESCTRL_CALLBACK_PRI); + } + + cpus_read_unlock(); + + if (err || (!exposed_alloc_capable && !exposed_mon_capable)) { + if (err) + pr_debug("Internal error %d - resctrl not supported\n", err); + else + pr_debug("No alloc(%u) or monitor(%u) found - resctrl not supported\n", + exposed_alloc_capable, exposed_mon_capable); + err = -EOPNOTSUPP; + } + + if (!err) { + if (!is_power_of_2(mpam_pmg_max + 1)) { + /* + * If not all the partid*pmg values are valid indexes, + * resctrl may allocate pmg that don't exist. This + * should cause an error interrupt. + */ + pr_warn("Number of PMG is not a power of 2! resctrl may misbehave"); + } + + err = resctrl_init(); + if (!err) + WRITE_ONCE(resctrl_enabled, true); + } + + return err; +} + +void mpam_resctrl_exit(void) +{ + if (!READ_ONCE(resctrl_enabled)) + return; + + WRITE_ONCE(resctrl_enabled, false); + resctrl_exit(); +} + +static void mpam_resctrl_teardown_mon(struct mpam_resctrl_mon *mon, struct mpam_class *class) +{ + u32 num_mbwu_mon = l3_num_allocated_mbwu; + + if (!mon->mbwu_idx_to_mon) + return; + + if (mon->assigned_counters) { + __free_mbwu_mon(class, mon->assigned_counters, num_mbwu_mon); + mon->assigned_counters = NULL; + kfree(mon->mbwu_idx_to_mon); + } else { + __free_mbwu_mon(class, mon->mbwu_idx_to_mon, num_mbwu_mon); + } + mon->mbwu_idx_to_mon = NULL; +} + +/* + * The driver is detaching an MSC from this class, if resctrl was using it, + * pull on resctrl_exit(). + */ +void mpam_resctrl_teardown_class(struct mpam_class *class) +{ + int i; + struct mpam_resctrl_res *res; + struct mpam_resctrl_mon *mon; + + might_sleep(); + + for (i = 0; i < RDT_NUM_RESOURCES; i++) { + res = &mpam_resctrl_controls[i]; + if (res->class == class) { + mpam_resctrl_exit(); + res->class = NULL; + break; + } + } + for (i = 0; i < QOS_NUM_EVENTS; i++) { + mon = &mpam_resctrl_counters[i]; + if (mon->class == class) { + mpam_resctrl_exit(); + mon->class = NULL; + + mpam_resctrl_teardown_mon(mon, class); + + break; + } + } +} + +static int __init __cacheinfo_ready(void) +{ + cacheinfo_ready = true; + wake_up(&wait_cacheinfo_ready); + + return 0; +} +device_initcall_sync(__cacheinfo_ready); + +#ifdef CONFIG_MPAM_KUNIT_TEST +#include "test_mpam_resctrl.c" +#endif --- linux-nvidia-7.0.0.orig/drivers/resctrl/test_mpam_devices.c +++ linux-nvidia-7.0.0/drivers/resctrl/test_mpam_devices.c @@ -12,17 +12,19 @@ { struct mpam_props parent = { 0 }; struct mpam_props child; + size_t props_bytes = offsetof(struct mpam_props, num_mbwu_mon) + + sizeof(parent.num_mbwu_mon); memset(&child, 0xff, sizeof(child)); __props_mismatch(&parent, &child, false); memset(&child, 0, sizeof(child)); - KUNIT_EXPECT_EQ(test, memcmp(&parent, &child, sizeof(child)), 0); + KUNIT_EXPECT_EQ(test, memcmp(&parent, &child, props_bytes), 0); memset(&child, 0xff, sizeof(child)); __props_mismatch(&parent, &child, true); - KUNIT_EXPECT_EQ(test, memcmp(&parent, &child, sizeof(child)), 0); + KUNIT_EXPECT_EQ(test, memcmp(&parent, &child, props_bytes), 0); } static struct list_head fake_classes_list; @@ -322,6 +324,71 @@ mutex_unlock(&mpam_list_lock); } +static void test_mpam_extend_config(struct kunit *test) +{ + struct mpam_config fake_cfg = { 0 }; + struct mpam_class fake_class = { 0 }; + + /* Configurations with both are not modified */ + fake_class.props.bwa_wd = 16; + fake_cfg.mbw_max = 0xfeef; + fake_cfg.mbw_min = 0xfeef; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_set_feature(mpam_feat_mbw_min, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xfeef); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xfeef); + + /* When a min is missing, it is generated */ + fake_class.props.bwa_wd = 16; + fake_cfg.mbw_max = 0xfeef; + fake_cfg.mbw_min = 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xfeef); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xf224); + + fake_class.props.bwa_wd = 8; + fake_cfg.mbw_max = 0xfeef; + fake_cfg.mbw_min = 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xfeef); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xf224); + + /* 5% below the minimum granule, is still the minimum granule */ + fake_class.props.bwa_wd = 12; + fake_cfg.mbw_max = 0xf; + fake_cfg.mbw_min = 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xf); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xf); + + fake_class.props.bwa_wd = 16; + fake_cfg.mbw_max = 0x4; + fake_cfg.mbw_min = 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0x4); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0x0); +} + static void __test_mpam_reset_msc_bitmap(struct mpam_msc *msc, u16 reg, u16 wd) { /* Avoid warnings when running with CONFIG_DEBUG_PREEMPT */ @@ -386,6 +453,7 @@ KUNIT_CASE(test_mpam_reset_msc_bitmap), KUNIT_CASE(test_mpam_enable_merge_features), KUNIT_CASE(test__props_mismatch), + KUNIT_CASE(test_mpam_extend_config), {} }; --- linux-nvidia-7.0.0.orig/drivers/resctrl/test_mpam_resctrl.c +++ linux-nvidia-7.0.0/drivers/resctrl/test_mpam_resctrl.c @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2025 Arm Ltd. +/* This file is intended to be included into mpam_resctrl.c */ + +#include +#include +#include +#include +#include + +struct percent_value_case { + u8 pc; + u8 width; + u16 value; +}; + +/* + * Mysterious inscriptions taken from ARM DDI 0598D.b, + * "Arm Architecture Reference Manual Supplement - Memory System + * Resource Partitioning and Monitoring (MPAM), for A-profile + * architecture", Section 9.8, "About the fixed-point fractional + * format" (exact percentage entries only): + */ +static const struct percent_value_case percent_value_cases[] = { + /* Architectural cases: */ + { 1, 8, 1 }, { 1, 12, 0x27 }, { 1, 16, 0x28e }, + { 25, 8, 0x3f }, { 25, 12, 0x3ff }, { 25, 16, 0x3fff }, + { 35, 8, 0x58 }, { 35, 12, 0x598 }, { 35, 16, 0x5998 }, + { 45, 8, 0x72 }, { 45, 12, 0x732 }, { 45, 16, 0x7332 }, + { 50, 8, 0x7f }, { 50, 12, 0x7ff }, { 50, 16, 0x7fff }, + { 52, 8, 0x84 }, { 52, 12, 0x850 }, { 52, 16, 0x851d }, + { 55, 8, 0x8b }, { 55, 12, 0x8cb }, { 55, 16, 0x8ccb }, + { 58, 8, 0x93 }, { 58, 12, 0x946 }, { 58, 16, 0x9479 }, + { 75, 8, 0xbf }, { 75, 12, 0xbff }, { 75, 16, 0xbfff }, + { 88, 8, 0xe0 }, { 88, 12, 0xe13 }, { 88, 16, 0xe146 }, + { 95, 8, 0xf2 }, { 95, 12, 0xf32 }, { 95, 16, 0xf332 }, + { 100, 8, 0xff }, { 100, 12, 0xfff }, { 100, 16, 0xffff }, + +}; + +static void test_percent_value_desc(const struct percent_value_case *param, + char *desc) +{ + snprintf(desc, KUNIT_PARAM_DESC_SIZE, + "pc=%d, width=%d, value=0x%.*x\n", + param->pc, param->width, + DIV_ROUND_UP(param->width, 4), param->value); +} + +KUNIT_ARRAY_PARAM(test_percent_value, percent_value_cases, + test_percent_value_desc); + +struct percent_value_test_info { + u32 pc; /* result of value-to-percent conversion */ + u32 value; /* result of percent-to-value conversion */ + u32 max_value; /* maximum raw value allowed by test params */ + unsigned int shift; /* promotes raw testcase value to 16 bits */ +}; + +/* + * Convert a reference percentage to a fixed-point MAX value and + * vice-versa, based on param (not test->param_value!) + */ +static void __prepare_percent_value_test(struct kunit *test, + struct percent_value_test_info *res, + const struct percent_value_case *param) +{ + struct mpam_props fake_props = { }; + + /* Reject bogus test parameters that would break the tests: */ + KUNIT_ASSERT_GE(test, param->width, 1); + KUNIT_ASSERT_LE(test, param->width, 16); + KUNIT_ASSERT_LT(test, param->value, 1 << param->width); + + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + fake_props.bwa_wd = param->width; + + res->shift = 16 - param->width; + res->max_value = GENMASK_U32(param->width - 1, 0); + res->value = percent_to_mbw_max(param->pc, &fake_props); + res->pc = mbw_max_to_percent(param->value << res->shift, &fake_props); +} + +static void test_get_mba_granularity(struct kunit *test) +{ + int ret; + struct mpam_props fake_props = { }; + + /* Use MBW_PBM */ + mpam_set_feature(mpam_feat_mbw_part, &fake_props); + + /* 0 bits means the control is unconfigurable */ + fake_props.mbw_pbm_bits = 0; + KUNIT_EXPECT_FALSE(test, mba_class_use_mbw_part(&fake_props)); + + /* Otherwise, bitmaps that fit in a u32 are supported: */ + fake_props.mbw_pbm_bits = 1; + KUNIT_EXPECT_TRUE(test, mba_class_use_mbw_part(&fake_props)); + + fake_props.mbw_pbm_bits = 32; + KUNIT_EXPECT_TRUE(test, mba_class_use_mbw_part(&fake_props)); + + /* But bigger bitmaps aren't: */ + fake_props.mbw_pbm_bits = 33; + KUNIT_EXPECT_FALSE(test, mba_class_use_mbw_part(&fake_props)); + + fake_props.mbw_pbm_bits = 4; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 25); /* DIV_ROUND_UP(100, 4)% = 25% */ + + fake_props.mbw_pbm_bits = 6; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 17); /* DIV_ROUND_UP(100, 6)% = 7% */ + + /* Largest bitmap size that the drivers supports, for now: */ + fake_props.mbw_pbm_bits = 32; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 4); /* DIV_ROUND_UP(100, 32)% = 4% */ + + /* Use MBW_MAX */ + bitmap_zero(fake_props.features, MPAM_FEATURE_LAST); + fake_props.mbw_pbm_bits = 0; + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + + fake_props.bwa_wd = 0; + KUNIT_EXPECT_FALSE(test, mba_class_use_mbw_max(&fake_props)); + + fake_props.bwa_wd = 1; + KUNIT_EXPECT_TRUE(test, mba_class_use_mbw_max(&fake_props)); + + /* Architectural maximum: */ + fake_props.bwa_wd = 16; + KUNIT_EXPECT_TRUE(test, mba_class_use_mbw_max(&fake_props)); + + /* No usable control... */ + fake_props.bwa_wd = 0; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 0); + + fake_props.bwa_wd = 1; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 50); /* DIV_ROUND_UP(100, 1 << 1)% = 50% */ + + fake_props.bwa_wd = 2; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 25); /* DIV_ROUND_UP(100, 1 << 2)% = 25% */ + + fake_props.bwa_wd = 3; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 13); /* DIV_ROUND_UP(100, 1 << 3)% = 13% */ + + fake_props.bwa_wd = 6; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 2); /* DIV_ROUND_UP(100, 1 << 6)% = 2% */ + + fake_props.bwa_wd = 7; + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 1); /* DIV_ROUND_UP(100, 1 << 7)% = 1% */ + + /* Granularity saturates at 1% */ + fake_props.bwa_wd = 16; /* architectural maximum */ + ret = get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 1); /* DIV_ROUND_UP(100, 1 << 16)% = 1% */ +} + +static void test_mbw_pbm_to_percent(struct kunit *test) +{ + int ret; + struct mpam_props fake_props = {0}; + + mpam_set_feature(mpam_feat_mbw_part, &fake_props); + fake_props.mbw_pbm_bits = 4; + + ret = mbw_pbm_to_percent(0x0, &fake_props); + KUNIT_EXPECT_EQ(test, ret, 0); + + ret = mbw_pbm_to_percent(0x3, &fake_props); + KUNIT_EXPECT_EQ(test, ret, 50); + + ret = mbw_pbm_to_percent(0x7, &fake_props); + KUNIT_EXPECT_EQ(test, ret, 75); + + fake_props.mbw_pbm_bits = 16; + ret = mbw_pbm_to_percent(0xffff, &fake_props); + KUNIT_EXPECT_EQ(test, ret, 100); + + fake_props.mbw_pbm_bits = 0; + ret = mbw_pbm_to_percent(0xff, &fake_props); + KUNIT_EXPECT_EQ(test, ret, 0); +} + +static void test_fract16_to_percent(struct kunit *test) +{ + const struct percent_value_case *param = test->param_value; + struct percent_value_test_info res; + + /* + * Since the reference values in percent_value_cases[] all + * correspond to exact percentages, round-to-nearest will + * always give the exact percentage back when the MPAM max + * value has precision of 0.5% or finer. (Always true for the + * reference data, since they all specify 8 bits or more of + * precision. + * + * So, keep it simple and demand an exact match: + */ + __prepare_percent_value_test(test, &res, param); + KUNIT_EXPECT_EQ(test, res.pc, param->pc); +} + +static void test_percent_to_mbw_pbm(struct kunit *test) +{ + unsigned long ret; + struct mpam_props fake_props = {0}; + + mpam_set_feature(mpam_feat_mbw_part, &fake_props); + fake_props.mbw_pbm_bits = 4; + + ret = percent_to_mbw_pbm(100, &fake_props); + KUNIT_EXPECT_EQ(test, bitmap_weight(&ret, fake_props.mbw_pbm_bits), 4); + + ret = percent_to_mbw_pbm(50, &fake_props); + KUNIT_EXPECT_EQ(test, bitmap_weight(&ret, fake_props.mbw_pbm_bits), 2); + + ret = percent_to_mbw_pbm(0, &fake_props); + KUNIT_EXPECT_EQ(test, bitmap_weight(&ret, fake_props.mbw_pbm_bits), 0); + + fake_props.mbw_pbm_bits = 16; + ret = percent_to_mbw_pbm(100, &fake_props); + KUNIT_EXPECT_EQ(test, bitmap_weight(&ret, fake_props.mbw_pbm_bits), 16); +} + +static void test_percent_to_mbw_max(struct kunit *test) +{ + const struct percent_value_case *param = test->param_value; + struct percent_value_test_info res; + + __prepare_percent_value_test(test, &res, param); + + KUNIT_EXPECT_GE(test, res.value, param->value << res.shift); + KUNIT_EXPECT_LE(test, res.value, (param->value + 1) << res.shift); + KUNIT_EXPECT_LE(test, res.value, res.max_value << res.shift); + + /* No flexibility allowed for 0% and 100%! */ + + if (param->pc == 0) + KUNIT_EXPECT_EQ(test, res.value, 0); + + if (param->pc == 100) + KUNIT_EXPECT_EQ(test, res.value, res.max_value << res.shift); +} + +static const void *test_all_bwa_wd_gen_params(const void *prev, + char *desc) +{ + uintptr_t param = (uintptr_t)prev; + + if (param > 15) + return NULL; + + param++; + + snprintf(desc, KUNIT_PARAM_DESC_SIZE, "wd=%u\n", (unsigned int)param); + + return (void *)param; +} + +static unsigned int test_get_bwa_wd(struct kunit *test) +{ + uintptr_t param = (uintptr_t)test->param_value; + + KUNIT_ASSERT_GE(test, param, 1); + KUNIT_ASSERT_LE(test, param, 16); + + return param; +} + +static void test_mbw_max_to_percent_limits(struct kunit *test) +{ + struct mpam_props fake_props = {0}; + u32 max_value; + + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + fake_props.bwa_wd = test_get_bwa_wd(test); + max_value = GENMASK(15, 16 - fake_props.bwa_wd); + + KUNIT_EXPECT_EQ(test, mbw_max_to_percent(max_value, &fake_props), + MAX_MBA_BW); + KUNIT_EXPECT_EQ(test, mbw_max_to_percent(0, &fake_props), + get_mba_min(&fake_props)); + + /* + * Rounding policy dependent 0% sanity-check: + * With round-to-nearest, the minimum mbw_max value really + * should map to 0% if there are at least 200 steps. + * (100 steps may be enough for some other rounding policies.) + */ + if (fake_props.bwa_wd >= 8) + KUNIT_EXPECT_EQ(test, mbw_max_to_percent(0, &fake_props), 0); + + if (fake_props.bwa_wd < 8 && + mbw_max_to_percent(0, &fake_props) == 0) + kunit_warn(test, "wd=%d: Testsuite/driver Rounding policy mismatch?", + fake_props.bwa_wd); +} + +/* + * Check that converting a percentage to mbw_max and back again (or, as + * appropriate, vice-versa) always restores the original value: + */ +static void test_percent_max_roundtrip_stability(struct kunit *test) +{ + struct mpam_props fake_props = {0}; + unsigned int shift; + u32 pc, max, pc2, max2; + + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + fake_props.bwa_wd = test_get_bwa_wd(test); + shift = 16 - fake_props.bwa_wd; + + /* + * Converting a valid value from the coarser scale to the finer + * scale and back again must yield the original value: + */ + if (fake_props.bwa_wd >= 7) { + /* More than 100 steps: only test exact pc values: */ + for (pc = get_mba_min(&fake_props); pc <= MAX_MBA_BW; pc++) { + max = percent_to_mbw_max(pc, &fake_props); + pc2 = mbw_max_to_percent(max, &fake_props); + KUNIT_EXPECT_EQ(test, pc2, pc); + } + } else { + /* Fewer than 100 steps: only test exact mbw_max values: */ + for (max = 0; max < 1 << 16; max += 1 << shift) { + pc = mbw_max_to_percent(max, &fake_props); + max2 = percent_to_mbw_max(pc, &fake_props); + KUNIT_EXPECT_EQ(test, max2, max); + } + } +} + +static void test_percent_to_max_rounding(struct kunit *test) +{ + const struct percent_value_case *param = test->param_value; + unsigned int num_rounded_up = 0, total = 0; + struct percent_value_test_info res; + + for (param = percent_value_cases, total = 0; + param < &percent_value_cases[ARRAY_SIZE(percent_value_cases)]; + param++, total++) { + __prepare_percent_value_test(test, &res, param); + if (res.value > param->value << res.shift) + num_rounded_up++; + } + + /* + * The MPAM driver applies a round-to-nearest policy, whereas a + * round-down policy seems to have been applied in the + * reference table from which the test vectors were selected. + * + * For a large and well-distributed suite of test vectors, + * about half should be rounded up and half down compared with + * the reference table. The actual test vectors are few in + * number and probably not very well distributed however, so + * tolerate a round-up rate of between 1/4 and 3/4 before + * crying foul: + */ + + kunit_info(test, "Round-up rate: %u%% (%u/%u)\n", + DIV_ROUND_CLOSEST(num_rounded_up * 100, total), + num_rounded_up, total); + + KUNIT_EXPECT_GE(test, 4 * num_rounded_up, 1 * total); + KUNIT_EXPECT_LE(test, 4 * num_rounded_up, 3 * total); +} + +static void test_num_assignable_counters(struct kunit *test) +{ + unsigned int orig_l3_num_allocated_mbwu = l3_num_allocated_mbwu; + u32 orig_mpam_partid_max = mpam_partid_max; + u32 orig_mpam_pmg_max = mpam_pmg_max; + bool orig_cdp_enabled = cdp_enabled; + struct rdt_resource fake_l3; + + /* Force there to be some PARTID/PMG */ + mpam_partid_max = 3; + mpam_pmg_max = 1; + + cdp_enabled = false; + + /* ABMC off, CDP off */ + l3_num_allocated_mbwu = resctrl_arch_system_num_rmid_idx(); + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, resctrl_arch_system_num_rmid_idx()); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* ABMC on, CDP off */ + l3_num_allocated_mbwu = 4; + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, 4); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_assign_on_mkdir); + + cdp_enabled = true; + + /* ABMC off, CDP on */ + l3_num_allocated_mbwu = resctrl_arch_system_num_rmid_idx(); + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + + /* (value not consumed by resctrl) */ + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, resctrl_arch_system_num_rmid_idx() / 2); + + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* ABMC on, CDP on */ + l3_num_allocated_mbwu = 4; + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, 2); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* ABMC 'on', CDP on - but not enough counters */ + l3_num_allocated_mbwu = 1; + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, 0); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* Restore global variables that were messed with */ + l3_num_allocated_mbwu = orig_l3_num_allocated_mbwu; + mpam_partid_max = orig_mpam_partid_max; + mpam_pmg_max = orig_mpam_pmg_max; + cdp_enabled = orig_cdp_enabled; +} + +static struct kunit_case mpam_resctrl_test_cases[] = { + KUNIT_CASE(test_get_mba_granularity), + KUNIT_CASE(test_mbw_pbm_to_percent), + KUNIT_CASE_PARAM(test_fract16_to_percent, test_percent_value_gen_params), + KUNIT_CASE(test_percent_to_mbw_pbm), + KUNIT_CASE_PARAM(test_percent_to_mbw_max, test_percent_value_gen_params), + KUNIT_CASE_PARAM(test_mbw_max_to_percent_limits, test_all_bwa_wd_gen_params), + KUNIT_CASE(test_percent_to_max_rounding), + KUNIT_CASE_PARAM(test_percent_max_roundtrip_stability, + test_all_bwa_wd_gen_params), + KUNIT_CASE(test_num_assignable_counters), + {} +}; + +static struct kunit_suite mpam_resctrl_test_suite = { + .name = "mpam_resctrl_test_suite", + .test_cases = mpam_resctrl_test_cases, +}; + +kunit_test_suites(&mpam_resctrl_test_suite); --- linux-nvidia-7.0.0.orig/drivers/scsi/libsas/sas_scsi_host.c +++ linux-nvidia-7.0.0/drivers/scsi/libsas/sas_scsi_host.c @@ -433,6 +433,9 @@ struct sas_internal *i = to_sas_internal(host->transportt); unsigned long flags; + if (current != host->ehandler) + return FAILED; + if (!i->dft->lldd_abort_task) return FAILED; --- linux-nvidia-7.0.0.orig/drivers/scsi/qla2xxx/qla_attr.c +++ linux-nvidia-7.0.0/drivers/scsi/qla2xxx/qla_attr.c @@ -1638,7 +1638,7 @@ { scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); int rval = QLA_FUNCTION_FAILED; - uint16_t state[6]; + uint16_t state[16]; uint32_t pstate; if (IS_QLAFX00(vha->hw)) { @@ -2402,6 +2402,63 @@ vha->dport_data[0], vha->dport_data[1], vha->dport_data[2], vha->dport_data[3]); } + +static ssize_t +qla2x00_mpi_fw_state_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); + int rval = QLA_FUNCTION_FAILED; + u16 state[16]; + u16 mpi_state; + struct qla_hw_data *ha = vha->hw; + + if (!(IS_QLA27XX(ha) || IS_QLA28XX(ha))) + return scnprintf(buf, PAGE_SIZE, + "MPI state reporting is not supported for this HBA.\n"); + + memset(state, 0, sizeof(state)); + + mutex_lock(&vha->hw->optrom_mutex); + if (qla2x00_chip_is_down(vha)) { + mutex_unlock(&vha->hw->optrom_mutex); + ql_dbg(ql_dbg_user, vha, 0x70df, + "ISP reset is in progress, failing mpi_fw_state.\n"); + return -EBUSY; + } else if (vha->hw->flags.eeh_busy) { + mutex_unlock(&vha->hw->optrom_mutex); + ql_dbg(ql_dbg_user, vha, 0x70ea, + "HBA in PCI error state, failing mpi_fw_state.\n"); + return -EBUSY; + } + + rval = qla2x00_get_firmware_state(vha, state); + mutex_unlock(&vha->hw->optrom_mutex); + if (rval != QLA_SUCCESS) { + ql_dbg(ql_dbg_user, vha, 0x70eb, + "MB Command to retrieve MPI state failed (%d), failing mpi_fw_state.\n", + rval); + return -EIO; + } + + mpi_state = state[11]; + + if (!(mpi_state & BIT_15)) + return scnprintf(buf, PAGE_SIZE, + "MPI firmware state reporting is not supported by this firmware. (0x%02x)\n", + mpi_state); + + if (!(mpi_state & BIT_8)) + return scnprintf(buf, PAGE_SIZE, + "MPI firmware is disabled. (0x%02x)\n", + mpi_state); + + return scnprintf(buf, PAGE_SIZE, + "MPI firmware is enabled, state is %s. (0x%02x)\n", + mpi_state & BIT_9 ? "active" : "inactive", + mpi_state); +} + static DEVICE_ATTR(dport_diagnostics, 0444, qla2x00_dport_diagnostics_show, NULL); @@ -2469,6 +2526,8 @@ qla2x00_port_speed_store); static DEVICE_ATTR(port_no, 0444, qla2x00_port_no_show, NULL); static DEVICE_ATTR(fw_attr, 0444, qla2x00_fw_attr_show, NULL); +static DEVICE_ATTR(mpi_fw_state, 0444, qla2x00_mpi_fw_state_show, NULL); + static struct attribute *qla2x00_host_attrs[] = { &dev_attr_driver_version.attr.attr, @@ -2517,6 +2576,7 @@ &dev_attr_qlini_mode.attr, &dev_attr_ql2xiniexchg.attr, &dev_attr_ql2xexchoffld.attr, + &dev_attr_mpi_fw_state.attr, NULL, }; --- linux-nvidia-7.0.0.orig/drivers/scsi/qla2xxx/qla_init.c +++ linux-nvidia-7.0.0/drivers/scsi/qla2xxx/qla_init.c @@ -4914,7 +4914,7 @@ unsigned long wtime, mtime, cs84xx_time; uint16_t min_wait; /* Minimum wait time if loop is down */ uint16_t wait_time; /* Wait time if loop is coming ready */ - uint16_t state[6]; + uint16_t state[16]; struct qla_hw_data *ha = vha->hw; if (IS_QLAFX00(vha->hw)) --- linux-nvidia-7.0.0.orig/drivers/scsi/qla2xxx/qla_mbx.c +++ linux-nvidia-7.0.0/drivers/scsi/qla2xxx/qla_mbx.c @@ -2268,6 +2268,13 @@ mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; else mcp->in_mb = MBX_1|MBX_0; + + if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { + mcp->mb[12] = 0; + mcp->out_mb |= MBX_12; + mcp->in_mb |= MBX_12; + } + mcp->tov = MBX_TOV_SECONDS; mcp->flags = 0; rval = qla2x00_mailbox_command(vha, mcp); @@ -2280,6 +2287,8 @@ states[3] = mcp->mb[4]; states[4] = mcp->mb[5]; states[5] = mcp->mb[6]; /* DPORT status */ + if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) + states[11] = mcp->mb[12]; /* MPI state. */ } if (rval != QLA_SUCCESS) { --- linux-nvidia-7.0.0.orig/drivers/thunderbolt/tb.c +++ linux-nvidia-7.0.0/drivers/thunderbolt/tb.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "tb.h" #include "tb_regs.h" @@ -18,6 +19,7 @@ #define TB_TIMEOUT 100 /* ms */ #define TB_RELEASE_BW_TIMEOUT 10000 /* ms */ +#define TB_PCIEHP_ENUMERATION_DELAY 300 /* ms */ /* * How many time bandwidth allocation request from graphics driver is @@ -83,6 +85,12 @@ int retry; }; +/* Delayed work to rescan PCIe bus after tunnel activation */ +struct tb_pci_rescan_work { + struct delayed_work work; + struct pci_bus *bus; +}; + static void tb_scan_port(struct tb_port *port); static void tb_handle_hotplug(struct work_struct *work); static void tb_dp_resource_unavailable(struct tb *tb, struct tb_port *port, @@ -90,6 +98,17 @@ static void tb_queue_dp_bandwidth_request(struct tb *tb, u64 route, u8 port, int retry, unsigned long delay); +static void tb_pci_rescan_work_fn(struct work_struct *work) +{ + struct tb_pci_rescan_work *rescan_work = + container_of(work, typeof(*rescan_work), work.work); + + pci_lock_rescan_remove(); + pci_rescan_bus(rescan_work->bus); + pci_unlock_rescan_remove(); + kfree(rescan_work); +} + static void tb_queue_hotplug(struct tb *tb, u64 route, u8 port, bool unplug) { struct tb_hotplug_event *ev; @@ -2313,6 +2332,22 @@ tb_sw_warn(sw, "failed to connect xHCI\n"); list_add_tail(&tunnel->list, &tcm->tunnel_list); + + /* Schedule a delayed PCIe bus rescan in case pciehp misses devices */ + if (tb->nhi && tb->nhi->pdev && tb->nhi->pdev->bus) { + struct pci_bus *bus = tb->nhi->pdev->bus; + struct tb_pci_rescan_work *rescan_work; + + rescan_work = kmalloc(sizeof(*rescan_work), GFP_KERNEL); + if (!rescan_work) + return 0; + + rescan_work->bus = bus->parent ? bus->parent : bus; + INIT_DELAYED_WORK(&rescan_work->work, tb_pci_rescan_work_fn); + queue_delayed_work(tb->wq, &rescan_work->work, + msecs_to_jiffies(TB_PCIEHP_ENUMERATION_DELAY)); + } + return 0; } --- linux-nvidia-7.0.0.orig/drivers/tty/serial/8250/8250_mtk.c +++ linux-nvidia-7.0.0/drivers/tty/serial/8250/8250_mtk.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "8250.h" @@ -521,6 +522,7 @@ struct mtk8250_data *data; struct resource *regs; int irq, err; + struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev); irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -543,12 +545,13 @@ data->clk_count = 0; - if (pdev->dev.of_node) { + if (is_of_node(fwnode)) { err = mtk8250_probe_of(pdev, &uart.port, data); if (err) return err; - } else + } else if (!fwnode) { return -ENODEV; + } spin_lock_init(&uart.port.lock); uart.port.mapbase = regs->start; @@ -564,14 +567,18 @@ uart.port.startup = mtk8250_startup; uart.port.set_termios = mtk8250_set_termios; uart.port.uartclk = clk_get_rate(data->uart_clk); + if (!uart.port.uartclk) + uart.port.uartclk = 26 * HZ_PER_MHZ; #ifdef CONFIG_SERIAL_8250_DMA if (data->dma) uart.dma = data->dma; #endif - /* Disable Rate Fix function */ - writel(0x0, uart.port.membase + + if (is_of_node(fwnode)) { + /* Disable Rate Fix function */ + writel(0x0, uart.port.membase + (MTK_UART_RATE_FIX << uart.port.regshift)); + } platform_set_drvdata(pdev, data); @@ -649,11 +656,18 @@ }; MODULE_DEVICE_TABLE(of, mtk8250_of_match); +static const struct acpi_device_id mtk8250_acpi_match[] = { + { "MTKI0511" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, mtk8250_acpi_match); + static struct platform_driver mtk8250_platform_driver = { .driver = { .name = "mt6577-uart", .pm = &mtk8250_pm_ops, .of_match_table = mtk8250_of_match, + .acpi_match_table = mtk8250_acpi_match, }, .probe = mtk8250_probe, .remove = mtk8250_remove, --- linux-nvidia-7.0.0.orig/drivers/usb/class/cdc-acm.c +++ linux-nvidia-7.0.0/drivers/usb/class/cdc-acm.c @@ -2016,6 +2016,20 @@ /* CH343 supports CAP_BRK, but doesn't advertise it */ { USB_DEVICE(0x1a86, 0x55d3), .driver_info = MISSING_CAP_BRK, }, + /* Exclude Exar USB serial ports */ + { USB_DEVICE(0x04e2, 0x1400), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1401), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1402), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1403), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1410), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1411), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1412), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1414), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1420), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1421), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1422), .driver_info = IGNORE_DEVICE, }, + { USB_DEVICE(0x04e2, 0x1424), .driver_info = IGNORE_DEVICE, }, + /* control interfaces without any protocol set */ { USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_ACM, USB_CDC_PROTO_NONE) }, --- linux-nvidia-7.0.0.orig/drivers/usb/core/hub.c +++ linux-nvidia-7.0.0/drivers/usb/core/hub.c @@ -5603,11 +5603,25 @@ /* When halfway through our retry count, power-cycle the port */ if (i == (PORT_INIT_TRIES - 1) / 2) { + int prr_reset; + dev_info(&port_dev->dev, "attempt power cycle\n"); usb_hub_set_port_power(hdev, hub, port1, false); msleep(2 * hub_power_on_good_delay(hub)); + prr_reset = usb_acpi_port_prr_reset(hdev, port1); usb_hub_set_port_power(hdev, hub, port1, true); msleep(hub_power_on_good_delay(hub)); + /* + * USB 2.0 spec §7.1.7.3 requires at least 100 ms + * between VBUS power-on and the first reset for power + * settling. hub_power_on_good_delay() on an xHCI root + * hub returns bPwrOn2PwrGood * 2 with no minimum floor, + * which can be as little as 20 ms. When _PRR _RST was + * also exercised the device must complete its power-on + * sequence before enumeration; enforce the spec minimum. + */ + if (prr_reset == 0) + msleep(100); } } if (hub->hdev->parent || --- linux-nvidia-7.0.0.orig/drivers/usb/core/usb-acpi.c +++ linux-nvidia-7.0.0/drivers/usb/core/usb-acpi.c @@ -143,6 +143,74 @@ EXPORT_SYMBOL_GPL(usb_acpi_set_power_state); /** + * usb_acpi_port_prr_reset - issue an ACPI _PRR reset on a hub port + * @hdev: USB device belonging to the usb hub + * @port1: port number (one-based) + * + * Some devices expose their hardware reset line via an ACPI Power Resource for + * Reset (_PRR). When such a device fails to enumerate (e.g. because the reset + * GPIO is stuck low), the USB power-cycle alone is not enough; the firmware + * reset path must also be exercised. + * + * This function evaluates _PRR on the port's ACPI companion to obtain the + * power-resource reference and then calls _RST on that resource to toggle the + * reset line. It is intended to be called alongside the mid-retry VBUS + * power-cycle already performed by hub_port_connect(). + * + * Returns 0 on success, -ENODEV if the port has no ACPI handle or no _PRR + * method, or a negative error code on failure. + */ +int usb_acpi_port_prr_reset(struct usb_device *hdev, int port1) +{ + acpi_handle port_handle; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object *pkg, *ref; + acpi_status status; + int ret = 0; + + port_handle = usb_get_hub_port_acpi_handle(hdev, port1); + if (!port_handle) + return -ENODEV; + + if (!acpi_has_method(port_handle, "_PRR")) + return -ENODEV; + + status = acpi_evaluate_object(port_handle, "_PRR", NULL, &buffer); + if (ACPI_FAILURE(status)) { + dev_dbg(&hdev->dev, "port%d: _PRR evaluation failed: %s\n", + port1, acpi_format_exception(status)); + return -ENODEV; + } + + pkg = buffer.pointer; + if (!pkg || pkg->type != ACPI_TYPE_PACKAGE || pkg->package.count < 1) { + dev_dbg(&hdev->dev, "port%d: _PRR returned unexpected object\n", + port1); + ret = -EINVAL; + goto out; + } + + ref = &pkg->package.elements[0]; + if (ref->type != ACPI_TYPE_LOCAL_REFERENCE || !ref->reference.handle) { + dev_dbg(&hdev->dev, "port%d: _PRR element is not a reference\n", + port1); + ret = -EINVAL; + goto out; + } + + status = acpi_evaluate_object(ref->reference.handle, "_RST", NULL, NULL); + if (ACPI_FAILURE(status)) { + dev_dbg(&hdev->dev, "port%d: _RST evaluation failed: %s\n", + port1, acpi_format_exception(status)); + ret = -EIO; + } + +out: + kfree(buffer.pointer); + return ret; +} + +/** * usb_acpi_add_usb4_devlink - add device link to USB4 Host Interface for tunneled USB3 devices * * @udev: Tunneled USB3 device connected to a roothub. --- linux-nvidia-7.0.0.orig/drivers/usb/core/usb.h +++ linux-nvidia-7.0.0/drivers/usb/core/usb.h @@ -211,7 +211,10 @@ extern void usb_acpi_unregister(void); extern acpi_handle usb_get_hub_port_acpi_handle(struct usb_device *hdev, int port1); +extern int usb_acpi_port_prr_reset(struct usb_device *hdev, int port1); #else static inline int usb_acpi_register(void) { return 0; }; static inline void usb_acpi_unregister(void) { }; +static inline int usb_acpi_port_prr_reset(struct usb_device *hdev, + int port1) { return -ENODEV; } #endif --- linux-nvidia-7.0.0.orig/drivers/usb/host/xhci-hub.c +++ linux-nvidia-7.0.0/drivers/usb/host/xhci-hub.c @@ -1290,6 +1290,17 @@ } port_li = readl(&port->port_reg->portli); status = xhci_get_ext_port_status(temp, port_li); + + /* + * In MT8901 USB host controller, the lane count can be wrongly set + * to 2 instead of 1 for USB Gen2x1 devices due to a HW Bug. As a SW + * WAR, check if port speed is 0x5 (SuperSpeedPlus Gen2x1) in + * PORTSC register and update the lane count as 1. + */ + if ((xhci->quirks & XHCI_NVIDIA_MT8901_HOST) && + DEV_SUPERSPEEDPLUS(temp)) + status &= ~0xff00; + put_unaligned_le32(status, &buf[4]); } break; --- linux-nvidia-7.0.0.orig/drivers/usb/host/xhci-plat.c +++ linux-nvidia-7.0.0/drivers/usb/host/xhci-plat.c @@ -277,6 +277,9 @@ if (device_property_read_bool(tmpdev, "xhci-skip-phy-init-quirk")) xhci->quirks |= XHCI_SKIP_PHY_INIT; + if (device_property_read_bool(tmpdev, "xhci-nvidia-mediatek-host")) + xhci->quirks |= XHCI_NVIDIA_MT8901_HOST; + device_property_read_u32(tmpdev, "imod-interval-ns", &xhci->imod_interval); device_property_read_u16(tmpdev, "num-hc-interrupters", --- linux-nvidia-7.0.0.orig/drivers/usb/host/xhci.c +++ linux-nvidia-7.0.0/drivers/usb/host/xhci.c @@ -3732,6 +3732,11 @@ if (ret < 0) goto cleanup; + if (xhci->quirks & XHCI_NVIDIA_MT8901_HOST) { + xhci_hub_control(hcd, SetPortFeature, USB_PORT_FEAT_U1_TIMEOUT, 0, NULL, 0); + xhci_hub_control(hcd, SetPortFeature, USB_PORT_FEAT_U2_TIMEOUT, 0, NULL, 0); + } + spin_lock_irqsave(&xhci->lock, flags); for (i = 0; i < num_eps; i++) { ep_index = xhci_get_endpoint_index(&eps[i]->desc); --- linux-nvidia-7.0.0.orig/drivers/usb/host/xhci.h +++ linux-nvidia-7.0.0/drivers/usb/host/xhci.h @@ -1644,6 +1644,7 @@ #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) #define XHCI_ETRON_HOST BIT_ULL(49) #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50) +#define XHCI_NVIDIA_MT8901_HOST BIT_ULL(51) unsigned int num_active_eps; unsigned int limit_active_eps; --- linux-nvidia-7.0.0.orig/drivers/usb/typec/mux/ps883x.c +++ linux-nvidia-7.0.0/drivers/usb/typec/mux/ps883x.c @@ -340,7 +340,6 @@ struct typec_switch_desc sw_desc = { }; struct typec_retimer_desc rtmr_desc = { }; struct ps883x_retimer *retimer; - unsigned int val; int ret; retimer = devm_kzalloc(dev, sizeof(*retimer), GFP_KERNEL); @@ -410,16 +409,6 @@ /* firmware initialization delay */ msleep(60); - - /* make sure device is accessible */ - ret = regmap_read(retimer->regmap, REG_USB_PORT_CONN_STATUS_0, - &val); - if (ret) { - dev_err(dev, "failed to read conn_status_0: %d\n", ret); - if (ret == -ENXIO) - ret = -EIO; - goto err_clk_disable; - } } sw_desc.drvdata = retimer; --- linux-nvidia-7.0.0.orig/drivers/usb/typec/ucsi/ucsi.c +++ linux-nvidia-7.0.0/drivers/usb/typec/ucsi/ucsi.c @@ -271,10 +271,13 @@ mutex_lock(&con->lock); - if (!con->partner) { - list_del(&uwork->node); + if (!con->partner || !con->wq) { + /* + * Workqueue is being destroyed. Don't free the work item here; + * ucsi_destroy_connector_wq() will handle cleanup to avoid + * use-after-free race. + */ mutex_unlock(&con->lock); - kfree(uwork); return; } @@ -290,13 +293,50 @@ mutex_unlock(&con->lock); } +/** + * ucsi_destroy_connector_wq - Safely destroy connector workqueue + * @con: UCSI connector + * + * Cancel all pending delayed work and destroy the workqueue to prevent + * timer races where delayed work tries to queue on destroyed workqueue. + */ +static void ucsi_destroy_connector_wq(struct ucsi_connector *con) +{ + struct workqueue_struct *wq; + struct ucsi_work *uwork, *tmp; + LIST_HEAD(list); + + if (!con->wq) + return; + + /* + * Prevent new work from being queued and signal existing work to stop. + * Move all work items to a temporary list while holding the lock, + * then cancel them without the lock to avoid deadlock with + * ucsi_poll_worker() which also acquires con->lock. + */ + mutex_lock(&con->lock); + wq = con->wq; + con->wq = NULL; /* Signal workers to stop before canceling */ + list_splice_init(&con->partner_tasks, &list); + mutex_unlock(&con->lock); + + list_for_each_entry_safe(uwork, tmp, &list, node) { + cancel_delayed_work_sync(&uwork->work); + list_del(&uwork->node); + kfree(uwork); + } + + destroy_workqueue(wq); +} + static int ucsi_partner_task(struct ucsi_connector *con, int (*cb)(struct ucsi_connector *), int retries, unsigned long delay) { struct ucsi_work *uwork; - if (!con->partner) + if (!con->partner || !con->wq) return 0; uwork = kzalloc_obj(*uwork); @@ -496,6 +536,73 @@ return ret; } +/* + * Check if an altmode is a duplicate. Some firmware implementations + * incorrectly return the same altmode multiple times, causing sysfs errors. + * Returns true if the altmode should be skipped. + */ +static bool ucsi_altmode_is_duplicate(struct ucsi_connector *con, u8 recipient, + const struct ucsi_altmode *alt_batch, int batch_idx, + u16 svid, u32 vdo, int offset) +{ + struct typec_altmode **altmodes; + const char *recipient_name; + int k; + + /* Check for duplicates within the current batch first */ + for (k = 0; k < batch_idx; k++) { + if (alt_batch[k].svid == svid && alt_batch[k].mid == vdo) { + dev_warn_once(con->ucsi->dev, + "con%d: Firmware bug: duplicate altmode SVID 0x%04x in same response at offset %d, ignoring. Please update your system firmware.\n", + con->num, svid, offset); + return true; + } + } + + /* Check for duplicates in already registered altmodes */ + + switch (recipient) { + case UCSI_RECIPIENT_CON: + altmodes = con->port_altmode; + recipient_name = "port"; + break; + case UCSI_RECIPIENT_SOP: + altmodes = con->partner_altmode; + recipient_name = "partner"; + break; + case UCSI_RECIPIENT_SOP_P: + altmodes = con->plug_altmode; + recipient_name = "plug"; + break; + default: + return false; + } + + for (k = 0; k < UCSI_MAX_ALTMODES; k++) { + if (!altmodes[k]) + break; + + /* Check SVID for all, VDO only for non-SOP */ + if (altmodes[k]->svid != svid) + continue; + if (recipient != UCSI_RECIPIENT_SOP && altmodes[k]->vdo != vdo) + continue; + + if (recipient == UCSI_RECIPIENT_SOP) { + dev_warn(con->ucsi->dev, + "con%d: Firmware bug: duplicate %s altmode SVID 0x%04x (VDO 0x%08x vs 0x%08x) at offset %d, ignoring. Please update your system firmware.\n", + con->num, recipient_name, svid, altmodes[k]->vdo, vdo, offset); + } else { + dev_warn_once(con->ucsi->dev, + "con%d: Firmware bug: duplicate %s altmode SVID 0x%04x at offset %d, ignoring. Please update your system firmware.\n", + con->num, recipient_name, svid, offset); + } + return true; + } + + return false; +} + static int ucsi_register_altmodes_nvidia(struct ucsi_connector *con, u8 recipient) { @@ -550,19 +657,25 @@ /* now register altmodes */ for (i = 0; i < max_altmodes; i++) { - memset(&desc, 0, sizeof(desc)); - if (multi_dp) { - desc.svid = updated[i].svid; - desc.vdo = updated[i].mid; - } else { - desc.svid = orig[i].svid; - desc.vdo = orig[i].mid; - } - desc.roles = TYPEC_PORT_DRD; + struct ucsi_altmode *altmode_array = multi_dp ? updated : orig; - if (!desc.svid) + if (!altmode_array[i].svid) return 0; + /* + * Check for duplicates in current array and already + * registered altmodes. Skip if duplicate found. + */ + if (ucsi_altmode_is_duplicate(con, recipient, altmode_array, i, + altmode_array[i].svid, + altmode_array[i].mid, i)) + continue; + + memset(&desc, 0, sizeof(desc)); + desc.svid = altmode_array[i].svid; + desc.vdo = altmode_array[i].mid; + desc.roles = TYPEC_PORT_DRD; + ret = ucsi_register_altmode(con, &desc, recipient); if (ret) return ret; @@ -620,6 +733,15 @@ if (!alt[j].svid) return 0; + /* + * Check for duplicates in current batch and already + * registered altmodes. Skip if duplicate found. + */ + if (ucsi_altmode_is_duplicate(con, recipient, alt, j, + alt[j].svid, alt[j].mid, + i - num + j)) + continue; + memset(&desc, 0, sizeof(desc)); desc.vdo = alt[j].mid; desc.svid = alt[j].svid; @@ -1778,10 +1900,8 @@ out_unlock: mutex_unlock(&con->lock); - if (ret && con->wq) { - destroy_workqueue(con->wq); - con->wq = NULL; - } + if (ret) + ucsi_destroy_connector_wq(con); return ret; } @@ -1907,8 +2027,7 @@ err_unregister: for (con = connector; con->port; con++) { - if (con->wq) - destroy_workqueue(con->wq); + ucsi_destroy_connector_wq(con); ucsi_unregister_partner(con); ucsi_unregister_altmodes(con, UCSI_RECIPIENT_CON); ucsi_unregister_port_psy(con); @@ -2130,19 +2249,7 @@ for (i = 0; i < ucsi->cap.num_connectors; i++) { cancel_work_sync(&ucsi->connector[i].work); - if (ucsi->connector[i].wq) { - struct ucsi_work *uwork; - - mutex_lock(&ucsi->connector[i].lock); - /* - * queue delayed items immediately so they can execute - * and free themselves before the wq is destroyed - */ - list_for_each_entry(uwork, &ucsi->connector[i].partner_tasks, node) - mod_delayed_work(ucsi->connector[i].wq, &uwork->work, 0); - mutex_unlock(&ucsi->connector[i].lock); - destroy_workqueue(ucsi->connector[i].wq); - } + ucsi_destroy_connector_wq(&ucsi->connector[i]); ucsi_unregister_partner(&ucsi->connector[i]); ucsi_unregister_altmodes(&ucsi->connector[i], --- linux-nvidia-7.0.0.orig/drivers/usb/typec/ucsi/ucsi_yoga_c630.c +++ linux-nvidia-7.0.0/drivers/usb/typec/ucsi/ucsi_yoga_c630.c @@ -137,28 +137,6 @@ return ret; } -static bool yoga_c630_ucsi_update_altmodes(struct ucsi *ucsi, - u8 recipient, - struct ucsi_altmode *orig, - struct ucsi_altmode *updated) -{ - int i; - - if (orig[0].svid == 0 || recipient != UCSI_RECIPIENT_SOP) - return false; - - /* EC is nice and repeats altmodes again and again. Ignore copies. */ - for (i = 1; i < UCSI_MAX_ALTMODES; i++) { - if (orig[i].svid == orig[0].svid) { - dev_dbg(ucsi->dev, "Found duplicate altmodes, starting from %d\n", i); - memset(&orig[i], 0, (UCSI_MAX_ALTMODES - i) * sizeof(*orig)); - break; - } - } - - return false; -} - static void yoga_c630_ucsi_update_connector(struct ucsi_connector *con) { if (con->num == 1) @@ -172,7 +150,6 @@ .read_message_in = yoga_c630_ucsi_read_message_in, .sync_control = yoga_c630_ucsi_sync_control, .async_control = yoga_c630_ucsi_async_control, - .update_altmodes = yoga_c630_ucsi_update_altmodes, .update_connector = yoga_c630_ucsi_update_connector, }; --- linux-nvidia-7.0.0.orig/drivers/vfio/pci/nvgrace-gpu/Kconfig +++ linux-nvidia-7.0.0/drivers/vfio/pci/nvgrace-gpu/Kconfig @@ -1,8 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-only +config NVGRACE_EGM + tristate "EGM driver for NVIDIA Grace Hopper and Blackwell Superchip" + depends on ARM64 || (COMPILE_TEST && 64BIT) + help + Extended GPU Memory (EGM) support for the GPU in the NVIDIA Grace + based chips required to avail the CPU memory as additional + cross-node/cross-socket memory for GPU using KVM/qemu. + + If you don't know what to do here, say N. + config NVGRACE_GPU_VFIO_PCI tristate "VFIO support for the GPU in the NVIDIA Grace Hopper Superchip" depends on ARM64 || (COMPILE_TEST && 64BIT) select VFIO_PCI_CORE + select NVGRACE_EGM help VFIO support for the GPU in the NVIDIA Grace Hopper Superchip is required to assign the GPU device to userspace using KVM/qemu/etc. --- linux-nvidia-7.0.0.orig/drivers/vfio/pci/nvgrace-gpu/Makefile +++ linux-nvidia-7.0.0/drivers/vfio/pci/nvgrace-gpu/Makefile @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_NVGRACE_GPU_VFIO_PCI) += nvgrace-gpu-vfio-pci.o nvgrace-gpu-vfio-pci-y := main.o + +obj-$(CONFIG_NVGRACE_EGM) += nvgrace-egm.o +nvgrace-egm-y := egm.o --- linux-nvidia-7.0.0.orig/drivers/vfio/pci/nvgrace-gpu/egm.c +++ linux-nvidia-7.0.0/drivers/vfio/pci/nvgrace-gpu/egm.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#include +#include +#include +#include +#include +#include + +#define MAX_EGM_NODES 256 + +struct gpu_node { + struct list_head list; + struct pci_dev *pdev; +}; + +struct egm_region { + struct list_head list; + int egmpxm; + atomic_t open_count; + phys_addr_t egmphys; + size_t egmlength; + struct device device; + struct cdev cdev; + struct list_head gpus; + DECLARE_HASHTABLE(htbl, 0x10); + struct pfn_address_space pfn_address_space; +}; + +struct h_node { + unsigned long mem_offset; + struct hlist_node node; +}; + +static dev_t dev; +static struct class *class; +static struct list_head egm_list; + +static int pfn_memregion_offset(struct egm_region *region, + unsigned long pfn, + pgoff_t *pfn_offset_in_region) +{ + unsigned long start_pfn, num_pages; + + start_pfn = PHYS_PFN(region->egmphys); + num_pages = region->egmlength >> PAGE_SHIFT; + + if (pfn < start_pfn || pfn >= start_pfn + num_pages) + return -EFAULT; + + *pfn_offset_in_region = pfn - start_pfn; + + return 0; +} + +static int track_ecc_offset(struct egm_region *region, + unsigned long mem_offset) +{ + struct h_node *cur_page, *ecc_page; + unsigned long bkt; + + hash_for_each(region->htbl, bkt, cur_page, node) { + if (cur_page->mem_offset == mem_offset) + return 0; + } + + ecc_page = (struct h_node *)(vzalloc(sizeof(struct h_node))); + if (!ecc_page) + return -ENOMEM; + + ecc_page->mem_offset = mem_offset; + + hash_add(region->htbl, &ecc_page->node, ecc_page->mem_offset); + + return 0; +} + +static int nvgrace_egm_pfn_to_vma_pgoff(struct vm_area_struct *vma, + unsigned long pfn, + pgoff_t *pgoff) +{ + struct egm_region *region = vma->vm_file->private_data; + pgoff_t vma_offset_in_region = vma->vm_pgoff & + ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); + pgoff_t pfn_offset_in_region; + int ret; + + ret = pfn_memregion_offset(region, pfn, &pfn_offset_in_region); + if (ret) + return ret; + + /* Ensure PFN is not before VMA's start within the region */ + if (pfn_offset_in_region < vma_offset_in_region) + return -EFAULT; + + /* Calculate offset from VMA start */ + *pgoff = vma->vm_pgoff + + (pfn_offset_in_region - vma_offset_in_region); + + /* Track and save the poisoned offset */ + return track_ecc_offset(region, *pgoff << PAGE_SHIFT); +} + +static int +nvgrace_egm_vfio_pci_register_pfn_range(struct inode *inode, + struct egm_region *region) +{ + int ret; + unsigned long pfn, nr_pages; + + pfn = PHYS_PFN(region->egmphys); + nr_pages = region->egmlength >> PAGE_SHIFT; + + region->pfn_address_space.node.start = pfn; + region->pfn_address_space.node.last = pfn + nr_pages - 1; + region->pfn_address_space.mapping = inode->i_mapping; + region->pfn_address_space.pfn_to_vma_pgoff = nvgrace_egm_pfn_to_vma_pgoff; + + ret = register_pfn_address_space(®ion->pfn_address_space); + + return ret; +} + +static int nvgrace_egm_open(struct inode *inode, struct file *file) +{ + void *memaddr; + struct egm_region *region = container_of(inode->i_cdev, + struct egm_region, cdev); + int ret; + + if (!region) + return -EINVAL; + + if (atomic_inc_return(®ion->open_count) > 1) + return 0; + + memaddr = memremap(region->egmphys, region->egmlength, MEMREMAP_WB); + if (!memaddr) { + atomic_dec(®ion->open_count); + return -EINVAL; + } + + { + size_t remaining = region->egmlength; + u8 *chunk_addr = (u8 *)memaddr; + size_t chunk_size; + + while (remaining > 0) { + chunk_size = min(remaining, SZ_1G); + memset(chunk_addr, 0, chunk_size); + cond_resched(); + chunk_addr += chunk_size; + remaining -= chunk_size; + } + } + + memunmap(memaddr); + file->private_data = region; + + ret = nvgrace_egm_vfio_pci_register_pfn_range(inode, region); + if (ret && ret != -EOPNOTSUPP) { + file->private_data = NULL; + return ret; + } + + return 0; +} + +static int nvgrace_egm_release(struct inode *inode, struct file *file) +{ + struct egm_region *region = container_of(inode->i_cdev, + struct egm_region, cdev); + + if (!region) + return -EINVAL; + + if (atomic_dec_and_test(®ion->open_count)) { + unregister_pfn_address_space(®ion->pfn_address_space); + + file->private_data = NULL; + } + + return 0; +} + +static int nvgrace_egm_mmap(struct file *file, struct vm_area_struct *vma) +{ + int ret = 0; + struct egm_region *region = file->private_data; + + if (!region) + return -EINVAL; + + ret = remap_pfn_range(vma, vma->vm_start, + PHYS_PFN(region->egmphys), + (vma->vm_end - vma->vm_start), + vma->vm_page_prot); + return ret; +} + +static long nvgrace_egm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + unsigned long minsz = offsetofend(struct egm_bad_pages_list, count); + struct egm_bad_pages_list info; + void __user *uarg = (void __user *)arg; + struct egm_region *region = file->private_data; + + if (copy_from_user(&info, uarg, minsz)) + return -EFAULT; + + if (info.argsz < minsz) + return -EINVAL; + + if (!region) + return -EINVAL; + + switch (cmd) { + case EGM_BAD_PAGES_LIST: + { + int ret; + unsigned long bad_page_struct_size = sizeof(struct egm_bad_pages_info); + struct egm_bad_pages_info tmp; + struct h_node *cur_page; + struct hlist_node *tmp_node; + unsigned long bkt; + int count = 0, index = 0; + + hash_for_each_safe(region->htbl, bkt, tmp_node, cur_page, node) + count++; + + if (info.argsz < (minsz + count * bad_page_struct_size)) { + info.argsz = minsz + count * bad_page_struct_size; + info.count = 0; + goto done; + } else { + hash_for_each_safe(region->htbl, bkt, tmp_node, cur_page, node) { + /* + * This check fails if there was an ECC error + * after the usermode app read the count of + * bad pages through this ioctl. + */ + if (minsz + index * bad_page_struct_size >= info.argsz) { + info.argsz = minsz + index * bad_page_struct_size; + info.count = index; + goto done; + } + + tmp.offset = cur_page->mem_offset; + tmp.size = PAGE_SIZE; + + ret = copy_to_user(uarg + minsz + + index * bad_page_struct_size, + &tmp, bad_page_struct_size); + if (ret) + return ret; + index++; + } + + info.count = index; + } + break; + } + default: + return -EINVAL; + } + +done: + return copy_to_user(uarg, &info, minsz) ? -EFAULT : 0; +} + +static const struct file_operations file_ops = { + .owner = THIS_MODULE, + .open = nvgrace_egm_open, + .release = nvgrace_egm_release, + .mmap = nvgrace_egm_mmap, + .unlocked_ioctl = nvgrace_egm_ioctl, +}; + +static int setup_egm_chardev(struct egm_region *region) +{ + int ret = 0; + + device_initialize(®ion->device); + + /* + * Use the proximity domain number as the device minor + * number. So the EGM corresponding to node X would be + * /dev/egmX. + */ + region->device.devt = MKDEV(MAJOR(dev), region->egmpxm); + region->device.class = class; + cdev_init(®ion->cdev, &file_ops); + region->cdev.owner = THIS_MODULE; + + ret = dev_set_name(®ion->device, "egm%d", region->egmpxm); + if (ret) + return ret; + + ret = cdev_device_add(®ion->cdev, ®ion->device); + + return ret; +} + +static void destroy_egm_chardev(struct egm_region *region) +{ + cdev_device_del(®ion->cdev, ®ion->device); +} + +static int +nvgrace_gpu_fetch_egm_property(struct pci_dev *pdev, u64 *pegmphys, + u64 *pegmlength, u64 *pegmpxm) +{ + int ret; + + /* + * The memory information is present in the system ACPI tables as DSD + * properties nvidia,egm-base-pa and nvidia,egmm-size. + */ + ret = device_property_read_u64(&pdev->dev, "nvidia,egm-size", + pegmlength); + if (ret) + return ret; + + if (*pegmlength > type_max(size_t)) + return -EOVERFLOW; + + ret = device_property_read_u64(&pdev->dev, "nvidia,egm-base-pa", + pegmphys); + if (ret) + return ret; + + if (*pegmphys > type_max(phys_addr_t)) + return -EOVERFLOW; + + ret = device_property_read_u64(&pdev->dev, "nvidia,egm-pxm", + pegmpxm); + if (ret) + return ret; + + if (*pegmpxm > type_max(phys_addr_t)) + return -EOVERFLOW; + + return 0; +} + +static void nvgrace_egm_fetch_bad_pages(struct pci_dev *pdev, + struct egm_region *region) +{ + u64 retiredpagesphys, count; + void *memaddr; + int index; + + if (device_property_read_u64(&pdev->dev, + "nvidia,egm-retired-pages-data-base", + &retiredpagesphys)) + return; + + /* Catch firmware bug and avoid a crash */ + if (WARN_ON_ONCE(retiredpagesphys == 0)) + return; + + memaddr = memremap(retiredpagesphys, PAGE_SIZE, MEMREMAP_WB); + if (!memaddr) + return; + + count = *(u64 *)memaddr; + + for (index = 0; index < count; index++) { + struct h_node *retired_page; + + /* + * Since the EGM is linearly mapped, the offset in the + * carveout is the same offset in the VM system memory. + * + * Calculate the offset to communicate to the usermode + * apps. + */ + retired_page = (struct h_node *)(vzalloc(sizeof(struct h_node))); + retired_page->mem_offset = *((u64 *)memaddr + index + 1) - + region->egmphys; + hash_add(region->htbl, &retired_page->node, retired_page->mem_offset); + } + + memunmap(memaddr); +} + +static ssize_t gpu_devices_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct egm_region *region = + container_of(dev, struct egm_region, device); + struct gpu_node *node, *temp_node; + int len = 0; + + list_for_each_entry_safe(node, temp_node, ®ion->gpus, list) { + struct pci_dev *pdev = node->pdev; + + len += sysfs_emit_at(buf, len, "%04x:%02x:%02x.%x\n", + pci_domain_nr(pdev->bus), + pdev->bus->number, + PCI_SLOT(pdev->devfn), + PCI_FUNC(pdev->devfn)); + } + + return len; +} + +static DEVICE_ATTR_RO(gpu_devices); + +static ssize_t egm_size_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct egm_region *region = + container_of(dev, struct egm_region, device); + return sysfs_emit(buf, "0x%lx\n", region->egmlength); +} + +static DEVICE_ATTR_RO(egm_size); + +static struct attribute *attrs[] = { + &dev_attr_gpu_devices.attr, + &dev_attr_egm_size.attr, + NULL, +}; + +static struct attribute_group attr_group = { + .attrs = attrs, +}; + +static int add_gpu(struct egm_region *region, struct pci_dev *pdev) +{ + struct gpu_node *node; + + node = kvzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->pdev = pdev; + + list_add_tail(&node->list, ®ion->gpus); + return 0; +} + +static void remove_gpu(struct egm_region *region, struct pci_dev *pdev) +{ + struct gpu_node *node, *tmp; + + list_for_each_entry_safe(node, tmp, ®ion->gpus, list) { + if (node->pdev == pdev) { + list_del(&node->list); + kvfree(node); + } + } +} + +int register_egm_node(struct pci_dev *pdev) +{ + struct egm_region *region = NULL; + u64 egmphys, egmlength, egmpxm; + int ret; + + ret = nvgrace_gpu_fetch_egm_property(pdev, &egmphys, &egmlength, &egmpxm); + if (ret) + return ret; + + /* Check if region already exists */ + list_for_each_entry(region, &egm_list, list) { + if (region->egmphys == egmphys) { + /* Add GPU to existing region */ + return add_gpu(region, pdev); + } + } + + /* Create new region */ + region = kvzalloc(sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + + region->egmphys = egmphys; + region->egmlength = egmlength; + region->egmpxm = egmpxm; + + hash_init(region->htbl); + INIT_LIST_HEAD(®ion->gpus); + + atomic_set(®ion->open_count, 0); + + nvgrace_egm_fetch_bad_pages(pdev, region); + + ret = setup_egm_chardev(region); + if (ret) + goto err_free_region; + + list_add_tail(®ion->list, &egm_list); + + ret = sysfs_create_group(®ion->device.kobj, &attr_group); + if (ret) + goto err_remove_from_list; + + ret = add_gpu(region, pdev); + if (ret) + goto err_remove_sysfs; + + return 0; + +err_remove_sysfs: + sysfs_remove_group(®ion->device.kobj, &attr_group); +err_remove_from_list: + list_del(®ion->list); + destroy_egm_chardev(region); +err_free_region: + kfree(region); + return ret; +} +EXPORT_SYMBOL_GPL(register_egm_node); + +void unregister_egm_node(struct pci_dev *pdev) +{ + struct egm_region *region, *temp_region; + struct h_node *cur_page; + unsigned long bkt; + struct hlist_node *temp_node; + u64 egmphys, egmlength, egmpxm; + int ret; + + ret = nvgrace_gpu_fetch_egm_property(pdev, &egmphys, &egmlength, &egmpxm); + if (ret) + return; + + list_for_each_entry_safe(region, temp_region, &egm_list, list) { + if (egmpxm == region->egmpxm) { + remove_gpu(region, pdev); + if (!list_empty(®ion->gpus)) + break; + + hash_for_each_safe(region->htbl, bkt, temp_node, cur_page, node) { + hash_del(&cur_page->node); + vfree(cur_page); + } + + sysfs_remove_group(®ion->device.kobj, &attr_group); + destroy_egm_chardev(region); + list_del(®ion->list); + kfree(region); + } + } +} +EXPORT_SYMBOL_GPL(unregister_egm_node); + +static char *egm_devnode(const struct device *device, umode_t *mode) +{ + if (mode) + *mode = 0600; + + return NULL; +} + +static int __init nvgrace_egm_init(void) +{ + int ret; + + ret = alloc_chrdev_region(&dev, + 0, MAX_EGM_NODES, "egm"); + if (ret < 0) + return ret; + + class = class_create("egm"); + if (IS_ERR(class)) { + unregister_chrdev_region(dev, MAX_EGM_NODES); + return PTR_ERR(class); + } + + class->devnode = egm_devnode; + + INIT_LIST_HEAD(&egm_list); + + return 0; +} + +static void __exit nvgrace_egm_cleanup(void) +{ + class_destroy(class); + unregister_chrdev_region(dev, MAX_EGM_NODES); +} + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ankit Agrawal "); +MODULE_DESCRIPTION("NVGRACE EGM - Helper module of NVGRACE GPU to support Extended GPU Memory"); + +module_init(nvgrace_egm_init); +module_exit(nvgrace_egm_cleanup); --- linux-nvidia-7.0.0.orig/drivers/vfio/pci/nvgrace-gpu/main.c +++ linux-nvidia-7.0.0/drivers/vfio/pci/nvgrace-gpu/main.c @@ -10,6 +10,7 @@ #include #include #include +#include /* * The device memory usable to the workloads running in the VM is cached @@ -64,8 +65,11 @@ bool has_mig_hw_bug; /* GPU has just been reset */ bool reset_done; + int egm_node; }; +static bool egm_enabled; + static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vdev) { struct nvgrace_gpu_pci_core_device *nvdev = @@ -991,7 +995,7 @@ if (ret) return ret; - if (*pmemphys > type_max(phys_addr_t)) + if (overflows_type(*pmemphys, phys_addr_t)) return -EOVERFLOW; ret = device_property_read_u64(&pdev->dev, "nvidia,gpu-mem-size", @@ -999,7 +1003,7 @@ if (ret) return ret; - if (*pmemlength > type_max(size_t)) + if (overflows_type(*pmemlength, size_t)) return -EOVERFLOW; /* @@ -1013,6 +1017,13 @@ } static int +nvgrace_gpu_has_egm_property(struct pci_dev *pdev, u64 *pegmpxm) +{ + return device_property_read_u64(&pdev->dev, "nvidia,egm-pxm", + pegmpxm); +} + +static int nvgrace_gpu_init_nvdev_struct(struct pci_dev *pdev, struct nvgrace_gpu_pci_core_device *nvdev, u64 memphys, u64 memlength) @@ -1181,6 +1192,7 @@ const struct vfio_device_ops *ops = &nvgrace_gpu_pci_core_ops; struct nvgrace_gpu_pci_core_device *nvdev; u64 memphys, memlength; + u64 egmpxm; int ret; ret = nvgrace_gpu_probe_check_device_ready(pdev); @@ -1188,9 +1200,14 @@ return ret; ret = nvgrace_gpu_fetch_memory_property(pdev, &memphys, &memlength); - if (!ret) + if (!ret) { ops = &nvgrace_gpu_pci_ops; + ret = nvgrace_gpu_has_egm_property(pdev, &egmpxm); + if (!ret) + egm_enabled = true; + } + nvdev = vfio_alloc_device(nvgrace_gpu_pci_core_device, core_device.vdev, &pdev->dev, ops); if (IS_ERR(nvdev)) @@ -1210,16 +1227,28 @@ if (ret) goto out_put_vdev; nvdev->core_device.pci_ops = &nvgrace_gpu_pci_dev_ops; + + if (egm_enabled) { + ret = register_egm_node(pdev); + if (ret) + goto out_put_vdev; + + nvdev->egm_node = egmpxm; + } + } else { nvdev->core_device.pci_ops = &nvgrace_gpu_pci_dev_core_ops; } ret = vfio_pci_core_register_device(&nvdev->core_device); if (ret) - goto out_put_vdev; + goto out_egm_unreg; return ret; +out_egm_unreg: + if (egm_enabled) + unregister_egm_node(pdev); out_put_vdev: vfio_put_device(&nvdev->core_device.vdev); return ret; @@ -1228,6 +1257,12 @@ static void nvgrace_gpu_remove(struct pci_dev *pdev) { struct vfio_pci_core_device *core_device = dev_get_drvdata(&pdev->dev); + struct nvgrace_gpu_pci_core_device *nvdev = + container_of(core_device, struct nvgrace_gpu_pci_core_device, + core_device); + + if (egm_enabled) + unregister_egm_node(pdev); vfio_pci_core_unregister_device(core_device); vfio_put_device(&core_device->vdev); --- linux-nvidia-7.0.0.orig/fs/ceph/mdsmap.c +++ linux-nvidia-7.0.0/fs/ceph/mdsmap.c @@ -13,6 +13,7 @@ #include "mdsmap.h" #include "mds_client.h" #include "super.h" +#include "mdsmap.h" #define CEPH_MDS_IS_READY(i, ignore_laggy) \ (m->m_info[i].state > 0 && ignore_laggy ? true : !m->m_info[i].laggy) --- linux-nvidia-7.0.0.orig/fs/debugfs/file.c +++ linux-nvidia-7.0.0/fs/debugfs/file.c @@ -1140,6 +1140,70 @@ &fops_str_ro, &fops_str_wo); } +static ssize_t debugfs_read_file_cpumask(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct dentry *dentry = F_DENTRY(file); + struct cpumask *cpumask; + char *kernel_buf; + ssize_t ret; + int len; + + ret = debugfs_file_get(dentry); + if (unlikely(ret)) + return ret; + + /* How long is a piece of string? */ + kernel_buf = kmalloc(PAGE_SIZE, GFP_KERNEL); + if (!kernel_buf) { + debugfs_file_put(dentry); + return -ENOMEM; + } + + cpumask = (struct cpumask *)file->private_data; + len = scnprintf(kernel_buf, PAGE_SIZE, + "%*pb\n", cpumask_pr_args(cpumask)); + debugfs_file_put(dentry); + if (len + 1 >= PAGE_SIZE) { + kfree(kernel_buf); + return -EIO; + } + + ret = simple_read_from_buffer(user_buf, count, ppos, kernel_buf, len); + kfree(kernel_buf); + + return ret; +} + +static const struct file_operations fops_cpumask_ro = { + .read = debugfs_read_file_cpumask, + .open = simple_open, + .llseek = default_llseek, +}; + +/** + * debugfs_create_cpumask - create a read-only debugfs file that is used to read a cpumask + * @name: a pointer to a string containing the name of the file to create. + * @mode: the permission that the file should have + * @parent: a pointer to the parent dentry for this file. This should be a + * directory dentry if set. If this parameter is %NULL, then the + * file will be created in the root of the debugfs filesystem. + * @value: a pointer to the variable that the file should read from. + * + * This function creates a file in debugfs with the given name that + * contains the value of the variable @value. + */ +void debugfs_create_cpumask(const char *name, umode_t mode, + struct dentry *parent, struct cpumask *value) +{ + /* Only read-only is supported */ + WARN_ON_ONCE(mode & S_IWUGO); + + debugfs_create_mode_unsafe(name, mode, parent, value, &fops_cpumask_ro, + &fops_cpumask_ro, &fops_cpumask_ro); +} + static ssize_t read_file_blob(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { --- linux-nvidia-7.0.0.orig/fs/file.c +++ linux-nvidia-7.0.0/fs/file.c @@ -887,6 +887,7 @@ return file; } +EXPORT_SYMBOL(file_close_fd); void do_close_on_exec(struct files_struct *files) { --- linux-nvidia-7.0.0.orig/fs/namei.c +++ linux-nvidia-7.0.0/fs/namei.c @@ -1196,8 +1196,8 @@ path_put(&last->link); } -static int sysctl_protected_symlinks __read_mostly; -static int sysctl_protected_hardlinks __read_mostly; +static int sysctl_protected_symlinks __read_mostly = 1; +static int sysctl_protected_hardlinks __read_mostly = 1; static int sysctl_protected_fifos __read_mostly; static int sysctl_protected_regular __read_mostly; --- linux-nvidia-7.0.0.orig/fs/overlayfs/params.c +++ linux-nvidia-7.0.0/fs/overlayfs/params.c @@ -55,6 +55,7 @@ Opt_uuid, Opt_nfs_export, Opt_userxattr, + Opt_nouserxattr, Opt_xino, Opt_metacopy, Opt_verity, @@ -170,6 +171,7 @@ fsparam_enum("uuid", Opt_uuid, ovl_parameter_uuid), fsparam_enum("nfs_export", Opt_nfs_export, ovl_parameter_bool), fsparam_flag("userxattr", Opt_userxattr), + fsparam_flag("nouserxattr", Opt_nouserxattr), fsparam_enum("xino", Opt_xino, ovl_parameter_xino), fsparam_enum("metacopy", Opt_metacopy, ovl_parameter_bool), fsparam_enum("verity", Opt_verity, ovl_parameter_verity), @@ -716,6 +718,9 @@ put_cred(cred); break; } + case Opt_nouserxattr: + config->userxattr = false; + break; default: pr_err("unrecognized mount option \"%s\" or missing value\n", param->key); @@ -823,6 +828,8 @@ ofs->config.xino = ovl_xino_def(); ofs->config.metacopy = ovl_metacopy_def; ofs->config.fsync_mode = ovl_fsync_mode_def(); + if (fc->user_ns != &init_user_ns) + ofs->config.userxattr = true; fc->s_fs_info = ofs; fc->fs_private = ctx; @@ -1097,6 +1104,8 @@ seq_printf(m, ",fsync=%s", ovl_fsync_mode(&ofs->config)); if (ofs->config.userxattr) seq_puts(m, ",userxattr"); + else + seq_puts(m, ",nouserxattr"); if (ofs->config.verity_mode != ovl_verity_mode_def()) seq_printf(m, ",verity=%s", ovl_verity_mode(&ofs->config)); --- linux-nvidia-7.0.0.orig/fs/proc/Makefile +++ linux-nvidia-7.0.0/fs/proc/Makefile @@ -33,4 +33,4 @@ proc-$(CONFIG_PROC_VMCORE) += vmcore.o proc-$(CONFIG_PRINTK) += kmsg.o proc-$(CONFIG_PROC_PAGE_MONITOR) += page.o -proc-$(CONFIG_BOOT_CONFIG) += bootconfig.o +proc-$(CONFIG_BOOT_CONFIG) += bootconfig.o version_signature.o --- linux-nvidia-7.0.0.orig/fs/proc/version_signature.c +++ linux-nvidia-7.0.0/fs/proc/version_signature.c @@ -0,0 +1,32 @@ +#include +#include +#include +#include +#include +#include +#include + +static int version_signature_proc_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%s\n", CONFIG_VERSION_SIGNATURE); + return 0; +} + +static int version_signature_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, version_signature_proc_show, NULL); +} + +static const struct proc_ops version_signature_proc_fops = { + .proc_open = version_signature_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, +}; + +static int __init proc_version_signature_init(void) +{ + proc_create("version_signature", 0, NULL, &version_signature_proc_fops); + return 0; +} +module_init(proc_version_signature_init); --- linux-nvidia-7.0.0.orig/fs/resctrl/Kconfig +++ linux-nvidia-7.0.0/fs/resctrl/Kconfig @@ -37,3 +37,9 @@ Enabled by the architecture when the RMID values depend on the CLOSID. This causes the CLOSID allocator to search for CLOSID with clean RMID. + +config RESCTRL_IOMMU + bool + help + Enabled by the architecture when some IOMMU are able to be configured + with CLOSID/RMID. --- linux-nvidia-7.0.0.orig/fs/resctrl/ctrlmondata.c +++ linux-nvidia-7.0.0/fs/resctrl/ctrlmondata.c @@ -40,19 +40,11 @@ * hardware. The allocated bandwidth percentage is rounded to the next * control step available on the hardware. */ -static bool bw_validate(char *buf, u32 *data, struct rdt_resource *r) +static bool bw_validate(char *buf, u32 *data, struct resctrl_schema *s) { int ret; u32 bw; - /* - * Only linear delay values is supported for current Intel SKUs. - */ - if (!r->membw.delay_linear && r->membw.arch_needs_linear) { - rdt_last_cmd_puts("No support for non-linear MB domains\n"); - return false; - } - ret = kstrtou32(buf, 10, &bw); if (ret) { rdt_last_cmd_printf("Invalid MB value %s\n", buf); @@ -60,18 +52,18 @@ } /* Nothing else to do if software controller is enabled. */ - if (is_mba_sc(r)) { + if (is_mba_sc(s->res)) { *data = bw; return true; } - if (bw < r->membw.min_bw || bw > r->membw.max_bw) { + if (bw < s->membw.min_bw || bw > s->membw.max_bw) { rdt_last_cmd_printf("MB value %u out of range [%d,%d]\n", - bw, r->membw.min_bw, r->membw.max_bw); + bw, s->membw.min_bw, s->membw.max_bw); return false; } - *data = roundup(bw, (unsigned long)r->membw.bw_gran); + *data = resctrl_arch_round_bw(bw, s); return true; } @@ -83,13 +75,7 @@ u32 closid = data->closid; u32 bw_val; - cfg = &d->staged_config[s->conf_type]; - if (cfg->have_new_ctrl) { - rdt_last_cmd_printf("Duplicate domain %d\n", d->hdr.id); - return -EINVAL; - } - - if (!bw_validate(data->buf, &bw_val, r)) + if (!bw_validate(data->buf, &bw_val, s)) return -EINVAL; if (is_mba_sc(r)) { @@ -97,6 +83,7 @@ return 0; } + cfg = &d->staged_config[s->conf_type]; cfg->new_ctrl = bw_val; cfg->have_new_ctrl = true; @@ -164,12 +151,6 @@ u32 closid = data->closid; u32 cbm_val; - cfg = &d->staged_config[s->conf_type]; - if (cfg->have_new_ctrl) { - rdt_last_cmd_printf("Duplicate domain %d\n", d->hdr.id); - return -EINVAL; - } - /* * Cannot set up more than one pseudo-locked region in a cache * hierarchy. @@ -206,6 +187,7 @@ } } + cfg = &d->staged_config[s->conf_type]; cfg->new_ctrl = cbm_val; cfg->have_new_ctrl = true; @@ -233,11 +215,13 @@ /* Walking r->domains, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); - switch (r->schema_fmt) { + switch (s->schema_fmt) { case RESCTRL_SCHEMA_BITMAP: parse_ctrlval = &parse_cbm; break; - case RESCTRL_SCHEMA_RANGE: + case RESCTRL_SCHEMA_PERCENT: + case RESCTRL_SCHEMA_MBPS: + case RESCTRL_SCHEMA__AMD_MBA: parse_ctrlval = &parse_bw; break; } @@ -251,6 +235,15 @@ return -EINVAL; } + /* + * Only linear delay values is supported for current Intel SKUs. + */ + if (r->rid == RDT_RESOURCE_MBA && + !r->mba.delay_linear && r->mba.arch_needs_linear) { + rdt_last_cmd_puts("No support for non-linear MB domains\n"); + return -EINVAL; + } + next: if (!line || line[0] == '\0') return 0; @@ -263,13 +256,18 @@ dom = strim(dom); list_for_each_entry(d, &r->ctrl_domains, hdr.list) { if (d->hdr.id == dom_id) { + cfg = &d->staged_config[t]; + if (cfg->have_new_ctrl) { + rdt_last_cmd_printf("Duplicate domain %d\n", d->hdr.id); + return -EINVAL; + } + data.buf = dom; data.closid = rdtgrp->closid; data.mode = rdtgrp->mode; if (parse_ctrlval(&data, s, d)) return -EINVAL; if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP) { - cfg = &d->staged_config[t]; /* * In pseudo-locking setup mode and just * parsed a valid CBM that should be --- linux-nvidia-7.0.0.orig/fs/resctrl/internal.h +++ linux-nvidia-7.0.0/fs/resctrl/internal.h @@ -42,6 +42,8 @@ bool enable_cdpl3; bool enable_mba_mbps; bool enable_debug; + bool mb_uses_numa_nid; + bool enable_abi_playground; }; static inline struct rdt_fs_context *rdt_fc2context(struct fs_context *fc) @@ -251,8 +253,8 @@ #define RFTYPE_TOP BIT(6) +/* files that are specific to a type of resource, e.g. throttle_mode */ #define RFTYPE_RES_CACHE BIT(8) - #define RFTYPE_RES_MB BIT(9) #define RFTYPE_DEBUG BIT(10) @@ -261,6 +263,11 @@ #define RFTYPE_RES_PERF_PKG BIT(12) +/* files that are specific to a type of control, e.g. percent_min */ +#define RFTYPE_SCHEMA_BITMAP BIT(13) +#define RFTYPE_SCHEMA_PERCENT BIT(14) +#define RFTYPE_SCHEMA_MBPS BIT(15) + #define RFTYPE_CTRL_INFO (RFTYPE_INFO | RFTYPE_CTRL) #define RFTYPE_MON_INFO (RFTYPE_INFO | RFTYPE_MON) @@ -314,6 +321,8 @@ u32 prev_bw; }; +DECLARE_STATIC_KEY_FALSE(resctrl_abi_playground); + extern struct mutex rdtgroup_mutex; static inline const char *rdt_kn_name(const struct kernfs_node *kn) --- linux-nvidia-7.0.0.orig/fs/resctrl/monitor.c +++ linux-nvidia-7.0.0/fs/resctrl/monitor.c @@ -18,6 +18,7 @@ #define pr_fmt(fmt) "resctrl: " fmt #include +#include #include #include #include @@ -98,12 +99,17 @@ * * The domain's rmid_busy_llc and rmid_ptrs[] are sized by index. The arch code * must accept an attempt to read every index. + * + * Returns NULL if the rmid_ptrs[] array is not allocated. */ static inline struct rmid_entry *__rmid_entry(u32 idx) { struct rmid_entry *entry; u32 closid, rmid; + if (!rmid_ptrs) + return NULL; + entry = &rmid_ptrs[idx]; resctrl_arch_rmid_idx_decode(idx, &closid, &rmid); @@ -113,6 +119,20 @@ return entry; } +static bool __has_closid_num_dirty_rmid_array(void) +{ + lockdep_assert_held(&rdtgroup_mutex); + + if (!IS_ENABLED(CONFIG_RESCTRL_RMID_DEPENDS_ON_CLOSID)) + return false; + + /* + * Avoid a race with dom_data_exit() freeing the array under + * rdtgroup_mutex. + */ + return closid_num_dirty_rmid; +} + static void limbo_release_entry(struct rmid_entry *entry) { lockdep_assert_held(&rdtgroup_mutex); @@ -120,7 +140,7 @@ rmid_limbo_count--; list_add_tail(&entry->list, &rmid_free_lru); - if (IS_ENABLED(CONFIG_RESCTRL_RMID_DEPENDS_ON_CLOSID)) + if (__has_closid_num_dirty_rmid_array()) closid_num_dirty_rmid[entry->closid]--; } @@ -161,6 +181,8 @@ break; entry = __rmid_entry(idx); + if (!entry) + break; if (resctrl_arch_rmid_read(r, &d->hdr, entry->closid, entry->rmid, QOS_L3_OCCUP_EVENT_ID, arch_priv, &val, arch_mon_ctx)) { @@ -242,7 +264,7 @@ lockdep_assert_held(&rdtgroup_mutex); - if (!IS_ENABLED(CONFIG_RESCTRL_RMID_DEPENDS_ON_CLOSID)) + if (!__has_closid_num_dirty_rmid_array()) return -EIO; for (i = 0; i < closids_supported(); i++) { @@ -315,7 +337,7 @@ } rmid_limbo_count++; - if (IS_ENABLED(CONFIG_RESCTRL_RMID_DEPENDS_ON_CLOSID)) + if (__has_closid_num_dirty_rmid_array()) closid_num_dirty_rmid[entry->closid]++; } @@ -326,6 +348,10 @@ lockdep_assert_held(&rdtgroup_mutex); + /* rmid_ptrs[] not allocated if there are no monitors */ + if (!resctrl_arch_mon_capable()) + return; + /* * Do not allow the default rmid to be free'd. Comparing by index * allows architectures that ignore the closid parameter to avoid an @@ -337,6 +363,8 @@ return; entry = __rmid_entry(idx); + if (!entry) + return; if (resctrl_is_mon_event_enabled(QOS_L3_OCCUP_EVENT_ID)) add_rmid_to_limbo(entry); @@ -793,6 +821,7 @@ struct rdt_l3_mon_domain *d; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); d = container_of(work, struct rdt_l3_mon_domain, cqm_limbo.work); @@ -807,6 +836,7 @@ } mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); } @@ -840,6 +870,7 @@ struct rdt_resource *r; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); /* @@ -873,6 +904,7 @@ out_unlock: mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); } @@ -893,8 +925,10 @@ /* * When a domain comes online there is no guarantee the filesystem is * mounted. If not, there is no need to catch counter overflow. + * Some architecture may have ~64bit counters, and can ignore overflow. */ - if (!resctrl_mounted || !resctrl_arch_mon_capable()) + if (!resctrl_mounted || !resctrl_arch_mon_capable() || + !resctrl_arch_mon_can_overflow()) return; cpu = cpumask_any_housekeeping(&dom->hdr.cpu_mask, exclude_cpu); dom->mbm_work_cpu = cpu; @@ -943,6 +977,7 @@ idx = resctrl_arch_rmid_idx_encode(RESCTRL_RESERVED_CLOSID, RESCTRL_RESERVED_RMID); entry = __rmid_entry(idx); + WARN_ON_ONCE(!entry); list_del(&entry->list); return 0; --- linux-nvidia-7.0.0.orig/fs/resctrl/pseudo_lock.c +++ linux-nvidia-7.0.0/fs/resctrl/pseudo_lock.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -694,6 +695,7 @@ int ret = -1; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); if (rdtgrp->flags & RDT_DELETED) { @@ -741,6 +743,7 @@ out: mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); return ret; } --- linux-nvidia-7.0.0.orig/fs/resctrl/rdtgroup.c +++ linux-nvidia-7.0.0/fs/resctrl/rdtgroup.c @@ -16,8 +16,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -87,6 +89,9 @@ static bool resctrl_debug; +/* Enable wacky behaviour that is not supported upstream. */ +DEFINE_STATIC_KEY_FALSE(resctrl_abi_playground); + void rdt_last_cmd_clear(void) { lockdep_assert_held(&rdtgroup_mutex); @@ -766,10 +771,65 @@ return ret; } +static int rdtgroup_move_iommu(int iommu_group_id, struct rdtgroup *rdtgrp, + struct kernfs_open_file *of) +{ + const struct cred *cred = current_cred(); + struct iommu_group *iommu_group; + int err; + + if (!uid_eq(cred->euid, GLOBAL_ROOT_UID)) { + rdt_last_cmd_printf("No permission to move iommu_group %d\n", + iommu_group_id); + return -EPERM; + } + + iommu_group = iommu_group_get_by_id(iommu_group_id); + if (!iommu_group) { + rdt_last_cmd_printf("No matching iommu_group %d\n", + iommu_group_id); + return -ESRCH; + } + + if (rdtgrp->type == RDTMON_GROUP && + !resctrl_arch_match_iommu_closid(iommu_group, + rdtgrp->mon.parent->closid)) { + rdt_last_cmd_puts("Can't move iommu_group to different control group\n"); + err = -EINVAL; + } else { + err = resctrl_arch_set_iommu_closid_rmid(iommu_group, + rdtgrp->closid, + rdtgrp->mon.rmid); + } + + iommu_group_put(iommu_group); + + return err; +} + +static bool string_is_iommu_group(char *buf, int *val) +{ + if (!IS_ENABLED(CONFIG_RESCTRL_IOMMU) || + !static_branch_unlikely(&resctrl_abi_playground)) + return false; + + if (strlen(buf) <= strlen("iommu_group:")) + return false; + + if (strncmp(buf, "iommu_group:", strlen("iommu_group:"))) + return false; + + buf += strlen("iommu_group:"); + + return !kstrtoint(buf, 0, val); +} + static ssize_t rdtgroup_tasks_write(struct kernfs_open_file *of, char *buf, size_t nbytes, loff_t off) { struct rdtgroup *rdtgrp; + int iommu_group_id; + bool is_iommu; char *pid_str; int ret = 0; pid_t pid; @@ -791,7 +851,10 @@ while (buf && buf[0] != '\0' && buf[0] != '\n') { pid_str = strim(strsep(&buf, ",")); - if (kstrtoint(pid_str, 0, &pid)) { + is_iommu = string_is_iommu_group(pid_str, &iommu_group_id); + if (is_iommu) + ret = rdtgroup_move_iommu(iommu_group_id, rdtgrp, of); + else if (kstrtoint(pid_str, 0, &pid)) { rdt_last_cmd_printf("Task list parsing error pid %s\n", pid_str); ret = -EINVAL; break; @@ -816,6 +879,42 @@ return ret ?: nbytes; } +static bool iommu_matches_rdtgroup(struct iommu_group *group, struct rdtgroup *r) +{ + if (r->type == RDTCTRL_GROUP) + return resctrl_arch_match_iommu_closid(group, r->closid); + + return resctrl_arch_match_iommu_closid_rmid(group, r->closid, + r->mon.rmid); +} + +static void show_rdt_iommu(struct rdtgroup *r, struct seq_file *s) +{ + struct kset *iommu_groups; + struct iommu_group *group; + struct kobject *group_kobj = NULL; + + if (!IS_ENABLED(CONFIG_RESCTRL_IOMMU) || + !static_branch_unlikely(&resctrl_abi_playground)) + return; + + iommu_groups = iommu_get_group_kset(); + + while ((group_kobj = kset_get_next_obj(iommu_groups, group_kobj))) { + /* iommu_group_get_from_kobj() wants to drop a reference */ + kobject_get(group_kobj); + + group = iommu_group_get_from_kobj(group_kobj); + if (!group) + continue; + + if (iommu_matches_rdtgroup(group, r)) + seq_printf(s, "iommu_group:%s\n", group_kobj->name); + } + + kset_put(iommu_groups); +} + static void show_rdt_tasks(struct rdtgroup *r, struct seq_file *s) { struct task_struct *p, *t; @@ -830,6 +929,8 @@ } } rcu_read_unlock(); + + show_rdt_iommu(r, s); } static int rdtgroup_tasks_show(struct kernfs_open_file *of, @@ -1004,9 +1105,8 @@ struct seq_file *seq, void *v) { struct resctrl_schema *s = rdt_kn_parent_priv(of->kn); - struct rdt_resource *r = s->res; - seq_printf(seq, "%x\n", resctrl_get_default_ctrl(r)); + seq_printf(seq, "%x\n", resctrl_get_schema_default_ctrl(s)); return 0; } @@ -1062,6 +1162,7 @@ u32 ctrl_val; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); list_for_each_entry(dom, &r->ctrl_domains, hdr.list) { if (sep) @@ -1139,6 +1240,7 @@ } seq_putc(seq, '\n'); mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); return 0; } @@ -1147,9 +1249,8 @@ struct seq_file *seq, void *v) { struct resctrl_schema *s = rdt_kn_parent_priv(of->kn); - struct rdt_resource *r = s->res; - seq_printf(seq, "%u\n", r->membw.min_bw); + seq_printf(seq, "%u\n", s->membw.min_bw); return 0; } @@ -1185,9 +1286,8 @@ struct seq_file *seq, void *v) { struct resctrl_schema *s = rdt_kn_parent_priv(of->kn); - struct rdt_resource *r = s->res; - seq_printf(seq, "%u\n", r->membw.bw_gran); + seq_printf(seq, "%u\n", s->membw.bw_gran); return 0; } @@ -1197,7 +1297,7 @@ struct resctrl_schema *s = rdt_kn_parent_priv(of->kn); struct rdt_resource *r = s->res; - seq_printf(seq, "%u\n", r->membw.delay_linear); + seq_printf(seq, "%u\n", r->mba.delay_linear); return 0; } @@ -1215,7 +1315,7 @@ struct resctrl_schema *s = rdt_kn_parent_priv(of->kn); struct rdt_resource *r = s->res; - switch (r->membw.throttle_mode) { + switch (r->mba.throttle_mode) { case THREAD_THROTTLE_PER_THREAD: seq_puts(seq, "per-thread\n"); return 0; @@ -1527,7 +1627,7 @@ struct cacheinfo *ci; int num_b; - if (WARN_ON_ONCE(r->ctrl_scope != RESCTRL_L2_CACHE && r->ctrl_scope != RESCTRL_L3_CACHE)) + if (WARN_ON_ONCE(r->schema_fmt != RESCTRL_SCHEMA_BITMAP)) return size; num_b = bitmap_weight(&cbm, r->cache.cbm_len); @@ -1550,7 +1650,7 @@ if (r->rid != RDT_RESOURCE_MBA) return false; - return r->membw.mba_sc; + return r->mba.mba_sc; } /* @@ -1614,11 +1714,11 @@ ctrl = resctrl_arch_get_config(r, d, closid, type); - if (r->rid == RDT_RESOURCE_MBA || - r->rid == RDT_RESOURCE_SMBA) - size = ctrl; - else + + if (schema->schema_fmt == RESCTRL_SCHEMA_BITMAP) size = rdtgroup_cbm_to_size(r, d, ctrl); + else + size = ctrl; } seq_printf(s, "%d=%u", d->hdr.id, size); sep = true; @@ -1645,6 +1745,7 @@ bool sep = false; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); list_for_each_entry(dom, &r->mon_domains, hdr.list) { @@ -1663,6 +1764,7 @@ seq_puts(s, "\n"); mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); return 0; @@ -1688,6 +1790,30 @@ return 0; } +static int resctrl_schema_format_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s = rdt_kn_parent_priv(of->kn); + + switch (s->schema_fmt) { + case RESCTRL_SCHEMA_BITMAP: + seq_puts(seq, "bitmap\n"); + break; + case RESCTRL_SCHEMA_PERCENT: + seq_puts(seq, "percentage\n"); + break; + case RESCTRL_SCHEMA_MBPS: + seq_puts(seq, "mbps\n"); + break; + /* The way these schema behave isn't discoverable from resctrl */ + case RESCTRL_SCHEMA__AMD_MBA: + seq_puts(seq, "platform\n"); + break; + } + + return 0; +} + static void mbm_config_write_domain(struct rdt_resource *r, struct rdt_l3_mon_domain *d, u32 evtid, u32 val) { @@ -1783,6 +1909,7 @@ return -EINVAL; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); rdt_last_cmd_clear(); @@ -1792,6 +1919,7 @@ ret = mon_config_write(r, buf, QOS_L3_MBM_TOTAL_EVENT_ID); mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); return ret ?: nbytes; @@ -1809,6 +1937,7 @@ return -EINVAL; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); rdt_last_cmd_clear(); @@ -1818,6 +1947,7 @@ ret = mon_config_write(r, buf, QOS_L3_MBM_LOCAL_EVENT_ID); mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); return ret ?: nbytes; @@ -1930,6 +2060,13 @@ .seq_show = resctrl_num_mbm_cntrs_show, }, { + .name = "bitmap_mask", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdt_default_ctrl_show, + .fflags = RFTYPE_CTRL_INFO | RFTYPE_SCHEMA_BITMAP, + }, + { .name = "min_cbm_bits", .mode = 0444, .kf_ops = &rdtgroup_kf_single_ops, @@ -1937,6 +2074,13 @@ .fflags = RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE, }, { + .name = "bitmaps_min_bits", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdt_min_cbm_bits_show, + .fflags = RFTYPE_CTRL_INFO | RFTYPE_SCHEMA_BITMAP, + }, + { .name = "shareable_bits", .mode = 0444, .kf_ops = &rdtgroup_kf_single_ops, @@ -1958,6 +2102,13 @@ .fflags = RFTYPE_CTRL_INFO | RFTYPE_RES_MB, }, { + .name = "percent_min", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdt_min_bw_show, + .fflags = RFTYPE_CTRL_INFO | RFTYPE_SCHEMA_PERCENT, + }, + { .name = "bandwidth_gran", .mode = 0444, .kf_ops = &rdtgroup_kf_single_ops, @@ -1965,6 +2116,13 @@ .fflags = RFTYPE_CTRL_INFO | RFTYPE_RES_MB, }, { + .name = "percent_gran", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdt_bw_gran_show, + .fflags = RFTYPE_CTRL_INFO | RFTYPE_SCHEMA_PERCENT, + }, + { .name = "delay_linear", .mode = 0444, .kf_ops = &rdtgroup_kf_single_ops, @@ -2116,6 +2274,14 @@ .seq_show = rdtgroup_closid_show, .fflags = RFTYPE_CTRL_BASE | RFTYPE_DEBUG, }, + { + .name = "schema_format", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = resctrl_schema_format_show, + .fflags = RFTYPE_CTRL_INFO, + }, + }; static int rdtgroup_add_files(struct kernfs_node *kn, unsigned long fflags) @@ -2172,13 +2338,13 @@ r_mba = resctrl_arch_get_resource(RDT_RESOURCE_MBA); if (r_mba->alloc_capable && - r_mba->membw.throttle_mode != THREAD_THROTTLE_UNDEFINED) - throttle_mode = r_mba->membw.throttle_mode; + r_mba->mba.throttle_mode != THREAD_THROTTLE_UNDEFINED) + throttle_mode = r_mba->mba.throttle_mode; r_smba = resctrl_arch_get_resource(RDT_RESOURCE_SMBA); if (r_smba->alloc_capable && - r_smba->membw.throttle_mode != THREAD_THROTTLE_UNDEFINED) - throttle_mode = r_smba->membw.throttle_mode; + r_smba->mba.throttle_mode != THREAD_THROTTLE_UNDEFINED) + throttle_mode = r_smba->mba.throttle_mode; if (throttle_mode == THREAD_THROTTLE_UNDEFINED) return; @@ -2400,7 +2566,35 @@ return RFTYPE_RES_PERF_PKG; } - return WARN_ON_ONCE(1); + return 0; +} + +static u32 fflags_from_schema(struct resctrl_schema *s) +{ + struct rdt_resource *r = s->res; + u32 fflags = 0; + + /* Some resources are configured purely from their rid */ + fflags |= fflags_from_resource(r); + if (fflags) + return fflags; + + switch (s->schema_fmt) { + case RESCTRL_SCHEMA_BITMAP: + fflags |= RFTYPE_SCHEMA_BITMAP; + break; + case RESCTRL_SCHEMA_PERCENT: + fflags |= RFTYPE_SCHEMA_PERCENT; + break; + case RESCTRL_SCHEMA_MBPS: + fflags |= RFTYPE_SCHEMA_MBPS; + break; + case RESCTRL_SCHEMA__AMD_MBA: + /* No standard files are exposed */ + break; + } + + return fflags; } static int rdtgroup_create_info_dir(struct kernfs_node *parent_kn) @@ -2423,7 +2617,7 @@ /* loop over enabled controls, these are all alloc_capable */ list_for_each_entry(s, &resctrl_schema_all, list) { r = s->res; - fflags = fflags_from_resource(r) | RFTYPE_CTRL_INFO; + fflags = fflags_from_schema(s) | RFTYPE_CTRL_INFO; ret = rdtgroup_mkdir_info_resdir(s, s->name, fflags); if (ret) goto out_destroy; @@ -2480,7 +2674,7 @@ static inline bool is_mba_linear(void) { - return resctrl_arch_get_resource(RDT_RESOURCE_MBA)->membw.delay_linear; + return resctrl_arch_get_resource(RDT_RESOURCE_MBA)->mba.delay_linear; } static int mba_sc_domain_allocate(struct rdt_resource *r, struct rdt_ctrl_domain *d) @@ -2538,7 +2732,7 @@ if (!supports_mba_mbps() || mba_sc == is_mba_sc(r)) return -EINVAL; - r->membw.mba_sc = mba_sc; + r->mba.mba_sc = mba_sc; rdtgroup_default.mba_mbps_event = mba_mbps_default_event; @@ -2610,6 +2804,7 @@ rdtgroup_kn_get(rdtgrp, kn); cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); /* Was this group deleted while we waited? */ @@ -2627,6 +2822,7 @@ return; mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); rdtgroup_kn_put(rdtgrp, kn); @@ -2640,6 +2836,7 @@ { resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L3, false); resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L2, false); + resctrl_arch_set_mb_uses_numa_nid(false); set_mba_sc(false); resctrl_debug = false; @@ -2670,8 +2867,17 @@ if (ctx->enable_debug) resctrl_debug = true; + if (ctx->mb_uses_numa_nid) { + ret = resctrl_arch_set_mb_uses_numa_nid(true); + if (ret) + goto out_debug; + } + return 0; +out_debug: + resctrl_debug = false; + set_mba_sc(false); out_cdpl3: resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L3, false); out_cdpl2: @@ -2727,11 +2933,28 @@ if (cl > max_name_width) max_name_width = cl; - switch (r->schema_fmt) { + s->schema_fmt = r->schema_fmt; + s->membw = r->membw; + + /* + * When mba_sc() is enabled the format used by user space is different + * to that expected by hardware. The conversion is done by + * update_mba_bw(). + */ + if (is_mba_sc(r)) { + s->schema_fmt = RESCTRL_SCHEMA_MBPS; + s->membw.min_bw = 0; + s->membw.max_bw = MBA_MAX_MBPS; + s->membw.bw_gran = 1; + } + + switch (s->schema_fmt) { case RESCTRL_SCHEMA_BITMAP: s->fmt_str = "%d=%x"; break; - case RESCTRL_SCHEMA_RANGE: + case RESCTRL_SCHEMA_PERCENT: + case RESCTRL_SCHEMA_MBPS: + case RESCTRL_SCHEMA__AMD_MBA: s->fmt_str = "%d=%u"; break; } @@ -2780,6 +3003,42 @@ } } +static void hack_file_mode(const char *name, u16 mode) +{ + struct rftype *rfts, *rft; + int len; + + mutex_lock(&rdtgroup_mutex); + + rfts = res_common_files; + len = ARRAY_SIZE(res_common_files); + + for (rft = rfts; rft < rfts + len; rft++) { + if (!strcmp(rft->name, name)) + rft->mode = mode; + } + + mutex_unlock(&rdtgroup_mutex); +} + +static void enable_abi_playground(void) +{ + static_key_enable(&resctrl_abi_playground.key); + + /* Make the tasks file read only */ + if (IS_ENABLED(CONFIG_CGROUP_RESCTRL)) + hack_file_mode("tasks", 0444); +} + +static void disable_abi_playground(void) +{ + static_key_disable(&resctrl_abi_playground.key); + + /* Make the tasks file read/write only */ + if (IS_ENABLED(CONFIG_CGROUP_RESCTRL)) + hack_file_mode("tasks", 0644); +} + static int rdt_get_tree(struct fs_context *fc) { struct rdt_fs_context *ctx = rdt_fc2context(fc); @@ -2790,7 +3049,11 @@ DO_ONCE_SLEEPABLE(resctrl_arch_pre_mount); + if (ctx->enable_abi_playground) + enable_abi_playground(); + cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); /* * resctrl file system can only be mounted once. @@ -2896,6 +3159,7 @@ out: rdt_last_cmd_clear(); mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); return ret; } @@ -2905,14 +3169,24 @@ Opt_cdpl2, Opt_mba_mbps, Opt_debug, + Opt_mb_uses_numa_nid, + Opt_not_abi_playground, nr__rdt_params }; static const struct fs_parameter_spec rdt_fs_parameters[] = { - fsparam_flag("cdp", Opt_cdp), - fsparam_flag("cdpl2", Opt_cdpl2), - fsparam_flag("mba_MBps", Opt_mba_mbps), - fsparam_flag("debug", Opt_debug), + fsparam_flag("cdp", Opt_cdp), + fsparam_flag("cdpl2", Opt_cdpl2), + fsparam_flag("mba_MBps", Opt_mba_mbps), + fsparam_flag("debug", Opt_debug), + fsparam_flag("mb_uses_numa_nid", Opt_mb_uses_numa_nid), + + /* + * Some of MPAM's out of tree code exposes things through resctrl + * that need much more discussion before they are considered for + * mainline. Add a mount option that can be used to hide these crimes. + */ + fsparam_flag("this_is_not_abi", Opt_not_abi_playground), {} }; @@ -2943,6 +3217,12 @@ case Opt_debug: ctx->enable_debug = true; return 0; + case Opt_mb_uses_numa_nid: + ctx->mb_uses_numa_nid = true; + return 0; + case Opt_not_abi_playground: + ctx->enable_abi_playground = true; + return 0; } return -EINVAL; @@ -3170,6 +3450,7 @@ struct rdt_resource *r; cpus_read_lock(); + get_online_mems(); mutex_lock(&rdtgroup_mutex); rdt_disable_ctx(); @@ -3186,7 +3467,11 @@ resctrl_mounted = false; kernfs_kill_sb(sb); mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); + + if (static_branch_unlikely(&resctrl_abi_playground)) + disable_abi_playground(); } static struct file_system_type rdt_fs_type = { @@ -3626,7 +3911,7 @@ } cfg = &d->staged_config[CDP_NONE]; - cfg->new_ctrl = resctrl_get_default_ctrl(r); + cfg->new_ctrl = resctrl_get_resource_default_ctrl(r); cfg->have_new_ctrl = true; } } @@ -4237,6 +4522,12 @@ if (resctrl_debug) seq_puts(seq, ",debug"); + if (resctrl_arch_get_mb_uses_numa_nid()) + seq_puts(seq, ",mb_uses_numa_nid"); + + if (static_branch_unlikely(&resctrl_abi_playground)) + seq_puts(seq, ",this_is_not_abi"); + return 0; } @@ -4641,12 +4932,14 @@ void resctrl_exit(void) { cpus_read_lock(); + get_online_mems(); WARN_ON_ONCE(resctrl_online_domains_exist()); mutex_lock(&rdtgroup_mutex); resctrl_fs_teardown(); mutex_unlock(&rdtgroup_mutex); + put_online_mems(); cpus_read_unlock(); debugfs_remove_recursive(debugfs_resctrl); --- linux-nvidia-7.0.0.orig/include/acpi/cppc_acpi.h +++ linux-nvidia-7.0.0/include/acpi/cppc_acpi.h @@ -151,6 +151,7 @@ extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); +extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); @@ -173,6 +174,12 @@ extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window); extern int cppc_get_auto_sel(int cpu, bool *enable); extern int cppc_set_auto_sel(int cpu, bool enable); +extern int cppc_get_min_perf(int cpu, u64 *min_perf); +extern int cppc_set_min_perf(int cpu, u64 min_perf); +extern int cppc_get_max_perf(int cpu, u64 *max_perf); +extern int cppc_set_max_perf(int cpu, u64 max_perf); +extern int cppc_get_perf_limited(int cpu, u64 *perf_limited); +extern int cppc_set_perf_limited(int cpu, u64 perf_limited); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -193,6 +200,10 @@ { return -EOPNOTSUPP; } +static inline int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + return -EOPNOTSUPP; +} static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) { return -EOPNOTSUPP; @@ -265,6 +276,30 @@ { return -EOPNOTSUPP; } +static inline int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_min_perf(int cpu, u64 min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_max_perf(int cpu, u64 max_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_perf_limited(int cpu, u64 perf_limited) +{ + return -EOPNOTSUPP; +} static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) { return -ENODEV; --- linux-nvidia-7.0.0.orig/include/asm-generic/mshyperv.h +++ linux-nvidia-7.0.0/include/asm-generic/mshyperv.h @@ -165,6 +165,14 @@ input, output); } +#ifndef PKG_ABI +/* + * Preserve the ability to 'make deb-pkg' since PKG_ABI is provided + * by the Ubuntu build rules. + */ +#define PKG_ABI 0 +#endif + /* Generate the guest OS identifier as described in the Hyper-V TLFS */ static inline u64 hv_generate_guest_id(u64 kernel_version) { @@ -172,6 +180,7 @@ guest_id = (((u64)HV_LINUX_VENDOR_ID) << 48); guest_id |= (kernel_version << 16); + guest_id |= PKG_ABI; return guest_id; } --- linux-nvidia-7.0.0.orig/include/drm/drm_connector.h +++ linux-nvidia-7.0.0/include/drm/drm_connector.h @@ -2493,6 +2493,7 @@ u32 scaling_mode_mask); int drm_connector_attach_vrr_capable_property( struct drm_connector *connector); +void drm_connector_attach_panel_type_property(struct drm_connector *connector); int drm_connector_attach_broadcast_rgb_property(struct drm_connector *connector); int drm_connector_attach_colorspace_property(struct drm_connector *connector); int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); --- linux-nvidia-7.0.0.orig/include/drm/drm_mode_config.h +++ linux-nvidia-7.0.0/include/drm/drm_mode_config.h @@ -601,6 +601,10 @@ */ struct drm_property *tile_property; /** + * @panel_type_property: Default connector property for panel type + */ + struct drm_property *panel_type_property; + /** * @link_status_property: Default connector property for link status * of a connector */ --- linux-nvidia-7.0.0.orig/include/hyperv/hvgdk.h +++ linux-nvidia-7.0.0/include/hyperv/hvgdk.h @@ -27,7 +27,7 @@ * 15:0 - Distro specific identification */ -#define HV_LINUX_VENDOR_ID 0x8100 +#define HV_LINUX_VENDOR_ID 0x80 /* Canonical */ /* HV_VMX_ENLIGHTENED_VMCS */ struct hv_enlightened_vmcs { --- linux-nvidia-7.0.0.orig/include/linux/acpi.h +++ linux-nvidia-7.0.0/include/linux/acpi.h @@ -1596,10 +1596,26 @@ void **region_ctxt); extern int acpi_ffh_address_space_arch_handler(acpi_integer *value, void *region_context); +int acpi_ffh_address_space_arch_update_custom_offset_handler( + int (*handler)(struct acpi_ffh_info *info, acpi_integer *value, + void *region_context)); #else static inline void acpi_init_ffh(void) { } #endif +#if defined(CONFIG_ACPI_FFH) && defined(CONFIG_ARM64) +int acpi_arm64_ffh_update_custom_offset_handler( + int (*handler)(struct acpi_ffh_info *info, acpi_integer *value, + void *region_context)); +#else +static inline int acpi_arm64_ffh_update_custom_offset_handler( + int (*handler)(struct acpi_ffh_info *info, acpi_integer *value, + void *region_context)) +{ + return -EOPNOTSUPP; +} +#endif + #ifdef CONFIG_ACPI extern void acpi_device_notify(struct device *dev); extern void acpi_device_notify_remove(struct device *dev); --- linux-nvidia-7.0.0.orig/include/linux/arm_mpam.h +++ linux-nvidia-7.0.0/include/linux/arm_mpam.h @@ -5,6 +5,8 @@ #define __LINUX_ARM_MPAM_H #include +#include +#include #include struct mpam_msc; @@ -12,6 +14,7 @@ enum mpam_msc_iface { MPAM_IFACE_MMIO, /* a real MPAM MSC */ MPAM_IFACE_PCC, /* a fake MPAM MSC */ + MPAM_IFACE_SCMI, /* through a firmware interface */ }; enum mpam_class_types { @@ -39,16 +42,62 @@ #ifdef CONFIG_ARM64_MPAM_DRIVER int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, - enum mpam_class_types type, u8 class_id, int component_id); + enum mpam_class_types type, u8 class_id, u32 component_id); #else static inline int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, enum mpam_class_types type, u8 class_id, - int component_id) + u32 component_id) { return -EINVAL; } #endif +struct resctrl_schema; +static inline u32 resctrl_arch_round_bw(u32 val, + const struct resctrl_schema *s __always_unused) +{ + /* + * Do nothing: for MPAM, resctrl_arch_update_one() has the necessary + * context to round the incoming value correctly. + */ + return val; +} + +static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) +{ + return val; +} + +bool resctrl_arch_alloc_capable(void); +bool resctrl_arch_mon_capable(void); +bool resctrl_arch_mon_can_overflow(void); + +void resctrl_arch_set_cpu_default_closid(int cpu, u32 closid); +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32 rmid); +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmid); +void resctrl_arch_sched_in(struct task_struct *tsk); +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid); +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid); +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid); +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid); +u32 resctrl_arch_system_num_rmid_idx(void); + +struct rdt_resource; +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, enum resctrl_event_id evtid); +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_id evtid, void *ctx); + +bool resctrl_arch_get_mb_uses_numa_nid(void); +int resctrl_arch_set_mb_uses_numa_nid(bool enabled); + +/* + * The CPU configuration for MPAM is cheap to write, and is only written if it + * has changed. No need for fine grained enables. + */ +static inline void resctrl_arch_enable_mon(void) { } +static inline void resctrl_arch_disable_mon(void) { } +static inline void resctrl_arch_enable_alloc(void) { } +static inline void resctrl_arch_disable_alloc(void) { } + /** * mpam_register_requestor() - Register a requestor with the MPAM driver * @partid_max: The maximum PARTID value the requestor can generate. --- linux-nvidia-7.0.0.orig/include/linux/cacheinfo.h +++ linux-nvidia-7.0.0/include/linux/cacheinfo.h @@ -112,6 +112,7 @@ #endif const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf); +u32 cache_of_calculate_id(struct device_node *np); /* * Get the cacheinfo structure for the cache associated with @cpu at @@ -147,6 +148,21 @@ return ci ? ci->id : -1; } +/** + * get_cpu_cacheinfo_size() - Get the size of the cache. + * @cpu: The cpu that is associated with the cache. + * @level: The level of the cache as seen by @cpu. + * + * cpuhp lock must be held. + * Returns the cache-size on success, or 0 for an error. + */ +static inline unsigned int get_cpu_cacheinfo_size(int cpu, int level) +{ + struct cacheinfo *ci = get_cpu_cacheinfo_level(cpu, level); + + return ci ? ci->size : 0; +} + #if defined(CONFIG_ARM64) || defined(CONFIG_ARM) #define use_arch_cache_info() (true) #else --- linux-nvidia-7.0.0.orig/include/linux/debugfs.h +++ linux-nvidia-7.0.0/include/linux/debugfs.h @@ -202,6 +202,8 @@ bool *value); void debugfs_create_str(const char *name, umode_t mode, struct dentry *parent, char **value); +void debugfs_create_cpumask(const char *name, umode_t mode, + struct dentry *parent, struct cpumask *value); struct dentry *debugfs_create_blob(const char *name, umode_t mode, struct dentry *parent, @@ -407,6 +409,10 @@ char **value) { } +static inline void debugfs_create_cpumask(const char *name, umode_t mode, + struct dentry *parent, struct cpumask *value) +{ } + static inline struct dentry *debugfs_create_blob(const char *name, umode_t mode, struct dentry *parent, struct debugfs_blob_wrapper *blob) --- linux-nvidia-7.0.0.orig/include/linux/efi.h +++ linux-nvidia-7.0.0/include/linux/efi.h @@ -45,6 +45,8 @@ #define EFI_ABORTED (21 | (1UL << (BITS_PER_LONG-1))) #define EFI_SECURITY_VIOLATION (26 | (1UL << (BITS_PER_LONG-1))) +#define EFI_IS_ERROR(x) ((x) & (1UL << (BITS_PER_LONG-1))) + typedef unsigned long efi_status_t; typedef u8 efi_bool_t; typedef u16 efi_char16_t; /* UNICODE character */ @@ -868,6 +870,23 @@ #define EFI_MEM_ATTR 9 /* Did firmware publish an EFI_MEMORY_ATTRIBUTES table? */ #define EFI_MEM_NO_SOFT_RESERVE 10 /* Is the kernel configured to ignore soft reservations? */ #define EFI_PRESERVE_BS_REGIONS 11 /* Are EFI boot-services memory segments available? */ +#define EFI_SECURE_BOOT 12 /* Are we in Secure Boot mode? */ + +enum efi_secureboot_mode { + efi_secureboot_mode_unset, + efi_secureboot_mode_unknown, + efi_secureboot_mode_disabled, + efi_secureboot_mode_enabled, +}; + +#ifdef CONFIG_EFI_PARAMS_FROM_FDT +u32 __init efi_get__secure_boot(void); +#else +static inline u32 efi_get__secure_boot(void) +{ + return efi_secureboot_mode_unset; +}; +#endif #ifdef CONFIG_EFI /* @@ -879,6 +898,8 @@ } extern void efi_reboot(enum reboot_mode reboot_mode, const char *__unused); +extern void __init efi_set_secure_boot(enum efi_secureboot_mode mode); + bool __pure __efi_soft_reserve_enabled(void); static inline bool __pure efi_soft_reserve_enabled(void) @@ -900,6 +921,8 @@ static inline void efi_reboot(enum reboot_mode reboot_mode, const char *__unused) {} +static inline void efi_set_secure_boot(enum efi_secureboot_mode mode) {} + static inline bool efi_soft_reserve_enabled(void) { return false; @@ -914,6 +937,7 @@ #endif extern int efi_status_to_err(efi_status_t status); +extern const char *efi_status_to_str(efi_status_t status); /* * Variable Attributes @@ -1131,13 +1155,6 @@ void efi_runtime_assert_lock_held(void); -enum efi_secureboot_mode { - efi_secureboot_mode_unset, - efi_secureboot_mode_unknown, - efi_secureboot_mode_disabled, - efi_secureboot_mode_enabled, -}; - static inline enum efi_secureboot_mode efi_get_secureboot_mode(efi_get_variable_t *get_var) { --- linux-nvidia-7.0.0.orig/include/linux/iommu.h +++ linux-nvidia-7.0.0/include/linux/iommu.h @@ -703,6 +703,12 @@ struct iommu_domain *parent_domain, const struct iommu_user_data *user_data); + /* Per group IOMMU features */ + int (*get_group_qos_params)(struct iommu_group *group, u16 *partition, + u8 *perf_mon_grp); + int (*set_group_qos_params)(struct iommu_group *group, u16 partition, + u8 perf_mon_grp); + const struct iommu_domain_ops *default_domain_ops; struct module *owner; struct iommu_domain *identity_domain; @@ -904,12 +910,15 @@ { return iommu_paging_domain_alloc_flags(dev, 0); } +struct iommu_group *iommu_group_get_from_kobj(struct kobject *group_kobj); +extern struct iommu_group *iommu_group_get_by_id(int id); extern void iommu_domain_free(struct iommu_domain *domain); extern int iommu_attach_device(struct iommu_domain *domain, struct device *dev); extern void iommu_detach_device(struct iommu_domain *domain, struct device *dev); extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); +extern struct iommu_domain *iommu_get_domain_for_group(struct iommu_group *group); struct iommu_domain *iommu_driver_get_domain_for_dev(struct device *dev); extern struct iommu_domain *iommu_get_dma_domain(struct device *dev); extern int iommu_map(struct iommu_domain *domain, unsigned long iova, @@ -961,6 +970,7 @@ extern void iommu_group_put(struct iommu_group *group); extern int iommu_group_id(struct iommu_group *group); +struct kset *iommu_get_group_kset(void); extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *); int iommu_set_pgtable_quirks(struct iommu_domain *domain, @@ -1189,6 +1199,10 @@ struct device *dev, ioasid_t pasid); ioasid_t iommu_alloc_global_pasid(struct device *dev); void iommu_free_global_pasid(ioasid_t pasid); +int iommu_group_set_qos_params(struct iommu_group *group, + u16 partition, u8 perf_mon_grp); +int iommu_group_get_qos_params(struct iommu_group *group, + u16 *partition, u8 *perf_mon_grp); /* PCI device reset functions */ int pci_dev_reset_iommu_prepare(struct pci_dev *pdev); @@ -1220,6 +1234,16 @@ return ERR_PTR(-ENODEV); } +static inline struct iommu_group *iommu_group_get_from_kobj(struct kobject *group_kobj) +{ + return NULL; +} + +static inline struct iommu_group *iommu_group_get_by_id(int id) +{ + return NULL; +} + static inline void iommu_domain_free(struct iommu_domain *domain) { } @@ -1378,6 +1402,11 @@ return -ENODEV; } +static inline struct kset *iommu_get_group_kset(void) +{ + return NULL; +} + static inline int iommu_set_pgtable_quirks(struct iommu_domain *domain, unsigned long quirks) { @@ -1517,6 +1546,18 @@ static inline void iommu_free_global_pasid(ioasid_t pasid) {} +static inline int iommu_group_set_qos_params(struct iommu_group *group, + u16 partition, u8 perf_mon_grp) +{ + return -ENODEV; +} + +static inline int iommu_group_get_qos_params(struct iommu_group *group, + u16 *partition, u8 *perf_mon_grp) +{ + return -ENODEV; +} + static inline int pci_dev_reset_iommu_prepare(struct pci_dev *pdev) { return 0; --- linux-nvidia-7.0.0.orig/include/linux/ipc_namespace.h +++ linux-nvidia-7.0.0/include/linux/ipc_namespace.h @@ -128,6 +128,9 @@ static inline int mq_init_ns(struct ipc_namespace *ns) { return 0; } #endif +extern struct ipc_namespace *get_ipc_ns_exported(struct ipc_namespace *ns); +extern struct ipc_namespace *show_init_ipc_ns(void); + #if defined(CONFIG_IPC_NS) static inline struct ipc_namespace *to_ipc_ns(struct ns_common *ns) { --- linux-nvidia-7.0.0.orig/include/linux/kobject.h +++ linux-nvidia-7.0.0/include/linux/kobject.h @@ -200,6 +200,8 @@ struct kobject *kset_find_obj(struct kset *, const char *); +struct kobject *kset_get_next_obj(struct kset *kset, struct kobject *prev); + /* The global /sys/kernel/ kobject for people to chain off of */ extern struct kobject *kernel_kobj; /* The global /sys/kernel/mm/ kobject for people to chain off of */ --- linux-nvidia-7.0.0.orig/include/linux/lsm_hook_defs.h +++ linux-nvidia-7.0.0/include/linux/lsm_hook_defs.h @@ -446,6 +446,7 @@ LSM_HOOK(int, 0, locked_down, enum lockdown_reason what) + #ifdef CONFIG_PERF_EVENTS LSM_HOOK(int, 0, perf_event_open, int type) LSM_HOOK(int, 0, perf_event_alloc, struct perf_event *event) --- linux-nvidia-7.0.0.orig/include/linux/lsm_hooks.h +++ linux-nvidia-7.0.0/include/linux/lsm_hooks.h @@ -119,6 +119,7 @@ unsigned int lbs_bpf_map; unsigned int lbs_bpf_prog; unsigned int lbs_bpf_token; + bool lbs_secmark; /* expressed desire for secmark use */ }; /* --- linux-nvidia-7.0.0.orig/include/linux/memory.h +++ linux-nvidia-7.0.0/include/linux/memory.h @@ -119,6 +119,7 @@ #define CPUSET_CALLBACK_PRI 10 #define MEMTIER_HOTPLUG_PRI 100 #define KSM_CALLBACK_PRI 100 +#define RESCTRL_CALLBACK_PRI 100 #ifndef CONFIG_MEMORY_HOTPLUG static inline void memory_dev_init(void) --- linux-nvidia-7.0.0.orig/include/linux/memory_hotplug.h +++ linux-nvidia-7.0.0/include/linux/memory_hotplug.h @@ -318,4 +318,10 @@ void arch_remove_linear_mapping(u64 start, u64 size); #endif /* CONFIG_MEMORY_HOTPLUG */ +#if defined(CONFIG_LOCKDEP) && defined(CONFIG_MEMORY_HOTPLUG) +void lockdep_assert_mems_held(void); +#else +static inline void lockdep_assert_mems_held(void) { } +#endif + #endif /* __LINUX_MEMORY_HOTPLUG_H */ --- linux-nvidia-7.0.0.orig/include/linux/mfd/cs42l43-regs.h +++ linux-nvidia-7.0.0/include/linux/mfd/cs42l43-regs.h @@ -1181,4 +1181,80 @@ /* CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG */ #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL 0xF05AA50F +/* CS42L43B VARIANT REGISTERS */ +#define CS42L43B_DEVID_VAL 0x0042A43B + +#define CS42L43B_DECIM_VOL_CTRL_CH1_CH2 0x00008280 +#define CS42L43B_DECIM_VOL_CTRL_CH3_CH4 0x00008284 + +#define CS42L43B_DECIM_VOL_CTRL_CH5_CH6 0x00008290 +#define CS42L43B_DECIM_VOL_CTRL_UPDATE 0x0000829C + +#define CS42L43B_DECIM_HPF_WNF_CTRL5 0x000082A0 +#define CS42L43B_DECIM_HPF_WNF_CTRL6 0x000082A4 + +#define CS42L43B_SWIRE_DP3_CH3_INPUT 0x0000C320 +#define CS42L43B_SWIRE_DP3_CH4_INPUT 0x0000C330 +#define CS42L43B_SWIRE_DP4_CH3_INPUT 0x0000C340 +#define CS42L43B_SWIRE_DP4_CH4_INPUT 0x0000C350 + +#define CS42L43B_ISRC1DEC3_INPUT1 0x0000C780 +#define CS42L43B_ISRC1DEC4_INPUT1 0x0000C790 +#define CS42L43B_ISRC2DEC3_INPUT1 0x0000C7A0 +#define CS42L43B_ISRC2DEC4_INPUT1 0x0000C7B0 + +#define CS42L43B_FW_MISSION_CTRL_NEED_CONFIGS 0x00117E00 +#define CS42L43B_FW_MISSION_CTRL_HAVE_CONFIGS 0x00117E04 +#define CS42L43B_FW_MISSION_CTRL_PATCH_START_ADDR_REG 0x00117E08 +#define CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x00117E0C +#define CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x00117E10 + +#define CS42L43B_MCU_SW_REV 0x00117314 +#define CS42L43B_PATCH_START_ADDR 0x00117318 +#define CS42L43B_CONFIG_SELECTION 0x0011731C +#define CS42L43B_NEED_CONFIGS 0x00117320 +#define CS42L43B_BOOT_STATUS 0x00117330 + +#define CS42L43B_FW_MISSION_CTRL_NEED_CONFIGS 0x00117E00 +#define CS42L43B_FW_MISSION_CTRL_HAVE_CONFIGS 0x00117E04 +#define CS42L43B_FW_MISSION_CTRL_PATCH_START_ADDR_REG 0x00117E08 +#define CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x00117E0C +#define CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x00117E10 + +#define CS42L43B_MCU_RAM_MAX 0x00117FFF + +/* CS42L43B_DECIM_DECIM_VOL_CTRL_CH5_CH6 */ +#define CS42L43B_DECIM6_MUTE_MASK 0x80000000 +#define CS42L43B_DECIM6_MUTE_SHIFT 31 +#define CS42L43B_DECIM6_VOL_MASK 0x3FC00000 +#define CS42L43B_DECIM6_VOL_SHIFT 22 +#define CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_MASK 0x00380000 +#define CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_SHIFT 19 +#define CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_MASK 0x00070000 +#define CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_SHIFT 16 +#define CS42L43B_DECIM5_MUTE_MASK 0x00008000 +#define CS42L43B_DECIM5_MUTE_SHIFT 15 +#define CS42L43B_DECIM5_VOL_MASK 0x00003FC0 +#define CS42L43B_DECIM5_VOL_SHIFT 6 +#define CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_MASK 0x00000038 +#define CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_SHIFT 3 +#define CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_MASK 0x00000007 +#define CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_SHIFT 0 + +/* CS42L43B_DECIM_VOL_CTRL_UPDATE */ +#define CS42L43B_DECIM6_PATH1_VOL_TRIG_MASK 0x00000800 +#define CS42L43B_DECIM6_PATH1_VOL_TRIG_SHIFT 11 +#define CS42L43B_DECIM5_PATH1_VOL_TRIG_MASK 0x00000100 +#define CS42L43B_DECIM5_PATH1_VOL_TRIG_SHIFT 8 +#define CS42L43B_DECIM4_VOL_UPDATE_MASK 0x00000020 +#define CS42L43B_DECIM4_VOL_UPDATE_SHIFT 5 + +/* CS42L43_ISRC1_CTRL..CS42L43_ISRC2_CTRL */ +#define CS42L43B_ISRC_DEC4_EN_MASK 0x00000008 +#define CS42L43B_ISRC_DEC4_EN_SHIFT 3 +#define CS42L43B_ISRC_DEC4_EN_WIDTH 1 +#define CS42L43B_ISRC_DEC3_EN_MASK 0x00000004 +#define CS42L43B_ISRC_DEC3_EN_SHIFT 2 +#define CS42L43B_ISRC_DEC3_EN_WIDTH 1 + #endif /* CS42L43_CORE_REGS_H */ --- linux-nvidia-7.0.0.orig/include/linux/mfd/cs42l43.h +++ linux-nvidia-7.0.0/include/linux/mfd/cs42l43.h @@ -98,6 +98,7 @@ bool sdw_pll_active; bool attached; bool hw_lock; + long variant_id; }; #endif /* CS42L43_CORE_EXT_H */ --- linux-nvidia-7.0.0.orig/include/linux/nvgrace-egm.h +++ linux-nvidia-7.0.0/include/linux/nvgrace-egm.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#ifndef _NVGRACE_EGM_H +#define _NVGRACE_EGM_H + +int register_egm_node(struct pci_dev *pdev); +void unregister_egm_node(struct pci_dev *pdev); + +#endif /* _NVGRACE_EGM_H */ --- linux-nvidia-7.0.0.orig/include/linux/pci.h +++ linux-nvidia-7.0.0/include/linux/pci.h @@ -501,6 +501,7 @@ unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ unsigned int non_mappable_bars:1; /* BARs can't be mapped to user-space */ + unsigned int aspm_os_control:1; /* Display of ROM attribute enabled? */ pci_dev_flags_t dev_flags; atomic_t enable_cnt; /* pci_enable_device has been called */ --- linux-nvidia-7.0.0.orig/include/linux/perf_event.h +++ linux-nvidia-7.0.0/include/linux/perf_event.h @@ -1784,6 +1784,12 @@ #define PERF_SECURITY_CPU 1 #define PERF_SECURITY_KERNEL 2 #define PERF_SECURITY_TRACEPOINT 3 +#define PERF_SECURITY_MAX 4 + +static inline bool perf_paranoid_any(void) +{ + return sysctl_perf_event_paranoid >= PERF_SECURITY_MAX; +} static inline int perf_is_paranoid(void) { --- linux-nvidia-7.0.0.orig/include/linux/resctrl.h +++ linux-nvidia-7.0.0/include/linux/resctrl.h @@ -3,6 +3,7 @@ #define _RESCTRL_H #include +#include #include #include #include @@ -54,6 +55,8 @@ RDT_RESOURCE_MBA, RDT_RESOURCE_SMBA, RDT_RESOURCE_PERF_PKG, + RDT_RESOURCE_L3_MAX, + RDT_RESOURCE_L2_MAX, /* Must be the last */ RDT_NUM_RESOURCES, @@ -137,7 +140,7 @@ */ struct rdt_domain_hdr { struct list_head list; - int id; + u32 id; enum resctrl_domain_type type; enum resctrl_res_level rid; struct cpumask cpu_mask; @@ -247,22 +250,28 @@ * @min_bw: Minimum memory bandwidth percentage user can request * @max_bw: Maximum memory bandwidth value, used as the reset value * @bw_gran: Granularity at which the memory bandwidth is allocated - * @delay_linear: True if memory B/W delay is in linear scale - * @arch_needs_linear: True if we can't configure non-linear resources - * @throttle_mode: Bandwidth throttling mode when threads request - * different memory bandwidths - * @mba_sc: True if MBA software controller(mba_sc) is enabled - * @mb_map: Mapping of memory B/W percentage to memory B/W delay */ struct resctrl_membw { u32 min_bw; u32 max_bw; u32 bw_gran; - u32 delay_linear; - bool arch_needs_linear; - enum membw_throttle_mode throttle_mode; +}; + +/** + * struct resctrl_mba - Resource properties that are specific to the MBA resource + * @mba_sc: True if MBA software controller(mba_sc) is enabled + * @mb_map: Mapping of memory B/W percentage to memory B/W delay + * @delay_linear: True if control is in linear scale + * @arch_needs_linear: True if we can't configure non-linear resources + * @throttle_mode: Mode when threads request different control values + */ +struct resctrl_mba { bool mba_sc; u32 *mb_map; + bool delay_linear; + bool arch_needs_linear; + enum membw_throttle_mode throttle_mode; + }; struct resctrl_schema; @@ -277,11 +286,15 @@ /** * enum resctrl_schema_fmt - The format user-space provides for a schema. * @RESCTRL_SCHEMA_BITMAP: The schema is a bitmap in hex. - * @RESCTRL_SCHEMA_RANGE: The schema is a decimal number. + * @RESCTRL_SCHEMA_PERCENT: The schema is a percentage. + * @RESCTRL_SCHEMA_MBPS: The schema ia a MBps value. + * @RESCTRL_SCHEMA__AMD_MBA: The schema value is MBA for AMD platforms. */ enum resctrl_schema_fmt { RESCTRL_SCHEMA_BITMAP, - RESCTRL_SCHEMA_RANGE, + RESCTRL_SCHEMA_PERCENT, + RESCTRL_SCHEMA_MBPS, + RESCTRL_SCHEMA__AMD_MBA, }; /** @@ -314,8 +327,12 @@ * @mon: Monitoring related data. * @ctrl_domains: RCU list of all control domains for this resource * @mon_domains: RCU list of all monitor domains for this resource + * @mba: Properties of the MBA resource * @name: Name to use in "schemata" file. - * @schema_fmt: Which format string and parser is used for this schema. + * @schema_fmt: Which format control parameters should be in for this resource. + * @evt_list: List of monitoring events + * @mbm_cfg_mask: Bandwidth sources that can be tracked when bandwidth + * monitoring events can be configured. * @cdp_capable: Is the CDP feature available on this resource */ struct rdt_resource { @@ -327,6 +344,7 @@ struct resctrl_cache cache; struct resctrl_membw membw; struct resctrl_mon mon; + struct resctrl_mba mba; struct list_head ctrl_domains; struct list_head mon_domains; char *name; @@ -347,9 +365,12 @@ * @list: Member of resctrl_schema_all. * @name: The name to use in the "schemata" file. * @fmt_str: Format string to show domain value. + * @schema_fmt: Which format string and parser is used for this schema. * @conf_type: Whether this schema is specific to code/data. * @res: The resource structure exported by the architecture to describe * the hardware that is configured by this schema. + * @membw The properties of the schema which may be different to the format + * that was specified by the resource, * @num_closid: The number of closid that can be used with this schema. When * features like CDP are enabled, this will be lower than the * hardware supports for the resource. @@ -358,8 +379,10 @@ struct list_head list; char name[8]; const char *fmt_str; + enum resctrl_schema_fmt schema_fmt; enum resctrl_conf_type conf_type; struct rdt_resource *res; + struct resctrl_membw membw; u32 num_closid; }; @@ -393,22 +416,43 @@ void resctrl_arch_sync_cpu_closid_rmid(void *info); /** - * resctrl_get_default_ctrl() - Return the default control value for this - * resource. - * @r: The resource whose default control type is queried. + * resctrl_get_resource_default_ctrl() - Return the default control value for + * this resource. + * @r: The resource whose default control value is queried. */ -static inline u32 resctrl_get_default_ctrl(struct rdt_resource *r) +static inline u32 resctrl_get_resource_default_ctrl(struct rdt_resource *r) { switch (r->schema_fmt) { case RESCTRL_SCHEMA_BITMAP: return BIT_MASK(r->cache.cbm_len) - 1; - case RESCTRL_SCHEMA_RANGE: + case RESCTRL_SCHEMA_PERCENT: + case RESCTRL_SCHEMA_MBPS: + case RESCTRL_SCHEMA__AMD_MBA: return r->membw.max_bw; } return WARN_ON_ONCE(1); } +/** + * resctrl_get_schema_default_ctrl() - Return the default control value for + * this schema. + * @s: The schema whose default control value is queried. + */ +static inline u32 resctrl_get_schema_default_ctrl(struct resctrl_schema *s) +{ + switch (s->schema_fmt) { + case RESCTRL_SCHEMA_BITMAP: + return resctrl_get_resource_default_ctrl(s->res); + case RESCTRL_SCHEMA_PERCENT: + case RESCTRL_SCHEMA_MBPS: + case RESCTRL_SCHEMA__AMD_MBA: + return s->membw.max_bw; + } + + return WARN_ON_ONCE(1); +} + /* The number of closid supported by this resource regardless of CDP */ u32 resctrl_arch_get_num_closid(struct rdt_resource *r); u32 resctrl_arch_system_num_rmid_idx(void); @@ -500,6 +544,8 @@ */ int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable); +u32 resctrl_arch_round_bw(u32 val, const struct resctrl_schema *s); + /* * Update the ctrl_val and apply this config right now. * Must be called on one of the domain's CPUs. @@ -705,6 +751,7 @@ int resctrl_init(void); void resctrl_exit(void); + #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK u64 resctrl_arch_get_prefetch_disable_bits(void); int resctrl_arch_pseudo_lock_fn(void *_plr); @@ -718,4 +765,30 @@ static inline int resctrl_arch_measure_l2_residency(void *_plr) { return 0; } static inline int resctrl_arch_measure_l3_residency(void *_plr) { return 0; } #endif /* CONFIG_RESCTRL_FS_PSEUDO_LOCK */ + +/* When supported, the architecture must implement these */ +#ifdef CONFIG_RESCTRL_IOMMU +int resctrl_arch_set_iommu_closid_rmid(struct iommu_group *group, u32 closid, + u32 rmid); +bool resctrl_arch_match_iommu_closid(struct iommu_group *group, u32 closid); +bool resctrl_arch_match_iommu_closid_rmid(struct iommu_group *group, u32 closid, + u32 rmid); +#else +static inline int resctrl_arch_set_iommu_closid_rmid(struct iommu_group *group, + u32 closid, u32 rmid) +{ + return -EOPNOTSUPP; +} +static inline bool resctrl_arch_match_iommu_closid(struct iommu_group *group, + u32 closid) +{ + return false; +} +static inline bool +resctrl_arch_match_iommu_closid_rmid(struct iommu_group *group, + u32 closid, u32 rmid) +{ + return false; +} +#endif /* CONFIG_RESCTRL_IOMMU */ #endif /* _RESCTRL_H */ --- linux-nvidia-7.0.0.orig/include/linux/scmi_protocol.h +++ linux-nvidia-7.0.0/include/linux/scmi_protocol.h @@ -878,6 +878,17 @@ }; /** + * struct scmi_mpam_proto_ops - operations provided by SCMI MPAM Protocol + * + * @mpam_transfer_buf: transfer an SCMI MPAM message to the agent + */ +struct scmi_mpam_proto_ops { + int (*mpam_transfer_buf)(const struct scmi_protocol_handle *ph, + u8 msg_id, void *msg_buf, size_t msg_len, + u32 *ret_val); +}; + +/** * struct scmi_handle - Handle returned to ARM SCMI clients for usage. * * @dev: pointer to the SCMI device @@ -926,6 +937,7 @@ SCMI_PROTOCOL_VOLTAGE = 0x17, SCMI_PROTOCOL_POWERCAP = 0x18, SCMI_PROTOCOL_PINCTRL = 0x19, + SCMI_PROTOCOL_MPAM = 0x1a, }; enum scmi_system_events { --- linux-nvidia-7.0.0.orig/include/linux/security.h +++ linux-nvidia-7.0.0/include/linux/security.h @@ -2405,4 +2405,13 @@ } #endif /* CONFIG_SECURITY */ +#ifdef CONFIG_SECURITY_LOCKDOWN_LSM +extern int security_lock_kernel_down(const char *where, enum lockdown_reason level); +#else +static inline int security_lock_kernel_down(const char *where, enum lockdown_reason level) +{ + return 0; +} +#endif /* CONFIG_SECURITY_LOCKDOWN_LSM */ + #endif /* ! __LINUX_SECURITY_H */ --- linux-nvidia-7.0.0.orig/include/linux/user_namespace.h +++ linux-nvidia-7.0.0/include/linux/user_namespace.h @@ -204,6 +204,8 @@ const struct user_namespace *child); extern bool current_in_userns(const struct user_namespace *target_ns); struct ns_common *ns_get_owner(struct ns_common *ns); + +extern int unprivileged_userns_clone; #else static inline struct user_namespace *get_user_ns(struct user_namespace *ns) --- linux-nvidia-7.0.0.orig/include/net/ip_tunnels.h +++ linux-nvidia-7.0.0/include/net/ip_tunnels.h @@ -138,6 +138,28 @@ }; struct metadata_dst; +/* A fan overlay /8 (250.0.0.0/8, for example) maps to exactly one /16 + * underlay (10.88.0.0/16, for example). Multiple local addresses within + * the /16 may be used, but a particular overlay may not span + * multiple underlay subnets. + * + * We store one underlay, indexed by the overlay's high order octet. + */ +#define FAN_OVERLAY_CNT 256 + +struct ip_fan_map { + __be32 underlay; + __be32 overlay; + u16 underlay_prefix; + u16 overlay_prefix; + u32 overlay_mask; + struct list_head list; + struct rcu_head rcu; +}; + +struct ip_tunnel_fan { + struct list_head fan_maps; +}; /* Kernel-side variant of ip_tunnel_parm */ struct ip_tunnel_parm_kern { @@ -189,6 +211,7 @@ #endif struct ip_tunnel_prl_entry __rcu *prl; /* potential router list */ unsigned int prl_count; /* # of entries in PRL */ + struct ip_tunnel_fan fan; unsigned int ip_tnl_net_id; struct gro_cells gro_cells; __u32 fwmark; @@ -196,6 +219,11 @@ bool ignore_df; }; +static inline int fan_has_map(const struct ip_tunnel_fan *fan) +{ + return !list_empty(&fan->fan_maps); +} + struct tnl_ptk_info { IP_TUNNEL_DECLARE_FLAGS(flags); __be16 proto; --- linux-nvidia-7.0.0.orig/include/net/vxlan.h +++ linux-nvidia-7.0.0/include/net/vxlan.h @@ -295,6 +295,8 @@ struct net *net; /* netns for packet i/o */ struct vxlan_rdst default_dst; /* default destination */ + struct ip_tunnel_fan fan; + struct timer_list age_timer; spinlock_t hash_lock; unsigned int addrcnt; --- linux-nvidia-7.0.0.orig/include/sound/soc.h +++ linux-nvidia-7.0.0/include/sound/soc.h @@ -465,6 +465,7 @@ const char *driver_name); struct snd_soc_component *snd_soc_lookup_component(struct device *dev, const char *driver_name); +struct snd_soc_component *snd_soc_lookup_component_by_name(const char *component_name); int soc_new_pcm(struct snd_soc_pcm_runtime *rtd); #ifdef CONFIG_SND_SOC_COMPRESS @@ -1239,7 +1240,6 @@ unsigned int sign_bit; unsigned int invert:1; unsigned int autodisable:1; - unsigned int sdca_q78:1; #ifdef CONFIG_SND_SOC_TOPOLOGY struct snd_soc_dobj dobj; #endif --- linux-nvidia-7.0.0.orig/include/uapi/asm-generic/fcntl.h +++ linux-nvidia-7.0.0/include/uapi/asm-generic/fcntl.h @@ -114,13 +114,11 @@ #define F_GETSIG 11 /* for sockets. */ #endif -#if __BITS_PER_LONG == 32 || defined(__KERNEL__) #ifndef F_GETLK64 #define F_GETLK64 12 /* using 'struct flock64' */ #define F_SETLK64 13 #define F_SETLKW64 14 #endif -#endif /* __BITS_PER_LONG == 32 || defined(__KERNEL__) */ #ifndef F_SETOWN_EX #define F_SETOWN_EX 15 --- linux-nvidia-7.0.0.orig/include/uapi/drm/amdxdna_accel.h +++ linux-nvidia-7.0.0/include/uapi/drm/amdxdna_accel.h @@ -353,7 +353,8 @@ }; enum amdxdna_sensor_type { - AMDXDNA_SENSOR_TYPE_POWER + AMDXDNA_SENSOR_TYPE_POWER, + AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION }; /** --- linux-nvidia-7.0.0.orig/include/uapi/drm/drm_mode.h +++ linux-nvidia-7.0.0/include/uapi/drm/drm_mode.h @@ -166,6 +166,10 @@ #define DRM_MODE_LINK_STATUS_GOOD 0 #define DRM_MODE_LINK_STATUS_BAD 1 +/* Panel type property */ +#define DRM_MODE_PANEL_TYPE_UNKNOWN 0 +#define DRM_MODE_PANEL_TYPE_OLED 1 + /* * DRM_MODE_ROTATE_ * --- linux-nvidia-7.0.0.orig/include/uapi/linux/apparmor.h +++ linux-nvidia-7.0.0/include/uapi/linux/apparmor.h @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_LINUX_APPARMOR_H +#define _UAPI_LINUX_APPARMOR_H + +#include + +#define APPARMOR_MODESET_AUDIT 1 +#define APPARMOR_MODESET_ALLOWED 2 +#define APPARMOR_MODESET_ENFORCE 4 +#define APPARMOR_MODESET_HINT 8 +#define APPARMOR_MODESET_STATUS 16 +#define APPARMOR_MODESET_ERROR 32 +#define APPARMOR_MODESET_KILL 64 +#define APPARMOR_MODESET_USER 128 + +#define APPARMOR_FLAG_NOCACHE 1 + +enum apparmor_notif_type { + APPARMOR_NOTIF_RESP_PERM, + APPARMOR_NOTIF_CANCEL, + APPARMOR_NOTIF_INTERUPT, + APPARMOR_NOTIF_ALIVE, + APPARMOR_NOTIF_OP, + APPARMOR_NOTIF_RESP_NAME, +}; + +#define APPARMOR_NOTIFY_V3 3 +#define APPARMOR_NOTIFY_V5 5 +#define APPARMOR_NOTIFY_VERSION 5 + +/* base notification struct embedded as head of notifications to userspace */ +struct apparmor_notif_common { + __u16 len; /* actual len data */ + __u16 version; /* interface version */ +} __attribute__((packed)); + +struct apparmor_notif_register_v5 { + struct apparmor_notif_common base; + __u64 listener_id; /* unique id for listener */ +} __attribute__((packed)); + +struct apparmor_notif_resend_v5 { + struct apparmor_notif_common base; + __u64 listener_id; /* unique id for listener */ + __u32 ready; /* notifications that are ready */ + __u32 pending; /* notifs that are pendying reply */ +} __attribute__((packed)); + +struct apparmor_notif_filter { + struct apparmor_notif_common base; + __u32 modeset; /* which notification mode */ + __u32 ns; /* offset into data */ + __u32 filter; /* offset into data */ + + __u8 data[]; +} __attribute__((packed)); + +// flags +#define URESPONSE_NO_CACHE 1 +#define URESPONSE_LOOKUP 2 +#define URESPONSE_PROFILE 4 +#define URESPONSE_TAILGLOB 8 +#define UNOTIF_RESENT 0x10 + +struct apparmor_notif { + struct apparmor_notif_common base; + __u16 ntype; /* notify type */ + __u8 signalled; + __u8 flags; + __u64 id; /* unique id, not gloablly unique*/ + __s32 error; /* error if unchanged */ +} __attribute__((packed)); + + +struct apparmor_notif_update { + struct apparmor_notif base; + __u16 ttl; /* max keep alives left */ +} __attribute__((packed)); + +/* userspace response to notification that expects a response */ +struct apparmor_notif_resp_perm { + struct apparmor_notif base; + __s32 error; /* error if unchanged */ + __u32 allow; + __u32 deny; +} __attribute__((packed)); + +struct apparmor_notif_resp_name { + union { + struct apparmor_notif base; + struct apparmor_notif_resp_perm perm; + }; + __u32 name; + __u8 data[]; +} __attribute__((packed)); + +struct apparmor_notif_op { + struct apparmor_notif base; + __u32 allow; + __u32 deny; + pid_t pid; /* pid of task causing notification */ + __u32 label; /* offset into data */ + __u16 class; + __u16 op; +} __attribute__((packed)); + +struct apparmor_tags_header_v5 { + __u32 mask; + __u32 count; + __u32 tagset; +} __attribute__((packed)); + +// v3 doesn't have tags but this just adds padding to the data section +struct apparmor_notif_file { + struct apparmor_notif_op base; + uid_t subj_uid, obj_uid; + __u32 name; /* offset into data */ + __u8 data[]; +} __attribute__((packed)); + +struct apparmor_notif_file_v5 { + struct apparmor_notif_op base; + uid_t subj_uid, obj_uid; + __u32 name; /* offset into data */ + __u32 tags; + __u16 tags_count; + __u8 data[]; +} __attribute__((packed)); + +/* ioctl structs */ +union apparmor_notif_filters { + struct { + struct apparmor_notif_common base; + __u32 modeset; /* which notification mode */ + __u32 ns; /* offset into data */ + __u32 filter; /* offset into data */ + + __u8 data[]; + }; + /* common and defined before vX, replicates v3 */ + struct apparmor_notif_filter v3; + struct apparmor_notif_filter v5; +} __attribute__((packed)); + +union apparmor_notif_recv { + /* common and defined before vX, replicates v3 */ + struct { + struct apparmor_notif_op base; + uid_t subj_uid, obj_uid; + __u32 name; /* offset into data */ + __u8 data[]; + }; + struct { + struct apparmor_notif_file file; + } v3; + struct { + struct apparmor_notif_file_v5 file; + } v5; +} __attribute__((packed)); + +union apparmor_notif_resp { + /* common and defined before vX, replicates v3 */ + struct apparmor_notif base; + struct apparmor_notif_resp_perm perm; + struct apparmor_notif_resp_name name; + union { + struct apparmor_notif_resp_perm perm; + struct apparmor_notif_resp_name name; + } v3; + union { + struct apparmor_notif_resp_perm perm; + struct apparmor_notif_resp_name name; + } v5; +} __attribute__((packed)); + +union apparmor_notif_register { + struct { + struct apparmor_notif_register_v5 registration; + struct apparmor_notif_resend_v5 resend; + } v5; +} __attribute__((packed)); + +union apparmor_notif_all { + struct apparmor_notif_common common; + struct apparmor_notif base; + struct apparmor_notif_op op; + struct apparmor_notif_file filev3; + struct apparmor_notif_file_v5 file; + union apparmor_notif_filters filter; + union apparmor_notif_recv recv; + union apparmor_notif_resp respnse; + union apparmor_notif_register registration; +} __attribute__((packed)); + +#define APPARMOR_IOC_MAGIC 0xF8 + +/* Flags for apparmor notification fd ioctl. */ + +#define APPARMOR_NOTIF_SET_FILTER _IOW(APPARMOR_IOC_MAGIC, 0, \ + union apparmor_notif_filters *) +#define APPARMOR_NOTIF_GET_FILTER _IOR(APPARMOR_IOC_MAGIC, 1, \ + union apparmor_notif_filters *) +#define APPARMOR_NOTIF_IS_ID_VALID _IOR(APPARMOR_IOC_MAGIC, 3, \ + __u64) +/* RECV/SEND from userspace pov */ +#define APPARMOR_NOTIF_RECV _IOWR(APPARMOR_IOC_MAGIC, 4, \ + union apparmor_notif_recv *) +#define APPARMOR_NOTIF_SEND _IOWR(APPARMOR_IOC_MAGIC, 5, \ + union apparmor_notif_resp *) +#define APPARMOR_NOTIF_REGISTER _IOWR(APPARMOR_IOC_MAGIC, 6, \ + union apparmor_notif_register *) +#define APPARMOR_NOTIF_RESEND _IOWR(APPARMOR_IOC_MAGIC, 7, \ + union apparmor_notif_register *) + + +#endif /* _UAPI_LINUX_APPARMOR_H */ --- linux-nvidia-7.0.0.orig/include/uapi/linux/egm.h +++ linux-nvidia-7.0.0/include/uapi/linux/egm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#ifndef _UAPIEGM_H +#define _UAPIEGM_H + +#define EGM_TYPE ('E') + +struct egm_bad_pages_info { + __aligned_u64 offset; + __aligned_u64 size; +}; + +struct egm_bad_pages_list { + __u32 argsz; + /* out */ + __u32 count; + /* out */ + struct egm_bad_pages_info bad_pages[]; +}; + +#define EGM_BAD_PAGES_LIST _IO(EGM_TYPE, 100) + +#endif /* _UAPIEGM_H */ --- linux-nvidia-7.0.0.orig/include/uapi/linux/if_link.h +++ linux-nvidia-7.0.0/include/uapi/linux/if_link.h @@ -1401,6 +1401,7 @@ IFLA_VXLAN_LABEL_POLICY, /* IPv6 flow label policy; ifla_vxlan_label_policy */ IFLA_VXLAN_RESERVED_BITS, IFLA_VXLAN_MC_ROUTE, + IFLA_VXLAN_FAN_MAP, __IFLA_VXLAN_MAX }; #define IFLA_VXLAN_MAX (__IFLA_VXLAN_MAX - 1) --- linux-nvidia-7.0.0.orig/include/uapi/linux/if_tunnel.h +++ linux-nvidia-7.0.0/include/uapi/linux/if_tunnel.h @@ -77,6 +77,10 @@ IFLA_IPTUN_ENCAP_DPORT, IFLA_IPTUN_COLLECT_METADATA, IFLA_IPTUN_FWMARK, + + __IFLA_IPTUN_VENDOR_BREAK, /* Ensure new entries do not hit the below. */ + IFLA_IPTUN_FAN_MAP = 33, + __IFLA_IPTUN_MAX, }; #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) @@ -218,4 +222,19 @@ __IP_TUNNEL_FLAG_NUM, }; +enum { + IFLA_FAN_UNSPEC, + IFLA_FAN_MAPPING, + __IFLA_FAN_MAX, +}; + +#define IFLA_FAN_MAX (__IFLA_FAN_MAX - 1) + +struct ifla_fan_map { + __be32 underlay; + __be32 overlay; + __u16 underlay_prefix; + __u16 overlay_prefix; +}; + #endif /* _UAPI_IF_TUNNEL_H_ */ --- linux-nvidia-7.0.0.orig/include/uapi/linux/rfkill.h +++ linux-nvidia-7.0.0/include/uapi/linux/rfkill.h @@ -159,16 +159,8 @@ * old behaviour for all userspace, unless it explicitly opts in to the * rules outlined here by using the new &struct rfkill_event_ext. * - * Additionally, some other userspace (bluez, g-s-d) was reading with a - * large size but as streaming reads rather than message-based, or with - * too strict checks for the returned size. So eventually, we completely - * reverted this, and extended messages need to be opted in to by using - * an ioctl: - * - * ioctl(fd, RFKILL_IOCTL_MAX_SIZE, sizeof(struct rfkill_event_ext)); - * - * Userspace using &struct rfkill_event_ext and the ioctl must adhere to - * the following rules: + * Userspace using &struct rfkill_event_ext must adhere to the following + * rules * * 1. accept short writes, optionally using them to detect that it's * running on an older kernel; @@ -183,8 +175,6 @@ #define RFKILL_IOC_MAGIC 'R' #define RFKILL_IOC_NOINPUT 1 #define RFKILL_IOCTL_NOINPUT _IO(RFKILL_IOC_MAGIC, RFKILL_IOC_NOINPUT) -#define RFKILL_IOC_MAX_SIZE 2 -#define RFKILL_IOCTL_MAX_SIZE _IOW(RFKILL_IOC_MAGIC, RFKILL_IOC_MAX_SIZE, __u32) /* and that's all userspace gets */ --- linux-nvidia-7.0.0.orig/include/uapi/linux/sysctl.h +++ linux-nvidia-7.0.0/include/uapi/linux/sysctl.h @@ -152,7 +152,7 @@ KERN_NMI_WATCHDOG=75, /* int: enable/disable nmi watchdog */ KERN_PANIC_ON_NMI=76, /* int: whether we will panic on an unrecovered */ KERN_PANIC_ON_WARN=77, /* int: call panic() in WARN() functions */ - KERN_PANIC_PRINT=78, /* ulong: bitmask to print system info on panic */ + KERN_PANIC_PRINT=78, /* unsigned long: bitmask to print system info on panic */ }; --- linux-nvidia-7.0.0.orig/include/uapi/linux/tty_flags.h +++ linux-nvidia-7.0.0/include/uapi/linux/tty_flags.h @@ -32,6 +32,7 @@ #define ASYNCB_AUTOPROBE 15 /* [x] Port was autoprobed by PCI/PNP code */ #define ASYNCB_MAGIC_MULTIPLIER 16 /* Use special CLK or divisor */ #define ASYNCB_LAST_USER 16 +#define ASYNCB_INITIALIZED 31 /* Serial port was initialized */ /* * Internal flags used only by kernel (read-only) @@ -40,7 +41,6 @@ * TTY_PORT_ flags in the iflags field (and not userspace-visible) */ #ifndef __KERNEL__ -#define ASYNCB_INITIALIZED 31 /* Serial port was initialized */ #define ASYNCB_SUSPENDED 30 /* Serial port is suspended */ #define ASYNCB_NORMAL_ACTIVE 29 /* Normal device is active */ #define ASYNCB_BOOT_AUTOCONF 28 /* Autoconfigure port on bootup */ --- linux-nvidia-7.0.0.orig/init/Kconfig +++ linux-nvidia-7.0.0/init/Kconfig @@ -455,6 +455,15 @@ but you may wish to use a different default here to make a minimal system more usable with less configuration. +config VERSION_SIGNATURE + string "Arbitrary version signature" + help + This string will be created in a file, /proc/version_signature. It + is useful in determining arbitrary data about your kernel. For instance, + if you have several kernels of the same version, but need to keep track + of a revision of the same kernel, but not affect it's ability to load + compatible modules, this is the easiest way to do that. + config SYSVIPC bool "System V IPC" help --- linux-nvidia-7.0.0.orig/init/do_mounts.c +++ linux-nvidia-7.0.0/init/do_mounts.c @@ -457,6 +457,8 @@ */ void __init prepare_namespace(void) { + int err; + if (root_delay) { printk(KERN_INFO "Waiting %d sec before mounting root device...\n", root_delay); @@ -493,6 +495,14 @@ return; } pr_info("VFS: Pivoted into new rootfs\n"); + +#ifdef CONFIG_BLOCK + /* recreate the /dev/root */ + err = create_dev("/dev/root", ROOT_DEV); + + if (err < 0) + pr_emerg("Failed to create /dev/root: %d\n", err); +#endif } static bool is_tmpfs; --- linux-nvidia-7.0.0.orig/init/version-timestamp.c +++ linux-nvidia-7.0.0/init/version-timestamp.c @@ -23,4 +23,8 @@ /* FIXED STRINGS! Don't touch! */ const char linux_banner[] = "Linux version " UTS_RELEASE " (" LINUX_COMPILE_BY "@" - LINUX_COMPILE_HOST ") (" LINUX_COMPILER ") " UTS_VERSION "\n"; + LINUX_COMPILE_HOST ") (" LINUX_COMPILER ") " UTS_VERSION +#ifdef CONFIG_VERSION_SIGNATURE + " (" CONFIG_VERSION_SIGNATURE ")" +#endif + "\n"; --- linux-nvidia-7.0.0.orig/ipc/mqueue.c +++ linux-nvidia-7.0.0/ipc/mqueue.c @@ -593,6 +593,15 @@ ipc_ns->mq_queues_count--; goto out_unlock; } + error = security_inode_init_security(inode, dir, + &dentry->d_name, NULL, + NULL); + if (error) { + iput(inode); + spin_lock(&mq_lock); + ipc_ns->mq_queues_count--; + goto out_unlock; + } put_ipc_ns(ipc_ns); dir->i_size += DIRENT_SIZE; --- linux-nvidia-7.0.0.orig/ipc/namespace.c +++ linux-nvidia-7.0.0/ipc/namespace.c @@ -210,6 +210,23 @@ schedule_work(&free_ipc_work); } } +EXPORT_SYMBOL(put_ipc_ns); + +struct ipc_namespace *get_ipc_ns_exported(struct ipc_namespace *ns) +{ + return get_ipc_ns(ns); +} +EXPORT_SYMBOL(get_ipc_ns_exported); + +struct ipc_namespace *show_init_ipc_ns(void) +{ +#if defined(CONFIG_IPC_NS) + return &init_ipc_ns; +#else + return NULL; +#endif +} +EXPORT_SYMBOL(show_init_ipc_ns); static struct ns_common *ipcns_get(struct task_struct *task) { --- linux-nvidia-7.0.0.orig/kernel/events/core.c +++ linux-nvidia-7.0.0/kernel/events/core.c @@ -491,8 +491,13 @@ * 0 - disallow raw tracepoint access for unpriv * 1 - disallow cpu events for unpriv * 2 - disallow kernel profiling for unpriv + * 4 - disallow all unpriv perf event use */ +#ifdef CONFIG_SECURITY_PERF_EVENTS_RESTRICT +int sysctl_perf_event_paranoid __read_mostly = PERF_SECURITY_MAX; +#else int sysctl_perf_event_paranoid __read_mostly = 2; +#endif /* Minimum for 512 kiB + 1 user control page. 'free' kiB per user. */ static int sysctl_perf_event_mlock __read_mostly = 512 + (PAGE_SIZE / 1024); @@ -13824,6 +13829,9 @@ if (flags & ~PERF_FLAG_ALL) return -EINVAL; + if (perf_paranoid_any() && !perfmon_capable()) + return -EACCES; + err = perf_copy_attr(attr_uptr, &attr); if (err) return err; --- linux-nvidia-7.0.0.orig/kernel/fork.c +++ linux-nvidia-7.0.0/kernel/fork.c @@ -121,6 +121,11 @@ #define CREATE_TRACE_POINTS #include +#ifdef CONFIG_USER_NS +extern int unprivileged_userns_clone; +#else +#define unprivileged_userns_clone 0 +#endif #include @@ -1984,6 +1989,10 @@ if ((clone_flags & (CLONE_NEWUSER|CLONE_FS)) == (CLONE_NEWUSER|CLONE_FS)) return ERR_PTR(-EINVAL); + if ((clone_flags & CLONE_NEWUSER) && !unprivileged_userns_clone) + if (!capable(CAP_SYS_ADMIN)) + return ERR_PTR(-EPERM); + /* * Thread groups must share signals as well, and detached threads * can only be started up within the thread group. @@ -3151,6 +3160,12 @@ if (unshare_flags & CLONE_NEWNS) unshare_flags |= CLONE_FS; + if ((unshare_flags & CLONE_NEWUSER) && !unprivileged_userns_clone) { + err = -EPERM; + if (!capable(CAP_SYS_ADMIN)) + goto bad_unshare_out; + } + err = check_unshare_flags(unshare_flags); if (err) goto bad_unshare_out; --- linux-nvidia-7.0.0.orig/kernel/ksysfs.c +++ linux-nvidia-7.0.0/kernel/ksysfs.c @@ -132,6 +132,15 @@ #endif /* CONFIG_VMCORE_INFO */ +#if defined(CONFIG_PREEMPT_RT) +static ssize_t realtime_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", 1); +} +KERNEL_ATTR_RO(realtime); +#endif + /* whether file capabilities are enabled */ static ssize_t fscaps_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) @@ -206,6 +215,9 @@ &rcu_expedited_attr.attr, &rcu_normal_attr.attr, #endif +#ifdef CONFIG_PREEMPT_RT + &realtime_attr.attr, +#endif NULL }; --- linux-nvidia-7.0.0.orig/kernel/kthread.c +++ linux-nvidia-7.0.0/kernel/kthread.c @@ -505,6 +505,17 @@ * new kernel thread. */ if (unlikely(wait_for_completion_killable(&done))) { + int i = 0; + + /* + * I got SIGKILL, but wait for 10 more seconds for completion + * unless chosen by the OOM killer. This delay is there as a + * workaround for boot failure caused by SIGKILL upon device + * driver initialization timeout. + */ + while (i++ < 10 && !test_tsk_thread_flag(current, TIF_MEMDIE)) + if (wait_for_completion_timeout(&done, HZ)) + goto ready; /* * If I was killed by a fatal signal before kthreadd (or new * kernel thread) calls complete(), leave the cleanup of this @@ -518,6 +529,7 @@ */ wait_for_completion(&done); } +ready: task = create->result; free_create: kfree(create); --- linux-nvidia-7.0.0.orig/kernel/module/signing.c +++ linux-nvidia-7.0.0/kernel/module/signing.c @@ -61,10 +61,17 @@ modlen -= sig_len + sizeof(ms); info->len = modlen; - return verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len, + ret = verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len, VERIFY_USE_SECONDARY_KEYRING, VERIFYING_MODULE_SIGNATURE, NULL, NULL); + if (ret == -ENOKEY && IS_ENABLED(CONFIG_INTEGRITY_PLATFORM_KEYRING)) { + ret = verify_pkcs7_signature(mod, modlen, mod + modlen, sig_len, + VERIFY_USE_PLATFORM_KEYRING, + VERIFYING_MODULE_SIGNATURE, + NULL, NULL); + } + return ret; } int module_sig_check(struct load_info *info, int flags) --- linux-nvidia-7.0.0.orig/kernel/sched/syscalls.c +++ linux-nvidia-7.0.0/kernel/sched/syscalls.c @@ -119,6 +119,7 @@ { return is_nice_reduction(p, nice) || capable(CAP_SYS_NICE); } +EXPORT_SYMBOL(can_nice); #ifdef __ARCH_WANT_SYS_NICE --- linux-nvidia-7.0.0.orig/kernel/sched/wait.c +++ linux-nvidia-7.0.0/kernel/sched/wait.c @@ -231,6 +231,7 @@ /* POLLFREE must have cleared the queue. */ WARN_ON_ONCE(waitqueue_active(wq_head)); } +EXPORT_SYMBOL_GPL(__wake_up_pollfree); /* * Note: we use "set_current_state()" _after_ the wait-queue add, --- linux-nvidia-7.0.0.orig/kernel/sys.c +++ linux-nvidia-7.0.0/kernel/sys.c @@ -1308,6 +1308,21 @@ DECLARE_RWSEM(uts_sem); #ifdef COMPAT_UTS_MACHINE +static char compat_uts_machine[__OLD_UTS_LEN+1] = COMPAT_UTS_MACHINE; + +static int __init parse_compat_uts_machine(char *arg) +{ + strncpy(compat_uts_machine, arg, __OLD_UTS_LEN); + compat_uts_machine[__OLD_UTS_LEN] = 0; + return 0; +} +early_param("compat_uts_machine", parse_compat_uts_machine); + +#undef COMPAT_UTS_MACHINE +#define COMPAT_UTS_MACHINE compat_uts_machine +#endif + +#ifdef COMPAT_UTS_MACHINE #define override_architecture(name) \ (personality(current->personality) == PER_LINUX32 && \ copy_to_user(name->machine, COMPAT_UTS_MACHINE, \ --- linux-nvidia-7.0.0.orig/kernel/sysctl.c +++ linux-nvidia-7.0.0/kernel/sysctl.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "../lib/kstrtox.h" @@ -1414,6 +1415,15 @@ .mode = 0644, .proc_handler = proc_dointvec, }, +#endif +#ifdef CONFIG_USER_NS + { + .procname = "unprivileged_userns_clone", + .data = &unprivileged_userns_clone, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, #endif }; --- linux-nvidia-7.0.0.orig/kernel/task_work.c +++ linux-nvidia-7.0.0/kernel/task_work.c @@ -102,6 +102,7 @@ return 0; } +EXPORT_SYMBOL(task_work_add); /** * task_work_cancel_match - cancel a pending work added by task_work_add() --- linux-nvidia-7.0.0.orig/kernel/user_namespace.c +++ linux-nvidia-7.0.0/kernel/user_namespace.c @@ -23,6 +23,12 @@ #include #include +/* + * sysctl determining whether unprivileged users may unshare a new + * userns. Allowed by default + */ +int unprivileged_userns_clone = 1; + static struct kmem_cache *user_ns_cachep __ro_after_init; static DEFINE_MUTEX(userns_state_mutex); --- linux-nvidia-7.0.0.orig/lib/kobject.c +++ linux-nvidia-7.0.0/lib/kobject.c @@ -920,6 +920,27 @@ } EXPORT_SYMBOL_GPL(kset_find_obj); +struct kobject *kset_get_next_obj(struct kset *kset, struct kobject *prev) +{ + struct kobject *k; + + spin_lock(&kset->list_lock); + + if (!prev) + k = list_first_entry_or_null(&kset->list, typeof(*k), entry); + else + k = list_next_entry(prev, entry); + + if (list_entry_is_head(k, &kset->list, entry)) + k = NULL; + + kobject_get(k); + spin_unlock(&kset->list_lock); + kobject_put(prev); + + return k; +} + static void kset_release(struct kobject *kobj) { struct kset *kset = container_of(kobj, struct kset, kobj); --- linux-nvidia-7.0.0.orig/mm/ksm.c +++ linux-nvidia-7.0.0/mm/ksm.c @@ -2814,9 +2814,14 @@ if (ksmd_should_run()) { sleep_ms = READ_ONCE(ksm_thread_sleep_millisecs); - wait_event_freezable_timeout(ksm_iter_wait, - sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs), - msecs_to_jiffies(sleep_ms)); + if (sleep_ms >= 1000) + wait_event_freezable_timeout(ksm_iter_wait, + sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs), + msecs_to_jiffies(round_jiffies_relative(sleep_ms))); + else + wait_event_freezable_timeout(ksm_iter_wait, + sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs), + msecs_to_jiffies(sleep_ms)); } else { wait_event_freezable(ksm_thread_wait, ksmd_should_run() || kthread_should_stop()); --- linux-nvidia-7.0.0.orig/mm/list_lru.c +++ linux-nvidia-7.0.0/mm/list_lru.c @@ -179,6 +179,7 @@ unlock_list_lru(l, false); return false; } +EXPORT_SYMBOL_GPL(list_lru_add); bool list_lru_add_obj(struct list_lru *lru, struct list_head *item) { @@ -216,6 +217,7 @@ unlock_list_lru(l, false); return false; } +EXPORT_SYMBOL_GPL(list_lru_del); bool list_lru_del_obj(struct list_lru *lru, struct list_head *item) { --- linux-nvidia-7.0.0.orig/mm/memory.c +++ linux-nvidia-7.0.0/mm/memory.c @@ -2235,6 +2235,7 @@ zap_page_range_single_batched(&tlb, vma, address, size, details); tlb_finish_mmu(&tlb); } +EXPORT_SYMBOL(zap_page_range_single); /** * zap_vma_ptes - remove ptes mapping the vma --- linux-nvidia-7.0.0.orig/mm/memory_hotplug.c +++ linux-nvidia-7.0.0/mm/memory_hotplug.c @@ -218,6 +218,17 @@ percpu_up_read(&mem_hotplug_lock); } +#ifdef CONFIG_LOCKDEP +void lockdep_assert_mems_held(void) +{ + /* See lockdep_assert_cpus_held() */ + if (system_state < SYSTEM_RUNNING) + return; + + percpu_rwsem_assert_held(&mem_hotplug_lock); +} +#endif + bool movable_node_enabled = false; static int mhp_default_online_type = -1; --- linux-nvidia-7.0.0.orig/mm/mmap_lock.c +++ linux-nvidia-7.0.0/mm/mmap_lock.c @@ -340,6 +340,7 @@ count_vm_vma_lock_event(VMA_LOCK_ABORT); return NULL; } +EXPORT_SYMBOL_GPL(lock_vma_under_rcu); static struct vm_area_struct *lock_next_vma_under_mmap_lock(struct mm_struct *mm, struct vma_iterator *vmi, --- linux-nvidia-7.0.0.orig/mm/vmalloc.c +++ linux-nvidia-7.0.0/mm/vmalloc.c @@ -3276,6 +3276,7 @@ NUMA_NO_NODE, GFP_KERNEL, __builtin_return_address(0)); } +EXPORT_SYMBOL(get_vm_area); struct vm_struct *get_vm_area_caller(unsigned long size, unsigned long flags, const void *caller) --- linux-nvidia-7.0.0.orig/net/ipv4/ip_tunnel.c +++ linux-nvidia-7.0.0/net/ipv4/ip_tunnel.c @@ -1252,7 +1252,7 @@ struct ip_tunnel_net *itn = net_generic(net, tunnel->ip_tnl_net_id); if (dev == itn->fb_tunnel_dev) - return -EINVAL; + return fan_has_map(&tunnel->fan) ? 0 : -EINVAL; t = ip_tunnel_find(itn, p, dev->type); --- linux-nvidia-7.0.0.orig/net/ipv4/ipip.c +++ linux-nvidia-7.0.0/net/ipv4/ipip.c @@ -101,6 +101,8 @@ #include #include #include +#include +#include #include #include @@ -275,6 +277,147 @@ } #endif +static struct ip_fan_map *ipip_fan_find_map(struct ip_tunnel *t, __be32 daddr) +{ + struct ip_fan_map *fan_map; + + rcu_read_lock(); + list_for_each_entry_rcu(fan_map, &t->fan.fan_maps, list) { + if (fan_map->overlay == + (daddr & inet_make_mask(fan_map->overlay_prefix))) { + rcu_read_unlock(); + return fan_map; + } + } + rcu_read_unlock(); + + return NULL; +} + +/* Determine fan tunnel endpoint to send packet to, based on the inner IP + * address. + * + * Given a /8 overlay and /16 underlay, for an overlay (inner) address + * Y.A.B.C, the transformation is F.G.A.B, where "F" and "G" are the first + * two octets of the underlay network (the network portion of a /16), "A" + * and "B" are the low order two octets of the underlay network host (the + * host portion of a /16), and "Y" is a configured first octet of the + * overlay network. + * + * E.g., underlay host 10.88.3.4/16 with an overlay of 99.0.0.0/8 would + * host overlay subnet 99.3.4.0/24. An overlay network datagram from + * 99.3.4.5 to 99.6.7.8, would be directed to underlay host 10.88.6.7, + * which hosts overlay network subnet 99.6.7.0/24. This transformation is + * described in detail further below. + * + * Using netmasks for the overlay and underlay other than /8 and /16, as + * shown above, can yield larger (or smaller) overlay subnets, with the + * trade-off of allowing fewer (or more) underlay hosts to participate. + * + * The size of each overlay network subnet is defined by the total of the + * network mask of the overlay plus the size of host portion of the + * underlay network. In the above example, /8 + /16 = /24. + * + * E.g., consider underlay host 10.99.238.5/20 and overlay 99.0.0.0/8. In + * this case, the network portion of the underlay is 10.99.224.0/20, and + * the host portion is 0.0.14.5 (12 bits). To determine the overlay + * network subnet, the 12 bits of host portion are left shifted 12 bits + * (/20 - /8) and ORed with the overlay subnet prefix. This yields an + * overlay subnet of 99.224.80/20, composed of 8 bits overlay, followed by + * 12 bits underlay. This yields 12 bits in the overlay network portion, + * allowing for 4094 addresses in each overlay network subnet. The + * trade-off is that fewer hosts may participate in the underlay network, + * as its host address size has shrunk from 16 bits (65534 addresses) in + * the first example to 12 bits (4094 addresses) here. + * + * For fewer hosts per overlay subnet (permitting a larger number of + * underlay hosts to participate), the underlay netmask may be made + * smaller. + * + * E.g., underlay host 10.111.1.2/12 (network 10.96.0.0/12, host portion + * is 0.15.1.2, 20 bits) with an overlay of 33.0.0.0/8 would left shift + * the 20 bits of host by 4 (so that it's highest order bit is adjacent to + * the lowest order bit of the /8 overlay). This yields an overlay subnet + * of 33.240.16.32/28 (8 bits overlay, 20 bits from the host portion of + * the underlay). This provides more addresses for the underlay network + * (approximately 2^20), but each host's segment of the overlay provides + * only 4 bits of addresses (14 usable). + * + * It is also possible to adjust the overlay subnet. + * + * For an overlay of 240.0.0.0/5 and underlay of 10.88.0.0/20, consider + * underlay host 10.88.129.2; the 12 bits of host, 0.0.1.2, are left + * shifted 15 bits (/20 - /5), yielding an overlay network of + * 240.129.0.0/17. An underlay host of 10.88.244.215 would yield an + * overlay network of 242.107.128.0/17. + * + * For an overlay of 100.64.0.0/10 and underlay of 10.224.220.0/24, for + * underlay host 10.224.220.10, the underlay host portion (.10) is left + * shifted 14 bits, yielding an overlay network subnet of 100.66.128.0/18. + * This would permit 254 addresses on the underlay, with each overlay + * segment providing approximately 2^14 - 2 addresses (16382). + * + * For packets being encapsulated, the overlay network destination IP + * address is deconstructed into its overlay and underlay-derived + * portions. The underlay portion (determined by the overlay mask and + * overlay subnet mask) is right shifted according to the size of the + * underlay network mask. This value is then ORed with the network + * portion of the underlay network to produce the underlay network + * destination for the encapsulated datagram. + * + * For example, using the initial example of underlay 10.88.3.4/16 and + * overlay 99.0.0.0/8, with underlay host 10.88.3.4/16 providing overlay + * subnet 99.3.4.0/24 with specfic host 99.3.4.5. A datagram from + * 99.3.4.5 to 99.6.7.8 would first have the underlay host derived portion + * of the address extracted. This is a number of bits equal to underlay + * network host portion. In the destination address, the highest order of + * these bits is one bit lower than the lowest order bit from the overlay + * network mask. + * + * Using the sample value, 99.6.7.8, the overlay mask is /8, and the + * underlay mask is /16 (leaving 16 bits for the host portion). The bits + * to be shifted are the middle two octets, 0.6.7.0, as this is 99.6.7.8 + * ANDed with the mask 0x00ffff00 (which is 16 bits, the highest order of + * which is 1 bit lower than the lowest order overlay address bit). + * + * These octets, 0.6.7.0, are then right shifted 8 bits, yielding 0.0.6.7. + * This value is then ORed with the underlay network portion, + * 10.88.0.0/16, providing 10.88.6.7 as the final underlay destination for + * the encapuslated datagram. + * + * Another transform using the final example: overlay 100.64.0.0/10 and + * underlay 10.224.220.0/24. Consider overlay address 100.66.128.1 + * sending a datagram to 100.66.200.5. In this case, 8 bits (the host + * portion size of 10.224.220.0/24) beginning after the 100.64/10 overlay + * prefix are masked off, yielding 0.2.192.0. This is right shifted 14 + * (32 - 10 - (32 - 24), i.e., the number of bits between the overlay + * network portion and the underlay host portion) bits, yielding 0.0.0.11. + * This is ORed with the underlay network portion, 10.224.220.0/24, giving + * the underlay destination of 10.224.220.11 for overlay destination + * 100.66.200.5. + */ +static int ipip_build_fan_iphdr(struct ip_tunnel *tunnel, struct sk_buff *skb, struct iphdr *iph) +{ + struct ip_fan_map *f_map; + u32 daddr, underlay; + + f_map = ipip_fan_find_map(tunnel, ip_hdr(skb)->daddr); + if (!f_map) + return -ENOENT; + + daddr = ntohl(ip_hdr(skb)->daddr); + underlay = ntohl(f_map->underlay); + if (!underlay) + return -EINVAL; + + *iph = tunnel->parms.iph; + iph->daddr = htonl(underlay | + ((daddr & ~f_map->overlay_mask) >> + (32 - f_map->overlay_prefix - + (32 - f_map->underlay_prefix)))); + return 0; +} + /* * This function assumes it is being called from dev_queue_xmit() * and that skb is filled properly by that function. @@ -285,6 +428,7 @@ struct ip_tunnel *tunnel = netdev_priv(dev); const struct iphdr *tiph = &tunnel->parms.iph; u8 ipproto; + struct iphdr fiph; if (!pskb_inet_may_pull(skb)) goto tx_error; @@ -308,6 +452,14 @@ if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP4)) goto tx_error; + if (fan_has_map(&tunnel->fan)) { + if (ipip_build_fan_iphdr(tunnel, skb, &fiph)) + goto tx_error; + tiph = &fiph; + } else { + tiph = &tunnel->parms.iph; + } + skb_set_inner_ipproto(skb, ipproto); if (tunnel->collect_md) @@ -397,6 +549,8 @@ static void ipip_tunnel_setup(struct net_device *dev) { + struct ip_tunnel *t = netdev_priv(dev); + dev->netdev_ops = &ipip_netdev_ops; dev->header_ops = &ip_tunnel_header_ops; @@ -409,6 +563,7 @@ dev->features |= IPIP_FEATURES; dev->hw_features |= IPIP_FEATURES; ip_tunnel_setup(dev, ipip_net_id); + INIT_LIST_HEAD(&t->fan.fan_maps); } static int ipip_tunnel_init(struct net_device *dev) @@ -461,6 +616,92 @@ *fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]); } +static void ipip_fan_flush_map(struct ip_tunnel *t) +{ + struct ip_fan_map *fan_map; + + list_for_each_entry_rcu(fan_map, &t->fan.fan_maps, list) { + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + } +} + +static int ipip_fan_del_map(struct ip_tunnel *t, __be32 overlay) +{ + struct ip_fan_map *fan_map; + + fan_map = ipip_fan_find_map(t, overlay); + if (!fan_map) + return -ENOENT; + + list_del_rcu(&fan_map->list); + kfree_rcu(fan_map, rcu); + + return 0; +} + +static int ipip_fan_add_map(struct ip_tunnel *t, struct ifla_fan_map *map) +{ + __be32 overlay_mask, underlay_mask; + struct ip_fan_map *fan_map; + + overlay_mask = inet_make_mask(map->overlay_prefix); + underlay_mask = inet_make_mask(map->underlay_prefix); + + if ((map->overlay & ~overlay_mask) || (map->underlay & ~underlay_mask)) + return -EINVAL; + + if (!(map->overlay & overlay_mask) && (map->underlay & underlay_mask)) + return -EINVAL; + + /* Special case: overlay 0 and underlay 0: flush all mappings */ + if (!map->overlay && !map->underlay) { + ipip_fan_flush_map(t); + return 0; + } + + /* Special case: overlay set and underlay 0: clear map for overlay */ + if (!map->underlay) + return ipip_fan_del_map(t, map->overlay); + + if (ipip_fan_find_map(t, map->overlay)) + return -EEXIST; + + fan_map = kmalloc(sizeof(*fan_map), GFP_KERNEL); + fan_map->underlay = map->underlay; + fan_map->overlay = map->overlay; + fan_map->underlay_prefix = map->underlay_prefix; + fan_map->overlay_mask = ntohl(overlay_mask); + fan_map->overlay_prefix = map->overlay_prefix; + + list_add_tail_rcu(&fan_map->list, &t->fan.fan_maps); + + return 0; +} + +static int ipip_netlink_fan(struct nlattr *data[], struct ip_tunnel *t, + struct ip_tunnel_parm_kern *parms) +{ + struct ifla_fan_map *map; + struct nlattr *attr; + int rem, rv; + + if (data == NULL || !data[IFLA_IPTUN_FAN_MAP]) + return 0; + + if (parms->iph.daddr) + return -EINVAL; + + nla_for_each_nested(attr, data[IFLA_IPTUN_FAN_MAP], rem) { + map = nla_data(attr); + rv = ipip_fan_add_map(t, map); + if (rv) + return rv; + } + + return 0; +} + static int ipip_newlink(struct net_device *dev, struct rtnl_newlink_params *params, struct netlink_ext_ack *extack) @@ -471,15 +712,19 @@ struct ip_tunnel_encap ipencap; struct ip_tunnel_parm_kern p; __u32 fwmark = 0; + int err; if (ip_tunnel_netlink_encap_parms(data, &ipencap)) { - int err = ip_tunnel_encap_setup(t, &ipencap); + err = ip_tunnel_encap_setup(t, &ipencap); if (err < 0) return err; } ipip_netlink_parms(data, &p, &t->collect_md, &fwmark); + err = ipip_netlink_fan(data, t, &p); + if (err < 0) + return err; return ip_tunnel_newlink(params->link_net ? : dev_net(dev), dev, tb, &p, fwmark); } @@ -493,9 +738,10 @@ struct ip_tunnel_parm_kern p; bool collect_md; __u32 fwmark = t->fwmark; + int err; if (ip_tunnel_netlink_encap_parms(data, &ipencap)) { - int err = ip_tunnel_encap_setup(t, &ipencap); + err = ip_tunnel_encap_setup(t, &ipencap); if (err < 0) return err; @@ -504,6 +750,9 @@ ipip_netlink_parms(data, &p, &collect_md, &fwmark); if (collect_md) return -EINVAL; + err = ipip_netlink_fan(data, t, &p); + if (err < 0) + return err; if (((dev->flags & IFF_POINTOPOINT) && !p.iph.daddr) || (!(dev->flags & IFF_POINTOPOINT) && p.iph.daddr)) @@ -541,6 +790,8 @@ nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + + /* IFLA_IPTUN_FAN_MAP */ + nla_total_size(sizeof(struct ifla_fan_map)) * 256 + 0; } @@ -573,6 +824,26 @@ if (tunnel->collect_md) if (nla_put_flag(skb, IFLA_IPTUN_COLLECT_METADATA)) goto nla_put_failure; + if (fan_has_map(&tunnel->fan)) { + struct nlattr *fan_nest; + struct ip_fan_map *fan_map; + + fan_nest = nla_nest_start(skb, IFLA_IPTUN_FAN_MAP); + if (!fan_nest) + goto nla_put_failure; + list_for_each_entry_rcu(fan_map, &tunnel->fan.fan_maps, list) { + struct ifla_fan_map map; + + map.underlay = fan_map->underlay; + map.underlay_prefix = fan_map->underlay_prefix; + map.overlay = fan_map->overlay; + map.overlay_prefix = fan_map->overlay_prefix; + if (nla_put(skb, IFLA_FAN_MAPPING, sizeof(map), &map)) + goto nla_put_failure; + } + nla_nest_end(skb, fan_nest); + } + return 0; nla_put_failure: @@ -593,6 +864,9 @@ [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, + + [__IFLA_IPTUN_VENDOR_BREAK ... IFLA_IPTUN_MAX] = { .type = NLA_BINARY }, + [IFLA_IPTUN_FAN_MAP] = { .type = NLA_NESTED }, }; static struct rtnl_link_ops ipip_link_ops __read_mostly = { @@ -642,6 +916,22 @@ .size = sizeof(struct ip_tunnel_net), }; +#ifdef CONFIG_SYSCTL +static struct ctl_table_header *ipip_fan_header; +static unsigned int ipip_fan_version = 3; + +static struct ctl_table ipip_fan_sysctls[] = { + { + .procname = "version", + .data = &ipip_fan_version, + .maxlen = sizeof(ipip_fan_version), + .mode = 0444, + .proc_handler = proc_dointvec, + }, +}; + +#endif /* CONFIG_SYSCTL */ + static int __init ipip_init(void) { int err; @@ -667,9 +957,22 @@ if (err < 0) goto rtnl_link_failed; +#ifdef CONFIG_SYSCTL + ipip_fan_header = register_net_sysctl(&init_net, "net/fan", + ipip_fan_sysctls); + if (!ipip_fan_header) { + err = -ENOMEM; + goto sysctl_failed; + } +#endif /* CONFIG_SYSCTL */ + out: return err; +#ifdef CONFIG_SYSCTL +sysctl_failed: + rtnl_link_unregister(&ipip_link_ops); +#endif /* CONFIG_SYSCTL */ rtnl_link_failed: #if IS_ENABLED(CONFIG_MPLS) xfrm4_tunnel_deregister(&mplsip_handler, AF_MPLS); @@ -684,6 +987,9 @@ static void __exit ipip_fini(void) { +#ifdef CONFIG_SYSCTL + unregister_net_sysctl_table(ipip_fan_header); +#endif /* CONFIG_SYSCTL */ rtnl_link_unregister(&ipip_link_ops); if (xfrm4_tunnel_deregister(&ipip_handler, AF_INET)) pr_info("%s: can't deregister tunnel\n", __func__); --- linux-nvidia-7.0.0.orig/net/ipv4/netfilter/arp_tables.c +++ linux-nvidia-7.0.0/net/ipv4/netfilter/arp_tables.c @@ -296,6 +296,17 @@ memcmp(&e->arp, &uncond, sizeof(uncond)) == 0; } +static bool next_offset_ok(const struct xt_table_info *t, unsigned int newpos) +{ + if (newpos > t->size - sizeof(struct arpt_entry)) + return false; + + if (newpos % __alignof__(struct arpt_entry) != 0) + return false; + + return true; +} + /* Figures out from what hook each rule can be called: returns 0 if * there are loops. Puts hook bitmask in comefrom. */ @@ -354,6 +365,8 @@ /* Move along one */ size = e->next_offset; + if (!next_offset_ok(newinfo, pos + size)) + return 0; e = entry0 + pos + size; if (pos + size >= newinfo->size) return 0; @@ -375,6 +388,10 @@ if (newpos >= newinfo->size) return 0; } + + if (!next_offset_ok(newinfo, newpos)) + return 0; + e = entry0 + newpos; e->counters.pcnt = pos; pos = newpos; --- linux-nvidia-7.0.0.orig/net/ipv4/netfilter/ip_tables.c +++ linux-nvidia-7.0.0/net/ipv4/netfilter/ip_tables.c @@ -361,6 +361,17 @@ else return verdict; } +static bool next_offset_ok(const struct xt_table_info *t, unsigned int newpos) +{ + if (newpos > t->size - sizeof(struct ipt_entry)) + return false; + + if (newpos % __alignof__(struct ipt_entry) != 0) + return false; + + return true; +} + /* Figures out from what hook each rule can be called: returns 0 if there are loops. Puts hook bitmask in comefrom. */ static int @@ -416,6 +427,8 @@ /* Move along one */ size = e->next_offset; + if (!next_offset_ok(newinfo, pos + size)) + return 0; e = entry0 + pos + size; if (pos + size >= newinfo->size) return 0; @@ -437,6 +450,10 @@ if (newpos >= newinfo->size) return 0; } + + if (!next_offset_ok(newinfo, newpos)) + return 0; + e = entry0 + newpos; e->counters.pcnt = pos; pos = newpos; --- linux-nvidia-7.0.0.orig/net/ipv6/netfilter/ip6_tables.c +++ linux-nvidia-7.0.0/net/ipv6/netfilter/ip6_tables.c @@ -379,6 +379,17 @@ else return verdict; } +static bool next_offset_ok(const struct xt_table_info *t, unsigned int newpos) +{ + if (newpos > t->size - sizeof(struct ip6t_entry)) + return false; + + if (newpos % __alignof__(struct ip6t_entry) != 0) + return false; + + return true; +} + /* Figures out from what hook each rule can be called: returns 0 if there are loops. Puts hook bitmask in comefrom. */ static int @@ -434,6 +445,8 @@ /* Move along one */ size = e->next_offset; + if (!next_offset_ok(newinfo, pos + size)) + return 0; e = entry0 + pos + size; if (pos + size >= newinfo->size) return 0; @@ -455,6 +468,10 @@ if (newpos >= newinfo->size) return 0; } + + if (!next_offset_ok(newinfo, newpos)) + return 0; + e = entry0 + newpos; e->counters.pcnt = pos; pos = newpos; --- linux-nvidia-7.0.0.orig/net/rds/ib_send.c +++ linux-nvidia-7.0.0/net/rds/ib_send.c @@ -503,7 +503,7 @@ int flow_controlled = 0; int nr_sig = 0; - BUG_ON(off % RDS_FRAG_SIZE); + BUG_ON(!conn->c_loopback && off % RDS_FRAG_SIZE); BUG_ON(hdr_off != 0 && hdr_off != sizeof(struct rds_header)); /* Do not send cong updates to IB loopback */ --- linux-nvidia-7.0.0.orig/net/rfkill/core.c +++ linux-nvidia-7.0.0/net/rfkill/core.c @@ -82,7 +82,6 @@ wait_queue_head_t read_wait; u32 event_count; bool input_handler; - u8 max_size; }; @@ -1183,8 +1182,6 @@ if (!data) return -ENOMEM; - data->max_size = RFKILL_EVENT_SIZE_V1; - INIT_LIST_HEAD(&data->events); mutex_init(&data->mtx); init_waitqueue_head(&data->read_wait); @@ -1265,7 +1262,6 @@ list); sz = min_t(unsigned long, sizeof(ev->ev), count); - sz = min_t(unsigned long, sz, data->max_size); ret = sz; if (copy_to_user(buf, &ev->ev, sz)) ret = -EFAULT; @@ -1281,7 +1277,6 @@ static ssize_t rfkill_fop_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) { - struct rfkill_data *data = file->private_data; struct rfkill *rfkill; struct rfkill_event_ext ev; int ret; @@ -1296,7 +1291,6 @@ * our API version even in a write() call, if it cares. */ count = min(count, sizeof(ev)); - count = min_t(size_t, count, data->max_size); if (copy_from_user(&ev, buf, count)) return -EFAULT; @@ -1356,47 +1350,31 @@ return 0; } +#ifdef CONFIG_RFKILL_INPUT static long rfkill_fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct rfkill_data *data = file->private_data; - int ret = -ENOTTY; - u32 size; if (_IOC_TYPE(cmd) != RFKILL_IOC_MAGIC) return -ENOTTY; + if (_IOC_NR(cmd) != RFKILL_IOC_NOINPUT) + return -ENOSYS; + mutex_lock(&data->mtx); - switch (_IOC_NR(cmd)) { -#ifdef CONFIG_RFKILL_INPUT - case RFKILL_IOC_NOINPUT: - if (!data->input_handler) { - if (atomic_inc_return(&rfkill_input_disabled) == 1) - printk(KERN_DEBUG "rfkill: input handler disabled\n"); - data->input_handler = true; - } - ret = 0; - break; -#endif - case RFKILL_IOC_MAX_SIZE: - if (get_user(size, (__u32 __user *)arg)) { - ret = -EFAULT; - break; - } - if (size < RFKILL_EVENT_SIZE_V1 || size > U8_MAX) { - ret = -EINVAL; - break; - } - data->max_size = size; - ret = 0; - break; - default: - break; + + if (!data->input_handler) { + if (atomic_inc_return(&rfkill_input_disabled) == 1) + printk(KERN_DEBUG "rfkill: input handler disabled\n"); + data->input_handler = true; } + mutex_unlock(&data->mtx); - return ret; + return 0; } +#endif static const struct file_operations rfkill_fops = { .owner = THIS_MODULE, @@ -1405,8 +1383,10 @@ .write = rfkill_fop_write, .poll = rfkill_fop_poll, .release = rfkill_fop_release, +#ifdef CONFIG_RFKILL_INPUT .unlocked_ioctl = rfkill_fop_ioctl, .compat_ioctl = compat_ptr_ioctl, +#endif }; #define RFKILL_NAME "rfkill" --- linux-nvidia-7.0.0.orig/rust/Makefile +++ linux-nvidia-7.0.0/rust/Makefile @@ -52,9 +52,9 @@ always-$(CONFIG_RUST) += $(libmacros_name) $(libpin_init_internal_name) # `$(rust_flags)` is passed in case the user added `--sysroot`. -rustc_sysroot := $(shell MAKEFLAGS= $(RUSTC) $(rust_flags) --print sysroot) +rustc_sysroot := $(shell MAKEFLAGS= $(RUSTC) $(rust_flags) --version | awk '{print "/usr/src/" $$1 "-" $$2}') rustc_host_target := $(shell $(RUSTC) --version --verbose | grep -F 'host: ' | cut -d' ' -f2) -RUST_LIB_SRC ?= $(rustc_sysroot)/lib/rustlib/src/rust/library +RUST_LIB_SRC ?= $(rustc_sysroot)/library ifneq ($(quiet),) rust_test_quiet=-q --- linux-nvidia-7.0.0.orig/scripts/Makefile.modinst +++ linux-nvidia-7.0.0/scripts/Makefile.modinst @@ -105,8 +105,11 @@ sig-key := $(CONFIG_MODULE_SIG_KEY) endif quiet_cmd_sign = SIGN $@ - cmd_sign = $(objtree)/scripts/sign-file $(CONFIG_MODULE_SIG_HASH) "$(sig-key)" $(objtree)/certs/signing_key.x509 $@ \ - $(if $(KBUILD_EXTMOD),|| true) + cmd_sign = if test -e $(srctree)/debian/scripts/sign-module && \ + $(srctree)/debian/scripts/sign-module $@ ; \ + then $(objtree)/scripts/sign-file $(CONFIG_MODULE_SIG_HASH) "$(sig-key)" $(objtree)/certs/signing_key.x509 $@ \ + $(if $(KBUILD_EXTMOD),|| true) ; \ + fi ifeq ($(sign-only),) --- linux-nvidia-7.0.0.orig/scripts/insert-sys-cert.c +++ linux-nvidia-7.0.0/scripts/insert-sys-cert.c @@ -7,7 +7,8 @@ * This software may be used and distributed according to the terms * of the GNU General Public License, incorporated herein by reference. * - * Usage: insert-sys-cert [-s -b -c + * Usage: insert-sys-cert [-s ] -b -c + * [-s ] -z -c */ #define _GNU_SOURCE @@ -257,6 +258,169 @@ return buf; } +static void get_payload_info(char *bzimage, int *offset, int *size) +{ + unsigned int system_offset; + unsigned char setup_sectors; + + setup_sectors = bzimage[0x1f1] + 1; + system_offset = setup_sectors * 512; + *offset = system_offset + *((int*)&bzimage[0x248]); + *size = *((int*)&bzimage[0x24c]); +} + +static void update_payload_info(char* bzimage, int new_size) +{ + int offset, size; + get_payload_info(bzimage, &offset, &size); + *((int*)&bzimage[0x24c]) = new_size; + if (new_size < size) + memset(bzimage + offset + new_size, 0, size - new_size); +} + +struct zipper { + unsigned char pattern[10]; + int length; + char *command; + char *compress; +}; + +struct zipper zippers[] = { + {{0x7F,'E','L','F'}, 4, "cat", "cat"}, + {{0x1F,0x8B}, 2, "gunzip", "gzip -n -f -9"}, + {{0xFD,'7','z','X','Z',0}, 6, "unxz", "xz"}, + {{'B','Z','h'},3, "bunzip2", "bzip2 -9"}, + {{0xFF,'L','Z','M','A',0}, 6, "unlzma", "lzma -9"}, + {{0xD3,'L','Z','O',0,'\r','\n',0x20,'\n'}, 9, "lzop -d", "lzop -9"} +}; + +static struct zipper* get_zipper(char *p) { + int i; + for (i = 0; i < sizeof(zippers)/sizeof(struct zipper); i++) { + if (memcmp(p, zippers[i].pattern, zippers[i].length) == 0) + return &zippers[i]; + } + return NULL; +} + +/* + * This only works for x86 bzImage + */ +static void extract_vmlinux(char *bzimage, int bzimage_size, + char **file, struct zipper **zipper) +{ + int r; + char src[15] = "vmlinux-XXXXXX"; + char dest[15] = "vmlinux-XXXXXX"; + char cmd[100]; + int src_fd, dest_fd; + int offset, size; + struct zipper *z; + + /* TODO: verify that bzImage is supported */ + + get_payload_info(bzimage, &offset, &size); + z = get_zipper(bzimage + offset); + if (z == NULL) { + err("Unable to determine the compression of vmlinux\n"); + return; + } + + src_fd = mkstemp(src); + if (src_fd == -1) { + perror("Could not create temp file"); + return; + } + + r = write(src_fd, bzimage + offset, size); + if (r != size) { + perror("Could not write vmlinux"); + return; + } + dest_fd = mkstemp(dest); + if (dest_fd == -1) { + perror("Could not create temp file"); + return; + } + + snprintf(cmd, sizeof(cmd), "%s <%s >%s", z->command, src, dest); + info("Executing: %s\n", cmd); + r = system(cmd); + if (r!=0) + warn("Possible errors when extracting\n"); + + r = remove(src); + if (r!=0) + perror(src); + + *file = strdup(dest); + *zipper = z; +} + +static void repack_image(char *bzimage, int bzimage_size, + char* vmlinux_file, struct zipper *z) +{ + char tmp[15] = "vmlinux-XXXXXX"; + char cmd[100]; + int fd; + struct stat st; + int new_size; + int r; + int offset, size; + + get_payload_info(bzimage, &offset, &size); + + fd = mkstemp(tmp); + if (fd == -1) { + perror("Could not create temp file"); + return; + } + snprintf(cmd, sizeof(cmd), "%s <%s >%s", + z->compress, vmlinux_file, tmp); + + info("Executing: %s\n", cmd); + r = system(cmd); + if (r!=0) + warn("Possible errors when compressing\n"); + + r = remove(vmlinux_file); + if (r!=0) + perror(vmlinux_file); + + if (fstat(fd, &st)) { + perror("Could not determine file size"); + close(fd); + + } + new_size = st.st_size; + if (new_size > size) { + err("Increase in compressed size is not supported.\n"); + err("Old size was %d, new size is %d\n", size, new_size); + exit(EXIT_FAILURE); + } + + r = read(fd, bzimage + offset, new_size); + if (r != new_size) + perror(tmp); + + r = remove(tmp); + if (r!=0) + perror(tmp); + + /* x86 specific patching of bzimage */ + update_payload_info(bzimage, new_size); + + /* TODO: update CRC */ + +} + +static void fill_random(unsigned char *p, int n) { + srand(0); + int i; + for (i = 0; i < n; i++) + p[i] = rand(); +} + static void print_sym(Elf_Ehdr *hdr, struct sym *s) { info("sym: %s\n", s->name); @@ -267,18 +431,23 @@ static void print_usage(char *e) { - printf("Usage %s [-s ] -b -c \n", e); + printf("Usage: %s [-s ] -b -c \n", e); + printf(" %s [-s ] -z -c \n", e); } int main(int argc, char **argv) { char *system_map_file = NULL; char *vmlinux_file = NULL; + char *bzimage_file = NULL; char *cert_file = NULL; int vmlinux_size; + int bzimage_size; int cert_size; Elf_Ehdr *hdr; char *cert; + char *bzimage = NULL; + struct zipper *z = NULL; FILE *system_map; unsigned long *lsize; int *used; @@ -286,7 +455,7 @@ Elf_Shdr *symtab = NULL; struct sym cert_sym, lsize_sym, used_sym; - while ((opt = getopt(argc, argv, "b:c:s:")) != -1) { + while ((opt = getopt(argc, argv, "b:z:c:s:")) != -1) { switch (opt) { case 's': system_map_file = optarg; @@ -294,6 +463,9 @@ case 'b': vmlinux_file = optarg; break; + case 'z': + bzimage_file = optarg; + break; case 'c': cert_file = optarg; break; @@ -302,7 +474,9 @@ } } - if (!vmlinux_file || !cert_file) { + if (!cert_file || + (!vmlinux_file && !bzimage_file) || + (vmlinux_file && bzimage_file)) { print_usage(argv[0]); exit(EXIT_FAILURE); } @@ -311,6 +485,16 @@ if (!cert) exit(EXIT_FAILURE); + if (bzimage_file) { + bzimage = map_file(bzimage_file, &bzimage_size); + if (!bzimage) + exit(EXIT_FAILURE); + + extract_vmlinux(bzimage, bzimage_size, &vmlinux_file, &z); + if (!vmlinux_file) + exit(EXIT_FAILURE); + } + hdr = map_file(vmlinux_file, &vmlinux_size); if (!hdr) exit(EXIT_FAILURE); @@ -386,7 +570,7 @@ } /* If the existing cert is the same, don't overwrite */ - if (cert_size == *used && + if (cert_size > 0 && cert_size == *used && strncmp(cert_sym.content, cert, cert_size) == 0) { warn("Certificate was already inserted.\n"); exit(EXIT_SUCCESS); @@ -396,9 +580,11 @@ warn("Replacing previously inserted certificate.\n"); memcpy(cert_sym.content, cert, cert_size); + if (cert_size < cert_sym.size) - memset(cert_sym.content + cert_size, - 0, cert_sym.size - cert_size); + /* This makes the reserved space incompressable */ + fill_random(cert_sym.content + cert_size, + cert_sym.size - cert_size); *lsize = *lsize + cert_size - *used; *used = cert_size; @@ -406,5 +592,15 @@ cert_sym.address); info("Used %d bytes out of %d bytes reserved.\n", *used, cert_sym.size); + + if (munmap(hdr, vmlinux_size) == -1) { + perror(vmlinux_file); + exit(EXIT_FAILURE); + } + + if (bzimage) { + repack_image(bzimage, bzimage_size, vmlinux_file, z); + } + exit(EXIT_SUCCESS); } --- linux-nvidia-7.0.0.orig/scripts/kconfig/lkc.h +++ linux-nvidia-7.0.0/scripts/kconfig/lkc.h @@ -44,7 +44,9 @@ /* confdata.c and expr.c */ static inline void xfwrite(const void *str, size_t len, size_t count, FILE *out) { - assert(len != 0); + //assert(len != 0); + if (len == 0) + return; if (fwrite(str, len, count, out) != count) fprintf(stderr, "Error in writing or end of file.\n"); --- linux-nvidia-7.0.0.orig/scripts/rust_is_available.sh +++ linux-nvidia-7.0.0/scripts/rust_is_available.sh @@ -267,8 +267,8 @@ # Check that the source code for the `core` standard library exists. # # `$KRUSTFLAGS` is passed in case the user added `--sysroot`. -rustc_sysroot=$("$RUSTC" $KRUSTFLAGS --print sysroot) -rustc_src=${RUST_LIB_SRC:-"$rustc_sysroot/lib/rustlib/src/rust/library"} +rustc_sysroot=$("$RUSTC" $KRUSTFLAGS --version | awk '{print "/usr/src/" $1 "-" $2}') +rustc_src=${RUST_LIB_SRC:-"$rustc_sysroot/library"} rustc_src_core="$rustc_src/core/src/lib.rs" if [ ! -e "$rustc_src_core" ]; then echo >&2 "***" --- linux-nvidia-7.0.0.orig/security/Kconfig +++ linux-nvidia-7.0.0/security/Kconfig @@ -72,6 +72,15 @@ For complete descriptions of memory sealing, please see Documentation/userspace-api/mseal.rst +config SECURITY_PERF_EVENTS_RESTRICT + bool "Restrict unprivileged use of performance events" + depends on PERF_EVENTS + help + If you say Y here, the kernel.perf_event_paranoid sysctl + will be set to 3 by default, and no unprivileged use of the + perf_event_open syscall will be permitted unless it is + changed. + config SECURITY bool "Enable different security models" depends on SYSFS --- linux-nvidia-7.0.0.orig/security/apparmor/Kconfig +++ linux-nvidia-7.0.0/security/apparmor/Kconfig @@ -104,6 +104,29 @@ includes policy, and has some form of integrity check. Disabling the check will speed up policy loads. +config SECURITY_APPARMOR_RESTRICT_USERNS + bool "Restrict user namespace creation to confined domains" + depends on SECURITY_APPARMOR && USER_NS + default y + help + This options allows controlling whether apparmor restricts + the creation of new user namespaces to confined tasks by + default. If set unconfined tasks without CAP_SYS_ADMIN + will not be allowed to create new user namespaces. Confined + tasks ability to create new user namespaces will be controlled + by their profile. + +config SECURITY_APPARMOR_PACKET_MEDIATION_ENABLED + bool "Enable AppArmor packet mediation by defauit + depends on SECURITY_APPARMOR && NETWORK_SECMARK + default n + help + This options controls whether apparmor packet mediation is + enabled by default. If disabled AppArmor will not do + mediation of packets, mediation of interfaces, or labeling + of packets. This just provides the default value, and it can + be changed via the sysctl apparmor_packet_mediation. + config SECURITY_APPARMOR_KUNIT_TEST tristate "Build KUnit tests for policy_unpack.c" if !KUNIT_ALL_TESTS depends on KUNIT && SECURITY_APPARMOR --- linux-nvidia-7.0.0.orig/security/apparmor/Makefile +++ linux-nvidia-7.0.0/security/apparmor/Makefile @@ -6,7 +6,7 @@ apparmor-y := apparmorfs.o audit.o capability.o task.o ipc.o lib.o match.o \ path.o domain.o policy.o policy_unpack.o procattr.o lsm.o \ resource.o secid.o file.o policy_ns.o label.o mount.o net.o \ - policy_compat.o af_unix.o + policy_compat.o af_unix.o af_inet.o notify.o apparmor-$(CONFIG_SECURITY_APPARMOR_HASH) += crypto.o obj-$(CONFIG_SECURITY_APPARMOR_KUNIT_TEST) += apparmor_policy_unpack_test.o --- linux-nvidia-7.0.0.orig/security/apparmor/af_inet.c +++ linux-nvidia-7.0.0/security/apparmor/af_inet.c @@ -0,0 +1,1583 @@ +/* + * AppArmor security module + * + * This file contains AppArmor inet fine grained mediation + * + * Copyright 2024 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "include/audit.h" +#include "include/af_inet.h" +#include "include/apparmor.h" +#include "include/file.h" +#include "include/label.h" +#include "include/net.h" +#include "include/policy.h" +#include "include/cred.h" +#include "include/secid.h" + + +static inline aa_state_t RULE_MEDIATES_SK(struct aa_ruleset *rules, + const struct sock *sk) +{ + return RULE_MEDIATES_NET(rules); +} + + +enum addr_type { + ADDR_LOCAL = 0, + ADDR_LOCAL_PRIV = 1, + ADDR_REMOTE = 2, +}; + +struct match_addr { + const char *addrp; + enum addr_type addrtype; + int len; + __be16 port; +}; + +struct stored_match_addr { + union { + struct sockaddr addr; + struct sockaddr_in addr4; + struct sockaddr_in6 addr6; + }; + int addrlen; + struct match_addr maddr; +}; + +static void set_ad_create(struct apparmor_audit_data *ad, + int family, int type, int protocol) +{ + ad->common.u.net->family = family; + ad->net.type = type; + ad->net.protocol = protocol; +} + +static int set_ad_addr(struct apparmor_audit_data *ad, + u16 family, bool source, struct match_addr *maddr) +{ + ad->common.u.net->family = family; + + if (source) { + ad->common.u.net->sport = maddr->port; + if (maddr->addrp) { + if (family == AF_INET) + //ad.u.net->v4info.saddr = addr4->sin_addr.s_addr; + ad->common.u.net->v4info.saddr = *(__be32 *)maddr->addrp; + else + //ad.u.net->v4info.saddr = addr6->sin6_addr.s6_addr; + ad->common.u.net->v6info.saddr = *(struct in6_addr *)maddr->addrp; + } + } else { + ad->common.u.net->dport = maddr->port; + if (maddr->addrp) { + if (family == AF_INET) + //ad.u.net->v4info.saddr = addr4->sin_addr.s_addr; + ad->common.u.net->v4info.daddr = *(__be32 *)maddr->addrp; + else + //ad.u.net->v4info.saddr = addr6->sin6_addr.s6_addr; + ad->common.u.net->v6info.daddr = *(struct in6_addr *)maddr->addrp; + } + } + return 0; +} + +/* returns 0 on success +* raw_port - if set raw_port (protocol) when SOCK_RAW */ +static int map_addr(struct sockaddr *addr, int addrlen, u16 raw_port, + enum addr_type addrtype, struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct sockaddr_in *addr4 = NULL; + struct sockaddr_in6 *addr6 = NULL; + + AA_BUG(!maddr); + + maddr->addrtype = addrtype; + if (!addr || addrlen < offsetofend(struct sockaddr, sa_family)) { + maddr->addrp = NULL; + maddr->port = 0; + maddr->len = 0; + return 0; + } + + /* + * its possibly to have sk->sk_family == PF_INET6 and + * addr->sa_family == AF_INET. sk_family is used for socket + * mediation, sa_family for when we have address ... + */ + switch (addr->sa_family) { + case AF_INET: + addr4 = (struct sockaddr_in *)addr; + if (addrlen < sizeof(struct sockaddr_in)) + return -EINVAL; + maddr->port = addr4->sin_port; + maddr->addrp = (char *)&addr4->sin_addr.s_addr; + maddr->len = 4; + break; + case AF_INET6: + addr6 = (struct sockaddr_in6 *)addr; + if (addrlen < SIN6_LEN_RFC2133) + return -EINVAL; + maddr->port = addr6->sin6_port; + maddr->addrp = (char *)&addr6->sin6_addr.s6_addr; + maddr->len = 16; + break; + default: + return -EAFNOSUPPORT; + } + /* per ip spec, && sk->sk_type == SOCK_RAW*/ + if (raw_port && addrtype != ADDR_REMOTE) + maddr->port = htons(raw_port); + if (ad) + set_ad_addr(ad, addr->sa_family, addrtype != ADDR_REMOTE, maddr); + + return 0; +} + +/* -ENOTCONN if not connected */ +static int map_sock_addr(struct socket *sock, enum addr_type addrtype, + struct stored_match_addr *maddr, + struct apparmor_audit_data *ad) +{ + /* do we need early bailout for !family ... */ + maddr->addrlen = sock->ops->getname(sock, (struct sockaddr *) &maddr->addr, addrtype != ADDR_REMOTE ? 0 : 1); + if (maddr->addrlen == -ENOTCONN) { + maddr->addrlen = 0; + return map_addr(NULL, 0, 0, addrtype, &maddr->maddr, ad); + } else if (maddr->addrlen < 0) + return maddr->addrlen; + return map_addr(&maddr->addr, maddr->addrlen, 0, addrtype, + &maddr->maddr, ad); +} + +/* TODO: combine with connect map addr */ +/* TODO: raw_port */ +static int bind_map_addr(const struct sock *sk, struct sockaddr *addr, + int addrlen, + struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct sockaddr_in *addr4 = NULL; + struct sockaddr_in6 *addr6 = NULL; + u16 family; + + AA_BUG(!addr); + AA_BUG(!maddr); + + if (addrlen < offsetofend(struct sockaddr, sa_family)) + return -EINVAL; + + maddr->addrtype = ADDR_LOCAL; + /* + * its possibly to have sk->sk_family == PF_INET6 and + * addr->sa_family == AF_INET. sk_family is used for socket + * mediation, sa_family for when we have address ... + */ + family = addr->sa_family; + switch (addr->sa_family) { + case AF_UNSPEC: + if (sk->sk_family == PF_INET6) { + /* Length check from inet6_bind_sk() */ + if (addrlen < SIN6_LEN_RFC2133) + return -EINVAL; + /* Family check from __inet6_bind() */ + return -EAFNOSUPPORT; + } + /* see __inet_bind(), we only want to allow + * AF_UNSPEC if the address is INADDR_ANY + */ + if (addr4->sin_addr.s_addr != htonl(INADDR_ANY)) + return -EAFNOSUPPORT; + family = AF_INET; + fallthrough; + case AF_INET: + addr4 = (struct sockaddr_in *)addr; + if (addrlen < sizeof(struct sockaddr_in)) + return -EINVAL; + maddr->port = addr4->sin_port; + maddr->addrp = (char *)&addr4->sin_addr.s_addr; + maddr->len = 4; + break; + case AF_INET6: + addr6 = (struct sockaddr_in6 *)addr; + if (addrlen < SIN6_LEN_RFC2133) + return -EINVAL; + maddr->port = addr6->sin6_port; + maddr->addrp = (char *)&addr6->sin6_addr.s6_addr; + maddr->len = 16; + break; + default: + return -EAFNOSUPPORT; + } + + if (ad) + set_ad_addr(ad, family, true, maddr); + + return 0; +} + +/* only continue match if + * insufficient current perms at current state + * indicates there are more perms in later state + * Returns: perms struct if early match + */ +static struct aa_perms *early_match(struct aa_policydb *policy, + aa_state_t state, u32 request) +{ + struct aa_perms *p; + + p = aa_lookup_perms(policy, state); + if (((p->allow & request) != request) && (p->allow & AA_CONT_MATCH)) + return NULL; + return p; +} + +static int do_perms(struct aa_profile *profile, aa_state_t state, u32 request, + struct aa_perms *p, struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms perms; + + AA_BUG(!profile); + + if (state || !p) + p = aa_lookup_perms(rules->policy, state); + perms = *p; + aa_apply_modes_to_perms(profile, &perms); + return aa_check_perms(profile, &perms, request, ad, + audit_net_cb); +} + +static aa_state_t match_addr(struct aa_dfa *dfa, aa_state_t state, + struct match_addr *maddr) +{ + char l = (char) maddr->addrtype; + + state = aa_dfa_match_len(dfa, state, &l, 1); + state = aa_dfa_match_len(dfa, state, (char *)&maddr->port, 2); + if (maddr->len == 0 && !maddr->addrp) { + l = 0; + } else if (maddr->len == 4) { + l = 1; + } else if (maddr->len == 16) { + l = 2; + } else { + AA_BUG("address length unsupported"); + return 0; + } + state = aa_dfa_match_len(dfa, state, &l, 1); + if (maddr->addrp) + state = aa_dfa_match_len(dfa, state, maddr->addrp, maddr->len); + /* null transition between addr and label */ + state = aa_dfa_null_transition(dfa, state); + + return state; +} + + +static aa_state_t match_addr_info(struct aa_dfa *dfa, aa_state_t state, + struct match_addr *maddr, + const char **info) +{ + state = match_addr(dfa, state, maddr); + if (!state) { + *info = maddr->addrtype == ADDR_REMOTE ? + "failed remote addr match" : + "failed local addr match"; + } + + return state; +} + +static aa_state_t match_addr_label(struct aa_policydb *policy, aa_state_t state, + u32 request, struct match_addr *maddr, + struct aa_perms **p, const char **info) +{ + state = match_addr_info(policy->dfa, state, maddr, info); + *p = early_match(policy, state, request); + if (!*p) { + /* TODO: actual label match: */ + if (!state) { + *info = maddr->addrtype == ADDR_REMOTE ? + "failed remote label match" : + "failed local label match"; + } + + /* null transition after label match */ + state = aa_dfa_null_transition(policy->dfa, state); + } + + return state; +} + + +static aa_state_t match_to_sk(struct aa_policydb *policy, aa_state_t state, + u32 request, const struct sock *sk, + struct match_addr *maddr, + struct aa_perms **p, const char **info) +{ + *p = NULL; + state = aa_match_to_prot(policy, state, request, sk->sk_family, + sk->sk_type, sk->sk_protocol, p, info); + if (*p || !state) + return state; + return match_addr_label(policy, state, request, maddr, p, info); +} + +enum cmd_type { + CMD_ADDR = 1, + CMD_LISTEN = 2, + CMD_OPT = 4, +}; + +static inline aa_state_t match_to_cmd(struct aa_policydb *policy, + aa_state_t state, u32 request, + const struct sock *sk, enum cmd_type cmd, + struct match_addr *maddr, + struct aa_perms **p, const char **info) +{ + state = match_to_sk(policy, state, request, sk, maddr, p, info); + if (!*p && state) { + char c = (char) cmd; + state = aa_dfa_match_len(policy->dfa, state, &c, 1); + if (!state) + *info = "failed cmd selection match"; + } + + return state; +} + +/* +static int match_label(struct aa_profile *profile, struct aa_profile *peer, + aa_state_t state, u32 request, + struct apparmor_audit_data *ad) +{ + AA_BUG(!profile); + AA_BUG(!peer); + + ad->peer = &peer->label; + + if (state) { + state = aa_dfa_match(profile->policy.dfa, state, + peer->base.hname); + if (!state) + ad->info = "failed peer label match"; + } + return do_perms(profile, state, request, ad); +} +*/ + +/* ---------------------------------------------------------------------- */ + + + +static inline int profile_sk_perm(struct aa_profile *profile, u32 request, + const struct sock *sk, + struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + + state = RULE_MEDIATES_NET(rules); + if (state) { + state = match_to_sk(rules->policy, state, request, sk, + maddr, &p, &ad->info); + return do_perms(profile, state, request, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, request, sk); +} + +/* no kernel_t bailout */ +static int profile_create_perm(struct aa_profile *profile, int family, + int type, int protocol, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + + state = RULE_MEDIATES_NET(rules); + if (state) { + state = aa_match_to_prot(rules->policy, state, AA_MAY_CREATE, + family, type, protocol, &p, &ad->info); + return do_perms(profile, state, AA_MAY_CREATE, p, ad); + } + + return aa_profile_af_compat_perm(profile, ad, AA_MAY_CREATE, family, + type); +} + + +/* sendmsg/rcvmsg/connect */ +static int profile_remote_perm(struct aa_profile *profile, + const struct sock *sk, + u32 request, struct match_addr *raddr, + struct match_addr *laddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!raddr); + AA_BUG(!laddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (!state) + return aa_profile_af_sk_perm(profile, ad, request, sk); + + /* TODO: deal with sa_family vs. sk_family */ + state = match_to_cmd(rules->policy, state, request, sk, CMD_ADDR, + raddr, &p, &ad->info); + if (state && !p) + /* check if perm is restricted to a pairing */ + state = match_addr_label(rules->policy, state, request, + laddr, &p, &ad->info); + return do_perms(profile, state, request, p, ad); +} + +static int profile_bind_perm(struct aa_profile *profile, + const struct sock *sk, + struct match_addr *maddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + unsigned short sport; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (!state) + return aa_profile_af_sk_perm(profile, ad, AA_MAY_BIND, sk); + + /* + * its possibly to have sk->sk_family == PF_INET6 and + * addr->sa_family == AF_INET + */ + sport = ntohs(maddr->port); + if (sport) { + if (inet_port_requires_bind_service(sock_net(sk), sport)) { + /* cap NET_BIND_SERVICE will get raised */ + maddr->addrtype = ADDR_LOCAL_PRIV; + } + } + state = match_to_sk(rules->policy, state, AA_MAY_BIND, sk, + maddr, &p, &ad->info); + return do_perms(profile, state, AA_MAY_BIND, p, ad); +} + +static int profile_listen_perm(struct aa_profile *profile, + const struct sock *sk, + struct match_addr *maddr, int backlog, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (state) { + __be16 b = htons(backlog); + + state = match_to_cmd(rules->policy, state, AA_MAY_LISTEN, sk, + CMD_LISTEN, maddr, &p, &ad->info); + if (state && !p) { + state = aa_dfa_match_len(rules->policy->dfa, state, + (char *) &b, 2); + if (!state) + ad->info = "failed listen backlog match"; + } + return do_perms(profile, state, AA_MAY_LISTEN, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, AA_MAY_LISTEN, sk); +} + +static inline int profile_accept_perm(struct aa_profile *profile, + const struct sock *sk, + struct match_addr *maddr, + const struct sock *newsk, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + /* AA_BUG(!newsk); newsk can be null here, since not using atm ... */ + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (state) { + state = match_to_sk(rules->policy, state, AA_MAY_ACCEPT, sk, + maddr, &p, &ad->info); + return do_perms(profile, state, AA_MAY_ACCEPT, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, AA_MAY_ACCEPT, sk); +} + +/* getopt/setopt */ +static int profile_opt_perm(struct aa_profile *profile, u32 request, + const struct sock *sk, struct match_addr *maddr, + int level, int optname, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!maddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SK(rules, sk); + if (state) { + __be16 l = htons(level); + __be16 n = htons(optname); + + state = match_to_cmd(rules->policy, state, request, sk, + CMD_OPT, maddr, &p, &ad->info); + if (state && !p) { + state = aa_dfa_match_len(rules->policy->dfa, state, + (char *) &l, 2); + state = aa_dfa_match_len(rules->policy->dfa, state, + (char *) &n, 2); + if (!state) + ad->info = "failed sockopt match"; + } + return do_perms(profile, state, request, p, ad); + } + + return aa_profile_af_sk_perm(profile, ad, request, sk); +} + +/* ---------------------------------------------------------------------- */ + +// TODO: cleanup init to use recursion, so we can have N init fns, in 1 macro +// TODO: lift DEFINE_AUDIT out of macro into init fn??? + +/* no kernel_t bailout */ +#define label_sk_has_perm2(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, XXXX, YYYY, CALLBACKFN) \ +({ \ + int __EERROR = 0; \ + if (label_mediates(LABEL, AA_CLASS_NET)) { \ + struct aa_profile *PROFILE; \ + DEFINE_AUDIT_SK(AAD, OP, CRED, SOCKSK); \ + (AAD).subj_cred = (CRED); \ + (AAD).request = (REQUEST); \ + __EERROR = (XXXX); \ + if (__EERROR == 0) { \ + __EERROR = (YYYY); \ + if (__EERROR == 0) { \ + __EERROR = fn_for_each(label, PROFILE, \ + (CALLBACKFN)); \ + } \ + } \ + } \ + __EERROR; \ +}) + +/* no kernel_t bailout */ +#define label_sk_has_perm(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, CALLBACKFN) \ + label_sk_has_perm2(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, \ + 0, 0, CALLBACKFN) + +/* no kernel_t bailout */ +#define label_sk_has_perm1(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, XXXX, CALLBACKFN) \ + label_sk_has_perm2(CRED, LABEL, SOCKSK, OP, REQUEST, PROFILE, AAD, \ + XXXX, 0, CALLBACKFN) + + +/* Early bailout for kernel_t - 2 init args before callback */ +#define sk_has_perm2(SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, YYYYX, CALLBACKFN) \ +({ \ + struct aa_label *label; \ + struct aa_sk_ctx *ctx = aa_sock(SOCKSK); \ + int __ERROR = 0; \ + if (rcu_access_pointer(ctx->label) != kernel_t) { \ + \ + label = begin_current_label_crit_section(); \ + __ERROR = label_sk_has_perm2(current_cred(), label, SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, YYYYX, CALLBACKFN); \ + end_current_label_crit_section(label); \ + } \ + __ERROR; \ +}) + +/* Early bailout for kernel_t - no init args before callback */ +#define sk_has_perm(SOCKSK, OP, REQUEST, PROFILE, AAD, CALLBACKFN) \ + sk_has_perm2(SOCKSK, OP, REQUEST, PROFILE, AAD, 0, 0, CALLBACKFN) + + +/* Early bailout for kernel_t - 1 init arg before callback */ +#define sk_has_perm1(SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, CALLBACKFN) \ + sk_has_perm2(SOCKSK, OP, REQUEST, PROFILE, AAD, XXXXY, 0, CALLBACKFN) + + + +/* no kernel_t early bailout */ +/* NOTE: already lifted label_mediates into lsm.c */ +int aa_inet_create_perm(struct aa_label *label, int family, int type, + int protocol) +{ + struct aa_profile *profile; + int error = 0; + DEFINE_AUDIT_NET(ad, OP_CREATE, current_cred(), NULL, family, type, + protocol); + + ad.subj_cred = current_cred(); + set_ad_create(&ad, family, type, protocol); + error = fn_for_each(label, profile, + profile_create_perm(profile, family, type, + protocol, &ad)); + + + return error; +} + +int aa_inet_bind_perm(struct socket *sock, struct sockaddr *addr, + int addrlen) +{ + struct match_addr maddr; + + return sk_has_perm1(sock->sk, OP_BIND, AA_MAY_BIND, profile, ad, + bind_map_addr(sock->sk, addr, addrlen, &maddr, + &ad), + profile_bind_perm(profile, sock->sk, &maddr, &ad)); +} + + +int aa_inet_connect_perm(struct socket *sock, struct sockaddr *addr, + int addrlen) +{ + struct stored_match_addr laddr; + struct match_addr raddr; + + /* disconnect socket */ + if (addr->sa_family == AF_UNSPEC) + return 0; + if (addrlen < offsetofend(struct sockaddr, sa_family)) + return -EINVAL; + + /* do we need early bailout for !family ... */ + return sk_has_perm2(sock->sk, OP_CONNECT, AA_MAY_CONNECT, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &laddr, &ad), + map_addr(addr, addrlen, 0, ADDR_REMOTE, &raddr, + &ad), + profile_remote_perm(profile, sock->sk, + AA_MAY_CONNECT, &raddr, + &laddr.maddr, &ad)); +} + +int aa_inet_listen_perm(struct socket *sock, int backlog) +{ + struct stored_match_addr maddr; + + /* do we need early bailout for !family ... */ + return sk_has_perm1(sock->sk, OP_LISTEN, AA_MAY_LISTEN, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_listen_perm(profile, sock->sk, &maddr.maddr, + backlog, &ad)); +} + +/* ability of sock to connect, not peer address binding */ +int aa_inet_accept_perm(struct socket *sock, struct socket *newsock) +{ + struct stored_match_addr maddr; + int error; + + error = sk_has_perm1(sock->sk, OP_ACCEPT, AA_MAY_ACCEPT, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_accept_perm(profile, sock->sk, + &maddr.maddr, + newsock->sk, &ad)); + + /* selinux updates inode - need to investigate this more */ + return error; +} + +/* sendmsg, recvmsg. */ +int aa_inet_msg_perm(const char *op, u32 request, struct socket *sock, + struct msghdr *msg, int size) +{ + struct stored_match_addr laddr; + struct match_addr raddr; + + /* do we need early bailout for !family ... */ + return sk_has_perm2(sock->sk, op, request, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &laddr, &ad), + map_addr(msg->msg_name, msg->msg_namelen, 0, + ADDR_REMOTE, &raddr, &ad), + profile_remote_perm(profile, sock->sk, request, + &raddr, &laddr.maddr, &ad)); +} + +/* getopt, setopt */ +int aa_inet_opt_perm(const char *op, u32 request, struct socket *sock, + int level, int optname) +{ + struct stored_match_addr maddr; + + return sk_has_perm1(sock->sk, op, request, profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_opt_perm(profile, request, sock->sk, + &maddr.maddr, level, optname, &ad)); +} + +static int inet_label_sock_perm(const struct cred *cred, struct aa_label *label, + const char *op, u32 request, + struct socket *sock) +{ + struct stored_match_addr maddr; + + return label_sk_has_perm1(cred, label, sock->sk, op, request, profile, + ad, + map_sock_addr(sock, ADDR_LOCAL, &maddr, &ad), + profile_sk_perm(profile, request, sock->sk, + &maddr.maddr, &ad)); +} + +/* revaliation, get/set attr/getsockname/peername */ +int aa_inet_sock_perm(const char *op, u32 request, struct socket *sock) +{ + struct aa_sk_ctx *ctx = aa_sock(sock->sk); + struct aa_label *label; + int error; + + if (rcu_access_pointer(ctx->label) == kernel_t) + return 0; + + label = begin_current_label_crit_section(); + error = inet_label_sock_perm(current_cred(), label, op, request, sock); + end_current_label_crit_section(label); + + return error; +} + +int aa_inet_file_perm(const struct cred *subj_cred, struct aa_label *label, + const char *op, u32 request, struct socket *sock) +{ + u32 sk_req = request & ~NET_PEER_MASK; + struct stored_match_addr laddr; + const struct sock *sk = sock->sk; + int error = 0; + + AA_BUG(!label); + AA_BUG(!sock); + AA_BUG(!sock->sk); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + /* access to the local sock */ + error = label_sk_has_perm1(subj_cred, label, sock->sk, op, request, + profile, ad, + map_sock_addr(sock, ADDR_LOCAL, &laddr, &ad), + profile_sk_perm(profile, sk_req, sock->sk, &laddr.maddr, + &ad)); + + if (!error) { + struct stored_match_addr raddr; + + /* TODO: have ad here: instead of in CB so we do have to redo */ + error = map_sock_addr(sock, ADDR_REMOTE, &raddr, NULL); + if (!error && raddr.maddr.addrp) { + error = label_sk_has_perm1(subj_cred, label, sock->sk, + op, request, profile, ad, + set_ad_addr(&ad, raddr.addr.sa_family, + false, &raddr.maddr), + profile_remote_perm(profile, sock->sk, + request, + &raddr.maddr, + &laddr.maddr, &ad)); + } + } + + return error; +} + +/* ------------------------ skb / interface ---------------------------- */ + +/* no kernel_t bailout */ +#define label_skb_has_perm2(CRED, LABEL, SOCKSK, SKB, OP, REQUEST, \ + PROFILE, AAD, XXXX, YYYY, CALLBACKFN) \ +({ \ + int __EERROR = 0; \ + if (label_mediates(LABEL, AA_CLASS_NETV9_SKB)) { \ + struct aa_profile *PROFILE; \ + DEFINE_AUDIT_SKB(AAD, OP, CRED, SOCKSK, SKB); \ + (AAD).subj_cred = (CRED); \ + (AAD).request = (REQUEST); \ + __EERROR = (XXXX); \ + if (__EERROR == 0) { \ + __EERROR = (YYYY); \ + if (__EERROR == 0) { \ + __EERROR = fn_for_each(label, PROFILE, \ + (CALLBACKFN)); \ + } \ + } \ + } \ + __EERROR; \ +}) + +/* no kernel_t bailout */ +#define label_skb_has_perm(CRED, LABEL, SOCKSK, SKB, OP, REQUEST, \ + PROFILE, AAD, CALLBACKFN) \ + label_skb_has_perm2(CRED, LABEL, SOCKSK, SKB, OP, REQUEST, \ + PROFILE, AAD, 0, 0, CALLBACKFN) + +/* no kernel_t bailout */ +#define label_skb_has_perm1(CRED, LABEL, SOCKSK, SKB, OP, REQUEST, \ + PROFILE, AAD, XXXX, CALLBACKFN) \ + label_skb_has_perm2(CRED, LABEL, SOCKSK, SKB, OP, REQUEST, \ + PROFILE, AAD, XXXX, 0, CALLBACKFN) + + +/* Early bailout for kernel_t - 2 init args before callback */ +#define skb_has_perm2(SOCKSK, SKB, OP, REQUEST, PROFILE, AAD, XXXXY, \ + YYYYX, CALLBACKFN) \ +({ \ + struct aa_label *label; \ + struct aa_sk_ctx *ctx = aa_sock(SOCKSK); \ + int __ERROR = 0; \ + if (rcu_access_pointer(ctx->label) != kernel_t) { \ + label = begin_current_label_crit_section(); \ + __ERROR = label_skb_has_perm2(current_cred(), label, \ + SOCKSK, SKB, OP, REQUEST, PROFILE, AAD, \ + XXXXY, YYYYX, CALLBACKFN); \ + end_current_label_crit_section(label); \ + } \ + __ERROR; \ +}) + +/* Early bailout for kernel_t - no init args before callback */ +#define skb_has_perm(SOCKSK, SKB, OP, REQUEST, PROFILE, AAD, \ + CALLBACKFN) \ + sk_has_perm2(SOCKSK, SKB, OP, REQUEST, PROFILE, AAD, 0, 0, CALLBACKFN) + + +/* Early bailout for kernel_t - 1 init arg before callback */ +#define skb_has_perm1(SOCKSK, SKB, OP, REQUEST, PROFILE, AAD, XXXXY, \ + CALLBACKFN) \ + sk_has_perm2(SOCKSK, SKB, OP, REQUEST, PROFILE, AAD, XXXXY, 0, \ + CALLBACKFN) + + + +/* based on selinux_parse_skb_ipv4 */ +static int map_skb_ipv4_addrs(const struct sk_buff *skb, + enum addr_type saddrtype, + struct stored_match_addr *saddr, + enum addr_type daddrtype, + struct stored_match_addr *daddr, + struct apparmor_audit_data *ad) +{ + int offset, ihlen; + struct iphdr _iph, *ih; + u16 typ = 0; + + offset = skb_network_offset(skb); + ih = skb_header_pointer(skb, offset, sizeof(_iph), &_iph); + if (ih == NULL) + return -EINVAL; + + ihlen = ih->ihl * 4; + if (ihlen < sizeof(_iph)) + return -EINVAL; + + saddr->addr.sa_family = AF_INET; + daddr->addr.sa_family = AF_INET; + saddr->addr4.sin_addr.s_addr = ih->saddr; + daddr->addr4.sin_addr.s_addr = ih->daddr; + saddr->addrlen = 4; + daddr->addrlen = 4; + + switch (ih->protocol) { + case IPPROTO_TCP: { + struct tcphdr _tcph, *th; + + if (ntohs(ih->frag_off) & IP_OFFSET) + break; + + offset += ihlen; + th = skb_header_pointer(skb, offset, sizeof(_tcph), &_tcph); + if (th == NULL) + break; + + saddr->addr4.sin_port = th->source; + daddr->addr4.sin_port = th->dest; + typ = SOCK_STREAM; + break; + } + + case IPPROTO_UDP: { + struct udphdr _udph, *uh; + + if (ntohs(ih->frag_off) & IP_OFFSET) + break; + + offset += ihlen; + uh = skb_header_pointer(skb, offset, sizeof(_udph), &_udph); + if (uh == NULL) + break; + + ad->common.u.net->sport = uh->source; + ad->common.u.net->dport = uh->dest; + typ = SOCK_DGRAM; + break; + } +#if IS_ENABLED(CONFIG_IP_SCTP) + case IPPROTO_SCTP: { + struct sctphdr _sctph, *sh; + struct socket *sock = skb->sk ? skb->sk->sk_socket : NULL; + + sh = skb_header_pointer(skb, offset, sizeof(_sctph), &_sctph); + if (sh == NULL) + break; + + ad->common.u.net->sport = sh->source; + ad->common.u.net->dport = sh->dest; + if (sock) + typ = sock->type; + break; + } +#endif + default: + break; + } + + if (ad) { + ad->net.protocol = ih->protocol; + ad->net.type = typ; + } + // LOCAL may change based whether sending or receiving + map_addr(&saddr->addr, saddr->addrlen, 0, saddrtype, &saddr->maddr, + ad); + map_addr(&daddr->addr, daddr->addrlen, 0, daddrtype, &daddr->maddr, + ad); + + return 0; +} + +#if IS_ENABLED(CONFIG_IPV6) + +/* based on selinux parse_skb_ipv6 */ +static int map_skb_ipv6_addrs(const struct sk_buff *skb, + enum addr_type saddrtype, + struct stored_match_addr *saddr, + enum addr_type daddrtype, + struct stored_match_addr *daddr, + struct apparmor_audit_data *ad) +{ + u8 nexthdr; + int offset; + struct ipv6hdr _ipv6h, *ih; + __be16 frag_off; + u16 typ = 0; + + offset = skb_network_offset(skb); + ih = skb_header_pointer(skb, offset, sizeof(_ipv6h), &_ipv6h); + if (ih == NULL) + return -EINVAL; + + saddr->addr.sa_family = AF_INET6; + daddr->addr.sa_family = AF_INET6; + saddr->addr6.sin6_addr = ih->saddr; + daddr->addr6.sin6_addr = ih->daddr; + saddr->addrlen = 16; + daddr->addrlen = 16; + +// ad->common.u.net->v6info.saddr = ih->saddr; +// ad->common.u.net->v6info.daddr = ih->daddr; + + nexthdr = ih->nexthdr; + offset += sizeof(_ipv6h); + offset = ipv6_skip_exthdr(skb, offset, &nexthdr, &frag_off); + if (offset < 0) + return -EINVAL; + + switch (nexthdr) { + case IPPROTO_TCP: { + struct tcphdr _tcph, *th; + + th = skb_header_pointer(skb, offset, sizeof(_tcph), &_tcph); + if (th == NULL) + break; + + saddr->addr6.sin6_port = th->source; + daddr->addr6.sin6_port = th->dest; + typ = SOCK_STREAM; + break; + } + + case IPPROTO_UDP: { + struct udphdr _udph, *uh; + + uh = skb_header_pointer(skb, offset, sizeof(_udph), &_udph); + if (uh == NULL) + break; + + ad->common.u.net->sport = uh->source; + ad->common.u.net->dport = uh->dest; + typ = SOCK_DGRAM; + break; + } + +#if IS_ENABLED(CONFIG_IP_SCTP) + case IPPROTO_SCTP: { + struct sctphdr _sctph, *sh; + struct socket *sock = skb->sk ? skb->sk->sk_socket : NULL; + + sh = skb_header_pointer(skb, offset, sizeof(_sctph), &_sctph); + if (sh == NULL) + break; + + ad->common.u.net->sport = sh->source; + ad->common.u.net->dport = sh->dest; + if (sock) + typ = sock->type; + break; + } +#endif + /* includes fragments */ + default: + break; + } + + if (ad) { + ad->net.protocol = nexthdr; + ad->net.type = typ; + } + + // LOCAL may change based whether sending or receiving + map_addr(&saddr->addr, saddr->addrlen, 0, saddrtype, &saddr->maddr, + ad); + map_addr(&daddr->addr, daddr->addrlen, 0, daddrtype, &daddr->maddr, + ad); + return 0; +} + +#endif /* IPV6 */ + +static int map_skb_addrs(const struct sk_buff *skb, + u16 family, + enum addr_type saddrtype, + struct stored_match_addr *saddr, + enum addr_type daddrtype, + struct stored_match_addr *daddr, + struct apparmor_audit_data *ad) +{ + int ret; + + /* handle mapped IPv4 packets arriving via IPv6 sockets */ + if (family == PF_INET6 && skb->protocol == htons(ETH_P_IP)) + family = PF_INET; + + ad->common.u.net->family = family; + switch (family) { + case PF_INET: + ret = map_skb_ipv4_addrs(skb, saddrtype, saddr, + daddrtype, daddr, ad); + if (ret) + goto parse_error; + break; + +#if IS_ENABLED(CONFIG_IPV6) + case PF_INET6: + ret = map_skb_ipv6_addrs(skb, saddrtype, saddr, + daddrtype, daddr, ad); + if (ret) + goto parse_error; + break; +#endif /* IPV6 */ + default: + break; + } + + return 0; + +parse_error: + pr_warn("AppArmor: failure in %s, unable to map skb addr", __func__); + return ret; +} + + +/* todo: optimize, do this once and buffer, have destruct to put at end */ +static aa_state_t match_iface(struct aa_profile *profile, + struct aa_dfa *dfa, aa_state_t state, + const struct sock *sk, int ifidx, + const char **info) +{ + if (ifidx > 0) { + struct net_device *dev; + struct net *ns; + + /* TODO: check netns against profile ctx */ + rcu_read_lock(); + ns = sock_net(sk); + dev = dev_get_by_index(ns, ifidx); + if (dev) { + /* TODO: share this so it is only done once */ + state = aa_dfa_match(dfa, state, dev->name); + dev_put(dev); + } else { + /* if lookup fails don't just skip interface check + * with null transition, force fail */ + state = 0; + } + rcu_read_unlock(); + } else if (ifidx == 0) { + /* this should not happen, caller specifies -1 to by-pass + * interface check. + */ + *info = "interface for packet not defined"; + state = 0; + } + /* null transition after iface match */ + state = aa_dfa_null_transition(dfa, state); + if (!state) + *info = "failed interface match"; + + return state; +} + +static aa_state_t match_addr_iface(struct aa_profile *profile, + struct aa_policydb *policy, + aa_state_t state, u32 request, + struct match_addr *maddr, + const struct sock *sk, int ifidx, + struct aa_perms **p, const char **info) +{ + aa_state_t tmp = state; + state = match_addr_info(policy->dfa, state, maddr, info); + *p = early_match(policy, state, request); + if (*p) + return state; + state = match_iface(profile, policy->dfa, state, sk, ifidx, info); + *p = early_match(policy, state, request); + + return state; +} + +static aa_state_t match_addr_iface_label(struct aa_profile *profile, + struct aa_ruleset *rules, + aa_state_t state, + u32 request, struct match_addr *maddr, + const struct sock *sk, int ifidx, + struct aa_label *seclabel, + struct aa_perms **p, + struct aa_perms *perms, + const char **info) +{ + state = match_addr_iface(profile, rules->policy, state, request, maddr, + sk, ifidx, p, info); + if (*p) + return state; + + if (seclabel) + state = aa_label_match(profile, rules, seclabel, state, false, + request, perms); + /* null transition after label match */ + state = aa_dfa_null_transition(rules->policy->dfa, state); + + if (!state) { + *info = maddr->addrtype == ADDR_REMOTE ? + "failed remote label match" : + "failed local label match"; + } + + return state; +} + +static aa_state_t skb_match_to_sk(struct aa_profile *profile, + struct aa_ruleset *rules, + aa_state_t state, u32 request, + const struct sock *sk, + const struct sk_buff *skb, + struct match_addr *maddr, + int ifidx, struct aa_label *seclabel, + struct aa_perms **p, struct aa_perms *perms, + const char **info) +{ + u16 family = sk->sk_family; + + *p = NULL; + + /* handle mapped IPv4 packets arriving via IPv6 sockets */ + if (family == PF_INET6 && skb->protocol == htons(ETH_P_IP)) + family = PF_INET; + + state = aa_match_to_prot(rules->policy, state, request, sk->sk_family, + sk->sk_type, sk->sk_protocol, p, info); + if (*p) + return state; + return match_addr_iface_label(profile, rules, state, request, maddr, + sk, ifidx, seclabel, p, perms, info); +} + +static inline aa_state_t skb_match_to_cmd(struct aa_profile *profile, + struct aa_ruleset *rules, + aa_state_t state, u32 request, + const struct sock *sk, + const struct sk_buff *skb, + enum cmd_type cmd, + struct match_addr *maddr, + int ifidx, + struct aa_label *seclabel, + struct aa_perms **p, + struct aa_perms *perms, + const char **info) +{ + state = skb_match_to_sk(profile, rules, state, request, sk, skb, maddr, + ifidx, seclabel, p, perms, info); + if (!*p && state) { + char c = (char) cmd; + + state = aa_dfa_match_len(rules->policy->dfa, state, &c, 1); + if (!state) + *info = "failed cmd selection match"; + } + + return state; +} + +static int profile_relabel_packet(struct aa_profile *profile, + struct aa_label *seclabel, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms perms = { }; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!seclabel); + + state = RULE_MEDIATES(rules, AA_CLASS_NETV9_SKB); + if (!state) + return 0; + state = aa_dfa_outofband_transition(rules->policy->dfa, state); + aa_label_match(profile, rules, seclabel, state, false, ad->request, + &perms); + aa_apply_modes_to_perms(profile, &perms); + return aa_check_perms(profile, &perms, ad->request, ad, + audit_net_cb); +} + +/* TODO: make so we can move this into lsm.c */ +int aa_secmark_relabel_packet(u32 sid) +{ + struct aa_label *label, *seclabel; + int error = 0; + + seclabel = aa_secid_to_label(sid); + if (!seclabel) + return -EINVAL; + label = begin_current_label_crit_section(); + + if (label_mediates(label, AA_CLASS_NETV9_SKB)) { + struct aa_profile *profile; + DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_NONE, AA_CLASS_NET, + OP_RELABEL_PACKET); + ad.subj_cred = current_cred(); + ad.peer = seclabel; + ad.request = AA_MAY_SETCRED; + + error = fn_for_each(label, profile, + profile_relabel_packet(profile, seclabel, + &ad)); + } + + end_current_label_crit_section(label); + + return error; +} + +/* rcu_read_lock held */ +static int __profile_skb_perm(struct aa_profile *profile, + const struct sock *sk, const struct sk_buff *skb, + u32 request, struct match_addr *raddr, + int ifidx, struct aa_label *seclabel, + struct match_addr *laddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms perms = { }; + struct aa_perms *p = NULL; + aa_state_t state; + + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!raddr); + AA_BUG(!laddr); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SKB(rules); + if (!state) { + return apparmor_secmark_check(&profile->label, + ad->op, request, + skb->secmark, sk); + } + + /* includes match on outbound iface */ + state = skb_match_to_cmd(profile, rules, state, request, sk, skb, + CMD_ADDR, raddr, ifidx, seclabel, &p, &perms, + &ad->info); + if (state && !p) { + struct aa_sk_ctx *ctx = aa_sock(sk); + + /* check if perm is restricted to a pairing */ + /* Note: ifidx on the second pairing is always -1, + * this is just present if we ever choose to support + * forward which has in and out iterfaces + */ + state = match_addr_iface_label(profile, rules, state, request, + laddr, sk, -1, + rcu_dereference(ctx->label), + &p, &perms, &ad->info); + } + return do_perms(profile, state, request, p, ad); +} + +/** + * __aa_sock_rcv_skb - check permission to receive skb + * @label: label doing the mediation (label off of sk) + * @sk: socket that is receiving the packet + * @skb: skb that is being mediated + * + * Returns: 0 on success or -errno on failure/denial + * + * assumes called in rcu_read_lock + * it is possible that the skb is unlabeled, by apparmor (which only will + * label outbound packets if explicitly requested to do so) or netfilter. + * At this point we have already determined the packet is being mediated, + * so treat the unlabeled packet case as unlabeled_t + */ +int __aa_sock_rcv_skb(struct aa_label *label, const struct sock *sk, + const struct sk_buff *skb) +{ + struct stored_match_addr sladdr; + struct stored_match_addr sraddr; + struct aa_label *seclabel; + int ifidx = skb->skb_iif; + u32 request = AA_MAY_RECEIVE; + + AA_BUG(!label); + AA_BUG(!sk); + AA_BUG(!skb); + + seclabel = aa_secid_to_label(skb->secmark); /* may be NULL */ + if (!seclabel) + seclabel = unlabeled_t; + /* sock sk label is proxy for receiving task label, + * receiving so + * source addr is remote + * dest addr is local + */ + return label_skb_has_perm1(NULL, label, sk, skb, + OP_RCV_SKB, request, profile, ad, + map_skb_addrs(skb, sk->sk_family, + ADDR_REMOTE, &sraddr, + ADDR_LOCAL, &sladdr, &ad), + __profile_skb_perm(profile, sk, skb, request, + &sraddr.maddr, ifidx, seclabel, + &sladdr.maddr, &ad)); +} + + +int __aa_inet_conn_request(struct aa_label *label, const struct sock *sk, + const struct sk_buff *skb, + const struct request_sock *req) +{ + struct stored_match_addr sladdr; + struct stored_match_addr sraddr; + struct aa_label *seclabel; + int ifidx = skb->skb_iif; + u16 family = req->rsk_ops->family; + u32 request = AA_MAY_CONNECT; + + AA_BUG(!label); + AA_BUG(!sk); + AA_BUG(!skb); + + seclabel = aa_secid_to_label(skb->secmark); /* may be NULL */ + if (!seclabel) + seclabel = unlabeled_t; + + /* sock sk label is proxy for receiving task label, + * receiving so + * source addr is remote + * dest addr is local + */ + return label_skb_has_perm1(NULL, label, sk, skb, + OP_CONN_REQ, request, profile, ad, + map_skb_addrs(skb, family, + ADDR_REMOTE, &sraddr, + ADDR_LOCAL, &sladdr, &ad), + __profile_skb_perm(profile, sk, skb, request, + &sraddr.maddr, ifidx, seclabel, + &sladdr.maddr, &ad)); +} + +int __aa_ip_postroute(struct aa_label *label, const struct sock *sk, + const struct sk_buff *skb, + const struct nf_hook_state *state) +{ + struct stored_match_addr sladdr; + struct stored_match_addr sraddr; + struct aa_label *seclabel; + int ifidx = state->out->ifindex; + + u32 request = AA_MAY_SEND; + + AA_BUG(!label); + AA_BUG(!sk); + AA_BUG(!skb); + + seclabel = aa_secid_to_label(skb->secmark); /* may be NULL */ + if (!seclabel) + seclabel = unlabeled_t; + + /* sock sk label is proxy for receiving task label, + * receiving so + * source addr is remote + * dest addr is local + */ + return label_skb_has_perm1(NULL, label, sk, skb, + OP_POSTROUTE, request, profile, ad, + map_skb_addrs(skb, state->pf, + ADDR_LOCAL, &sladdr, + ADDR_REMOTE, &sraddr, &ad), + __profile_skb_perm(profile, sk, skb, request, + &sraddr.maddr, ifidx, seclabel, + &sladdr.maddr, &ad)); +} + +/* returns refcounted label, ERR_PTR, or NULL if profile should be skipped */ +static struct aa_label *profile_ip_localout(const struct cred *subj_cred, + struct aa_profile *profile, + const struct sock *sk, + const struct sk_buff *skb, + struct match_addr *raddr, + struct match_addr *laddr, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms perms = { }; + struct aa_perms *p = NULL; + aa_state_t state; + u32 request = AA_SET_LABEL; + + AA_BUG(!subj_cred); + AA_BUG(!profile); + AA_BUG(!sk); + AA_BUG(!skb); + AA_BUG(!raddr); + AA_BUG(!laddr); + AA_BUG(!ad); + AA_BUG(skb->skb_iif); + AA_BUG(sk->sk_family != PF_INET && sk->sk_family != PF_INET6, + "family=%d", sk->sk_family); + + state = RULE_MEDIATES_SKB(rules); + if (!state) + /* does not add to label or block */ + return NULL; + + state = skb_match_to_cmd(profile, rules, state, request, sk, skb, + CMD_ADDR, raddr, -1, NULL, &p, &perms, &ad->info); + if (state && !p) { + struct aa_sk_ctx *ctx = aa_sock(sk); + + /* check if perm is restricted to a pairing */ + state = match_addr_iface_label(profile, rules, state, request, + laddr, sk, -1, + rcu_dereference(ctx->label), + &p, &perms, &ad->info); + } + if (!p) + p = aa_lookup_perms(rules->policy, state); + if ((p->allow & request) == request) { + if (p->label != 0) { + AA_DEBUG_PROFILE(profile, DEBUG_SKB, + "label specified but not currently supported"); + /* not supported yet */ + return ERR_PTR(-EACCES); + } + return aa_get_label(&profile->label); + } + return NULL; +} + +/* called from within spinlocks */ +struct aa_label *__aa_ip_localout(struct aa_label *label, const struct sock *sk, + const struct sk_buff *skb) +{ + struct stored_match_addr sladdr; + struct stored_match_addr sraddr; + struct aa_profile *profile; + DEFINE_AUDIT_SKB(ad, OP_LOCALOUT, current_cred(), sk, skb); + + AA_BUG(!label); + AA_BUG(!sk); + AA_BUG(!skb); + + map_skb_addrs(skb, sk->sk_family, ADDR_LOCAL, &sladdr, + ADDR_REMOTE, &sraddr, &ad); + ad.subj_cred = current_cred(); + + /* TODO: caching mechanism - to reduce calls to build */ + + return fn_label_build_in_netns_scope(label, profile, GFP_ATOMIC, + profile_ip_localout(current_cred(), profile, + sk, skb, &sraddr.maddr, + &sladdr.maddr, &ad)); +} --- linux-nvidia-7.0.0.orig/security/apparmor/af_unix.c +++ linux-nvidia-7.0.0/security/apparmor/af_unix.c @@ -20,6 +20,7 @@ #include "include/apparmor.h" #include "include/file.h" #include "include/label.h" +#include "include/net.h" #include "include/path.h" #include "include/policy.h" #include "include/cred.h" @@ -53,7 +54,7 @@ }; return aa_path_perm(op, subj_cred, label, path, - PATH_SOCK_COND, mask, &cond); + PATH_SOCK_COND, mask, &cond, NULL); } /* else implicitly delegated */ return 0; @@ -208,7 +209,7 @@ AA_BUG(!profile); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { state = aa_match_to_prot(rules->policy, state, AA_MAY_CREATE, PF_UNIX, type, protocol, NULL, @@ -218,8 +219,8 @@ NULL, ad); } - return aa_profile_af_perm(profile, ad, AA_MAY_CREATE, family, type, - protocol); + return aa_profile_af_compat_perm(profile, ad, AA_MAY_CREATE, family, + type); } static int profile_sk_perm(struct aa_profile *profile, @@ -234,7 +235,7 @@ AA_BUG(!sk); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { if (is_unix_fs(sk)) return unix_fs_perm(ad->op, request, ad->subj_cred, @@ -263,7 +264,7 @@ AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { if (is_unix_addr_fs(ad->net.addr, ad->net.addrlen)) /* under v7-9 fs hook handles bind */ @@ -294,7 +295,7 @@ AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { __be16 b = cpu_to_be16(backlog); @@ -331,7 +332,7 @@ AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { if (is_unix_fs(sk)) return unix_fs_perm(ad->op, AA_MAY_ACCEPT, @@ -361,7 +362,7 @@ AA_BUG(!ad); AA_BUG(profile_unconfined(profile)); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { __be16 b = cpu_to_be16(optname); if (is_unix_fs(sk)) @@ -402,7 +403,7 @@ AA_BUG(!peer_label); AA_BUG(!ad); - state = RULE_MEDIATES_v9NET(rules); + state = RULE_MEDIATES_UNIX(rules); if (state) { struct aa_profile *peerp; --- linux-nvidia-7.0.0.orig/security/apparmor/apparmorfs.c +++ linux-nvidia-7.0.0/security/apparmor/apparmorfs.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "include/apparmor.h" #include "include/apparmorfs.h" @@ -32,10 +33,12 @@ #include "include/crypto.h" #include "include/ipc.h" #include "include/label.h" +#include "include/net.h" #include "include/lib.h" #include "include/policy.h" #include "include/policy_ns.h" #include "include/resource.h" +#include "include/path.h" #include "include/policy_unpack.h" #include "include/task.h" @@ -71,10 +74,10 @@ struct rawdata_f_data { struct aa_loaddata *loaddata; + DECLARE_FLEX_ARRAY(char, data); }; #ifdef CONFIG_SECURITY_APPARMOR_EXPORT_BINARY -#define RAWDATA_F_DATA_BUF(p) (char *)(p + 1) static void rawdata_f_data_free(struct rawdata_f_data *private) { @@ -174,14 +177,6 @@ return NULL; } -static struct aa_loaddata *get_loaddata_common_ref(struct aa_common_ref *ref) -{ - if (ref) - return aa_get_i_loaddata(container_of(ref, struct aa_loaddata, - count)); - return NULL; -} - static void aa_put_common_ref(struct aa_common_ref *ref) { if (!ref) @@ -489,6 +484,69 @@ return data; } +static int decompress_zstd(char *src, size_t slen, char *dst, size_t dlen); +/** + * aa_get_data_from_compressed - common routine for getting compressed policy + * from user and get both compressed and uncompressed version. + * @userbuf: user buffer to copy data from (NOT NULL) + * @buffer_size: size of user buffer + * @pos: position write is at in the file (NOT NULL) + * @compressed_data Ptr on compressed data. *compressed_data is allocated there + * + * Returns: kernel buffer containing copy of user buffer data or an + * ERR_PTR on failure. + */ + +static struct aa_loaddata *aa_get_data_from_compressed(const char __user *userbuf, + size_t buffer_size, + loff_t *pos, + char **compressed_data) +{ + struct aa_loaddata *data; + zstd_frame_header header; + int error; + + if (!userbuf || !pos) + return ERR_PTR(-EINVAL); + if (*pos) + return ERR_PTR(-ESPIPE); + + *compressed_data = kvmalloc(buffer_size, GFP_KERNEL); + if (!*compressed_data) + return ERR_PTR(-ENOMEM); + error = copy_from_user(*compressed_data, userbuf, buffer_size); + if (error) + goto fail; + + error = zstd_get_frame_header(&header, *compressed_data, buffer_size); + if (error || header.frameContentSize == ZSTD_CONTENTSIZE_UNKNOWN || + header.frameContentSize == ZSTD_CONTENTSIZE_ERROR) { + error = -EINVAL; + goto fail; + } + + data = aa_loaddata_alloc(header.frameContentSize); + if (IS_ERR(data)) { + error = PTR_ERR(data); + goto fail; + } + + // We then decompress the data + error = decompress_zstd(*compressed_data, buffer_size, data->data, + header.frameContentSize); + if (error) + goto fail_decompress; + + data->size = header.frameContentSize; + return data; + +fail_decompress: + aa_put_i_loaddata(data); +fail: + kvfree(*compressed_data); + return ERR_PTR(error); + +} static ssize_t policy_update(u32 mask, const char __user *buf, size_t size, loff_t *pos, struct aa_ns *ns, @@ -497,6 +555,9 @@ struct aa_loaddata *data; struct aa_label *label; ssize_t error; + char *compressed_data = NULL; + __le32 magic_le; + bool is_compressed; label = begin_current_label_crit_section(); @@ -507,10 +568,33 @@ if (error) goto end_section; - data = aa_simple_write_to_buffer(buf, size, size, pos); - error = PTR_ERR(data); + /* If the policy is userspace compressed we start by decompressing it + * to make the required checks (computing hash, verifying profile, ...) + * + * Getting a userspace-compressed version then decompressing it in the + * kernel actually makes sense since zstd decompression is ~3.5x faster + * than compression. This also allow to increase the compression level. + */ + + if (size >= sizeof(__le32) && + !copy_from_user(&magic_le, buf, sizeof(magic_le)) && + le32_to_cpu(magic_le) == ZSTD_MAGICNUMBER) + is_compressed = true; + else + is_compressed = false; + + if (is_compressed) { + + data = aa_get_data_from_compressed(buf, size, pos, &compressed_data); + error = PTR_ERR(data); + } else { + data = aa_simple_write_to_buffer(buf, size, size, pos); + error = PTR_ERR(data); + } + if (!IS_ERR(data)) { - error = aa_replace_profiles(ns, label, mask, data); + error = aa_replace_profiles(ns, label, mask, data, + compressed_data, size); /* put pcount, which will put count and free if no * profiles referencing it. */ @@ -557,6 +641,7 @@ .llseek = default_llseek, }; + /* .remove file hook fn to remove loaded policy */ static ssize_t profile_remove(struct file *f, const char __user *buf, size_t size, loff_t *pos) @@ -693,6 +778,368 @@ .release = ns_revision_release, }; + +/* file hook fn for notificaions of policy actions */ +static int listener_release(struct inode *inode, struct file *file) +{ + struct aa_listener_proxy *proxy = file->private_data; + + if (!aa_current_policy_admin_capable(NULL)) + return -EPERM; + AA_DEBUG(DEBUG_UPCALL, "file %p, listener %p, id %llu", file, proxy->listener, proxy->listener->listener_id); + if (proxy) { + AA_DEBUG(DEBUG_UPCALL, "file putting proxy"); + aa_delayed_free_listener_proxy(proxy); + } + return 0; +} + +static int listener_open(struct inode *inode, struct file *file) +{ + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + struct aa_ns *ns = NULL; + + if (!aa_current_policy_admin_capable(NULL)) + return -EPERM; + listener = aa_new_listener(NULL, GFP_KERNEL); + if (!listener) + return -ENOMEM; + proxy = aa_new_listener_proxy(listener, ns); + aa_put_listener(listener); + if (!proxy) + return -ENOMEM; + AA_DEBUG(DEBUG_UPCALL, "Registered listener using protocol version %d", + listener->version); + file->private_data = proxy; + return 0; +} + +static bool notif_supported_version(struct apparmor_notif_common *unotif) +{ + return (unotif->version == 3 || unotif->version == 5); +} + +/* todo: separate register and set filter */ +static long notify_set_filter(struct aa_listener *listener, + unsigned long arg) +{ + union apparmor_notif_filters *unotif; + struct aa_ns *ns = NULL; + long ret; + u16 size; + void __user *buf = (void __user *)arg; + + if (copy_from_user(&size, buf, sizeof(size))) + return -EFAULT; + if (size < sizeof(unotif)) + return -EINVAL; + /* size is capped at U16_MAX by data type */ + unotif = kzalloc(size, GFP_KERNEL); + if (!unotif) + return -ENOMEM; + + if (copy_from_user(unotif, buf, size)) { + ret = -EFAULT; + goto out; + } + ret = size; + + if (!notif_supported_version((struct apparmor_notif_common *)unotif)) { + AA_DEBUG(DEBUG_UPCALL, "Failed to Register listener using unsupported protocol version %d", unotif->base.version); + ret = -EPROTONOSUPPORT; + goto out; + } + + listener->version = unotif->base.version; + /* todo validate to known modes */ + listener->mask = unotif->modeset; + AA_DEBUG(DEBUG_UPCALL, "setting filter mask to 0x%x", listener->mask); + if (unotif->ns) + /* todo */ + ns = NULL; + if (unotif->filter) { + struct aa_dfa *dfa; + void *pos = (void *) unotif + unotif->filter; + + if (unotif->filter >= size || + ALIGN((size_t) pos, 8) != (size_t)pos) { + ret = -EINVAL; + goto out; + } + dfa = aa_dfa_unpack(pos, size - ((void *) unotif - pos), + DFA_FLAG_VERIFY_STATES | + TO_ACCEPT1_FLAG(YYTD_DATA32)); + if (IS_ERR(dfa)) { + ret = PTR_ERR(dfa); + goto out; + } + listener->filter = dfa; + } + +out: + kfree(unotif); + + return ret; +} + + +static long notify_user_recv(struct aa_listener *listener, + unsigned long arg) +{ + struct apparmor_notif_common common; + void __user *buf = (void __user *)arg; + __u16 version; + + if (copy_from_user(&common.len, buf, sizeof(common.len))) + return -EFAULT; + if (listener->version >= 5) { + /* allow individual messages to specify version */ + if (common.len < sizeof(common)) + return -EMSGSIZE; + if (copy_from_user(&common, buf, sizeof(common))) + return -EFAULT; + version = common.version; + } else { + version = listener->version; + } + /* size check handled by individual message handlers */ + return aa_listener_unotif_recv(listener, buf, common.len, + version); +} + +static long notify_user_response(struct aa_listener *listener, + unsigned long arg) +{ + union apparmor_notif_resp uresp = {}; + union apparmor_notif_resp *big_resp = NULL; + long error; + u16 size; + void __user *buf = (void __user *)arg; + + if (copy_from_user(&size, buf, sizeof(size))) + return -EFAULT; + if (size > aa_g_path_max) + return -EMSGSIZE; + if (size > sizeof(uresp)) { + /* TODO: put max size on message */ + big_resp = (union apparmor_notif_resp *) aa_get_buffer(false); + if (big_resp) + return -ENOMEM; + if (copy_from_user(big_resp, buf, size)) { + kfree(big_resp); + return -EFAULT; + } + } else { + size = min_t(size_t, size, sizeof(uresp)); + if (copy_from_user(&uresp, buf, size)) + return -EFAULT; + } + + if (!notif_supported_version((struct apparmor_notif_common *)&uresp)) { + AA_DEBUG(DEBUG_UPCALL, "Failed response listener using unsupported protocol version %d", uresp.base.base.version); + error = -EPROTONOSUPPORT; + goto out; + } + error = aa_listener_unotif_response(listener, &uresp, size); +out: + aa_put_buffer((char *) big_resp); + + return error; +} + +static long notify_is_id_valid(struct aa_listener *listener, + unsigned long arg) +{ + void __user *buf = (void __user *)arg; + u64 id; + long ret = -ENOENT; + + if (copy_from_user(&id, buf, sizeof(id))) + return -EFAULT; + + spin_lock(&listener->lock); + if (__aa_find_notif(listener, id)) + ret = 0; + spin_unlock(&listener->lock); + + return ret; +} + +static long notify_user_register(struct aa_listener *listener, + unsigned long arg, struct file *file) +{ + struct apparmor_notif_register_v5 reg; + struct aa_listener *found = NULL; + void __user *buf = (void __user *)arg; + long res; + + if (copy_from_user(®.base.len, buf, sizeof(reg.base.len))) + return -EFAULT; + if (reg.base.len < sizeof(reg)) + return -EMSGSIZE; + if (copy_from_user(®, buf, sizeof(reg))) + return -EFAULT; + /* to balance potential put and retry, ideally would grab from + * file here, but need to refactor for that + */ + aa_get_listener(listener); +retry: + res = aa_register_listener_id(listener, ®.listener_id, &found); + AA_DEBUG(DEBUG_UPCALL, "registered id %llu found %p res %ld", reg.listener_id, found, res); + if (res >= 0) { + if (found) { + struct aa_listener *l; + + AA_DEBUG(DEBUG_UPCALL, "updating file"); + struct aa_listener_proxy *proxy; + + spin_lock(&file->f_lock); + proxy = file->private_data; + if (proxy->listener != listener) { + /* raced, try again */ + l = aa_get_listener(proxy->listener); + spin_unlock(&file->f_lock); + aa_put_listener(found); + aa_put_listener(listener); + listener = l; + found = NULL; + goto retry; + } + spin_lock(&listener->lock); + l = proxy->listener; + proxy->listener = NULL; + list_del_init(&proxy->llist); + spin_unlock(&listener->lock); + + spin_lock(&found->lock); + proxy->listener = found; /* transfer search ref */ + list_add_tail_entry(proxy, &found->ns_proxies, + llist); + spin_unlock(&found->lock); + spin_unlock(&file->f_lock); + aa_put_listener(l); + AA_DEBUG(DEBUG_UPCALL, "completed file update"); + } + res = sizeof(reg); + if (copy_to_user(buf, ®, sizeof(reg))) + res = -EFAULT; + } + aa_put_listener(listener); + /* size check handled by individual message handlers */ + + return res; +} + +static long notify_user_resend(struct aa_listener *listener, + unsigned long arg) +{ + struct apparmor_notif_resend_v5 resend; + void __user *buf = (void __user *)arg; + long res; + + if (copy_from_user(&resend.base.len, buf, sizeof(resend.base.len))) + return -EFAULT; + if (resend.base.len < sizeof(resend)) + return -EMSGSIZE; + if (copy_from_user(&resend, buf, sizeof(resend))) + return -EFAULT; + + /* size check handled by individual message handlers */ + res = aa_listener_unotif_resend(listener, &resend.ready, + &resend.pending); + if (!res) { + if (copy_to_user(buf, &resend, sizeof(resend))) + return -EFAULT; + res = sizeof(resend); + } + return res; +} + + +static long listener_ioctl_switch(struct file *file, + struct aa_listener *listener, + unsigned int cmd, unsigned long arg) +{ + /* todo permission to issue these commands */ + switch (cmd) { + case APPARMOR_NOTIF_SET_FILTER: + return notify_set_filter(listener, arg); + case APPARMOR_NOTIF_RECV: + return notify_user_recv(listener, arg); + case APPARMOR_NOTIF_SEND: + return notify_user_response(listener, arg); + case APPARMOR_NOTIF_IS_ID_VALID: + return notify_is_id_valid(listener, arg); + case APPARMOR_NOTIF_REGISTER: + return notify_user_register(listener, arg, file); + case APPARMOR_NOTIF_RESEND: + return notify_user_resend(listener, arg); + } + return -EINVAL; +} + +static long listener_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + long error; + + if (!aa_current_policy_admin_capable(NULL)) + return -EPERM; + + spin_lock(&file->f_lock); + proxy = file->private_data; + listener = aa_get_listener(proxy->listener); + spin_unlock(&file->f_lock); + if (!listener) + return -EINVAL; + + error = listener_ioctl_switch(file, listener, cmd, arg); + aa_put_listener(listener); + + return error; +} + +static __poll_t listener_poll(struct file *file, poll_table *pt) +{ + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + __poll_t mask = 0; + + if (!aa_current_policy_admin_capable(NULL)) + return EPOLLERR; + + spin_lock(&file->f_lock); + proxy = file->private_data; + listener = aa_get_listener(proxy->listener); + spin_unlock(&file->f_lock); + + if (listener) { + spin_lock(&listener->lock); + poll_wait(file, &listener->wait, pt); + if (!list_empty(&listener->notifications)) + mask |= EPOLLIN | EPOLLRDNORM; + if (!list_empty(&listener->pending)) + mask |= EPOLLOUT | EPOLLWRNORM; + spin_unlock(&listener->lock); + } + aa_put_listener(listener); + + return mask; +} + +static const struct file_operations aa_sfs_notify_fops = { + .owner = THIS_MODULE, + .open = listener_open, + .poll = listener_poll, +// .read = notification_read, + .llseek = generic_file_llseek, + .release = listener_release, + .unlocked_ioctl = listener_ioctl, +}; + static void profile_query_cb(struct aa_profile *profile, struct aa_perms *perms, const char *match_str, size_t match_len) { @@ -715,14 +1162,6 @@ } else if (rules->policy->dfa) { if (!RULE_MEDIATES(rules, *match_str)) return; /* no change to current perms */ - /* old user space does not correctly detect dbus mediation - * support so we may get dbus policy and requests when - * the abi doesn't support it. This can cause mediation - * regressions, so explicitly test for this situation. - */ - if (*match_str == AA_CLASS_DBUS && - !RULE_MEDIATES_v9NET(rules)) - return; /* no change to current perms */ state = aa_dfa_match_len(rules->policy->dfa, rules->policy->start[0], match_str, match_len); @@ -1091,6 +1530,10 @@ case AA_SFS_TYPE_BOOLEAN: seq_printf(seq, "%s\n", str_yes_no(fs_file->v.boolean)); break; + case AA_SFS_TYPE_BOOLEAN_INTPRINT: + // Allow printing the boolean as 0/1 for backwards compatibility + seq_printf(seq, "%s\n", fs_file->v.boolean ? "1" : "0"); + break; case AA_SFS_TYPE_STRING: seq_printf(seq, "%s\n", fs_file->v.string); break; @@ -1214,10 +1657,24 @@ return 0; } +static int seq_profile_learning_count_show(struct seq_file *seq, void *v) +{ + struct aa_proxy *proxy = seq->private; + struct aa_label *label = aa_get_label_rcu(&proxy->label); + struct aa_profile *profile = labels_profile(label); + int count = READ_ONCE(profile->learning_cache.size); + + seq_printf(seq, "%d\n", count); + aa_put_label(label); + + return 0; +} + SEQ_PROFILE_FOPS(name); SEQ_PROFILE_FOPS(mode); SEQ_PROFILE_FOPS(attach); SEQ_PROFILE_FOPS(hash); +SEQ_PROFILE_FOPS(learning_count); /* * namespace based files @@ -1329,6 +1786,14 @@ .release = seq_rawdata_release, \ } \ +static struct aa_loaddata *get_loaddata_common_ref(struct aa_common_ref *ref) +{ + if (ref) + return aa_get_i_loaddata(container_of(ref, struct aa_loaddata, + count)); + return NULL; +} + static int seq_rawdata_open(struct inode *inode, struct file *file, int (*show)(struct seq_file *, void *)) { @@ -1445,7 +1910,7 @@ struct rawdata_f_data *private = file->private_data; return simple_read_from_buffer(buf, size, ppos, - RAWDATA_F_DATA_BUF(private), + private->data, private->loaddata->size); } @@ -1478,8 +1943,7 @@ private->loaddata = loaddata; error = decompress_zstd(loaddata->data, loaddata->compressed_size, - RAWDATA_F_DATA_BUF(private), - loaddata->size); + private->data, loaddata->size); if (error) goto fail_decompress; @@ -1834,6 +2298,12 @@ goto fail; profile->dents[AAFS_PROF_ATTACH] = dent; + dent = create_profile_file(dir, "learning_count", profile, + &seq_profile_learning_count_fops); + if (IS_ERR(dent)) + goto fail; + profile->dents[AAFS_PROF_LEARNING_COUNT] = dent; + if (profile->hash) { dent = create_profile_file(dir, "sha256", profile, &seq_profile_hash_fops); @@ -2384,6 +2854,12 @@ { } }; +static struct aa_sfs_entry aa_sfs_entry_ipc[] = { + AA_SFS_FILE_STRING("posix_mqueue", + "create read write open delete setattr getattr label"), + { } +}; + static struct aa_sfs_entry aa_sfs_entry_ptrace[] = { AA_SFS_FILE_STRING("mask", "read trace"), { } @@ -2409,7 +2885,9 @@ AA_SFS_FILE_BOOLEAN("post_nnp_subset", 1), AA_SFS_FILE_BOOLEAN("computed_longest_left", 1), AA_SFS_DIR("attach_conditions", aa_sfs_entry_attach), + AA_SFS_FILE_BOOLEAN("interruptible", 1), AA_SFS_FILE_BOOLEAN("disconnected.path", 1), + AA_SFS_FILE_BOOLEAN("disconnected.ipc", 1), AA_SFS_FILE_BOOLEAN("kill.signal", 1), AA_SFS_FILE_STRING("version", "1.2"), { } @@ -2417,6 +2895,11 @@ static struct aa_sfs_entry aa_sfs_entry_unconfined[] = { AA_SFS_FILE_BOOLEAN("change_profile", 1), + /* Retain backwards compatibility with Ubuntu userspace + * code that is expecting integer values for these sysctls + */ + AA_SFS_FILE_BOOLEAN_INTPRINT("userns", 1), + AA_SFS_FILE_BOOLEAN_INTPRINT("io_uring", 1), { } }; @@ -2429,16 +2912,36 @@ { } }; +static struct aa_sfs_entry aa_sfs_entry_notify[] = { + AA_SFS_FILE_STRING("user", "file tags"), + { } +}; + +static struct aa_sfs_entry aa_sfs_entry_notify_versions[] = { + AA_SFS_FILE_BOOLEAN("v3", 1), + AA_SFS_FILE_BOOLEAN("v5", 1), + { } +}; + +/* permstable v1: skipped + v2: accept1 index, no accept2 + v3: accept1 index, accept2 flags +*/ #define PERMS32STR "allow deny subtree cond kill complain prompt audit quiet hide xindex tag label" static struct aa_sfs_entry aa_sfs_entry_policy[] = { AA_SFS_DIR("versions", aa_sfs_entry_versions), AA_SFS_FILE_BOOLEAN("set_load", 1), + AA_SFS_FILE_BOOLEAN("diff_encode", 1), /* number of out of band transitions supported */ AA_SFS_FILE_U64("outofband", MAX_OOB_SUPPORTED), AA_SFS_FILE_U64("permstable32_version", 3), AA_SFS_FILE_STRING("permstable32", PERMS32STR), + AA_SFS_FILE_U64("metadata_tagging_version", 1), AA_SFS_FILE_U64("state32", 1), AA_SFS_DIR("unconfined_restrictions", aa_sfs_entry_unconfined), + AA_SFS_DIR("notify", aa_sfs_entry_notify), + AA_SFS_DIR("notify_versions", aa_sfs_entry_notify_versions), + AA_SFS_FILE_BOOLEAN("compressed_load", 1), { } }; @@ -2452,6 +2955,7 @@ AA_SFS_FILE_BOOLEAN("profile", 1), AA_SFS_FILE_BOOLEAN("pivot_root", 0), AA_SFS_FILE_STRING("mask", "userns_create"), + AA_SFS_FILE_STRING("userns_create", "pciu&"), { } }; @@ -2481,8 +2985,11 @@ AA_SFS_DIR("policy", aa_sfs_entry_policy), AA_SFS_DIR("domain", aa_sfs_entry_domain), AA_SFS_DIR("file", aa_sfs_entry_file), + AA_SFS_DIR("network", aa_sfs_entry_network_compat), + AA_SFS_DIR("ipc", aa_sfs_entry_ipc), AA_SFS_DIR("network_v8", aa_sfs_entry_network), AA_SFS_DIR("network_v9", aa_sfs_entry_networkv9), + AA_SFS_DIR("network_v9_skb", aa_sfs_entry_networkv9_skb), AA_SFS_DIR("mount", aa_sfs_entry_mount), AA_SFS_DIR("namespaces", aa_sfs_entry_ns), AA_SFS_FILE_U64("capability", VFS_CAP_FLAGS_MASK), @@ -2498,6 +3005,7 @@ static struct aa_sfs_entry aa_sfs_entry_apparmor[] = { AA_SFS_FILE_FOPS(".access", 0666, &aa_sfs_access), + AA_SFS_FILE_FOPS(".notify", 0666, &aa_sfs_notify_fops), AA_SFS_FILE_FOPS(".stacked", 0444, &seq_ns_stacked_fops), AA_SFS_FILE_FOPS(".ns_stacked", 0444, &seq_ns_nsstacked_fops), AA_SFS_FILE_FOPS(".ns_level", 0444, &seq_ns_level_fops), --- linux-nvidia-7.0.0.orig/security/apparmor/audit.c +++ linux-nvidia-7.0.0/security/apparmor/audit.c @@ -52,7 +52,7 @@ "unknown", "unknown", "net", - "unknown", + "netv9", "label", "posix_mqueue", "io_uring", @@ -67,7 +67,7 @@ "unknown", "unknown", "unknown", - "unknown", + "netv9_packet", "X", "dbus", }; @@ -289,3 +289,283 @@ } return 0; } + +/****************************** audit cache *******************************/ + +static int uid_cmp(kuid_t lhs, kuid_t rhs) +{ + if (uid_lt(lhs, rhs)) + return -1; + if (uid_gt(lhs, rhs)) + return 1; + return 0; +} + +/* std C cmp. negative is less than, 0 is equal, positive greater than */ +long aa_audit_data_cmp(struct apparmor_audit_data *lhs, + struct apparmor_audit_data *rhs) +{ + long res; + + /* don't compare type */ + res = lhs->class - rhs->class; + if (res) + return res; + /* don't compare op */ + if (lhs->flags & AUDIT_TAILGLOB_NAME) + /* lhs glob matches strings longer than it */ + res = strncmp(lhs->name, rhs->name, strlen(lhs->name)); + else + res = strcmp(lhs->name, rhs->name); + if (res) + return res; + res = aa_label_cmp(lhs->subj_label, rhs->subj_label); + if (res) + return res; + switch (lhs->class) { + case AA_CLASS_FILE: + if (lhs->subj_cred) { + if (rhs->subj_cred) { + return uid_cmp(lhs->subj_cred->fsuid, + rhs->subj_cred->fsuid); + } else { + return 1; + } + } else if (rhs->subj_cred) { + return -1; + } + res = uid_cmp(lhs->fs.ouid, rhs->fs.ouid); + if (res) + return res; + res = lhs->fs.target - rhs->fs.target; + if (res) + return res; + } + return 0; +} + +static void audit_node_free(struct aa_audit_node *node) +{ + if (!node) + return; + + AA_BUG(!list_empty(&node->list)); + + /* common data that needs freed */ + kfree(node->data.name); + aa_put_label(node->data.subj_label); + if (node->data.subj_cred) + put_cred(node->data.subj_cred); + + /* class specific data that needs freed */ + switch (node->data.class) { + case AA_CLASS_FILE: + aa_put_label(node->data.peer); + kfree(node->data.fs.target); + } + + kmem_cache_free(aa_audit_slab, node); +} + +static void audit_node_free_rcu(struct rcu_head *head) +{ + struct aa_audit_node *node = container_of(head, typeof(*node), rcu); + + audit_node_free(node); +} + +void aa_audit_node_free_kref(struct kref *kref) +{ + struct aa_audit_node *node = container_of(kref, struct aa_audit_node, + count); + call_rcu(&node->rcu, audit_node_free_rcu); +} + +struct aa_audit_node *aa_dup_audit_data(struct apparmor_audit_data *orig, + gfp_t gfp) +{ + struct aa_audit_node *copy; + + copy = kmem_cache_zalloc(aa_audit_slab, gfp); + if (!copy) + return NULL; + kref_init(©->count); + + copy->knotif.ad = ©->data; + INIT_LIST_HEAD(©->list); + /* copy class early so aa_free_audit_node can use switch on failure */ + copy->data.class = orig->class; + copy->data.flags = orig->flags; + + /* handle anything with possible failure first */ + if (orig->name) { + copy->data.name = kstrdup(orig->name, gfp); + if (!copy->data.name) + goto fail; + } + /* don't dup info */ + switch (orig->class) { + case AA_CLASS_FILE: + if (orig->fs.target) { + copy->data.fs.target = kstrdup(orig->fs.target, gfp); + if (!copy->data.fs.target) + goto fail; + } + break; + case AA_CLASS_MOUNT: + if (orig->mnt.src_name) { + copy->data.mnt.src_name = kstrdup(orig->mnt.src_name, gfp); + if (!copy->data.mnt.src_name) + goto fail; + } + if (orig->mnt.type) { + copy->data.mnt.type = kstrdup(orig->mnt.type, gfp); + if (!copy->data.mnt.type) + goto fail; + } + // copy->mnt.trans; not used atm + if (orig->mnt.data) { + copy->data.mnt.data = kstrdup(orig->mnt.data, gfp); + if (!copy->data.mnt.data) + goto fail; + } + break; + } + + /* now inc counts, and copy data that can't fail */ + copy->data.error = orig->error; + copy->data.type = orig->type; + copy->data.request = orig->request; + copy->data.denied = orig->denied; + copy->data.subj_label = aa_get_label(orig->subj_label); + + if (orig->subj_cred) + copy->data.subj_cred = get_cred(orig->subj_cred); + + switch (orig->class) { + case AA_CLASS_NET: + /* + * peer_sk; + * addr; + */ + fallthrough; + case AA_CLASS_FILE: + copy->data.fs.ouid = orig->fs.ouid; + break; + case AA_CLASS_RLIMITS: + case AA_CLASS_SIGNAL: + case AA_CLASS_POSIX_MQUEUE: + copy->data.peer = aa_get_label(orig->peer); + break; +/* + * case AA_CLASS_IFACE: + * copy->data.iface.profile = aa_get_label(orig.iface.profile); + * break; + */ + }; + + + return copy; +fail: + audit_node_free(copy); + return NULL; +} + +#define __audit_cache_find(C, AD, COND...) \ +({ \ + struct aa_audit_node *__node; \ + list_for_each_entry_rcu(__node, &(C)->head, list, COND) { \ + if (aa_audit_data_cmp(&__node->data, AD) == 0) \ + goto __out_skip; \ + } \ + __node = NULL; \ +__out_skip: \ + __node; \ +}) + +// increments refcount on node +struct aa_audit_node *aa_audit_cache_find(struct aa_audit_cache *cache, + struct apparmor_audit_data *ad) +{ + struct aa_audit_node *node; + + rcu_read_lock(); + node = __audit_cache_find(cache, ad); + aa_get_audit_node(node); + rcu_read_unlock(); + + return node; +} + +/** + * aa_audit_cache_insert - insert an audit node into the cache + * @cache: the cache to insert into + * @node: the audit node to insert into the cache + * + * Returns: refcounted matching node in cache OR @node if @node was inserted. + * + * Increments refcount on node if successfully inserted. Assumes caller + * already has valid ref count. + * Increments refcount on existing node if returned + */ +struct aa_audit_node *aa_audit_cache_insert(struct aa_audit_cache *cache, + struct aa_audit_node *node) + +{ + struct aa_audit_node *tmp; + + spin_lock(&cache->lock); + tmp = __audit_cache_find(cache, &node->data, + spin_is_lock(&cache->lock)); + if (!tmp) { + list_add_rcu(&node->list, &cache->head); + tmp = node; + cache->size++; + } + + aa_get_audit_node(tmp); + /* else raced another insert */ + spin_unlock(&cache->lock); + + return tmp; +} + +/** + * aa_audit_cache_remove - remove an audit node from the cache + * @cache: cache to remove from + * @node: the audit node to remov from the cache + */ +void aa_audit_cache_remove(struct aa_audit_cache *cache, + struct aa_audit_node *node) + +{ + spin_lock(&cache->lock); + list_del_rcu(&node->list); + cache->size--; + aa_put_audit_node(node); + spin_unlock(&cache->lock); + +} + +void aa_audit_cache_update_ent(struct aa_audit_cache *cache, + struct aa_audit_node *node, + struct apparmor_audit_data *data) +{ + spin_lock(&cache->lock); + node->data.denied |= data->denied; + node->data.request = (node->data.request | data->request) & + ~node->data.denied; + spin_unlock(&cache->lock); +} + +/* assumes rcu callback has already happened and list can not be walked */ +void aa_audit_cache_destroy(struct aa_audit_cache *cache) +{ + struct aa_audit_node *node, *tmp; + + list_for_each_entry_safe(node, tmp, &cache->head, list) { + list_del_init(&node->list); + aa_put_audit_node(node); + } + cache->size = 0; +} --- linux-nvidia-7.0.0.orig/security/apparmor/domain.c +++ linux-nvidia-7.0.0/security/apparmor/domain.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -705,7 +706,7 @@ /* Don't cause error if auditing fails */ (void) aa_audit_file(subj_cred, profile, &perms, OP_EXEC, MAY_EXEC, name, target, new, cond->uid, - info, error); + info, error, false); } if (new) { AA_DEBUG(DEBUG_DOMAIN, "unconfined attached to new label"); @@ -778,9 +779,8 @@ } audit: - aa_audit_file(subj_cred, profile, &perms, OP_EXEC, MAY_EXEC, name, - target, new, - cond->uid, info, error); + aa_audit_file(subj_cred, profile, &perms, OP_EXEC, MAY_EXEC, name, target, new, + cond->uid, info, error, true); if (!new || nonewprivs) { aa_put_label(new); return ERR_PTR(error); @@ -859,10 +859,19 @@ audit: return aa_audit_file(subj_cred, profile, &perms, OP_EXEC, AA_MAY_ONEXEC, xname, - NULL, onexec, cond->uid, info, error); + NULL, onexec, cond->uid, info, error, false); } /* ensure none ns domain transitions are correctly applied with onexec */ +static struct aa_label *label_merge_wrap(struct aa_label *a, struct aa_label *b, + gfp_t gfp) +{ + struct aa_label *label = aa_label_merge(a, b, gfp); + + if (!label) + return ERR_PTR(-ENOMEM); + return label; +} static struct aa_label *handle_onexec(const struct cred *subj_cred, struct aa_label *label, @@ -890,12 +899,13 @@ return ERR_PTR(error); new = fn_label_build_in_scope(label, profile, GFP_KERNEL, - stack ? aa_label_merge(&profile->label, onexec, - GFP_KERNEL) + stack ? label_merge_wrap(&profile->label, onexec, + GFP_KERNEL) : aa_get_newest_label(onexec), profile_transition(subj_cred, profile, bprm, buffer, cond, unsafe)); - if (new) + AA_BUG(!new); + if (!IS_ERR(new)) return new; /* TODO: get rid of GLOBAL_ROOT_UID */ @@ -904,7 +914,8 @@ OP_CHANGE_ONEXEC, AA_MAY_ONEXEC, bprm->filename, NULL, onexec, GLOBAL_ROOT_UID, - "failed to build target label", -ENOMEM)); + "failed to build target label", + PTR_ERR(new), false)); return ERR_PTR(error); } @@ -968,13 +979,9 @@ buffer, &cond, &unsafe)); - AA_BUG(!new); if (IS_ERR(new)) { error = PTR_ERR(new); goto done; - } else if (!new) { - error = -ENOMEM; - goto done; } /* Policy has specified a domain transitions. If no_new_privs and @@ -1040,7 +1047,8 @@ aa_audit_file(current_cred(), profile, &nullperms, OP_EXEC, MAY_EXEC, bprm->filename, NULL, new, - vfsuid_into_kuid(vfsuid), info, error)); + vfsuid_into_kuid(vfsuid), info, error, + false)); aa_put_label(new); goto done; } @@ -1091,7 +1099,7 @@ AA_MAY_CHANGEHAT, name, hat ? hat->base.hname : NULL, hat ? &hat->label : NULL, GLOBAL_ROOT_UID, info, - error); + error, false); if (!hat || (error && error != -ENOENT)) return ERR_PTR(error); /* if hat && error - complain mode, already audited and we adjust for @@ -1109,6 +1117,7 @@ int count, int flags) { struct aa_profile *profile, *root, *hat = NULL; + struct aa_ns *ns, *new_ns; struct aa_label *new; struct label_it it; bool sibling = false; @@ -1119,6 +1128,32 @@ AA_BUG(!hats); AA_BUG(count < 1); + /* + * Acquire the newest label and then hold the lock until we choose a + * hat, so that profile replacement doesn't atomically truncate the + * list of potential hats. Because we are getting the namespaces from + * the profiles and label, we can rely on the namespaces being live + * and avoid incrementing their refcounts while grabbing the lock. + */ + label = aa_get_label(label); + ns = labels_ns(label); + +retry: + mutex_lock_nested(&ns->lock, ns->level); + if (label_is_stale(label)) { + new = aa_get_newest_label(label); + new_ns = labels_ns(new); + if (new_ns != ns) { + aa_put_label(new); + mutex_unlock(&ns->lock); + ns = new_ns; + label = new; + goto retry; + } + aa_put_label(label); + label = new; + } + if (PROFILE_IS_HAT(labels_profile(label))) sibling = true; @@ -1127,7 +1162,7 @@ name = hats[i]; label_for_each_in_scope(it, labels_ns(label), label, profile) { if (sibling && PROFILE_IS_HAT(profile)) { - root = aa_get_profile_rcu(&profile->parent); + root = aa_get_profile(profile->parent); } else if (!sibling && !PROFILE_IS_HAT(profile)) { root = aa_get_profile(profile); } else { /* conflicting change type */ @@ -1184,9 +1219,10 @@ aa_audit_file(subj_cred, profile, &nullperms, OP_CHANGE_HAT, AA_MAY_CHANGEHAT, name, NULL, NULL, - GLOBAL_ROOT_UID, info, error); + GLOBAL_ROOT_UID, info, error, false); } } + mutex_unlock(&ns->lock); return ERR_PTR(error); build: @@ -1194,11 +1230,9 @@ build_change_hat(subj_cred, profile, name, sibling), aa_get_label(&profile->label)); - if (!new) { - info = "label build failed"; - error = -ENOMEM; - goto fail; - } /* else if (IS_ERR) build_change_hat has logged error so return new */ + mutex_unlock(&ns->lock); + AA_BUG(!new); + /* return new label or error ptr */ return new; } @@ -1343,7 +1377,7 @@ fn_for_each_in_scope(label, profile, aa_audit_file(subj_cred, profile, &perms, OP_CHANGE_HAT, AA_MAY_CHANGEHAT, NULL, NULL, target, - GLOBAL_ROOT_UID, info, error)); + GLOBAL_ROOT_UID, info, error, false)); goto out; } @@ -1367,7 +1401,7 @@ error = aa_audit_file(subj_cred, profile, perms, op, request, name, NULL, target, GLOBAL_ROOT_UID, info, - error); + error, false); return error; } @@ -1451,7 +1485,8 @@ (void) fn_for_each_in_scope(label, profile, aa_audit_file(subj_cred, profile, &perms, op, request, auditname, NULL, target, - GLOBAL_ROOT_UID, stack_msg, 0)); + GLOBAL_ROOT_UID, stack_msg, 0, + false)); perms.audit = 0; } @@ -1527,6 +1562,12 @@ new = fn_label_build_in_scope(label, profile, GFP_KERNEL, aa_get_label(target), aa_get_label(&profile->label)); + AA_BUG(!new); + if (IS_ERR(new)) { + error = PTR_ERR(new); + new = NULL; + goto out; + } /* * no new privs prevents domain transitions that would * reduce restrictions. @@ -1557,10 +1598,9 @@ } error = aa_replace_current_label(new); } else { - if (new) { - aa_put_label(new); - new = NULL; - } + /* new will be recomputed so at exec time. So discard */ + aa_put_label(new); + new = NULL; /* full transition will be built in exec path */ aa_set_current_onexec(target, stack); @@ -1571,7 +1611,7 @@ aa_audit_file(subj_cred, profile, &perms, op, request, auditname, NULL, new ? new : target, - GLOBAL_ROOT_UID, info, error)); + GLOBAL_ROOT_UID, info, error, false)); out: aa_put_label(new); --- linux-nvidia-7.0.0.orig/security/apparmor/file.c +++ linux-nvidia-7.0.0/security/apparmor/file.c @@ -13,14 +13,17 @@ #include #include #include +#include #include "include/af_unix.h" #include "include/apparmor.h" #include "include/audit.h" #include "include/cred.h" #include "include/file.h" +#include "include/ipc.h" #include "include/match.h" #include "include/net.h" +#include "include/notify.h" #include "include/path.h" #include "include/policy.h" #include "include/label.h" @@ -76,6 +79,106 @@ } } +// ??? differentiate between +// cached - allow : no audit == 1 +// cached - deny : no audit < 0 +// cached - complain : no audit +// cached - partial : audit missing part : as miss +// not cached = 0 +static int check_cache(struct aa_profile *profile, + struct apparmor_audit_data *ad) +{ + struct aa_audit_node *hit; + + AA_BUG(!profile); + ad->subj_label = &profile->label; // normally set in aa_audit + + /* TODO: need rcu locking around whole check once we allow + * removing node from cache + */ + AA_DEBUG(DEBUG_UPCALL, "cache check: profile '%s', pid %d name:'%s'", + profile->base.hname, current->pid, ad->name); + hit = aa_audit_cache_find(&profile->learning_cache, ad); + if (hit) { + AA_DEBUG(DEBUG_UPCALL, " matched node in audit cache"); + if (ad->request & hit->data.denied) { + /* this request could only partly succeed prompting for + * the part and failing makes no sense + */ + AA_DEBUG(DEBUG_UPCALL, + " hit denied, request: 0x%x by cached deny 0x%x\n", + ad->request, hit->data.denied); + aa_put_audit_node(hit); + return ad->error; + } else if (ad->request & ~hit->data.request) { + /* asking for more perms than is cached */ + AA_DEBUG(DEBUG_UPCALL, + " miss insufficient perms, request: 0x%x cached 0x%x\n", + ad->request, hit->data.request); + /* continue to do prompt */ + } else { + AA_DEBUG(DEBUG_UPCALL, "cache hit->error %d. returning 0", + hit->data.error); + aa_put_audit_node(hit); + /* don't audit: if its in the cache already audited */ + return 0; + } + aa_put_audit_node(hit); + } else { + AA_DEBUG(DEBUG_UPCALL, "cache miss"); + } + + return 1; +} + +// error - immediate return +// - debug message do audit +// caching is handled on listener task side +static int check_user(struct aa_profile *profile, + struct apparmor_audit_data *ad, + struct aa_perms *perms) +{ + struct aa_audit_node *node = NULL; + int err; + + /* assume we are going to dispatch */ + node = aa_dup_audit_data(ad, GFP_KERNEL); + if (!node) { + AA_DEBUG(DEBUG_UPCALL, + "notifcation failed to duplicate with error -ENOMEM\n"); + /* do audit */ + return -ENOMEM; + } + + get_task_struct(current); + node->data.subjtsk = current; + node->data.type = AUDIT_APPARMOR_USER; + node->data.request = ad->request; + node->data.tags = ad->tags; + node->data.denied = ad->request & ~perms->allow; + AA_DEBUG_PROFILE(profile, DEBUG_UPCALL, "attempting upcall\n"); + err = aa_do_notification(APPARMOR_NOTIF_OP, node); + put_task_struct(node->data.subjtsk); + + if (err) { + // do we want to do something special with -ERESTARTSYS + AA_DEBUG(DEBUG_UPCALL, "notifcation failed with error %d\n", + err); + goto return_to_audit; + } + + /* update based on node data for audit */ + perms->deny = node->data.denied; + perms->allow = node->data.request & ~node->data.denied; + ad->request |= node->data.request; + ad->denied = node->data.denied; + ad->error = node->data.error; + +return_to_audit: + aa_put_audit_node(node); + return err; +} + /** * aa_audit_file - handle the auditing of file operations * @subj_cred: cred of the subject @@ -96,9 +199,10 @@ struct aa_profile *profile, struct aa_perms *perms, const char *op, u32 request, const char *name, const char *target, struct aa_label *tlabel, - kuid_t ouid, const char *info, int error) + kuid_t ouid, const char *info, int error, bool prompt) { int type = AUDIT_APPARMOR_AUTO; + int err; DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_TASK, AA_CLASS_FILE, op); ad.subj_cred = subj_cred; @@ -111,6 +215,46 @@ ad.info = info; ad.error = error; ad.common.u.tsk = NULL; + ad.subjtsk = NULL; + + ad.denied = denied_perms(perms, ad.request); + + if (unlikely(ad.error)) { + u32 implicit_deny; + + /* learning cache - not audit dedup yet */ + err = check_cache(profile, &ad); + if (err <= 0) { + AA_DEBUG(DEBUG_UPCALL, "cache early bail %d\n", err); + /* cached */ + return err; + } + implicit_deny = (ad.request & ~perms->allow) & ~perms->deny; + if (USER_MODE(profile)) + perms->prompt = ALL_PERMS_MASK; + + if (ad.request & MAY_EXEC) + AA_DEBUG(DEBUG_UPCALL, + "do prompt %d: exec req 0x%x, allow 0x%x, deny 0x%x, ideny 0x%x, prompt 0x%x", + prompt, ad.request, perms->allow, perms->deny, + implicit_deny, perms->prompt); + + /* don't prompt + * - if explicit deny + * - if implicit_deny is not entirely covered by prompt + * as no point asking user to just deny it anyway. + */ + if (prompt && !(request & perms->deny) && + (perms->prompt & implicit_deny) == implicit_deny) { + err = check_user(profile, &ad, perms); + if (err == -ERESTARTSYS) { + AA_DEBUG(DEBUG_UPCALL, " check user returned -ERESTART_SYS"); + /* are there other errors we should bail on */ + return err; + } + } else + AA_DEBUG_PROFILE(profile, DEBUG_UPCALL, "not prompting prompt %d, requiest 0x%x, deny 0x%x, prompt 0x%x implicit deny 0x%x", prompt, request, perms->deny, perms->prompt, implicit_deny); + } if (likely(!ad.error)) { u32 mask = perms->audit; @@ -142,14 +286,15 @@ return ad.error; } - ad.denied = ad.request & ~perms->allow; - return aa_audit(type, profile, &ad, file_audit_cb); + err = aa_audit(type, profile, &ad, file_audit_cb); + return err; } static int path_name(const char *op, const struct cred *subj_cred, struct aa_label *label, const struct path *path, int flags, char *buffer, - const char **name, struct path_cond *cond, u32 request) + const char **name, struct path_cond *cond, u32 request, + bool prompt) { struct aa_profile *profile; const char *info = NULL; @@ -165,7 +310,8 @@ fn_for_each_confined(label, profile, aa_audit_file(subj_cred, profile, &nullperms, op, request, *name, - NULL, NULL, cond->uid, info, error)); + NULL, NULL, cond->uid, info, error, + prompt)); return error; } @@ -226,13 +372,13 @@ int __aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_profile *profile, const char *name, u32 request, struct path_cond *cond, int flags, - struct aa_perms *perms) + struct aa_perms *perms, bool prompt) { struct aa_ruleset *rules = profile->label.rules[0]; int e = 0; if (profile_unconfined(profile) || - ((flags & PATH_SOCK_COND) && !RULE_MEDIATES_v9NET(rules))) + ((flags & PATH_SOCK_COND) && !RULE_MEDIATES_UNIX(rules))) return 0; aa_str_perms(rules->file, rules->file->start[AA_CLASS_FILE], name, cond, perms); @@ -240,7 +386,7 @@ e = -EACCES; return aa_audit_file(subj_cred, profile, perms, op, request, name, NULL, NULL, - cond->uid, NULL, e); + cond->uid, NULL, e, prompt); } @@ -248,7 +394,8 @@ struct aa_profile *profile, const struct path *path, char *buffer, u32 request, struct path_cond *cond, int flags, - struct aa_perms *perms) + struct aa_perms *perms, + u32 *allow, bool prompt) { const char *name; int error; @@ -258,11 +405,16 @@ error = path_name(op, subj_cred, &profile->label, path, flags | profile->path_flags, buffer, &name, cond, - request); + request, prompt); if (error) return error; - return __aa_path_perm(op, subj_cred, profile, name, request, cond, - flags, perms); + error = __aa_path_perm(op, subj_cred, profile, name, request, cond, + flags, perms, prompt); + /* accumulate intersection of allowed to set on object cache */ + if (!error && allow) + *allow &= perms->allow; + + return error; } /** @@ -274,13 +426,14 @@ * @flags: any additional path flags beyond what the profile specifies * @request: requested permissions * @cond: conditional info for this request (NOT NULL) + * @allow: in/out intersected set of allowed permissions (MAYBE NULL) * * Returns: %0 else error if access denied or other error */ int aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_label *label, const struct path *path, int flags, u32 request, - struct path_cond *cond) + struct path_cond *cond, u32 *allow) { struct aa_perms perms = {}; struct aa_profile *profile; @@ -294,7 +447,8 @@ return -ENOMEM; error = fn_for_each_confined(label, profile, profile_path_perm(op, subj_cred, profile, path, buffer, - request, cond, flags, &perms)); + request, cond, flags, &perms, allow, + true)); aa_put_buffer(buffer); @@ -337,14 +491,14 @@ error = path_name(OP_LINK, subj_cred, &profile->label, link, profile->path_flags, - buffer, &lname, cond, AA_MAY_LINK); + buffer, &lname, cond, AA_MAY_LINK, false); if (error) goto audit; /* buffer2 freed below, tname is pointer in buffer2 */ error = path_name(OP_LINK, subj_cred, &profile->label, target, profile->path_flags, - buffer2, &tname, cond, AA_MAY_LINK); + buffer2, &tname, cond, AA_MAY_LINK, false); if (error) goto audit; @@ -403,9 +557,9 @@ error = 0; audit: - return aa_audit_file(subj_cred, - profile, &lperms, OP_LINK, request, lname, tname, - NULL, cond->uid, info, error); + return aa_audit_file(subj_cred, profile, &lperms, OP_LINK, request, + lname, tname, + NULL, cond->uid, info, error, false); } /** @@ -460,7 +614,7 @@ } static void update_file_ctx(struct aa_file_ctx *fctx, struct aa_label *label, - u32 request) + u32 request, u32 allow) { struct aa_label *l, *old; @@ -475,42 +629,44 @@ aa_put_label(old); } else aa_put_label(l); - fctx->allow |= request; + /* TODO: reduction of perms here should result in revalidation + * of components not already checked. Only affects stacking + */ + fctx->allow = allow; } spin_unlock(&fctx->lock); } -static int __file_path_perm(const char *op, const struct cred *subj_cred, - struct aa_label *label, - struct aa_label *flabel, struct file *file, - u32 request, u32 denied, bool in_atomic) +static int __path_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, struct aa_label *flabel, + struct file *file, u32 request, u32 denied, + struct path_cond *cond, int flags, + bool in_atomic, bool is_mqueue, + struct apparmor_audit_data *ad) { struct aa_profile *profile; struct aa_perms perms = {}; - vfsuid_t vfsuid = i_uid_into_vfsuid(file_mnt_idmap(file), - file_inode(file)); - struct path_cond cond = { - .uid = vfsuid_into_kuid(vfsuid), - .mode = file_inode(file)->i_mode - }; char *buffer; - int flags, error; + u32 allow = ALL_PERMS_MASK; + int error; /* revalidation due to label out of date. No revocation at this time */ if (!denied && aa_label_is_subset(flabel, label)) /* TODO: check for revocation on stale profiles */ return 0; - flags = PATH_DELEGATE_DELETED | (S_ISDIR(cond.mode) ? PATH_IS_DIR : 0); buffer = aa_get_buffer(in_atomic); if (!buffer) return -ENOMEM; /* check every profile in task label not in current cache */ - error = fn_for_each_not_in_set(flabel, label, profile, + error = fn_for_each_not_in_set(flabel, label, profile, is_mqueue ? + aa_profile_mqueue_perm(profile, &file->f_path, + request, buffer, ad) : profile_path_perm(op, subj_cred, profile, &file->f_path, buffer, - request, &cond, flags, &perms)); + request, cond, flags, &perms, + &allow, false)); if (denied && !error) { /* * check every profile in file label that was not tested @@ -521,26 +677,51 @@ * TODO: don't audit here */ if (label == flabel) - error = fn_for_each(label, profile, + error = fn_for_each(label, profile, is_mqueue ? + aa_profile_mqueue_perm(profile, &file->f_path, + request, buffer, ad) : profile_path_perm(op, subj_cred, profile, &file->f_path, - buffer, request, &cond, flags, - &perms)); + buffer, request, cond, flags, + &perms, &allow, false)); else - error = fn_for_each_not_in_set(label, flabel, profile, + error = fn_for_each_not_in_set(label, flabel, profile, is_mqueue ? + aa_profile_mqueue_perm(profile, &file->f_path, + request, buffer, ad) : profile_path_perm(op, subj_cred, profile, &file->f_path, - buffer, request, &cond, flags, - &perms)); + buffer, request, cond, flags, + &perms, &allow, false)); } if (!error) - update_file_ctx(file_ctx(file), label, request); + update_file_ctx(file_ctx(file), label, request, + is_mqueue ? request : allow); aa_put_buffer(buffer); return error; } +static int __file_path_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + struct aa_label *flabel, struct file *file, + u32 request, u32 denied, bool in_atomic) +{ + vfsuid_t vfsuid = i_uid_into_vfsuid(file_mnt_idmap(file), + file_inode(file)); + struct path_cond cond = { + .uid = vfsuid_into_kuid(vfsuid), + .mode = file_inode(file)->i_mode + }; + int flags; + + flags = PATH_DELEGATE_DELETED | (S_ISDIR(cond.mode) ? PATH_IS_DIR : 0); + + return __path_perm(op, subj_cred, label, flabel, file, + request, denied, &cond, flags, in_atomic, + false, NULL); +} + static int __file_sock_perm(const char *op, const struct cred *subj_cred, struct aa_label *label, struct aa_label *flabel, struct file *file, @@ -561,11 +742,28 @@ request, file)); } if (!error) - update_file_ctx(file_ctx(file), label, request); + update_file_ctx(file_ctx(file), label, request, request); return error; } +static int __file_mqueue_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + struct aa_label *flabel, struct file *file, + u32 request, u32 denied, bool in_atomic) +{ + DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_NONE, AA_CLASS_POSIX_MQUEUE, op); + + ad.subj_cred = subj_cred; + ad.request = request; + ad.peer = NULL; + ad.mq.ouid = file_inode(file)->i_uid; + + return __path_perm(op, subj_cred, label, flabel, file, + request, denied, NULL, 0, in_atomic, + true, &ad); +} + /* for now separate fn to indicate semantics of the check */ static bool __file_is_delegated(struct aa_label *obj_label) { @@ -657,7 +855,10 @@ flabel = aa_get_newest_label(flabel); rcu_read_unlock(); - if (path_mediated_fs(file->f_path.dentry)) + if (is_mqueue_inode(file_inode(file))) { + error = __file_mqueue_perm(op, subj_cred, label, flabel, file, + request, denied, true); + } else if (path_mediated_fs(file->f_path.dentry)) error = __file_path_perm(op, subj_cred, label, flabel, file, request, denied, in_atomic); --- linux-nvidia-7.0.0.orig/security/apparmor/include/af_inet.h +++ linux-nvidia-7.0.0/security/apparmor/include/af_inet.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AppArmor security module + * + * This file contains AppArmor af_unix fine grained mediation + * + * Copyright 2024 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ +#ifndef __AA_AF_INET_H + +#include "label.h" + +struct cred; +struct sock; +struct sk_buff; +struct nf_hook_state; +struct match_addr; +struct apparmor_audit_data; + +int aa_inet_peer_perm(const struct cred *subj_cred, + struct aa_label *label, const char *op, u32 request, + const struct sock *sk, const struct sock *peer_sk, + struct aa_label *peer_label); +int aa_inet_label_sk_perm(const struct cred *subj_cred, + struct aa_label *label, const char *op, u32 request, + const struct sock *sk); +int aa_inet_sock_perm(const char *op, u32 request, struct socket *sock); +int aa_inet_create_perm(struct aa_label *label, int family, int type, + int protocol); +int aa_inet_bind_perm(struct socket *sock, struct sockaddr *address, + int addrlen); +int aa_inet_connect_perm(struct socket *sock, struct sockaddr *address, + int addrlen); +int aa_inet_listen_perm(struct socket *sock, int backlog); +int aa_inet_accept_perm(struct socket *sock, struct socket *newsock); +int aa_inet_msg_perm(const char *op, u32 request, struct socket *sock, + struct msghdr *msg, int size); +int aa_inet_opt_perm(const char *op, u32 request, struct socket *sock, int level, + int optname); +int aa_inet_file_perm(const struct cred *subj_cred, + struct aa_label *label, const char *op, u32 request, + struct socket *sock); + + +int aa_secmark_relabel_packet(u32 sid); +int __aa_sock_rcv_skb(struct aa_label *label, const struct sock *sk, + const struct sk_buff *skb); +int __aa_inet_conn_request(struct aa_label *label, const struct sock *sk, + const struct sk_buff *skb, + const struct request_sock *req); +int __aa_ip_forward(struct aa_label *label, struct sk_buff *skb, + const struct nf_hook_state *state); +int __aa_ip_postroute(struct aa_label *label, const struct sock *sk, + const struct sk_buff *skb, + const struct nf_hook_state *state); +struct aa_label *__aa_ip_localout(struct aa_label *label, + const struct sock *sk, + const struct sk_buff *skb); + +#endif /* __AA_AF_INET_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/apparmor.h +++ linux-nvidia-7.0.0/security/apparmor/include/apparmor.h @@ -20,7 +20,7 @@ #define AA_CLASS_UNKNOWN 1 #define AA_CLASS_FILE 2 #define AA_CLASS_CAP 3 -#define AA_CLASS_DEPRECATED 4 +#define AA_CLASS_NET_COMPAT 4 #define AA_CLASS_RLIMITS 5 #define AA_CLASS_DOMAIN 6 #define AA_CLASS_MOUNT 7 @@ -36,6 +36,7 @@ #define AA_CLASS_NS 21 #define AA_CLASS_IO_URING 22 +#define AA_CLASS_NETV9_SKB 30 #define AA_CLASS_X 31 #define AA_CLASS_DBUS 32 --- linux-nvidia-7.0.0.orig/security/apparmor/include/apparmorfs.h +++ linux-nvidia-7.0.0/security/apparmor/include/apparmorfs.h @@ -11,10 +11,15 @@ #ifndef __AA_APPARMORFS_H #define __AA_APPARMORFS_H +#include +#include + extern struct path aa_null; enum aa_sfs_type { AA_SFS_TYPE_BOOLEAN, + // Boolean that gets printed as 0/1 for backwards compatibility + AA_SFS_TYPE_BOOLEAN_INTPRINT, AA_SFS_TYPE_STRING, AA_SFS_TYPE_U64, AA_SFS_TYPE_FOPS, @@ -43,6 +48,10 @@ { .name = (_name), .mode = 0444, \ .v_type = AA_SFS_TYPE_BOOLEAN, .v.boolean = (_value), \ .file_ops = &aa_sfs_seq_file_ops } +#define AA_SFS_FILE_BOOLEAN_INTPRINT(_name, _value) \ + { .name = (_name), .mode = 0444, \ + .v_type = AA_SFS_TYPE_BOOLEAN_INTPRINT, .v.boolean = (_value), \ + .file_ops = &aa_sfs_seq_file_ops } #define AA_SFS_FILE_STRING(_name, _value) \ { .name = (_name), .mode = 0444, \ .v_type = AA_SFS_TYPE_STRING, .v.string = (_value), \ @@ -89,6 +98,7 @@ AAFS_PROF_RAW_DATA, AAFS_PROF_RAW_HASH, AAFS_PROF_RAW_ABI, + AAFS_PROF_LEARNING_COUNT, AAFS_PROF_SIZEOF, }; --- linux-nvidia-7.0.0.orig/security/apparmor/include/audit.h +++ linux-nvidia-7.0.0/security/apparmor/include/audit.h @@ -19,6 +19,7 @@ #include "file.h" #include "label.h" +#include "notify.h" extern const char *const audit_mode_names[]; #define AUDIT_MAX_INDEX 5 @@ -38,6 +39,7 @@ AUDIT_APPARMOR_STATUS, AUDIT_APPARMOR_ERROR, AUDIT_APPARMOR_KILL, + AUDIT_APPARMOR_USER, AUDIT_APPARMOR_AUTO }; @@ -58,6 +60,7 @@ #define OP_CHMOD "chmod" #define OP_CHOWN "chown" #define OP_GETATTR "getattr" +#define OP_SETATTR "setattr" #define OP_OPEN "open" #define OP_FRECEIVE "file_receive" @@ -84,6 +87,11 @@ #define OP_GETSOCKOPT "getsockopt" #define OP_SETSOCKOPT "setsockopt" #define OP_SHUTDOWN "socket_shutdown" +#define OP_RELABEL_PACKET "relabel_packet" +#define OP_RCV_SKB "receive_packet" +#define OP_LOCALOUT "localout" +#define OP_CONN_REQ "conn_req" +#define OP_POSTROUTE "postroute" #define OP_PTRACE "ptrace" #define OP_SIGNAL "signal" @@ -108,7 +116,9 @@ #define OP_URING_OVERRIDE "uring_override" #define OP_URING_SQPOLL "uring_sqpoll" +#define AUDIT_TAILGLOB_NAME 1 struct apparmor_audit_data { + u32 flags; /* control flags not part of actual data */ int error; int type; u16 class; @@ -121,6 +131,8 @@ u32 denied; u32 tags; + struct task_struct *subjtsk; + union { /* these entries require a custom callback fn */ struct { @@ -147,6 +159,12 @@ int addrlen; } peer; } net; + struct { + const char *target; + } ns; + struct { + kuid_t ouid; + } mq; }; }; struct { @@ -169,6 +187,50 @@ struct common_audit_data common; }; +struct aa_audit_node { + struct kref count; + struct apparmor_audit_data data; + struct list_head list; + struct aa_knotif knotif; + union { + struct delayed_work work; + struct rcu_head rcu; + }; +}; +extern struct kmem_cache *aa_audit_slab; + +static inline struct aa_audit_node *aa_alloc_audit_node(gfp_t gfp) +{ + return kmem_cache_zalloc(aa_audit_slab, gfp); +} + + +struct aa_audit_cache { + spinlock_t lock; + int size; + struct list_head head; +}; + +static inline void aa_audit_cache_init(struct aa_audit_cache *cache) +{ + cache->size = 0; + spin_lock_init(&cache->lock); + INIT_LIST_HEAD(&cache->head); +} + +struct aa_audit_node *aa_audit_cache_find(struct aa_audit_cache *cache, + struct apparmor_audit_data *ad); +struct aa_audit_node *aa_audit_cache_insert(struct aa_audit_cache *cache, + struct aa_audit_node *node); +void aa_audit_cache_update_ent(struct aa_audit_cache *cache, + struct aa_audit_node *node, + struct apparmor_audit_data *data); +void aa_audit_cache_remove(struct aa_audit_cache *cache, + struct aa_audit_node *node); +void aa_audit_cache_destroy(struct aa_audit_cache *cache); + + + /* macros for dealing with apparmor_audit_data structure */ #define aad(SA) (container_of(SA, struct apparmor_audit_data, common)) #define aad_of_va(VA) aad((struct common_audit_data *)(VA)) @@ -178,6 +240,7 @@ struct apparmor_audit_data NAME = { \ .class = (C), \ .op = (X), \ + .subjtsk = NULL, \ .common.type = (T), \ .common.u.tsk = NULL, \ .common.apparmor_audit_data = &NAME, \ @@ -209,4 +272,27 @@ int aa_audit_rule_known(struct audit_krule *rule); int aa_audit_rule_match(struct lsm_prop *prop, u32 field, u32 op, void *vrule); + +void aa_audit_node_free_kref(struct kref *kref); +struct aa_audit_node *aa_dup_audit_data(struct apparmor_audit_data *orig, + gfp_t gfp); +long aa_audit_data_cmp(struct apparmor_audit_data *lhs, + struct apparmor_audit_data *rhs); + + +static inline struct aa_audit_node *aa_get_audit_node(struct aa_audit_node *node) +{ + if (node) + kref_get(&(node->count)); + + return node; +} + +static inline void aa_put_audit_node(struct aa_audit_node *node) +{ + if (node) + kref_put(&node->count, aa_audit_node_free_kref); +} + + #endif /* __AA_AUDIT_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/capability.h +++ linux-nvidia-7.0.0/security/apparmor/include/capability.h @@ -11,6 +11,7 @@ #ifndef __AA_CAPABILITY_H #define __AA_CAPABILITY_H +#include #include #include "apparmorfs.h" --- linux-nvidia-7.0.0.orig/security/apparmor/include/file.h +++ linux-nvidia-7.0.0/security/apparmor/include/file.h @@ -75,7 +75,7 @@ struct aa_profile *profile, struct aa_perms *perms, const char *op, u32 request, const char *name, const char *target, struct aa_label *tlabel, kuid_t ouid, - const char *info, int error); + const char *info, int error, bool prompt); struct aa_perms *aa_lookup_condperms(kuid_t subj_uid, struct aa_policydb *file_rules, @@ -87,10 +87,11 @@ int __aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_profile *profile, const char *name, u32 request, struct path_cond *cond, int flags, - struct aa_perms *perms); + struct aa_perms *perms, bool prompt); int aa_path_perm(const char *op, const struct cred *subj_cred, struct aa_label *label, const struct path *path, - int flags, u32 request, struct path_cond *cond); + int flags, u32 request, struct path_cond *cond, + u32 *allow); int aa_path_link(const struct cred *subj_cred, struct aa_label *label, struct dentry *old_dentry, const struct path *new_dir, --- linux-nvidia-7.0.0.orig/security/apparmor/include/inode.h +++ linux-nvidia-7.0.0/security/apparmor/include/inode.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AppArmor security module + * + * This file contains AppArmor file mediation function definitions. + * + * Copyright 2022 Canonical Ltd. + */ + +#ifndef __AA_INODE_H +#define __AA_INODE_H + +#include + +#include "lib.h" + +struct aa_inode_sec { + struct inode *inode; /* back pointer to inode object */ + struct aa_label *label; + u16 sclass; /* security class of this object */ + bool initialized; /* initialization flag */ + spinlock_t lock; +}; + +struct aa_superblock_sec { + struct aa_label *label; +}; + +static inline struct aa_inode_sec *apparmor_inode(const struct inode *inode) +{ + if (unlikely(!inode->i_security)) + return NULL; + return inode->i_security + apparmor_blob_sizes.lbs_inode; +} + +static inline struct aa_superblock_sec *apparmor_superblock( + const struct super_block *sb) +{ + return sb->s_security + apparmor_blob_sizes.lbs_superblock; +} + +#endif /* __AA_INODE_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/ipc.h +++ linux-nvidia-7.0.0/security/apparmor/include/ipc.h @@ -11,13 +11,71 @@ #ifndef __AA_IPC_H #define __AA_IPC_H +#include #include +#include "audit.h" +#include "inode.h" +#include "perms.h" #define SIGUNKNOWN 0 #define MAXMAPPED_SIG 35 +struct aa_msg_sec { + struct aa_label *label; +}; + +struct aa_ipc_sec { + struct aa_label *label; +}; + +static inline struct aa_ipc_sec *apparmor_ipc(const struct kern_ipc_perm *ipc) +{ + return ipc->security + apparmor_blob_sizes.lbs_ipc; +} + +static inline struct aa_msg_sec *apparmor_msg_msg(const struct msg_msg *msg_msg) +{ + return msg_msg->security + apparmor_blob_sizes.lbs_msg_msg; +} + + +static inline bool is_mqueue_sb(struct super_block *sb) +{ + if (!sb) + pr_warn("mqueue sb == NULL\n"); + if (!sb && !sb->s_type->name) + pr_warn("mqueue sb name == NULL\n"); + return sb && sb->s_type->name && strcmp(sb->s_type->name, "mqueue") == 0; +} + +static inline bool is_mqueue_inode(struct inode *i) +{ + struct aa_inode_sec *isec; + + if (!i) + return false; + + isec = apparmor_inode(i); + return isec && isec->sclass == AA_CLASS_POSIX_MQUEUE; +} + int aa_may_signal(const struct cred *subj_cred, struct aa_label *sender, const struct cred *target_cred, struct aa_label *target, int sig); +#define AA_AUDIT_POSIX_MQUEUE_MASK (AA_MAY_WRITE | AA_MAY_READ | \ + AA_MAY_CREATE | AA_MAY_DELETE | \ + AA_MAY_OPEN | AA_MAY_SETATTR | \ + AA_MAY_GETATTR) + + +int aa_profile_mqueue_perm(struct aa_profile *profile, + const struct path *path, + u32 request, char *buffer, + struct apparmor_audit_data *ad); + +int aa_mqueue_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + const struct path *path, u32 request); + #endif /* __AA_IPC_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/label.h +++ linux-nvidia-7.0.0/security/apparmor/include/label.h @@ -91,7 +91,7 @@ FLAG_PROFILE = 0x200, /* label is a profile */ FLAG_EXPLICIT = 0x400, /* explicit static label */ FLAG_STALE = 0x800, /* replaced/removed */ - FLAG_RENAMED = 0x1000, /* label has renaming in it */ + FLAG_INTERRUPTIBLE = 0x1000, FLAG_REVOKED = 0x2000, /* label has revocation in it */ FLAG_DEBUG1 = 0x4000, FLAG_DEBUG2 = 0x8000, @@ -258,6 +258,7 @@ return label_mediates(L, C); } +int aa_label_cmp(struct aa_label *a, struct aa_label *b); void aa_labelset_destroy(struct aa_labelset *ls); void aa_labelset_init(struct aa_labelset *ls); void __aa_labelset_update_subtree(struct aa_ns *ns); --- linux-nvidia-7.0.0.orig/security/apparmor/include/lib.h +++ linux-nvidia-7.0.0/security/apparmor/include/lib.h @@ -18,12 +18,17 @@ extern struct aa_dfa *stacksplitdfa; +#define list_add_entry(ent, list, member) list_add(&(ent)->member, (list)) +#define list_add_tail_entry(ent, list, member) list_add_tail(&(ent)->member, (list)) + /* * split individual debug cases out in preparation for finer grained * debug controls in the future. */ #define dbg_printk(__fmt, __args...) pr_debug(__fmt, ##__args) +#define DEBUG_PROMPT 2 + #define DEBUG_NONE 0 #define DEBUG_LABEL_ABS_ROOT 1 #define DEBUG_LABEL 2 @@ -32,8 +37,10 @@ #define DEBUG_INTERFACE 0x10 #define DEBUG_UNPACK 0x20 #define DEBUG_TAGS 0x40 +#define DEBUG_UPCALL 0x80 +#define DEBUG_SKB 0x100 -#define DEBUG_ALL 0x7f /* update if new DEBUG_X added */ +#define DEBUG_ALL 0x1ff /* update if new DEBUG_X added */ #define DEBUG_PARSE_ERROR (-1) #define DEBUG_ON (aa_g_debug != DEBUG_NONE) @@ -42,8 +49,9 @@ #define AA_DEBUG(opt, fmt, args...) \ do { \ if (aa_g_debug & opt) \ - pr_warn_ratelimited("%s: " fmt, __func__, ##args); \ + pr_warn("%s: " fmt, __func__, ##args); \ } while (0) +#define AA_DEBUG_ON(C, args...) do { if (C) AA_DEBUG(args); } while (0) #define AA_DEBUG_LABEL(LAB, X, fmt, args...) \ do { \ if ((LAB)->flags & FLAG_DEBUG1) \ @@ -143,6 +151,14 @@ return aa_dfa_next(dfa, start, 0); } +static inline aa_state_t aa_dfa_match_u16(struct aa_dfa *dfa, aa_state_t state, + u16 data) +{ + __be16 buffer = cpu_to_be16(data); + + return aa_dfa_match_len(dfa, state, (char *) &buffer, 2); +} + static inline bool path_mediated_fs(struct dentry *dentry) { return !(dentry->d_sb->s_flags & SB_NOUSER); @@ -281,15 +297,15 @@ * @FN: fn to call for each profile transition. @P is set to the profile * * Returns: new label on success + * NULL if all callbacks decline to specify a transition * ERR_PTR if build @FN fails - * NULL if label_build fails due to low memory conditions * - * @FN must return a label or ERR_PTR on failure. NULL is not allowed + * @FN must return a label or ERR_PTR on failure. */ #define fn_label_build(L, P, GFP, FN) \ ({ \ __label__ __do_cleanup, __done; \ - struct aa_label *__new_; \ + struct aa_label *__new_= NULL; \ \ if ((L)->size > 1) { \ /* TODO: add cache of transitions already done */ \ @@ -298,17 +314,21 @@ DEFINE_VEC(label, __lvec); \ DEFINE_VEC(profile, __pvec); \ if (vec_setup(label, __lvec, (L)->size, (GFP))) { \ - __new_ = NULL; \ + __new_ = ERR_PTR(-ENOMEM); \ goto __done; \ } \ __j = 0; \ label_for_each(__i, (L), (P)) { \ __new_ = (FN); \ - AA_BUG(!__new_); \ + if (!__new_) \ + continue; \ if (IS_ERR(__new_)) \ goto __do_cleanup; \ __lvec[__j++] = __new_; \ } \ + if (__j == 0) \ + /* no components adding to build */ \ + goto __do_cleanup; \ for (__j = __count = 0; __j < (L)->size; __j++) \ __count += __lvec[__j]->size; \ if (!vec_setup(profile, __pvec, __count, (GFP))) { \ @@ -320,14 +340,13 @@ if (__count > 1) { \ __new_ = aa_vec_find_or_create_label(__pvec,\ __count, (GFP)); \ - /* only fails if out of Mem */ \ if (!__new_) \ - __new_ = NULL; \ + __new_ = ERR_PTR(-ENOMEM); \ } else \ __new_ = aa_get_label(&__pvec[0]->label); \ vec_cleanup(profile, __pvec, __count); \ } else \ - __new_ = NULL; \ + __new_ = ERR_PTR(-ENOMEM); \ __do_cleanup: \ vec_cleanup(label, __lvec, (L)->size); \ } else { \ @@ -335,7 +354,7 @@ __new_ = (FN); \ } \ __done: \ - if (!__new_) \ + if (PTR_ERR(__new_)) \ AA_DEBUG(DEBUG_LABEL, "label build failed\n"); \ (__new_); \ }) @@ -357,4 +376,7 @@ __fn_build_in_scope(labels_ns(L), (P), (NS_FN), (OTHER_FN))); \ }) +#define fn_label_build_in_netns_scope(L, P, GFP, FN) \ + fn_label_build((L), (P), (GFP), (FN)) + #endif /* __AA_LIB_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/net.h +++ linux-nvidia-7.0.0/security/apparmor/include/net.h @@ -33,33 +33,43 @@ #define AA_MAY_SETOPT 0x01000000 #define AA_MAY_GETOPT 0x02000000 -#define NET_PERMS_MASK (AA_MAY_SEND | AA_MAY_RECEIVE | AA_MAY_CREATE | \ - AA_MAY_SHUTDOWN | AA_MAY_BIND | AA_MAY_LISTEN | \ - AA_MAY_CONNECT | AA_MAY_ACCEPT | AA_MAY_SETATTR | \ - AA_MAY_GETATTR | AA_MAY_SETOPT | AA_MAY_GETOPT) - -#define NET_FS_PERMS (AA_MAY_SEND | AA_MAY_RECEIVE | AA_MAY_CREATE | \ - AA_MAY_SHUTDOWN | AA_MAY_CONNECT | AA_MAY_RENAME |\ - AA_MAY_SETATTR | AA_MAY_GETATTR | AA_MAY_CHMOD | \ - AA_MAY_CHOWN | AA_MAY_CHGRP | AA_MAY_LOCK | \ +#define AA_SET_LABEL 0x80000000 + +#define NET_PERMS_MASK (AA_MAY_SEND | AA_MAY_RECEIVE | AA_MAY_CREATE | \ + AA_MAY_SHUTDOWN | AA_MAY_BIND | AA_MAY_LISTEN | \ + AA_MAY_CONNECT | AA_MAY_ACCEPT | AA_MAY_SETATTR | \ + AA_MAY_GETATTR | AA_MAY_SETCRED | AA_MAY_GETCRED | \ + AA_MAY_SETOPT | AA_MAY_GETOPT) + +#define NET_FS_PERMS (AA_MAY_SEND | AA_MAY_RECEIVE | AA_MAY_CREATE | \ + AA_MAY_SHUTDOWN | AA_MAY_CONNECT | AA_MAY_RENAME | \ + AA_MAY_SETATTR | AA_MAY_GETATTR | AA_MAY_SETCRED | \ + AA_MAY_GETCRED | AA_MAY_CHMOD | \ + AA_MAY_CHOWN | AA_MAY_CHGRP | AA_MAY_LOCK | \ AA_MAY_MPROT) #define NET_PEER_MASK (AA_MAY_SEND | AA_MAY_RECEIVE | AA_MAY_CONNECT | \ - AA_MAY_ACCEPT) + AA_MAY_ACCEPT | AA_SET_LABEL) struct aa_sk_ctx { struct aa_label __rcu *label; struct aa_label __rcu *peer; struct aa_label __rcu *peer_lastupdate; /* ptr cmp only, no deref */ }; +static inline bool aa_secmark(void) +{ + return apparmor_blob_sizes.lbs_secmark; +} + static inline struct aa_sk_ctx *aa_sock(const struct sock *sk) { return sk->sk_security + apparmor_blob_sizes.lbs_sock; } -#define DEFINE_AUDIT_NET(NAME, OP, CRED, SK, F, T, P) \ +#define DEFINE_AUDIT_NET_BASE(NAME, OP, CRED, SK, IFIDX, F, T, P) \ struct lsm_network_audit NAME ## _net = { .sk = (SK), \ - .family = (F)}; \ + .family = (F), \ + .netif = (IFIDX)}; \ DEFINE_AUDIT_DATA(NAME, \ ((SK) && (F) != AF_UNIX) ? LSM_AUDIT_DATA_NET : \ LSM_AUDIT_DATA_NONE, \ @@ -70,10 +80,35 @@ NAME.net.type = (T); \ NAME.net.protocol = (P) -#define DEFINE_AUDIT_SK(NAME, OP, CRED, SK) \ - DEFINE_AUDIT_NET(NAME, OP, CRED, SK, (SK)->sk_family, (SK)->sk_type, \ +#define DEFINE_AUDIT_NET(NAME, OP, CRED, SK, F, T, P) \ + DEFINE_AUDIT_NET_BASE(NAME, OP, CRED, SK, 0, F, T, P) + +#define DEFINE_AUDIT_SK(NAME, OP, CRED, SK) \ + DEFINE_AUDIT_NET(NAME, OP, CRED, SK, \ + (SK)->sk_family, (SK)->sk_type, \ (SK)->sk_protocol) +#define DEFINE_AUDIT_SKB(NAME, OP, CRED, SK, SKB) \ + DEFINE_AUDIT_NET_BASE(NAME, OP, CRED, SK, (SKB)->skb_iif, \ + (SK)->sk_family, (SK)->sk_type, \ + (SK)->sk_protocol) + + +static inline aa_state_t RULE_MEDIATES_SKB(struct aa_ruleset *rules) +{ + return RULE_MEDIATES(rules, AA_CLASS_NETV9_SKB); +} + +/* struct aa_net - network confinement data + * @allow: basic network families permissions + * @audit: which network permissions to force audit + * @quiet: which network permissions to quiet rejects + */ +struct aa_net_compat { + u16 allow[AF_MAX]; + u16 audit[AF_MAX]; + u16 quiet[AF_MAX]; +}; struct aa_secmark { u8 audit; @@ -83,7 +118,9 @@ }; extern struct aa_sfs_entry aa_sfs_entry_network[]; +extern struct aa_sfs_entry aa_sfs_entry_network_compat[]; extern struct aa_sfs_entry aa_sfs_entry_networkv9[]; +extern struct aa_sfs_entry aa_sfs_entry_networkv9_skb[]; int aa_do_perms(struct aa_profile *profile, struct aa_policydb *policy, aa_state_t state, u32 request, struct aa_perms *p, @@ -93,27 +130,26 @@ u32 request, u16 af, int type, int protocol, struct aa_perms **p, const char **info); void audit_net_cb(struct audit_buffer *ab, void *va); -int aa_profile_af_perm(struct aa_profile *profile, - struct apparmor_audit_data *ad, - u32 request, u16 family, int type, int protocol); +int aa_profile_af_compat_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, + u32 request, u16 family, int type); int aa_af_perm(const struct cred *subj_cred, struct aa_label *label, const char *op, u32 request, u16 family, int type, int protocol); static inline int aa_profile_af_sk_perm(struct aa_profile *profile, struct apparmor_audit_data *ad, - u32 request, - struct sock *sk) + u32 request, const struct sock *sk) { - return aa_profile_af_perm(profile, ad, request, sk->sk_family, - sk->sk_type, sk->sk_protocol); + return aa_profile_af_compat_perm(profile, ad, request, sk->sk_family, + sk->sk_type); } -int aa_sk_perm(const char *op, u32 request, struct sock *sk); +int aa_sk_perm(const char *op, u32 request, const struct sock *sk); int aa_sock_file_perm(const struct cred *subj_cred, struct aa_label *label, const char *op, u32 request, struct file *file); -int apparmor_secmark_check(struct aa_label *label, char *op, u32 request, +int apparmor_secmark_check(struct aa_label *label, const char *op, u32 request, u32 secid, const struct sock *sk); #endif /* __AA_NET_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/notify.h +++ linux-nvidia-7.0.0/security/apparmor/include/notify.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AppArmor security module + * + * This file contains AppArmor notifications function definitions. + * + * Copyright 2019 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ + +#ifndef __AA_NOTIFY_H +#define __AA_NOTIFY_H + +#include +#include +#include +#include +#include +#include + +#include + +#include "label.h" +#include "match.h" + +extern int aa_cache_timeout; + +struct aa_ns; +struct aa_audit_node; +struct apparmor_audit_data; + +struct aa_listener { + struct kref count; + spinlock_t lock; + wait_queue_head_t wait; + struct list_head ns_proxies; /* aa_listener_proxy */ + struct list_head notifications; /* aa_audit_proxy */ + struct list_head pending; /* aa_audit_proxy */ + struct aa_ns *ns; /* counted - ns of listener */ + struct aa_dfa *filter; + struct aa_label *label; + u64 listener_id; /* unique id of listener */ + u64 last_id; + u32 mask; + u32 flags; + u16 version; +}; + +struct aa_listener_proxy { + struct aa_ns *ns; /* counted - ns listening to */ + struct aa_listener *listener; + struct list_head llist; + struct list_head nslist; + struct delayed_work work; +}; + +#define KNOTIF_ON_LIST 1 +#define KNOTIF_PULSE +#define KNOTIF_PENDING +#define KNOTIF_CANCELLED +#define KNOTIF_RESEND 2 + +/* need to split knofif into audit_proxy + * prompt notifications only go to first taker so no need for completion + * in the proxy, it increases size of proxy in non-prompt case + */ +struct aa_knotif { + struct apparmor_audit_data *ad; /* counted */ + struct list_head list; + struct completion ready; + u64 id; + u16 ntype; + u16 flags; +}; + +void aa_free_listener_proxy(struct aa_listener_proxy *proxy); +struct aa_listener_proxy *aa_new_listener_proxy(struct aa_listener *listener, + struct aa_ns *ns); +void aa_delayed_free_listener_proxy(struct aa_listener_proxy *proxy); +struct aa_listener *aa_new_listener(struct aa_ns *ns, gfp_t gfp); +struct aa_knotif *__aa_find_notif(struct aa_listener *listener, u64 id); +int aa_do_notification(u16 ntype, struct aa_audit_node *node); + +long aa_listener_unotif_recv(struct aa_listener *listener, void __user *buf, + u16 max_size, u16 version); +long aa_listener_unotif_response(struct aa_listener *listener, + union apparmor_notif_resp *uresp, + u16 size); +long aa_register_listener_id(struct aa_listener *listener, u64 *id, + struct aa_listener **found); +long aa_listener_unotif_resend(struct aa_listener *listener, u32 *ready, + u32 *pending); + +void aa_listener_kref(struct kref *kref); +void aa_listener_fskref(struct kref *kref); + +static inline struct aa_listener *aa_get_listener(struct aa_listener *listener) +{ + if (listener) + kref_get(&(listener->count)); + + return listener; +} + +static inline void aa_put_listener(struct aa_listener *listener) +{ + if (listener) + kref_put(&listener->count, aa_listener_kref); +} + +#endif /* __AA_NOTIFY_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/path.h +++ linux-nvidia-7.0.0/security/apparmor/include/path.h @@ -11,12 +11,16 @@ #ifndef __AA_PATH_H #define __AA_PATH_H +#include +#include + enum path_flags { PATH_IS_DIR = 0x1, /* path is a directory */ PATH_SOCK_COND = 0x2, PATH_CONNECT_PATH = 0x4, /* connect disconnected paths to / */ PATH_CHROOT_REL = 0x8, /* do path lookup relative to chroot */ PATH_CHROOT_NSCONNECT = 0x10, /* connect paths that are at ns root */ + PATH_CONNECT_IPC_PATH = 0x20, /* connect IPC disconnected paths to / */ PATH_DELEGATE_DELETED = 0x10000, /* delegate deleted files */ PATH_MEDIATE_DELETED = 0x20000, /* mediate deleted paths */ @@ -25,6 +29,8 @@ int aa_path_name(const struct path *path, int flags, char *buffer, const char **name, const char **info, const char *disconnected); +int aa_disconnect(const struct path *path, char *buf, char **name, + int flags, int flags_match, const char *disconnected); #define IN_ATOMIC true char *aa_get_buffer(bool in_atomic); --- linux-nvidia-7.0.0.orig/security/apparmor/include/perms.h +++ linux-nvidia-7.0.0/security/apparmor/include/perms.h @@ -204,6 +204,9 @@ u32 mask); void aa_audit_perm_names(struct audit_buffer *ab, const char * const *names, u32 mask); +void aa_audit_perms(struct audit_buffer *ab, struct apparmor_audit_data *ad, + const char *chrs, u32 chrsmask, const char * const *names, + u32 namesmask); void aa_audit_perm_mask(struct audit_buffer *ab, u32 mask, const char *chrs, u32 chrsmask, const char * const *names, u32 namesmask); void aa_apply_modes_to_perms(struct aa_profile *profile, @@ -213,6 +216,11 @@ void aa_profile_match_label(struct aa_profile *profile, struct aa_ruleset *rules, struct aa_label *label, int type, u32 request, struct aa_perms *perms); +static inline u32 denied_perms(struct aa_perms *perms, u32 request) +{ + return request & (~perms->allow | perms->deny); +} + int aa_check_perms(struct aa_profile *profile, struct aa_perms *perms, u32 request, struct apparmor_audit_data *ad, void (*cb)(struct audit_buffer *, void *)); --- linux-nvidia-7.0.0.orig/security/apparmor/include/policy.h +++ linux-nvidia-7.0.0/security/apparmor/include/policy.h @@ -26,7 +26,6 @@ #include "file.h" #include "lib.h" #include "label.h" -#include "net.h" #include "perms.h" #include "resource.h" @@ -34,7 +33,12 @@ struct aa_ns; extern int unprivileged_userns_apparmor_policy; +extern int aa_unprivileged_userns_restricted; +extern int aa_unprivileged_userns_restricted_force; +extern int aa_unprivileged_userns_restricted_complain; extern int aa_unprivileged_unconfined_restricted; +extern int aa_unprivileged_uring_restricted; +extern int aa_skb_packet_mediation; extern const char *const aa_profile_mode_names[]; #define APPARMOR_MODE_NAMES_MAX_INDEX 4 @@ -202,6 +206,9 @@ struct aa_secmark *secmark; }; +void aa_free_ruleset(struct aa_ruleset *rules); +struct aa_ruleset *aa_new_ruleset(gfp_t gfp); +struct aa_ruleset *aa_clone_ruleset(struct aa_ruleset *rules); /* struct aa_attachment - data and rules for a profiles attachment * @list: @@ -232,6 +239,7 @@ * @disconnected: what to prepend if attach_disconnected is specified * @attach: attachment rules for the profile * @rules: rules to be enforced + * @net_compat: v2 compat network controls for the profile * * learning_cache: the accesses learned in complain mode * raw_data: rawdata of the loaded profile policy @@ -267,8 +275,12 @@ u32 path_flags; int signal; const char *disconnected; + const char *disconnected_ipc; struct aa_attachment attach; + struct aa_net_compat *net_compat; + + struct aa_audit_cache learning_cache; struct aa_loaddata *rawdata; unsigned char *hash; @@ -305,7 +317,8 @@ const char *fqname, size_t n); ssize_t aa_replace_profiles(struct aa_ns *view, struct aa_label *label, - u32 mask, struct aa_loaddata *udata); + u32 mask, struct aa_loaddata *udata, + char *compressed_profile, size_t compressed_size); ssize_t aa_remove_profiles(struct aa_ns *view, struct aa_label *label, char *name, size_t size); void __aa_profile_list_release(struct list_head *head); @@ -351,7 +364,23 @@ /* fallback and check v7/8 if v9 is NOT mediated */ if (!state) state = RULE_MEDIATES(rules, AA_CLASS_NET); + return state; +} + +static inline aa_state_t RULE_MEDIATES_UNIX(struct aa_ruleset *rules) +{ + /* can not use RULE_MEDIATE_v9AF here, because AF match fail + * can not be distiguished from class match fail, and we only + * fallback to checking older class on class match failure + */ + aa_state_t state = RULE_MEDIATES(rules, AA_CLASS_NETV9); + /* fallback and check v7/8 if v9 is NOT mediated */ + if (!state) { + state = RULE_MEDIATES(rules, AA_CLASS_NET); + if (!state) + state = RULE_MEDIATES(rules, AA_CLASS_NET_COMPAT); + } return state; } --- linux-nvidia-7.0.0.orig/security/apparmor/include/policy_ns.h +++ linux-nvidia-7.0.0/security/apparmor/include/policy_ns.h @@ -12,6 +12,7 @@ #define __AA_NAMESPACE_H #include +#include #include "apparmor.h" #include "apparmorfs.h" @@ -44,6 +45,12 @@ * @uniq_null: uniq value used for null learning profiles * @uniq_id: a unique id count for the profiles in the namespace * @level: level of ns within the tree hierarchy + * @revision: policy revision for this ns + * @wait: waitq for tasks waiting on revision changes + * @listener_lock: lock for listeners + * @listeners: notification listeners' proxies list + * @labels: all the labels associated with this ns + * @rawdata_list: raw policy data for policy * @dents: dentries for the namespaces file entries in apparmorfs * * An aa_ns defines the set profiles that are searched to determine which @@ -67,9 +74,13 @@ atomic_t uniq_null; long uniq_id; int level; + long revision; wait_queue_head_t wait; + spinlock_t listener_lock; + struct list_head listeners; + struct aa_labelset labels; struct list_head rawdata_list; @@ -77,6 +88,7 @@ }; extern struct aa_label *kernel_t; +extern struct aa_label *unlabeled_t; extern struct aa_ns *root_ns; extern const char *aa_hidden_ns_name; --- linux-nvidia-7.0.0.orig/security/apparmor/include/policy_unpack.h +++ linux-nvidia-7.0.0/security/apparmor/include/policy_unpack.h @@ -16,6 +16,7 @@ #include #include +#include "lib.h" struct aa_load_ent { struct list_head list; @@ -31,6 +32,7 @@ #define PACKED_FLAG_HAT 1 #define PACKED_FLAG_DEBUG1 2 #define PACKED_FLAG_DEBUG2 4 +#define PACKED_FLAG_INTERRUPTIBLE 8 #define PACKED_MODE_ENFORCE 0 #define PACKED_MODE_COMPLAIN 1 @@ -128,7 +130,8 @@ char *data; }; -int aa_unpack(struct aa_loaddata *udata, struct list_head *lh, const char **ns); +int aa_unpack(struct aa_loaddata *udata, struct list_head *lh, const char **ns, + char *compressed_data, size_t compressed_size); /** * aa_get_loaddata - get a reference count from a counted data reference --- linux-nvidia-7.0.0.orig/security/apparmor/include/procattr.h +++ linux-nvidia-7.0.0/security/apparmor/include/procattr.h @@ -11,6 +11,8 @@ #ifndef __AA_PROCATTR_H #define __AA_PROCATTR_H +#include "label.h" + int aa_getprocattr(struct aa_label *label, char **string, bool newline); int aa_setprocattr_changehat(char *args, size_t size, int flags); --- linux-nvidia-7.0.0.orig/security/apparmor/include/secid.h +++ linux-nvidia-7.0.0/security/apparmor/include/secid.h @@ -34,4 +34,14 @@ int aa_alloc_secid(struct aa_label *label, gfp_t gfp); void aa_free_secid(u32 secid); +static inline void aa_pin_secid(struct aa_label *label) +{ + /* currently a nop but could change */ +} + +static inline void aa_release_secid(int secid) +{ + /* currently a not, needs to change in sync with pin */ +} + #endif /* __AA_SECID_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/include/task.h +++ linux-nvidia-7.0.0/security/apparmor/include/task.h @@ -10,6 +10,11 @@ #ifndef __AA_TASK_H #define __AA_TASK_H +#include + +#include "audit.h" +#include "label.h" + static inline struct aa_task_ctx *task_ctx(struct task_struct *task) { return task->security + apparmor_blob_sizes.lbs_task; @@ -99,7 +104,8 @@ #define AA_USERNS_CREATE 8 -int aa_profile_ns_perm(struct aa_profile *profile, - struct apparmor_audit_data *ad, u32 request); +struct aa_label *aa_profile_ns_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, + u32 request); #endif /* __AA_TASK_H */ --- linux-nvidia-7.0.0.orig/security/apparmor/ipc.c +++ linux-nvidia-7.0.0/security/apparmor/ipc.c @@ -9,10 +9,13 @@ */ #include +#include +#include #include "include/audit.h" #include "include/capability.h" #include "include/cred.h" +#include "include/path.h" #include "include/policy.h" #include "include/ipc.h" #include "include/sig_names.h" @@ -114,3 +117,127 @@ profile_signal_perm(target_cred, profile, sender, MAY_READ, &ad)); } + + +static void audit_mqueue_cb(struct audit_buffer *ab, void *va) +{ + struct apparmor_audit_data *ad = aad_of_va(va); + + aa_audit_perms(ab, ad, NULL, 0, NULL, AA_AUDIT_POSIX_MQUEUE_MASK); + + /* move class into generic audit framse work */ + audit_log_format(ab, " class=\"posix_mqueue\""); + if (ad->request & AA_AUDIT_FILE_MASK) { + audit_log_format(ab, " fsuid=%u", + from_kuid(&init_user_ns, ad->subj_cred->fsuid)); + audit_log_format(ab, " ouid=%u", + from_kuid(&init_user_ns, ad->mq.ouid)); + } + if (ad->peer) { + audit_log_format(ab, " olabel="); + aa_label_xaudit(ab, labels_ns(ad->subj_label), ad->peer, + FLAGS_NONE, GFP_ATOMIC); + } +} + +int aa_profile_mqueue_perm(struct aa_profile *profile, const struct path *path, + u32 request, char *buffer, + struct apparmor_audit_data *ad) +{ + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_perms perms = { }; + unsigned int state; + char *name; + struct aa_inode_sec *isec; + + if (profile_unconfined(profile) || + !RULE_MEDIATES(rules, AA_CLASS_POSIX_MQUEUE)) + return 0; + + ad->subj_label = &profile->label; + + name = dentry_path_raw(path->dentry, buffer, aa_g_path_max); + if (IS_ERR(name)) + return PTR_ERR(name); + + if (path->mnt != current->nsproxy->ipc_ns->mq_mnt) { + /* check if enforced by userspace? */ + if (aa_disconnect(path, buffer, &name, profile->path_flags, + PATH_CONNECT_PATH | PATH_CONNECT_IPC_PATH, + profile->disconnected_ipc)) { + ad->info = "Failed name lookup - disconnected IPC path"; + return aa_check_perms(profile, &perms, request, + ad, audit_mqueue_cb); + } + } + + ad->name = name; + + state = aa_dfa_match(rules->policy->dfa, + rules->policy->start[AA_CLASS_POSIX_MQUEUE], + name); + perms = *aa_lookup_perms(rules->policy, state); + aa_apply_modes_to_perms(profile, &perms); + if (!denied_perms(&perms, request)) { + /* early bailout sufficient perms no need to do further + * checks + */ + return aa_check_perms(profile, &perms, request, ad, + audit_mqueue_cb); + } + /* continue check to see if we have label perms */ + if (!(request & AA_MAY_CREATE)) { + if (!d_backing_inode(path->dentry)) { + pr_warn("apparmor: could not get inode\n"); + goto err; + } + isec = apparmor_inode(d_backing_inode(path->dentry)); + if (!isec) { + pr_warn("apparmor: could not get inode sec context\n"); + goto err; + } + ad->peer = isec->label; + state = aa_dfa_null_transition(rules->policy->dfa, state); + aa_label_match(profile, rules, isec->label, state, false, request, &perms); + aa_apply_modes_to_perms(profile, &perms); + } +err: + return aa_check_perms(profile, &perms, request, ad, audit_mqueue_cb); +} + +/* mqueue - no label caching test */ +int aa_mqueue_perm(const char *op, const struct cred *subj_cred, + struct aa_label *label, + const struct path *path, u32 request) +{ + struct aa_profile *profile; + char *buffer; + int error; + DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_NONE, AA_CLASS_POSIX_MQUEUE, op); + + // do we need delegate deleted with mqueues? probably + //flags |= PATH_DELEGATE_DELETED; + + /* sadly due to rcu walk hairiness, we use dentry_path_raw instead + * of just accessing the name directly, which means we need to + * do the whole buffer allocation mess + */ + buffer = aa_get_buffer(false); + if (!buffer) + return -ENOMEM; + + /* audit fields that won't change during iteration */ + ad.subj_cred = subj_cred; + ad.request = request; + ad.peer = NULL; + ad.mq.ouid = d_backing_inode(path->dentry) ? + d_backing_inode(path->dentry)->i_uid : + subj_cred->fsuid; + + error = fn_for_each_confined(label, profile, + aa_profile_mqueue_perm(profile, path, request, + buffer, &ad)); + aa_put_buffer(buffer); + + return error; +} --- linux-nvidia-7.0.0.orig/security/apparmor/label.c +++ linux-nvidia-7.0.0/security/apparmor/label.c @@ -83,7 +83,7 @@ tmp = rcu_dereference_protected(orig->proxy->label, &labels_ns(orig)->lock); rcu_assign_pointer(orig->proxy->label, aa_get_label(new)); - orig->flags |= FLAG_STALE; + __label_make_stale(orig); aa_put_label(tmp); } @@ -465,7 +465,7 @@ /** - * label_cmp - label comparison for set ordering + * aa_label_cmp - label comparison for set ordering * @a: label to compare (NOT NULL) * @b: label to compare (NOT NULL) * @@ -473,7 +473,7 @@ * ==0 if a == b * >0 if a > b */ -static int label_cmp(struct aa_label *a, struct aa_label *b) +int aa_label_cmp(struct aa_label *a, struct aa_label *b) { AA_BUG(!b); @@ -688,7 +688,7 @@ new = &ls->root.rb_node; while (*new) { struct aa_label *this = rb_entry(*new, struct aa_label, node); - int result = label_cmp(label, this); + int result = aa_label_cmp(label, this); parent = *new; if (result == 0) { --- linux-nvidia-7.0.0.orig/security/apparmor/lib.c +++ linux-nvidia-7.0.0/security/apparmor/lib.c @@ -46,6 +46,8 @@ { "interface", DEBUG_INTERFACE }, { "unpack", DEBUG_UNPACK }, { "tags", DEBUG_TAGS }, + { "upcall", DEBUG_UPCALL }, + { "skb", DEBUG_SKB }, { NULL, 0 } }; @@ -250,7 +252,7 @@ const char aa_file_perm_chrs[] = "xwracd km l "; -const char *aa_file_perm_names[] = { +static const char * const aa_base_perm_names[] = { "exec", "write", "read", @@ -340,6 +342,10 @@ { char str[33]; + if (!chrs) + chrs = aa_file_perm_chrs; + if (!names) + names = aa_base_perm_names; audit_log_format(ab, "\""); if ((mask & chrsmask) && chrs) { aa_perm_mask_to_str(str, sizeof(str), chrs, mask & chrsmask); @@ -353,6 +359,22 @@ audit_log_format(ab, "\""); } +void aa_audit_perms(struct audit_buffer *ab, struct apparmor_audit_data *ad, + const char *chrs, u32 chrsmask, const char * const *names, + u32 namesmask) +{ + if (ad->request) { + audit_log_format(ab, " requested="); + aa_audit_perm_mask(ab, ad->request, chrs, chrsmask, + names, namesmask); + } + if (ad->denied) { + audit_log_format(ab, " denied="); + aa_audit_perm_mask(ab, ad->denied, chrs, chrsmask, + names, namesmask); + } +} + /** * aa_apply_modes_to_perms - apply namespace and profile flags to perms * @profile: that perms where computed from @@ -422,7 +444,7 @@ void (*cb)(struct audit_buffer *, void *)) { int type, error; - u32 denied = request & (~perms->allow | perms->deny); + u32 denied = denied_perms(perms, request); if (likely(!denied)) { /* mask off perms that are not being force audited */ @@ -451,6 +473,7 @@ } if (ad) { + // do_notification() ad->subj_label = &profile->label; ad->request = request; ad->denied = denied; --- linux-nvidia-7.0.0.orig/security/apparmor/lsm.c +++ linux-nvidia-7.0.0/security/apparmor/lsm.c @@ -17,7 +17,10 @@ #include #include #include +#include #include +#include +#include #include #include #include @@ -27,6 +30,7 @@ #include #include "include/af_unix.h" +#include "include/af_inet.h" #include "include/apparmor.h" #include "include/apparmorfs.h" #include "include/audit.h" @@ -34,6 +38,7 @@ #include "include/cred.h" #include "include/crypto.h" #include "include/file.h" +#include "include/inode.h" #include "include/ipc.h" #include "include/net.h" #include "include/path.h" @@ -66,6 +71,13 @@ static DEFINE_SPINLOCK(aa_buffers_lock); static DEFINE_PER_CPU(struct aa_local_cache, aa_local_buffers); +struct kmem_cache *aa_audit_slab; + +static bool is_mqueue_dentry(struct dentry *dentry) +{ + return dentry && is_mqueue_inode(d_backing_inode(dentry)); +} + /* * LSM hook functions */ @@ -226,7 +238,7 @@ label = __begin_current_label_crit_section(&needput); if (!unconfined(label)) error = aa_path_perm(op, current_cred(), label, path, 0, mask, - cond); + cond, NULL); __end_current_label_crit_section(label, needput); return error; @@ -416,12 +428,12 @@ label, &new_path, 0, MAY_READ | AA_MAY_GETATTR | MAY_WRITE | AA_MAY_SETATTR | AA_MAY_DELETE, - &cond_exchange); + &cond_exchange, NULL); if (!error) error = aa_path_perm(OP_RENAME_DEST, current_cred(), label, &old_path, 0, MAY_WRITE | AA_MAY_SETATTR | - AA_MAY_CREATE, &cond_exchange); + AA_MAY_CREATE, &cond_exchange, NULL); } if (!error) @@ -429,12 +441,12 @@ label, &old_path, 0, MAY_READ | AA_MAY_GETATTR | MAY_WRITE | AA_MAY_SETATTR | AA_MAY_DELETE, - &cond); + &cond, NULL); if (!error) error = aa_path_perm(OP_RENAME_DEST, current_cred(), label, &new_path, 0, MAY_WRITE | AA_MAY_SETATTR | - AA_MAY_CREATE, &cond); + AA_MAY_CREATE, &cond, NULL); } end_current_label_crit_section(label); @@ -452,11 +464,162 @@ return common_perm_cond(OP_CHOWN, path, AA_MAY_CHOWN); } +static int common_mqueue_path_perm(const char *op, u32 request, + const struct path *path) +{ + struct aa_label *label; + int error = 0; + + label = begin_current_label_crit_section(); + if (!unconfined(label)) + error = aa_mqueue_perm(op, current_cred(), label, path, + request); + + end_current_label_crit_section(label); + + return error; +} + static int apparmor_inode_getattr(const struct path *path) { + if (is_mqueue_dentry(path->dentry)) + /* TODO: fn() for d_parent */ + return common_mqueue_path_perm(OP_GETATTR, AA_MAY_GETATTR, path); + return common_perm_cond(OP_GETATTR, path, AA_MAY_GETATTR); } +/* inode security operations */ + +/* alloced by infrastructure */ +static int apparmor_inode_alloc_security(struct inode *inode) +{ + struct aa_inode_sec *isec = apparmor_inode(inode); + + spin_lock_init(&isec->lock); + isec->inode = inode; + isec->label = NULL; + isec->sclass = 0; + isec->initialized = false; + + return 0; +} + +/* freed by infrastructure */ +static void apparmor_inode_free_security(struct inode *inode) +{ + struct aa_inode_sec *isec = apparmor_inode(inode); + + if (unlikely(!isec)) + return; + + aa_put_label(isec->label); +} + +static int inode_init_with_dentry(struct inode *inode, struct dentry *dentry) +{ + struct aa_inode_sec *isec = apparmor_inode(inode); + + if (isec->initialized) + return 0; + spin_lock(&isec->lock); + /* recheck under lock */ + if (isec->initialized) + goto unlock; + + if (is_mqueue_sb(inode->i_sb)) { + /* only initialize based on implied label atm */ + isec->label = aa_get_current_label(); + isec->sclass = AA_CLASS_POSIX_MQUEUE; + isec->initialized = true; + } + +unlock: + spin_unlock(&isec->lock); + + return 0; +} + +static int apparmor_inode_init_security(struct inode *inode, struct inode *dir, + const struct qstr *qstr, + struct xattr *xattrs, int *xattr_count) +{ + int error; + + error = inode_init_with_dentry(inode, NULL); + if (error) + return error; + + /* we aren't setting xattrs yet so -EOPNOTSUPP indicates + * that, not an error + */ + return -EOPNOTSUPP; +} + +static void apparmor_d_instantiate(struct dentry *dentry, struct inode *inode) +{ + if (inode) + inode_init_with_dentry(inode, dentry); +} + +static int apparmor_inode_create(struct inode *dir, struct dentry *dentry, + umode_t mode) +{ + struct aa_label *label; + int error = 0; + + label = begin_current_label_crit_section(); + if (!unconfined(label)) { + struct path path = { + .dentry = dentry, + .mnt = current->nsproxy->ipc_ns->mq_mnt, + }; + if (is_mqueue_inode(dir)) + error = aa_mqueue_perm(OP_CREATE, current_cred(), + label, &path, AA_MAY_CREATE); + } + end_current_label_crit_section(label); + + return error; +} + +static int common_mqueue_perm(const char *op, u32 request, struct inode *dir, struct dentry *dentry) +{ + /* can't directly determine ipc ns, but know for mqueues dir is mnt_root */ + bool isdir = d_inode(current->nsproxy->ipc_ns->mq_mnt->mnt_root) == dir; + struct path path = { + .dentry = dentry, + .mnt = isdir ? current->nsproxy->ipc_ns->mq_mnt : NULL, + }; + + if (dir != d_inode(current->nsproxy->ipc_ns->mq_mnt->mnt_root)) + pr_warn("apparmor: unlink dir != mnt_root - disconnected"); + + return common_mqueue_path_perm(op, request, &path); +} + +static int apparmor_inode_unlink(struct inode *dir, struct dentry *dentry) +{ + int error = 0; + + if (is_mqueue_dentry(dentry)) + error = common_mqueue_perm(OP_UNLINK, AA_MAY_DELETE, dir, dentry); + + return error; +} + +static int apparmor_inode_setattr(struct mnt_idmap *idmap, + struct dentry *dentry, struct iattr *iattr) +{ + /* TODO: extend to support iattr as a parameter */ + if (is_mqueue_dentry(dentry)) + /* TODO: fn() for d_parent */ + return common_mqueue_perm(OP_SETATTR, AA_MAY_SETATTR, + d_backing_inode(dentry->d_parent), dentry); + + return 0; +} + static int apparmor_file_open(struct file *file) { struct aa_file_ctx *fctx = file_ctx(file); @@ -484,17 +647,28 @@ struct mnt_idmap *idmap = file_mnt_idmap(file); struct inode *inode = file_inode(file); vfsuid_t vfsuid; + u32 allow; struct path_cond cond = { .mode = inode->i_mode, }; vfsuid = i_uid_into_vfsuid(idmap, inode); cond.uid = vfsuid_into_kuid(vfsuid); - error = aa_path_perm(OP_OPEN, file->f_cred, - label, &file->f_path, 0, - aa_map_file_to_perms(file), &cond); - /* todo cache full allowed permissions set and state */ - fctx->allow = aa_map_file_to_perms(file); + if (is_mqueue_inode(file_inode(file))) { + error = aa_mqueue_perm(OP_OPEN, file->f_cred, + label, &file->f_path, + aa_map_file_to_perms(file)); + allow = aa_map_file_to_perms(file); + } else { + /* will be intersected and reduced with each profile */ + allow = ALL_PERMS_MASK; + error = aa_path_perm(OP_OPEN, file->f_cred, + label, &file->f_path, 0, + aa_map_file_to_perms(file), &cond, + &allow); + } + if (!error) + fctx->allow = allow; } aa_put_label_condref(label, needput); @@ -506,6 +680,7 @@ struct aa_file_ctx *ctx = file_ctx(file); struct aa_label *label = begin_current_label_crit_section(); + /* no inode available here */ spin_lock_init(&ctx->lock); rcu_assign_pointer(ctx->label, aa_get_label(label)); end_current_label_crit_section(label); @@ -623,13 +798,40 @@ { unsigned int state; struct aa_ruleset *rules; - int error = 0; AA_BUG(!profile); rules = profile->label.rules[0]; + /* TODO: rework unconfined profile/dfa to mediate user ns, then + * we can drop the unconfined test + */ state = RULE_MEDIATES(rules, AA_CLASS_IO_URING); - if (state) { + if (!state) { + /* TODO: this gets replaced when the default unconfined + * profile dfa gets updated to handle this + */ + if (profile_unconfined(profile) && + profile == profiles_ns(profile)->unconfined) { + if (!aa_unprivileged_uring_restricted || + ns_capable_noaudit(current_user_ns(), cap)) + /* unconfined early bail out */ + return 0; + /* unconfined unprivileged user */ + /* don't just return: allow complain mode to override */ + } else { + /* Fallback to capability check if profile doesn't + * support io_uring rules. Note: special unconfined + * profiles as well. + */ + return aa_capable(current_cred(), &profile->label, + cap, CAP_OPT_NONE); + } + /* continue to mediation - !state means non-accepting + * but can be overidden by complain + */ + } + /* block so perms is not initialized unless mediating */ + do { struct aa_perms perms = { }; if (new) { @@ -639,11 +841,11 @@ perms = *aa_lookup_perms(rules->policy, state); } aa_apply_modes_to_perms(profile, &perms); - error = aa_check_perms(profile, &perms, request, ad, + return aa_check_perms(profile, &perms, request, ad, audit_uring_cb); - } + } while (0); - return error; + return 0; } /** @@ -822,25 +1024,23 @@ char **value) { int error = -ENOENT; - /* released below */ - const struct cred *cred = get_task_cred(task); - struct aa_task_ctx *ctx = task_ctx(current); struct aa_label *label = NULL; + rcu_read_lock(); if (strcmp(name, "current") == 0) - label = aa_get_newest_label(cred_label(cred)); - else if (strcmp(name, "prev") == 0 && ctx->previous) - label = aa_get_newest_label(ctx->previous); - else if (strcmp(name, "exec") == 0 && ctx->onexec) - label = aa_get_newest_label(ctx->onexec); + label = aa_get_newest_cred_label(__task_cred(task)); + else if (strcmp(name, "prev") == 0 && task_ctx(task)->previous) + label = aa_get_newest_label(task_ctx(task)->previous); + else if (strcmp(name, "exec") == 0 && task_ctx(task)->onexec) + label = aa_get_newest_label(task_ctx(task)->onexec); else error = -EINVAL; + rcu_read_unlock(); if (label) error = aa_getprocattr(label, value, true); aa_put_label(label); - put_cred(cred); return error; } @@ -858,12 +1058,9 @@ /* AppArmor requires that the buffer must be null terminated atm */ if (args[size - 1] != '\0') { - /* null terminate */ - largs = args = kmalloc(size + 1, GFP_KERNEL); + largs = args = kmemdup_nul(value, size, GFP_KERNEL); if (!args) return -ENOMEM; - memcpy(args, value, size); - args[size] = '\0'; } error = -EINVAL; @@ -1045,21 +1242,32 @@ return error; } -static int apparmor_userns_create(const struct cred *cred) +static int apparmor_userns_create(const struct cred *new_cred) { struct aa_label *label; struct aa_profile *profile; int error = 0; - DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_TASK, AA_CLASS_NS, - OP_USERNS_CREATE); - - ad.subj_cred = current_cred(); label = begin_current_label_crit_section(); - if (!unconfined(label)) { - error = fn_for_each(label, profile, - aa_profile_ns_perm(profile, &ad, - AA_USERNS_CREATE)); + /* remove unprivileged_userns_restricted check when unconfined is updated */ + if (aa_unprivileged_userns_restricted || + label_mediates(label, AA_CLASS_NS)) { + struct aa_label *new; + DEFINE_AUDIT_DATA(ad, LSM_AUDIT_DATA_TASK, AA_CLASS_NS, + OP_USERNS_CREATE); + ad.subj_cred = current_cred(); + + new = fn_label_build(label, profile, GFP_KERNEL, + aa_profile_ns_perm(profile, &ad, + AA_USERNS_CREATE)); + if (IS_ERR(new)) { + error = PTR_ERR(new); + } else if (new && cred_label(new_cred) != new) { + aa_put_label(cred_label(new_cred)); + set_cred_label(new_cred, new); + } else { + aa_put_label(new); + } } end_current_label_crit_section(label); @@ -1263,13 +1471,21 @@ label = begin_current_label_crit_section(); if (!unconfined(label)) { - if (family == PF_UNIX) + switch (family) { + case PF_UNIX: error = aa_unix_create_perm(label, family, type, protocol); - else + break; + case PF_INET: + case PF_INET6: + error = aa_inet_create_perm(label, family, type, + protocol); + break; + default: error = aa_af_perm(current_cred(), label, OP_CREATE, AA_MAY_CREATE, family, type, protocol); + } } end_current_label_crit_section(label); @@ -1363,8 +1579,13 @@ AA_BUG(!address); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_bind_perm(sock, address, addrlen); + case PF_INET: + case PF_INET6: + return aa_inet_bind_perm(sock, address, addrlen); + } return aa_sk_perm(OP_BIND, AA_MAY_BIND, sock->sk); } @@ -1377,8 +1598,13 @@ AA_BUG(in_interrupt()); /* PF_UNIX goes through unix_stream_connect && unix_may_send */ - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return 0; + case PF_INET: + case PF_INET6: + return aa_inet_connect_perm(sock, address, addrlen); + } return aa_sk_perm(OP_CONNECT, AA_MAY_CONNECT, sock->sk); } @@ -1388,8 +1614,13 @@ AA_BUG(!sock->sk); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_listen_perm(sock, backlog); + case PF_INET: + case PF_INET6: + return aa_inet_listen_perm(sock, backlog); + } return aa_sk_perm(OP_LISTEN, AA_MAY_LISTEN, sock->sk); } @@ -1404,8 +1635,13 @@ AA_BUG(!newsock); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_accept_perm(sock, newsock); + case PF_INET: + case PF_INET6: + return aa_inet_accept_perm(sock, newsock); + } return aa_sk_perm(OP_ACCEPT, AA_MAY_ACCEPT, sock->sk); } @@ -1418,8 +1654,14 @@ AA_BUG(in_interrupt()); /* PF_UNIX goes through unix_may_send */ - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return 0; + case PF_INET: + case PF_INET6: + return aa_inet_msg_perm(op, request, sock, msg, size); + } + return aa_sk_perm(op, request, sock->sk); } @@ -1442,8 +1684,13 @@ AA_BUG(!sock->sk); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_sock_perm(op, request, sock); + case PF_INET: + case PF_INET6: + return aa_inet_sock_perm(op, request, sock); + } return aa_sk_perm(op, request, sock->sk); } @@ -1465,8 +1712,13 @@ AA_BUG(!sock->sk); AA_BUG(in_interrupt()); - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_opt_perm(op, request, sock, level, optname); + case PF_INET: + case PF_INET6: + return aa_inet_opt_perm(op, request, sock, level, optname); + } return aa_sk_perm(op, request, sock->sk); } @@ -1489,54 +1741,14 @@ return aa_sock_perm(OP_SHUTDOWN, AA_MAY_SHUTDOWN, sock); } -#ifdef CONFIG_NETWORK_SECMARK -/** - * apparmor_socket_sock_rcv_skb - check perms before associating skb to sk - * @sk: sk to associate @skb with - * @skb: skb to check for perms - * - * Note: can not sleep may be called with locks held - * - * dont want protocol specific in __skb_recv_datagram() - * to deny an incoming connection socket_sock_rcv_skb() - */ -static int apparmor_socket_sock_rcv_skb(struct sock *sk, struct sk_buff *skb) -{ - struct aa_sk_ctx *ctx = aa_sock(sk); - int error; - - if (!skb->secmark) - return 0; - - /* - * If reach here before socket_post_create hook is called, in which - * case label is null, drop the packet. - */ - if (!rcu_access_pointer(ctx->label)) - return -EACCES; - - rcu_read_lock(); - error = apparmor_secmark_check(rcu_dereference(ctx->label), OP_RECVMSG, - AA_MAY_RECEIVE, skb->secmark, sk); - rcu_read_unlock(); - - return error; -} -#endif - - static struct aa_label *sk_peer_get_label(struct sock *sk) { struct aa_sk_ctx *ctx = aa_sock(sk); - struct aa_label *label = ERR_PTR(-ENOPROTOOPT); if (rcu_access_pointer(ctx->peer)) return aa_get_label_rcu(&ctx->peer); - if (sk->sk_family != PF_UNIX) - return ERR_PTR(-ENOPROTOOPT); - - return label; + return ERR_PTR(-ENOPROTOOPT); } /** @@ -1628,23 +1840,287 @@ } #ifdef CONFIG_NETWORK_SECMARK -static int apparmor_inet_conn_request(const struct sock *sk, struct sk_buff *skb, + +/* secmark reference count */ +static atomic_t apparmor_secmark_refcount = ATOMIC_INIT(0); + + +/* count of rules using secmark that have been loaded into netfilter + * would be nice if it was per packet, or least per secid so we know which ids + * to pin + */ +static void apparmor_secmark_refcount_inc(void) +{ + atomic_inc(&apparmor_secmark_refcount); +} + +/* rule using secmark has been removed from netfilter */ +static void apparmor_secmark_refcount_dec(void) +{ + atomic_dec(&apparmor_secmark_refcount); +} + +static inline bool aa_secmark_enabled(void) +{ + return (aa_secmark() && aa_skb_packet_mediation); +} + +static inline bool aa_mediates_secmark(struct aa_label *label) +{ + return aa_secmark_enabled() && + (label_mediates(label, AA_CLASS_NETV9_SKB) || + atomic_read(&apparmor_secmark_refcount)); +} + +/* check if current process can use secmark to set a label on the packet + * only done in mangle or security tables + * @sid is the label that is going to be set + */ +static int apparmor_secmark_relabel_packet(u32 sid) +{ + if (!aa_secmark_enabled()) + return 0; + + return aa_secmark_relabel_packet(sid); +} + +#endif /* CONFIG_NETWROK_SECMARK */ + + + +/** + * apparmor_socket_sock_rcv_skb - check perms before associating skb to sk + * @sk: sk to associate @skb with + * @skb: skb to check for perms + * + * Note: can not sleep may be called with locks held + * + * dont want protocol specific in __skb_recv_datagram() + * to deny an incoming connection socket_sock_rcv_skb() + */ +static int apparmor_socket_sock_rcv_skb(struct sock *sk, struct sk_buff *skb) +{ + struct aa_sk_ctx *ctx = aa_sock(sk); + struct aa_label *label; + int error = 0; + + if (!aa_secmark_enabled()) + return 0; + if (sk->sk_family != PF_INET && sk->sk_family != PF_INET6) + return 0; + + /* + * If reach here before socket_post_create hook is called, in which + * case label is null, drop the packet. + */ + if (!rcu_access_pointer(ctx->label)) + return -EACCES; + + rcu_read_lock(); + label = rcu_dereference(ctx->label); + if (label_mediates(label, AA_CLASS_NETV9_SKB) || skb->secmark) + /* receive uses socket label as proxy + * may do interface processing without SECMARK + */ + error = __aa_sock_rcv_skb(label, sk, skb); + /* else none of the profiles in label mediate skbs && + * the skb is unlabeled + */ + rcu_read_unlock(); + + return error; +} + +/* Accept an incoming connection request + */ +static int apparmor_inet_conn_request(const struct sock *sk, + struct sk_buff *skb, struct request_sock *req) { struct aa_sk_ctx *ctx = aa_sock(sk); - int error; + struct aa_label *label; + int error = 0; - if (!skb->secmark) + if (!aa_secmark_enabled()) return 0; rcu_read_lock(); - error = apparmor_secmark_check(rcu_dereference(ctx->label), OP_CONNECT, - AA_MAY_CONNECT, skb->secmark, sk); + label = rcu_dereference(ctx->label); + if (label_mediates(label, AA_CLASS_NETV9_SKB) || skb->secmark) + /* receive uses socket label as proxy + * may do interface processing without SECMARK + */ + error = __aa_inet_conn_request(label, sk, skb, req); + /* else none of the profiles in label mediate skbs && + * the skb is unlabeled + */ rcu_read_unlock(); return error; } -#endif + + +#ifdef CONFIG_NETFILTER + +static unsigned int apparmor_ip_postroute(void *priv, + struct sk_buff *skb, + const struct nf_hook_state *state) +{ + struct aa_sk_ctx *ctx; + struct aa_label *label; + struct sock *sk; + int error = 0; + + /* we need the secmark for postroute mediation */ + if (!aa_secmark_enabled() || !skb->secmark) + return NF_ACCEPT; + + sk = skb_to_full_sk(skb); + if (sk == NULL) { + if (skb->skb_iif) + /* Forwarded packet, not handled atm */ + return NF_ACCEPT; + /* kernel sending a packet - no need to look at secmark */ + label = kernel_t; + } else if (sk_listener(sk)) { + /* locally generated SYN_ACK - regenerate below using ctx */ + } else { + /* locally generated packet - look at skb and ctx below*/ + } + + ctx = aa_sock(sk); + rcu_read_lock(); + if (!label) + label = aa_secid_to_label(skb->secmark); /* may be NULL */ + if (!label) + label = rcu_dereference(ctx->label); + if (label && label_mediates(label, AA_CLASS_NETV9_SKB)) + error = __aa_ip_postroute(label, sk, skb, state); + rcu_read_unlock(); + + if (error) + return NF_DROP_ERR(-ECONNREFUSED); + + return NF_ACCEPT; +} + + +static unsigned int apparmor_ip_localout(void *priv, struct sk_buff *skb, + const struct nf_hook_state *state) +{ + struct aa_label *label, *out; + bool needput; + + if (!aa_secmark_enabled()) + return NF_ACCEPT; + + label = __begin_current_label_crit_section(&needput); + if (!label_mediates(label, AA_CLASS_NETV9_SKB)) { + /* apparmor isn't going to do iface or packet based + * filtering so bail. + */ + AA_DEBUG_LABEL(label, DEBUG_SKB, "label does not mediate skb"); + end_current_label_crit_section(label); + return NF_ACCEPT; + } + + struct sock *sk = skb_to_full_sk(skb); + + if (sk) { + if (sk_listener(sk)) { + /* socket is in listening state, packet is a SYN-ACK + * If using socket as proxy would need conn/request + * socket, but only have parent. + * However unless socket perms are delegated not + * labeling based on socket but sending task + */ + if (aa_g_debug & DEBUG_SKB) { + rcu_read_lock(); + struct aa_label *sklabel = aa_get_label(aa_sock(sk)->label); + + rcu_read_unlock(); + aa_put_label(sklabel); + + } + AA_DEBUG_LABEL(label, DEBUG_SKB, "sk_listener"); + return NF_ACCEPT; + } + /* TODO: support delegation via socket label instead of + * task + */ + out = __aa_ip_localout(label, sk, skb); + } else { + out = kernel_t; + } + __end_current_label_crit_section(label, needput); + + if (IS_ERR(out)) + return NF_DROP_ERR(PTR_ERR(out)); + + if (!out) + /* all profiles decline to provide a label */ + out = unlabeled_t; + + /* put mark on packet */ + aa_pin_secid(out); + skb->secmark = out->secid; + if (out != unlabeled_t && out != kernel_t) + aa_put_label(out); + + return NF_ACCEPT; +} + +/* HOOKS requiring NETFILTER, and may require SECMARK */ +static const struct nf_hook_ops apparmor_nf_ops[] = { + { + .hook = apparmor_ip_localout, + .pf = NFPROTO_IPV4, + .hooknum = NF_INET_LOCAL_OUT, + .priority = NF_IP_PRI_SELINUX_FIRST, + }, +#ifdef CONFIG_NETWORK_SECMARK + { + .hook = apparmor_ip_postroute, + .pf = NFPROTO_IPV4, + .hooknum = NF_INET_POST_ROUTING, + .priority = NF_IP_PRI_SELINUX_FIRST, + }, + /* ip_forward goes here is apparmor ever supports it + *{ + * .hook = apparmor_ip_forward, + * .pf = NFPROTO_IPV4, + * .hooknum = NF_INET_FORWARD, + * .priority = NF_IP_PRI_SELINUX_FIRST, + *}, + */ +#endif /* CONFIG_NETWORK_SECMARK */ + +#if IS_ENABLED(CONFIG_IPV6) + { + .hook = apparmor_ip_localout, + .pf = NFPROTO_IPV6, + .hooknum = NF_INET_LOCAL_OUT, + .priority = NF_IP6_PRI_SELINUX_FIRST, + }, +#ifdef CONFIG_NETWORK_SECMARK + { + .hook = apparmor_ip_postroute, + .pf = NFPROTO_IPV6, + .hooknum = NF_INET_POST_ROUTING, + .priority = NF_IP6_PRI_SELINUX_FIRST, + }, + /* ip_forward goes here is apparmor ever supports it + *{ + * .hook = apparmor_ip_forward, + * .pf = NFPROTO_IPV6, + * .hooknum = NF_INET_FORWARD, + * .priority = NF_IP6_PRI_SELINUX_FIRST, + *}, + */ +#endif /* CONFIG_NETWORK_SECMARK */ +#endif /* IS_ENABLED(CONFIG_IPV6) */ +}; +#endif /* CONFIG_NETFILTER */ /* * The cred blob is a pointer to, not an instance of, an aa_label. @@ -1652,8 +2128,13 @@ struct lsm_blob_sizes apparmor_blob_sizes __ro_after_init = { .lbs_cred = sizeof(struct aa_label *), .lbs_file = sizeof(struct aa_file_ctx), + .lbs_inode = sizeof(struct aa_inode_sec), .lbs_task = sizeof(struct aa_task_ctx), .lbs_sock = sizeof(struct aa_sk_ctx), + .lbs_secmark = true, + .lbs_ipc = sizeof(struct aa_ipc_sec), + .lbs_msg_msg = sizeof(struct aa_msg_sec), + .lbs_superblock = sizeof(struct aa_superblock_sec), }; static const struct lsm_id apparmor_lsmid = { @@ -1684,6 +2165,16 @@ LSM_HOOK_INIT(path_truncate, apparmor_path_truncate), LSM_HOOK_INIT(inode_getattr, apparmor_inode_getattr), + LSM_HOOK_INIT(inode_alloc_security, apparmor_inode_alloc_security), + LSM_HOOK_INIT(inode_free_security, apparmor_inode_free_security), + LSM_HOOK_INIT(inode_init_security, apparmor_inode_init_security), + LSM_HOOK_INIT(d_instantiate, apparmor_d_instantiate), + + LSM_HOOK_INIT(inode_create, apparmor_inode_create), + LSM_HOOK_INIT(inode_unlink, apparmor_inode_unlink), + LSM_HOOK_INIT(inode_setattr, apparmor_inode_setattr), + LSM_HOOK_INIT(inode_getattr, apparmor_inode_getattr), + LSM_HOOK_INIT(file_open, apparmor_file_open), LSM_HOOK_INIT(file_receive, apparmor_file_receive), LSM_HOOK_INIT(file_permission, apparmor_file_permission), @@ -1720,17 +2211,18 @@ LSM_HOOK_INIT(socket_getsockopt, apparmor_socket_getsockopt), LSM_HOOK_INIT(socket_setsockopt, apparmor_socket_setsockopt), LSM_HOOK_INIT(socket_shutdown, apparmor_socket_shutdown), -#ifdef CONFIG_NETWORK_SECMARK LSM_HOOK_INIT(socket_sock_rcv_skb, apparmor_socket_sock_rcv_skb), +#ifdef CONFIG_NETWORK_SECMARK + LSM_HOOK_INIT(secmark_relabel_packet, apparmor_secmark_relabel_packet), + LSM_HOOK_INIT(secmark_refcount_inc, apparmor_secmark_refcount_inc), + LSM_HOOK_INIT(secmark_refcount_dec, apparmor_secmark_refcount_dec), #endif LSM_HOOK_INIT(socket_getpeersec_stream, apparmor_socket_getpeersec_stream), LSM_HOOK_INIT(socket_getpeersec_dgram, apparmor_socket_getpeersec_dgram), LSM_HOOK_INIT(sock_graft, apparmor_sock_graft), -#ifdef CONFIG_NETWORK_SECMARK LSM_HOOK_INIT(inet_conn_request, apparmor_inet_conn_request), -#endif LSM_HOOK_INIT(cred_alloc_blank, apparmor_cred_alloc_blank), LSM_HOOK_INIT(cred_free, apparmor_cred_free), @@ -2073,7 +2565,7 @@ return -EINVAL; if (apparmor_initialized && !aa_current_policy_view_capable(NULL)) return -EPERM; - return sprintf(buffer, "%s", audit_mode_names[aa_g_audit]); + return sysfs_emit(buffer, "%s\n", audit_mode_names[aa_g_audit]); } static int param_set_audit(const char *val, const struct kernel_param *kp) @@ -2101,8 +2593,7 @@ return -EINVAL; if (apparmor_initialized && !aa_current_policy_view_capable(NULL)) return -EPERM; - - return sprintf(buffer, "%s", aa_profile_mode_names[aa_g_profile_mode]); + return sysfs_emit(buffer, "%s\n", aa_profile_mode_names[aa_g_profile_mode]); } static int param_set_mode(const char *val, const struct kernel_param *kp) @@ -2327,6 +2818,17 @@ return proc_dointvec(table, write, buffer, lenp, ppos); } +static int userns_restrict_dointvec(const struct ctl_table *table, int write, + void *buffer, size_t *lenp, loff_t *ppos) +{ + if (!apparmor_enabled) + return -EINVAL; + if (write && !aa_current_policy_admin_capable(NULL)) + return -EPERM; + + return proc_dointvec(table, write, buffer, lenp, ppos); +} + static const struct ctl_table apparmor_sysctl_table[] = { #ifdef CONFIG_USER_NS { @@ -2344,10 +2846,54 @@ .mode = 0600, .proc_handler = apparmor_dointvec, }, +#ifdef CONFIG_USER_NS + { + .procname = "apparmor_restrict_unprivileged_userns", + .data = &aa_unprivileged_userns_restricted, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = userns_restrict_dointvec, + }, + { + .procname = "apparmor_restrict_unprivileged_userns_force", + .data = &aa_unprivileged_userns_restricted_force, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = apparmor_dointvec, + }, + { + .procname = "apparmor_restrict_unprivileged_userns_complain", + .data = &aa_unprivileged_userns_restricted_complain, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = apparmor_dointvec, + }, +#endif /* CONFIG_USER_NS */ { .procname = "apparmor_restrict_unprivileged_unconfined", .data = &aa_unprivileged_unconfined_restricted, .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = userns_restrict_dointvec, + }, + { + .procname = "apparmor_restrict_unprivileged_io_uring", + .data = &aa_unprivileged_uring_restricted, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = apparmor_dointvec, + }, + { + .procname = "apparmor_cache_timeout", + .data = &aa_cache_timeout, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = apparmor_dointvec, + }, + { + .procname = "apparmor_packet_mediation", + .data = &aa_skb_packet_mediation, + .maxlen = sizeof(int), .mode = 0600, .proc_handler = apparmor_dointvec, }, @@ -2364,51 +2910,8 @@ } #endif /* CONFIG_SYSCTL */ -#if defined(CONFIG_NETFILTER) && defined(CONFIG_NETWORK_SECMARK) -static unsigned int apparmor_ip_postroute(void *priv, - struct sk_buff *skb, - const struct nf_hook_state *state) -{ - struct aa_sk_ctx *ctx; - struct sock *sk; - int error; - - if (!skb->secmark) - return NF_ACCEPT; - - sk = skb_to_full_sk(skb); - if (sk == NULL) - return NF_ACCEPT; - - ctx = aa_sock(sk); - rcu_read_lock(); - error = apparmor_secmark_check(rcu_dereference(ctx->label), OP_SENDMSG, - AA_MAY_SEND, skb->secmark, sk); - rcu_read_unlock(); - if (!error) - return NF_ACCEPT; - - return NF_DROP_ERR(-ECONNREFUSED); - -} - -static const struct nf_hook_ops apparmor_nf_ops[] = { - { - .hook = apparmor_ip_postroute, - .pf = NFPROTO_IPV4, - .hooknum = NF_INET_POST_ROUTING, - .priority = NF_IP_PRI_SELINUX_FIRST, - }, -#if IS_ENABLED(CONFIG_IPV6) - { - .hook = apparmor_ip_postroute, - .pf = NFPROTO_IPV6, - .hooknum = NF_INET_POST_ROUTING, - .priority = NF_IP6_PRI_SELINUX_FIRST, - }, -#endif -}; +#if defined(CONFIG_NETFILTER) && defined(CONFIG_NETWORK_SECMARK) static int __net_init apparmor_nf_register(struct net *net) { return nf_register_net_hooks(net, apparmor_nf_ops, @@ -2439,7 +2942,7 @@ return 0; } -#endif +#endif /* defined(CONFIG_NETFILTER) && defined(CONFIG_NETWORK_SECMARK) */ static char nulldfa_src[] __aligned(8) = { #include "nulldfa.in" @@ -2506,7 +3009,16 @@ static int __init apparmor_init(void) { - int error; + int error = -ENOMEM; + + /* setup allocation caches */ + aa_audit_slab = kmem_cache_create("apparmor_auditcache", + sizeof(struct aa_audit_node), + 0, SLAB_PANIC, NULL); + if (!aa_audit_slab) { + AA_ERROR("Unable to setup auditdata slab cache\n"); + goto alloc_out; + } error = aa_setup_dfa_engine(); if (error) { @@ -2554,6 +3066,18 @@ else aa_info_message("AppArmor initialized"); + if (aa_secmark()) { + if (aa_skb_packet_mediation) + aa_info_message("AppArmor secmark mediation enabled"); + else + aa_info_message("AppArmor secmark mediation reserved: ready to be enabled"); + } else { +#ifdef CONFIG_NETWORK_SECMARK + aa_info_message("AppArmor secmark mediation disabled - failed to register"); +#else + aa_info_message("AppArmor secmark mediation disabled by config"); +#endif /* CONFIG_NETWORK_SECMARK */ + } return error; buffers_out: @@ -2561,6 +3085,7 @@ alloc_out: aa_destroy_aafs(); aa_teardown_dfa_engine(); + kmem_cache_destroy(aa_audit_slab); apparmor_enabled = false; return error; @@ -2568,7 +3093,7 @@ DEFINE_LSM(apparmor) = { .id = &apparmor_lsmid, - .flags = LSM_FLAG_LEGACY_MAJOR | LSM_FLAG_EXCLUSIVE, + .flags = LSM_FLAG_LEGACY_MAJOR, .enabled = &apparmor_enabled, .blobs = &apparmor_blob_sizes, .init = apparmor_init, --- linux-nvidia-7.0.0.orig/security/apparmor/match.c +++ linux-nvidia-7.0.0/security/apparmor/match.c @@ -27,13 +27,13 @@ * @blob: data to unpack (NOT NULL) * @bsize: size of blob * - * Returns: pointer to table else NULL on failure + * Returns: pointer to table else ERR_PTR on failure * * NOTE: must be freed by kvfree (not kfree) */ static struct table_header *unpack_table(char *blob, size_t bsize) { - struct table_header *table = NULL; + struct table_header *table = ERR_PTR(-EPROTO); struct table_header th; size_t tsize; @@ -74,20 +74,21 @@ else if (th.td_flags == YYTD_DATA32) UNPACK_ARRAY(table->td_data, blob, th.td_lolen, u32, __be32, get_unaligned_be32); - else - goto fail; + else { + kvfree(table); + table = ERR_PTR(-EPROTO); + goto out; + } /* if table was vmalloced make sure the page tables are synced * before it is used, as it goes live to all cpus. */ if (is_vmalloc_addr(table)) vm_unmap_aliases(); - } + } else + table = ERR_PTR(-ENOMEM); out: return table; -fail: - kvfree(table); - return NULL; } /** @@ -359,8 +360,11 @@ while (size > 0) { table = unpack_table(data, size); - if (!table) + if (IS_ERR(table)) { + error = PTR_ERR(table); + table = NULL; goto fail; + } switch (table->td_id) { case YYTD_ID_ACCEPT: --- linux-nvidia-7.0.0.orig/security/apparmor/net.c +++ linux-nvidia-7.0.0/security/apparmor/net.c @@ -9,6 +9,7 @@ */ #include "include/af_unix.h" +#include "include/af_inet.h" #include "include/apparmor.h" #include "include/audit.h" #include "include/cred.h" @@ -22,6 +23,7 @@ struct aa_sfs_entry aa_sfs_entry_network[] = { AA_SFS_FILE_STRING("af_mask", AA_SFS_AF_MASK), + AA_SFS_FILE_BOOLEAN("af_inet", 1), { } }; @@ -30,6 +32,21 @@ AA_SFS_FILE_BOOLEAN("af_unix", 1), { } }; +struct aa_sfs_entry aa_sfs_entry_networkv9_skb[] = { + AA_SFS_FILE_STRING("af_mask", "inet inet6"), + AA_SFS_FILE_STRING("iface", "receive connect, secmark_postroute"), + AA_SFS_FILE_STRING("rcv_skb", "secmark_receive"), + /*AA_SFS_FILE_STRING("forward", "secmar_forwardk"),*/ + AA_SFS_FILE_STRING("postroute", "secmark_send"), + AA_SFS_FILE_STRING("localout", "secmark_set"), + AA_SFS_FILE_STRING("relabel", "setcred"), + { } +}; +struct aa_sfs_entry aa_sfs_entry_network_compat[] = { + AA_SFS_FILE_STRING("af_mask", AA_SFS_AF_MASK), + AA_SFS_FILE_BOOLEAN("af_unix", 1), + { } +}; static const char * const net_mask_names[] = { "unknown", @@ -70,7 +87,7 @@ "unknown", "unknown", "unknown", - "unknown", + "set_label", }; static void audit_unix_addr(struct audit_buffer *ab, const char *str, @@ -131,12 +148,12 @@ audit_log_format(ab, " protocol=%d", ad->net.protocol); if (ad->request & NET_PERMS_MASK) { - audit_log_format(ab, " requested_mask="); + audit_log_format(ab, " requested="); aa_audit_perm_mask(ab, ad->request, NULL, 0, net_mask_names, NET_PERMS_MASK); if (ad->denied & NET_PERMS_MASK) { - audit_log_format(ab, " denied_mask="); + audit_log_format(ab, " denied="); aa_audit_perm_mask(ab, ad->denied, NULL, 0, net_mask_names, NET_PERMS_MASK); } @@ -246,10 +263,44 @@ return state; } -/* Generic af perm */ -int aa_profile_af_perm(struct aa_profile *profile, +int aa_profile_af_compat_perm(struct aa_profile *profile, struct apparmor_audit_data *ad, u32 request, u16 family, - int type, int protocol) + int type) +{ + AA_BUG(family >= AF_MAX); + AA_BUG(type < 0 || type >= SOCK_MAX); + + /* 2.x socket mediation was opt in, ie. only applied if net_compat + * struct is present + */ + if (profile->net_compat && !profile_unconfined(profile)) { + /* 2.x socket mediation compat */ + struct aa_ruleset *rules = profile->label.rules[0]; + aa_state_t state = DFA_NOMATCH; + + struct aa_perms perms = { }; + + perms.allow = (profile->net_compat->allow[family] & + (1 << type)) ? + ALL_PERMS_MASK : 0; + perms.audit = (profile->net_compat->audit[family] & + (1 << type)) ? + ALL_PERMS_MASK : 0; + perms.quiet = (profile->net_compat->quiet[family] & + (1 << type)) ? + ALL_PERMS_MASK : 0; + + return aa_do_perms(profile, rules->policy, state, request, + &perms, ad); + } + + return 0; +} + +/* Generic af perm */ +static int profile_af_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, u32 request, + u16 family, int type, int protocol) { struct aa_ruleset *rules = profile->label.rules[0]; struct aa_perms *p = NULL; @@ -257,16 +308,16 @@ AA_BUG(family >= AF_MAX); AA_BUG(type < 0 || type >= SOCK_MAX); - AA_BUG(profile_unconfined(profile)); - if (profile_unconfined(profile)) - return 0; state = RULE_MEDIATES_NET(rules); - if (!state) - return 0; - state = aa_match_to_prot(rules->policy, state, request, family, type, - protocol, &p, &ad->info); - return aa_do_perms(profile, rules->policy, state, request, p, ad); + if (state) { + state = aa_match_to_prot(rules->policy, state, request, family, + type, protocol, &p, &ad->info); + return aa_do_perms(profile, rules->policy, state, request, p, + ad); + } /* else */ + + return aa_profile_af_compat_perm(profile, ad, request, family, type); } int aa_af_perm(const struct cred *subj_cred, struct aa_label *label, @@ -276,14 +327,14 @@ DEFINE_AUDIT_NET(ad, op, subj_cred, NULL, family, type, protocol); return fn_for_each_confined(label, profile, - aa_profile_af_perm(profile, &ad, request, family, - type, protocol)); + profile_af_perm(profile, &ad, request, family, type, + protocol)); } static int aa_label_sk_perm(const struct cred *subj_cred, struct aa_label *label, const char *op, u32 request, - struct sock *sk) + const struct sock *sk) { struct aa_sk_ctx *ctx = aa_sock(sk); int error = 0; @@ -297,13 +348,14 @@ ad.subj_cred = subj_cred; error = fn_for_each_confined(label, profile, - aa_profile_af_sk_perm(profile, &ad, request, sk)); + profile_af_perm(profile, &ad, request, sk->sk_family, + sk->sk_type, sk->sk_protocol)); } return error; } -int aa_sk_perm(const char *op, u32 request, struct sock *sk) +int aa_sk_perm(const char *op, u32 request, const struct sock *sk) { struct aa_label *label; int error; @@ -331,8 +383,15 @@ if (!sock || !sock->sk) return 0; - if (sock->sk->sk_family == PF_UNIX) + switch (sock->sk->sk_family) { + case PF_UNIX: return aa_unix_file_perm(subj_cred, label, op, request, file); + break; + case PF_INET: + case PF_INET6: + return aa_inet_file_perm(subj_cred, label, op, request, sock); + break; + } return aa_label_sk_perm(subj_cred, label, op, request, sock->sk); } @@ -392,12 +451,15 @@ return aa_check_perms(profile, &perms, request, ad, audit_net_cb); } -int apparmor_secmark_check(struct aa_label *label, char *op, u32 request, +int apparmor_secmark_check(struct aa_label *label, const char *op, u32 request, u32 secid, const struct sock *sk) { struct aa_profile *profile; DEFINE_AUDIT_SK(ad, op, NULL, sk); + if (secid == 0) + return 0; + return fn_for_each_confined(label, profile, aa_secmark_perm(profile, request, secid, &ad)); --- linux-nvidia-7.0.0.orig/security/apparmor/notify.c +++ linux-nvidia-7.0.0/security/apparmor/notify.c @@ -0,0 +1,1406 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AppArmor security module + * + * This file contains AppArmor notifications function definitions. + * + * Copyright 2019 Canonical Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + */ +#include +#include +#include +#include + +#include + +#include "include/audit.h" +#include "include/cred.h" +#include "include/lib.h" +#include "include/notify.h" +#include "include/policy.h" +#include "include/policy_ns.h" + + +#define DEFAULT_TEMPORAL_CACHE_TIMEOUT 5 + +int aa_cache_timeout = DEFAULT_TEMPORAL_CACHE_TIMEOUT; + +static DEFINE_SPINLOCK(notif_lock); +static u64 g_listener_id = 1; + +static u64 get_next_listener_id(void) +{ + u64 tmp; + + spin_lock(¬if_lock); + tmp = ++g_listener_id; + spin_unlock(¬if_lock); + + return tmp; +} + +/*****************************************************************/ + +/* TODO: when adding listener or ns propagate, on recursive add to child ns */ + +// TODO: currently all knotif will have audit_node but not all in future +static inline struct aa_knotif *aa_get_knotif(struct aa_knotif *knotif) +{ + if (knotif) + aa_get_audit_node(container_of(knotif, struct aa_audit_node, + knotif)); + + return knotif; +} + +static inline void aa_put_knotif(struct aa_knotif *knotif) +{ + if (knotif) + aa_put_audit_node(container_of(knotif, struct aa_audit_node, + knotif)); +} + +static void put_refs(struct aa_listener *listener, struct aa_knotif *knotif) +{ + aa_put_listener(listener); + aa_put_knotif(knotif); +} + +static void get_refs(struct aa_listener *listener, struct aa_knotif *knotif) +{ + aa_get_listener(listener); + aa_get_knotif(knotif); +} + +static void __knotif_del_and_hold(struct aa_knotif *knotif) +{ + list_del_init(&knotif->list); + knotif->flags &= ~KNOTIF_ON_LIST; + /* keep list refcounts */ +} + +static void __list_append_held(struct list_head *lh, struct aa_knotif *knotif) +{ + AA_BUG(!lh); + AA_BUG(!knotif); + + list_add_tail_entry(knotif, lh, list); + knotif->flags |= KNOTIF_ON_LIST; +} + +/* +static void __list_push_held(struct list_head *lh, struct aa_knotif *knotif) +{ + AA_BUG(!lh); + AA_BUG(!knotif); + + list_add_entry(knotif, lh, list); + knotif->flags |= KNOTIF_ON_LIST; +} +*/ + +static void __listener_add_knotif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + AA_BUG(!knotif); + lockdep_assert_held(&listener->lock); + + get_refs(listener, knotif); + __list_append_held(&listener->notifications, knotif); +} + +// drops refs +static void __listener_del_knotif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + AA_BUG(!knotif); + lockdep_assert_held(&listener->lock); + + list_del_init(&knotif->list); + if (knotif->flags & KNOTIF_ON_LIST) { + knotif->flags &= ~KNOTIF_ON_LIST; + put_refs(listener, knotif); + } +} + +void aa_free_listener_proxy(struct aa_listener_proxy *proxy) +{ + if (proxy->listener) { + spin_lock(&proxy->listener->lock); + list_del_init(&proxy->llist); + spin_unlock(&proxy->listener->lock); + } + if (proxy->ns) { + spin_lock(&proxy->ns->listener_lock); + list_del_init(&proxy->nslist); + spin_unlock(&proxy->ns->listener_lock); + } + aa_put_ns(proxy->ns); + aa_put_listener(proxy->listener); + kfree_sensitive(proxy); +} + +// transfers listeners refcount +struct aa_listener_proxy *aa_new_listener_proxy(struct aa_listener *listener, + struct aa_ns *ns) +{ + struct aa_listener_proxy *proxy; + + AA_BUG(!listener); + lockdep_assert_not_held(&listener->lock); + + proxy = kzalloc(sizeof(*proxy), GFP_KERNEL); + if (!proxy) + return NULL; + INIT_LIST_HEAD(&proxy->llist); + INIT_LIST_HEAD(&proxy->nslist); + + proxy->listener = aa_get_listener(listener); + if (ns) + ns = aa_get_ns(ns); + else + ns = aa_get_current_ns(); + proxy->ns = ns; + + spin_lock(&listener->lock); + list_add_tail_entry(proxy, &listener->ns_proxies, llist); + spin_unlock(&listener->lock); + + spin_lock(&ns->listener_lock); + list_add_tail_entry(proxy, &ns->listeners, nslist); + spin_unlock(&ns->listener_lock); + + AA_DEBUG(DEBUG_UPCALL, "Added new listener proxy for listener %lld", listener->listener_id); + return proxy; +} + +static void free_listener(struct aa_listener *listener) +{ + struct aa_listener_proxy *proxy; + struct aa_knotif *knotif; + + AA_DEBUG(DEBUG_UPCALL, "enter freeing listener_id %llu", listener->listener_id); + if (!listener) + return; + + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); + + spin_lock(&listener->lock); + while (!list_empty(&listener->ns_proxies)) { + proxy = list_first_entry(&listener->ns_proxies, + struct aa_listener_proxy, + llist); + list_del_init(&proxy->llist); + spin_unlock(&listener->lock); + + spin_lock(&proxy->ns->listener_lock); + list_del_init(&proxy->nslist); + spin_unlock(&proxy->ns->listener_lock); + + aa_put_ns(proxy->ns); + kfree_sensitive(proxy); + + spin_lock(&listener->lock); + } + spin_unlock(&listener->lock); + + spin_lock(&listener->lock); + while (!list_empty(&listener->notifications)) { + knotif = list_first_entry(&listener->notifications, + struct aa_knotif, + list); + __listener_del_knotif(listener, knotif); + complete(&knotif->ready); + put_refs(listener, knotif); + } + spin_unlock(&listener->lock); + + spin_lock(&listener->lock); + while (!list_empty(&listener->pending)) { + knotif = list_first_entry(&listener->pending, + struct aa_knotif, + list); + __listener_del_knotif(listener, knotif); + complete(&knotif->ready); + put_refs(listener, knotif); + } + spin_unlock(&listener->lock); + + /* todo count on audit_data */ + aa_put_ns(listener->ns); + aa_put_dfa(listener->filter); + aa_put_label(listener->label); + + AA_DEBUG(DEBUG_UPCALL, "freeing listener_id %llu", listener->listener_id); + kfree_sensitive(listener); +} + +void aa_listener_kref(struct kref *kref) +{ + struct aa_listener *l = container_of(kref, struct aa_listener, count); + + AA_DEBUG(DEBUG_UPCALL, "going to free listener %p, label %p, id %llu", l, l->label, l->listener_id); + free_listener(l); +} + +#define from_delayed_work(var, callback_work, work_fieldname) \ + container_of(to_delayed_work(callback_work), typeof(*var), work_fieldname) + +static void proxy_work_function(struct work_struct *t) +{ + struct aa_listener_proxy *proxy = from_delayed_work(proxy, t, work); + AA_DEBUG(DEBUG_UPCALL, "listener reclaim timer fired. Putting listener %llu", proxy->listener->listener_id); + aa_free_listener_proxy(proxy); + /* don't want to remove here because may have been reclaimed */ + //aa_put_listener(proxy->listener); +} + + +//unsigned long seconds = 1; +void aa_delayed_free_listener_proxy(struct aa_listener_proxy *proxy) +{ + memset(&proxy->work, 0, sizeof(proxy->work)); + + AA_DEBUG(DEBUG_UPCALL, "before timer listener %p listener_id %llu label %p", proxy->listener, proxy->listener->listener_id, proxy->listener->label); + + /* delay putting the listener giving a chance to reclaim */ + INIT_DELAYED_WORK(&proxy->work, proxy_work_function); + schedule_delayed_work(&proxy->work, secs_to_jiffies(30)); + + AA_DEBUG(DEBUG_UPCALL, "after timer listener %p listener_id %llu label %p", proxy->listener, proxy->listener->listener_id, proxy->listener->label); +} + +struct aa_listener *aa_new_listener(struct aa_ns *ns, gfp_t gfp) +{ + struct aa_listener *listener = kzalloc(sizeof(*listener), gfp); + + if (!listener) + return NULL; + AA_DEBUG(DEBUG_UPCALL, "listener %p", listener); + + kref_init(&listener->count); + spin_lock_init(&listener->lock); + init_waitqueue_head(&listener->wait); + INIT_LIST_HEAD(&listener->ns_proxies); + INIT_LIST_HEAD(&listener->notifications); + INIT_LIST_HEAD(&listener->pending); + kref_init(&listener->count); + + if (ns) + ns = aa_get_ns(ns); + else + ns = aa_get_current_ns(); + listener->ns = ns; + listener->last_id = 1; + listener->listener_id = get_next_listener_id(); + + AA_DEBUG(DEBUG_UPCALL, "created listener %lld ns %p", listener->listener_id, ns); + return listener; +} + +/* increments proxy->listener ref count +* can still be on list because file callback to cleanup is delayed +*/ +static struct aa_listener *find_matching_listener_by_id(struct aa_ns *ns, + u64 id) +{ + struct aa_listener *listener = NULL; + struct aa_listener_proxy *proxy = NULL; + + spin_lock(&ns->listener_lock); + list_for_each_entry(proxy, &ns->listeners, nslist) { + AA_DEBUG(DEBUG_UPCALL, " comparing listener %p label %p id %llu to %llu", proxy->listener, proxy->listener->label, proxy->listener->listener_id, id); + spin_lock(&proxy->listener->lock); + if (proxy->listener->listener_id == id) { + listener = aa_get_listener(proxy->listener); + spin_unlock(&proxy->listener->lock); + AA_DEBUG(DEBUG_UPCALL, " found listener %p label %p id %llu to %llu", listener, listener->label, listener->listener_id, id); + break; + } + spin_unlock(&proxy->listener->lock); + } + spin_unlock(&ns->listener_lock); + + return listener; +} + +/* attempt to register a listener. If id is 0 get a new id else find + * existing listener + */ +long aa_register_listener_id(struct aa_listener *listener, u64 *id, + struct aa_listener **found) +{ + struct aa_label *label; + int error = 0; + + AA_BUG(!listener); + AA_BUG(!id); + + *found = NULL; + + label = begin_current_label_crit_section(); + if (*id == 0) { + spin_lock(&listener->ns->listener_lock); + if (listener->label) { + if (listener->label == label) { + *id = listener->listener_id; + } else { + error = -EPERM; + } + } else { + listener->label = aa_get_label(label); + *id = listener->listener_id; + AA_DEBUG(DEBUG_UPCALL, "assigned label %p to listener %p listener->label %p id %llu", label, listener, listener->label, listener->listener_id); + } + spin_unlock(&listener->ns->listener_lock); + } else { + struct aa_listener *tmp = find_matching_listener_by_id(listener->ns, *id); + if (tmp) { + if (tmp->label != label) { + AA_DEBUG(DEBUG_UPCALL, "confinement for listener %p id %llu search id %llu, listener->label %p != label %p", tmp, tmp->listener_id, *id, tmp->label , label); + aa_put_listener(tmp); + error = -EPERM; + } else { + *found = tmp; + } + } else { + AA_DEBUG(DEBUG_UPCALL, " no listener found"); + error = -ENOENT; + } + } + end_current_label_crit_section(label); + + return error; +} + +static struct aa_knotif *__aa_find_notif_pending(struct aa_listener *listener, + u64 id) +{ + struct aa_knotif *knotif; + + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + list_for_each_entry(knotif, &listener->pending, list) { + if (knotif->id == id) + return knotif; + } + + return NULL; +} + +struct aa_knotif *__aa_find_notif(struct aa_listener *listener, u64 id) +{ + struct aa_knotif *knotif; + + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + list_for_each_entry(knotif, &listener->notifications, list) { + if (knotif->id == id) + goto out; + } + + knotif = __aa_find_notif_pending(listener, id); +out: + + return knotif; +} + +// don't drop refcounts +/* TODO: replace use of pop/push with more correct append or enqueue/dequeue */ +static struct aa_knotif * +listener_pop_and_hold_knotif(struct aa_listener *listener) +{ + struct aa_knotif *knotif = NULL; + + spin_lock(&listener->lock); + if (!list_empty(&listener->notifications)) { + knotif = list_first_entry(&listener->notifications, typeof(*knotif), list); + __knotif_del_and_hold(knotif); + } + spin_unlock(&listener->lock); + + return knotif; +} + +// require refcounts held +/* +static void listener_push_held_knotif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + spin_lock(&listener->lock); + // listener ref held from pop and hold + __list_push_held(&listener->notifications, knotif); + spin_unlock(&listener->lock); + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); +} +*/ + +// require refcounts held +// list of knotifs waiting for response +static void listener_append_held_user_pending(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + spin_lock(&listener->lock); + __list_append_held(&listener->pending, knotif); + spin_unlock(&listener->lock); + //extraneous wakeup, called after reading notification + //wake_up_interruptible_poll(&listener->wait, EPOLLOUT | EPOLLWRNORM); +} + +// don't drop refcounts +static struct aa_knotif * +__del_and_hold_user_pending(struct aa_listener *listener, u64 id) +{ + struct aa_knotif *knotif; + + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + list_for_each_entry(knotif, &listener->pending, list) { + if (knotif->id == id) { + __knotif_del_and_hold(knotif); + return knotif; + } + } + + return NULL; +} + + +/***************** kernel dispatching notification ********************/ + +/* + * cancelled notification message due to non-timer wake-up vs. + * keep alive message + * cancel notification because ns removed? + * - proxy pins ns + * - ns can remove its list of proxies + * - and remove queued notifications + */ + +/* TODO: allow registering on multiple namespaces */ +static bool notification_match(struct aa_listener *listener, + struct aa_audit_node *ad) +{ + if (!(listener->mask & (1 << ad->data.type))) { + AA_DEBUG(DEBUG_UPCALL, "listener mask failed 0x%x, type %d", listener->mask, ad->data.type); + return false; + } + + if (listener->filter) { + aa_state_t state; + unsigned int mask; + + AA_DEBUG(DEBUG_UPCALL, "using filter"); + if (!aa_ns_visible(listener->ns, labels_ns(ad->data.subj_label), + false)) + return false; + state = aa_dfa_next(listener->filter, DFA_START, ad->data.type); + state = aa_dfa_match(listener->filter, state, ad->data.subj_label->hname); + if (!state) + return false; + state = aa_dfa_null_transition(listener->filter, state); + state = aa_dfa_match_u16(listener->filter, state, ad->data.class); + mask = ACCEPT_TABLE(listener->filter)[state]; + if (ad->data.request & mask) + return true; + + /* allow for enhanced match conditions in the future + * if (mask & AA_MATCH_CONT) { + * // TODO: match extensions + * } + */ + AA_DEBUG(DEBUG_UPCALL, "failed filter match"); + return false; + } + AA_DEBUG(DEBUG_UPCALL, "matched type mask filter"); + return true; +} + +/* Add a notification to the listener queue and wake up listener??? */ +static void dispatch_notif(struct aa_listener *listener, u16 ntype, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + AA_BUG(!knotif); + lockdep_assert_held(&listener->lock); + + AA_DEBUG_ON(knotif->id, DEBUG_UPCALL, + "dispatching notification as new id %lld", + listener->last_id); + knotif->ntype = ntype; + knotif->id = ++listener->last_id; + knotif->flags = 0; + // only needed if syncrhonous notit + init_completion(&knotif->ready); + INIT_LIST_HEAD(&knotif->list); + __listener_add_knotif(listener, knotif); + AA_DEBUG(DEBUG_UPCALL, "id %lld: %s wake_up_interruptible", + knotif->id, __func__); + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); +} + + +/* handle waiting for a user space reply to a notification + * Returns: <0 : error or -ERESTARTSYS if interrupted + * 0 : success + */ +static int handle_synchronous_notif(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + long werr; + int err; + + if (knotif->ad->subj_label->flags & FLAG_INTERRUPTIBLE) + werr = wait_for_completion_interruptible_timeout(&knotif->ready, + msecs_to_jiffies(60000)); + else + /* do not use close to long jiffies so cast is safe */ + werr = (long) wait_for_completion_timeout(&knotif->ready, + msecs_to_jiffies(60000)); + /* time out OR interrupt */ + if (werr <= 0) { + /* ensure knotif is not on list because of early exit */ + spin_lock(&listener->lock); + // puts refs but still have calling refs + __listener_del_knotif(listener, knotif); + spin_unlock(&listener->lock); + if (werr == 0) { + AA_DEBUG(DEBUG_UPCALL, "id %lld: prompt timed out", + knotif->id); + //err = -1; // TODO: ???; + err = 0; + } else if (werr == -ERESTARTSYS) { + // interrupt fired syscall needs to be restarted + // instead of mediated + AA_DEBUG(DEBUG_UPCALL, "id %lld: prompt interrupted, error %ld", + knotif->id, werr); + err = -ERESTARTSYS; + } else { + AA_DEBUG(DEBUG_UPCALL, "id %lld: prompt errored out error %ld", + knotif->id, werr); + err = (int) werr; + } + /* time out is not considered an error and will fallback + * to regular mediation + */ + } else { + err = 0; + spin_lock(&listener->lock); + if (!list_empty(&knotif->list)) { + // puts refs but still have calling refs + __listener_del_knotif(listener, knotif); + AA_DEBUG(DEBUG_UPCALL, + "id %lld: bug prompt knotif still on listener list at notif completion", + knotif->id); + } + spin_unlock(&listener->lock); + } + + return err; +} + +// permissions changed in ad +int aa_do_notification(u16 ntype, struct aa_audit_node *node) +{ + struct aa_ns *ns = labels_ns(node->data.subj_label); + struct aa_listener_proxy *proxy; + struct aa_listener *listener; + struct aa_knotif *knotif; + int count = 0, err = 0; + + AA_BUG(!node); + AA_BUG(!ns); + + knotif = &node->knotif; + + /* TODO: make read side of list walk lockless */ + spin_lock(&ns->listener_lock); + list_for_each_entry(proxy, &ns->listeners, nslist) { + + AA_BUG(!proxy); + listener = aa_get_listener(proxy->listener); + AA_BUG(!listener); + spin_lock(&listener->lock); + AA_DEBUG(DEBUG_UPCALL, "checking listener %lld for match", listener->listener_id); + if (!notification_match(listener, node)) { + spin_unlock(&listener->lock); + aa_put_listener(listener); + continue; + } + /* delvier notification - dispatch determines if we break */ + dispatch_notif(listener, ntype, knotif); + spin_unlock(&listener->lock); + AA_DEBUG(DEBUG_UPCALL, "id %lld: found listener\n", + knotif->id); + + /* break to prompt */ + if (node->data.type == AUDIT_APPARMOR_USER) { + spin_unlock(&ns->listener_lock); + err = handle_synchronous_notif(listener, knotif); + aa_put_listener(listener); + return err; + } + count++; + aa_put_listener(listener); + } + spin_unlock(&ns->listener_lock); + AA_DEBUG(DEBUG_UPCALL, "id %lld: %d listener matches\n", + knotif->id, count); + + /* count == 0 is no match found. No change to audit params + * long term need to fold prompt perms into denied + **/ + return err; +} + +long aa_listener_unotif_resend(struct aa_listener *listener, u32 *ready, + u32 *pending) +{ + struct aa_knotif *knotif; + *ready = 0; + *pending = 0; + + spin_lock(&listener->ns->listener_lock); + list_for_each_entry(knotif, &listener->notifications, list) { + (*ready)++; + } + list_for_each_entry(knotif, &listener->pending, list) { + knotif->flags = KNOTIF_RESEND; + AA_DEBUG_ON(knotif->id, DEBUG_UPCALL, + "redispatching notification id %lld", + knotif->id); + (*pending)++; + } + /* splice is like stack to move pending onto of notification + * but pulled from head like queue. ie pending is moving + * to the front of the queue. + */ + list_splice_init(&listener->pending, &listener->notifications); + AA_DEBUG(DEBUG_UPCALL, "id %lld: %s wake_up_interruptible", + knotif->id, __func__); + wake_up_interruptible_poll(&listener->wait, EPOLLIN | EPOLLRDNORM); + spin_unlock(&listener->ns->listener_lock); + + return 0; +} + +/******************** task responding to notification **********************/ + +// drop references +// complete anything pending on ready +static void __listener_complete_held_user_pending(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + AA_BUG(!listener); + lockdep_assert_held(&listener->lock); + + __knotif_del_and_hold(knotif); + complete(&knotif->ready); + put_refs(listener, knotif); +} + +static void listener_complete_held_user_pending(struct aa_listener *listener, + struct aa_knotif *knotif) +{ + spin_lock(&listener->lock); + __listener_complete_held_user_pending(listener, knotif); + spin_unlock(&listener->lock); +} + +static bool response_is_valid_perm(struct apparmor_notif_resp_perm *reply, + struct aa_knotif *knotif, u16 size) +{ + if ((knotif->ad->denied) & ~(reply->allow | reply->deny)) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: response does not cover permission bits in the upcall request/reply 0x%x/0x%x deny/reply 0x%x/0x%x", + knotif->id, knotif->ad->request, reply->allow, knotif->ad->denied, + reply->deny); + return false; + } + return true; + /* TODO: this was disabled per snapd request, setup flag to do check + * // allow bits that were never requested + * if (reply->allow & ~knotif->ad->request) { + * AA_DEBUG(DEBUG_UPCALL, "response allows more than requested"); + * return false; + * } + * // denying perms not in either permission set in the original + * // notification + * if (reply->deny & ~(knotif->ad->request | knotif->ad->denied)) { + * AA_DEBUG(DEBUG_UPCALL, "response denies more than requested"); + * return false; + * } + */ +} + +static bool response_is_valid_name(struct apparmor_notif_resp_name *reply, + struct aa_knotif *knotif, u16 size) +{ + long i; + + if (size <= sizeof(*reply)) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad size %u < %ld", + knotif->id, size, sizeof(*reply)); + return -EMSGSIZE; + } + if (reply->name < sizeof(*reply)) { + /* inside of data declared fields */ + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad name offset in fields %u < %ld", + knotif->id, reply->name, sizeof(*reply)); + return -EINVAL; + } + if (reply->name > size) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply name pasted end of data size %u > %ld", + knotif->id, reply->name, sizeof(*reply)); + return -EINVAL; + } + /* currently supported flags */ + if ((reply->perm.base.flags != (URESPONSE_LOOKUP | URESPONSE_PROFILE))) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad flags 0x%x expected 0x%x", + knotif->id, reply->perm.base.flags, + URESPONSE_LOOKUP | URESPONSE_PROFILE); + return -EINVAL; + } + + if ((reply->perm.base.flags == URESPONSE_TAILGLOB) && + !response_is_valid_perm(&reply->perm, knotif, size)) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad tail glob perms", + knotif->id); + return false; + } + + /* check name for terminating null */ + for (i = reply->name - sizeof(*reply); i < size - sizeof(*reply); i++) { + if (reply->data[i] == 0) + return true; + } + /* reached end of data without finding null */ + AA_DEBUG(DEBUG_UPCALL, + "id %lld: reply bad no terminating null on name", + knotif->id); + + return false; +} + +/* base checks userspace respnse to a notification is valid */ +static bool response_is_valid(union apparmor_notif_resp *reply, + struct aa_knotif *knotif, u16 size) +{ + if (reply->base.ntype == APPARMOR_NOTIF_RESP_PERM) + return response_is_valid_perm(&reply->perm, knotif, size); + else if (reply->base.ntype == APPARMOR_NOTIF_RESP_NAME) + return response_is_valid_name(&reply->name, knotif, size); + else + return false; + return false; +} + + +static bool insert_in_cache(struct aa_knotif *knotif) +{ + struct aa_audit_node *node = container_of(knotif, + struct aa_audit_node, + knotif); + struct aa_audit_node *hit; + struct aa_profile *profile = labels_profile(node->data.subj_label); + + AA_DEBUG(DEBUG_UPCALL, "id %lld: inserting cache entry requ 0x%x denied 0x%x", + knotif->id, node->data.request, node->data.denied); + hit = aa_audit_cache_insert(&profile->learning_cache, + node); + AA_DEBUG(DEBUG_UPCALL, + "id %lld: (node %p, hit %p) cache insert %s: name %s node %s\n", + knotif->id, node, hit, hit != node ? "entry already exists" : "", + hit->data.name, node->data.name); + if (hit != node) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: updating existing cache entry", + knotif->id); + aa_audit_cache_update_ent(&profile->learning_cache, + hit, &node->data); + aa_put_audit_node(hit); + + return false; + } + + AA_DEBUG(DEBUG_UPCALL, "inserted into cache"); + return true; +} + +static void audit_cache_work_function(struct work_struct *t) +{ + struct aa_audit_node *node = from_delayed_work(node, t, work); + struct aa_profile *profile = labels_profile(node->data.subj_label); + + AA_DEBUG(DEBUG_UPCALL, "node reclaim timer fired. Removing node %llu", node->knotif.id); + + aa_audit_cache_remove(&profile->learning_cache, node); + /* ref is put so can't rely on it being live here + AA_DEBUG(DEBUG_UPCALL, "id %lld: (node %p) cache remove %s\n", + node->knotif.id, node, node->data.name); + */ +} + + +/* copy uresponse into knotif */ +static void knotif_update_from_uresp_perm(struct aa_knotif *knotif, + struct apparmor_notif_resp_perm *uresp) +{ + u16 flags; + + if (uresp) { + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allow/reply 0x%x/0x%x, denied/reply 0x%x/0x%x, error %d/%d", + knotif->id, knotif->ad->request, uresp->allow, + knotif->ad->denied, uresp->deny, knotif->ad->error, + uresp->base.error); + + knotif->ad->denied = uresp->deny; + knotif->ad->request = (knotif->ad->request | uresp->allow) & + ~uresp->deny; + flags = uresp->base.flags; + if (!knotif->ad->denied) { + /* no more denial, clear the error*/ + knotif->ad->error = 0; + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allowed, clearing error\n", + knotif->id); + } else { + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response denied returning error %d\n", + knotif->id, knotif->ad->error); + } + } else { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: respons bad going with: allow 0x%x, denied 0x%x, error %d", + knotif->id, knotif->ad->request, knotif->ad->denied, + knotif->ad->error); + } + + if (!(flags & URESPONSE_NO_CACHE)) { + /* cache of response requested */ + insert_in_cache(knotif); + /* now to audit */ + } else if (aa_cache_timeout > 0) { + /* caching off of file is not enough because of other + * types of acces, cache for a short time for decision to + * cover immediate following accesses + */ + struct aa_audit_node *node = container_of(knotif, + struct aa_audit_node, + knotif); + + insert_in_cache(knotif); + INIT_DELAYED_WORK(&node->work, audit_cache_work_function); + schedule_delayed_work(&node->work, + secs_to_jiffies(aa_cache_timeout)); + } /* cache_response */ +} + + +void aa_free_ruleset(struct aa_ruleset *rules) +{ + if (!rules) + return; + aa_put_pdb(rules->policy); + aa_put_pdb(rules->file); + kfree_sensitive(rules); +} + +struct aa_ruleset *aa_new_ruleset(gfp_t gfp) +{ + struct aa_ruleset *rules = kzalloc(sizeof(*rules), gfp); + + return rules; +} + +struct aa_ruleset *aa_clone_ruleset(struct aa_ruleset *rules) +{ + struct aa_ruleset *clone; + + clone = aa_new_ruleset(GFP_KERNEL); + if (!clone) + return NULL; + clone->size = rules->size; + clone->policy = aa_get_pdb(rules->policy); + clone->file = aa_get_pdb(rules->file); + clone->caps = rules->caps; + clone->rlimits = rules->rlimits; + + /* TODO: secmark */ + return clone; +} + +static long knotif_update_from_uresp_name(struct aa_knotif *knotif, + struct apparmor_notif_resp_name *reply, + u16 size) +{ + struct aa_ruleset *rules; + struct aa_profile *profile; + struct aa_ns *ns; + char *name, *glob; + struct aa_audit_node *clone; + struct aa_audit_node *node = container_of(knotif, + struct aa_audit_node, + knotif); + + ns = aa_get_current_ns(); + name = (char *) &reply->data[reply->name - sizeof(*reply)]; + + if (reply->perm.base.flags == (URESPONSE_LOOKUP | URESPONSE_PROFILE)) { + profile = aa_lookupn_profile(ns, name, strlen(name)); + if (!profile) { + aa_put_ns(ns); + return -ENOENT; + } + aa_put_ns(ns); + + rules = aa_clone_ruleset(profile->label.rules[0]); + if (!rules) { + aa_put_profile(profile); + return -ENOMEM; + } + AA_DEBUG(DEBUG_UPCALL, + "id %lld: cloned profile '%s' rule set", knotif->id, + profile->base.hname); + aa_put_profile(profile); + + /* add list to profile rules TODO: improve locking*/ + profile = labels_profile(node->data.subj_label); + // list_add_tail_entry(rules, &profile->label.rules[0], list); + } else if (reply->perm.base.flags == URESPONSE_TAILGLOB) { + // TODO: dedup with cache update in perm + struct aa_audit_node *node = container_of(knotif, + struct aa_audit_node, + knotif); + struct aa_audit_node *hit; + struct aa_profile *profile = labels_profile(node->data.subj_label); + + clone = aa_dup_audit_data(&node->data, GFP_KERNEL); + glob = kstrdup(name, GFP_KERNEL); + if (!name) + return -ENOMEM; + if (!clone) { + kfree(name); + return -ENOMEM; + } + kfree(clone->data.name); + clone->data.name = glob; + clone->data.flags = AUDIT_TAILGLOB_NAME; + clone->knotif.id = knotif->id; + clone->knotif.ntype = knotif->ntype; + node = clone; + knotif = &clone->knotif; + + // now add it to the cache + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allow/reply 0x%x/0x%x, denied/reply 0x%x/0x%x, error %d/%d", + knotif->id, knotif->ad->request, reply->perm.allow, + knotif->ad->denied, reply->perm.deny, knotif->ad->error, + reply->base.error); + + knotif->ad->denied = reply->perm.deny; + knotif->ad->request = reply->perm.allow | reply->perm.deny; + + if (!knotif->ad->denied) { + /* no more denial, clear the error*/ + knotif->ad->error = 0; + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response allowed, clearing error\n", + knotif->id); + } else { + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: response denied returning error %d\n", + knotif->id, knotif->ad->error); + } + + AA_DEBUG(DEBUG_UPCALL, "id %lld: inserting cache entry requ 0x%x denied 0x%x", + knotif->id, node->data.request, node->data.denied); + hit = aa_audit_cache_insert(&profile->learning_cache, + node); + AA_DEBUG(DEBUG_UPCALL, "id %lld: cache insert %s: name %s node %s\n", + knotif->id, hit != node ? "lost race" : "", + hit->data.name, node->data.name); + if (hit != node) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: updating existing cache entry", + knotif->id); + aa_audit_cache_update_ent(&profile->learning_cache, + hit, &node->data); + aa_put_audit_node(hit); + } else { + + AA_DEBUG(DEBUG_UPCALL, "inserted into cache"); + } + aa_put_audit_node(clone); + } + return size; +} + +/* handle userspace responding to a synchronous notification */ +long aa_listener_unotif_response(struct aa_listener *listener, + union apparmor_notif_resp *uresp, + u16 size) +{ + struct aa_knotif *knotif = NULL; + long ret; + + spin_lock(&listener->lock); + knotif = __del_and_hold_user_pending(listener, uresp->base.id); + if (!knotif) { + ret = -ENOENT; + AA_DEBUG(DEBUG_UPCALL, "could not find id %lld", + uresp->base.id); + goto out; + } + if (!response_is_valid(uresp, knotif, size)) { + ret = -EINVAL; + AA_DEBUG(DEBUG_UPCALL, "id %lld: response not valid", knotif->id); + __listener_complete_held_user_pending(listener, knotif); + goto out; + } + + if (uresp->perm.base.ntype == APPARMOR_NOTIF_RESP_PERM) { + knotif_update_from_uresp_perm(knotif, &uresp->perm); + } else if (uresp->perm.base.ntype == APPARMOR_NOTIF_RESP_NAME) { + size = knotif_update_from_uresp_name(knotif, &uresp->name, size); + } else { + AA_DEBUG(DEBUG_UPCALL, "id %lld: unknown response type", knotif->id); + size = -EINVAL; + } + ret = size; + + AA_DEBUG(DEBUG_UPCALL, "id %lld: completing notif", knotif->id); + __listener_complete_held_user_pending(listener, knotif); +out: + spin_unlock(&listener->lock); + + return ret; +} + +/******************** task reading notification to userspace ****************/ + +static long append_bytes(void __user *pos, long remaining, const char *str, + u32 size) +{ + if (size > remaining) + return -EMSGSIZE; + if (copy_to_user(pos, str, size)) + return -EFAULT; + + return size; +} + +/* __POS will be updated + * __FIELD will be updated + * returns __SIZE or error + */ +#define build_append_bytes(__BUF, __POS, __MAX, __STR, __SIZE, __FIELD) \ +({ \ + long __tmp_size; \ + long __tmp_offset = __POS - __BUF; \ + __tmp_size = append_bytes(__POS, __MAX - __tmp_offset, __STR, __SIZE); \ + if (__tmp_size >= 0) { \ + __FIELD = __tmp_offset; \ + __POS += __tmp_size; \ + } \ + (__tmp_size); \ +}) + +/* __POS will be updated + * __FIELD will be updated + * returns __SIZE or error + */ +#define build_append_str(__BUF, __POS, __MAX, __STR, __FIELD) \ +({ \ + long __tmp_size = 0; \ + if (__STR) { \ + __tmp_size = build_append_bytes(__BUF, __POS, __MAX, __STR, \ + strlen(__STR)+1, __FIELD);\ + } \ + (__tmp_size); \ +}) + +/* returns amount written to tpos */ +static long build_tagset(void __user *buf, void __user *hpos, void __user *tpos, + u16 max_size, u32 mask, u32 count, const char *tagstr, + u32 tagsize) +{ + struct apparmor_tags_header_v5 th; + long size; + + th.mask = mask; + th.count = count; + th.tagset = tpos - buf; + size = build_append_bytes(buf, tpos, max_size, tagstr, tagsize, + th.tagset); + if (size < 0) { + AA_DEBUG(DEBUG_TAGS, "build_append_bytes %ld < 0, max %d, tagstr '%s', (long) pos %d, size %d", size, max_size, tagstr, th.tagset, tagsize); + return size; + } + AA_DEBUG(DEBUG_TAGS, " tagset: mask 0x%x, count %d, pos %d, str '%s', strlen %ld, size %ld, return size %ld\n", mask, count, th.tagset, tagstr, strlen(tagstr), (long) tagsize, size); + if (copy_to_user(hpos, &th, sizeof(th))) { + AA_DEBUG(DEBUG_TAGS, "failed: copy_to_user hpos %ld", (long) hpos); + return -EFAULT; + } + return size; +} + +/* build tags for a given tag index */ +static long build_tags(union apparmor_notif_all *unotif, + void __user *buf, void __user *pos, u16 max_size, + struct aa_tags_struct *metatags, u32 mask, u32 permidx) +{ + void __user *hpos, *tpos; + int i, c = 0; + + if (!metatags || permidx == 0) + return pos - buf; + + /* count number of header that need to be laid down */ + for (i = 0; i < metatags->sets.table[permidx]; i++) { + u32 idx = metatags->sets.table[permidx+1+i]; + if (mask & metatags->hdrs.table[idx].mask) { + c++; + AA_DEBUG(DEBUG_TAGS, "matched mask 0x%x, tag[%d].mask 0x%x\n", mask, i, metatags->hdrs.table[idx].mask); + } + } + if (c == 0) { + AA_DEBUG(DEBUG_TAGS, "No matching tag info"); + /* no tags match */ + return pos - buf; + } + + hpos = PTR_ALIGN(pos, 8); + tpos = hpos + (c * sizeof(struct apparmor_tags_header_v5)); //c * 96 + + unotif->file.tags = hpos - buf; + unotif->file.tags_count = c; + AA_DEBUG(DEBUG_TAGS, + "file tags header hpos %ld, tpos %ld tagset_count %d", + hpos - buf, tpos- buf, c); + for (i = 0; i < metatags->sets.table[permidx]; i++) { + u32 idx = metatags->sets.table[permidx+1+i]; + AA_DEBUG(DEBUG_TAGS, + " ... building loop %d, idx %d, mask 0x%x, tags mask 0x%x", + i, idx, mask, metatags->hdrs.table[idx].mask); + if (mask & metatags->hdrs.table[idx].mask) { + struct aa_tags_header *h = &metatags->hdrs.table[idx]; + long size; + + AA_DEBUG(DEBUG_TAGS, + " build_tagset hpos %ld, tpos %ld, index tagset %d tagstr '%s'", + hpos - buf, tpos - buf, h->tags, + metatags->strs.table[h->tags].strs); + size = build_tagset(buf, hpos, tpos, max_size, + h->mask, h->count, + metatags->strs.table[h->tags].strs, + h->size); + if (size < 0) { + AA_DEBUG(DEBUG_TAGS, "build_tagset failed"); + return size; + } + hpos += sizeof(struct apparmor_tags_header_v5); + tpos += size; + } else + AA_DEBUG(DEBUG_TAGS, " no build tagset %d", + mask & metatags->hdrs.table[idx].mask); + } + + AA_DEBUG(DEBUG_TAGS, + " build_tags completed pos %ld, buf %ld, size %ld", + (long) tpos, (long) buf, tpos-buf); + return tpos - buf; +} + +static long build_v35_unotif_common(struct aa_profile *profile, + u16 version, + struct aa_knotif *knotif, + union apparmor_notif_all *unotif, + void __user *buf, u16 max_size) +{ + struct user_namespace *user_ns; + + AA_DEBUG(DEBUG_UPCALL, "building notif max size %d", max_size); + if (sizeof(*unotif) > max_size) + return -EMSGSIZE; + + user_ns = get_user_ns(current->nsproxy->uts_ns->user_ns); + + /* build response */ + unotif->common.len = sizeof(*unotif); + unotif->common.version = version; + unotif->base.ntype = knotif->ntype; + if (knotif->flags & KNOTIF_RESEND) + unotif->base.flags |= UNOTIF_RESENT; + unotif->base.id = knotif->id; + unotif->base.error = knotif->ad->error; + unotif->op.allow = knotif->ad->request & ~knotif->ad->denied; + unotif->op.deny = knotif->ad->denied; + AA_DEBUG(DEBUG_UPCALL, + "notif %lld: sent to user read request 0x%x, denied 0x%x, error %d", + knotif->id, knotif->ad->request, knotif->ad->denied, knotif->ad->error); + + if (knotif->ad->subjtsk != NULL) { + unotif->op.pid = task_pid_vnr(knotif->ad->subjtsk); + unotif->file.subj_uid = from_kuid(user_ns, task_uid(knotif->ad->subjtsk)); + } + unotif->op.class = knotif->ad->class; + unotif->file.obj_uid = from_kuid(user_ns, knotif->ad->fs.ouid); + + put_user_ns(user_ns); + + return sizeof(*unotif); +} + +/* returns total size */ +static long build_v35_unotif_file(struct aa_profile *profile, + struct aa_knotif *knotif, + union apparmor_notif_all *unotif, + void __user *buf, long size, u16 max_size) +{ + void __user *pos = buf + size; + size = build_append_str(buf, pos, max_size, profile->base.hname, + unotif->op.label); + if (size < 0) + return size; + size = build_append_str(buf, pos, max_size, knotif->ad->name, + unotif->file.name); + if (size < 0) + return size; + + if (unotif->common.version == 5) { + struct aa_ruleset *rules = profile->label.rules[0]; + size = build_tags(unotif, buf, pos, max_size, &rules->file->tags, + knotif->ad->request | knotif->ad->denied, + knotif->ad->tags); + if (size < 0) + return size; + pos = buf + size; + } + return pos - buf; +} + +/* copy to userspace: notification data */ +static long build_v35_unotif(u16 version, struct aa_knotif *knotif, + void __user *buf, u16 max_size) +{ + union apparmor_notif_all unotif = { }; + struct aa_profile *profile; + long size; + + profile = labels_profile(knotif->ad->subj_label); + AA_BUG(profile == NULL); + + size = build_v35_unotif_common(profile, version, knotif, &unotif, buf, + max_size); + if (size < 0) + return size; + size = build_v35_unotif_file(profile, knotif, &unotif, buf, size, + max_size); + if (size < 0) + return size; + + /* set size after appending variable length info */ + unotif.common.len = size; + /* now the struct, at the start of user mem */ + if (copy_to_user(buf, &unotif, sizeof(unotif))) + return -EFAULT; + + return size; +} + +// return < 0 == error +// 0 == repeat +// > 0 == built notification successfully +static long build_mediation_unotif(struct aa_listener *listener, + struct aa_knotif *knotif, + void __user *buf, u16 max_size, + u16 version) +{ + long ret; + + switch (knotif->ad->class) { + case AA_CLASS_FILE: + if (listener->version == APPARMOR_NOTIFY_V3 || + listener->version == APPARMOR_NOTIFY_V5) { + ret = build_v35_unotif(listener->version, knotif, + buf, max_size); + if (ret < 0) { + AA_DEBUG(DEBUG_UPCALL, + "id %lld: (error=%ld) failed to copy data to user reading size %ld, maxsize %d", + knotif->id, ret, + sizeof(union apparmor_notif_all), max_size); + goto out; + } + } else { + ret = -EPROTONOSUPPORT; + } + break; + default: + AA_BUG("unknown notification class"); + AA_DEBUG(DEBUG_UPCALL, "id %lld: unknown notification class", knotif->id); + /* skip and move onto the next notification */ + return 0; + } +out: + return ret; +} + +/* Handle the listener reading a notification into userspace */ +// TODO: output multiple messages in one recv +long aa_listener_unotif_recv(struct aa_listener *listener, void __user *buf, + u16 max_size, u16 version) +{ + struct aa_knotif *knotif; + long ret; + + do { + knotif = listener_pop_and_hold_knotif(listener); + if (!knotif) { + return -ENOENT; + } + AA_DEBUG(DEBUG_UPCALL, "id %lld: removed notif from listener queue", + knotif->id); + + ret = build_mediation_unotif(listener, knotif, buf, max_size, + version); + if (ret < 0) { + /* failed - drop notif and return error to reader */ + listener_complete_held_user_pending(listener, knotif); + return ret; + } else if (ret > 0) { + /* else notification copied */ + break; + } + /* unknown notification: drop and try next */ + listener_complete_held_user_pending(listener, knotif); + } while (ret == 0); + + /* success */ + if (knotif->ad->type == AUDIT_APPARMOR_USER) { + AA_DEBUG(DEBUG_UPCALL, "id %lld: adding notif to pending", knotif->id); + listener_append_held_user_pending(listener, knotif); + } else { + /* no one waiting on this notification drop it */ + AA_DEBUG(DEBUG_UPCALL, "id %lld: non-prompt audit notif delivered", knotif->id); + listener_complete_held_user_pending(listener, knotif); + } + + return ret; +} --- linux-nvidia-7.0.0.orig/security/apparmor/path.c +++ linux-nvidia-7.0.0/security/apparmor/path.c @@ -34,7 +34,16 @@ #define CHROOT_NSCONNECT (PATH_CHROOT_REL | PATH_CHROOT_NSCONNECT) -/* If the path is not connected to the expected root, +/** + * aa_disconnect - handle paths not connected + * @path: path to lookup (NOT NULL) + * @buf: buffer to store path to (NOT NULL) + * @name: Returns - pointer for start of path name with in @buf (NOT NULL) + * @flags: profile flags perms controlling path lookup + * @flag_match: flags matching path lookup from enum path_flags + * @disconnected: string to prefix to disconnected paths + * + * If the path is not connected to the expected root, * check if it is a sysctl and handle specially else remove any * leading / that __d_path may have returned. * Unless @@ -45,12 +54,12 @@ * of chroot) and specifically directed to connect paths to * namespace root. */ -static int disconnect(const struct path *path, char *buf, char **name, - int flags, const char *disconnected) +int aa_disconnect(const struct path *path, char *buf, char **name, + int flags, int flags_match, const char *disconnected) { int error = 0; - if (!(flags & PATH_CONNECT_PATH) && + if (!(flags & flags_match) && !(((flags & CHROOT_NSCONNECT) == CHROOT_NSCONNECT) && our_mnt(path->mnt))) { /* disconnected path, don't return pathname starting @@ -110,8 +119,9 @@ error = prepend(name, *name - buf, "/proc", 5); goto out; } else - error = disconnect(path, buf, name, flags, - disconnected); + error = aa_disconnect(path, buf, name, flags, + PATH_CONNECT_PATH, + disconnected); goto out; } @@ -149,7 +159,8 @@ *name = res; if (!connected) - error = disconnect(path, buf, name, flags, disconnected); + error = aa_disconnect(path, buf, name, flags, + PATH_CONNECT_PATH, disconnected); /* Handle two cases: * 1. A deleted dentry && profile is not allowing mediation of deleted @@ -164,14 +175,16 @@ } out: - /* Append "/" to directory paths, except for root "/" which - * already ends in a slash. + /* Append "/" to directory paths and reterminate string, except for + * root "/" which already ends in a slash. */ if (!error && isdir) { bool is_root = (*name)[0] == '/' && (*name)[1] == '\0'; - if (!is_root) + if (!is_root) { buf[aa_g_path_max - 2] = '/'; + buf[aa_g_path_max - 1] = '\0'; + } } return error; --- linux-nvidia-7.0.0.orig/security/apparmor/policy.c +++ linux-nvidia-7.0.0/security/apparmor/policy.c @@ -81,14 +81,20 @@ #include "include/file.h" #include "include/ipc.h" #include "include/match.h" +#include "include/net.h" #include "include/path.h" #include "include/policy.h" #include "include/policy_ns.h" #include "include/policy_unpack.h" #include "include/resource.h" +int aa_skb_packet_mediation = IS_ENABLED(CONFIG_SECURITY_APPARMOR_PACKET_MEDIATION); int unprivileged_userns_apparmor_policy = 1; +int aa_unprivileged_userns_restricted = IS_ENABLED(CONFIG_SECURITY_APPARMOR_RESTRICT_USERNS); +int aa_unprivileged_userns_restricted_force; +int aa_unprivileged_userns_restricted_complain; int aa_unprivileged_unconfined_restricted; +int aa_unprivileged_uring_restricted; const char *const aa_profile_mode_names[] = { "enforce", @@ -232,6 +238,13 @@ aa_label_remove(&profile->label); __aafs_profile_rmdir(profile); __list_remove_profile(profile); + /* rawdata is only ever referenced by fs lookup, that is no + * longer possible here, so put the reference to it. This will + * enable the rawdata to be freed if for some reason the profile + * is pinned and going to live for a while. + */ + aa_put_profile_loaddata(profile->rawdata); + profile->rawdata = NULL; } /** @@ -330,8 +343,17 @@ aa_put_ns(profile->ns); kfree_sensitive(profile->rename); kfree_sensitive(profile->disconnected); + /* + * If disconnected is specified while disconnected_ipc is not, + * disconnected_ipc will be set to disconnected in unpack_profile(). + * Thus, we need to check that the pointers are distinct in order to + * prevent a double free. + */ + if (profile->disconnected_ipc != profile->disconnected) + kfree_sensitive(profile->disconnected_ipc); free_attachment(&profile->attach); + kfree_sensitive(profile->net_compat); /* * at this point there are no tasks that can have a reference @@ -352,6 +374,7 @@ kfree_sensitive(profile->hash); aa_put_profile_loaddata(profile->rawdata); aa_label_destroy(&profile->label); + aa_audit_cache_destroy(&profile->learning_cache); kfree_sensitive(profile); } @@ -402,6 +425,8 @@ profile->label.vec[0] = profile; profile->signal = SIGKILL; + aa_audit_cache_init(&profile->learning_cache); + /* refcount released by caller */ return profile; @@ -1151,6 +1176,8 @@ * @label: label that is attempting to load/replace policy * @mask: permission mask * @udata: serialized data stream (NOT NULL) + * @compressed_profile: The userspace-provided compressed profile. May be NULL + * @compressed_size: If compressed_data is not NULL, the compressed data size * * unpack and replace a profile on the profile list and uses of that profile * by any task creds via invalidating the old version of the profile, which @@ -1160,7 +1187,8 @@ * Returns: size of data consumed else error code on failure. */ ssize_t aa_replace_profiles(struct aa_ns *policy_ns, struct aa_label *label, - u32 mask, struct aa_loaddata *udata) + u32 mask, struct aa_loaddata *udata, + char *compressed_profile, size_t compressed_size) { const char *ns_name = NULL, *info = NULL; struct aa_ns *ns = NULL; @@ -1173,7 +1201,7 @@ op = mask & AA_MAY_REPLACE_POLICY ? OP_PROF_REPL : OP_PROF_LOAD; aa_get_profile_loaddata(udata); /* released below */ - error = aa_unpack(udata, &lh, &ns_name); + error = aa_unpack(udata, &lh, &ns_name, compressed_profile, compressed_size); if (error) goto out; @@ -1330,7 +1358,8 @@ list_del_init(&ent->list); op = (!ent->old && !ent->rename) ? OP_PROF_LOAD : OP_PROF_REPL; - if (ent->old && ent->old->rawdata == ent->new->rawdata && + if (ent->old && ent->old->learning_cache.size == 0 && + ent->old->rawdata == ent->new->rawdata && ent->new->rawdata) { /* dedup actual profile replacement */ audit_policy(label, op, ns_name, ent->new->base.hname, @@ -1371,13 +1400,15 @@ mutex_unlock(&ns->lock); out: + ssize_t udata_sz = udata->size; + aa_put_ns(ns); aa_put_profile_loaddata(udata); kfree(ns_name); if (error) return error; - return udata->size; + return udata_sz; fail_lock: mutex_unlock(&ns->lock); --- linux-nvidia-7.0.0.orig/security/apparmor/policy_compat.c +++ linux-nvidia-7.0.0/security/apparmor/policy_compat.c @@ -107,6 +107,8 @@ perms->allow |= AA_MAY_CHANGE_PROFILE; if (ACCEPT_TABLE(dfa)[state] & 0x40000000) perms->allow |= AA_MAY_ONEXEC; + if (ACCEPT_TABLE(dfa)[state] & 0x10000000) + perms->allow |= AA_CONT_MATCH; } static struct aa_perms compute_fperms_user(struct aa_dfa *dfa, @@ -216,6 +218,8 @@ perms.allow = dfa_user_allow(dfa, state); perms.audit = dfa_user_audit(dfa, state); perms.quiet = dfa_user_quiet(dfa, state); + if (ACCEPT_TABLE(dfa)[state] & 0x10000000) + perms.allow |= AA_CONT_MATCH; /* * This mapping is convulated due to history. --- linux-nvidia-7.0.0.orig/security/apparmor/policy_ns.c +++ linux-nvidia-7.0.0/security/apparmor/policy_ns.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "include/apparmor.h" #include "include/cred.h" @@ -24,6 +25,7 @@ /* kernel label */ struct aa_label *kernel_t; +struct aa_label *unlabeled_t; /* root profile namespace */ struct aa_ns *root_ns; @@ -117,6 +119,8 @@ INIT_LIST_HEAD(&ns->rawdata_list); mutex_init(&ns->lock); init_waitqueue_head(&ns->wait); + spin_lock_init(&ns->listener_lock); + INIT_LIST_HEAD(&ns->listeners); /* released by aa_free_ns() */ ns->unconfined = alloc_unconfined("unconfined"); @@ -372,15 +376,25 @@ return -ENOMEM; kernel_p = alloc_unconfined("kernel_t"); - if (!kernel_p) { - destroy_ns(root_ns); - aa_free_ns(root_ns); - return -ENOMEM; - } + if (!kernel_p) + goto fail; kernel_t = &kernel_p->label; + + kernel_p = alloc_unconfined("unlabeled_t"); + if (!kernel_p) + goto fail; + unlabeled_t = &kernel_p->label; + root_ns->unconfined->ns = aa_get_ns(root_ns); + return 0; +fail: + aa_put_label(kernel_t); + aa_put_label(unlabeled_t); + destroy_ns(root_ns); + aa_free_ns(root_ns); + return -ENOMEM; } /** --- linux-nvidia-7.0.0.orig/security/apparmor/policy_unpack.c +++ linux-nvidia-7.0.0/security/apparmor/policy_unpack.c @@ -25,6 +25,7 @@ #include "include/crypto.h" #include "include/file.h" #include "include/match.h" +#include "include/net.h" #include "include/path.h" #include "include/policy.h" #include "include/policy_unpack.h" @@ -287,6 +288,19 @@ return false; } +VISIBLE_IF_KUNIT bool unpack_u16(struct aa_ext *e, u16 *data, const char *name) +{ + if (aa_unpack_nameX(e, AA_U16, name)) { + if (!aa_inbounds(e, sizeof(u16))) + return 0; + if (data) + *data = le16_to_cpu(get_unaligned((__le16 *) e->pos)); + e->pos += sizeof(u16); + return 1; + } + return 0; +} + VISIBLE_IF_KUNIT bool aa_unpack_u32(struct aa_ext *e, u32 *data, const char *name) { void *pos = e->pos; @@ -1116,9 +1130,10 @@ struct aa_profile *profile = NULL; const char *tmpname, *tmpns = NULL, *name = NULL; const char *info = "failed to unpack profile"; + u16 size = 0; size_t ns_len; struct rhashtable_params params = { 0 }; - char *key = NULL, *disconnected = NULL; + char *key = NULL, *disconnected = NULL, *disconnected_ipc = NULL; struct aa_data *data; int error = -EPROTO; kernel_cap_t tmpcap; @@ -1191,6 +1206,12 @@ (void) aa_unpack_strdup(e, &disconnected, "disconnected"); profile->disconnected = disconnected; + /* disconnected attachment for ipc string is optional + * but it fallbacks to the plain disconnected if not present + */ + (void) aa_unpack_strdup(e, &disconnected_ipc, "disconnected_ipc"); + profile->disconnected_ipc = disconnected_ipc ? disconnected_ipc : disconnected; + /* optional */ (void) aa_unpack_u32(e, &profile->signal, "kill"); if (profile->signal < 1 || profile->signal > MAXMAPPED_SIG) { @@ -1211,6 +1232,8 @@ profile->label.flags |= FLAG_DEBUG1; if (tmp & PACKED_FLAG_DEBUG2) profile->label.flags |= FLAG_DEBUG2; + if (tmp & PACKED_FLAG_INTERRUPTIBLE) + profile->label.flags |= FLAG_INTERRUPTIBLE; if (!aa_unpack_u32(e, &tmp, NULL)) goto fail; if (tmp == PACKED_MODE_COMPLAIN || (e->version & FORCE_COMPLAIN_FLAG)) { @@ -1294,6 +1317,45 @@ goto fail; } + if (aa_unpack_array(e, "net_allowed_af", &size) || + VERSION_LT(e->version, v8)) { + u16 i; + + profile->net_compat = kzalloc(sizeof(struct aa_net_compat), + GFP_KERNEL); + if (!profile->net_compat) { + info = "out of memory"; + goto fail; + } + for (i = 0; i < size; i++) { + /* discard extraneous rules that this kernel will + * never request + */ + if (i >= AF_MAX) { + u16 tmp; + + if (!unpack_u16(e, &tmp, NULL) || + !unpack_u16(e, &tmp, NULL) || + !unpack_u16(e, &tmp, NULL)) + goto fail; + continue; + } + if (!unpack_u16(e, &profile->net_compat->allow[i], NULL)) + goto fail; + if (!unpack_u16(e, &profile->net_compat->audit[i], NULL)) + goto fail; + if (!unpack_u16(e, &profile->net_compat->quiet[i], NULL)) + goto fail; + } + if (size && !aa_unpack_nameX(e, AA_ARRAYEND, NULL)) + goto fail; + if (VERSION_LT(e->version, v7)) { + /* pre v7 policy always allowed these */ + profile->net_compat->allow[AF_UNIX] = 0xffff; + profile->net_compat->allow[AF_NETLINK] = 0xffff; + } + } + if (aa_unpack_nameX(e, AA_STRUCT, "policydb")) { /* generic policy dfa - optional and may be NULL */ info = "failed to unpack policydb"; @@ -1465,6 +1527,7 @@ if (*ns && strcmp(*ns, name)) { audit_iface(NULL, NULL, NULL, "invalid ns change", e, error); + return error; } else if (!*ns) { *ns = kstrdup(name, GFP_KERNEL); if (!*ns) @@ -1715,6 +1778,8 @@ * @udata: user data copied to kmem (NOT NULL) * @lh: list to place unpacked profiles in a aa_repl_ws * @ns: Returns namespace profile is in if specified else NULL (NOT NULL) + * @compressed_data: The userspace-provided compressed data. May be NULL + * @compressed_size: If compressed_data is not NULL, the compressed data size * * Unpack user data and return refcounted allocated profile(s) stored in * @lh in order of discovery, with the list chain stored in base.list @@ -1723,12 +1788,12 @@ * Returns: profile(s) on @lh else error pointer if fails to unpack */ int aa_unpack(struct aa_loaddata *udata, struct list_head *lh, - const char **ns) + const char **ns, char *compressed_data, size_t compressed_size) { struct aa_load_ent *tmp, *ent; struct aa_profile *profile = NULL; char *ns_name = NULL; - int error; + int error = 0; struct aa_ext e = { .start = udata->data, .end = udata->data + udata->size, @@ -1781,10 +1846,23 @@ } if (aa_g_export_binary) { - error = compress_loaddata(udata); + /* Do we have userspace-compressed data? */ + if (compressed_data) { + kvfree(udata->data); + udata->data = compressed_data; + udata->compressed_size = compressed_size; + compressed_data = NULL; /* consumed */ + + } else + error = compress_loaddata(udata); + if (error) goto fail; + } else if (compressed_data) { + kvfree(compressed_data); + compressed_data = NULL; } + return 0; fail_profile: @@ -1792,6 +1870,8 @@ aa_put_profile(profile); fail: + if (compressed_data) + kvfree(compressed_data); list_for_each_entry_safe(ent, tmp, lh, list) { list_del_init(&ent->list); aa_load_ent_free(ent); --- linux-nvidia-7.0.0.orig/security/apparmor/task.c +++ linux-nvidia-7.0.0/security/apparmor/task.c @@ -334,7 +334,14 @@ if (ad->denied & AA_USERNS_CREATE) audit_log_format(ab, " denied=\"userns_create\""); - + if (ad->peer) { + audit_log_format(ab, " target="); + aa_label_xaudit(ab, labels_ns(ad->subj_label), ad->peer, + FLAG_VIEW_SUBNS, GFP_KERNEL); + } else if (ad->ns.target) { + audit_log_format(ab, " target="); + audit_log_untrustedstring(ab, ad->ns.target); + } buffer = aa_get_buffer(false); if (!buffer) return; // OOM @@ -344,29 +351,162 @@ aa_put_buffer(buffer); } -int aa_profile_ns_perm(struct aa_profile *profile, - struct apparmor_audit_data *ad, - u32 request) +/* + * Returns: refcounted label to change to, even if no change + * PTR_ERR on failure + */ +static struct aa_label *ns_x_to_label(struct aa_profile *profile, + u32 xindex, const char **lookupname, + const char **info) +{ + struct aa_label *new = NULL; + u32 xtype = xindex & AA_X_TYPE_MASK; + struct aa_label *stack = NULL; + + /* must be none or table */ + switch (xtype) { + case AA_X_NONE: + /* default not failure */ + *lookupname = NULL; + return NULL; + break; + case AA_X_TABLE: + /* TODO: fix when perm mapping done at unload */ + /* released by caller + * if null for both stack and direct want to try fallback + */ + new = x_table_lookup(profile, xindex, lookupname); + if (!new) { + *info = "failed to find transition profile"; + return ERR_PTR(-ENOMEM); + } + if (**lookupname == '&') { + stack = new; + new = NULL; + } + break; + default: + *info = "invalid profile transition type"; + return ERR_PTR(-EINVAL); + break; + } + + /* stack is true if !new */ + if (!new) { + if (xindex & AA_X_UNCONFINED) { + new = aa_get_newest_label(ns_unconfined(profile->ns)); + *info = "ux fallback"; + } else { + if (xindex & AA_X_INHERIT) { + /* (p|c|n)ix - don't change profile but do + * use the newest version + */ + *info = "ix fallback"; + /* no profile && no error */ + } /* else, stack is implicitly against current */ + new = aa_get_newest_label(&profile->label); + } + } + + if (stack) { + /* base the stack on post domain transition */ + struct aa_label *base = new; + + new = aa_label_merge(base, stack, GFP_KERNEL); + /* null on error */ + aa_put_label(base); + aa_put_label(stack); + if (!new) + return ERR_PTR(-ENOMEM); + } + + /* released by caller */ + return new; +} + +struct aa_label *aa_profile_ns_perm(struct aa_profile *profile, + struct apparmor_audit_data *ad, + u32 request) { + struct aa_ruleset *rules = profile->label.rules[0]; + struct aa_label *new; struct aa_perms perms = { }; - int error = 0; + aa_state_t state; ad->subj_label = &profile->label; ad->request = request; + int error; - if (!profile_unconfined(profile)) { - struct aa_ruleset *rules = profile->label.rules[0]; - aa_state_t state; - - state = RULE_MEDIATES(rules, ad->class); - if (!state) - /* TODO: add flag to complain about unmediated */ - return 0; - perms = *aa_lookup_perms(rules->policy, state); - aa_apply_modes_to_perms(profile, &perms); - error = aa_check_perms(profile, &perms, request, ad, - audit_ns_cb); + + /* TODO: rework unconfined profile/dfa to mediate user ns, then + * we can drop the unconfined test + */ + state = RULE_MEDIATES(rules, ad->class); + if (!state) { + /* TODO: this gets replaced when the default unconfined + * profile dfa gets updated to handle this + */ + if (profile_unconfined(profile) && + profile == profiles_ns(profile)->unconfined) { + if (!aa_unprivileged_userns_restricted || + ns_capable_noaudit(current_user_ns(), + CAP_SYS_ADMIN)) + return aa_get_newest_label(&profile->label); + ad->info = "User namespace creation restricted"; + /* unconfined unprivileged user */ + /* don't just return: allow complain mode to override */ +// hardcode unconfined transition for now + new = aa_label_parse(&profile->label, + "unprivileged_userns", GFP_KERNEL, + true, false); + if (IS_ERR(new)) { + ad->info = "Userns create restricted - failed to find unprivileged_userns profile"; + ad->error = PTR_ERR(new); + ad->ns.target = "unprivileged_userns"; + new = NULL; + perms.deny |= request; + goto hard_coded; + } + ad->info = "Userns create - transitioning profile"; + perms.audit = request; + perms.allow = request; + goto hard_coded; +// once we have special unconfined profile, jump to ns_x_to_label() +// end hardcode + } else if (!aa_unprivileged_userns_restricted_force) { + return aa_get_newest_label(&profile->label); + } + /* continue to mediation */ } - return error; + perms = *aa_lookup_perms(rules->policy, state); + new = ns_x_to_label(profile, perms.xindex, &ad->ns.target, &ad->info); + if (IS_ERR(new)) { + ad->error = PTR_ERR(new); + new = NULL; + perms.deny |= request; + } else if (!new) { + /* no transition - not done in x_to_label so we can track */ + new = aa_get_label(&profile->label); + } else { +hard_coded: + ad->peer = new; + } + if (aa_unprivileged_userns_restricted_complain) + perms.complain = ALL_PERMS_MASK; + // TODO: nnp + // TODO: complain mode support for transitions + + aa_apply_modes_to_perms(profile, &perms); + error = aa_check_perms(profile, &perms, request, ad, audit_ns_cb); + if (error) { + aa_put_label(new); + return ERR_PTR(error); + } else if (!new) { + /* would only happen if complain mode changed error, + * which should not happen. + */ + return ERR_PTR(ad->error); + } + return new; } --- linux-nvidia-7.0.0.orig/security/integrity/digsig.c +++ linux-nvidia-7.0.0/security/integrity/digsig.c @@ -201,7 +201,7 @@ rc = kernel_read_file_from_path(path, 0, &data, INT_MAX, NULL, READING_X509_CERTIFICATE); if (rc < 0) { - pr_err("Unable to open file: %s (%d)", path, rc); + pr_warn("Unable to open file: %s (%d)", path, rc); return rc; } size = rc; --- linux-nvidia-7.0.0.orig/security/integrity/ima/ima_fs.c +++ linux-nvidia-7.0.0/security/integrity/ima/ima_fs.c @@ -305,7 +305,7 @@ rc = kernel_read_file_from_path(path, 0, &data, INT_MAX, NULL, READING_POLICY); if (rc < 0) { - pr_err("Unable to open file: %s (%d)", path, rc); + pr_warn("Unable to open file: %s (%d)", path, rc); return rc; } size = rc; --- linux-nvidia-7.0.0.orig/security/integrity/platform_certs/keyring_handler.c +++ linux-nvidia-7.0.0/security/integrity/platform_certs/keyring_handler.c @@ -40,6 +40,7 @@ static __init void uefi_revocation_list_x509(const char *source, const void *data, size_t len) { + pr_info("Revoking X.509 certificate: %s\n", source); add_key_to_revocation_list(data, len); } --- linux-nvidia-7.0.0.orig/security/integrity/platform_certs/load_uefi.c +++ linux-nvidia-7.0.0/security/integrity/platform_certs/load_uefi.c @@ -74,7 +74,8 @@ return NULL; if (*status != EFI_BUFFER_TOO_SMALL) { - pr_err("Couldn't get size: 0x%lx\n", *status); + pr_err("Couldn't get size: %s (0x%lx)\n", + efi_status_to_str(*status), *status); return NULL; } @@ -85,7 +86,8 @@ *status = efi.get_variable(name, guid, NULL, &lsize, db); if (*status != EFI_SUCCESS) { kfree(db); - pr_err("Error reading db var: 0x%lx\n", *status); + pr_err("Error reading db var: %s (0x%lx)\n", + efi_status_to_str(*status), *status); return NULL; } @@ -94,17 +96,18 @@ } /* - * load_moklist_certs() - Load MokList certs + * load_moklist_certs() - Load Mok(X)List certs + * @load_db: Load MokListRT into db when true; MokListXRT into dbx when false * - * Load the certs contained in the UEFI MokListRT database into the - * platform trusted keyring. + * Load the certs contained in the UEFI MokList(X)RT database into the + * platform trusted/denied keyring. * * This routine checks the EFI MOK config table first. If and only if - * that fails, this routine uses the MokListRT ordinary UEFI variable. + * that fails, this routine uses the MokList(X)RT ordinary UEFI variable. * * Return: Status */ -static int __init load_moklist_certs(void) +static int __init load_moklist_certs(const bool load_db) { struct efi_mokvar_table_entry *mokvar_entry; efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; @@ -112,41 +115,55 @@ unsigned long moksize; efi_status_t status; int rc; + const char *mokvar_name = "MokListRT"; + /* Should be const, but get_cert_list() doesn't have it as const yet */ + efi_char16_t *efivar_name = L"MokListRT"; + const char *parse_mokvar_name = "UEFI:MokListRT (MOKvar table)"; + const char *parse_efivar_name = "UEFI:MokListRT"; + efi_element_handler_t (*get_handler_for_guid)(const efi_guid_t *) = get_handler_for_db; + + if (!load_db) { + mokvar_name = "MokListXRT"; + efivar_name = L"MokListXRT"; + parse_mokvar_name = "UEFI:MokListXRT (MOKvar table)"; + parse_efivar_name = "UEFI:MokListXRT"; + get_handler_for_guid = get_handler_for_dbx; + } /* First try to load certs from the EFI MOKvar config table. * It's not an error if the MOKvar config table doesn't exist * or the MokListRT entry is not found in it. */ - mokvar_entry = efi_mokvar_entry_find("MokListRT"); + mokvar_entry = efi_mokvar_entry_find(mokvar_name); if (mokvar_entry) { - rc = parse_efi_signature_list("UEFI:MokListRT (MOKvar table)", + rc = parse_efi_signature_list(parse_mokvar_name, mokvar_entry->data, mokvar_entry->data_size, - get_handler_for_mok); + get_handler_for_guid); /* All done if that worked. */ if (!rc) return rc; - pr_err("Couldn't parse MokListRT signatures from EFI MOKvar config table: %d\n", - rc); + pr_err("Couldn't parse %s signatures from EFI MOKvar config table: %d\n", + mokvar_name, rc); } /* Get MokListRT. It might not exist, so it isn't an error * if we can't get it. */ - mok = get_cert_list(L"MokListRT", &mok_var, &moksize, &status); + mok = get_cert_list(efivar_name, &mok_var, &moksize, &status); if (mok) { - rc = parse_efi_signature_list("UEFI:MokListRT", - mok, moksize, get_handler_for_mok); + rc = parse_efi_signature_list(parse_efivar_name, + mok, moksize, get_handler_for_guid); kfree(mok); if (rc) - pr_err("Couldn't parse MokListRT signatures: %d\n", rc); + pr_err("Couldn't parse %s signatures: %d\n", mokvar_name, rc); return rc; } if (status == EFI_NOT_FOUND) - pr_debug("MokListRT variable wasn't found\n"); + pr_debug("%s variable wasn't found\n", mokvar_name); else - pr_info("Couldn't get UEFI MokListRT\n"); + pr_info("Couldn't get UEFI %s\n", mokvar_name); return 0; } @@ -160,9 +177,8 @@ static int __init load_uefi_certs(void) { efi_guid_t secure_var = EFI_IMAGE_SECURITY_DATABASE_GUID; - efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; - void *db = NULL, *dbx = NULL, *mokx = NULL; - unsigned long dbsize = 0, dbxsize = 0, mokxsize = 0; + void *db = NULL, *dbx = NULL; + unsigned long dbsize = 0, dbxsize = 0; efi_status_t status; int rc = 0; const struct dmi_system_id *dmi_id; @@ -215,23 +231,15 @@ if (!arch_ima_get_secureboot()) return 0; - mokx = get_cert_list(L"MokListXRT", &mok_var, &mokxsize, &status); - if (!mokx) { - if (status == EFI_NOT_FOUND) - pr_debug("mokx variable wasn't found\n"); - else - pr_info("Couldn't get mokx list\n"); - } else { - rc = parse_efi_signature_list("UEFI:MokListXRT", - mokx, mokxsize, - get_handler_for_dbx); - if (rc) - pr_err("Couldn't parse mokx signatures %d\n", rc); - kfree(mokx); - } + /* Load the MokListXRT certs */ + rc = load_moklist_certs(false); + if (rc) + pr_err("Couldn't parse mokx signatures: %d\n", rc); /* Load the MokListRT certs */ - rc = load_moklist_certs(); + rc = load_moklist_certs(true); + if (rc) + pr_err("Couldn't parse mok signatures: %d\n", rc); return rc; } --- linux-nvidia-7.0.0.orig/security/lockdown/Kconfig +++ linux-nvidia-7.0.0/security/lockdown/Kconfig @@ -16,6 +16,19 @@ subsystem is fully initialised. If enabled, lockdown will unconditionally be called before any other LSMs. +config LOCK_DOWN_IN_SECURE_BOOT + bool "Lock down the kernel in Secure Boot mode" + default n + depends on (EFI || S390 || PPC) && SECURITY_LOCKDOWN_LSM_EARLY + help + Secure Boot provides a mechanism for ensuring that the firmware will + only load signed bootloaders and kernels. Secure boot mode + determination is platform-specific; examples include EFI secure boot + and SIPL on s390. + + Enabling this option results in kernel lockdown being triggered if + booted under secure boot. + choice prompt "Kernel default lockdown mode" default LOCK_DOWN_KERNEL_FORCE_NONE --- linux-nvidia-7.0.0.orig/security/lockdown/lockdown.c +++ linux-nvidia-7.0.0/security/lockdown/lockdown.c @@ -72,6 +72,17 @@ return 0; } +/** + * security_lock_kernel_down() - Put the kernel into lock-down mode. + * + * @where: Where the lock-down is originating from (e.g. command line option) + * @level: The lock-down level (can only increase) + */ +int security_lock_kernel_down(const char *where, enum lockdown_reason level) +{ + return lock_kernel_down(where, level); +} + static struct security_hook_list lockdown_hooks[] __ro_after_init = { LSM_HOOK_INIT(locked_down, lockdown_is_locked_down), }; --- linux-nvidia-7.0.0.orig/security/lsm_init.c +++ linux-nvidia-7.0.0/security/lsm_init.c @@ -314,6 +314,14 @@ lsm_blob_size_update(&blobs->lbs_bpf_map, &blob_sizes.lbs_bpf_map); lsm_blob_size_update(&blobs->lbs_bpf_prog, &blob_sizes.lbs_bpf_prog); lsm_blob_size_update(&blobs->lbs_bpf_token, &blob_sizes.lbs_bpf_token); + + if (blobs->lbs_secmark) { + if (blob_sizes.lbs_secmark) + blobs->lbs_secmark = false; + else + blob_sizes.lbs_secmark = true; + } + } /** --- linux-nvidia-7.0.0.orig/security/security.c +++ linux-nvidia-7.0.0/security/security.c @@ -489,6 +489,7 @@ { return call_int_hook(binder_set_context_mgr, mgr); } +EXPORT_SYMBOL(security_binder_set_context_mgr); /** * security_binder_transaction() - Check if a binder transaction is allowed @@ -504,6 +505,7 @@ { return call_int_hook(binder_transaction, from, to); } +EXPORT_SYMBOL(security_binder_transaction); /** * security_binder_transfer_binder() - Check if a binder transfer is allowed @@ -519,6 +521,7 @@ { return call_int_hook(binder_transfer_binder, from, to); } +EXPORT_SYMBOL(security_binder_transfer_binder); /** * security_binder_transfer_file() - Check if a binder file xfer is allowed @@ -535,6 +538,7 @@ { return call_int_hook(binder_transfer_file, from, to, file); } +EXPORT_SYMBOL(security_binder_transfer_file); /** * security_ptrace_access_check() - Check if tracing is allowed @@ -3875,8 +3879,13 @@ */ int security_secctx_to_secid(const char *secdata, u32 seclen, u32 *secid) { + struct lsm_static_call *scall; + *secid = 0; - return call_int_hook(secctx_to_secid, secdata, seclen, secid); + lsm_for_each_hook(scall, secctx_to_secid) { + return scall->hl->hook.secctx_to_secid(secdata, seclen, secid); + } + return LSM_RET_DEFAULT(secctx_to_secid); } EXPORT_SYMBOL(security_secctx_to_secid); @@ -4337,8 +4346,13 @@ int security_socket_getpeersec_stream(struct socket *sock, sockptr_t optval, sockptr_t optlen, unsigned int len) { - return call_int_hook(socket_getpeersec_stream, sock, optval, optlen, - len); + struct lsm_static_call *scall; + + lsm_for_each_hook(scall, socket_getpeersec_stream) { + return scall->hl->hook.socket_getpeersec_stream(sock, optval, + optlen, len); + } + return LSM_RET_DEFAULT(socket_getpeersec_stream); } /** @@ -4358,7 +4372,13 @@ int security_socket_getpeersec_dgram(struct socket *sock, struct sk_buff *skb, u32 *secid) { - return call_int_hook(socket_getpeersec_dgram, sock, skb, secid); + struct lsm_static_call *scall; + + lsm_for_each_hook(scall, socket_getpeersec_dgram) { + return scall->hl->hook.socket_getpeersec_dgram(sock, skb, + secid); + } + return LSM_RET_DEFAULT(socket_getpeersec_dgram); } EXPORT_SYMBOL(security_socket_getpeersec_dgram); --- linux-nvidia-7.0.0.orig/security/selinux/hooks.c +++ linux-nvidia-7.0.0/security/selinux/hooks.c @@ -166,7 +166,8 @@ */ static int selinux_secmark_enabled(void) { - return (selinux_policycap_alwaysnetwork() || + return selinux_blob_sizes.lbs_secmark && + (selinux_policycap_alwaysnetwork() || atomic_read(&selinux_secmark_refcount)); } @@ -7408,6 +7409,7 @@ .lbs_bpf_map = sizeof(struct bpf_security_struct), .lbs_bpf_prog = sizeof(struct bpf_security_struct), .lbs_bpf_token = sizeof(struct bpf_security_struct), + .lbs_secmark = true, }; /* --- linux-nvidia-7.0.0.orig/security/smack/smack.h +++ linux-nvidia-7.0.0/security/smack/smack.h @@ -400,6 +400,11 @@ return (sip->smk_flags & SMK_INODE_TRANSMUTE) != 0; } +static inline bool smack_secmark(void) +{ + return smack_blob_sizes.lbs_secmark; +} + /* * Present a pointer to the smack label entry in an inode blob. */ --- linux-nvidia-7.0.0.orig/security/smack/smack_lsm.c +++ linux-nvidia-7.0.0/security/smack/smack_lsm.c @@ -4195,7 +4195,7 @@ #ifdef CONFIG_NETWORK_SECMARK static struct smack_known *smack_from_skb(struct sk_buff *skb) { - if (skb == NULL || skb->secmark == 0) + if (!smack_secmark() || skb == NULL || skb->secmark == 0) return NULL; return smack_from_secid(skb->secmark); @@ -5121,6 +5121,7 @@ .lbs_sock = sizeof(struct socket_smack), .lbs_superblock = sizeof(struct superblock_smack), .lbs_xattr_count = SMACK_INODE_INIT_XATTRS, + .lbs_secmark = true, }; static const struct lsm_id smack_lsmid = { --- linux-nvidia-7.0.0.orig/security/smack/smack_netfilter.c +++ linux-nvidia-7.0.0/security/smack/smack_netfilter.c @@ -26,7 +26,7 @@ struct socket_smack *ssp; struct smack_known *skp; - if (sk) { + if (smack_secmark() && sk) { ssp = smack_sock(sk); skp = ssp->smk_out; skb->secmark = skp->smk_secid; @@ -54,12 +54,18 @@ static int __net_init smack_nf_register(struct net *net) { + if (!smack_secmark()) + return 0; + return nf_register_net_hooks(net, smack_nf_ops, ARRAY_SIZE(smack_nf_ops)); } static void __net_exit smack_nf_unregister(struct net *net) { + if (!smack_secmark()) + return; + nf_unregister_net_hooks(net, smack_nf_ops, ARRAY_SIZE(smack_nf_ops)); } @@ -70,7 +76,7 @@ int __init smack_nf_ip_init(void) { - if (smack_enabled == 0) + if (smack_enabled == 0 || !smack_secmark()) return 0; printk(KERN_DEBUG "Smack: Registering netfilter hooks\n"); --- linux-nvidia-7.0.0.orig/sound/soc/codecs/cs42l43.c +++ linux-nvidia-7.0.0/sound/soc/codecs/cs42l43.c @@ -45,12 +45,25 @@ static const struct snd_kcontrol_new cs42l43_##name##_mux = \ SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) +#define CS42L43B_DECL_MUX(name, reg) \ +static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \ + 0, CS42L43_MIXER_SRC_MASK, \ + cs42l43b_mixer_texts, cs42l43b_mixer_values); \ +static const struct snd_kcontrol_new cs42l43_##name##_mux = \ + SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) + #define CS42L43_DECL_MIXER(name, reg) \ CS42L43_DECL_MUX(name##_in1, reg); \ CS42L43_DECL_MUX(name##_in2, reg + 0x4); \ CS42L43_DECL_MUX(name##_in3, reg + 0x8); \ CS42L43_DECL_MUX(name##_in4, reg + 0xC) +#define CS42L43B_DECL_MIXER(name, reg) \ + CS42L43B_DECL_MUX(name##_in1, reg); \ + CS42L43B_DECL_MUX(name##_in2, reg + 0x4); \ + CS42L43B_DECL_MUX(name##_in3, reg + 0x8); \ + CS42L43B_DECL_MUX(name##_in4, reg + 0xC) + #define CS42L43_DAPM_MUX(name_str, name) \ SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux) @@ -99,11 +112,23 @@ { name_str, "EQ1", "EQ" }, \ { name_str, "EQ2", "EQ" } +#define CS42L43B_BASE_ROUTES(name_str) \ + { name_str, "Decimator 5", "Decimator 5" }, \ + { name_str, "Decimator 6", "Decimator 6" }, \ + { name_str, "ISRC1 DEC3", "ISRC1DEC3" }, \ + { name_str, "ISRC1 DEC4", "ISRC1DEC4" }, \ + { name_str, "ISRC2 DEC3", "ISRC2DEC3" }, \ + { name_str, "ISRC2 DEC4", "ISRC2DEC4" } + #define CS42L43_MUX_ROUTES(name_str, widget) \ { widget, NULL, name_str " Input" }, \ { name_str " Input", NULL, "Mixer Core" }, \ CS42L43_BASE_ROUTES(name_str " Input") +#define CS42L43B_MUX_ROUTES(name_str, widget) \ + CS42L43_MUX_ROUTES(name_str, widget), \ + CS42L43B_BASE_ROUTES(name_str " Input") + #define CS42L43_MIXER_ROUTES(name_str, widget) \ { name_str " Mixer", NULL, name_str " Input 1" }, \ { name_str " Mixer", NULL, name_str " Input 2" }, \ @@ -116,6 +141,13 @@ CS42L43_BASE_ROUTES(name_str " Input 3"), \ CS42L43_BASE_ROUTES(name_str " Input 4") +#define CS42L43B_MIXER_ROUTES(name_str, widget) \ + CS42L43_MIXER_ROUTES(name_str, widget), \ + CS42L43B_BASE_ROUTES(name_str " Input 1"), \ + CS42L43B_BASE_ROUTES(name_str " Input 2"), \ + CS42L43B_BASE_ROUTES(name_str " Input 3"), \ + CS42L43B_BASE_ROUTES(name_str " Input 4") + #define CS42L43_MIXER_VOLUMES(name_str, base) \ SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \ CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ @@ -300,6 +332,7 @@ struct snd_soc_component *component = dai->component; struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); struct cs42l43 *cs42l43 = priv->core; + int ret; int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, CS42L43_ASP_MASTER_MODE_MASK); @@ -309,6 +342,14 @@ else priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK; + if (cs42l43->variant_id == CS42L43_DEVID_VAL && (dai->id == 3 || dai->id == 4)) { + ret = snd_pcm_hw_constraint_minmax(substream->runtime, + SNDRV_PCM_HW_PARAM_CHANNELS, + 1, 2); + if (ret < 0) + return ret; + } + return snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &priv->constraint); @@ -590,12 +631,25 @@ "Decimator 2 Switch", "Decimator 3 Switch", "Decimator 4 Switch", + "Decimator 5 Switch", + "Decimator 6 Switch", }; - int i; + int control_size, i; static_assert(ARRAY_SIZE(controls) == ARRAY_SIZE(priv->kctl)); - for (i = 0; i < ARRAY_SIZE(controls); i++) { + switch (priv->core->variant_id) { + case CS42L43_DEVID_VAL: + control_size = ARRAY_SIZE(controls) - 2; // ignore Decimator 5 and 6 + break; + case CS42L43B_DEVID_VAL: + control_size = ARRAY_SIZE(controls); + break; + default: + return -EINVAL; + } + + for (i = 0; i < control_size; i++) { if (priv->kctl[i]) continue; @@ -703,7 +757,7 @@ .capture = { .stream_name = "DP3 Capture", .channels_min = 1, - .channels_max = 2, + .channels_max = 4, .rates = SNDRV_PCM_RATE_KNOT, .formats = CS42L43_SDW_FORMATS, }, @@ -715,7 +769,7 @@ .capture = { .stream_name = "DP4 Capture", .channels_min = 1, - .channels_max = 2, + .channels_max = 4, .rates = SNDRV_PCM_RATE_KNOT, .formats = CS42L43_SDW_FORMATS, }, @@ -808,6 +862,10 @@ CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5, + CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6, + CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); static const char * const cs42l43_hpf_corner_text[] = { "3Hz", "12Hz", "48Hz", "96Hz", @@ -821,6 +879,10 @@ CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5, + CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6, + CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); @@ -839,6 +901,31 @@ static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text); +static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text); + static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0); static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP, @@ -898,6 +985,37 @@ 0x58, 0x59, // EQ1, 2 }; +static const char * const cs42l43b_mixer_texts[] = { + "None", + "Tone Generator 1", "Tone Generator 2", + "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", "Decimator 5", "Decimator 6", + "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6", + "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2", + "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4", + "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4", + "ISRC1 INT1", "ISRC1 INT2", + "ISRC1 DEC1", "ISRC1 DEC2", "ISRC1 DEC3", "ISRC1 DEC4", + "ISRC2 INT1", "ISRC2 INT2", + "ISRC2 DEC1", "ISRC2 DEC2", "ISRC2 DEC3", "ISRC2 DEC4", + "EQ1", "EQ2", +}; + +static const unsigned int cs42l43b_mixer_values[] = { + 0x00, // None + 0x04, 0x05, // Tone Generator 1, 2 + 0x10, 0x11, 0x80, 0x81, 0x12, 0x13, // Decimator 1, 2, 3, 4, 5, 6 + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6 + 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2 + 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4 + 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4 + 0x50, 0x51, // ISRC1 INT1, 2 + 0x52, 0x53, 0x78, 0x79, // ISRC1 DEC1, 2, 3, 4 + 0x54, 0x55, // ISRC2 INT1, 2 + 0x56, 0x57, 0x7A, 0x7B, // ISRC2 DEC1, 2, 3, 4 + 0x58, 0x59, // EQ1, 2 +}; + +/* A variant */ CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT); CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT); CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT); @@ -946,6 +1064,63 @@ CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1); CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1); +/* B variant */ +CS42L43B_DECL_MUX(b_asptx1, CS42L43_ASPTX1_INPUT); +CS42L43B_DECL_MUX(b_asptx2, CS42L43_ASPTX2_INPUT); +CS42L43B_DECL_MUX(b_asptx3, CS42L43_ASPTX3_INPUT); +CS42L43B_DECL_MUX(b_asptx4, CS42L43_ASPTX4_INPUT); +CS42L43B_DECL_MUX(b_asptx5, CS42L43_ASPTX5_INPUT); +CS42L43B_DECL_MUX(b_asptx6, CS42L43_ASPTX6_INPUT); + +CS42L43B_DECL_MUX(b_dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT); +CS42L43B_DECL_MUX(b_dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT); +CS42L43B_DECL_MUX(b_dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT); +CS42L43B_DECL_MUX(b_dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT); +CS42L43B_DECL_MUX(b_dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT); +CS42L43B_DECL_MUX(b_dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT); +CS42L43B_DECL_MUX(b_dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT); +CS42L43B_DECL_MUX(b_dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT); +CS42L43B_DECL_MUX(b_dp3tx3, CS42L43B_SWIRE_DP3_CH3_INPUT); +CS42L43B_DECL_MUX(b_dp3tx4, CS42L43B_SWIRE_DP3_CH4_INPUT); +CS42L43B_DECL_MUX(b_dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT); +CS42L43B_DECL_MUX(b_dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT); +CS42L43B_DECL_MUX(b_dp4tx3, CS42L43B_SWIRE_DP4_CH3_INPUT); +CS42L43B_DECL_MUX(b_dp4tx4, CS42L43B_SWIRE_DP4_CH4_INPUT); + +CS42L43B_DECL_MUX(b_asrcint1, CS42L43_ASRC_INT1_INPUT1); +CS42L43B_DECL_MUX(b_asrcint2, CS42L43_ASRC_INT2_INPUT1); +CS42L43B_DECL_MUX(b_asrcint3, CS42L43_ASRC_INT3_INPUT1); +CS42L43B_DECL_MUX(b_asrcint4, CS42L43_ASRC_INT4_INPUT1); +CS42L43B_DECL_MUX(b_asrcdec1, CS42L43_ASRC_DEC1_INPUT1); +CS42L43B_DECL_MUX(b_asrcdec2, CS42L43_ASRC_DEC2_INPUT1); +CS42L43B_DECL_MUX(b_asrcdec3, CS42L43_ASRC_DEC3_INPUT1); +CS42L43B_DECL_MUX(b_asrcdec4, CS42L43_ASRC_DEC4_INPUT1); + +CS42L43B_DECL_MUX(b_isrc1int1, CS42L43_ISRC1INT1_INPUT1); +CS42L43B_DECL_MUX(b_isrc1int2, CS42L43_ISRC1INT2_INPUT1); +CS42L43B_DECL_MUX(b_isrc1dec1, CS42L43_ISRC1DEC1_INPUT1); +CS42L43B_DECL_MUX(b_isrc1dec2, CS42L43_ISRC1DEC2_INPUT1); +CS42L43B_DECL_MUX(b_isrc1dec3, CS42L43B_ISRC1DEC3_INPUT1); +CS42L43B_DECL_MUX(b_isrc1dec4, CS42L43B_ISRC1DEC4_INPUT1); +CS42L43B_DECL_MUX(b_isrc2int1, CS42L43_ISRC2INT1_INPUT1); +CS42L43B_DECL_MUX(b_isrc2int2, CS42L43_ISRC2INT2_INPUT1); +CS42L43B_DECL_MUX(b_isrc2dec1, CS42L43_ISRC2DEC1_INPUT1); +CS42L43B_DECL_MUX(b_isrc2dec2, CS42L43_ISRC2DEC2_INPUT1); +CS42L43B_DECL_MUX(b_isrc2dec3, CS42L43B_ISRC2DEC3_INPUT1); +CS42L43B_DECL_MUX(b_isrc2dec4, CS42L43B_ISRC2DEC4_INPUT1); + +CS42L43B_DECL_MUX(b_spdif1, CS42L43_SPDIF1_INPUT1); +CS42L43B_DECL_MUX(b_spdif2, CS42L43_SPDIF2_INPUT1); + +CS42L43B_DECL_MIXER(b_eq1, CS42L43_EQ1MIX_INPUT1); +CS42L43B_DECL_MIXER(b_eq2, CS42L43_EQ2MIX_INPUT1); + +CS42L43B_DECL_MIXER(b_amp1, CS42L43_AMP1MIX_INPUT1); +CS42L43B_DECL_MIXER(b_amp2, CS42L43_AMP2MIX_INPUT1); + +CS42L43B_DECL_MIXER(b_amp3, CS42L43_AMP3MIX_INPUT1); +CS42L43B_DECL_MIXER(b_amp4, CS42L43_AMP4MIX_INPUT1); + static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -1174,44 +1349,6 @@ SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner), SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner), - SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, - CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), - SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, - CS42L43_DECIM1_MUTE_SHIFT, 1, 1, - cs42l43_decim_get, cs42l43_dapm_put_volsw), - SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, - CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), - SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, - CS42L43_DECIM2_MUTE_SHIFT, 1, 1, - cs42l43_decim_get, cs42l43_dapm_put_volsw), - SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, - CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), - SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, - CS42L43_DECIM3_MUTE_SHIFT, 1, 1, - cs42l43_decim_get, cs42l43_dapm_put_volsw), - SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, - CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), - SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, - CS42L43_DECIM4_MUTE_SHIFT, 1, 1, - cs42l43_decim_get, cs42l43_dapm_put_volsw), - - SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), - SOC_DOUBLE_R_EXT("Speaker Digital Switch", CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, CS42L43_AMP_MUTE_SHIFT, 1, 1, @@ -1601,35 +1738,81 @@ unsigned int *val; int ret; - switch (w->shift) { - case CS42L43_ADC1_EN_SHIFT: - case CS42L43_PDM1_DIN_L_EN_SHIFT: - reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; - ramp = CS42L43_DECIM1_VD_RAMP_MASK; - mute = CS42L43_DECIM1_MUTE_MASK; - val = &priv->decim_cache[0]; - break; - case CS42L43_ADC2_EN_SHIFT: - case CS42L43_PDM1_DIN_R_EN_SHIFT: - reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; - ramp = CS42L43_DECIM2_VD_RAMP_MASK; - mute = CS42L43_DECIM2_MUTE_MASK; - val = &priv->decim_cache[1]; - break; - case CS42L43_PDM2_DIN_L_EN_SHIFT: - reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; - ramp = CS42L43_DECIM3_VD_RAMP_MASK; - mute = CS42L43_DECIM3_MUTE_MASK; - val = &priv->decim_cache[2]; - break; - case CS42L43_PDM2_DIN_R_EN_SHIFT: - reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; - ramp = CS42L43_DECIM4_VD_RAMP_MASK; - mute = CS42L43_DECIM4_MUTE_MASK; - val = &priv->decim_cache[3]; - break; - default: - dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); + if (cs42l43->variant_id == CS42L43_DEVID_VAL) { + switch (w->shift) { + case CS42L43_ADC1_EN_SHIFT: + case CS42L43_PDM1_DIN_L_EN_SHIFT: + reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; + ramp = CS42L43_DECIM1_VD_RAMP_MASK; + mute = CS42L43_DECIM1_MUTE_MASK; + val = &priv->decim_cache[0]; + break; + case CS42L43_ADC2_EN_SHIFT: + case CS42L43_PDM1_DIN_R_EN_SHIFT: + reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; + ramp = CS42L43_DECIM2_VD_RAMP_MASK; + mute = CS42L43_DECIM2_MUTE_MASK; + val = &priv->decim_cache[1]; + break; + case CS42L43_PDM2_DIN_L_EN_SHIFT: + reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; + ramp = CS42L43_DECIM3_VD_RAMP_MASK; + mute = CS42L43_DECIM3_MUTE_MASK; + val = &priv->decim_cache[2]; + break; + case CS42L43_PDM2_DIN_R_EN_SHIFT: + reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; + ramp = CS42L43_DECIM4_VD_RAMP_MASK; + mute = CS42L43_DECIM4_MUTE_MASK; + val = &priv->decim_cache[3]; + break; + default: + dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); + return -EINVAL; + } + } else if (cs42l43->variant_id == CS42L43B_DEVID_VAL) { + switch (w->shift) { + case CS42L43_ADC1_EN_SHIFT: + reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2; + ramp = CS42L43_DECIM1_VD_RAMP_MASK; + mute = CS42L43_DECIM1_MUTE_MASK; + val = &priv->decim_cache[0]; + break; + case CS42L43_ADC2_EN_SHIFT: + reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2; + ramp = CS42L43_DECIM2_VD_RAMP_MASK; + mute = CS42L43_DECIM2_MUTE_MASK; + val = &priv->decim_cache[1]; + break; + case CS42L43_PDM1_DIN_L_EN_SHIFT: + reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4; + ramp = CS42L43_DECIM3_VD_RAMP_MASK; + mute = CS42L43_DECIM3_MUTE_MASK; + val = &priv->decim_cache[2]; + break; + case CS42L43_PDM1_DIN_R_EN_SHIFT: + reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4; + ramp = CS42L43_DECIM4_VD_RAMP_MASK; + mute = CS42L43_DECIM4_MUTE_MASK; + val = &priv->decim_cache[3]; + break; + case CS42L43_PDM2_DIN_L_EN_SHIFT: + reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6; + ramp = CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_MASK; + mute = CS42L43B_DECIM5_MUTE_MASK; + val = &priv->decim_cache[4]; + break; + case CS42L43_PDM2_DIN_R_EN_SHIFT: + reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6; + ramp = CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_MASK; + mute = CS42L43B_DECIM6_MUTE_MASK; + val = &priv->decim_cache[5]; + break; + default: + dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); + return -EINVAL; + } + } else { return -EINVAL; } @@ -1722,11 +1905,6 @@ 0, NULL, 0, cs42l43_mic_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), - SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, - &cs42l43_dec_mode_ctl[0]), - SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, - &cs42l43_dec_mode_ctl[1]), - SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0), @@ -1871,53 +2049,6 @@ SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT, 0, NULL, 0), - CS42L43_DAPM_MUX("ASPTX1", asptx1), - CS42L43_DAPM_MUX("ASPTX2", asptx2), - CS42L43_DAPM_MUX("ASPTX3", asptx3), - CS42L43_DAPM_MUX("ASPTX4", asptx4), - CS42L43_DAPM_MUX("ASPTX5", asptx5), - CS42L43_DAPM_MUX("ASPTX6", asptx6), - - CS42L43_DAPM_MUX("DP1TX1", dp1tx1), - CS42L43_DAPM_MUX("DP1TX2", dp1tx2), - CS42L43_DAPM_MUX("DP1TX3", dp1tx3), - CS42L43_DAPM_MUX("DP1TX4", dp1tx4), - CS42L43_DAPM_MUX("DP2TX1", dp2tx1), - CS42L43_DAPM_MUX("DP2TX2", dp2tx2), - CS42L43_DAPM_MUX("DP3TX1", dp3tx1), - CS42L43_DAPM_MUX("DP3TX2", dp3tx2), - CS42L43_DAPM_MUX("DP4TX1", dp4tx1), - CS42L43_DAPM_MUX("DP4TX2", dp4tx2), - - CS42L43_DAPM_MUX("ASRC INT1", asrcint1), - CS42L43_DAPM_MUX("ASRC INT2", asrcint2), - CS42L43_DAPM_MUX("ASRC INT3", asrcint3), - CS42L43_DAPM_MUX("ASRC INT4", asrcint4), - CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), - CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), - CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), - CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), - - CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), - CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), - CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), - CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), - CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), - CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), - CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), - CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), - - CS42L43_DAPM_MUX("SPDIF1", spdif1), - CS42L43_DAPM_MUX("SPDIF2", spdif2), - - CS42L43_DAPM_MIXER("EQ1", eq1), - CS42L43_DAPM_MIXER("EQ2", eq2), - - CS42L43_DAPM_MIXER("Speaker L", amp1), - CS42L43_DAPM_MIXER("Speaker R", amp2), - - CS42L43_DAPM_MIXER("Headphone L", amp3), - CS42L43_DAPM_MIXER("Headphone R", amp4), }; static const struct snd_soc_dapm_route cs42l43_routes[] = { @@ -1963,16 +2094,6 @@ { "PDM2L", NULL, "PDM2_DIN" }, { "PDM2R", NULL, "PDM2_DIN" }, - { "Decimator 1 Mode", "PDM", "PDM1L" }, - { "Decimator 1 Mode", "ADC", "ADC1" }, - { "Decimator 2 Mode", "PDM", "PDM1R" }, - { "Decimator 2 Mode", "ADC", "ADC2" }, - - { "Decimator 1", NULL, "Decimator 1 Mode" }, - { "Decimator 2", NULL, "Decimator 2 Mode" }, - { "Decimator 3", NULL, "PDM2L" }, - { "Decimator 4", NULL, "PDM2R" }, - { "ASP Capture", NULL, "ASPTX1" }, { "ASP Capture", NULL, "ASPTX2" }, { "ASP Capture", NULL, "ASPTX3" }, @@ -2060,6 +2181,261 @@ { "ASRC_DEC4", NULL, "ASRC_DEC" }, { "EQ", NULL, "EQ Clock" }, +}; + +static const struct snd_kcontrol_new cs42l43_a_controls[] = { + SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + + SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM1_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM2_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM3_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM4_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), +}; + +static const struct snd_kcontrol_new cs42l43_b_controls[] = { + SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM1_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, + CS42L43_DECIM2_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM3_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, + CS42L43_DECIM4_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 5 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM5_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 5 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM5_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + SOC_SINGLE_TLV("Decimator 6 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM6_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), + SOC_SINGLE_EXT("Decimator 6 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, + CS42L43B_DECIM6_MUTE_SHIFT, 1, 1, + cs42l43_decim_get, cs42l43_dapm_put_volsw), + + SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43b_dec1_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43b_dec1_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43b_dec2_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43b_dec2_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43b_dec3_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43b_dec3_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43b_dec4_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43b_dec4_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 5 Ramp Up", cs42l43b_dec5_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 5 Ramp Down", cs42l43b_dec5_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 6 Ramp Up", cs42l43b_dec6_ramp_up, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + SOC_ENUM_EXT("Decimator 6 Ramp Down", cs42l43b_dec6_ramp_down, + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), + + SOC_SINGLE("Decimator 5 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5, + CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), + SOC_SINGLE("Decimator 6 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6, + CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), + + SOC_ENUM("Decimator 5 WNF Corner Frequency", cs42l43b_dec5_wnf_corner), + SOC_ENUM("Decimator 6 WNF Corner Frequency", cs42l43b_dec6_wnf_corner), + + SOC_SINGLE("Decimator 5 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5, + CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), + SOC_SINGLE("Decimator 6 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6, + CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), + + SOC_ENUM("Decimator 5 HPF Corner Frequency", cs42l43b_dec5_hpf_corner), + SOC_ENUM("Decimator 6 HPF Corner Frequency", cs42l43b_dec6_hpf_corner), +}; + +static const struct snd_soc_dapm_widget cs42l43_a_widgets[] = { + SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, + &cs42l43_dec_mode_ctl[0]), + SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, + &cs42l43_dec_mode_ctl[1]), + CS42L43_DAPM_MUX("ASPTX1", asptx1), + CS42L43_DAPM_MUX("ASPTX2", asptx2), + CS42L43_DAPM_MUX("ASPTX3", asptx3), + CS42L43_DAPM_MUX("ASPTX4", asptx4), + CS42L43_DAPM_MUX("ASPTX5", asptx5), + CS42L43_DAPM_MUX("ASPTX6", asptx6), + + CS42L43_DAPM_MUX("DP1TX1", dp1tx1), + CS42L43_DAPM_MUX("DP1TX2", dp1tx2), + CS42L43_DAPM_MUX("DP1TX3", dp1tx3), + CS42L43_DAPM_MUX("DP1TX4", dp1tx4), + CS42L43_DAPM_MUX("DP2TX1", dp2tx1), + CS42L43_DAPM_MUX("DP2TX2", dp2tx2), + CS42L43_DAPM_MUX("DP3TX1", dp3tx1), + CS42L43_DAPM_MUX("DP3TX2", dp3tx2), + CS42L43_DAPM_MUX("DP4TX1", dp4tx1), + CS42L43_DAPM_MUX("DP4TX2", dp4tx2), + + CS42L43_DAPM_MUX("ASRC INT1", asrcint1), + CS42L43_DAPM_MUX("ASRC INT2", asrcint2), + CS42L43_DAPM_MUX("ASRC INT3", asrcint3), + CS42L43_DAPM_MUX("ASRC INT4", asrcint4), + CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), + CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), + CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), + CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), + + CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), + CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), + CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), + CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), + CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), + CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), + CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), + CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), + + CS42L43_DAPM_MUX("SPDIF1", spdif1), + CS42L43_DAPM_MUX("SPDIF2", spdif2), + + CS42L43_DAPM_MIXER("EQ1", eq1), + CS42L43_DAPM_MIXER("EQ2", eq2), + + CS42L43_DAPM_MIXER("Speaker L", amp1), + CS42L43_DAPM_MIXER("Speaker R", amp2), + + CS42L43_DAPM_MIXER("Headphone L", amp3), + CS42L43_DAPM_MIXER("Headphone R", amp4), +}; + +static const struct snd_soc_dapm_widget cs42l43_b_widgets[] = { + SND_SOC_DAPM_AIF_OUT("DP3TX3", NULL, 2, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("DP3TX4", NULL, 3, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("DP4TX3", NULL, 2, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("DP4TX4", NULL, 3, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_PGA("Decimator 5", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Decimator 6", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_PGA("ISRC1DEC3", CS42L43_ISRC1_CTRL, + CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("ISRC1DEC4", CS42L43_ISRC1_CTRL, + CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("ISRC2DEC3", CS42L43_ISRC2_CTRL, + CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("ISRC2DEC4", CS42L43_ISRC2_CTRL, + CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0), + + CS42L43_DAPM_MUX("ASPTX1", b_asptx1), + CS42L43_DAPM_MUX("ASPTX2", b_asptx2), + CS42L43_DAPM_MUX("ASPTX3", b_asptx3), + CS42L43_DAPM_MUX("ASPTX4", b_asptx4), + CS42L43_DAPM_MUX("ASPTX5", b_asptx5), + CS42L43_DAPM_MUX("ASPTX6", b_asptx6), + + CS42L43_DAPM_MUX("DP1TX1", b_dp1tx1), + CS42L43_DAPM_MUX("DP1TX2", b_dp1tx2), + CS42L43_DAPM_MUX("DP1TX3", b_dp1tx3), + CS42L43_DAPM_MUX("DP1TX4", b_dp1tx4), + CS42L43_DAPM_MUX("DP2TX1", b_dp2tx1), + CS42L43_DAPM_MUX("DP2TX2", b_dp2tx2), + CS42L43_DAPM_MUX("DP3TX1", b_dp3tx1), + CS42L43_DAPM_MUX("DP3TX2", b_dp3tx2), + CS42L43_DAPM_MUX("DP3TX3", b_dp3tx3), + CS42L43_DAPM_MUX("DP3TX4", b_dp3tx4), + CS42L43_DAPM_MUX("DP4TX1", b_dp4tx1), + CS42L43_DAPM_MUX("DP4TX2", b_dp4tx2), + CS42L43_DAPM_MUX("DP4TX3", b_dp4tx3), + CS42L43_DAPM_MUX("DP4TX4", b_dp4tx4), + + CS42L43_DAPM_MUX("ASRC INT1", b_asrcint1), + CS42L43_DAPM_MUX("ASRC INT2", b_asrcint2), + CS42L43_DAPM_MUX("ASRC INT3", b_asrcint3), + CS42L43_DAPM_MUX("ASRC INT4", b_asrcint4), + CS42L43_DAPM_MUX("ASRC DEC1", b_asrcdec1), + CS42L43_DAPM_MUX("ASRC DEC2", b_asrcdec2), + CS42L43_DAPM_MUX("ASRC DEC3", b_asrcdec3), + CS42L43_DAPM_MUX("ASRC DEC4", b_asrcdec4), + + CS42L43_DAPM_MUX("ISRC1INT1", b_isrc1int1), + CS42L43_DAPM_MUX("ISRC1INT2", b_isrc1int2), + CS42L43_DAPM_MUX("ISRC1DEC1", b_isrc1dec1), + CS42L43_DAPM_MUX("ISRC1DEC2", b_isrc1dec2), + CS42L43_DAPM_MUX("ISRC1DEC3", b_isrc1dec3), + CS42L43_DAPM_MUX("ISRC1DEC4", b_isrc1dec4), + CS42L43_DAPM_MUX("ISRC2INT1", b_isrc2int1), + CS42L43_DAPM_MUX("ISRC2INT2", b_isrc2int2), + CS42L43_DAPM_MUX("ISRC2DEC1", b_isrc2dec1), + CS42L43_DAPM_MUX("ISRC2DEC2", b_isrc2dec2), + CS42L43_DAPM_MUX("ISRC2DEC3", b_isrc2dec3), + CS42L43_DAPM_MUX("ISRC2DEC4", b_isrc2dec4), + + CS42L43_DAPM_MUX("SPDIF1", b_spdif1), + CS42L43_DAPM_MUX("SPDIF2", b_spdif2), + + CS42L43_DAPM_MIXER("EQ1", b_eq1), + CS42L43_DAPM_MIXER("EQ2", b_eq2), + + CS42L43_DAPM_MIXER("Speaker L", b_amp1), + CS42L43_DAPM_MIXER("Speaker R", b_amp2), + + CS42L43_DAPM_MIXER("Headphone L", b_amp3), + CS42L43_DAPM_MIXER("Headphone R", b_amp4), +}; + +static const struct snd_soc_dapm_route cs42l43_a_routes[] = { + { "Decimator 1 Mode", "PDM", "PDM1L" }, + { "Decimator 1 Mode", "ADC", "ADC1" }, + { "Decimator 2 Mode", "PDM", "PDM1R" }, + { "Decimator 2 Mode", "ADC", "ADC2" }, + + { "Decimator 1", NULL, "Decimator 1 Mode" }, + { "Decimator 2", NULL, "Decimator 2 Mode" }, + { "Decimator 3", NULL, "PDM2L" }, + { "Decimator 4", NULL, "PDM2R" }, CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"), CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"), @@ -2110,6 +2486,81 @@ CS42L43_MIXER_ROUTES("Headphone R", "HP"), }; +static const struct snd_soc_dapm_route cs42l43_b_routes[] = { + { "Decimator 1", NULL, "ADC1" }, + { "Decimator 2", NULL, "ADC2" }, + { "Decimator 3", NULL, "PDM1L" }, + { "Decimator 4", NULL, "PDM1R" }, + { "Decimator 5", NULL, "PDM2L" }, + { "Decimator 6", NULL, "PDM2R" }, + + { "DP3 Capture", NULL, "DP3TX3" }, + { "DP3 Capture", NULL, "DP3TX4" }, + { "DP4 Capture", NULL, "DP4TX3" }, + { "DP4 Capture", NULL, "DP4TX4" }, + + { "ISRC1DEC3", NULL, "ISRC1" }, + { "ISRC1DEC4", NULL, "ISRC1" }, + { "ISRC2DEC3", NULL, "ISRC2" }, + { "ISRC2DEC4", NULL, "ISRC2" }, + + CS42L43B_MUX_ROUTES("ASPTX1", "ASPTX1"), + CS42L43B_MUX_ROUTES("ASPTX2", "ASPTX2"), + CS42L43B_MUX_ROUTES("ASPTX3", "ASPTX3"), + CS42L43B_MUX_ROUTES("ASPTX4", "ASPTX4"), + CS42L43B_MUX_ROUTES("ASPTX5", "ASPTX5"), + CS42L43B_MUX_ROUTES("ASPTX6", "ASPTX6"), + + CS42L43B_MUX_ROUTES("DP1TX1", "DP1TX1"), + CS42L43B_MUX_ROUTES("DP1TX2", "DP1TX2"), + CS42L43B_MUX_ROUTES("DP1TX3", "DP1TX3"), + CS42L43B_MUX_ROUTES("DP1TX4", "DP1TX4"), + CS42L43B_MUX_ROUTES("DP2TX1", "DP2TX1"), + CS42L43B_MUX_ROUTES("DP2TX2", "DP2TX2"), + CS42L43B_MUX_ROUTES("DP3TX1", "DP3TX1"), + CS42L43B_MUX_ROUTES("DP3TX2", "DP3TX2"), + CS42L43B_MUX_ROUTES("DP3TX3", "DP3TX3"), + CS42L43B_MUX_ROUTES("DP3TX4", "DP3TX4"), + CS42L43B_MUX_ROUTES("DP4TX1", "DP4TX1"), + CS42L43B_MUX_ROUTES("DP4TX2", "DP4TX2"), + CS42L43B_MUX_ROUTES("DP4TX3", "DP4TX3"), + CS42L43B_MUX_ROUTES("DP4TX4", "DP4TX4"), + + CS42L43B_MUX_ROUTES("ASRC INT1", "ASRC_INT1"), + CS42L43B_MUX_ROUTES("ASRC INT2", "ASRC_INT2"), + CS42L43B_MUX_ROUTES("ASRC INT3", "ASRC_INT3"), + CS42L43B_MUX_ROUTES("ASRC INT4", "ASRC_INT4"), + CS42L43B_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"), + CS42L43B_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"), + CS42L43B_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"), + CS42L43B_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"), + + CS42L43B_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + CS42L43B_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + CS42L43B_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + CS42L43B_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + CS42L43B_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + CS42L43B_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + CS42L43B_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + CS42L43B_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + CS42L43B_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + CS42L43B_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + CS42L43B_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), + CS42L43B_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), + + CS42L43B_MUX_ROUTES("SPDIF1", "SPDIF"), + CS42L43B_MUX_ROUTES("SPDIF2", "SPDIF"), + + CS42L43B_MIXER_ROUTES("EQ1", "EQ"), + CS42L43B_MIXER_ROUTES("EQ2", "EQ"), + + CS42L43B_MIXER_ROUTES("Speaker L", "AMP1"), + CS42L43B_MIXER_ROUTES("Speaker R", "AMP2"), + + CS42L43B_MIXER_ROUTES("Headphone L", "HP"), + CS42L43B_MIXER_ROUTES("Headphone R", "HP"), +}; + static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id, int src, unsigned int freq, int dir) { @@ -2126,8 +2577,14 @@ static int cs42l43_component_probe(struct snd_soc_component *component) { + struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); + unsigned int num_controls, num_widgets, num_routes; + const struct snd_soc_dapm_widget *widgets; + const struct snd_kcontrol_new *controls; + const struct snd_soc_dapm_route *routes; struct cs42l43 *cs42l43 = priv->core; + int ret; snd_soc_component_init_regmap(component, cs42l43->regmap); @@ -2139,6 +2596,39 @@ priv->component = component; priv->constraint = cs42l43_constraint; + switch (cs42l43->variant_id) { + case CS42L43_DEVID_VAL: + controls = cs42l43_a_controls; + num_controls = ARRAY_SIZE(cs42l43_a_controls); + widgets = cs42l43_a_widgets; + num_widgets = ARRAY_SIZE(cs42l43_a_widgets); + routes = cs42l43_a_routes; + num_routes = ARRAY_SIZE(cs42l43_a_routes); + break; + case CS42L43B_DEVID_VAL: + controls = cs42l43_b_controls; + num_controls = ARRAY_SIZE(cs42l43_b_controls); + widgets = cs42l43_b_widgets; + num_widgets = ARRAY_SIZE(cs42l43_b_widgets); + routes = cs42l43_b_routes; + num_routes = ARRAY_SIZE(cs42l43_b_routes); + break; + default: + return -EINVAL; + } + + ret = snd_soc_add_component_controls(component, controls, num_controls); + if (ret) + return ret; + + ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets); + if (ret) + return ret; + + ret = snd_soc_dapm_add_routes(dapm, routes, num_routes); + if (ret) + return ret; + return 0; } --- linux-nvidia-7.0.0.orig/sound/soc/codecs/cs42l43.h +++ linux-nvidia-7.0.0/sound/soc/codecs/cs42l43.h @@ -61,7 +61,7 @@ unsigned int refclk_freq; struct completion pll_ready; - unsigned int decim_cache[4]; + unsigned int decim_cache[6]; unsigned int adc_ena; unsigned int hp_ena; @@ -103,7 +103,7 @@ bool hp_ilimited; int hp_ilimit_count; - struct snd_kcontrol *kctl[5]; + struct snd_kcontrol *kctl[7]; }; #if IS_REACHABLE(CONFIG_SND_SOC_CS42L43_SDW) --- linux-nvidia-7.0.0.orig/sound/soc/sdca/sdca_asoc.c +++ linux-nvidia-7.0.0/sound/soc/sdca/sdca_asoc.c @@ -51,6 +51,25 @@ return control->has_fixed || control->mode == SDCA_ACCESS_MODE_RO; } +static int ge_count_routes(struct sdca_entity *entity) +{ + int count = 0; + int i, j; + + for (i = 0; i < entity->ge.num_modes; i++) { + struct sdca_ge_mode *mode = &entity->ge.modes[i]; + + for (j = 0; j < mode->num_controls; j++) { + struct sdca_ge_control *affected = &mode->controls[j]; + + if (affected->sel != SDCA_CTL_SU_SELECTOR || affected->val) + count++; + } + } + + return count; +} + /** * sdca_asoc_count_component - count the various component parts * @dev: Pointer to the device against which allocations will be done. @@ -74,6 +93,7 @@ int *num_widgets, int *num_routes, int *num_controls, int *num_dais) { + struct sdca_control *control; int i, j; *num_widgets = function->num_entities - 1; @@ -83,6 +103,7 @@ for (i = 0; i < function->num_entities - 1; i++) { struct sdca_entity *entity = &function->entities[i]; + bool skip_primary_routes = false; /* Add supply/DAI widget connections */ switch (entity->type) { @@ -96,6 +117,17 @@ case SDCA_ENTITY_TYPE_PDE: *num_routes += entity->pde.num_managed; break; + case SDCA_ENTITY_TYPE_GE: + *num_routes += ge_count_routes(entity); + skip_primary_routes = true; + break; + case SDCA_ENTITY_TYPE_SU: + control = sdca_selector_find_control(dev, entity, SDCA_CTL_SU_SELECTOR); + if (!control) + return -EINVAL; + + skip_primary_routes = (control->layers == SDCA_ACCESS_LAYER_DEVICE); + break; default: break; } @@ -104,7 +136,8 @@ (*num_routes)++; /* Add primary entity connections from DisCo */ - *num_routes += entity->num_sources; + if (!skip_primary_routes) + *num_routes += entity->num_sources; for (j = 0; j < entity->num_controls; j++) { if (exported_control(entity, &entity->controls[j])) @@ -442,7 +475,6 @@ struct snd_soc_dapm_route **route) { struct sdca_control_range *range; - int num_routes = 0; int i, j; if (!entity->group) { @@ -478,11 +510,6 @@ return -EINVAL; } - if (++num_routes > entity->num_sources) { - dev_err(dev, "%s: too many input routes\n", entity->label); - return -EINVAL; - } - term = sdca_range_search(range, SDCA_SELECTED_MODE_INDEX, mode->val, SDCA_SELECTED_MODE_TERM_TYPE); if (!term) { @@ -778,6 +805,70 @@ } EXPORT_SYMBOL_NS(sdca_asoc_populate_dapm, "SND_SOC_SDCA"); +static int q78_write(struct snd_soc_component *component, + struct soc_mixer_control *mc, + unsigned int reg, const int val) +{ + unsigned int mask = GENMASK(mc->sign_bit, 0); + unsigned int reg_val; + + if (val < 0 || val > mc->max - mc->min) + return -EINVAL; + + reg_val = (val + mc->min) * mc->shift; + + return snd_soc_component_update_bits(component, reg, mask, reg_val); +} + +static int q78_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + int ret; + + ret = q78_write(component, mc, mc->reg, ucontrol->value.integer.value[0]); + if (ret < 0) + return ret; + + if (snd_soc_volsw_is_stereo(mc)) { + int err; /* Don't drop change flag */ + + err = q78_write(component, mc, mc->rreg, ucontrol->value.integer.value[1]); + if (err) + return err; + } + + return ret; +} + +static int q78_read(struct snd_soc_component *component, + struct soc_mixer_control *mc, unsigned int reg) +{ + unsigned int reg_val; + int val; + + reg_val = snd_soc_component_read(component, reg); + + val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min; + + return val & GENMASK(mc->sign_bit, 0); +} + +static int q78_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + + ucontrol->value.integer.value[0] = q78_read(component, mc, mc->reg); + + if (snd_soc_volsw_is_stereo(mc)) + ucontrol->value.integer.value[1] = q78_read(component, mc, mc->rreg); + + return 0; +} + static int control_limit_kctl(struct device *dev, struct sdca_entity *entity, struct sdca_control *control, @@ -814,16 +905,15 @@ tlv[2] = (min * 100) >> 8; tlv[3] = (max * 100) >> 8; - step = (step * 100) >> 8; - - mc->min = ((int)tlv[2] / step); - mc->max = ((int)tlv[3] / step); + mc->min = min / step; + mc->max = max / step; mc->shift = step; mc->sign_bit = 15; - mc->sdca_q78 = 1; kctl->tlv.p = tlv; kctl->access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ; + kctl->get = q78_get_volsw; + kctl->put = q78_put_volsw; return 0; } --- linux-nvidia-7.0.0.orig/sound/soc/sdca/sdca_fdl.c +++ linux-nvidia-7.0.0/sound/soc/sdca/sdca_fdl.c @@ -46,11 +46,6 @@ if (ret) // Allowed for function reset to not be implemented return 0; - if (!function->reset_max_delay) { - dev_err(dev, "No reset delay specified in DisCo\n"); - return -EINVAL; - } - /* * Poll up to 16 times but no more than once per ms, these are just * arbitrarily selected values, so may be fine tuned in future. --- linux-nvidia-7.0.0.orig/sound/soc/sdca/sdca_functions.c +++ linux-nvidia-7.0.0/sound/soc/sdca/sdca_functions.c @@ -2176,8 +2176,12 @@ ret = fwnode_property_read_u32(function_desc->node, "mipi-sdca-function-reset-max-delay", &tmp); - if (!ret) + if (ret || tmp == 0) { + dev_dbg(dev, "reset delay missing, defaulting to 100mS\n"); + function->reset_max_delay = 100000; + } else { function->reset_max_delay = tmp; + } dev_dbg(dev, "%pfwP: name %s busy delay %dus reset delay %dus\n", function->desc->node, function->desc->name, --- linux-nvidia-7.0.0.orig/sound/soc/sdw_utils/soc_sdw_utils.c +++ linux-nvidia-7.0.0/sound/soc/sdw_utils/soc_sdw_utils.c @@ -724,12 +724,66 @@ .dai_num = 4, }, { + .part_id = 0x2A3B, + .name_prefix = "cs42l43", + .count_sidecar = asoc_sdw_bridge_cs35l56_count_sidecar, + .add_sidecar = asoc_sdw_bridge_cs35l56_add_sidecar, + .dais = { + { + .direction = {true, false}, + .codec_name = "cs42l43-codec", + .dai_name = "cs42l43-dp5", + .dai_type = SOC_SDW_DAI_TYPE_JACK, + .dailink = {SOC_SDW_JACK_OUT_DAI_ID, SOC_SDW_UNUSED_DAI_ID}, + .rtd_init = asoc_sdw_cs42l43_hs_rtd_init, + .controls = generic_jack_controls, + .num_controls = ARRAY_SIZE(generic_jack_controls), + .widgets = generic_jack_widgets, + .num_widgets = ARRAY_SIZE(generic_jack_widgets), + }, + { + .direction = {false, true}, + .codec_name = "cs42l43-codec", + .dai_name = "cs42l43-dp1", + .dai_type = SOC_SDW_DAI_TYPE_MIC, + .dailink = {SOC_SDW_UNUSED_DAI_ID, SOC_SDW_DMIC_DAI_ID}, + .rtd_init = asoc_sdw_cs42l43_dmic_rtd_init, + .widgets = generic_dmic_widgets, + .num_widgets = ARRAY_SIZE(generic_dmic_widgets), + .quirk = SOC_SDW_CODEC_MIC, + .quirk_exclude = true, + }, + { + .direction = {false, true}, + .codec_name = "cs42l43-codec", + .dai_name = "cs42l43-dp2", + .dai_type = SOC_SDW_DAI_TYPE_JACK, + .dailink = {SOC_SDW_UNUSED_DAI_ID, SOC_SDW_JACK_IN_DAI_ID}, + }, + { + .direction = {true, false}, + .codec_name = "cs42l43-codec", + .dai_name = "cs42l43-dp6", + .dai_type = SOC_SDW_DAI_TYPE_AMP, + .dailink = {SOC_SDW_AMP_OUT_DAI_ID, SOC_SDW_UNUSED_DAI_ID}, + .init = asoc_sdw_cs42l43_spk_init, + .rtd_init = asoc_sdw_cs42l43_spk_rtd_init, + .controls = generic_spk_controls, + .num_controls = ARRAY_SIZE(generic_spk_controls), + .widgets = generic_spk_widgets, + .num_widgets = ARRAY_SIZE(generic_spk_widgets), + .quirk = SOC_SDW_CODEC_SPKR | SOC_SDW_SIDECAR_AMPS, + }, + }, + .dai_num = 4, + }, + { .part_id = 0x4245, .name_prefix = "cs42l45", .dais = { { .direction = {true, false}, - .codec_name = "snd_soc_sdca.UAJ.1", + .codec_name = "snd_soc_sdca.UAJ", .dai_name = "IT 41", .dai_type = SOC_SDW_DAI_TYPE_JACK, .dailink = {SOC_SDW_JACK_OUT_DAI_ID, SOC_SDW_UNUSED_DAI_ID}, @@ -745,7 +799,7 @@ }, { .direction = {false, true}, - .codec_name = "snd_soc_sdca.UAJ.1", + .codec_name = "snd_soc_sdca.UAJ", .dai_name = "OT 36", .dai_type = SOC_SDW_DAI_TYPE_JACK, .dailink = {SOC_SDW_UNUSED_DAI_ID, SOC_SDW_JACK_IN_DAI_ID}, @@ -754,7 +808,7 @@ .dai_num = 3, .auxs = { { - .codec_name = "snd_soc_sdca.HID.2", + .codec_name = "snd_soc_sdca.HID", }, }, .aux_num = 1, @@ -1215,8 +1269,18 @@ const struct snd_soc_acpi_link_adr *adr_link, int adr_index) { - if (dai_info->codec_name) - return devm_kstrdup(dev, dai_info->codec_name, GFP_KERNEL); + if (dai_info->codec_name) { + struct snd_soc_component *component; + + component = snd_soc_lookup_component_by_name(dai_info->codec_name); + if (component) { + dev_dbg(dev, "%s found component %s for codec_name %s\n", + __func__, component->name, dai_info->codec_name); + return devm_kstrdup(dev, component->name, GFP_KERNEL); + } else { + return devm_kstrdup(dev, dai_info->codec_name, GFP_KERNEL); + } + } return _asoc_sdw_get_codec_name(dev, adr_link, adr_index); } @@ -1528,7 +1592,17 @@ return -EINVAL; for (j = 0; j < codec_info->aux_num; j++) { - soc_aux->dlc.name = codec_info->auxs[j].codec_name; + struct snd_soc_component *component; + + component = snd_soc_lookup_component_by_name(codec_info->auxs[j].codec_name); + if (component) { + dev_dbg(dev, "%s found component %s for aux name %s\n", + __func__, component->name, + codec_info->auxs[j].codec_name); + soc_aux->dlc.name = component->name; + } else { + soc_aux->dlc.name = codec_info->auxs[j].codec_name; + } soc_aux++; } --- linux-nvidia-7.0.0.orig/sound/soc/soc-core.c +++ linux-nvidia-7.0.0/sound/soc/soc-core.c @@ -404,6 +404,19 @@ } EXPORT_SYMBOL_GPL(snd_soc_lookup_component); +struct snd_soc_component *snd_soc_lookup_component_by_name(const char *component_name) +{ + struct snd_soc_component *component; + + guard(mutex)(&client_mutex); + for_each_component(component) + if (strstr(component->name, component_name)) + return component; + + return NULL; +} +EXPORT_SYMBOL_GPL(snd_soc_lookup_component_by_name); + struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link) --- linux-nvidia-7.0.0.orig/sound/soc/soc-ops.c +++ linux-nvidia-7.0.0/sound/soc/soc-ops.c @@ -110,37 +110,6 @@ } EXPORT_SYMBOL_GPL(snd_soc_put_enum_double); -static int sdca_soc_q78_reg_to_ctl(struct soc_mixer_control *mc, unsigned int reg_val, - unsigned int mask, unsigned int shift, int max, - bool sx) -{ - int val = reg_val; - - if (WARN_ON(!mc->shift)) - return -EINVAL; - - val = sign_extend32(val, mc->sign_bit); - val = (((val * 100) >> 8) / (int)mc->shift); - val -= mc->min; - - return val & mask; -} - -static unsigned int sdca_soc_q78_ctl_to_reg(struct soc_mixer_control *mc, int val, - unsigned int mask, unsigned int shift, int max) -{ - unsigned int ret_val; - int reg_val; - - if (WARN_ON(!mc->shift)) - return -EINVAL; - - reg_val = val + mc->min; - ret_val = (int)((reg_val * mc->shift) << 8) / 100; - - return ret_val & mask; -} - static int soc_mixer_reg_to_ctl(struct soc_mixer_control *mc, unsigned int reg_val, unsigned int mask, unsigned int shift, int max, bool sx) @@ -234,27 +203,19 @@ struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc, int mask, int max) { - unsigned int (*ctl_to_reg)(struct soc_mixer_control *, int, unsigned int, unsigned int, int); struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); unsigned int val1, val_mask; unsigned int val2 = 0; bool double_r = false; int ret; - if (mc->sdca_q78) { - ctl_to_reg = sdca_soc_q78_ctl_to_reg; - val_mask = mask; - } else { - ctl_to_reg = soc_mixer_ctl_to_reg; - val_mask = mask << mc->shift; - } - ret = soc_mixer_valid_ctl(mc, ucontrol->value.integer.value[0], max); if (ret) return ret; - val1 = ctl_to_reg(mc, ucontrol->value.integer.value[0], + val1 = soc_mixer_ctl_to_reg(mc, ucontrol->value.integer.value[0], mask, mc->shift, max); + val_mask = mask << mc->shift; if (snd_soc_volsw_is_stereo(mc)) { ret = soc_mixer_valid_ctl(mc, ucontrol->value.integer.value[1], max); @@ -262,10 +223,14 @@ return ret; if (mc->reg == mc->rreg) { - val1 |= ctl_to_reg(mc, ucontrol->value.integer.value[1], mask, mc->rshift, max); + val1 |= soc_mixer_ctl_to_reg(mc, + ucontrol->value.integer.value[1], + mask, mc->rshift, max); val_mask |= mask << mc->rshift; } else { - val2 = ctl_to_reg(mc, ucontrol->value.integer.value[1], mask, mc->shift, max); + val2 = soc_mixer_ctl_to_reg(mc, + ucontrol->value.integer.value[1], + mask, mc->shift, max); double_r = true; } } @@ -289,28 +254,21 @@ struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc, int mask, int max, bool sx) { - int (*reg_to_ctl)(struct soc_mixer_control *, unsigned int, unsigned int, - unsigned int, int, bool); struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); unsigned int reg_val; int val; - if (mc->sdca_q78) - reg_to_ctl = sdca_soc_q78_reg_to_ctl; - else - reg_to_ctl = soc_mixer_reg_to_ctl; - reg_val = snd_soc_component_read(component, mc->reg); - val = reg_to_ctl(mc, reg_val, mask, mc->shift, max, sx); + val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->shift, max, sx); ucontrol->value.integer.value[0] = val; if (snd_soc_volsw_is_stereo(mc)) { if (mc->reg == mc->rreg) { - val = reg_to_ctl(mc, reg_val, mask, mc->rshift, max, sx); + val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->rshift, max, sx); } else { reg_val = snd_soc_component_read(component, mc->rreg); - val = reg_to_ctl(mc, reg_val, mask, mc->shift, max, sx); + val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->shift, max, sx); } ucontrol->value.integer.value[1] = val; --- linux-nvidia-7.0.0.orig/tools/hv/hv_kvp_daemon.8 +++ linux-nvidia-7.0.0/tools/hv/hv_kvp_daemon.8 @@ -0,0 +1,26 @@ +.\" This page Copyright (C) 2012 Andy Whitcroft +.\" Distributed under the GPL v2 or later. +.TH HV_KVP_DAEMON 8 +.SH NAME +hv_kvp_daemon \- Hyper-V Key Value Pair daemon +.SH SYNOPSIS +.ft B +.B hv_kvp_daemon +.br +.SH DESCRIPTION +\fBhv_kvp_daemon\fP +is the userspace component of the Hyper-V key value pair functionality, +communicating via a netlink socket with the kernel HV-KVP driver. +This pairing allows the Hyper-V host to pass configuration information +(such as IP addresses) to the guest and allows the host to obtain guest +version information. + +.SH FILES +.ta +.nf +/var/opt/hyperv/.kvp_pool_* +.fi + +.SH AUTHORS +.nf +Written by K. Y. Srinivasan --- linux-nvidia-7.0.0.orig/tools/hv/lsvmbus.8 +++ linux-nvidia-7.0.0/tools/hv/lsvmbus.8 @@ -0,0 +1,23 @@ +.\" This page Copyright (C) 2016 Andy Whitcroft +.\" Distributed under the GPL v2 or later. +.TH LSVMBUS 8 +.SH NAME +lsvmbus \- List Hyper-V VMBus devices +.SH SYNOPSIS +.ft B +.B lsvmbus [-vv] +.br +.SH DESCRIPTION +\fBlsvmbus\fP +displays devices attached to the Hyper-V VMBus. +.SH OPTIONS +.\" +.TP +.B -v +With -v more information is printed including the VMBus Rel_ID, class ID, +Rel_ID, and which channel is bound to which virtual processor. Use -vv +for additional detail including the Device_ID and the sysfs path. +.\" +.SH AUTHORS +.nf +Written by Dexuan Cui --- linux-nvidia-7.0.0.orig/tools/objtool/check.c +++ linux-nvidia-7.0.0/tools/objtool/check.c @@ -4318,7 +4318,10 @@ } } - return warnings; + /* RETPOLINE is an optional security safety feature, make it + * fatal to ensure no new code is introduced that fails + * RETPOLINE */ + return -warnings; } static bool is_kasan_insn(struct instruction *insn) @@ -4863,7 +4866,9 @@ } } - return warnings; + /* SLS is an optional security safety feature, make it fatal + * to ensure no new code is introduced that fails SLS */ + return -warnings; } static int validate_reachable_instructions(struct objtool_file *file) --- linux-nvidia-7.0.0.orig/tools/perf/Makefile.config +++ linux-nvidia-7.0.0/tools/perf/Makefile.config @@ -912,6 +912,11 @@ endif endif +ifdef HAVE_NO_LIBBFD + feature-libbfd := 0 + $(info libbfd overidden OFF) +else + ifdef BUILD_NONDISTRO # call all detections now so we get correct status in VF output $(call feature_check,libbfd) @@ -948,6 +953,8 @@ endif endif +endif + ifndef NO_LIBLLVM $(call feature_check,llvm-perf) ifeq ($(feature-llvm-perf), 1) @@ -1170,7 +1177,7 @@ RUST_TARGET_FLAGS_m68k := m68k-unknown-linux-gnu RUST_TARGET_FLAGS_mips := mipsel-unknown-linux-gnu RUST_TARGET_FLAGS_powerpc := powerpc64le-unknown-linux-gnu - RUST_TARGET_FLAGS_riscv := riscv64gc-unknown-linux-gnu + RUST_TARGET_FLAGS_riscv := riscv64a23-unknown-linux-gnu RUST_TARGET_FLAGS_s390 := s390x-unknown-linux-gnu RUST_TARGET_FLAGS_x86 := x86_64-unknown-linux-gnu RUST_TARGET_FLAGS_x86_64 := x86_64-unknown-linux-gnu --- linux-nvidia-7.0.0.orig/tools/testing/selftests/ftrace/test.d/trigger/trigger-trace-marker-snapshot.tc +++ linux-nvidia-7.0.0/tools/testing/selftests/ftrace/test.d/trigger/trigger-trace-marker-snapshot.tc @@ -14,12 +14,12 @@ x=$2 cat $file | while read line; do - comment=`echo $line | sed -e 's/^#//'` + comment=`echo "$line" | sed -e 's/^#//'` if [ "$line" != "$comment" ]; then continue fi echo "testing $line for >$x<" - match=`echo $line | sed -e "s/>$x$x$x< in it" fi --- linux-nvidia-7.0.0.orig/tools/testing/selftests/kselftest/runner.sh +++ linux-nvidia-7.0.0/tools/testing/selftests/kselftest/runner.sh @@ -36,7 +36,7 @@ tap_timeout() { # Make sure tests will time out if utility is available. - if [ -x /usr/bin/timeout ] ; then + if [ -x /usr/bin/timeout ] && [ $kselftest_timeout -gt 0 ] ; then /usr/bin/timeout --foreground "$kselftest_timeout" \ /usr/bin/timeout "$kselftest_timeout" $1 else --- linux-nvidia-7.0.0.orig/tools/testing/selftests/memory-hotplug/settings +++ linux-nvidia-7.0.0/tools/testing/selftests/memory-hotplug/settings @@ -0,0 +1 @@ +timeout=600 --- linux-nvidia-7.0.0.orig/tools/testing/selftests/net/gre_gso.sh +++ linux-nvidia-7.0.0/tools/testing/selftests/net/gre_gso.sh @@ -120,12 +120,12 @@ PID=$! while ! $NS_EXEC ss -ltn | grep -q $port; do ((i++)); sleep 0.01; done - cat $TMPFILE | timeout 1 socat -u STDIN TCP:$addr:$port + cat $TMPFILE | timeout 3 socat -u STDIN TCP:$addr:$port log_test $? 0 "$name - copy file w/ TSO" ethtool -K veth0 tso off - cat $TMPFILE | timeout 1 socat -u STDIN TCP:$addr:$port + cat $TMPFILE | timeout 3 socat -u STDIN TCP:$addr:$port log_test $? 0 "$name - copy file w/ GSO" ethtool -K veth0 tso on --- linux-nvidia-7.0.0.orig/tools/testing/selftests/net/settings +++ linux-nvidia-7.0.0/tools/testing/selftests/net/settings @@ -1 +1 @@ -timeout=3600 +timeout=0 --- linux-nvidia-7.0.0.orig/tools/testing/selftests/net/socket.c +++ linux-nvidia-7.0.0/tools/testing/selftests/net/socket.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "kselftest.h" @@ -26,7 +27,10 @@ }; static struct socket_testcase tests[] = { - { AF_MAX, 0, 0, -EAFNOSUPPORT, 0 }, + /* libc might have a smaller value of AF_MAX than the kernel + * actually supports, so use INT_MAX instead. + */ + { INT_MAX, 0, 0, -EAFNOSUPPORT, 0 }, { AF_INET, SOCK_STREAM, IPPROTO_TCP, 0, 1 }, { AF_INET, SOCK_DGRAM, IPPROTO_TCP, -EPROTONOSUPPORT, 1 }, { AF_INET, SOCK_DGRAM, IPPROTO_UDP, 0, 1 }, --- linux-nvidia-7.0.0.orig/tools/testing/selftests/net/tls.c +++ linux-nvidia-7.0.0/tools/testing/selftests/net/tls.c @@ -467,64 +467,6 @@ close(filefd); } -static void chunked_sendfile(struct __test_metadata *_metadata, - struct _test_data_tls *self, - uint16_t chunk_size, - uint16_t extra_payload_size) -{ - char buf[TLS_PAYLOAD_MAX_LEN]; - uint16_t test_payload_size; - int size = 0; - int ret; - char filename[] = "/tmp/mytemp.XXXXXX"; - int fd = mkstemp(filename); - off_t offset = 0; - - unlink(filename); - ASSERT_GE(fd, 0); - EXPECT_GE(chunk_size, 1); - test_payload_size = chunk_size + extra_payload_size; - ASSERT_GE(TLS_PAYLOAD_MAX_LEN, test_payload_size); - memset(buf, 1, test_payload_size); - size = write(fd, buf, test_payload_size); - EXPECT_EQ(size, test_payload_size); - fsync(fd); - - while (size > 0) { - ret = sendfile(self->fd, fd, &offset, chunk_size); - EXPECT_GE(ret, 0); - size -= ret; - } - - EXPECT_EQ(recv(self->cfd, buf, test_payload_size, MSG_WAITALL), - test_payload_size); - - close(fd); -} - -TEST_F(tls, multi_chunk_sendfile) -{ - chunked_sendfile(_metadata, self, 4096, 4096); - chunked_sendfile(_metadata, self, 4096, 0); - chunked_sendfile(_metadata, self, 4096, 1); - chunked_sendfile(_metadata, self, 4096, 2048); - chunked_sendfile(_metadata, self, 8192, 2048); - chunked_sendfile(_metadata, self, 4096, 8192); - chunked_sendfile(_metadata, self, 8192, 4096); - chunked_sendfile(_metadata, self, 12288, 1024); - chunked_sendfile(_metadata, self, 12288, 2000); - chunked_sendfile(_metadata, self, 15360, 100); - chunked_sendfile(_metadata, self, 15360, 300); - chunked_sendfile(_metadata, self, 1, 4096); - chunked_sendfile(_metadata, self, 2048, 4096); - chunked_sendfile(_metadata, self, 2048, 8192); - chunked_sendfile(_metadata, self, 4096, 8192); - chunked_sendfile(_metadata, self, 1024, 12288); - chunked_sendfile(_metadata, self, 2000, 12288); - chunked_sendfile(_metadata, self, 100, 15360); - chunked_sendfile(_metadata, self, 300, 15360); -} - TEST_F(tls, recv_max) { unsigned int send_len = TLS_PAYLOAD_MAX_LEN; --- linux-nvidia-7.0.0.orig/tools/testing/selftests/powerpc/ptrace/Makefile +++ linux-nvidia-7.0.0/tools/testing/selftests/powerpc/ptrace/Makefile @@ -34,7 +34,7 @@ $(TESTS_64): CFLAGS += -m64 $(TM_TESTS): CFLAGS += -I../tm -mhtm -CFLAGS += $(KHDR_INCLUDES) -fno-pie +CFLAGS += $(KHDR_INCLUDES) -fno-pie -Wno-error=deprecated $(OUTPUT)/ptrace-gpr: ptrace-gpr.S $(OUTPUT)/ptrace-perf-hwbreak: ptrace-perf-asm.S --- linux-nvidia-7.0.0.orig/tools/testing/selftests/seccomp/settings +++ linux-nvidia-7.0.0/tools/testing/selftests/seccomp/settings @@ -1 +1 @@ -timeout=180 +timeout=300 --- linux-nvidia-7.0.0.orig/tools/testing/selftests/timers/rtcpie.c +++ linux-nvidia-7.0.0/tools/testing/selftests/timers/rtcpie.c @@ -111,11 +111,11 @@ timersub(&end, &start, &diff); if (diff.tv_sec > 0 || diff.tv_usec > ((1000000L / tmp) * 1.10)) { - fprintf(stderr, "\nPIE delta error: %ld.%06ld should be close to 0.%06ld\n", + fprintf(stderr, "\nUbuntu Testing Force Pass LP #1814234: PIE delta error: %ld.%06ld should be close to 0.%06ld\n", diff.tv_sec, diff.tv_usec, (1000000L / tmp)); fflush(stdout); - exit(-1); + break; // LP: #1814234 } fprintf(stderr, " %d",i); --- linux-nvidia-7.0.0.orig/tools/usb/usbip/configure.ac +++ linux-nvidia-7.0.0/tools/usb/usbip/configure.ac @@ -18,7 +18,7 @@ # Silent build for automake >= 1.11 m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])]) -AC_SUBST([EXTRA_CFLAGS], ["-Wall -Werror -Wextra -std=gnu99"]) +AC_SUBST([EXTRA_CFLAGS], ["-Wall -Werror -Wextra -Wno-address-of-packed-member -std=gnu99"]) # Checks for programs. AC_PROG_CC --- linux-nvidia-7.0.0.orig/ubuntu/Kconfig +++ linux-nvidia-7.0.0/ubuntu/Kconfig @@ -0,0 +1,28 @@ +menu "Ubuntu Supplied Third-Party Device Drivers" + + +config UBUNTU_ODM_DRIVERS + bool "Ubuntu ODM supplied drivers" + help + Turn on support for Ubuntu ODM supplied drivers + +# +# NOTE: to allow drivers to be added and removed without causing merge +# collisions you should add new entries in the middle of the six lines +# of ## at the bottom of the list. Always add three lines of ## above +# your new entry and maintain the six lines below. +# + +## +## +## +source "ubuntu/ubuntu-host/Kconfig" +## +## +## +source "ubuntu/igh-ecat/Kconfig" +## +## +## + +endmenu --- linux-nvidia-7.0.0.orig/ubuntu/Makefile +++ linux-nvidia-7.0.0/ubuntu/Makefile @@ -0,0 +1,22 @@ +# +# Makefile for the Linux kernel ubuntu supplied third-party device drivers. +# + +# +# NOTE: to allow drivers to be added and removed without causing merge +# collisions you should add new entries in the middle of the six lines +# of ## at the bottom of the list. Always add three lines of ## above +# your new entry and maintain the six lines below. +# + +## +## +## +obj-$(CONFIG_UBUNTU_HOST) += ubuntu-host/ +## +## +## +obj-$(CONFIG_IGH_ECAT) += igh-ecat/ +## +## +## --- linux-nvidia-7.0.0.orig/ubuntu/hio/Makefile +++ linux-nvidia-7.0.0/ubuntu/hio/Makefile @@ -0,0 +1,69 @@ +ifneq ($(KERNELRELEASE),) +# hio-y := hio_main.o +# obj-$(CONFIG_HIO_DRIVER) += hio.o + obj-m += hio.o +else + +KVER= +ifeq ($(KVER),) + KVER=$(shell uname -r) +endif + +PDIR= +ifeq ($(PDIR),) + PDIR=extra +endif + +PREFIX= + +MODDIR=/lib/modules/$(KVER)/$(PDIR)/hio/ +MOD=hio.ko + +ifeq ($(KVER),2.6.32-300.3.1.el6uek.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),2.6.32-220.el6.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),2.6.32-358.el6.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),2.6.32-358.23.2.el6.x86_64) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),3.0.58-0.6.6-xen) + FLAGS += -DSSD_QUEUE_PBIO +endif +ifeq ($(KVER),3.2.0-4-amd64) + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-400.209.1.el5uek) #Oracle Linux Server release 5.10 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-400.215.10.el5uek) #Oracle Linux Server release 5.11 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-200.24.1.el6uek.x86_64) #Oracle Linux Server release 6.3 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif +ifeq ($(KVER),2.6.39-400.17.1.el6uek.x86_64) #Oracle Linux Server release 6.4 + FLAGS += -DSSD_BIOVEC_PHYS_MERGEABLE_FIXED +endif + + +KERNELDIR ?= /lib/modules/$(KVER)/build +PWD := $(shell pwd) + +default: + $(MAKE) -C $(KERNELDIR) M=$(PWD) EXTRA_CFLAGS="$(FLAGS)" modules +clean: + rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions Module.* + +install: default + mkdir -p $(PREFIX)/$(MODDIR) + install -m 444 $(MOD) $(PREFIX)/$(MODDIR) + @if [ "$(PREFIX)" = "" ]; then /sbin/depmod -a ;\ + else echo " *** Run 'depmod -a' to update the module database.";\ + fi +endif + --- linux-nvidia-7.0.0.orig/ubuntu/hio/hio.c +++ linux-nvidia-7.0.0/ubuntu/hio/hio.c @@ -0,0 +1,12527 @@ +/* +* Huawei SSD device driver +* Copyright (c) 2016, Huawei Technologies Co., Ltd. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef LINUX_VERSION_CODE +#include +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* HDIO_GETGEO */ +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) +#include +#endif +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,2,0)) +#include +#include +#else +#include +#endif +#include +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)) +#include +#endif + +/* driver */ +#define MODULE_NAME "hio" +#define DRIVER_VERSION "2.1.0.23" +#define DRIVER_VERSION_LEN 16 + +#define SSD_FW_MIN 0x1 + +#define SSD_DEV_NAME MODULE_NAME +#define SSD_DEV_NAME_LEN 16 +#define SSD_CDEV_NAME "c"SSD_DEV_NAME +#define SSD_SDEV_NAME "s"SSD_DEV_NAME + + +#define SSD_CMAJOR 0 +#define SSD_MAJOR 0 +#define SSD_MAJOR_SL 0 +#define SSD_MINORS 16 + +#define SSD_MAX_DEV 702 +#define SSD_ALPHABET_NUM 26 + +#define hio_info(f, arg...) printk(KERN_INFO MODULE_NAME"info: " f , ## arg) +#define hio_note(f, arg...) printk(KERN_NOTICE MODULE_NAME"note: " f , ## arg) +#define hio_warn(f, arg...) printk(KERN_WARNING MODULE_NAME"warn: " f , ## arg) +#define hio_err(f, arg...) printk(KERN_ERR MODULE_NAME"err: " f , ## arg) + +/* slave port */ +#define SSD_SLAVE_PORT_DEVID 0x000a + +/* int mode */ + +/* 2.6.9 msi affinity bug, should turn msi & msi-x off */ +//#define SSD_MSI +#define SSD_ESCAPE_IRQ + +//#define SSD_MSIX +#ifndef MODULE +#define SSD_MSIX +#endif +#define SSD_MSIX_VEC 8 +#ifdef SSD_MSIX +#undef SSD_MSI +//#undef SSD_ESCAPE_IRQ +#define SSD_MSIX_AFFINITY_FORCE +#endif + +#define SSD_TRIM + +/* Over temperature protect */ +#define SSD_OT_PROTECT + +#ifdef SSD_QUEUE_PBIO +#define BIO_SSD_PBIO 20 +#endif + +/* debug */ +//#define SSD_DEBUG_ERR + +/* cmd timer */ +#define SSD_CMD_TIMEOUT (60*HZ) + +/* i2c & smbus */ +#define SSD_SPI_TIMEOUT (5*HZ) +#define SSD_I2C_TIMEOUT (5*HZ) + +#define SSD_I2C_MAX_DATA (127) +#define SSD_SMBUS_BLOCK_MAX (32) +#define SSD_SMBUS_DATA_MAX (SSD_SMBUS_BLOCK_MAX + 2) + +/* wait for init */ +#define SSD_INIT_WAIT (1000) //1s +#define SSD_CONTROLLER_WAIT (20*1000/SSD_INIT_WAIT) //20s +#define SSD_INIT_MAX_WAIT (500*1000/SSD_INIT_WAIT) //500s +#define SSD_INIT_MAX_WAIT_V3_2 (1400*1000/SSD_INIT_WAIT) //1400s +#define SSD_RAM_INIT_MAX_WAIT (10*1000/SSD_INIT_WAIT) //10s +#define SSD_CH_INFO_MAX_WAIT (10*1000/SSD_INIT_WAIT) //10s + +/* blkdev busy wait */ +#define SSD_DEV_BUSY_WAIT 1000 //ms +#define SSD_DEV_BUSY_MAX_WAIT (8*1000/SSD_DEV_BUSY_WAIT) //8s + +/* smbus retry */ +#define SSD_SMBUS_RETRY_INTERVAL (5) //ms +#define SSD_SMBUS_RETRY_MAX (1000/SSD_SMBUS_RETRY_INTERVAL) + +#define SSD_BM_RETRY_MAX 7 + +/* bm routine interval */ +#define SSD_BM_CAP_LEARNING_DELAY (10*60*1000) + +/* routine interval */ +#define SSD_ROUTINE_INTERVAL (10*1000) //10s +#define SSD_HWMON_ROUTINE_TICK (60*1000/SSD_ROUTINE_INTERVAL) +#define SSD_CAPMON_ROUTINE_TICK ((3600*1000/SSD_ROUTINE_INTERVAL)*24*30) +#define SSD_CAPMON2_ROUTINE_TICK (10*60*1000/SSD_ROUTINE_INTERVAL) //fault recover + +/* dma align */ +#define SSD_DMA_ALIGN (16) + +/* some hw defalut */ +#define SSD_LOG_MAX_SZ 4096 + +#define SSD_NAND_OOB_SZ 1024 +#define SSD_NAND_ID_SZ 8 +#define SSD_NAND_ID_BUFF_SZ 1024 +#define SSD_NAND_MAX_CE 2 + +#define SSD_BBT_RESERVED 8 + +#define SSD_ECC_MAX_FLIP (64+1) + +#define SSD_RAM_ALIGN 16 + + +#define SSD_RELOAD_FLAG 0x3333CCCC +#define SSD_RELOAD_FW 0xAA5555AA +#define SSD_RESET_NOINIT 0xAA5555AA +#define SSD_RESET 0x55AAAA55 +#define SSD_RESET_FULL 0x5A +//#define SSD_RESET_WAIT 1000 //1s +//#define SSD_RESET_MAX_WAIT (200*1000/SSD_RESET_WAIT) //200s + + +/* reverion 1 */ +#define SSD_PROTOCOL_V1 0x0 + +#define SSD_ROM_SIZE (16*1024*1024) +#define SSD_ROM_BLK_SIZE (256*1024) +#define SSD_ROM_PAGE_SIZE (256) +#define SSD_ROM_NR_BRIDGE_FW 2 +#define SSD_ROM_NR_CTRL_FW 2 +#define SSD_ROM_BRIDGE_FW_BASE 0 +#define SSD_ROM_BRIDGE_FW_SIZE (2*1024*1024) +#define SSD_ROM_CTRL_FW_BASE (SSD_ROM_NR_BRIDGE_FW*SSD_ROM_BRIDGE_FW_SIZE) +#define SSD_ROM_CTRL_FW_SIZE (5*1024*1024) +#define SSD_ROM_LABEL_BASE (SSD_ROM_CTRL_FW_BASE+SSD_ROM_CTRL_FW_SIZE*SSD_ROM_NR_CTRL_FW) +#define SSD_ROM_VP_BASE (SSD_ROM_LABEL_BASE+SSD_ROM_BLK_SIZE) + +/* reverion 3 */ +#define SSD_PROTOCOL_V3 0x3000000 +#define SSD_PROTOCOL_V3_1_1 0x3010001 +#define SSD_PROTOCOL_V3_1_3 0x3010003 +#define SSD_PROTOCOL_V3_2 0x3020000 +#define SSD_PROTOCOL_V3_2_1 0x3020001 /* <4KB improved */ +#define SSD_PROTOCOL_V3_2_2 0x3020002 /* ot protect */ +#define SSD_PROTOCOL_V3_2_4 0x3020004 + + +#define SSD_PV3_ROM_NR_BM_FW 1 +#define SSD_PV3_ROM_BM_FW_SZ (64*1024*8) + +#define SSD_ROM_LOG_SZ (64*1024*4) + +#define SSD_ROM_NR_SMART_MAX 2 +#define SSD_PV3_ROM_NR_SMART SSD_ROM_NR_SMART_MAX +#define SSD_PV3_ROM_SMART_SZ (64*1024) + +/* reverion 3.2 */ +#define SSD_PV3_2_ROM_LOG_SZ (64*1024*80) /* 5MB */ +#define SSD_PV3_2_ROM_SEC_SZ (256*1024) /* 256KB */ + + +/* register */ +#define SSD_REQ_FIFO_REG 0x0000 +#define SSD_RESP_FIFO_REG 0x0008 //0x0010 +#define SSD_RESP_PTR_REG 0x0010 //0x0018 +#define SSD_INTR_INTERVAL_REG 0x0018 +#define SSD_READY_REG 0x001C +#define SSD_BRIDGE_TEST_REG 0x0020 +#define SSD_STRIPE_SIZE_REG 0x0028 +#define SSD_CTRL_VER_REG 0x0030 //controller +#define SSD_BRIDGE_VER_REG 0x0034 //bridge +#define SSD_PCB_VER_REG 0x0038 +#define SSD_BURN_FLAG_REG 0x0040 +#define SSD_BRIDGE_INFO_REG 0x0044 + +#define SSD_WL_VAL_REG 0x0048 //32-bit + +#define SSD_BB_INFO_REG 0x004C + +#define SSD_ECC_TEST_REG 0x0050 //test only +#define SSD_ERASE_TEST_REG 0x0058 //test only +#define SSD_WRITE_TEST_REG 0x0060 //test only + +#define SSD_RESET_REG 0x0068 +#define SSD_RELOAD_FW_REG 0x0070 + +#define SSD_RESERVED_BLKS_REG 0x0074 +#define SSD_VALID_PAGES_REG 0x0078 +#define SSD_CH_INFO_REG 0x007C + +#define SSD_CTRL_TEST_REG_SZ 0x8 +#define SSD_CTRL_TEST_REG0 0x0080 +#define SSD_CTRL_TEST_REG1 0x0088 +#define SSD_CTRL_TEST_REG2 0x0090 +#define SSD_CTRL_TEST_REG3 0x0098 +#define SSD_CTRL_TEST_REG4 0x00A0 +#define SSD_CTRL_TEST_REG5 0x00A8 +#define SSD_CTRL_TEST_REG6 0x00B0 +#define SSD_CTRL_TEST_REG7 0x00B8 + +#define SSD_FLASH_INFO_REG0 0x00C0 +#define SSD_FLASH_INFO_REG1 0x00C8 +#define SSD_FLASH_INFO_REG2 0x00D0 +#define SSD_FLASH_INFO_REG3 0x00D8 +#define SSD_FLASH_INFO_REG4 0x00E0 +#define SSD_FLASH_INFO_REG5 0x00E8 +#define SSD_FLASH_INFO_REG6 0x00F0 +#define SSD_FLASH_INFO_REG7 0x00F8 + +#define SSD_RESP_INFO_REG 0x01B8 +#define SSD_NAND_BUFF_BASE 0x01BC //for nand write + +#define SSD_CHIP_INFO_REG_SZ 0x10 +#define SSD_CHIP_INFO_REG0 0x0100 //128 bit +#define SSD_CHIP_INFO_REG1 0x0110 +#define SSD_CHIP_INFO_REG2 0x0120 +#define SSD_CHIP_INFO_REG3 0x0130 +#define SSD_CHIP_INFO_REG4 0x0140 +#define SSD_CHIP_INFO_REG5 0x0150 +#define SSD_CHIP_INFO_REG6 0x0160 +#define SSD_CHIP_INFO_REG7 0x0170 + +#define SSD_RAM_INFO_REG 0x01C4 + +#define SSD_BBT_BASE_REG 0x01C8 +#define SSD_ECT_BASE_REG 0x01CC + +#define SSD_CLEAR_INTR_REG 0x01F0 + +#define SSD_INIT_STATE_REG_SZ 0x8 +#define SSD_INIT_STATE_REG0 0x0200 +#define SSD_INIT_STATE_REG1 0x0208 +#define SSD_INIT_STATE_REG2 0x0210 +#define SSD_INIT_STATE_REG3 0x0218 +#define SSD_INIT_STATE_REG4 0x0220 +#define SSD_INIT_STATE_REG5 0x0228 +#define SSD_INIT_STATE_REG6 0x0230 +#define SSD_INIT_STATE_REG7 0x0238 + +#define SSD_ROM_INFO_REG 0x0600 +#define SSD_ROM_BRIDGE_FW_INFO_REG 0x0604 +#define SSD_ROM_CTRL_FW_INFO_REG 0x0608 +#define SSD_ROM_VP_INFO_REG 0x060C + +#define SSD_LOG_INFO_REG 0x0610 +#define SSD_LED_REG 0x0614 +#define SSD_MSG_BASE_REG 0x06F8 + +/*spi reg */ +#define SSD_SPI_REG_CMD 0x0180 +#define SSD_SPI_REG_CMD_HI 0x0184 +#define SSD_SPI_REG_WDATA 0x0188 +#define SSD_SPI_REG_ID 0x0190 +#define SSD_SPI_REG_STATUS 0x0198 +#define SSD_SPI_REG_RDATA 0x01A0 +#define SSD_SPI_REG_READY 0x01A8 + +/* i2c register */ +#define SSD_I2C_CTRL_REG 0x06F0 +#define SSD_I2C_RDATA_REG 0x06F4 + +/* temperature reg */ +#define SSD_BRIGE_TEMP_REG 0x0618 + +#define SSD_CTRL_TEMP_REG0 0x0700 +#define SSD_CTRL_TEMP_REG1 0x0708 +#define SSD_CTRL_TEMP_REG2 0x0710 +#define SSD_CTRL_TEMP_REG3 0x0718 +#define SSD_CTRL_TEMP_REG4 0x0720 +#define SSD_CTRL_TEMP_REG5 0x0728 +#define SSD_CTRL_TEMP_REG6 0x0730 +#define SSD_CTRL_TEMP_REG7 0x0738 + +/* reversion 3 reg */ +#define SSD_PROTOCOL_VER_REG 0x01B4 + +#define SSD_FLUSH_TIMEOUT_REG 0x02A4 +#define SSD_BM_FAULT_REG 0x0660 + +#define SSD_PV3_RAM_STATUS_REG_SZ 0x4 +#define SSD_PV3_RAM_STATUS_REG0 0x0260 +#define SSD_PV3_RAM_STATUS_REG1 0x0264 +#define SSD_PV3_RAM_STATUS_REG2 0x0268 +#define SSD_PV3_RAM_STATUS_REG3 0x026C +#define SSD_PV3_RAM_STATUS_REG4 0x0270 +#define SSD_PV3_RAM_STATUS_REG5 0x0274 +#define SSD_PV3_RAM_STATUS_REG6 0x0278 +#define SSD_PV3_RAM_STATUS_REG7 0x027C + +#define SSD_PV3_CHIP_INFO_REG_SZ 0x40 +#define SSD_PV3_CHIP_INFO_REG0 0x0300 +#define SSD_PV3_CHIP_INFO_REG1 0x0340 +#define SSD_PV3_CHIP_INFO_REG2 0x0380 +#define SSD_PV3_CHIP_INFO_REG3 0x03B0 +#define SSD_PV3_CHIP_INFO_REG4 0x0400 +#define SSD_PV3_CHIP_INFO_REG5 0x0440 +#define SSD_PV3_CHIP_INFO_REG6 0x0480 +#define SSD_PV3_CHIP_INFO_REG7 0x04B0 + +#define SSD_PV3_INIT_STATE_REG_SZ 0x20 +#define SSD_PV3_INIT_STATE_REG0 0x0500 +#define SSD_PV3_INIT_STATE_REG1 0x0520 +#define SSD_PV3_INIT_STATE_REG2 0x0540 +#define SSD_PV3_INIT_STATE_REG3 0x0560 +#define SSD_PV3_INIT_STATE_REG4 0x0580 +#define SSD_PV3_INIT_STATE_REG5 0x05A0 +#define SSD_PV3_INIT_STATE_REG6 0x05C0 +#define SSD_PV3_INIT_STATE_REG7 0x05E0 + +/* reversion 3.1.1 reg */ +#define SSD_FULL_RESET_REG 0x01B0 + +#define SSD_CTRL_REG_ZONE_SZ 0x800 + +#define SSD_BB_THRESHOLD_L1_REG 0x2C0 +#define SSD_BB_THRESHOLD_L2_REG 0x2C4 + +#define SSD_BB_ACC_REG_SZ 0x4 +#define SSD_BB_ACC_REG0 0x21C0 +#define SSD_BB_ACC_REG1 0x29C0 +#define SSD_BB_ACC_REG2 0x31C0 + +#define SSD_EC_THRESHOLD_L1_REG 0x2C8 +#define SSD_EC_THRESHOLD_L2_REG 0x2CC + +#define SSD_EC_ACC_REG_SZ 0x4 +#define SSD_EC_ACC_REG0 0x21E0 +#define SSD_EC_ACC_REG1 0x29E0 +#define SSD_EC_ACC_REG2 0x31E0 + +/* reversion 3.1.2 & 3.1.3 reg */ +#define SSD_HW_STATUS_REG 0x02AC + +#define SSD_PLP_INFO_REG 0x0664 + +/*reversion 3.2 reg*/ +#define SSD_POWER_ON_REG 0x01EC +#define SSD_PCIE_LINKSTATUS_REG 0x01F8 +#define SSD_PL_CAP_LEARN_REG 0x01FC + +#define SSD_FPGA_1V0_REG0 0x2070 +#define SSD_FPGA_1V8_REG0 0x2078 +#define SSD_FPGA_1V0_REG1 0x2870 +#define SSD_FPGA_1V8_REG1 0x2878 + +/*reversion 3.2 reg*/ +#define SSD_READ_OT_REG0 0x2260 +#define SSD_WRITE_OT_REG0 0x2264 +#define SSD_READ_OT_REG1 0x2A60 +#define SSD_WRITE_OT_REG1 0x2A64 + + +/* function */ +#define SSD_FUNC_READ 0x01 +#define SSD_FUNC_WRITE 0x02 +#define SSD_FUNC_NAND_READ_WOOB 0x03 +#define SSD_FUNC_NAND_READ 0x04 +#define SSD_FUNC_NAND_WRITE 0x05 +#define SSD_FUNC_NAND_ERASE 0x06 +#define SSD_FUNC_NAND_READ_ID 0x07 +#define SSD_FUNC_READ_LOG 0x08 +#define SSD_FUNC_TRIM 0x09 +#define SSD_FUNC_RAM_READ 0x10 +#define SSD_FUNC_RAM_WRITE 0x11 +#define SSD_FUNC_FLUSH 0x12 //cache / bbt + +/* spi function */ +#define SSD_SPI_CMD_PROGRAM 0x02 +#define SSD_SPI_CMD_READ 0x03 +#define SSD_SPI_CMD_W_DISABLE 0x04 +#define SSD_SPI_CMD_READ_STATUS 0x05 +#define SSD_SPI_CMD_W_ENABLE 0x06 +#define SSD_SPI_CMD_ERASE 0xd8 +#define SSD_SPI_CMD_CLSR 0x30 +#define SSD_SPI_CMD_READ_ID 0x9f + +/* i2c */ +#define SSD_I2C_CTRL_READ 0x00 +#define SSD_I2C_CTRL_WRITE 0x01 + +/* i2c internal register */ +#define SSD_I2C_CFG_REG 0x00 +#define SSD_I2C_DATA_REG 0x01 +#define SSD_I2C_CMD_REG 0x02 +#define SSD_I2C_STATUS_REG 0x03 +#define SSD_I2C_SADDR_REG 0x04 +#define SSD_I2C_LEN_REG 0x05 +#define SSD_I2C_RLEN_REG 0x06 +#define SSD_I2C_WLEN_REG 0x07 +#define SSD_I2C_RESET_REG 0x08 //write for reset +#define SSD_I2C_PRER_REG 0x09 + + +/* hw mon */ +/* FPGA volt = ADC_value / 4096 * 3v */ +#define SSD_FPGA_1V0_ADC_MIN 1228 // 0.9v +#define SSD_FPGA_1V0_ADC_MAX 1502 // 1.1v +#define SSD_FPGA_1V8_ADC_MIN 2211 // 1.62v +#define SSD_FPGA_1V8_ADC_MAX 2703 // 1.98 + +/* ADC value */ +#define SSD_FPGA_VOLT_MAX(val) (((val) & 0xffff) >> 4) +#define SSD_FPGA_VOLT_MIN(val) (((val >> 16) & 0xffff) >> 4) +#define SSD_FPGA_VOLT_CUR(val) (((val >> 32) & 0xffff) >> 4) +#define SSD_FPGA_VOLT(val) ((val * 3000) >> 12) + +#define SSD_VOLT_LOG_DATA(idx, ctrl, volt) (((uint32_t)idx << 24) | ((uint32_t)ctrl << 16) | ((uint32_t)volt)) + +enum ssd_fpga_volt +{ + SSD_FPGA_1V0 = 0, + SSD_FPGA_1V8, + SSD_FPGA_VOLT_NR +}; + +enum ssd_clock +{ + SSD_CLOCK_166M_LOST = 0, + SSD_CLOCK_166M_SKEW, + SSD_CLOCK_156M_LOST, + SSD_CLOCK_156M_SKEW, + SSD_CLOCK_NR +}; + +/* sensor */ +#define SSD_SENSOR_LM75_SADDRESS (0x49 << 1) +#define SSD_SENSOR_LM80_SADDRESS (0x28 << 1) + +#define SSD_SENSOR_CONVERT_TEMP(val) ((int)(val >> 8)) + +#define SSD_INLET_OT_TEMP (55) //55 DegC +#define SSD_INLET_OT_HYST (50) //50 DegC +#define SSD_FLASH_OT_TEMP (70) //70 DegC +#define SSD_FLASH_OT_HYST (65) //65 DegC + +enum ssd_sensor +{ + SSD_SENSOR_LM80 = 0, + SSD_SENSOR_LM75, + SSD_SENSOR_NR +}; + + +/* lm75 */ +enum ssd_lm75_reg +{ + SSD_LM75_REG_TEMP = 0, + SSD_LM75_REG_CONF, + SSD_LM75_REG_THYST, + SSD_LM75_REG_TOS +}; + +/* lm96080 */ +#define SSD_LM80_REG_IN_MAX(nr) (0x2a + (nr) * 2) +#define SSD_LM80_REG_IN_MIN(nr) (0x2b + (nr) * 2) +#define SSD_LM80_REG_IN(nr) (0x20 + (nr)) + +#define SSD_LM80_REG_FAN1 0x28 +#define SSD_LM80_REG_FAN2 0x29 +#define SSD_LM80_REG_FAN_MIN(nr) (0x3b + (nr)) + +#define SSD_LM80_REG_TEMP 0x27 +#define SSD_LM80_REG_TEMP_HOT_MAX 0x38 +#define SSD_LM80_REG_TEMP_HOT_HYST 0x39 +#define SSD_LM80_REG_TEMP_OS_MAX 0x3a +#define SSD_LM80_REG_TEMP_OS_HYST 0x3b + +#define SSD_LM80_REG_CONFIG 0x00 +#define SSD_LM80_REG_ALARM1 0x01 +#define SSD_LM80_REG_ALARM2 0x02 +#define SSD_LM80_REG_MASK1 0x03 +#define SSD_LM80_REG_MASK2 0x04 +#define SSD_LM80_REG_FANDIV 0x05 +#define SSD_LM80_REG_RES 0x06 + +#define SSD_LM80_CONVERT_VOLT(val) ((val * 10) >> 8) + +#define SSD_LM80_3V3_VOLT(val) ((val)*33/19) + +#define SSD_LM80_CONV_INTERVAL (1000) + +enum ssd_lm80_in +{ + SSD_LM80_IN_CAP = 0, + SSD_LM80_IN_1V2, + SSD_LM80_IN_1V2a, + SSD_LM80_IN_1V5, + SSD_LM80_IN_1V8, + SSD_LM80_IN_FPGA_3V3, + SSD_LM80_IN_3V3, + SSD_LM80_IN_NR +}; + +struct ssd_lm80_limit +{ + uint8_t low; + uint8_t high; +}; + +/* +/- 5% except cap in*/ +static struct ssd_lm80_limit ssd_lm80_limit[SSD_LM80_IN_NR] = { + {171, 217}, /* CAP in: 1710 ~ 2170 */ + {114, 126}, + {114, 126}, + {142, 158}, + {171, 189}, + {180, 200}, + {180, 200}, +}; + +/* temperature sensors */ +enum ssd_temp_sensor +{ + SSD_TEMP_INLET = 0, + SSD_TEMP_FLASH, + SSD_TEMP_CTRL, + SSD_TEMP_NR +}; + + +#ifdef SSD_OT_PROTECT +#define SSD_OT_DELAY (60) //ms + +#define SSD_OT_TEMP (90) //90 DegC + +#define SSD_OT_TEMP_HYST (85) //85 DegC +#endif + +/* fpga temperature */ +//#define CONVERT_TEMP(val) ((float)(val)*503.975f/4096.0f-273.15f) +#define CONVERT_TEMP(val) ((val)*504/4096-273) + +#define MAX_TEMP(val) CONVERT_TEMP(((val & 0xffff) >> 4)) +#define MIN_TEMP(val) CONVERT_TEMP((((val>>16) & 0xffff) >> 4)) +#define CUR_TEMP(val) CONVERT_TEMP((((val>>32) & 0xffff) >> 4)) + + +/* CAP monitor */ +#define SSD_PL_CAP_U1 SSD_LM80_REG_IN(SSD_LM80_IN_CAP) +#define SSD_PL_CAP_U2 SSD_LM80_REG_IN(SSD_LM80_IN_1V8) +#define SSD_PL_CAP_LEARN(u1, u2, t) ((t*(u1+u2))/(2*162*(u1-u2))) +#define SSD_PL_CAP_LEARN_WAIT (20) //20ms +#define SSD_PL_CAP_LEARN_MAX_WAIT (1000/SSD_PL_CAP_LEARN_WAIT) //1s + +#define SSD_PL_CAP_CHARGE_WAIT (1000) +#define SSD_PL_CAP_CHARGE_MAX_WAIT ((120*1000)/SSD_PL_CAP_CHARGE_WAIT) //120s + +#define SSD_PL_CAP_VOLT(val) (val*7) + +#define SSD_PL_CAP_VOLT_FULL (13700) +#define SSD_PL_CAP_VOLT_READY (12880) + +#define SSD_PL_CAP_THRESHOLD (8900) +#define SSD_PL_CAP_CP_THRESHOLD (5800) +#define SSD_PL_CAP_THRESHOLD_HYST (100) + +enum ssd_pl_cap_status +{ + SSD_PL_CAP = 0, + SSD_PL_CAP_NR +}; + +enum ssd_pl_cap_type +{ + SSD_PL_CAP_DEFAULT = 0, /* 4 cap */ + SSD_PL_CAP_CP /* 3 cap */ +}; + + +/* hwmon offset */ +#define SSD_HWMON_OFFS_TEMP (0) +#define SSD_HWMON_OFFS_SENSOR (SSD_HWMON_OFFS_TEMP + SSD_TEMP_NR) +#define SSD_HWMON_OFFS_PL_CAP (SSD_HWMON_OFFS_SENSOR + SSD_SENSOR_NR) +#define SSD_HWMON_OFFS_LM80 (SSD_HWMON_OFFS_PL_CAP + SSD_PL_CAP_NR) +#define SSD_HWMON_OFFS_CLOCK (SSD_HWMON_OFFS_LM80 + SSD_LM80_IN_NR) +#define SSD_HWMON_OFFS_FPGA (SSD_HWMON_OFFS_CLOCK + SSD_CLOCK_NR) + +#define SSD_HWMON_TEMP(idx) (SSD_HWMON_OFFS_TEMP + idx) +#define SSD_HWMON_SENSOR(idx) (SSD_HWMON_OFFS_SENSOR + idx) +#define SSD_HWMON_PL_CAP(idx) (SSD_HWMON_OFFS_PL_CAP + idx) +#define SSD_HWMON_LM80(idx) (SSD_HWMON_OFFS_LM80 + idx) +#define SSD_HWMON_CLOCK(idx) (SSD_HWMON_OFFS_CLOCK + idx) +#define SSD_HWMON_FPGA(ctrl, idx) (SSD_HWMON_OFFS_FPGA + (ctrl * SSD_FPGA_VOLT_NR) + idx) + + + +/* fifo */ +typedef struct sfifo +{ + uint32_t in; + uint32_t out; + uint32_t size; + uint32_t esize; + uint32_t mask; + spinlock_t lock; + void *data; +} sfifo_t; + +static int sfifo_alloc(struct sfifo *fifo, uint32_t size, uint32_t esize) +{ + uint32_t __size = 1; + + if (!fifo || size > INT_MAX || esize == 0) { + return -EINVAL; + } + + while (__size < size) __size <<= 1; + + if (__size < 2) { + return -EINVAL; + } + + fifo->data = vmalloc(esize * __size); + if (!fifo->data) { + return -ENOMEM; + } + + fifo->in = 0; + fifo->out = 0; + fifo->mask = __size - 1; + fifo->size = __size; + fifo->esize = esize; + spin_lock_init(&fifo->lock); + + return 0; +} + +static void sfifo_free(struct sfifo *fifo) +{ + if (!fifo) { + return; + } + + vfree(fifo->data); + fifo->data = NULL; + fifo->in = 0; + fifo->out = 0; + fifo->mask = 0; + fifo->size = 0; + fifo->esize = 0; +} + +static int __sfifo_put(struct sfifo *fifo, void *val) +{ + if (((fifo->in + 1) & fifo->mask) == fifo->out) { + return -1; + } + + memcpy((fifo->data + (fifo->in * fifo->esize)), val, fifo->esize); + fifo->in = (fifo->in + 1) & fifo->mask; + + return 0; +} + +static int sfifo_put(struct sfifo *fifo, void *val) +{ + int ret = 0; + + if (!fifo || !val) { + return -EINVAL; + } + + if (!in_interrupt()) { + spin_lock_irq(&fifo->lock); + ret = __sfifo_put(fifo, val); + spin_unlock_irq(&fifo->lock); + } else { + spin_lock(&fifo->lock); + ret = __sfifo_put(fifo, val); + spin_unlock(&fifo->lock); + } + + return ret; +} + +static int __sfifo_get(struct sfifo *fifo, void *val) +{ + if (fifo->out == fifo->in) { + return -1; + } + + memcpy(val, (fifo->data + (fifo->out * fifo->esize)), fifo->esize); + fifo->out = (fifo->out + 1) & fifo->mask; + + return 0; +} + +static int sfifo_get(struct sfifo *fifo, void *val) +{ + int ret = 0; + + if (!fifo || !val) { + return -EINVAL; + } + + if (!in_interrupt()) { + spin_lock_irq(&fifo->lock); + ret = __sfifo_get(fifo, val); + spin_unlock_irq(&fifo->lock); + } else { + spin_lock(&fifo->lock); + ret = __sfifo_get(fifo, val); + spin_unlock(&fifo->lock); + } + + return ret; +} + +/* bio list */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +struct ssd_blist { + struct bio *prev; + struct bio *next; +}; + +static inline void ssd_blist_init(struct ssd_blist *ssd_bl) +{ + ssd_bl->prev = NULL; + ssd_bl->next = NULL; +} + +static inline struct bio *ssd_blist_get(struct ssd_blist *ssd_bl) +{ + struct bio *bio = ssd_bl->prev; + + ssd_bl->prev = NULL; + ssd_bl->next = NULL; + + return bio; +} + +static inline void ssd_blist_add(struct ssd_blist *ssd_bl, struct bio *bio) +{ + bio->bi_next = NULL; + + if (ssd_bl->next) { + ssd_bl->next->bi_next = bio; + } else { + ssd_bl->prev = bio; + } + + ssd_bl->next = bio; +} + +#else +#define ssd_blist bio_list +#define ssd_blist_init bio_list_init +#define ssd_blist_get bio_list_get +#define ssd_blist_add bio_list_add +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) +#define bio_start(bio) (bio->bi_sector) +#else +#define bio_start(bio) (bio->bi_iter.bi_sector) +#endif + +/* mutex */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) +#define mutex_lock down +#define mutex_unlock up +#define mutex semaphore +#define mutex_init init_MUTEX +#endif + +/* i2c */ +typedef union ssd_i2c_ctrl { + uint32_t val; + struct { + uint8_t wdata; + uint8_t addr; + uint16_t rw:1; + uint16_t pad:15; + } bits; +}__attribute__((packed)) ssd_i2c_ctrl_t; + +typedef union ssd_i2c_data { + uint32_t val; + struct { + uint32_t rdata:8; + uint32_t valid:1; + uint32_t pad:23; + } bits; +}__attribute__((packed)) ssd_i2c_data_t; + +/* write mode */ +enum ssd_write_mode +{ + SSD_WMODE_BUFFER = 0, + SSD_WMODE_BUFFER_EX, + SSD_WMODE_FUA, + /* dummy */ + SSD_WMODE_AUTO, + SSD_WMODE_DEFAULT +}; + +/* reset type */ +enum ssd_reset_type +{ + SSD_RST_NOINIT = 0, + SSD_RST_NORMAL, + SSD_RST_FULL +}; + +/* ssd msg */ +typedef struct ssd_sg_entry +{ + uint64_t block:48; + uint64_t length:16; + uint64_t buf; +}__attribute__((packed))ssd_sg_entry_t; + +typedef struct ssd_rw_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t nsegs; + uint8_t fun; + uint32_t reserved; //for 64-bit align + struct ssd_sg_entry sge[1]; //base +}__attribute__((packed))ssd_rw_msg_t; + +typedef struct ssd_resp_msg +{ + uint8_t tag; + uint8_t status:2; + uint8_t bitflip:6; + uint8_t log; + uint8_t fun; + uint32_t reserved; +}__attribute__((packed))ssd_resp_msg_t; + +typedef struct ssd_flush_msg +{ + uint8_t tag; + uint8_t flag:2; //flash cache 0 or bbt 1 + uint8_t flash:6; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align +}__attribute__((packed))ssd_flush_msg_t; + +typedef struct ssd_nand_op_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint16_t page_count; + uint8_t chip_ce; + uint8_t chip_no; + uint32_t page_no; + uint64_t buf; +}__attribute__((packed))ssd_nand_op_msg_t; + +typedef struct ssd_ram_op_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint32_t start; + uint32_t length; + uint64_t buf; +}__attribute__((packed))ssd_ram_op_msg_t; + + +/* log msg */ +typedef struct ssd_log_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint64_t buf; +}__attribute__((packed))ssd_log_msg_t; + +typedef struct ssd_log_op_msg +{ + uint8_t tag; + uint8_t flag; + uint8_t ctrl_idx; + uint8_t fun; + uint32_t reserved; //align + uint64_t reserved1; //align + uint64_t buf; +}__attribute__((packed))ssd_log_op_msg_t; + +typedef struct ssd_log_resp_msg +{ + uint8_t tag; + uint16_t status :2; + uint16_t reserved1 :2; //align with the normal resp msg + uint16_t nr_log :12; + uint8_t fun; + uint32_t reserved; +}__attribute__((packed))ssd_log_resp_msg_t; + + +/* resp msg */ +typedef union ssd_response_msq +{ + ssd_resp_msg_t resp_msg; + ssd_log_resp_msg_t log_resp_msg; + uint64_t u64_msg; + uint32_t u32_msg[2]; +} ssd_response_msq_t; + + +/* custom struct */ +typedef struct ssd_protocol_info +{ + uint32_t ver; + uint32_t init_state_reg; + uint32_t init_state_reg_sz; + uint32_t chip_info_reg; + uint32_t chip_info_reg_sz; +} ssd_protocol_info_t; + +typedef struct ssd_hw_info +{ + uint32_t bridge_ver; + uint32_t ctrl_ver; + + uint32_t cmd_fifo_sz; + uint32_t cmd_fifo_sz_mask; + uint32_t cmd_max_sg; + uint32_t sg_max_sec; + uint32_t resp_ptr_sz; + uint32_t resp_msg_sz; + + uint16_t nr_ctrl; + + uint16_t nr_data_ch; + uint16_t nr_ch; + uint16_t max_ch; + uint16_t nr_chip; + + uint8_t pcb_ver; + uint8_t upper_pcb_ver; + + uint8_t nand_vendor_id; + uint8_t nand_dev_id; + + uint8_t max_ce; + uint8_t id_size; + uint16_t oob_size; + + uint16_t bbf_pages; + uint16_t bbf_seek; // + + uint16_t page_count; //per block + uint32_t page_size; + uint32_t block_count; //per flash + + uint64_t ram_size; + uint32_t ram_align; + uint32_t ram_max_len; + + uint64_t bbt_base; + uint32_t bbt_size; + uint64_t md_base; //metadata + uint32_t md_size; + uint32_t md_entry_sz; + + uint32_t log_sz; + + uint64_t nand_wbuff_base; + + uint32_t md_reserved_blks; + uint32_t reserved_blks; + uint32_t valid_pages; + uint32_t max_valid_pages; + uint64_t size; +} ssd_hw_info_t; + +typedef struct ssd_hw_info_extend +{ + uint8_t board_type; + uint8_t cap_type; + uint8_t plp_type; + uint8_t work_mode; + uint8_t form_factor; + + uint8_t pad[59]; +}ssd_hw_info_extend_t; + +typedef struct ssd_rom_info +{ + uint32_t size; + uint32_t block_size; + uint16_t page_size; + uint8_t nr_bridge_fw; + uint8_t nr_ctrl_fw; + uint8_t nr_bm_fw; + uint8_t nr_smart; + uint32_t bridge_fw_base; + uint32_t bridge_fw_sz; + uint32_t ctrl_fw_base; + uint32_t ctrl_fw_sz; + uint32_t bm_fw_base; + uint32_t bm_fw_sz; + uint32_t log_base; + uint32_t log_sz; + uint32_t smart_base; + uint32_t smart_sz; + uint32_t vp_base; + uint32_t label_base; +} ssd_rom_info_t; + +/* debug info */ +enum ssd_debug_type +{ + SSD_DEBUG_NONE = 0, + SSD_DEBUG_READ_ERR, + SSD_DEBUG_WRITE_ERR, + SSD_DEBUG_RW_ERR, + SSD_DEBUG_READ_TO, + SSD_DEBUG_WRITE_TO, + SSD_DEBUG_RW_TO, + SSD_DEBUG_LOG, + SSD_DEBUG_OFFLINE, + SSD_DEBUG_NR +}; + +typedef struct ssd_debug_info +{ + int type; + union { + struct { + uint64_t off; + uint32_t len; + } loc; + struct { + int event; + uint32_t extra; + } log; + } data; +}ssd_debug_info_t; + +/* label */ +#define SSD_LABEL_FIELD_SZ 32 +#define SSD_SN_SZ 16 + +typedef struct ssd_label +{ + char date[SSD_LABEL_FIELD_SZ]; + char sn[SSD_LABEL_FIELD_SZ]; + char part[SSD_LABEL_FIELD_SZ]; + char desc[SSD_LABEL_FIELD_SZ]; + char other[SSD_LABEL_FIELD_SZ]; + char maf[SSD_LABEL_FIELD_SZ]; +} ssd_label_t; + +#define SSD_LABEL_DESC_SZ 256 + +typedef struct ssd_labelv3 +{ + char boardtype[SSD_LABEL_FIELD_SZ]; + char barcode[SSD_LABEL_FIELD_SZ]; + char item[SSD_LABEL_FIELD_SZ]; + char description[SSD_LABEL_DESC_SZ]; + char manufactured[SSD_LABEL_FIELD_SZ]; + char vendorname[SSD_LABEL_FIELD_SZ]; + char issuenumber[SSD_LABEL_FIELD_SZ]; + char cleicode[SSD_LABEL_FIELD_SZ]; + char bom[SSD_LABEL_FIELD_SZ]; +} ssd_labelv3_t; + +/* battery */ +typedef struct ssd_battery_info +{ + uint32_t fw_ver; +} ssd_battery_info_t; + +/* ssd power stat */ +typedef struct ssd_power_stat +{ + uint64_t nr_poweron; + uint64_t nr_powerloss; + uint64_t init_failed; +} ssd_power_stat_t; + +/* io stat */ +typedef struct ssd_io_stat +{ + uint64_t run_time; + uint64_t nr_to; + uint64_t nr_ioerr; + uint64_t nr_rwerr; + uint64_t nr_read; + uint64_t nr_write; + uint64_t rsectors; + uint64_t wsectors; +} ssd_io_stat_t; + +/* ecc */ +typedef struct ssd_ecc_info +{ + uint64_t bitflip[SSD_ECC_MAX_FLIP]; +} ssd_ecc_info_t; + +/* log */ +enum ssd_log_level +{ + SSD_LOG_LEVEL_INFO = 0, + SSD_LOG_LEVEL_NOTICE, + SSD_LOG_LEVEL_WARNING, + SSD_LOG_LEVEL_ERR, + SSD_LOG_NR_LEVEL +}; + +typedef struct ssd_log_info +{ + uint64_t nr_log; + uint64_t stat[SSD_LOG_NR_LEVEL]; +} ssd_log_info_t; + +/* S.M.A.R.T. */ +#define SSD_SMART_MAGIC (0x5452414D53445353ull) + +typedef struct ssd_smart +{ + struct ssd_power_stat pstat; + struct ssd_io_stat io_stat; + struct ssd_ecc_info ecc_info; + struct ssd_log_info log_info; + uint64_t version; + uint64_t magic; +} ssd_smart_t; + +/* internal log */ +typedef struct ssd_internal_log +{ + uint32_t nr_log; + void *log; +} ssd_internal_log_t; + +/* ssd cmd */ +typedef struct ssd_cmd +{ + struct bio *bio; + struct scatterlist *sgl; + struct list_head list; + void *dev; + int nsegs; + int flag; /*pbio(1) or bio(0)*/ + + int tag; + void *msg; + dma_addr_t msg_dma; + + unsigned long start_time; + + int errors; + unsigned int nr_log; + + struct timer_list cmd_timer; + struct completion *waiting; +} ssd_cmd_t; + +typedef void (*send_cmd_func)(struct ssd_cmd *); +typedef int (*ssd_event_call)(struct gendisk *, int, int); /* gendisk, event id, event level */ + +/* dcmd sz */ +#define SSD_DCMD_MAX_SZ 32 + +typedef struct ssd_dcmd +{ + struct list_head list; + void *dev; + uint8_t msg[SSD_DCMD_MAX_SZ]; +} ssd_dcmd_t; + + +enum ssd_state { + SSD_INIT_WORKQ, + SSD_INIT_BD, + SSD_ONLINE, + /* full reset */ + SSD_RESETING, + /* hw log */ + SSD_LOG_HW, + /* log err */ + SSD_LOG_ERR +}; + +#define SSD_QUEUE_NAME_LEN 16 +typedef struct ssd_queue { + char name[SSD_QUEUE_NAME_LEN]; + void *dev; + + int idx; + + uint32_t resp_idx; + uint32_t resp_idx_mask; + uint32_t resp_msg_sz; + + void *resp_msg; + void *resp_ptr; + + struct ssd_cmd *cmd; + + struct ssd_io_stat io_stat; + struct ssd_ecc_info ecc_info; +} ssd_queue_t; + +typedef struct ssd_device { + char name[SSD_DEV_NAME_LEN]; + + int idx; + int major; + int readonly; + + int int_mode; +#ifdef SSD_ESCAPE_IRQ + int irq_cpu; +#endif + + int reload_fw; + + int ot_delay; //in ms + + atomic_t refcnt; + atomic_t tocnt; + atomic_t in_flight[2]; //r&w + + uint64_t uptime; + + struct list_head list; + struct pci_dev *pdev; + + unsigned long mmio_base; + unsigned long mmio_len; + void __iomem *ctrlp; + + struct mutex spi_mutex; + struct mutex i2c_mutex; + + struct ssd_protocol_info protocol_info; + struct ssd_hw_info hw_info; + struct ssd_rom_info rom_info; + struct ssd_label label; + + struct ssd_smart smart; + + atomic_t in_sendq; + spinlock_t sendq_lock; + struct ssd_blist sendq; + struct task_struct *send_thread; + wait_queue_head_t send_waitq; + + atomic_t in_doneq; + spinlock_t doneq_lock; + struct ssd_blist doneq; + struct task_struct *done_thread; + wait_queue_head_t done_waitq; + + struct ssd_dcmd *dcmd; + spinlock_t dcmd_lock; + struct list_head dcmd_list; /* direct cmd list */ + wait_queue_head_t dcmd_wq; + + unsigned long *tag_map; + wait_queue_head_t tag_wq; + + spinlock_t cmd_lock; + struct ssd_cmd *cmd; + send_cmd_func scmd; + + ssd_event_call event_call; + void *msg_base; + dma_addr_t msg_base_dma; + + uint32_t resp_idx; + void *resp_msg_base; + void *resp_ptr_base; + dma_addr_t resp_msg_base_dma; + dma_addr_t resp_ptr_base_dma; + + int nr_queue; + struct msix_entry entry[SSD_MSIX_VEC]; + struct ssd_queue queue[SSD_MSIX_VEC]; + + struct request_queue *rq; /* The device request queue */ + struct gendisk *gd; /* The gendisk structure */ + + struct mutex internal_log_mutex; + struct ssd_internal_log internal_log; + struct workqueue_struct *workq; + struct work_struct log_work; /* get log */ + void *log_buf; + + unsigned long state; /* device state, for example, block device inited */ + + struct module *owner; + + /* extend */ + + int slave; + int cmajor; + int save_md; + int ot_protect; + + struct kref kref; + + struct mutex gd_mutex; + struct ssd_log_info log_info; /* volatile */ + + atomic_t queue_depth; + struct mutex barrier_mutex; + struct mutex fw_mutex; + + struct ssd_hw_info_extend hw_info_ext; + struct ssd_labelv3 labelv3; + + int wmode; + int user_wmode; + struct mutex bm_mutex; + struct work_struct bm_work; /* check bm */ + struct timer_list bm_timer; + struct sfifo log_fifo; + + struct timer_list routine_timer; + unsigned long routine_tick; + unsigned long hwmon; + + struct work_struct hwmon_work; /* check hw */ + struct work_struct capmon_work; /* check battery */ + struct work_struct tempmon_work; /* check temp */ + + /* debug info */ + struct ssd_debug_info db_info; +} ssd_device_t; + + +/* Ioctl struct */ +typedef struct ssd_acc_info { + uint32_t threshold_l1; + uint32_t threshold_l2; + uint32_t val; +} ssd_acc_info_t; + +typedef struct ssd_reg_op_info +{ + uint32_t offset; + uint32_t value; +} ssd_reg_op_info_t; + +typedef struct ssd_spi_op_info +{ + void __user *buf; + uint32_t off; + uint32_t len; +} ssd_spi_op_info_t; + +typedef struct ssd_i2c_op_info +{ + uint8_t saddr; + uint8_t wsize; + uint8_t rsize; + void __user *wbuf; + void __user *rbuf; +} ssd_i2c_op_info_t; + +typedef struct ssd_smbus_op_info +{ + uint8_t saddr; + uint8_t cmd; + uint8_t size; + void __user *buf; +} ssd_smbus_op_info_t; + +typedef struct ssd_ram_op_info { + uint8_t ctrl_idx; + uint32_t length; + uint64_t start; + uint8_t __user *buf; +} ssd_ram_op_info_t; + +typedef struct ssd_flash_op_info { + uint32_t page; + uint16_t flash; + uint8_t chip; + uint8_t ctrl_idx; + uint8_t __user *buf; +} ssd_flash_op_info_t; + +typedef struct ssd_sw_log_info { + uint16_t event; + uint16_t pad; + uint32_t data; +} ssd_sw_log_info_t; + +typedef struct ssd_version_info +{ + uint32_t bridge_ver; /* bridge fw version */ + uint32_t ctrl_ver; /* controller fw version */ + uint32_t bm_ver; /* battery manager fw version */ + uint8_t pcb_ver; /* main pcb version */ + uint8_t upper_pcb_ver; + uint8_t pad0; + uint8_t pad1; +} ssd_version_info_t; + +typedef struct pci_addr +{ + uint16_t domain; + uint8_t bus; + uint8_t slot; + uint8_t func; +} pci_addr_t; + +typedef struct ssd_drv_param_info { + int mode; + int status_mask; + int int_mode; + int threaded_irq; + int log_level; + int wmode; + int ot_protect; + int finject; + int pad[8]; +} ssd_drv_param_info_t; + + +/* form factor */ +enum ssd_form_factor +{ + SSD_FORM_FACTOR_HHHL = 0, + SSD_FORM_FACTOR_FHHL +}; + + +/* ssd power loss protect */ +enum ssd_plp_type +{ + SSD_PLP_SCAP = 0, + SSD_PLP_CAP, + SSD_PLP_NONE +}; + +/* ssd bm */ +#define SSD_BM_SLAVE_ADDRESS 0x16 +#define SSD_BM_CAP 5 + +/* SBS cmd */ +#define SSD_BM_SAFETYSTATUS 0x51 +#define SSD_BM_OPERATIONSTATUS 0x54 + +/* ManufacturerAccess */ +#define SSD_BM_MANUFACTURERACCESS 0x00 +#define SSD_BM_ENTER_CAP_LEARNING 0x0023 /* cap learning */ + +/* Data flash access */ +#define SSD_BM_DATA_FLASH_SUBCLASS_ID 0x77 +#define SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1 0x78 +#define SSD_BM_SYSTEM_DATA_SUBCLASS_ID 56 +#define SSD_BM_CONFIGURATION_REGISTERS_ID 64 + +/* min cap voltage */ +#define SSD_BM_CAP_VOLT_MIN 500 + +/* +enum ssd_bm_cap +{ + SSD_BM_CAP_VINA = 1, + SSD_BM_CAP_JH = 3 +};*/ + +enum ssd_bmstatus +{ + SSD_BMSTATUS_OK = 0, + SSD_BMSTATUS_CHARGING, /* not fully charged */ + SSD_BMSTATUS_WARNING +}; + +enum sbs_unit { + SBS_UNIT_VALUE = 0, + SBS_UNIT_TEMPERATURE, + SBS_UNIT_VOLTAGE, + SBS_UNIT_CURRENT, + SBS_UNIT_ESR, + SBS_UNIT_PERCENT, + SBS_UNIT_CAPACITANCE +}; + +enum sbs_size { + SBS_SIZE_BYTE = 1, + SBS_SIZE_WORD, + SBS_SIZE_BLK, +}; + +struct sbs_cmd { + uint8_t cmd; + uint8_t size; + uint8_t unit; + uint8_t off; + uint16_t mask; + char *desc; +}; + +struct ssd_bm { + uint16_t temp; + uint16_t volt; + uint16_t curr; + uint16_t esr; + uint16_t rsoc; + uint16_t health; + uint16_t cap; + uint16_t chg_curr; + uint16_t chg_volt; + uint16_t cap_volt[SSD_BM_CAP]; + uint16_t sf_alert; + uint16_t sf_status; + uint16_t op_status; + uint16_t sys_volt; +}; + +struct ssd_bm_manufacturer_data +{ + uint16_t pack_lot_code; + uint16_t pcb_lot_code; + uint16_t firmware_ver; + uint16_t hardware_ver; +}; + +struct ssd_bm_configuration_registers +{ + struct { + uint16_t cc:3; + uint16_t rsvd:5; + uint16_t stack:1; + uint16_t rsvd1:2; + uint16_t temp:2; + uint16_t rsvd2:1; + uint16_t lt_en:1; + uint16_t rsvd3:1; + } operation_cfg; + uint16_t pad; + uint16_t fet_action; + uint16_t pad1; + uint16_t fault; +}; + +#define SBS_VALUE_MASK 0xffff + +#define bm_var_offset(var) ((size_t) &((struct ssd_bm *)0)->var) +#define bm_var(start, offset) ((void *) start + (offset)) + +static struct sbs_cmd ssd_bm_sbs[] = { + {0x08, SBS_SIZE_WORD, SBS_UNIT_TEMPERATURE, bm_var_offset(temp), SBS_VALUE_MASK, "Temperature"}, + {0x09, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(volt), SBS_VALUE_MASK, "Voltage"}, + {0x0a, SBS_SIZE_WORD, SBS_UNIT_CURRENT, bm_var_offset(curr), SBS_VALUE_MASK, "Current"}, + {0x0b, SBS_SIZE_WORD, SBS_UNIT_ESR, bm_var_offset(esr), SBS_VALUE_MASK, "ESR"}, + {0x0d, SBS_SIZE_BYTE, SBS_UNIT_PERCENT, bm_var_offset(rsoc), SBS_VALUE_MASK, "RelativeStateOfCharge"}, + {0x0e, SBS_SIZE_BYTE, SBS_UNIT_PERCENT, bm_var_offset(health), SBS_VALUE_MASK, "Health"}, + {0x10, SBS_SIZE_WORD, SBS_UNIT_CAPACITANCE, bm_var_offset(cap), SBS_VALUE_MASK, "Capacitance"}, + {0x14, SBS_SIZE_WORD, SBS_UNIT_CURRENT, bm_var_offset(chg_curr), SBS_VALUE_MASK, "ChargingCurrent"}, + {0x15, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(chg_volt), SBS_VALUE_MASK, "ChargingVoltage"}, + {0x3b, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[4]), SBS_VALUE_MASK, "CapacitorVoltage5"}, + {0x3c, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[3]), SBS_VALUE_MASK, "CapacitorVoltage4"}, + {0x3d, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[2]), SBS_VALUE_MASK, "CapacitorVoltage3"}, + {0x3e, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[1]), SBS_VALUE_MASK, "CapacitorVoltage2"}, + {0x3f, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[0]), SBS_VALUE_MASK, "CapacitorVoltage1"}, + {0x50, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(sf_alert), 0x870F, "SafetyAlert"}, + {0x51, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(sf_status), 0xE7BF, "SafetyStatus"}, + {0x54, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(op_status), 0x79F4, "OperationStatus"}, + {0x5a, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(sys_volt), SBS_VALUE_MASK, "SystemVoltage"}, + {0, 0, 0, 0, 0, NULL}, +}; + +/* ssd ioctl */ +#define SSD_CMD_GET_PROTOCOL_INFO _IOR('H', 100, struct ssd_protocol_info) +#define SSD_CMD_GET_HW_INFO _IOR('H', 101, struct ssd_hw_info) +#define SSD_CMD_GET_ROM_INFO _IOR('H', 102, struct ssd_rom_info) +#define SSD_CMD_GET_SMART _IOR('H', 103, struct ssd_smart) +#define SSD_CMD_GET_IDX _IOR('H', 105, int) +#define SSD_CMD_GET_AMOUNT _IOR('H', 106, int) +#define SSD_CMD_GET_TO_INFO _IOR('H', 107, int) +#define SSD_CMD_GET_DRV_VER _IOR('H', 108, char[DRIVER_VERSION_LEN]) + +#define SSD_CMD_GET_BBACC_INFO _IOR('H', 109, struct ssd_acc_info) +#define SSD_CMD_GET_ECACC_INFO _IOR('H', 110, struct ssd_acc_info) + +#define SSD_CMD_GET_HW_INFO_EXT _IOR('H', 111, struct ssd_hw_info_extend) + +#define SSD_CMD_REG_READ _IOWR('H', 120, struct ssd_reg_op_info) +#define SSD_CMD_REG_WRITE _IOWR('H', 121, struct ssd_reg_op_info) + +#define SSD_CMD_SPI_READ _IOWR('H', 125, struct ssd_spi_op_info) +#define SSD_CMD_SPI_WRITE _IOWR('H', 126, struct ssd_spi_op_info) +#define SSD_CMD_SPI_ERASE _IOWR('H', 127, struct ssd_spi_op_info) + +#define SSD_CMD_I2C_READ _IOWR('H', 128, struct ssd_i2c_op_info) +#define SSD_CMD_I2C_WRITE _IOWR('H', 129, struct ssd_i2c_op_info) +#define SSD_CMD_I2C_WRITE_READ _IOWR('H', 130, struct ssd_i2c_op_info) + +#define SSD_CMD_SMBUS_SEND_BYTE _IOWR('H', 131, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_RECEIVE_BYTE _IOWR('H', 132, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_WRITE_BYTE _IOWR('H', 133, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_READ_BYTE _IOWR('H', 135, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_WRITE_WORD _IOWR('H', 136, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_READ_WORD _IOWR('H', 137, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_WRITE_BLOCK _IOWR('H', 138, struct ssd_smbus_op_info) +#define SSD_CMD_SMBUS_READ_BLOCK _IOWR('H', 139, struct ssd_smbus_op_info) + +#define SSD_CMD_BM_GET_VER _IOR('H', 140, uint16_t) +#define SSD_CMD_BM_GET_NR_CAP _IOR('H', 141, int) +#define SSD_CMD_BM_CAP_LEARNING _IOW('H', 142, int) +#define SSD_CMD_CAP_LEARN _IOR('H', 143, uint32_t) +#define SSD_CMD_GET_CAP_STATUS _IOR('H', 144, int) + +#define SSD_CMD_RAM_READ _IOWR('H', 150, struct ssd_ram_op_info) +#define SSD_CMD_RAM_WRITE _IOWR('H', 151, struct ssd_ram_op_info) + +#define SSD_CMD_NAND_READ_ID _IOR('H', 160, struct ssd_flash_op_info) +#define SSD_CMD_NAND_READ _IOWR('H', 161, struct ssd_flash_op_info) //with oob +#define SSD_CMD_NAND_WRITE _IOWR('H', 162, struct ssd_flash_op_info) +#define SSD_CMD_NAND_ERASE _IOWR('H', 163, struct ssd_flash_op_info) +#define SSD_CMD_NAND_READ_EXT _IOWR('H', 164, struct ssd_flash_op_info) //ingore EIO + +#define SSD_CMD_UPDATE_BBT _IOW('H', 180, struct ssd_flash_op_info) + +#define SSD_CMD_CLEAR_ALARM _IOW('H', 190, int) +#define SSD_CMD_SET_ALARM _IOW('H', 191, int) + +#define SSD_CMD_RESET _IOW('H', 200, int) +#define SSD_CMD_RELOAD_FW _IOW('H', 201, int) +#define SSD_CMD_UNLOAD_DEV _IOW('H', 202, int) +#define SSD_CMD_LOAD_DEV _IOW('H', 203, int) +#define SSD_CMD_UPDATE_VP _IOWR('H', 205, uint32_t) +#define SSD_CMD_FULL_RESET _IOW('H', 206, int) + +#define SSD_CMD_GET_NR_LOG _IOR('H', 220, uint32_t) +#define SSD_CMD_GET_LOG _IOR('H', 221, void *) +#define SSD_CMD_LOG_LEVEL _IOW('H', 222, int) + +#define SSD_CMD_OT_PROTECT _IOW('H', 223, int) +#define SSD_CMD_GET_OT_STATUS _IOR('H', 224, int) + +#define SSD_CMD_CLEAR_LOG _IOW('H', 230, int) +#define SSD_CMD_CLEAR_SMART _IOW('H', 231, int) + +#define SSD_CMD_SW_LOG _IOW('H', 232, struct ssd_sw_log_info) + +#define SSD_CMD_GET_LABEL _IOR('H', 235, struct ssd_label) +#define SSD_CMD_GET_VERSION _IOR('H', 236, struct ssd_version_info) +#define SSD_CMD_GET_TEMPERATURE _IOR('H', 237, int) +#define SSD_CMD_GET_BMSTATUS _IOR('H', 238, int) +#define SSD_CMD_GET_LABEL2 _IOR('H', 239, void *) + + +#define SSD_CMD_FLUSH _IOW('H', 240, int) +#define SSD_CMD_SAVE_MD _IOW('H', 241, int) + +#define SSD_CMD_SET_WMODE _IOW('H', 242, int) +#define SSD_CMD_GET_WMODE _IOR('H', 243, int) +#define SSD_CMD_GET_USER_WMODE _IOR('H', 244, int) + +#define SSD_CMD_DEBUG _IOW('H', 250, struct ssd_debug_info) +#define SSD_CMD_DRV_PARAM_INFO _IOR('H', 251, struct ssd_drv_param_info) + + +/* log */ +#define SSD_LOG_MAX_SZ 4096 +#define SSD_LOG_LEVEL SSD_LOG_LEVEL_NOTICE + +enum ssd_log_data +{ + SSD_LOG_DATA_NONE = 0, + SSD_LOG_DATA_LOC, + SSD_LOG_DATA_HEX +}; + +typedef struct ssd_log_entry +{ + union { + struct { + uint32_t page:10; + uint32_t block:14; + uint32_t flash:8; + } loc; + struct { + uint32_t page:12; + uint32_t block:12; + uint32_t flash:8; + } loc1; + uint32_t val; + } data; + uint16_t event:10; + uint16_t mod:6; + uint16_t idx; +}__attribute__((packed))ssd_log_entry_t; + +typedef struct ssd_log +{ + uint64_t time:56; + uint64_t ctrl_idx:8; + ssd_log_entry_t le; +} __attribute__((packed)) ssd_log_t; + +typedef struct ssd_log_desc +{ + uint16_t event; + uint8_t level; + uint8_t data; + uint8_t sblock; + uint8_t spage; + char *desc; +} __attribute__((packed)) ssd_log_desc_t; + +#define SSD_LOG_SW_IDX 0xF +#define SSD_UNKNOWN_EVENT ((uint16_t)-1) +static struct ssd_log_desc ssd_log_desc[] = { + /* event, level, show flash, show block, show page, desc */ + {0x0, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 0, 0, "Create BBT failure"}, //g3 + {0x1, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 0, 0, "Read BBT failure"}, //g3 + {0x2, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Mark bad block"}, + {0x3, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Flush BBT failure"}, + {0x4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x7, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "No available blocks"}, + {0x8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Bad EC header"}, + {0x9, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 0, "Bad VID header"}, //g3 + {0xa, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 0, "Wear leveling"}, + {0xb, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "WL read back failure"}, + {0x11, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Data recovery failure"}, // err + {0x20, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: scan mapping table failure"}, // err g3 + {0x21, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x22, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x23, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x24, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Merge: read mapping page failure"}, + {0x25, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Merge: read back failure"}, + {0x26, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0x27, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 1, "Data corrupted for abnormal power down"}, //g3 + {0x28, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Merge: mapping page corrupted"}, + {0x29, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: no mapping page"}, + {0x2a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: mapping pages incomplete"}, + {0x2b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Read back failure after programming failure"}, // err + {0xf1, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Read failure without recovery"}, // err + {0xf2, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 0, 0, "No available blocks"}, // maybe err g3 + {0xf3, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Init: RAID incomplete"}, // err g3 + {0xf4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0xf5, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read failure in moving data"}, + {0xf6, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"}, + {0xf7, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 1, "Init: RAID not complete"}, + {0xf8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: data moving interrupted"}, + {0xfe, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Data inspection failure"}, + {0xff, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "IO: ECC failed"}, + + /* new */ + {0x2e, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 0, 0, "No available reserved blocks" }, // err + {0x30, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PMT membership not found"}, + {0x31, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Init: PMT corrupted"}, + {0x32, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT membership not found"}, + {0x33, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT not found"}, + {0x34, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT corrupted"}, + {0x35, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT page read failure"}, + {0x36, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT page read failure"}, + {0x37, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT backup page read failure"}, + {0x38, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBMT read failure"}, + {0x39, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: PBMT scan failure"}, // err + {0x3a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: first page read failure"}, + {0x3b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: first page scan failure"}, // err + {0x3c, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: scan unclosed block failure"}, // err + {0x3d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: write pointer mismatch"}, + {0x3e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT recovery: PBMT read failure"}, + {0x3f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: PMT recovery: PBMT scan failure"}, + {0x40, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT recovery: data page read failure"}, //err + {0x41, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT write pointer mismatch"}, + {0x42, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT latest version corrupted"}, + {0x43, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Init: too many unclosed blocks"}, + {0x44, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Init: PDW block found"}, + {0x45, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Init: more than one PDW block found"}, //err + {0x46, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: first page is blank or read failure"}, + {0x47, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PDW block not found"}, + + {0x50, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Cache: hit error data"}, // err + {0x51, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Cache: read back failure"}, // err + {0x52, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Cache: unknown command"}, //? + {0x53, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "GC/WL read back failure"}, // err + + {0x60, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Erase failure"}, + + {0x70, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "LPA not matched"}, + {0x71, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "PBN not matched"}, + {0x72, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read retry failure"}, + {0x73, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Need raid recovery"}, + {0x74, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 1, "Need read retry"}, + {0x75, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read invalid data page"}, + {0x76, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in cache, PBN matched"}, + {0x77, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in cache, PBN not matched"}, + {0x78, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in flash, PBN not matched"}, + {0x79, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC ok, data in cache, LPA not matched"}, + {0x7a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC ok, data in flash, LPA not matched"}, + {0x7b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID data in cache, LPA not matched"}, + {0x7c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID data in flash, LPA not matched"}, + {0x7d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read data page status error"}, + {0x7e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read blank page"}, + {0x7f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Access flash timeout"}, + + {0x80, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "EC overflow"}, + {0x81, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_NONE, 0, 0, "Scrubbing completed"}, + {0x82, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 0, "Unstable block(too much bit flip)"}, + {0x83, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: ram error"}, //? + {0x84, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: one PBMT read failure"}, + + {0x88, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: mark bad block"}, + {0x89, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: invalid page count error"}, // maybe err + {0x8a, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Warning: Bad Block close to limit"}, + {0x8b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Error: Bad Block over limit"}, + {0x8c, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Warning: P/E cycles close to limit"}, + {0x8d, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Error: P/E cycles over limit"}, + + {0x90, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Over temperature"}, //xx + {0x91, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature is OK"}, //xx + {0x92, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Battery fault"}, + {0x93, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "SEU fault"}, //err + {0x94, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "DDR error"}, //err + {0x95, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Controller serdes error"}, //err + {0x96, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Bridge serdes 1 error"}, //err + {0x97, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Bridge serdes 2 error"}, //err + {0x98, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "SEU fault (corrected)"}, //err + {0x99, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Battery is OK"}, + {0x9a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature close to limit"}, //xx + + {0x9b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "SEU fault address (low)"}, + {0x9c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "SEU fault address (high)"}, + {0x9d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "I2C fault" }, + {0x9e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "DDR single bit error" }, + {0x9f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Board voltage fault" }, + + {0xa0, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "LPA not matched"}, + {0xa1, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Re-read data in cache"}, + {0xa2, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read blank page"}, + {0xa3, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: Read blank page"}, + {0xa4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: new data in cache"}, + {0xa5, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: PBN not matched"}, + {0xa6, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read data with error flag"}, + {0xa7, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: recoverd data with error flag"}, + {0xa8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Blank page in cache, PBN matched"}, + {0xa9, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: Blank page in cache, PBN matched"}, + {0xaa, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Flash init failure"}, + {0xab, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Mapping table recovery failure"}, + {0xac, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: ECC failed"}, + {0xb0, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature is up to degree 95"}, + {0xb1, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Temperature is up to degree 100"}, + + {0x300, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "CMD timeout"}, + {0x301, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Power on"}, + {0x302, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Power off"}, + {0x303, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear log"}, + {0x304, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set capacity"}, + {0x305, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear data"}, + {0x306, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "BM safety status"}, + {0x307, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "I/O error"}, + {0x308, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "CMD error"}, + {0x309, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set wmode"}, + {0x30a, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "DDR init failed" }, + {0x30b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "PCIe link status" }, + {0x30c, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Controller reset sync error" }, + {0x30d, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Clock fault" }, + {0x30e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "FPGA voltage fault status" }, + {0x30f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set capacity finished"}, + {0x310, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear data finished"}, + {0x311, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Reset"}, + {0x312, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_HEX, 0, 0, "CAP: voltage fault"}, + {0x313, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_NONE, 0, 0, "CAP: learn fault"}, + {0x314, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "CAP status"}, + {0x315, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Board voltage fault status"}, + {0x316, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Inlet over temperature"}, + {0x317, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Inlet temperature is OK"}, + {0x318, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Flash over temperature"}, + {0x319, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Flash temperature is OK"}, + {0x31a, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_NONE, 0, 0, "CAP: short circuit"}, + {0x31b, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_HEX, 0, 0, "Sensor fault"}, + {0x31c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Erase all data"}, + {0x31d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Erase all data finished"}, + + {SSD_UNKNOWN_EVENT, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "unknown event"}, +}; +/* */ +#define SSD_LOG_OVER_TEMP 0x90 +#define SSD_LOG_NORMAL_TEMP 0x91 +#define SSD_LOG_WARN_TEMP 0x9a +#define SSD_LOG_SEU_FAULT 0x93 +#define SSD_LOG_SEU_FAULT1 0x98 +#define SSD_LOG_BATTERY_FAULT 0x92 +#define SSD_LOG_BATTERY_OK 0x99 +#define SSD_LOG_BOARD_VOLT_FAULT 0x9f + +/* software log */ +#define SSD_LOG_TIMEOUT 0x300 +#define SSD_LOG_POWER_ON 0x301 +#define SSD_LOG_POWER_OFF 0x302 +#define SSD_LOG_CLEAR_LOG 0x303 +#define SSD_LOG_SET_CAPACITY 0x304 +#define SSD_LOG_CLEAR_DATA 0x305 +#define SSD_LOG_BM_SFSTATUS 0x306 +#define SSD_LOG_EIO 0x307 +#define SSD_LOG_ECMD 0x308 +#define SSD_LOG_SET_WMODE 0x309 +#define SSD_LOG_DDR_INIT_ERR 0x30a +#define SSD_LOG_PCIE_LINK_STATUS 0x30b +#define SSD_LOG_CTRL_RST_SYNC 0x30c +#define SSD_LOG_CLK_FAULT 0x30d +#define SSD_LOG_VOLT_FAULT 0x30e +#define SSD_LOG_SET_CAPACITY_END 0x30F +#define SSD_LOG_CLEAR_DATA_END 0x310 +#define SSD_LOG_RESET 0x311 +#define SSD_LOG_CAP_VOLT_FAULT 0x312 +#define SSD_LOG_CAP_LEARN_FAULT 0x313 +#define SSD_LOG_CAP_STATUS 0x314 +#define SSD_LOG_VOLT_STATUS 0x315 +#define SSD_LOG_INLET_OVER_TEMP 0x316 +#define SSD_LOG_INLET_NORMAL_TEMP 0x317 +#define SSD_LOG_FLASH_OVER_TEMP 0x318 +#define SSD_LOG_FLASH_NORMAL_TEMP 0x319 +#define SSD_LOG_CAP_SHORT_CIRCUIT 0x31a +#define SSD_LOG_SENSOR_FAULT 0x31b +#define SSD_LOG_ERASE_ALL 0x31c +#define SSD_LOG_ERASE_ALL_END 0x31d + + +/* sw log fifo depth */ +#define SSD_LOG_FIFO_SZ 1024 + + +/* done queue */ +static DEFINE_PER_CPU(struct list_head, ssd_doneq); +static DEFINE_PER_CPU(struct tasklet_struct, ssd_tasklet); + + +/* unloading driver */ +static volatile int ssd_exiting = 0; + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) +static struct class_simple *ssd_class; +#else +static struct class *ssd_class; +#endif + +static int ssd_cmajor = SSD_CMAJOR; + +/* ssd block device major, minors */ +static int ssd_major = SSD_MAJOR; +static int ssd_major_sl = SSD_MAJOR_SL; +static int ssd_minors = SSD_MINORS; + +/* ssd device list */ +static struct list_head ssd_list; +static unsigned long ssd_index_bits[SSD_MAX_DEV / BITS_PER_LONG + 1]; +static unsigned long ssd_index_bits_sl[SSD_MAX_DEV / BITS_PER_LONG + 1]; +static atomic_t ssd_nr; + +/* module param */ +enum ssd_drv_mode +{ + SSD_DRV_MODE_STANDARD = 0, /* full */ + SSD_DRV_MODE_DEBUG = 2, /* debug */ + SSD_DRV_MODE_BASE /* base only */ +}; + +enum ssd_int_mode +{ + SSD_INT_LEGACY = 0, + SSD_INT_MSI, + SSD_INT_MSIX +}; + +#if (defined SSD_MSIX) +#define SSD_INT_MODE_DEFAULT SSD_INT_MSIX +#elif (defined SSD_MSI) +#define SSD_INT_MODE_DEFAULT SSD_INT_MSI +#else +/* auto select the defaut int mode according to the kernel version*/ +/* suse 11 sp1 irqbalance bug: use msi instead*/ +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR >= 6) || (defined RHEL_MAJOR && RHEL_MAJOR == 5 && RHEL_MINOR >= 5)) +#define SSD_INT_MODE_DEFAULT SSD_INT_MSIX +#else +#define SSD_INT_MODE_DEFAULT SSD_INT_MSI +#endif +#endif + +static int mode = SSD_DRV_MODE_STANDARD; +static int status_mask = 0xFF; +static int int_mode = SSD_INT_MODE_DEFAULT; +static int threaded_irq = 0; +static int log_level = SSD_LOG_LEVEL_WARNING; +static int ot_protect = 1; +static int wmode = SSD_WMODE_DEFAULT; +static int finject = 0; + +module_param(mode, int, 0); +module_param(status_mask, int, 0); +module_param(int_mode, int, 0); +module_param(threaded_irq, int, 0); +module_param(log_level, int, 0); +module_param(ot_protect, int, 0); +module_param(wmode, int, 0); +module_param(finject, int, 0); + + +MODULE_PARM_DESC(mode, "driver mode, 0 - standard, 1 - debug, 2 - debug without IO, 3 - basic debug mode"); +MODULE_PARM_DESC(status_mask, "command status mask, 0 - without command error, 0xff - with command error"); +MODULE_PARM_DESC(int_mode, "preferred interrupt mode, 0 - legacy, 1 - msi, 2 - msix"); +MODULE_PARM_DESC(threaded_irq, "threaded irq, 0 - normal irq, 1 - threaded irq"); +MODULE_PARM_DESC(log_level, "log level to display, 0 - info and above, 1 - notice and above, 2 - warning and above, 3 - error only"); +MODULE_PARM_DESC(ot_protect, "over temperature protect, 0 - disable, 1 - enable"); +MODULE_PARM_DESC(wmode, "write mode, 0 - write buffer (with risk for the 6xx firmware), 1 - write buffer ex, 2 - write through, 3 - auto, 4 - default"); +MODULE_PARM_DESC(finject, "enable fault simulation, 0 - off, 1 - on, for debug purpose only"); + + +#ifndef MODULE +static int __init ssd_drv_mode(char *str) +{ + mode = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_status_mask(char *str) +{ + status_mask = (int)simple_strtoul(str, NULL, 16); + + return 1; +} + +static int __init ssd_int_mode(char *str) +{ + int_mode = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_threaded_irq(char *str) +{ + threaded_irq = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_log_level(char *str) +{ + log_level = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_ot_protect(char *str) +{ + ot_protect = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_wmode(char *str) +{ + wmode = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +static int __init ssd_finject(char *str) +{ + finject = (int)simple_strtoul(str, NULL, 0); + + return 1; +} + +__setup(MODULE_NAME"_mode=", ssd_drv_mode); +__setup(MODULE_NAME"_status_mask=", ssd_status_mask); +__setup(MODULE_NAME"_int_mode=", ssd_int_mode); +__setup(MODULE_NAME"_threaded_irq=", ssd_threaded_irq); +__setup(MODULE_NAME"_log_level=", ssd_log_level); +__setup(MODULE_NAME"_ot_protect=", ssd_ot_protect); +__setup(MODULE_NAME"_wmode=", ssd_wmode); +__setup(MODULE_NAME"_finject=", ssd_finject); +#endif + + +#ifdef CONFIG_PROC_FS +#include +#include + +#define SSD_PROC_DIR MODULE_NAME +#define SSD_PROC_INFO "info" + +static struct proc_dir_entry *ssd_proc_dir = NULL; +static struct proc_dir_entry *ssd_proc_info = NULL; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) +static int ssd_proc_read(char *page, char **start, + off_t off, int count, int *eof, void *data) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + uint64_t size; + int idx; + int len = 0; + //char type; //xx + + if (ssd_exiting) { + return 0; + } + + len += snprintf((page + len), (count - len), "Driver Version:\t%s\n", DRIVER_VERSION); + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + idx = dev->idx + 1; + size = dev->hw_info.size ; + do_div(size, 1000000000); + + len += snprintf((page + len), (count - len), "\n"); + + len += snprintf((page + len), (count - len), "HIO %d Size:\t%uGB\n", idx, (uint32_t)size); + + len += snprintf((page + len), (count - len), "HIO %d Bridge FW VER:\t%03X\n", idx, dev->hw_info.bridge_ver); + if (dev->hw_info.ctrl_ver != 0) { + len += snprintf((page + len), (count - len), "HIO %d Controller FW VER:\t%03X\n", idx, dev->hw_info.ctrl_ver); + } + + len += snprintf((page + len), (count - len), "HIO %d PCB VER:\t.%c\n", idx, dev->hw_info.pcb_ver); + + if (dev->hw_info.upper_pcb_ver >= 'A') { + len += snprintf((page + len), (count - len), "HIO %d Upper PCB VER:\t.%c\n", idx, dev->hw_info.upper_pcb_ver); + } + + len += snprintf((page + len), (count - len), "HIO %d Device:\t%s\n", idx, dev->name); + } + + return len; +} + +#else + +static int ssd_proc_show(struct seq_file *m, void *v) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + uint64_t size; + int idx; + + if (ssd_exiting) { + return 0; + } + + seq_printf(m, "Driver Version:\t%s\n", DRIVER_VERSION); + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + idx = dev->idx + 1; + size = dev->hw_info.size ; + do_div(size, 1000000000); + + seq_printf(m, "\n"); + + seq_printf(m, "HIO %d Size:\t%uGB\n", idx, (uint32_t)size); + + seq_printf(m, "HIO %d Bridge FW VER:\t%03X\n", idx, dev->hw_info.bridge_ver); + if (dev->hw_info.ctrl_ver != 0) { + seq_printf(m, "HIO %d Controller FW VER:\t%03X\n", idx, dev->hw_info.ctrl_ver); + } + + seq_printf(m, "HIO %d PCB VER:\t.%c\n", idx, dev->hw_info.pcb_ver); + + if (dev->hw_info.upper_pcb_ver >= 'A') { + seq_printf(m, "HIO %d Upper PCB VER:\t.%c\n", idx, dev->hw_info.upper_pcb_ver); + } + + seq_printf(m, "HIO %d Device:\t%s\n", idx, dev->name); + } + + return 0; +} + +static int ssd_proc_open(struct inode *inode, struct file *file) +{ +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0)) + return single_open(file, ssd_proc_show, PDE(inode)->data); +#else + return single_open(file, ssd_proc_show, PDE_DATA(inode)); +#endif +} + +static const struct file_operations ssd_proc_fops = { + .open = ssd_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif + + +static void ssd_cleanup_proc(void) +{ + if (ssd_proc_info) { + remove_proc_entry(SSD_PROC_INFO, ssd_proc_dir); + ssd_proc_info = NULL; + } + if (ssd_proc_dir) { + remove_proc_entry(SSD_PROC_DIR, NULL); + ssd_proc_dir = NULL; + } +} +static int ssd_init_proc(void) +{ + ssd_proc_dir = proc_mkdir(SSD_PROC_DIR, NULL); + if (!ssd_proc_dir) + goto out_proc_mkdir; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) + ssd_proc_info = create_proc_entry(SSD_PROC_INFO, S_IFREG | S_IRUGO | S_IWUSR, ssd_proc_dir); + if (!ssd_proc_info) + goto out_create_proc_entry; + + ssd_proc_info->read_proc = ssd_proc_read; + +/* kernel bug */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) + ssd_proc_info->owner = THIS_MODULE; +#endif +#else + ssd_proc_info = proc_create(SSD_PROC_INFO, 0600, ssd_proc_dir, &ssd_proc_fops); + if (!ssd_proc_info) + goto out_create_proc_entry; +#endif + + return 0; + +out_create_proc_entry: + remove_proc_entry(SSD_PROC_DIR, NULL); +out_proc_mkdir: + return -ENOMEM; +} + +#else +static void ssd_cleanup_proc(void) +{ + return; +} +static int ssd_init_proc(void) +{ + return 0; +} +#endif /* CONFIG_PROC_FS */ + +/* sysfs */ +static void ssd_unregister_sysfs(struct ssd_device *dev) +{ + return; +} + +static int ssd_register_sysfs(struct ssd_device *dev) +{ + return 0; +} + +static void ssd_cleanup_sysfs(void) +{ + return; +} + +static int ssd_init_sysfs(void) +{ + return 0; +} + +static inline void ssd_put_index(int slave, int index) +{ + unsigned long *index_bits = ssd_index_bits; + + if (slave) { + index_bits = ssd_index_bits_sl; + } + + if (test_and_clear_bit(index, index_bits)) { + atomic_dec(&ssd_nr); + } +} + +static inline int ssd_get_index(int slave) +{ + unsigned long *index_bits = ssd_index_bits; + int index; + + if (slave) { + index_bits = ssd_index_bits_sl; + } + +find_index: + if ((index = find_first_zero_bit(index_bits, SSD_MAX_DEV)) >= SSD_MAX_DEV) { + return -1; + } + + if (test_and_set_bit(index, index_bits)) { + goto find_index; + } + + atomic_inc(&ssd_nr); + + return index; +} + +static void ssd_cleanup_index(void) +{ + return; +} + +static int ssd_init_index(void) +{ + INIT_LIST_HEAD(&ssd_list); + atomic_set(&ssd_nr, 0); + memset(ssd_index_bits, 0, (SSD_MAX_DEV / BITS_PER_LONG + 1)); + memset(ssd_index_bits_sl, 0, (SSD_MAX_DEV / BITS_PER_LONG + 1)); + + return 0; +} + +static void ssd_set_dev_name(char *name, size_t size, int idx) +{ + if(idx < SSD_ALPHABET_NUM) { + snprintf(name, size, "%c", 'a'+idx); + } else { + idx -= SSD_ALPHABET_NUM; + snprintf(name, size, "%c%c", 'a'+(idx/SSD_ALPHABET_NUM), 'a'+(idx%SSD_ALPHABET_NUM)); + } +} + +/* pci register r&w */ +static inline void ssd_reg_write(void *addr, uint64_t val) +{ + iowrite32((uint32_t)val, addr); + iowrite32((uint32_t)(val >> 32), addr + 4); + wmb(); +} + +static inline uint64_t ssd_reg_read(void *addr) +{ + uint64_t val; + uint32_t val_lo, val_hi; + + val_lo = ioread32(addr); + val_hi = ioread32(addr + 4); + + rmb(); + val = val_lo | ((uint64_t)val_hi << 32); + + return val; +} + + +#define ssd_reg32_write(addr, val) writel(val, addr) +#define ssd_reg32_read(addr) readl(addr) + +/* alarm led */ +static void ssd_clear_alarm(struct ssd_device *dev) +{ + uint32_t val; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_LED_REG); + + /* firmware control */ + val &= ~0x2; + + ssd_reg32_write(dev->ctrlp + SSD_LED_REG, val); +} + +static void ssd_set_alarm(struct ssd_device *dev) +{ + uint32_t val; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_LED_REG); + + /* light up */ + val &= ~0x1; + /* software control */ + val |= 0x2; + + ssd_reg32_write(dev->ctrlp + SSD_LED_REG, val); +} + +#define u32_swap(x) \ + ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define u16_swap(x) \ + ((uint16_t)( \ + (((uint16_t)(x) & (uint16_t)0x00ff) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00) >> 8) )) + + +#if 0 +/* No lock, for init only*/ +static int ssd_spi_read_id(struct ssd_device *dev, uint32_t *id) +{ + uint32_t val; + unsigned long st; + int ret = 0; + + if (!dev || !id) { + return -EINVAL; + } + + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_ID); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + st = jiffies; + for (;;) { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + if (val == 0x1000000) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_ID); + *id = val; + +out: + return ret; +} +#endif + +/* spi access */ +static int ssd_init_spi(struct ssd_device *dev) +{ + uint32_t val; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->spi_mutex); + st = jiffies; + for(;;) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS); + + do { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } while (val != 0x1000000); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS); + if (!(val & 0x1)) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + +out: + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (val & 0x1) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR); + } + } + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE); + mutex_unlock(&dev->spi_mutex); + + ret = 0; + + return ret; +} + +static int ssd_spi_page_read(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t val; + uint32_t rlen = 0; + unsigned long st; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || size > dev->rom_info.page_size) { + return -EINVAL; + } + + mutex_lock(&dev->spi_mutex); + while (rlen < size) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, ((off + rlen) >> 24)); + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, (((off + rlen) << 8) | SSD_SPI_CMD_READ)); + + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + st = jiffies; + for (;;) { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + if (val == 0x1000000) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_RDATA); + *(uint32_t *)(buf + rlen)= u32_swap(val); + + rlen += sizeof(uint32_t); + } + +out: + mutex_unlock(&dev->spi_mutex); + return ret; +} + +static int ssd_spi_page_write(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t val; + uint32_t wlen; + unsigned long st; + int i; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || size > dev->rom_info.page_size || + (off / dev->rom_info.page_size) != ((off + size - 1) / dev->rom_info.page_size)) { + return -EINVAL; + } + + mutex_lock(&dev->spi_mutex); + + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE); + + wlen = size / sizeof(uint32_t); + for (i=0; i<(int)wlen; i++) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_WDATA, u32_swap(*((uint32_t *)buf + i))); + } + + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, (off >> 24)); + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, ((off << 8) | SSD_SPI_CMD_PROGRAM)); + + udelay(1); + + st = jiffies; + for (;;) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS); + do { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } while (val != 0x1000000); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS); + if (!(val & 0x1)) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if ((val >> 6) & 0x1) { + ret = -EIO; + goto out; + } + } + +out: + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (val & 0x1) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR); + } + } + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE); + + mutex_unlock(&dev->spi_mutex); + + return ret; +} + +static int ssd_spi_block_erase(struct ssd_device *dev, uint32_t off) +{ + uint32_t val; + unsigned long st; + int ret = 0; + + if (!dev) { + return -EINVAL; + } + + if ((off % dev->rom_info.block_size) != 0 || off >= dev->rom_info.size) { + return -EINVAL; + } + + mutex_lock(&dev->spi_mutex); + + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE); + + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, (off >> 24)); + wmb(); + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, ((off << 8) | SSD_SPI_CMD_ERASE)); + + st = jiffies; + for (;;) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS); + + do { + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY); + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } while (val != 0x1000000); + + val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS); + if (!(val & 0x1)) { + break; + } + + if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if ((val >> 5) & 0x1) { + ret = -EIO; + goto out; + } + } + +out: + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (val & 0x1) { + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR); + } + } + ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE); + + mutex_unlock(&dev->spi_mutex); + + return ret; +} + +static int ssd_spi_read(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t len = 0; + uint32_t roff; + uint32_t rsize; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size) { + return -EINVAL; + } + + while (len < size) { + roff = (off + len) % dev->rom_info.page_size; + rsize = dev->rom_info.page_size - roff; + if ((size - len) < rsize) { + rsize = (size - len); + } + roff = off + len; + + ret = ssd_spi_page_read(dev, (buf + len), roff, rsize); + if (ret) { + goto out; + } + + len += rsize; + + cond_resched(); + } + +out: + return ret; +} + +static int ssd_spi_write(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size) +{ + uint32_t len = 0; + uint32_t woff; + uint32_t wsize; + int ret = 0; + + if (!dev || !buf) { + return -EINVAL; + } + + if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 || + ((uint64_t)off + (uint64_t)size) > dev->rom_info.size) { + return -EINVAL; + } + + while (len < size) { + woff = (off + len) % dev->rom_info.page_size; + wsize = dev->rom_info.page_size - woff; + if ((size - len) < wsize) { + wsize = (size - len); + } + woff = off + len; + + ret = ssd_spi_page_write(dev, (buf + len), woff, wsize); + if (ret) { + goto out; + } + + len += wsize; + + cond_resched(); + } + +out: + return ret; +} + +static int ssd_spi_erase(struct ssd_device *dev, uint32_t off, uint32_t size) +{ + uint32_t len = 0; + uint32_t eoff; + int ret = 0; + + if (!dev) { + return -EINVAL; + } + + if (size == 0 || ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || + (off % dev->rom_info.block_size) != 0 || (size % dev->rom_info.block_size) != 0) { + return -EINVAL; + } + + while (len < size) { + eoff = (off + len); + + ret = ssd_spi_block_erase(dev, eoff); + if (ret) { + goto out; + } + + len += dev->rom_info.block_size; + + cond_resched(); + } + +out: + return ret; +} + +/* i2c access */ +static uint32_t __ssd_i2c_reg32_read(void *addr) +{ + return ssd_reg32_read(addr); +} + +static void __ssd_i2c_reg32_write(void *addr, uint32_t val) +{ + ssd_reg32_write(addr, val); + ssd_reg32_read(addr); +} + +static int __ssd_i2c_clear(struct ssd_device *dev, uint8_t saddr) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t status = 0; + int nr_data = 0; + unsigned long st; + int ret = 0; + +check_status: + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + status = data.bits.rdata; + + if (!(status & 0x4)) { + /* clear read fifo data */ + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out; + } + cond_resched(); + } + + nr_data++; + if (nr_data <= SSD_I2C_MAX_DATA) { + goto check_status; + } else { + goto out_reset; + } + } + + if (status & 0x3) { + /* clear int */ + ctrl.bits.wdata = 0x04; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + } + + if (!(status & 0x8)) { +out_reset: + /* reset i2c controller */ + ctrl.bits.wdata = 0x0; + ctrl.bits.addr = SSD_I2C_RESET_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + } + +out: + return ret; +} + +static int ssd_i2c_write(struct ssd_device *dev, uint8_t saddr, uint8_t size, uint8_t *buf) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t off = 0; + uint8_t status = 0; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->i2c_mutex); + + ctrl.val = 0; + + /* slave addr */ + ctrl.bits.wdata = saddr; + ctrl.bits.addr = SSD_I2C_SADDR_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* data */ + while (off < size) { + ctrl.bits.wdata = buf[off]; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + off++; + } + + /* write */ + ctrl.bits.wdata = 0x01; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* wait */ + st = jiffies; + for (;;) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + status = data.bits.rdata; + if (status & 0x1) { + break; + } + + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + if (!(status & 0x1)) { + ret = -1; + goto out_clear; + } + + /* busy ? */ + if (status & 0x20) { + ret = -2; + goto out_clear; + } + + /* ack ? */ + if (status & 0x10) { + ret = -3; + goto out_clear; + } + + /* clear */ +out_clear: + if (__ssd_i2c_clear(dev, saddr)) { + if (!ret) ret = -4; + } + + mutex_unlock(&dev->i2c_mutex); + + return ret; +} + +static int ssd_i2c_read(struct ssd_device *dev, uint8_t saddr, uint8_t size, uint8_t *buf) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t off = 0; + uint8_t status = 0; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->i2c_mutex); + + ctrl.val = 0; + + /* slave addr */ + ctrl.bits.wdata = saddr; + ctrl.bits.addr = SSD_I2C_SADDR_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* read len */ + ctrl.bits.wdata = size; + ctrl.bits.addr = SSD_I2C_LEN_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* read */ + ctrl.bits.wdata = 0x02; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* wait */ + st = jiffies; + for (;;) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + status = data.bits.rdata; + if (status & 0x2) { + break; + } + + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + if (!(status & 0x2)) { + ret = -1; + goto out_clear; + } + + /* busy ? */ + if (status & 0x20) { + ret = -2; + goto out_clear; + } + + /* ack ? */ + if (status & 0x10) { + ret = -3; + goto out_clear; + } + + /* data */ + while (off < size) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + buf[off] = data.bits.rdata; + + off++; + } + + /* clear */ +out_clear: + if (__ssd_i2c_clear(dev, saddr)) { + if (!ret) ret = -4; + } + + mutex_unlock(&dev->i2c_mutex); + + return ret; +} + +static int ssd_i2c_write_read(struct ssd_device *dev, uint8_t saddr, uint8_t wsize, uint8_t *wbuf, uint8_t rsize, uint8_t *rbuf) +{ + ssd_i2c_ctrl_t ctrl; + ssd_i2c_data_t data; + uint8_t off = 0; + uint8_t status = 0; + unsigned long st; + int ret = 0; + + mutex_lock(&dev->i2c_mutex); + + ctrl.val = 0; + + /* slave addr */ + ctrl.bits.wdata = saddr; + ctrl.bits.addr = SSD_I2C_SADDR_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* data */ + off = 0; + while (off < wsize) { + ctrl.bits.wdata = wbuf[off]; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + off++; + } + + /* read len */ + ctrl.bits.wdata = rsize; + ctrl.bits.addr = SSD_I2C_LEN_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* write -> read */ + ctrl.bits.wdata = 0x03; + ctrl.bits.addr = SSD_I2C_CMD_REG; + ctrl.bits.rw = SSD_I2C_CTRL_WRITE; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + /* wait */ + st = jiffies; + for (;;) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_STATUS_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + status = data.bits.rdata; + if (status & 0x2) { + break; + } + + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + if (!(status & 0x2)) { + ret = -1; + goto out_clear; + } + + /* busy ? */ + if (status & 0x20) { + ret = -2; + goto out_clear; + } + + /* ack ? */ + if (status & 0x10) { + ret = -3; + goto out_clear; + } + + /* data */ + off = 0; + while (off < rsize) { + ctrl.bits.wdata = 0; + ctrl.bits.addr = SSD_I2C_DATA_REG; + ctrl.bits.rw = SSD_I2C_CTRL_READ; + __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val); + + st = jiffies; + for (;;) { + data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG); + if (data.bits.valid == 0) { + break; + } + + /* retry */ + if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) { + ret = -ETIMEDOUT; + goto out_clear; + } + cond_resched(); + } + + rbuf[off] = data.bits.rdata; + + off++; + } + + /* clear */ +out_clear: + if (__ssd_i2c_clear(dev, saddr)) { + if (!ret) ret = -4; + } + mutex_unlock(&dev->i2c_mutex); + + return ret; +} + +static int ssd_smbus_send_byte(struct ssd_device *dev, uint8_t saddr, uint8_t *buf) +{ + int i = 0; + int ret = 0; + + for (;;) { + ret = ssd_i2c_write(dev, saddr, 1, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_receive_byte(struct ssd_device *dev, uint8_t saddr, uint8_t *buf) +{ + int i = 0; + int ret = 0; + + for (;;) { + ret = ssd_i2c_read(dev, saddr, 1, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_write_byte(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + memcpy((smb_data + 1), buf, 1); + + for (;;) { + ret = ssd_i2c_write(dev, saddr, 2, smb_data); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_read_byte(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + + for (;;) { + ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, 1, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_write_word(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + memcpy((smb_data + 1), buf, 2); + + for (;;) { + ret = ssd_i2c_write(dev, saddr, 3, smb_data); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_read_word(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + + for (;;) { + ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, 2, buf); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_write_block(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t size, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + smb_data[1] = size; + memcpy((smb_data + 2), buf, size); + + for (;;) { + ret = ssd_i2c_write(dev, saddr, (2 + size), smb_data); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + + return ret; +} + +static int ssd_smbus_read_block(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t size, uint8_t *buf) +{ + uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0}; + uint8_t rsize; + int i = 0; + int ret = 0; + + smb_data[0] = cmd; + + for (;;) { + ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, (SSD_SMBUS_BLOCK_MAX + 1), (smb_data + 1)); + if (!ret || -ETIMEDOUT == ret) { + break; + } + + i++; + if (i >= SSD_SMBUS_RETRY_MAX) { + break; + } + msleep(SSD_SMBUS_RETRY_INTERVAL); + } + if (ret) { + return ret; + } + + rsize = smb_data[1]; + + if (rsize > size ) { + rsize = size; + } + + memcpy(buf, (smb_data + 2), rsize); + + return 0; +} + + +static int ssd_gen_swlog(struct ssd_device *dev, uint16_t event, uint32_t data); + +/* sensor */ +static int ssd_init_lm75(struct ssd_device *dev, uint8_t saddr) +{ + uint8_t conf = 0; + int ret = 0; + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM75_REG_CONF, &conf); + if (ret) { + goto out; + } + + conf &= (uint8_t)(~1u); + + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM75_REG_CONF, &conf); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm75_read(struct ssd_device *dev, uint8_t saddr, uint16_t *data) +{ + uint16_t val = 0; + int ret; + + ret = ssd_smbus_read_word(dev, saddr, SSD_LM75_REG_TEMP, (uint8_t *)&val); + if (ret) { + return ret; + } + + *data = u16_swap(val); + + return 0; +} + +static int ssd_init_lm80(struct ssd_device *dev, uint8_t saddr) +{ + uint8_t val; + uint8_t low, high; + int i; + int ret = 0; + + /* init */ + val = 0x80; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_CONFIG, &val); + if (ret) { + goto out; + } + + /* 11-bit temp */ + val = 0x08; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_RES, &val); + if (ret) { + goto out; + } + + /* set volt limit */ + for (i=0; ihw_info.nr_ctrl <= 1 && SSD_LM80_IN_1V2 == i) { + high = 0xFF; + low = 0; + } + + /* high limit */ + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_IN_MAX(i), &high); + if (ret) { + goto out; + } + + /* low limit*/ + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_IN_MIN(i), &low); + if (ret) { + goto out; + } + } + + /* set interrupt mask: allow volt in interrupt except cap in*/ + val = 0x81; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + + /* set interrupt mask: disable others */ + val = 0xFF; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK2, &val); + if (ret) { + goto out; + } + + /* start */ + val = 0x03; + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_CONFIG, &val); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm80_enable_in(struct ssd_device *dev, uint8_t saddr, int idx) +{ + uint8_t val = 0; + int ret = 0; + + if (idx >= SSD_LM80_IN_NR || idx < 0) { + return -EINVAL; + } + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + + val &= ~(1UL << (uint32_t)idx); + + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm80_disable_in(struct ssd_device *dev, uint8_t saddr, int idx) +{ + uint8_t val = 0; + int ret = 0; + + if (idx >= SSD_LM80_IN_NR || idx < 0) { + return -EINVAL; + } + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + + val |= (1UL << (uint32_t)idx); + + ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_lm80_read_temp(struct ssd_device *dev, uint8_t saddr, uint16_t *data) +{ + uint16_t val = 0; + int ret; + + ret = ssd_smbus_read_word(dev, saddr, SSD_LM80_REG_TEMP, (uint8_t *)&val); + if (ret) { + return ret; + } + + *data = u16_swap(val); + + return 0; +} + +static int ssd_lm80_check_event(struct ssd_device *dev, uint8_t saddr) +{ + uint32_t volt; + uint16_t val = 0, status; + uint8_t alarm1 = 0, alarm2 = 0; + int i; + int ret = 0; + + /* read interrupt status to clear interrupt */ + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_ALARM1, &alarm1); + if (ret) { + goto out; + } + + ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_ALARM2, &alarm2); + if (ret) { + goto out; + } + + status = (uint16_t)alarm1 | ((uint16_t)alarm2 << 8); + + /* parse inetrrupt status */ + for (i=0; i> (uint32_t)i) & 0x1)) { + if (test_and_clear_bit(SSD_HWMON_LM80(i), &dev->hwmon)) { + /* enable INx irq */ + ret = ssd_lm80_enable_in(dev, saddr, i); + if (ret) { + goto out; + } + } + + continue; + } + + /* disable INx irq */ + ret = ssd_lm80_disable_in(dev, saddr, i); + if (ret) { + goto out; + } + + if (test_and_set_bit(SSD_HWMON_LM80(i), &dev->hwmon)) { + continue; + } + + ret = ssd_smbus_read_word(dev, saddr, SSD_LM80_REG_IN(i), (uint8_t *)&val); + if (ret) { + goto out; + } + + volt = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + + switch (i) { + case SSD_LM80_IN_CAP: { + if (0 == volt) { + ssd_gen_swlog(dev, SSD_LOG_CAP_SHORT_CIRCUIT, 0); + } else { + ssd_gen_swlog(dev, SSD_LOG_CAP_VOLT_FAULT, SSD_PL_CAP_VOLT(volt)); + } + break; + } + + case SSD_LM80_IN_1V2: + case SSD_LM80_IN_1V2a: + case SSD_LM80_IN_1V5: + case SSD_LM80_IN_1V8: { + ssd_gen_swlog(dev, SSD_LOG_VOLT_STATUS, SSD_VOLT_LOG_DATA(i, 0, volt)); + break; + } + case SSD_LM80_IN_FPGA_3V3: + case SSD_LM80_IN_3V3: { + ssd_gen_swlog(dev, SSD_LOG_VOLT_STATUS, SSD_VOLT_LOG_DATA(i, 0, SSD_LM80_3V3_VOLT(volt))); + break; + } + default: + break; + } + } + +out: + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, (uint32_t)saddr); + } + } else { + test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon); + } + return ret; +} + +static int ssd_init_sensor(struct ssd_device *dev) +{ + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + goto out; + } + + ret = ssd_init_lm75(dev, SSD_SENSOR_LM75_SADDRESS); + if (ret) { + hio_warn("%s: init lm75 failed\n", dev->name); + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM75_SADDRESS); + } + goto out; + } + + if (dev->hw_info.pcb_ver >= 'B' || dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_HHHL) { + ret = ssd_init_lm80(dev, SSD_SENSOR_LM80_SADDRESS); + if (ret) { + hio_warn("%s: init lm80 failed\n", dev->name); + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +/* board volt */ +static int ssd_mon_boardvolt(struct ssd_device *dev) +{ + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + return ssd_lm80_check_event(dev, SSD_SENSOR_LM80_SADDRESS); +} + +/* temperature */ +static int ssd_mon_temp(struct ssd_device *dev) +{ + int cur; + uint16_t val = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + /* inlet */ + ret = ssd_lm80_read_temp(dev, SSD_SENSOR_LM80_SADDRESS, &val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon); + + cur = SSD_SENSOR_CONVERT_TEMP(val); + if (cur >= SSD_INLET_OT_TEMP) { + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_INLET), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_INLET_OVER_TEMP, (uint32_t)cur); + } + } else if(cur < SSD_INLET_OT_HYST) { + if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_INLET), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_INLET_NORMAL_TEMP, (uint32_t)cur); + } + } + + /* flash */ + ret = ssd_lm75_read(dev, SSD_SENSOR_LM75_SADDRESS, &val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM75_SADDRESS); + } + goto out; + } + test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon); + + cur = SSD_SENSOR_CONVERT_TEMP(val); + if (cur >= SSD_FLASH_OT_TEMP) { + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_FLASH), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_FLASH_OVER_TEMP, (uint32_t)cur); + } + } else if(cur < SSD_FLASH_OT_HYST) { + if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_FLASH), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_FLASH_NORMAL_TEMP, (uint32_t)cur); + } + } + +out: + return ret; +} + +/* cmd tag */ +static inline void ssd_put_tag(struct ssd_device *dev, int tag) +{ + test_and_clear_bit(tag, dev->tag_map); + wake_up(&dev->tag_wq); +} + +static inline int ssd_get_tag(struct ssd_device *dev, int wait) +{ + int tag; + +find_tag: + while ((tag = find_first_zero_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz)) >= atomic_read(&dev->queue_depth)) { + DEFINE_WAIT(__wait); + + if (!wait) { + return -1; + } + + prepare_to_wait_exclusive(&dev->tag_wq, &__wait, TASK_UNINTERRUPTIBLE); + schedule(); + + finish_wait(&dev->tag_wq, &__wait); + } + + if (test_and_set_bit(tag, dev->tag_map)) { + goto find_tag; + } + + return tag; +} + +static void ssd_barrier_put_tag(struct ssd_device *dev, int tag) +{ + test_and_clear_bit(tag, dev->tag_map); +} + +static int ssd_barrier_get_tag(struct ssd_device *dev) +{ + int tag = 0; + + if (test_and_set_bit(tag, dev->tag_map)) { + return -1; + } + + return tag; +} + +static void ssd_barrier_end(struct ssd_device *dev) +{ + atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz); + wake_up_all(&dev->tag_wq); + + mutex_unlock(&dev->barrier_mutex); +} + +static int ssd_barrier_start(struct ssd_device *dev) +{ + int i; + + mutex_lock(&dev->barrier_mutex); + + atomic_set(&dev->queue_depth, 0); + + for (i=0; itag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) { + return 0; + } + + __set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + + atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz); + wake_up_all(&dev->tag_wq); + + mutex_unlock(&dev->barrier_mutex); + + return -EBUSY; +} + +static int ssd_busy(struct ssd_device *dev) +{ + if (find_first_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) { + return 0; + } + + return 1; +} + +static int ssd_wait_io(struct ssd_device *dev) +{ + int i; + + for (i=0; itag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) { + return 0; + } + + __set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + + return -EBUSY; +} + +#if 0 +static int ssd_in_barrier(struct ssd_device *dev) +{ + return (0 == atomic_read(&dev->queue_depth)); +} +#endif + +static void ssd_cleanup_tag(struct ssd_device *dev) +{ + kfree(dev->tag_map); +} + +static int ssd_init_tag(struct ssd_device *dev) +{ + int nr_ulongs = ALIGN(dev->hw_info.cmd_fifo_sz, BITS_PER_LONG) / BITS_PER_LONG; + + mutex_init(&dev->barrier_mutex); + + atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz); + + dev->tag_map = kmalloc(nr_ulongs * sizeof(unsigned long), GFP_ATOMIC); + if (!dev->tag_map) { + return -ENOMEM; + } + + memset(dev->tag_map, 0, nr_ulongs * sizeof(unsigned long)); + + init_waitqueue_head(&dev->tag_wq); + + return 0; +} + +/* io stat */ +static void ssd_end_io_acct(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct bio *bio = cmd->bio; + unsigned long dur = jiffies - cmd->start_time; + int rw = bio_data_dir(bio); + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6 && RHEL_MINOR >= 7)) + int cpu = part_stat_lock(); + struct hd_struct *part = disk_map_sector_rcu(dev->gd, bio_start(bio)); + part_round_stats(cpu, part); + part_stat_add(cpu, part, ticks[rw], dur); + part_dec_in_flight(part, rw); + part_stat_unlock(); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + int cpu = part_stat_lock(); + struct hd_struct *part = &dev->gd->part0; + part_round_stats(cpu, part); + part_stat_add(cpu, part, ticks[rw], dur); + part_stat_unlock(); + part->in_flight[rw] = atomic_dec_return(&dev->in_flight[rw]); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)) + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + disk_stat_add(dev->gd, ticks[rw], dur); + dev->gd->in_flight = atomic_dec_return(&dev->in_flight[0]); +#else + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + if (rw == WRITE) { + disk_stat_add(dev->gd, write_ticks, dur); + } else { + disk_stat_add(dev->gd, read_ticks, dur); + } + dev->gd->in_flight = atomic_dec_return(&dev->in_flight[0]); +#endif +} + +static void ssd_start_io_acct(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct bio *bio = cmd->bio; + int rw = bio_data_dir(bio); + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6 && RHEL_MINOR >= 7)) + int cpu = part_stat_lock(); + struct hd_struct *part = disk_map_sector_rcu(dev->gd, bio_start(bio)); + part_round_stats(cpu, part); + part_stat_inc(cpu, part, ios[rw]); + part_stat_add(cpu, part, sectors[rw], bio_sectors(bio)); + part_inc_in_flight(part, rw); + part_stat_unlock(); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + int cpu = part_stat_lock(); + struct hd_struct *part = &dev->gd->part0; + part_round_stats(cpu, part); + part_stat_inc(cpu, part, ios[rw]); + part_stat_add(cpu, part, sectors[rw], bio_sectors(bio)); + part_stat_unlock(); + part->in_flight[rw] = atomic_inc_return(&dev->in_flight[rw]); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)) + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + disk_stat_inc(dev->gd, ios[rw]); + disk_stat_add(dev->gd, sectors[rw], bio_sectors(bio)); + dev->gd->in_flight = atomic_inc_return(&dev->in_flight[0]); +#else + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + if (rw == WRITE) { + disk_stat_inc(dev->gd, writes); + disk_stat_add(dev->gd, write_sectors, bio_sectors(bio)); + } else { + disk_stat_inc(dev->gd, reads); + disk_stat_add(dev->gd, read_sectors, bio_sectors(bio)); + } + dev->gd->in_flight = atomic_inc_return(&dev->in_flight[0]); +#endif + + cmd->start_time = jiffies; +} + +/* io */ +static void ssd_queue_bio(struct ssd_device *dev, struct bio *bio) +{ + spin_lock(&dev->sendq_lock); + ssd_blist_add(&dev->sendq, bio); + spin_unlock(&dev->sendq_lock); + + atomic_inc(&dev->in_sendq); + wake_up(&dev->send_waitq); +} + +static inline void ssd_end_request(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct bio *bio = cmd->bio; + int errors = cmd->errors; + int tag = cmd->tag; + + if (bio) { +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))) + if (!(bio->bi_rw & REQ_DISCARD)) { + ssd_end_io_acct(cmd); + if (!cmd->flag) { + pci_unmap_sg(dev->pdev, cmd->sgl, cmd->nsegs, + bio_data_dir(bio) == READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); + } + } +#elif (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (!bio_rw_flagged(bio, BIO_RW_DISCARD)) { + ssd_end_io_acct(cmd); + if (!cmd->flag) { + pci_unmap_sg(dev->pdev, cmd->sgl, cmd->nsegs, + bio_data_dir(bio) == READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); + } + } +#else + ssd_end_io_acct(cmd); + + if (!cmd->flag) { + pci_unmap_sg(dev->pdev, cmd->sgl, cmd->nsegs, + bio_data_dir(bio) == READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); + } +#endif + + cmd->bio = NULL; + ssd_put_tag(dev, tag); + + if (SSD_INT_MSIX == dev->int_mode || tag < 16 || errors) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, errors); +#else + bio_endio(bio, bio->bi_size, errors); +#endif + } else /* if (bio->bi_idx >= bio->bi_vcnt)*/ { + spin_lock(&dev->doneq_lock); + ssd_blist_add(&dev->doneq, bio); + spin_unlock(&dev->doneq_lock); + + atomic_inc(&dev->in_doneq); + wake_up(&dev->done_waitq); + } + } else { + if (cmd->waiting) { + complete(cmd->waiting); + } + } +} + +static void ssd_end_timeout_request(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg; + int i; + + for (i=0; inr_queue; i++) { + disable_irq(dev->entry[i].vector); + } + + atomic_inc(&dev->tocnt); + //if (cmd->bio) { + hio_err("%s: cmd timeout: tag %d fun %#x\n", dev->name, msg->tag, msg->fun); + cmd->errors = -ETIMEDOUT; + ssd_end_request(cmd); + //} + + for (i=0; inr_queue; i++) { + enable_irq(dev->entry[i].vector); + } + + /* alarm led */ + ssd_set_alarm(dev); +} + +/* cmd timer */ +static void ssd_cmd_add_timer(struct ssd_cmd *cmd, int timeout, void (*complt)(struct ssd_cmd *)) +{ + init_timer(&cmd->cmd_timer); + + cmd->cmd_timer.data = (unsigned long)cmd; + cmd->cmd_timer.expires = jiffies + timeout; + cmd->cmd_timer.function = (void (*)(unsigned long)) complt; + + add_timer(&cmd->cmd_timer); +} + +static int ssd_cmd_del_timer(struct ssd_cmd *cmd) +{ + return del_timer(&cmd->cmd_timer); +} + +static void ssd_add_timer(struct timer_list *timer, int timeout, void (*complt)(void *), void *data) +{ + init_timer(timer); + + timer->data = (unsigned long)data; + timer->expires = jiffies + timeout; + timer->function = (void (*)(unsigned long)) complt; + + add_timer(timer); +} + +static int ssd_del_timer(struct timer_list *timer) +{ + return del_timer(timer); +} + +static void ssd_cmd_timeout(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = cmd->dev; + uint32_t msg = *(uint32_t *)cmd->msg; + + ssd_end_timeout_request(cmd); + + ssd_gen_swlog(dev, SSD_LOG_TIMEOUT, msg); +} + + +static void __ssd_done(unsigned long data) +{ + struct ssd_cmd *cmd; + LIST_HEAD(localq); + + local_irq_disable(); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + list_splice_init(&__get_cpu_var(ssd_doneq), &localq); +#else + list_splice_init(this_cpu_ptr(&ssd_doneq), &localq); +#endif + local_irq_enable(); + + while (!list_empty(&localq)) { + cmd = list_entry(localq.next, struct ssd_cmd, list); + list_del_init(&cmd->list); + + ssd_end_request(cmd); + } +} + +static void __ssd_done_db(unsigned long data) +{ + struct ssd_cmd *cmd; + struct ssd_device *dev; + struct bio *bio; + LIST_HEAD(localq); + + local_irq_disable(); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + list_splice_init(&__get_cpu_var(ssd_doneq), &localq); +#else + list_splice_init(this_cpu_ptr(&ssd_doneq), &localq); +#endif + local_irq_enable(); + + while (!list_empty(&localq)) { + cmd = list_entry(localq.next, struct ssd_cmd, list); + list_del_init(&cmd->list); + + dev = (struct ssd_device *)cmd->dev; + bio = cmd->bio; + + if (bio) { + sector_t off = dev->db_info.data.loc.off; + uint32_t len = dev->db_info.data.loc.len; + + switch (dev->db_info.type) { + case SSD_DEBUG_READ_ERR: + if (bio_data_dir(bio) == READ && + !((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) { + cmd->errors = -EIO; + } + break; + case SSD_DEBUG_WRITE_ERR: + if (bio_data_dir(bio) == WRITE && + !((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) { + cmd->errors = -EROFS; + } + break; + case SSD_DEBUG_RW_ERR: + if (!((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) { + if (bio_data_dir(bio) == READ) { + cmd->errors = -EIO; + } else { + cmd->errors = -EROFS; + } + } + break; + default: + break; + } + } + + ssd_end_request(cmd); + } +} + +static inline void ssd_done_bh(struct ssd_cmd *cmd) +{ + unsigned long flags = 0; + + if (unlikely(!ssd_cmd_del_timer(cmd))) { + struct ssd_device *dev = cmd->dev; + struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg; + hio_err("%s: unknown cmd: tag %d fun %#x\n", dev->name, msg->tag, msg->fun); + + /* alarm led */ + ssd_set_alarm(dev); + return; + } + + local_irq_save(flags); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + list_add_tail(&cmd->list, &__get_cpu_var(ssd_doneq)); + tasklet_hi_schedule(&__get_cpu_var(ssd_tasklet)); +#else + list_add_tail(&cmd->list, this_cpu_ptr(&ssd_doneq)); + tasklet_hi_schedule(this_cpu_ptr(&ssd_tasklet)); +#endif + local_irq_restore(flags); + + return; +} + +static inline void ssd_done(struct ssd_cmd *cmd) +{ + if (unlikely(!ssd_cmd_del_timer(cmd))) { + struct ssd_device *dev = cmd->dev; + struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg; + hio_err("%s: unknown cmd: tag %d fun %#x\n", dev->name, msg->tag, msg->fun); + + /* alarm led */ + ssd_set_alarm(dev); + return; + } + + ssd_end_request(cmd); + + return; +} + +static inline void ssd_dispatch_cmd(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = (struct ssd_device *)cmd->dev; + + ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout); + + spin_lock(&dev->cmd_lock); + ssd_reg_write(dev->ctrlp + SSD_REQ_FIFO_REG, cmd->msg_dma); + spin_unlock(&dev->cmd_lock); +} + +static inline void ssd_send_cmd(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = (struct ssd_device *)cmd->dev; + + ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout); + + ssd_reg32_write(dev->ctrlp + SSD_REQ_FIFO_REG, ((uint32_t)cmd->tag | ((uint32_t)cmd->nsegs << 16))); +} + +static inline void ssd_send_cmd_db(struct ssd_cmd *cmd) +{ + struct ssd_device *dev = (struct ssd_device *)cmd->dev; + struct bio *bio = cmd->bio; + + ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout); + + if (bio) { + switch (dev->db_info.type) { + case SSD_DEBUG_READ_TO: + if (bio_data_dir(bio) == READ) { + return; + } + break; + case SSD_DEBUG_WRITE_TO: + if (bio_data_dir(bio) == WRITE) { + return; + } + break; + case SSD_DEBUG_RW_TO: + return; + break; + default: + break; + } + } + + ssd_reg32_write(dev->ctrlp + SSD_REQ_FIFO_REG, ((uint32_t)cmd->tag | ((uint32_t)cmd->nsegs << 16))); +} + + +/* fixed for BIOVEC_PHYS_MERGEABLE */ +#ifdef SSD_BIOVEC_PHYS_MERGEABLE_FIXED +#include +#include +#include + +static bool xen_biovec_phys_mergeable_fixed(const struct bio_vec *vec1, + const struct bio_vec *vec2) +{ + unsigned long mfn1 = pfn_to_mfn(page_to_pfn(vec1->bv_page)); + unsigned long mfn2 = pfn_to_mfn(page_to_pfn(vec2->bv_page)); + + return __BIOVEC_PHYS_MERGEABLE(vec1, vec2) && + ((mfn1 == mfn2) || ((mfn1+1) == mfn2)); +} + +#ifdef BIOVEC_PHYS_MERGEABLE +#undef BIOVEC_PHYS_MERGEABLE +#endif +#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ + (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ + (!xen_domain() || xen_biovec_phys_mergeable_fixed(vec1, vec2))) + +#endif + +static inline int ssd_bio_map_sg(struct ssd_device *dev, struct bio *bio, struct scatterlist *sgl) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) + struct bio_vec *bvec, *bvprv = NULL; + struct scatterlist *sg = NULL; + int i = 0, nsegs = 0; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)) + sg_init_table(sgl, dev->hw_info.cmd_max_sg); +#endif + + /* + * for each segment in bio + */ + bio_for_each_segment(bvec, bio, i) { + if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { + sg->length += bvec->bv_len; + } else { + if (unlikely(nsegs >= (int)dev->hw_info.cmd_max_sg)) { + break; + } + + sg = sg ? (sg + 1) : sgl; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset); +#else + sg->page = bvec->bv_page; + sg->length = bvec->bv_len; + sg->offset = bvec->bv_offset; +#endif + nsegs++; + } + bvprv = bvec; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + if (sg) { + sg_mark_end(sg); + } +#endif + + bio->bi_idx = i; + + return nsegs; +#else + struct bio_vec bvec, bvprv; + struct bvec_iter iter; + struct scatterlist *sg = NULL; + int nsegs = 0; + int first = 1; + + sg_init_table(sgl, dev->hw_info.cmd_max_sg); + + /* + * for each segment in bio + */ + bio_for_each_segment(bvec, bio, iter) { + if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) { + sg->length += bvec.bv_len; + } else { + if (unlikely(nsegs >= (int)dev->hw_info.cmd_max_sg)) { + break; + } + + sg = sg ? (sg + 1) : sgl; + + sg_set_page(sg, bvec.bv_page, bvec.bv_len, bvec.bv_offset); + + nsegs++; + first = 0; + } + bvprv = bvec; + } + + if (sg) { + sg_mark_end(sg); + } + + return nsegs; +#endif +} + + +static int __ssd_submit_pbio(struct ssd_device *dev, struct bio *bio, int wait) +{ + struct ssd_cmd *cmd; + struct ssd_rw_msg *msg; + struct ssd_sg_entry *sge; + sector_t block = bio_start(bio); + int tag; + int i; + + tag = ssd_get_tag(dev, wait); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->bio = bio; + cmd->flag = 1; + + msg = (struct ssd_rw_msg *)cmd->msg; + +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))) + if (bio->bi_rw & REQ_DISCARD) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#elif (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (bio_rw_flagged(bio, BIO_RW_DISCARD)) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#endif + + //msg->nsegs = cmd->nsegs = ssd_bio_map_sg(dev, bio, sgl); + msg->nsegs = cmd->nsegs = bio->bi_vcnt; + + //xx + if (bio_data_dir(bio) == READ) { + msg->fun = SSD_FUNC_READ; + msg->flag = 0; + } else { + msg->fun = SSD_FUNC_WRITE; + msg->flag = dev->wmode; + } + + sge = msg->sge; + for (i=0; ibi_vcnt; i++) { + sge->block = block; + sge->length = bio->bi_io_vec[i].bv_len >> 9; + sge->buf = (uint64_t)((void *)bio->bi_io_vec[i].bv_page + bio->bi_io_vec[i].bv_offset); + + block += sge->length; + sge++; + } + + msg->tag = tag; + +#ifdef SSD_OT_PROTECT + if (unlikely(dev->ot_delay > 0 && dev->ot_protect != 0)) { + msleep_interruptible(dev->ot_delay); + } +#endif + + ssd_start_io_acct(cmd); + dev->scmd(cmd); + + return 0; +} + +static inline int ssd_submit_bio(struct ssd_device *dev, struct bio *bio, int wait) +{ + struct ssd_cmd *cmd; + struct ssd_rw_msg *msg; + struct ssd_sg_entry *sge; + struct scatterlist *sgl; + sector_t block = bio_start(bio); + int tag; + int i; + + tag = ssd_get_tag(dev, wait); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->bio = bio; + cmd->flag = 0; + + msg = (struct ssd_rw_msg *)cmd->msg; + + sgl = cmd->sgl; + +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))) + if (bio->bi_rw & REQ_DISCARD) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#elif (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (bio_rw_flagged(bio, BIO_RW_DISCARD)) { + unsigned int length = bio_sectors(bio); + + //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block); + msg->tag = tag; + msg->fun = SSD_FUNC_TRIM; + + sge = msg->sge; + for (i=0; i<(dev->hw_info.cmd_max_sg); i++) { + sge->block = block; + sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length; + sge->buf = 0; + + block += sge->length; + length -= sge->length; + sge++; + + if (length <= 0) { + break; + } + } + msg->nsegs = cmd->nsegs = (i + 1); + + dev->scmd(cmd); + return 0; + } +#endif + + msg->nsegs = cmd->nsegs = ssd_bio_map_sg(dev, bio, sgl); + + //xx + if (bio_data_dir(bio) == READ) { + msg->fun = SSD_FUNC_READ; + msg->flag = 0; + pci_map_sg(dev->pdev, sgl, cmd->nsegs, PCI_DMA_FROMDEVICE); + } else { + msg->fun = SSD_FUNC_WRITE; + msg->flag = dev->wmode; + pci_map_sg(dev->pdev, sgl, cmd->nsegs, PCI_DMA_TODEVICE); + } + + sge = msg->sge; + for (i=0; insegs; i++) { + sge->block = block; + sge->length = sg_dma_len(sgl) >> 9; + sge->buf = sg_dma_address(sgl); + + block += sge->length; + sgl++; + sge++; + } + + msg->tag = tag; + +#ifdef SSD_OT_PROTECT + if (unlikely(dev->ot_delay > 0 && dev->ot_protect != 0)) { + msleep_interruptible(dev->ot_delay); + } +#endif + + ssd_start_io_acct(cmd); + dev->scmd(cmd); + + return 0; +} + +/* threads */ +static int ssd_done_thread(void *data) +{ + struct ssd_device *dev; + struct bio *bio; + struct bio *next; +#ifdef SSD_ESCAPE_IRQ + cpumask_t new_mask; +#endif + + if (!data) { + return -EINVAL; + } + dev = data; + + //set_user_nice(current, -5); + + while (!kthread_should_stop()) { + wait_event_interruptible(dev->done_waitq, (atomic_read(&dev->in_doneq) || kthread_should_stop())); + + while (atomic_read(&dev->in_doneq)) { + if (threaded_irq) { + spin_lock(&dev->doneq_lock); + bio = ssd_blist_get(&dev->doneq); + spin_unlock(&dev->doneq_lock); + } else { + spin_lock_irq(&dev->doneq_lock); + bio = ssd_blist_get(&dev->doneq); + spin_unlock_irq(&dev->doneq_lock); + } + + while (bio) { + next = bio->bi_next; + bio->bi_next = NULL; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, 0); +#else + bio_endio(bio, bio->bi_size, 0); +#endif + atomic_dec(&dev->in_doneq); + bio = next; + } + + cond_resched(); + +#ifdef SSD_ESCAPE_IRQ + if (unlikely(smp_processor_id() == dev->irq_cpu)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) + cpumask_setall(&new_mask); + cpumask_clear_cpu(dev->irq_cpu, &new_mask); + set_cpus_allowed_ptr(current, &new_mask); +#else + cpus_setall(new_mask); + cpu_clear(dev->irq_cpu, new_mask); + set_cpus_allowed(current, new_mask); +#endif + } +#endif + } + } + return 0; +} + +static int ssd_send_thread(void *data) +{ + struct ssd_device *dev; + struct bio *bio; + struct bio *next; +#ifdef SSD_ESCAPE_IRQ + cpumask_t new_mask; +#endif + + if (!data) { + return -EINVAL; + } + dev = data; + + //set_user_nice(current, -5); + + while (!kthread_should_stop()) { + wait_event_interruptible(dev->send_waitq, (atomic_read(&dev->in_sendq) || kthread_should_stop())); + + while (atomic_read(&dev->in_sendq)) { + spin_lock(&dev->sendq_lock); + bio = ssd_blist_get(&dev->sendq); + spin_unlock(&dev->sendq_lock); + + while (bio) { + next = bio->bi_next; + bio->bi_next = NULL; +#ifdef SSD_QUEUE_PBIO + if (test_and_clear_bit(BIO_SSD_PBIO, &bio->bi_flags)) { + __ssd_submit_pbio(dev, bio, 1); + } else { + ssd_submit_bio(dev, bio, 1); + } +#else + ssd_submit_bio(dev, bio, 1); +#endif + atomic_dec(&dev->in_sendq); + bio = next; + } + + cond_resched(); + +#ifdef SSD_ESCAPE_IRQ + if (unlikely(smp_processor_id() == dev->irq_cpu)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) + cpumask_setall(&new_mask); + cpumask_clear_cpu(dev->irq_cpu, &new_mask); + set_cpus_allowed_ptr(current, &new_mask); +#else + cpus_setall(new_mask); + cpu_clear(dev->irq_cpu, new_mask); + set_cpus_allowed(current, new_mask); +#endif + } +#endif + } + } + + return 0; +} + +static void ssd_cleanup_thread(struct ssd_device *dev) +{ + kthread_stop(dev->send_thread); + kthread_stop(dev->done_thread); +} + +static int ssd_init_thread(struct ssd_device *dev) +{ + int ret; + + atomic_set(&dev->in_doneq, 0); + atomic_set(&dev->in_sendq, 0); + + spin_lock_init(&dev->doneq_lock); + spin_lock_init(&dev->sendq_lock); + + ssd_blist_init(&dev->doneq); + ssd_blist_init(&dev->sendq); + + init_waitqueue_head(&dev->done_waitq); + init_waitqueue_head(&dev->send_waitq); + + dev->done_thread = kthread_run(ssd_done_thread, dev, "%s/d", dev->name); + if (IS_ERR(dev->done_thread)) { + ret = PTR_ERR(dev->done_thread); + goto out_done_thread; + } + + dev->send_thread = kthread_run(ssd_send_thread, dev, "%s/s", dev->name); + if (IS_ERR(dev->send_thread)) { + ret = PTR_ERR(dev->send_thread); + goto out_send_thread; + } + + return 0; + +out_send_thread: + kthread_stop(dev->done_thread); +out_done_thread: + return ret; +} + +/* dcmd pool */ +static void ssd_put_dcmd(struct ssd_dcmd *dcmd) +{ + struct ssd_device *dev = (struct ssd_device *)dcmd->dev; + + spin_lock(&dev->dcmd_lock); + list_add_tail(&dcmd->list, &dev->dcmd_list); + spin_unlock(&dev->dcmd_lock); +} + +static struct ssd_dcmd *ssd_get_dcmd(struct ssd_device *dev) +{ + struct ssd_dcmd *dcmd = NULL; + + spin_lock(&dev->dcmd_lock); + if (!list_empty(&dev->dcmd_list)) { + dcmd = list_entry(dev->dcmd_list.next, + struct ssd_dcmd, list); + list_del_init(&dcmd->list); + } + spin_unlock(&dev->dcmd_lock); + + return dcmd; +} + +static void ssd_cleanup_dcmd(struct ssd_device *dev) +{ + kfree(dev->dcmd); +} + +static int ssd_init_dcmd(struct ssd_device *dev) +{ + struct ssd_dcmd *dcmd; + int dcmd_sz = sizeof(struct ssd_dcmd)*dev->hw_info.cmd_fifo_sz; + int i; + + spin_lock_init(&dev->dcmd_lock); + INIT_LIST_HEAD(&dev->dcmd_list); + init_waitqueue_head(&dev->dcmd_wq); + + dev->dcmd = kmalloc(dcmd_sz, GFP_KERNEL); + if (!dev->dcmd) { + hio_warn("%s: can not alloc dcmd\n", dev->name); + goto out_alloc_dcmd; + } + memset(dev->dcmd, 0, dcmd_sz); + + for (i=0, dcmd=dev->dcmd; i<(int)dev->hw_info.cmd_fifo_sz; i++, dcmd++) { + dcmd->dev = dev; + INIT_LIST_HEAD(&dcmd->list); + list_add_tail(&dcmd->list, &dev->dcmd_list); + } + + return 0; + +out_alloc_dcmd: + return -ENOMEM; +} + +static void ssd_put_dmsg(void *msg) +{ + struct ssd_dcmd *dcmd = container_of(msg, struct ssd_dcmd, msg); + struct ssd_device *dev = (struct ssd_device *)dcmd->dev; + + memset(dcmd->msg, 0, SSD_DCMD_MAX_SZ); + ssd_put_dcmd(dcmd); + wake_up(&dev->dcmd_wq); +} + +static void *ssd_get_dmsg(struct ssd_device *dev) +{ + struct ssd_dcmd *dcmd = ssd_get_dcmd(dev); + + while (!dcmd) { + DEFINE_WAIT(wait); + prepare_to_wait_exclusive(&dev->dcmd_wq, &wait, TASK_UNINTERRUPTIBLE); + schedule(); + + dcmd = ssd_get_dcmd(dev); + + finish_wait(&dev->dcmd_wq, &wait); + } + return dcmd->msg; +} + +/* do direct cmd */ +static int ssd_do_request(struct ssd_device *dev, int rw, void *msg, int *done) +{ + DECLARE_COMPLETION(wait); + struct ssd_cmd *cmd; + int tag; + int ret = 0; + + tag = ssd_get_tag(dev, 1); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->nsegs = 1; + memcpy(cmd->msg, msg, SSD_DCMD_MAX_SZ); + ((struct ssd_rw_msg *)cmd->msg)->tag = tag; + + cmd->waiting = &wait; + + dev->scmd(cmd); + + wait_for_completion(cmd->waiting); + cmd->waiting = NULL; + + if (cmd->errors == -ETIMEDOUT) { + ret = cmd->errors; + } else if (cmd->errors) { + ret = -EIO; + } + + if (done != NULL) { + *done = cmd->nr_log; + } + ssd_put_tag(dev, cmd->tag); + + return ret; +} + +static int ssd_do_barrier_request(struct ssd_device *dev, int rw, void *msg, int *done) +{ + DECLARE_COMPLETION(wait); + struct ssd_cmd *cmd; + int tag; + int ret = 0; + + tag = ssd_barrier_get_tag(dev); + if (tag < 0) { + return -EBUSY; + } + + cmd = &dev->cmd[tag]; + cmd->nsegs = 1; + memcpy(cmd->msg, msg, SSD_DCMD_MAX_SZ); + ((struct ssd_rw_msg *)cmd->msg)->tag = tag; + + cmd->waiting = &wait; + + dev->scmd(cmd); + + wait_for_completion(cmd->waiting); + cmd->waiting = NULL; + + if (cmd->errors == -ETIMEDOUT) { + ret = cmd->errors; + } else if (cmd->errors) { + ret = -EIO; + } + + if (done != NULL) { + *done = cmd->nr_log; + } + ssd_barrier_put_tag(dev, cmd->tag); + + return ret; +} + +#ifdef SSD_OT_PROTECT +static void ssd_check_temperature(struct ssd_device *dev, int temp) +{ + uint64_t val; + uint32_t off; + int cur; + int i; + + if (mode != SSD_DRV_MODE_STANDARD) { + return; + } + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + } + + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_CTRL_TEMP_REG0 + i * sizeof(uint64_t); + + val = ssd_reg_read(dev->ctrlp + off); + if (val == 0xffffffffffffffffull) { + continue; + } + + cur = (int)CUR_TEMP(val); + if (cur >= temp) { + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) { + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) { + hio_warn("%s: Over temperature, please check the fans.\n", dev->name); + dev->ot_delay = SSD_OT_DELAY; + } + } + return; + } + } + + if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) { + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) { + hio_warn("%s: Temperature is OK.\n", dev->name); + dev->ot_delay = 0; + } + } +} +#endif + +static int ssd_get_ot_status(struct ssd_device *dev, int *status) +{ + uint32_t off; + uint32_t val; + int i; + + if (!dev || !status) { + return -EINVAL; + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_2) { + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_READ_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if ((val >> 22) & 0x1) { + *status = 1; + goto out; + } + + + off = SSD_WRITE_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if ((val >> 22) & 0x1) { + *status = 1; + goto out; + } + } + } else { + *status = !!dev->ot_delay; + } + +out: + return 0; +} + +static void ssd_set_ot_protect(struct ssd_device *dev, int protect) +{ + uint32_t off; + uint32_t val; + int i; + + mutex_lock(&dev->fw_mutex); + + dev->ot_protect = !!protect; + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_2) { + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_READ_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if (dev->ot_protect) { + val |= (1U << 21); + } else { + val &= ~(1U << 21); + } + ssd_reg32_write(dev->ctrlp + off, val); + + + off = SSD_WRITE_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ); + val = ssd_reg32_read(dev->ctrlp + off); + if (dev->ot_protect) { + val |= (1U << 21); + } else { + val &= ~(1U << 21); + } + ssd_reg32_write(dev->ctrlp + off, val); + } + } + + mutex_unlock(&dev->fw_mutex); +} + +static int ssd_init_ot_protect(struct ssd_device *dev) +{ + ssd_set_ot_protect(dev, ot_protect); + +#ifdef SSD_OT_PROTECT + ssd_check_temperature(dev, SSD_OT_TEMP); +#endif + + return 0; +} + +/* log */ +static int ssd_read_log(struct ssd_device *dev, int ctrl_idx, void *buf, int *nr_log) +{ + struct ssd_log_op_msg *msg; + struct ssd_log_msg *lmsg; + dma_addr_t buf_dma; + size_t length = dev->hw_info.log_sz; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl) { + return -EINVAL; + } + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + msg = (struct ssd_log_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + lmsg = (struct ssd_log_msg *)msg; + lmsg->fun = SSD_FUNC_READ_LOG; + lmsg->ctrl_idx = ctrl_idx; + lmsg->buf = buf_dma; + } else { + msg->fun = SSD_FUNC_READ_LOG; + msg->ctrl_idx = ctrl_idx; + msg->buf = buf_dma; + } + + ret = ssd_do_request(dev, READ, msg, nr_log); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +#define SSD_LOG_PRINT_BUF_SZ 256 +static int ssd_parse_log(struct ssd_device *dev, struct ssd_log *log, int print) +{ + struct ssd_log_desc *log_desc = ssd_log_desc; + struct ssd_log_entry *le; + char *sn = NULL; + char print_buf[SSD_LOG_PRINT_BUF_SZ]; + int print_len; + + le = &log->le; + + /* find desc */ + while (log_desc->event != SSD_UNKNOWN_EVENT) { + if (log_desc->event == le->event) { + break; + } + log_desc++; + } + + if (!print) { + goto out; + } + + if (log_desc->level < log_level) { + goto out; + } + + /* parse */ + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + sn = dev->label.sn; + } else { + sn = dev->labelv3.barcode; + } + + print_len = snprintf(print_buf, SSD_LOG_PRINT_BUF_SZ, "%s (%s): <%#x>", dev->name, sn, le->event); + + if (log->ctrl_idx != SSD_LOG_SW_IDX) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " controller %d", log->ctrl_idx); + } + + switch (log_desc->data) { + case SSD_LOG_DATA_NONE: + break; + case SSD_LOG_DATA_LOC: + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " flash %d", le->data.loc.flash); + if (log_desc->sblock) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " block %d", le->data.loc.block); + } + if (log_desc->spage) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " page %d", le->data.loc.page); + } + } else { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " flash %d", le->data.loc1.flash); + if (log_desc->sblock) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " block %d", le->data.loc1.block); + } + if (log_desc->spage) { + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " page %d", le->data.loc1.page); + } + } + break; + case SSD_LOG_DATA_HEX: + print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " info %#x", le->data.val); + break; + default: + break; + } + /*print_len += */snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), ": %s", log_desc->desc); + + switch (log_desc->level) { + case SSD_LOG_LEVEL_INFO: + hio_info("%s\n", print_buf); + break; + case SSD_LOG_LEVEL_NOTICE: + hio_note("%s\n", print_buf); + break; + case SSD_LOG_LEVEL_WARNING: + hio_warn("%s\n", print_buf); + break; + case SSD_LOG_LEVEL_ERR: + hio_err("%s\n", print_buf); + //printk(KERN_ERR MODULE_NAME": some exception occurred, please check the data or refer to FAQ."); + break; + default: + hio_warn("%s\n", print_buf); + break; + } + +out: + return log_desc->level; +} + +static int ssd_bm_get_sfstatus(struct ssd_device *dev, uint16_t *status); +static int ssd_switch_wmode(struct ssd_device *dev, int wmode); + + +static int ssd_handle_event(struct ssd_device *dev, uint16_t event, int level) +{ + int ret = 0; + + switch (event) { + case SSD_LOG_OVER_TEMP: { +#ifdef SSD_OT_PROTECT + if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) { + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) { + hio_warn("%s: Over temperature, please check the fans.\n", dev->name); + dev->ot_delay = SSD_OT_DELAY; + } + } +#endif + break; + } + + case SSD_LOG_NORMAL_TEMP: { +#ifdef SSD_OT_PROTECT + /* need to check all controller's temperature */ + ssd_check_temperature(dev, SSD_OT_TEMP_HYST); +#endif + break; + } + + case SSD_LOG_BATTERY_FAULT: { + uint16_t sfstatus; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + if (!ssd_bm_get_sfstatus(dev, &sfstatus)) { + ssd_gen_swlog(dev, SSD_LOG_BM_SFSTATUS, sfstatus); + } + } + + if (!test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_switch_wmode(dev, dev->user_wmode); + } + break; + } + + case SSD_LOG_BATTERY_OK: { + if (test_and_clear_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_switch_wmode(dev, dev->user_wmode); + } + break; + } + + case SSD_LOG_BOARD_VOLT_FAULT: { + ssd_mon_boardvolt(dev); + break; + } + + case SSD_LOG_CLEAR_LOG: { + /* update smart */ + memset(&dev->smart.log_info, 0, sizeof(struct ssd_log_info)); + break; + } + + case SSD_LOG_CAP_VOLT_FAULT: + case SSD_LOG_CAP_LEARN_FAULT: + case SSD_LOG_CAP_SHORT_CIRCUIT: { + if (!test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_switch_wmode(dev, dev->user_wmode); + } + break; + } + + default: + break; + } + + /* ssd event call */ + if (dev->event_call) { + dev->event_call(dev->gd, event, level); + + /* FIXME */ + if (SSD_LOG_CAP_VOLT_FAULT == event || SSD_LOG_CAP_LEARN_FAULT == event || SSD_LOG_CAP_SHORT_CIRCUIT == event) { + dev->event_call(dev->gd, SSD_LOG_BATTERY_FAULT, level); + } + } + + return ret; +} + +static int ssd_save_log(struct ssd_device *dev, struct ssd_log *log) +{ + uint32_t off, size; + void *internal_log; + int ret = 0; + + mutex_lock(&dev->internal_log_mutex); + + size = sizeof(struct ssd_log); + off = dev->internal_log.nr_log * size; + + if (off == dev->rom_info.log_sz) { + if (dev->internal_log.nr_log == dev->smart.log_info.nr_log) { + hio_warn("%s: internal log is full\n", dev->name); + } + goto out; + } + + internal_log = dev->internal_log.log + off; + memcpy(internal_log, log, size); + + if (dev->protocol_info.ver > SSD_PROTOCOL_V3) { + off += dev->rom_info.log_base; + + ret = ssd_spi_write(dev, log, off, size); + if (ret) { + goto out; + } + } + + dev->internal_log.nr_log++; + +out: + mutex_unlock(&dev->internal_log_mutex); + return ret; +} + +static int ssd_save_swlog(struct ssd_device *dev, uint16_t event, uint32_t data) +{ + struct ssd_log log; + struct timeval tv; + int level; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + memset(&log, 0, sizeof(struct ssd_log)); + + do_gettimeofday(&tv); + log.ctrl_idx = SSD_LOG_SW_IDX; + log.time = tv.tv_sec; + log.le.event = event; + log.le.data.val = data; + + level = ssd_parse_log(dev, &log, 0); + if (level >= SSD_LOG_LEVEL) { + ret = ssd_save_log(dev, &log); + } + + /* set alarm */ + if (SSD_LOG_LEVEL_ERR == level) { + ssd_set_alarm(dev); + } + + /* update smart */ + dev->smart.log_info.nr_log++; + dev->smart.log_info.stat[level]++; + + /* handle event */ + ssd_handle_event(dev, event, level); + + return ret; +} + +static int ssd_gen_swlog(struct ssd_device *dev, uint16_t event, uint32_t data) +{ + struct ssd_log_entry le; + int ret; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + /* slave port ? */ + if (dev->slave) { + return 0; + } + + memset(&le, 0, sizeof(struct ssd_log_entry)); + le.event = event; + le.data.val = data; + + ret = sfifo_put(&dev->log_fifo, &le); + if (ret) { + return ret; + } + + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->log_work); + } + + return 0; +} + +static int ssd_do_swlog(struct ssd_device *dev) +{ + struct ssd_log_entry le; + int ret = 0; + + memset(&le, 0, sizeof(struct ssd_log_entry)); + while (!sfifo_get(&dev->log_fifo, &le)) { + ret = ssd_save_swlog(dev, le.event, le.data.val); + if (ret) { + break; + } + } + + return ret; +} + +static int __ssd_clear_log(struct ssd_device *dev) +{ + uint32_t off, length; + int ret; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (dev->internal_log.nr_log == 0) { + return 0; + } + + mutex_lock(&dev->internal_log_mutex); + + off = dev->rom_info.log_base; + length = dev->rom_info.log_sz; + + ret = ssd_spi_erase(dev, off, length); + if (ret) { + hio_warn("%s: log erase: failed\n", dev->name); + goto out; + } + + dev->internal_log.nr_log = 0; + +out: + mutex_unlock(&dev->internal_log_mutex); + return ret; +} + +static int ssd_clear_log(struct ssd_device *dev) +{ + int ret; + + ret = __ssd_clear_log(dev); + if(!ret) { + ssd_gen_swlog(dev, SSD_LOG_CLEAR_LOG, 0); + } + + return ret; +} + +static int ssd_do_log(struct ssd_device *dev, int ctrl_idx, void *buf) +{ + struct ssd_log_entry *le; + struct ssd_log log; + struct timeval tv; + int nr_log = 0; + int level; + int ret = 0; + + ret = ssd_read_log(dev, ctrl_idx, buf, &nr_log); + if (ret) { + return ret; + } + + do_gettimeofday(&tv); + + log.time = tv.tv_sec; + log.ctrl_idx = ctrl_idx; + + le = (ssd_log_entry_t *)buf; + while (nr_log > 0) { + memcpy(&log.le, le, sizeof(struct ssd_log_entry)); + + level = ssd_parse_log(dev, &log, 1); + if (level >= SSD_LOG_LEVEL) { + ssd_save_log(dev, &log); + } + + /* set alarm */ + if (SSD_LOG_LEVEL_ERR == level) { + ssd_set_alarm(dev); + } + + dev->smart.log_info.nr_log++; + if (SSD_LOG_SEU_FAULT != le->event && SSD_LOG_SEU_FAULT1 != le->event) { + dev->smart.log_info.stat[level]++; + } else { + /* SEU fault */ + + /* log to the volatile log info */ + dev->log_info.nr_log++; + dev->log_info.stat[level]++; + + /* do something */ + dev->reload_fw = 1; + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FLAG); + + /*dev->readonly = 1; + set_disk_ro(dev->gd, 1); + hio_warn("%s: switched to read-only mode.\n", dev->name);*/ + } + + /* handle event */ + ssd_handle_event(dev, le->event, level); + + le++; + nr_log--; + } + + return 0; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_log_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_log_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, log_work); +#endif + int i; + int ret; + + if (!test_bit(SSD_LOG_ERR, &dev->state) && test_bit(SSD_ONLINE, &dev->state)) { + /* alloc log buf */ + if (!dev->log_buf) { + dev->log_buf = kmalloc(dev->hw_info.log_sz, GFP_KERNEL); + if (!dev->log_buf) { + hio_warn("%s: ssd_log_worker: no mem\n", dev->name); + return; + } + } + + /* get log */ + if (test_and_clear_bit(SSD_LOG_HW, &dev->state)) { + for (i=0; ihw_info.nr_ctrl; i++) { + ret = ssd_do_log(dev, i, dev->log_buf); + if (ret) { + (void)test_and_set_bit(SSD_LOG_ERR, &dev->state); + hio_warn("%s: do log fail\n", dev->name); + } + } + } + } + + ret = ssd_do_swlog(dev); + if (ret) { + hio_warn("%s: do swlog fail\n", dev->name); + } +} + +static void ssd_cleanup_log(struct ssd_device *dev) +{ + if (dev->log_buf) { + kfree(dev->log_buf); + dev->log_buf = NULL; + } + + sfifo_free(&dev->log_fifo); + + if (dev->internal_log.log) { + vfree(dev->internal_log.log); + dev->internal_log.log = NULL; + } +} + +static int ssd_init_log(struct ssd_device *dev) +{ + struct ssd_log *log; + uint32_t off, size; + uint32_t len = 0; + int ret = 0; + + mutex_init(&dev->internal_log_mutex); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + INIT_WORK(&dev->log_work, ssd_log_worker, dev); +#else + INIT_WORK(&dev->log_work, ssd_log_worker); +#endif + + off = dev->rom_info.log_base; + size = dev->rom_info.log_sz; + + dev->internal_log.log = vmalloc(size); + if (!dev->internal_log.log) { + ret = -ENOMEM; + goto out_alloc_log; + } + + ret = sfifo_alloc(&dev->log_fifo, SSD_LOG_FIFO_SZ, sizeof(struct ssd_log_entry)); + if (ret < 0) { + goto out_alloc_log_fifo; + } + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + log = (struct ssd_log *)dev->internal_log.log; + while (len < size) { + ret = ssd_spi_read(dev, log, off, sizeof(struct ssd_log)); + if (ret) { + goto out_read_log; + } + + if (log->ctrl_idx == 0xff) { + break; + } + + dev->internal_log.nr_log++; + log++; + len += sizeof(struct ssd_log); + off += sizeof(struct ssd_log); + } + + return 0; + +out_read_log: + sfifo_free(&dev->log_fifo); +out_alloc_log_fifo: + vfree(dev->internal_log.log); + dev->internal_log.log = NULL; + dev->internal_log.nr_log = 0; +out_alloc_log: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +/* work queue */ +static void ssd_stop_workq(struct ssd_device *dev) +{ + test_and_clear_bit(SSD_INIT_WORKQ, &dev->state); + flush_workqueue(dev->workq); +} + +static void ssd_start_workq(struct ssd_device *dev) +{ + (void)test_and_set_bit(SSD_INIT_WORKQ, &dev->state); + + /* log ? */ + queue_work(dev->workq, &dev->log_work); +} + +static void ssd_cleanup_workq(struct ssd_device *dev) +{ + flush_workqueue(dev->workq); + destroy_workqueue(dev->workq); + dev->workq = NULL; +} + +static int ssd_init_workq(struct ssd_device *dev) +{ + int ret = 0; + + dev->workq = create_singlethread_workqueue(dev->name); + if (!dev->workq) { + ret = -ESRCH; + goto out; + } + +out: + return ret; +} + +/* rom */ +static int ssd_init_rom_info(struct ssd_device *dev) +{ + uint32_t val; + + mutex_init(&dev->spi_mutex); + mutex_init(&dev->i2c_mutex); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + /* fix bug: read data to clear status */ + (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_RDATA); + + dev->rom_info.size = SSD_ROM_SIZE; + dev->rom_info.block_size = SSD_ROM_BLK_SIZE; + dev->rom_info.page_size = SSD_ROM_PAGE_SIZE; + + dev->rom_info.bridge_fw_base = SSD_ROM_BRIDGE_FW_BASE; + dev->rom_info.bridge_fw_sz = SSD_ROM_BRIDGE_FW_SIZE; + dev->rom_info.nr_bridge_fw = SSD_ROM_NR_BRIDGE_FW; + + dev->rom_info.ctrl_fw_base = SSD_ROM_CTRL_FW_BASE; + dev->rom_info.ctrl_fw_sz = SSD_ROM_CTRL_FW_SIZE; + dev->rom_info.nr_ctrl_fw = SSD_ROM_NR_CTRL_FW; + + dev->rom_info.log_sz = SSD_ROM_LOG_SZ; + + dev->rom_info.vp_base = SSD_ROM_VP_BASE; + dev->rom_info.label_base = SSD_ROM_LABEL_BASE; + } else if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_INFO_REG); + dev->rom_info.size = 0x100000 * (1U << (val & 0xFF)); + dev->rom_info.block_size = 0x10000 * (1U << ((val>>8) & 0xFF)); + dev->rom_info.page_size = (val>>16) & 0xFFFF; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_BRIDGE_FW_INFO_REG); + dev->rom_info.bridge_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.bridge_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_bridge_fw = ((val >> 30) & 0x3) + 1; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_CTRL_FW_INFO_REG); + dev->rom_info.ctrl_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.ctrl_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_ctrl_fw = ((val >> 30) & 0x3) + 1; + + dev->rom_info.bm_fw_base = dev->rom_info.ctrl_fw_base + (dev->rom_info.nr_ctrl_fw * dev->rom_info.ctrl_fw_sz); + dev->rom_info.bm_fw_sz = SSD_PV3_ROM_BM_FW_SZ; + dev->rom_info.nr_bm_fw = SSD_PV3_ROM_NR_BM_FW; + + dev->rom_info.log_base = dev->rom_info.bm_fw_base + (dev->rom_info.nr_bm_fw * dev->rom_info.bm_fw_sz); + dev->rom_info.log_sz = SSD_ROM_LOG_SZ; + + dev->rom_info.smart_base = dev->rom_info.log_base + dev->rom_info.log_sz; + dev->rom_info.smart_sz = SSD_PV3_ROM_SMART_SZ; + dev->rom_info.nr_smart = SSD_PV3_ROM_NR_SMART; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_VP_INFO_REG); + dev->rom_info.vp_base = dev->rom_info.block_size * val; + dev->rom_info.label_base = dev->rom_info.vp_base + dev->rom_info.block_size; + if (dev->rom_info.label_base >= dev->rom_info.size) { + dev->rom_info.label_base = dev->rom_info.vp_base - dev->rom_info.block_size; + } + } else { + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_INFO_REG); + dev->rom_info.size = 0x100000 * (1U << (val & 0xFF)); + dev->rom_info.block_size = 0x10000 * (1U << ((val>>8) & 0xFF)); + dev->rom_info.page_size = (val>>16) & 0xFFFF; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_BRIDGE_FW_INFO_REG); + dev->rom_info.bridge_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.bridge_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_bridge_fw = ((val >> 30) & 0x3) + 1; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_CTRL_FW_INFO_REG); + dev->rom_info.ctrl_fw_base = dev->rom_info.block_size * (val & 0xFFFF); + dev->rom_info.ctrl_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF); + dev->rom_info.nr_ctrl_fw = ((val >> 30) & 0x3) + 1; + + val = ssd_reg32_read(dev->ctrlp + SSD_ROM_VP_INFO_REG); + dev->rom_info.vp_base = dev->rom_info.block_size * val; + dev->rom_info.label_base = dev->rom_info.vp_base - SSD_PV3_2_ROM_SEC_SZ; + + dev->rom_info.nr_smart = SSD_PV3_ROM_NR_SMART; + dev->rom_info.smart_sz = SSD_PV3_2_ROM_SEC_SZ; + dev->rom_info.smart_base = dev->rom_info.label_base - (dev->rom_info.smart_sz * dev->rom_info.nr_smart); + if (dev->rom_info.smart_sz > dev->rom_info.block_size) { + dev->rom_info.smart_sz = dev->rom_info.block_size; + } + + dev->rom_info.log_sz = SSD_PV3_2_ROM_LOG_SZ; + dev->rom_info.log_base = dev->rom_info.smart_base - dev->rom_info.log_sz; + } + + return ssd_init_spi(dev); +} + +/* smart */ +static int ssd_update_smart(struct ssd_device *dev, struct ssd_smart *smart) +{ + struct timeval tv; + uint64_t run_time; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + struct hd_struct *part; + int cpu; +#endif + int i, j; + int ret = 0; + + if (!test_bit(SSD_INIT_BD, &dev->state)) { + return 0; + } + + do_gettimeofday(&tv); + if ((uint64_t)tv.tv_sec < dev->uptime) { + run_time = 0; + } else { + run_time = tv.tv_sec - dev->uptime; + } + + /* avoid frequently update */ + if (run_time >= 60) { + ret = 1; + } + + /* io stat */ + smart->io_stat.run_time += run_time; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) + cpu = part_stat_lock(); + part = &dev->gd->part0; + part_round_stats(cpu, part); + part_stat_unlock(); + + smart->io_stat.nr_read += part_stat_read(part, ios[READ]); + smart->io_stat.nr_write += part_stat_read(part, ios[WRITE]); + smart->io_stat.rsectors += part_stat_read(part, sectors[READ]); + smart->io_stat.wsectors += part_stat_read(part, sectors[WRITE]); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)) + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + + smart->io_stat.nr_read += disk_stat_read(dev->gd, ios[READ]); + smart->io_stat.nr_write += disk_stat_read(dev->gd, ios[WRITE]); + smart->io_stat.rsectors += disk_stat_read(dev->gd, sectors[READ]); + smart->io_stat.wsectors += disk_stat_read(dev->gd, sectors[WRITE]); +#else + preempt_disable(); + disk_round_stats(dev->gd); + preempt_enable(); + + smart->io_stat.nr_read += disk_stat_read(dev->gd, reads); + smart->io_stat.nr_write += disk_stat_read(dev->gd, writes); + smart->io_stat.rsectors += disk_stat_read(dev->gd, read_sectors); + smart->io_stat.wsectors += disk_stat_read(dev->gd, write_sectors); +#endif + + smart->io_stat.nr_to += atomic_read(&dev->tocnt); + + for (i=0; inr_queue; i++) { + smart->io_stat.nr_rwerr += dev->queue[i].io_stat.nr_rwerr; + smart->io_stat.nr_ioerr += dev->queue[i].io_stat.nr_ioerr; + } + + for (i=0; inr_queue; i++) { + for (j=0; jecc_info.bitflip[j] += dev->queue[i].ecc_info.bitflip[j]; + } + } + + //dev->uptime = tv.tv_sec; + + return ret; +} + +static int ssd_clear_smart(struct ssd_device *dev) +{ + struct timeval tv; + uint64_t sversion; + uint32_t off, length; + int i; + int ret; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + /* clear smart */ + off = dev->rom_info.smart_base; + length = dev->rom_info.smart_sz * dev->rom_info.nr_smart; + + ret = ssd_spi_erase(dev, off, length); + if (ret) { + hio_warn("%s: info erase: failed\n", dev->name); + goto out; + } + + sversion = dev->smart.version; + + memset(&dev->smart, 0, sizeof(struct ssd_smart)); + dev->smart.version = sversion + 1; + dev->smart.magic = SSD_SMART_MAGIC; + + /* clear all tmp acc */ + for (i=0; inr_queue; i++) { + memset(&(dev->queue[i].io_stat), 0, sizeof(struct ssd_io_stat)); + memset(&(dev->queue[i].ecc_info), 0, sizeof(struct ssd_ecc_info)); + } + + atomic_set(&dev->tocnt, 0); + + /* clear tmp log info */ + memset(&dev->log_info, 0, sizeof(struct ssd_log_info)); + + do_gettimeofday(&tv); + dev->uptime = tv.tv_sec; + + /* clear alarm ? */ + //ssd_clear_alarm(dev); +out: + return ret; +} + +static int ssd_save_smart(struct ssd_device *dev) +{ + uint32_t off, size; + int i; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (!ssd_update_smart(dev, &dev->smart)) { + return 0; + } + + dev->smart.version++; + + for (i=0; irom_info.nr_smart; i++) { + off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i); + size = dev->rom_info.smart_sz; + + ret = ssd_spi_erase(dev, off, size); + if (ret) { + hio_warn("%s: info erase failed\n", dev->name); + goto out; + } + + size = sizeof(struct ssd_smart); + + ret = ssd_spi_write(dev, &dev->smart, off, size); + if (ret) { + hio_warn("%s: info write failed\n", dev->name); + goto out; + } + + //xx + } + +out: + return ret; +} + +static int ssd_init_smart(struct ssd_device *dev) +{ + struct ssd_smart *smart; + struct timeval tv; + uint32_t off, size; + int i; + int ret = 0; + + do_gettimeofday(&tv); + dev->uptime = tv.tv_sec; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + smart = kmalloc(sizeof(struct ssd_smart) * SSD_ROM_NR_SMART_MAX, GFP_KERNEL); + if (!smart) { + ret = -ENOMEM; + goto out_nomem; + } + + memset(&dev->smart, 0, sizeof(struct ssd_smart)); + + /* read smart */ + for (i=0; irom_info.nr_smart; i++) { + memset(&smart[i], 0, sizeof(struct ssd_smart)); + + off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i); + size = sizeof(struct ssd_smart); + + ret = ssd_spi_read(dev, &smart[i], off, size); + if (ret) { + hio_warn("%s: info read failed\n", dev->name); + goto out; + } + + if (smart[i].magic != SSD_SMART_MAGIC) { + smart[i].magic = 0; + smart[i].version = 0; + continue; + } + + if (smart[i].version > dev->smart.version) { + memcpy(&dev->smart, &smart[i], sizeof(struct ssd_smart)); + } + } + + if (dev->smart.magic != SSD_SMART_MAGIC) { + /* first time power up */ + dev->smart.magic = SSD_SMART_MAGIC; + dev->smart.version = 1; + } + + /* check log info */ + { + struct ssd_log_info log_info; + struct ssd_log *log = (struct ssd_log *)dev->internal_log.log; + + memset(&log_info, 0, sizeof(struct ssd_log_info)); + + while (log_info.nr_log < dev->internal_log.nr_log) { + /* skip the volatile log info */ + if (SSD_LOG_SEU_FAULT != log->le.event && SSD_LOG_SEU_FAULT1 != log->le.event) { + log_info.stat[ssd_parse_log(dev, log, 0)]++; + } + + log_info.nr_log++; + log++; + } + + /* check */ + for (i=(SSD_LOG_NR_LEVEL-1); i>=0; i--) { + if (log_info.stat[i] > dev->smart.log_info.stat[i]) { + /* unclean */ + memcpy(&dev->smart.log_info, &log_info, sizeof(struct ssd_log_info)); + dev->smart.version++; + break; + } + } + } + + for (i=0; irom_info.nr_smart; i++) { + if (smart[i].magic == SSD_SMART_MAGIC && smart[i].version == dev->smart.version) { + continue; + } + + off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i); + size = dev->rom_info.smart_sz; + + ret = ssd_spi_erase(dev, off, size); + if (ret) { + hio_warn("%s: info erase failed\n", dev->name); + goto out; + } + + size = sizeof(struct ssd_smart); + ret = ssd_spi_write(dev, &dev->smart, off, size); + if (ret) { + hio_warn("%s: info write failed\n", dev->name); + goto out; + } + + //xx + } + + /* sync smart with alarm led */ + if (dev->smart.io_stat.nr_to || dev->smart.io_stat.nr_rwerr || dev->smart.log_info.stat[SSD_LOG_LEVEL_ERR]) { + hio_warn("%s: some fault found in the history info\n", dev->name); + ssd_set_alarm(dev); + } + +out: + kfree(smart); +out_nomem: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +/* bm */ +static int __ssd_bm_get_version(struct ssd_device *dev, uint16_t *ver) +{ + struct ssd_bm_manufacturer_data bm_md = {0}; + uint16_t sc_id = SSD_BM_SYSTEM_DATA_SUBCLASS_ID; + uint8_t cmd; + int ret = 0; + + if (!dev || !ver) { + return -EINVAL; + } + + mutex_lock(&dev->bm_mutex); + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID; + ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&sc_id); + if (ret) { + goto out; + } + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1; + ret = ssd_smbus_read_block(dev, SSD_BM_SLAVE_ADDRESS, cmd, sizeof(struct ssd_bm_manufacturer_data), (uint8_t *)&bm_md); + if (ret) { + goto out; + } + + if (bm_md.firmware_ver & 0xF000) { + ret = -EIO; + goto out; + } + + *ver = bm_md.firmware_ver; + +out: + mutex_unlock(&dev->bm_mutex); + return ret; +} + +static int ssd_bm_get_version(struct ssd_device *dev, uint16_t *ver) +{ + uint16_t tmp = 0; + int i = SSD_BM_RETRY_MAX; + int ret = 0; + + while (i-- > 0) { + ret = __ssd_bm_get_version(dev, &tmp); + if (!ret) { + break; + } + } + if (ret) { + return ret; + } + + *ver = tmp; + + return 0; +} + +static int __ssd_bm_nr_cap(struct ssd_device *dev, int *nr_cap) +{ + struct ssd_bm_configuration_registers bm_cr; + uint16_t sc_id = SSD_BM_CONFIGURATION_REGISTERS_ID; + uint8_t cmd; + int ret; + + mutex_lock(&dev->bm_mutex); + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID; + ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&sc_id); + if (ret) { + goto out; + } + + cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1; + ret = ssd_smbus_read_block(dev, SSD_BM_SLAVE_ADDRESS, cmd, sizeof(struct ssd_bm_configuration_registers), (uint8_t *)&bm_cr); + if (ret) { + goto out; + } + + if (bm_cr.operation_cfg.cc == 0 || bm_cr.operation_cfg.cc > 4) { + ret = -EIO; + goto out; + } + + *nr_cap = bm_cr.operation_cfg.cc + 1; + +out: + mutex_unlock(&dev->bm_mutex); + return ret; +} + +static int ssd_bm_nr_cap(struct ssd_device *dev, int *nr_cap) +{ + int tmp = 0; + int i = SSD_BM_RETRY_MAX; + int ret = 0; + + while (i-- > 0) { + ret = __ssd_bm_nr_cap(dev, &tmp); + if (!ret) { + break; + } + } + if (ret) { + return ret; + } + + *nr_cap = tmp; + + return 0; +} + +static int ssd_bm_enter_cap_learning(struct ssd_device *dev) +{ + uint16_t buf = SSD_BM_ENTER_CAP_LEARNING; + uint8_t cmd = SSD_BM_MANUFACTURERACCESS; + int ret; + + ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&buf); + if (ret) { + goto out; + } + +out: + return ret; +} + +static int ssd_bm_get_sfstatus(struct ssd_device *dev, uint16_t *status) +{ + uint16_t val = 0; + uint8_t cmd = SSD_BM_SAFETYSTATUS; + int ret; + + ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&val); + if (ret) { + goto out; + } + + *status = val; +out: + return ret; +} + +static int ssd_bm_get_opstatus(struct ssd_device *dev, uint16_t *status) +{ + uint16_t val = 0; + uint8_t cmd = SSD_BM_OPERATIONSTATUS; + int ret; + + ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&val); + if (ret) { + goto out; + } + + *status = val; +out: + return ret; +} + +static int ssd_get_bmstruct(struct ssd_device *dev, struct ssd_bm *bm_status_out) +{ + struct sbs_cmd *bm_sbs = ssd_bm_sbs; + struct ssd_bm bm_status; + uint8_t buf[2] = {0, }; + uint16_t val = 0; + uint16_t cval; + int ret = 0; + + memset(&bm_status, 0, sizeof(struct ssd_bm)); + + while (bm_sbs->desc != NULL) { + switch (bm_sbs->size) { + case SBS_SIZE_BYTE: + ret = ssd_smbus_read_byte(dev, SSD_BM_SLAVE_ADDRESS, bm_sbs->cmd, buf); + if (ret) { + //printf("Error: smbus read byte %#x\n", bm_sbs->cmd); + goto out; + } + val = buf[0]; + break; + case SBS_SIZE_WORD: + ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, bm_sbs->cmd, (uint8_t *)&val); + if (ret) { + //printf("Error: smbus read word %#x\n", bm_sbs->cmd); + goto out; + } + //val = *(uint16_t *)buf; + break; + default: + ret = -1; + goto out; + break; + } + + switch (bm_sbs->unit) { + case SBS_UNIT_VALUE: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val & bm_sbs->mask; + break; + case SBS_UNIT_TEMPERATURE: + cval = (uint16_t)(val - 2731) / 10; + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = cval; + break; + case SBS_UNIT_VOLTAGE: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_CURRENT: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_ESR: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_PERCENT: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + case SBS_UNIT_CAPACITANCE: + *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val; + break; + default: + ret = -1; + goto out; + break; + } + + bm_sbs++; + } + + memcpy(bm_status_out, &bm_status, sizeof(struct ssd_bm)); + +out: + return ret; +} + +static int __ssd_bm_status(struct ssd_device *dev, int *status) +{ + struct ssd_bm bm_status = {0}; + int nr_cap = 0; + int i; + int ret = 0; + + ret = ssd_get_bmstruct(dev, &bm_status); + if (ret) { + goto out; + } + + /* capacitor voltage */ + ret = ssd_bm_nr_cap(dev, &nr_cap); + if (ret) { + goto out; + } + + for (i=0; i> 12) & 0x1)) { + *status = SSD_BMSTATUS_CHARGING; + }else{ + *status = SSD_BMSTATUS_OK; + } + +out: + return ret; +} + +static void ssd_set_flush_timeout(struct ssd_device *dev, int mode); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_bm_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_bm_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, bm_work); +#endif + + uint16_t opstatus; + int ret = 0; + + if (mode != SSD_DRV_MODE_STANDARD) { + return; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return; + } + + if (dev->hw_info_ext.plp_type != SSD_PLP_SCAP) { + return; + } + + ret = ssd_bm_get_opstatus(dev, &opstatus); + if (ret) { + hio_warn("%s: get bm operationstatus failed\n", dev->name); + return; + } + + /* need cap learning ? */ + if (!(opstatus & 0xF0)) { + ret = ssd_bm_enter_cap_learning(dev); + if (ret) { + hio_warn("%s: enter capacitance learning failed\n", dev->name); + return; + } + } +} + +static void ssd_bm_routine_start(void *data) +{ + struct ssd_device *dev; + + if (!data) { + return; + } + dev = data; + + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + queue_work(dev->workq, &dev->bm_work); + } else { + queue_work(dev->workq, &dev->capmon_work); + } + } +} + +/* CAP */ +static int ssd_do_cap_learn(struct ssd_device *dev, uint32_t *cap) +{ + uint32_t u1, u2, t; + uint16_t val = 0; + int wait = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + *cap = 0; + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + *cap = 0; + return 0; + } + + /* make sure the lm80 voltage value is updated */ + msleep(SSD_LM80_CONV_INTERVAL); + + /* check if full charged */ + wait = 0; + for (;;) { + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + if (SSD_PL_CAP_VOLT(u1) >= SSD_PL_CAP_VOLT_FULL) { + break; + } + + wait++; + if (wait > SSD_PL_CAP_CHARGE_MAX_WAIT) { + ret = -ETIMEDOUT; + goto out; + } + msleep(SSD_PL_CAP_CHARGE_WAIT); + } + + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U2, (uint8_t *)&val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + u2 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + + if (u1 == u2) { + ret = -EINVAL; + goto out; + } + + /* enter cap learn */ + ssd_reg32_write(dev->ctrlp + SSD_PL_CAP_LEARN_REG, 0x1); + + wait = 0; + for (;;) { + msleep(SSD_PL_CAP_LEARN_WAIT); + + t = ssd_reg32_read(dev->ctrlp + SSD_PL_CAP_LEARN_REG); + if (!((t >> 1) & 0x1)) { + break; + } + + wait++; + if (wait > SSD_PL_CAP_LEARN_MAX_WAIT) { + ret = -ETIMEDOUT; + goto out; + } + } + + if ((t >> 4) & 0x1) { + ret = -ETIMEDOUT; + goto out; + } + + t = (t >> 8); + if (0 == t) { + ret = -EINVAL; + goto out; + } + + *cap = SSD_PL_CAP_LEARN(u1, u2, t); + +out: + return ret; +} + +static int ssd_cap_learn(struct ssd_device *dev, uint32_t *cap) +{ + int ret = 0; + + if (!dev || !cap) { + return -EINVAL; + } + + mutex_lock(&dev->bm_mutex); + + ssd_stop_workq(dev); + + ret = ssd_do_cap_learn(dev, cap); + if (ret) { + ssd_gen_swlog(dev, SSD_LOG_CAP_LEARN_FAULT, 0); + goto out; + } + + ssd_gen_swlog(dev, SSD_LOG_CAP_STATUS, *cap); + +out: + ssd_start_workq(dev); + mutex_unlock(&dev->bm_mutex); + + return ret; +} + +static int ssd_check_pl_cap(struct ssd_device *dev) +{ + uint32_t u1; + uint16_t val = 0; + uint8_t low = 0; + int wait = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + /* cap ready ? */ + wait = 0; + for (;;) { + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + if (SSD_PL_CAP_VOLT(u1) >= SSD_PL_CAP_VOLT_READY) { + break; + } + + wait++; + if (wait > SSD_PL_CAP_CHARGE_MAX_WAIT) { + ret = -ETIMEDOUT; + ssd_gen_swlog(dev, SSD_LOG_CAP_VOLT_FAULT, SSD_PL_CAP_VOLT(u1)); + goto out; + } + msleep(SSD_PL_CAP_CHARGE_WAIT); + } + + low = ssd_lm80_limit[SSD_LM80_IN_CAP].low; + ret = ssd_smbus_write_byte(dev, SSD_SENSOR_LM80_SADDRESS, SSD_LM80_REG_IN_MIN(SSD_LM80_IN_CAP), &low); + if (ret) { + goto out; + } + + /* enable cap INx */ + ret = ssd_lm80_enable_in(dev, SSD_SENSOR_LM80_SADDRESS, SSD_LM80_IN_CAP); + if (ret) { + if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS); + } + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_pl_cap_fast(struct ssd_device *dev) +{ + uint32_t u1; + uint16_t val = 0; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return 0; + } + + /* cap ready ? */ + ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val); + if (ret) { + goto out; + } + u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val)); + if (SSD_PL_CAP_VOLT(u1) < SSD_PL_CAP_VOLT_READY) { + ret = 1; + } + +out: + return ret; +} + +static int ssd_init_pl_cap(struct ssd_device *dev) +{ + int ret = 0; + + /* set here: user write mode */ + dev->user_wmode = wmode; + + mutex_init(&dev->bm_mutex); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + uint32_t val; + val = ssd_reg32_read(dev->ctrlp + SSD_BM_FAULT_REG); + if ((val >> 1) & 0x1) { + (void)test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon); + } + } else { + ret = ssd_check_pl_cap(dev); + if (ret) { + (void)test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon); + } + } + + return 0; +} + +/* label */ +static void __end_str(char *str, int len) +{ + int i; + + for(i=0; irom_info.label_base; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + size = sizeof(struct ssd_label); + + /* read label */ + ret = ssd_spi_read(dev, &dev->label, off, size); + if (ret) { + memset(&dev->label, 0, size); + goto out; + } + + __end_str(dev->label.date, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.sn, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.part, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.desc, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.other, SSD_LABEL_FIELD_SZ); + __end_str(dev->label.maf, SSD_LABEL_FIELD_SZ); + } else { + size = sizeof(struct ssd_labelv3); + + /* read label */ + ret = ssd_spi_read(dev, &dev->labelv3, off, size); + if (ret) { + memset(&dev->labelv3, 0, size); + goto out; + } + + __end_str(dev->labelv3.boardtype, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.barcode, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.item, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.description, SSD_LABEL_DESC_SZ); + __end_str(dev->labelv3.manufactured, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.vendorname, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.issuenumber, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.cleicode, SSD_LABEL_FIELD_SZ); + __end_str(dev->labelv3.bom, SSD_LABEL_FIELD_SZ); + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +int ssd_get_label(struct block_device *bdev, struct ssd_label *label) +{ + struct ssd_device *dev; + + if (!bdev || !label || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + memset(label, 0, sizeof(struct ssd_label)); + memcpy(label->date, dev->labelv3.manufactured, SSD_LABEL_FIELD_SZ); + memcpy(label->sn, dev->labelv3.barcode, SSD_LABEL_FIELD_SZ); + memcpy(label->desc, dev->labelv3.boardtype, SSD_LABEL_FIELD_SZ); + memcpy(label->maf, dev->labelv3.vendorname, SSD_LABEL_FIELD_SZ); + } else { + memcpy(label, &dev->label, sizeof(struct ssd_label)); + } + + return 0; +} + +static int __ssd_get_version(struct ssd_device *dev, struct ssd_version_info *ver) +{ + uint16_t bm_ver = 0; + int ret = 0; + + if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + ret = ssd_bm_get_version(dev, &bm_ver); + if(ret){ + goto out; + } + } + + ver->bridge_ver = dev->hw_info.bridge_ver; + ver->ctrl_ver = dev->hw_info.ctrl_ver; + ver->bm_ver = bm_ver; + ver->pcb_ver = dev->hw_info.pcb_ver; + ver->upper_pcb_ver = dev->hw_info.upper_pcb_ver; + +out: + return ret; + +} + +int ssd_get_version(struct block_device *bdev, struct ssd_version_info *ver) +{ + struct ssd_device *dev; + int ret; + + if (!bdev || !ver || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_version(dev, ver); + mutex_unlock(&dev->fw_mutex); + + return ret; +} + +static int __ssd_get_temperature(struct ssd_device *dev, int *temp) +{ + uint64_t val; + uint32_t off; + int max = -300; + int cur; + int i; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + *temp = 0; + return 0; + } + + if (finject) { + if (dev->db_info.type == SSD_DEBUG_LOG && + (dev->db_info.data.log.event == SSD_LOG_OVER_TEMP || + dev->db_info.data.log.event == SSD_LOG_NORMAL_TEMP || + dev->db_info.data.log.event == SSD_LOG_WARN_TEMP)) { + *temp = (int)dev->db_info.data.log.extra; + return 0; + } + } + + for (i=0; ihw_info.nr_ctrl; i++) { + off = SSD_CTRL_TEMP_REG0 + i * sizeof(uint64_t); + + val = ssd_reg_read(dev->ctrlp + off); + if (val == 0xffffffffffffffffull) { + continue; + } + + cur = (int)CUR_TEMP(val); + if (cur >= max) { + max = cur; + } + } + + *temp = max; + + return 0; +} + +int ssd_get_temperature(struct block_device *bdev, int *temp) +{ + struct ssd_device *dev; + int ret; + + if (!bdev || !temp || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_temperature(dev, temp); + mutex_unlock(&dev->fw_mutex); + + return ret; +} + +int ssd_set_otprotect(struct block_device *bdev, int otprotect) + { + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + ssd_set_ot_protect(dev, !!otprotect); + + return 0; + } + +int ssd_bm_status(struct block_device *bdev, int *status) +{ + struct ssd_device *dev; + int ret = 0; + + if (!bdev || !status || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + mutex_lock(&dev->fw_mutex); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + *status = SSD_BMSTATUS_WARNING; + } else { + *status = SSD_BMSTATUS_OK; + } + } else if(dev->protocol_info.ver > SSD_PROTOCOL_V3) { + ret = __ssd_bm_status(dev, status); + } else { + *status = SSD_BMSTATUS_OK; + } + mutex_unlock(&dev->fw_mutex); + + return ret; +} + +int ssd_get_pciaddr(struct block_device *bdev, struct pci_addr *paddr) +{ + struct ssd_device *dev; + + if (!bdev || !paddr || !bdev->bd_disk) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + paddr->domain = pci_domain_nr(dev->pdev->bus); + paddr->bus = dev->pdev->bus->number; + paddr->slot = PCI_SLOT(dev->pdev->devfn); + paddr->func= PCI_FUNC(dev->pdev->devfn); + + return 0; +} + +/* acc */ +static int ssd_bb_acc(struct ssd_device *dev, struct ssd_acc_info *acc) +{ + uint32_t val; + int ctrl, chip; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return -EOPNOTSUPP; + } + + acc->threshold_l1 = ssd_reg32_read(dev->ctrlp + SSD_BB_THRESHOLD_L1_REG); + if (0xffffffffull == acc->threshold_l1) { + return -EIO; + } + acc->threshold_l2 = ssd_reg32_read(dev->ctrlp + SSD_BB_THRESHOLD_L2_REG); + if (0xffffffffull == acc->threshold_l2) { + return -EIO; + } + acc->val = 0; + + for (ctrl=0; ctrlhw_info.nr_ctrl; ctrl++) { + for (chip=0; chiphw_info.nr_chip; chip++) { + val = ssd_reg32_read(dev->ctrlp + SSD_BB_ACC_REG0 + (SSD_CTRL_REG_ZONE_SZ * ctrl) + (SSD_BB_ACC_REG_SZ * chip)); + if (0xffffffffull == acc->val) { + return -EIO; + } + if (val > acc->val) { + acc->val = val; + } + } + } + + return 0; +} + +static int ssd_ec_acc(struct ssd_device *dev, struct ssd_acc_info *acc) +{ + uint32_t val; + int ctrl, chip; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return -EOPNOTSUPP; + } + + acc->threshold_l1 = ssd_reg32_read(dev->ctrlp + SSD_EC_THRESHOLD_L1_REG); + if (0xffffffffull == acc->threshold_l1) { + return -EIO; + } + acc->threshold_l2 = ssd_reg32_read(dev->ctrlp + SSD_EC_THRESHOLD_L2_REG); + if (0xffffffffull == acc->threshold_l2) { + return -EIO; + } + acc->val = 0; + + for (ctrl=0; ctrlhw_info.nr_ctrl; ctrl++) { + for (chip=0; chiphw_info.nr_chip; chip++) { + val = ssd_reg32_read(dev->ctrlp + SSD_EC_ACC_REG0 + (SSD_CTRL_REG_ZONE_SZ * ctrl) + (SSD_EC_ACC_REG_SZ * chip)); + if (0xffffffffull == acc->val) { + return -EIO; + } + + if (val > acc->val) { + acc->val = val; + } + } + } + + return 0; +} + + +/* ram r&w */ +static int ssd_ram_read_4k(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + struct ssd_ram_op_msg *msg; + dma_addr_t buf_dma; + size_t len = length; + loff_t ofs_w = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size + || !length || length > dev->hw_info.ram_max_len + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + len /= dev->hw_info.ram_align; + do_div(ofs_w, dev->hw_info.ram_align); + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + msg = (struct ssd_ram_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_RAM_READ; + msg->ctrl_idx = ctrl_idx; + msg->start = (uint32_t)ofs_w; + msg->length = len; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +static int ssd_ram_write_4k(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + struct ssd_ram_op_msg *msg; + dma_addr_t buf_dma; + size_t len = length; + loff_t ofs_w = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size + || !length || length > dev->hw_info.ram_max_len + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + len /= dev->hw_info.ram_align; + do_div(ofs_w, dev->hw_info.ram_align); + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_TODEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map write DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + msg = (struct ssd_ram_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_RAM_WRITE; + msg->ctrl_idx = ctrl_idx; + msg->start = (uint32_t)ofs_w; + msg->length = len; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_TODEVICE); + +out_dma_mapping: + return ret; + +} + +static int ssd_ram_read(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + int left = length; + size_t len; + loff_t off = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size || !length + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + while (left > 0) { + len = dev->hw_info.ram_max_len; + if (left < (int)dev->hw_info.ram_max_len) { + len = left; + } + + ret = ssd_ram_read_4k(dev, buf, len, off, ctrl_idx); + if (ret) { + break; + } + + left -= len; + off += len; + buf += len; + } + + return ret; +} + +static int ssd_ram_write(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx) +{ + int left = length; + size_t len; + loff_t off = ofs; + int ret = 0; + + if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size || !length + || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) { + return -EINVAL; + } + + while (left > 0) { + len = dev->hw_info.ram_max_len; + if (left < (int)dev->hw_info.ram_max_len) { + len = left; + } + + ret = ssd_ram_write_4k(dev, buf, len, off, ctrl_idx); + if (ret) { + break; + } + + left -= len; + off += len; + buf += len; + } + + return ret; +} + + +/* flash op */ +static int ssd_check_flash(struct ssd_device *dev, int flash, int page, int ctrl_idx) +{ + int cur_ch = flash % dev->hw_info.max_ch; + int cur_chip = flash /dev->hw_info.max_ch; + + if (ctrl_idx >= dev->hw_info.nr_ctrl) { + return -EINVAL; + } + + if (cur_ch >= dev->hw_info.nr_ch || cur_chip >= dev->hw_info.nr_chip) { + return -EINVAL; + } + + if (page >= (int)(dev->hw_info.block_count * dev->hw_info.page_count)) { + return -EINVAL; + } + return 0; +} + +static int ssd_nand_read_id(struct ssd_device *dev, void *id, int flash, int chip, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int ret = 0; + + if (unlikely(!id)) + return -EINVAL; + + buf_dma = pci_map_single(dev->pdev, id, SSD_NAND_ID_BUFF_SZ, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_READ_ID; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->ctrl_idx = ctrl_idx; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, SSD_NAND_ID_BUFF_SZ, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +#if 0 +static int ssd_nand_read(struct ssd_device *dev, void *buf, + int flash, int chip, int page, int page_count, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int length; + int ret = 0; + + if (!buf) { + return -EINVAL; + } + + if ((page + page_count) > dev->hw_info.block_count*dev->hw_info.page_count) { + return -EINVAL; + } + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + length = page_count * dev->hw_info.page_size; + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = (flash << 1) | chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_READ; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->page_no = page; + msg->page_count = page_count; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} +#endif + +static int ssd_nand_read_w_oob(struct ssd_device *dev, void *buf, + int flash, int chip, int page, int count, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int length; + int ret = 0; + + if (!buf) { + return -EINVAL; + } + + if ((page + count) > (int)(dev->hw_info.block_count * dev->hw_info.page_count)) { + return -EINVAL; + } + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + length = count * (dev->hw_info.page_size + dev->hw_info.oob_size); + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map read DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_READ_WOOB; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->page_no = page; + msg->page_count = count; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, READ, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE); + +out_dma_mapping: + return ret; +} + +/* write 1 page */ +static int ssd_nand_write(struct ssd_device *dev, void *buf, + int flash, int chip, int page, int count, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + dma_addr_t buf_dma; + int length; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + return -EINVAL; + } + + if (!buf) { + return -EINVAL; + } + + if (count != 1) { + return -EINVAL; + } + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + length = count * (dev->hw_info.page_size + dev->hw_info.oob_size); + + /* write data to ram */ + /*ret = ssd_ram_write(dev, buf, length, dev->hw_info.nand_wbuff_base, ctrl_idx); + if (ret) { + return ret; + }*/ + + buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_TODEVICE); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + ret = dma_mapping_error(buf_dma); +#else + ret = dma_mapping_error(&(dev->pdev->dev), buf_dma); +#endif + if (ret) { + hio_warn("%s: unable to map write DMA buffer\n", dev->name); + goto out_dma_mapping; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_WRITE; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + + msg->page_no = page; + msg->page_count = count; + msg->buf = buf_dma; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_TODEVICE); + +out_dma_mapping: + return ret; +} + +static int ssd_nand_erase(struct ssd_device *dev, int flash, int chip, int page, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + int ret = 0; + + ret = ssd_check_flash(dev, flash, page, ctrl_idx); + if (ret) { + return ret; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + flash = ((uint32_t)flash << 1) | (uint32_t)chip; + chip = 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_NAND_ERASE; + msg->ctrl_idx = ctrl_idx; + msg->chip_no = flash; + msg->chip_ce = chip; + msg->page_no = page; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_update_bbt(struct ssd_device *dev, int flash, int ctrl_idx) +{ + struct ssd_nand_op_msg *msg; + struct ssd_flush_msg *fmsg; + int ret = 0; + + ret = ssd_check_flash(dev, flash, 0, ctrl_idx); + if (ret) { + return ret; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + fmsg = (struct ssd_flush_msg *)msg; + + fmsg->fun = SSD_FUNC_FLUSH; + fmsg->flag = 0x1; + fmsg->flash = flash; + fmsg->ctrl_idx = ctrl_idx; + } else { + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0x1; + msg->chip_no = flash; + msg->ctrl_idx = ctrl_idx; + } + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +/* flash controller init state */ +static int __ssd_check_init_state(struct ssd_device *dev) +{ + uint32_t *init_state = NULL; + int reg_base, reg_sz; + int max_wait = SSD_INIT_MAX_WAIT; + int init_wait = 0; + int i, j, k; + int ch_start = 0; + +/* + for (i=0; ihw_info.nr_ctrl; i++) { + ssd_reg32_write(dev->ctrlp + SSD_CTRL_TEST_REG0 + i * 8, test_data); + read_data = ssd_reg32_read(dev->ctrlp + SSD_CTRL_TEST_REG0 + i * 8); + if (read_data == ~test_data) { + //dev->hw_info.nr_ctrl++; + dev->hw_info.nr_ctrl_map |= 1<ctrlp + SSD_READY_REG); + j=0; + for (i=0; ihw_info.nr_ctrl; i++) { + if (((read_data>>i) & 0x1) == 0) { + j++; + } + } + + if (dev->hw_info.nr_ctrl != j) { + printk(KERN_WARNING "%s: nr_ctrl mismatch: %d %d\n", dev->name, dev->hw_info.nr_ctrl, j); + return -1; + } +*/ + +/* + init_state = ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0); + for (j=1; jhw_info.nr_ctrl;j++) { + if (init_state != ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0 + j*8)) { + printk(KERN_WARNING "SSD_FLASH_INFO_REG[%d], not match\n", j); + return -1; + } + } +*/ + +/* init_state = ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0); + for (j=1; jhw_info.nr_ctrl; j++) { + if (init_state != ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + j*16)) { + printk(KERN_WARNING "SSD_CHIP_INFO_REG Lo [%d], not match\n", j); + return -1; + } + } + + init_state = ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + 8); + for (j=1; jhw_info.nr_ctrl; j++) { + if (init_state != ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + 8 + j*16)) { + printk(KERN_WARNING "SSD_CHIP_INFO_REG Hi [%d], not match\n", j); + return -1; + } + } +*/ + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + max_wait = SSD_INIT_MAX_WAIT_V3_2; + } + + reg_base = dev->protocol_info.init_state_reg; + reg_sz = dev->protocol_info.init_state_reg_sz; + + init_state = (uint32_t *)kmalloc(reg_sz, GFP_KERNEL); + if (!init_state) { + return -ENOMEM; + } + + for (i=0; ihw_info.nr_ctrl; i++) { +check_init: + for (j=0, k=0; jctrlp + reg_base + j); + } + + if (dev->protocol_info.ver > SSD_PROTOCOL_V3) { + /* just check the last bit, no need to check all channel */ + ch_start = dev->hw_info.max_ch - 1; + } else { + ch_start = 0; + } + + for (j=0; jhw_info.nr_chip; j++) { + for (k=ch_start; khw_info.max_ch; k++) { + if (test_bit((j*dev->hw_info.max_ch + k), (void *)init_state)) { + continue; + } + + init_wait++; + if (init_wait <= max_wait) { + msleep(SSD_INIT_WAIT); + goto check_init; + } else { + if (k < dev->hw_info.nr_ch) { + hio_warn("%s: controller %d chip %d ch %d init failed\n", + dev->name, i, j, k); + } else { + hio_warn("%s: controller %d chip %d init failed\n", + dev->name, i, j); + } + + kfree(init_state); + return -1; + } + } + } + reg_base += reg_sz; + } + //printk(KERN_WARNING "%s: init wait %d\n", dev->name, init_wait); + + kfree(init_state); + return 0; +} + +static int ssd_check_init_state(struct ssd_device *dev) +{ + if (mode != SSD_DRV_MODE_STANDARD) { + return 0; + } + + return __ssd_check_init_state(dev); +} + +static void ssd_reset_resp_ptr(struct ssd_device *dev); + +/* reset flash controller etc */ +static int __ssd_reset(struct ssd_device *dev, int type) +{ + if (type < SSD_RST_NOINIT || type > SSD_RST_FULL) { + return -EINVAL; + } + + mutex_lock(&dev->fw_mutex); + + if (type == SSD_RST_NOINIT) { //no init + ssd_reg32_write(dev->ctrlp + SSD_RESET_REG, SSD_RESET_NOINIT); + } else if (type == SSD_RST_NORMAL) { //reset & init + ssd_reg32_write(dev->ctrlp + SSD_RESET_REG, SSD_RESET); + } else { // full reset + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + mutex_unlock(&dev->fw_mutex); + return -EINVAL; + } + + ssd_reg32_write(dev->ctrlp + SSD_FULL_RESET_REG, SSD_RESET_FULL); + + /* ?? */ + ssd_reset_resp_ptr(dev); + } + +#ifdef SSD_OT_PROTECT + dev->ot_delay = 0; +#endif + + msleep(1000); + + /* xx */ + ssd_set_flush_timeout(dev, dev->wmode); + + mutex_unlock(&dev->fw_mutex); + ssd_gen_swlog(dev, SSD_LOG_RESET, (uint32_t)type); + + return __ssd_check_init_state(dev); +} + +static int ssd_save_md(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (!dev->save_md) { + return 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0x2; + msg->ctrl_idx = 0; + msg->chip_no = 0; + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_barrier_save_md(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return 0; + } + + if (!dev->save_md) { + return 0; + } + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0x2; + msg->ctrl_idx = 0; + msg->chip_no = 0; + + ret = ssd_do_barrier_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_flush(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + struct ssd_flush_msg *fmsg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + fmsg = (struct ssd_flush_msg *)msg; + + fmsg->fun = SSD_FUNC_FLUSH; + fmsg->flag = 0; + fmsg->ctrl_idx = 0; + fmsg->flash = 0; + } else { + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0; + msg->ctrl_idx = 0; + msg->chip_no = 0; + } + + ret = ssd_do_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +static int ssd_barrier_flush(struct ssd_device *dev) +{ + struct ssd_nand_op_msg *msg; + struct ssd_flush_msg *fmsg; + int ret = 0; + + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + + msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev); + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + fmsg = (struct ssd_flush_msg *)msg; + + fmsg->fun = SSD_FUNC_FLUSH; + fmsg->flag = 0; + fmsg->ctrl_idx = 0; + fmsg->flash = 0; + } else { + msg->fun = SSD_FUNC_FLUSH; + msg->flag = 0; + msg->ctrl_idx = 0; + msg->chip_no = 0; + } + + ret = ssd_do_barrier_request(dev, WRITE, msg, NULL); + ssd_put_dmsg(msg); + + return ret; +} + +#define SSD_WMODE_BUFFER_TIMEOUT 0x00c82710 +#define SSD_WMODE_BUFFER_EX_TIMEOUT 0x000500c8 +#define SSD_WMODE_FUA_TIMEOUT 0x000503E8 +static void ssd_set_flush_timeout(struct ssd_device *dev, int m) +{ + uint32_t to; + uint32_t val = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + return; + } + + switch(m) { + case SSD_WMODE_BUFFER: + to = SSD_WMODE_BUFFER_TIMEOUT; + break; + case SSD_WMODE_BUFFER_EX: + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2_1) { + to = SSD_WMODE_BUFFER_EX_TIMEOUT; + } else { + to = SSD_WMODE_BUFFER_TIMEOUT; + } + break; + case SSD_WMODE_FUA: + to = SSD_WMODE_FUA_TIMEOUT; + break; + default: + return; + } + + val = (((uint32_t)((uint32_t)m & 0x3) << 28) | to); + + ssd_reg32_write(dev->ctrlp + SSD_FLUSH_TIMEOUT_REG, val); +} + +static int ssd_do_switch_wmode(struct ssd_device *dev, int m) +{ + int ret = 0; + + ret = ssd_barrier_start(dev); + if (ret) { + goto out; + } + + ret = ssd_barrier_flush(dev); + if (ret) { + goto out_barrier_end; + } + + /* set contoller flush timeout */ + ssd_set_flush_timeout(dev, m); + + dev->wmode = m; + mb(); + +out_barrier_end: + ssd_barrier_end(dev); +out: + return ret; +} + +static int ssd_switch_wmode(struct ssd_device *dev, int m) +{ + int default_wmode; + int next_wmode; + int ret = 0; + + if (!test_bit(SSD_ONLINE, &dev->state)) { + return -ENODEV; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + default_wmode = SSD_WMODE_BUFFER; + } else { + default_wmode = SSD_WMODE_BUFFER_EX; + } + + if (SSD_WMODE_AUTO == m) { + /* battery fault ? */ + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + next_wmode = SSD_WMODE_FUA; + } else { + next_wmode = default_wmode; + } + } else if (SSD_WMODE_DEFAULT == m) { + next_wmode = default_wmode; + } else { + next_wmode = m; + } + + if (next_wmode != dev->wmode) { + hio_warn("%s: switch write mode (%d -> %d)\n", dev->name, dev->wmode, next_wmode); + ret = ssd_do_switch_wmode(dev, next_wmode); + if (ret) { + hio_err("%s: can not switch write mode (%d -> %d)\n", dev->name, dev->wmode, next_wmode); + } + } + + return ret; +} + +static int ssd_init_wmode(struct ssd_device *dev) +{ + int default_wmode; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + default_wmode = SSD_WMODE_BUFFER; + } else { + default_wmode = SSD_WMODE_BUFFER_EX; + } + + /* dummy mode */ + if (SSD_WMODE_AUTO == dev->user_wmode) { + /* battery fault ? */ + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + dev->wmode = SSD_WMODE_FUA; + } else { + dev->wmode = default_wmode; + } + } else if (SSD_WMODE_DEFAULT == dev->user_wmode) { + dev->wmode = default_wmode; + } else { + dev->wmode = dev->user_wmode; + } + ssd_set_flush_timeout(dev, dev->wmode); + + return ret; +} + +static int __ssd_set_wmode(struct ssd_device *dev, int m) +{ + int ret = 0; + + /* not support old fw*/ + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) { + ret = -EOPNOTSUPP; + goto out; + } + + if (m < SSD_WMODE_BUFFER || m > SSD_WMODE_DEFAULT) { + ret = -EINVAL; + goto out; + } + + ssd_gen_swlog(dev, SSD_LOG_SET_WMODE, m); + + dev->user_wmode = m; + + ret = ssd_switch_wmode(dev, dev->user_wmode); + if (ret) { + goto out; + } + +out: + return ret; +} + +int ssd_set_wmode(struct block_device *bdev, int m) +{ + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + return __ssd_set_wmode(dev, m); +} + +static int ssd_do_reset(struct ssd_device *dev) +{ + int ret = 0; + + if (test_and_set_bit(SSD_RESETING, &dev->state)) { + return 0; + } + + ssd_stop_workq(dev); + + ret = ssd_barrier_start(dev); + if (ret) { + goto out; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + /* old reset */ + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } else { + /* full reset */ + //ret = __ssd_reset(dev, SSD_RST_FULL); + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } + if (ret) { + goto out_barrier_end; + } + +out_barrier_end: + ssd_barrier_end(dev); +out: + ssd_start_workq(dev); + test_and_clear_bit(SSD_RESETING, &dev->state); + return ret; +} + +static int ssd_full_reset(struct ssd_device *dev) +{ + int ret = 0; + + if (test_and_set_bit(SSD_RESETING, &dev->state)) { + return 0; + } + + ssd_stop_workq(dev); + + ret = ssd_barrier_start(dev); + if (ret) { + goto out; + } + + ret = ssd_barrier_flush(dev); + if (ret) { + goto out_barrier_end; + } + + ret = ssd_barrier_save_md(dev); + if (ret) { + goto out_barrier_end; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + /* old reset */ + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } else { + /* full reset */ + //ret = __ssd_reset(dev, SSD_RST_FULL); + ret = __ssd_reset(dev, SSD_RST_NORMAL); + } + if (ret) { + goto out_barrier_end; + } + +out_barrier_end: + ssd_barrier_end(dev); +out: + ssd_start_workq(dev); + test_and_clear_bit(SSD_RESETING, &dev->state); + return ret; +} + +int ssd_reset(struct block_device *bdev) +{ + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + + return ssd_full_reset(dev); +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static int ssd_issue_flush_fn(struct request_queue *q, struct gendisk *disk, + sector_t *error_sector) +{ + struct ssd_device *dev = q->queuedata; + + return ssd_flush(dev); +} +#endif + +void ssd_submit_pbio(struct request_queue *q, struct bio *bio) +{ + struct ssd_device *dev = q->queuedata; +#ifdef SSD_QUEUE_PBIO + int ret = -EBUSY; +#endif + + if (!test_bit(SSD_ONLINE, &dev->state)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -ENODEV); +#else + bio_endio(bio, bio->bi_size, -ENODEV); +#endif + goto out; + } + +#ifdef SSD_DEBUG_ERR + if (atomic_read(&dev->tocnt)) { + hio_warn("%s: IO rejected because of IO timeout!\n", dev->name); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EIO); +#else + bio_endio(bio, bio->bi_size, -EIO); +#endif + goto out; + } +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32)) + if (unlikely(bio_barrier(bio))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)) + if (unlikely(bio_rw_flagged(bio, BIO_RW_BARRIER))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) + if (unlikely(bio->bi_rw & REQ_HARDBARRIER)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#else + //xx + if (unlikely(bio->bi_rw & REQ_FUA)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#endif + + if (unlikely(dev->readonly && bio_data_dir(bio) == WRITE)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EROFS); +#else + bio_endio(bio, bio->bi_size, -EROFS); +#endif + goto out; + } + +#ifdef SSD_QUEUE_PBIO + if (0 == atomic_read(&dev->in_sendq)) { + ret = __ssd_submit_pbio(dev, bio, 0); + } + + if (ret) { + (void)test_and_set_bit(BIO_SSD_PBIO, &bio->bi_flags); + ssd_queue_bio(dev, bio); + } +#else + __ssd_submit_pbio(dev, bio, 1); +#endif + +out: + return; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) +static int ssd_make_request(struct request_queue *q, struct bio *bio) +#else +static void ssd_make_request(struct request_queue *q, struct bio *bio) +#endif +{ + struct ssd_device *dev = q->queuedata; + int ret = -EBUSY; + + if (!test_bit(SSD_ONLINE, &dev->state)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -ENODEV); +#else + bio_endio(bio, bio->bi_size, -ENODEV); +#endif + goto out; + } + +#ifdef SSD_DEBUG_ERR + if (atomic_read(&dev->tocnt)) { + hio_warn("%s: IO rejected because of IO timeout!\n", dev->name); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EIO); +#else + bio_endio(bio, bio->bi_size, -EIO); +#endif + goto out; + } +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32)) + if (unlikely(bio_barrier(bio))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)) + if (unlikely(bio_rw_flagged(bio, BIO_RW_BARRIER))) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) + if (unlikely(bio->bi_rw & REQ_HARDBARRIER)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } +#else + //xx + if (unlikely(bio->bi_rw & REQ_FUA)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + bio_endio(bio, -EOPNOTSUPP); +#else + bio_endio(bio, bio->bi_size, -EOPNOTSUPP); +#endif + goto out; + } + + /* writeback_cache_control.txt: REQ_FLUSH requests without data can be completed successfully without doing any work */ + if (unlikely((bio->bi_rw & REQ_FLUSH) && !bio_sectors(bio))) { + bio_endio(bio, 0); + goto out; + } + +#endif + + if (0 == atomic_read(&dev->in_sendq)) { + ret = ssd_submit_bio(dev, bio, 0); + } + + if (ret) { + ssd_queue_bio(dev, bio); + } + +out: +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) + return 0; +#else + return; +#endif +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)) +static int ssd_block_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct ssd_device *dev; + + if (!bdev) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } + + geo->heads = 4; + geo->sectors = 16; + geo->cylinders = (dev->hw_info.size & ~0x3f) >> 6; + return 0; +} +#endif + +static void ssd_cleanup_blkdev(struct ssd_device *dev); +static int ssd_init_blkdev(struct ssd_device *dev); +static int ssd_ioctl_common(struct ssd_device *dev, unsigned int cmd, unsigned long arg) +{ + void __user *argp = (void __user *)arg; + void __user *buf = NULL; + void *kbuf = NULL; + int ret = 0; + + switch (cmd) { + case SSD_CMD_GET_PROTOCOL_INFO: + if (copy_to_user(argp, &dev->protocol_info, sizeof(struct ssd_protocol_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_HW_INFO: + if (copy_to_user(argp, &dev->hw_info, sizeof(struct ssd_hw_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_ROM_INFO: + if (copy_to_user(argp, &dev->rom_info, sizeof(struct ssd_rom_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_SMART: { + struct ssd_smart smart; + int i; + + memcpy(&smart, &dev->smart, sizeof(struct ssd_smart)); + + mutex_lock(&dev->gd_mutex); + ssd_update_smart(dev, &smart); + mutex_unlock(&dev->gd_mutex); + + /* combine the volatile log info */ + if (dev->log_info.nr_log) { + for (i=0; ilog_info.stat[i]; + } + } + + if (copy_to_user(argp, &smart, sizeof(struct ssd_smart))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_GET_IDX: + if (copy_to_user(argp, &dev->idx, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_GET_AMOUNT: { + int nr_ssd = atomic_read(&ssd_nr); + if (copy_to_user(argp, &nr_ssd, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_TO_INFO: { + int tocnt = atomic_read(&dev->tocnt); + + if (copy_to_user(argp, &tocnt, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_DRV_VER: { + char ver[] = DRIVER_VERSION; + int len = sizeof(ver); + + if (len > (DRIVER_VERSION_LEN - 1)) { + len = (DRIVER_VERSION_LEN - 1); + } + if (copy_to_user(argp, ver, len)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_BBACC_INFO: { + struct ssd_acc_info acc; + + mutex_lock(&dev->fw_mutex); + ret = ssd_bb_acc(dev, &acc); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &acc, sizeof(struct ssd_acc_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_ECACC_INFO: { + struct ssd_acc_info acc; + + mutex_lock(&dev->fw_mutex); + ret = ssd_ec_acc(dev, &acc); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &acc, sizeof(struct ssd_acc_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_HW_INFO_EXT: + if (copy_to_user(argp, &dev->hw_info_ext, sizeof(struct ssd_hw_info_extend))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_REG_READ: { + struct ssd_reg_op_info reg_info; + + if (copy_from_user(®_info, argp, sizeof(struct ssd_reg_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (reg_info.offset > dev->mmio_len-sizeof(uint32_t)) { + ret = -EINVAL; + break; + } + + reg_info.value = ssd_reg32_read(dev->ctrlp + reg_info.offset); + if (copy_to_user(argp, ®_info, sizeof(struct ssd_reg_op_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_REG_WRITE: { + struct ssd_reg_op_info reg_info; + + if (copy_from_user(®_info, argp, sizeof(struct ssd_reg_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (reg_info.offset > dev->mmio_len-sizeof(uint32_t)) { + ret = -EINVAL; + break; + } + + ssd_reg32_write(dev->ctrlp + reg_info.offset, reg_info.value); + + break; + } + + case SSD_CMD_SPI_READ: { + struct ssd_spi_op_info spi_info; + uint32_t off, size; + + if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + off = spi_info.off; + size = spi_info.len; + buf = spi_info.buf; + + if (size > dev->rom_info.size || 0 == size || (off + size) > dev->rom_info.size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(size, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + ret = ssd_spi_page_read(dev, kbuf, off, size); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_SPI_WRITE: { + struct ssd_spi_op_info spi_info; + uint32_t off, size; + + if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + off = spi_info.off; + size = spi_info.len; + buf = spi_info.buf; + + if (size > dev->rom_info.size || 0 == size || (off + size) > dev->rom_info.size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(size, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user(kbuf, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = ssd_spi_page_write(dev, kbuf, off, size); + if (ret) { + kfree(kbuf); + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_SPI_ERASE: { + struct ssd_spi_op_info spi_info; + uint32_t off; + + if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + off = spi_info.off; + + if ((off + dev->rom_info.block_size) > dev->rom_info.size) { + ret = -EINVAL; + break; + } + + ret = ssd_spi_block_erase(dev, off); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_I2C_READ: { + struct ssd_i2c_op_info i2c_info; + uint8_t saddr; + uint8_t rsize; + + if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = i2c_info.saddr; + rsize = i2c_info.rsize; + buf = i2c_info.rbuf; + + if (rsize <= 0 || rsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(rsize, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + ret = ssd_i2c_read(dev, saddr, rsize, kbuf); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, rsize)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_I2C_WRITE: { + struct ssd_i2c_op_info i2c_info; + uint8_t saddr; + uint8_t wsize; + + if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = i2c_info.saddr; + wsize = i2c_info.wsize; + buf = i2c_info.wbuf; + + if (wsize <= 0 || wsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(wsize, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user(kbuf, buf, wsize)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = ssd_i2c_write(dev, saddr, wsize, kbuf); + if (ret) { + kfree(kbuf); + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_I2C_WRITE_READ: { + struct ssd_i2c_op_info i2c_info; + uint8_t saddr; + uint8_t wsize; + uint8_t rsize; + uint8_t size; + + if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = i2c_info.saddr; + wsize = i2c_info.wsize; + rsize = i2c_info.rsize; + buf = i2c_info.wbuf; + + if (wsize <= 0 || wsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + if (rsize <= 0 || rsize > SSD_I2C_MAX_DATA) { + ret = -EINVAL; + break; + } + + size = wsize + rsize; + + kbuf = kmalloc(size, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user((kbuf + rsize), buf, wsize)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + buf = i2c_info.rbuf; + + ret = ssd_i2c_write_read(dev, saddr, wsize, (kbuf + rsize), rsize, kbuf); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, rsize)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_SMBUS_SEND_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + buf = smbus_info.buf; + size = 1; + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_send_byte(dev, saddr, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_RECEIVE_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + buf = smbus_info.buf; + size = 1; + + ret = ssd_smbus_receive_byte(dev, saddr, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_SMBUS_WRITE_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 1; + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_write_byte(dev, saddr, command, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_READ_BYTE: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 1; + + ret = ssd_smbus_read_byte(dev, saddr, command, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_SMBUS_WRITE_WORD: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 2; + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_write_word(dev, saddr, command, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_READ_WORD: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = 2; + + ret = ssd_smbus_read_word(dev, saddr, command, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_SMBUS_WRITE_BLOCK: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = smbus_info.size; + + if (size > SSD_SMBUS_BLOCK_MAX) { + ret = -EINVAL; + break; + } + + if (copy_from_user(smb_data, buf, size)) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_smbus_write_block(dev, saddr, command, size, smb_data); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_SMBUS_READ_BLOCK: { + struct ssd_smbus_op_info smbus_info; + uint8_t smb_data[SSD_SMBUS_BLOCK_MAX]; + uint8_t saddr; + uint8_t command; + uint8_t size; + + if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + saddr = smbus_info.saddr; + command = smbus_info.cmd; + buf = smbus_info.buf; + size = smbus_info.size; + + if (size > SSD_SMBUS_BLOCK_MAX) { + ret = -EINVAL; + break; + } + + ret = ssd_smbus_read_block(dev, saddr, command, size, smb_data); + if (ret) { + break; + } + + if (copy_to_user(buf, smb_data, size)) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_BM_GET_VER: { + uint16_t ver; + + ret = ssd_bm_get_version(dev, &ver); + if (ret) { + break; + } + + if (copy_to_user(argp, &ver, sizeof(uint16_t))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_BM_GET_NR_CAP: { + int nr_cap; + + ret = ssd_bm_nr_cap(dev, &nr_cap); + if (ret) { + break; + } + + if (copy_to_user(argp, &nr_cap, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_BM_CAP_LEARNING: { + ret = ssd_bm_enter_cap_learning(dev); + + if (ret) { + break; + } + + break; + } + + case SSD_CMD_CAP_LEARN: { + uint32_t cap = 0; + + ret = ssd_cap_learn(dev, &cap); + if (ret) { + break; + } + + if (copy_to_user(argp, &cap, sizeof(uint32_t))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_GET_CAP_STATUS: { + int cap_status = 0; + + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + cap_status = 1; + } + + if (copy_to_user(argp, &cap_status, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_RAM_READ: { + struct ssd_ram_op_info ram_info; + uint64_t ofs; + uint32_t length; + size_t rlen, len = dev->hw_info.ram_max_len; + int ctrl_idx; + + if (copy_from_user(&ram_info, argp, sizeof(struct ssd_ram_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ofs = ram_info.start; + length = ram_info.length; + buf = ram_info.buf; + ctrl_idx = ram_info.ctrl_idx; + + if (ofs >= dev->hw_info.ram_size || length > dev->hw_info.ram_size || 0 == length || (ofs + length) > dev->hw_info.ram_size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + for (rlen=0; rlenhw_info.ram_max_len; + int ctrl_idx; + + if (copy_from_user(&ram_info, argp, sizeof(struct ssd_ram_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + ofs = ram_info.start; + length = ram_info.length; + buf = ram_info.buf; + ctrl_idx = ram_info.ctrl_idx; + + if (ofs >= dev->hw_info.ram_size || length > dev->hw_info.ram_size || 0 == length || (ofs + length) > dev->hw_info.ram_size) { + ret = -EINVAL; + break; + } + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + for (wlen=0; wlenname); + ret = -EFAULT; + break; + } + + chip_no = flash_info.flash; + chip_ce = flash_info.chip; + ctrl_idx = flash_info.ctrl_idx; + buf = flash_info.buf; + length = dev->hw_info.id_size; + + //kbuf = kmalloc(length, GFP_KERNEL); + kbuf = kmalloc(SSD_NAND_ID_BUFF_SZ, GFP_KERNEL); //xx + if (!kbuf) { + ret = -ENOMEM; + break; + } + memset(kbuf, 0, length); + + ret = ssd_nand_read_id(dev, kbuf, chip_no, chip_ce, ctrl_idx); + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + + break; + } + + case SSD_CMD_NAND_READ: { //with oob + struct ssd_flash_op_info flash_info; + uint32_t length; + int flash, chip, page, ctrl_idx; + int err = 0; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + buf = flash_info.buf; + ctrl_idx = flash_info.ctrl_idx; + + length = dev->hw_info.page_size + dev->hw_info.oob_size; + + kbuf = kmalloc(length, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + err = ret = ssd_nand_read_w_oob(dev, kbuf, flash, chip, page, 1, ctrl_idx); + if (ret && (-EIO != ret)) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = err; + + kfree(kbuf); + break; + } + + case SSD_CMD_NAND_WRITE: { + struct ssd_flash_op_info flash_info; + int flash, chip, page, ctrl_idx; + uint32_t length; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + buf = flash_info.buf; + ctrl_idx = flash_info.ctrl_idx; + + length = dev->hw_info.page_size + dev->hw_info.oob_size; + + kbuf = kmalloc(length, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + if (copy_from_user(kbuf, buf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + ret = ssd_nand_write(dev, kbuf, flash, chip, page, 1, ctrl_idx); + if (ret) { + kfree(kbuf); + break; + } + + kfree(kbuf); + break; + } + + case SSD_CMD_NAND_ERASE: { + struct ssd_flash_op_info flash_info; + int flash, chip, page, ctrl_idx; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + ctrl_idx = flash_info.ctrl_idx; + + if ((page % dev->hw_info.page_count) != 0) { + ret = -EINVAL; + break; + } + + //hio_warn("erase fs = %llx\n", ofs); + ret = ssd_nand_erase(dev, flash, chip, page, ctrl_idx); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_NAND_READ_EXT: { //ingore EIO + struct ssd_flash_op_info flash_info; + uint32_t length; + int flash, chip, page, ctrl_idx; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + flash = flash_info.flash; + chip = flash_info.chip; + page = flash_info.page; + buf = flash_info.buf; + ctrl_idx = flash_info.ctrl_idx; + + length = dev->hw_info.page_size + dev->hw_info.oob_size; + + kbuf = kmalloc(length, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + break; + } + + ret = ssd_nand_read_w_oob(dev, kbuf, flash, chip, page, 1, ctrl_idx); + if (-EIO == ret) { //ingore EIO + ret = 0; + } + if (ret) { + kfree(kbuf); + break; + } + + if (copy_to_user(buf, kbuf, length)) { + kfree(kbuf); + ret = -EFAULT; + break; + } + + kfree(kbuf); + break; + } + + case SSD_CMD_UPDATE_BBT: { + struct ssd_flash_op_info flash_info; + int ctrl_idx, flash; + + if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ctrl_idx = flash_info.ctrl_idx; + flash = flash_info.flash; + ret = ssd_update_bbt(dev, flash, ctrl_idx); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_CLEAR_ALARM: + ssd_clear_alarm(dev); + break; + + case SSD_CMD_SET_ALARM: + ssd_set_alarm(dev); + break; + + case SSD_CMD_RESET: + ret = ssd_do_reset(dev); + break; + + case SSD_CMD_RELOAD_FW: + dev->reload_fw = 1; + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FLAG); + } else if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_1_1) { + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW); + + } + break; + + case SSD_CMD_UNLOAD_DEV: { + if (atomic_read(&dev->refcnt)) { + ret = -EBUSY; + break; + } + + /* save smart */ + ssd_save_smart(dev); + + ret = ssd_flush(dev); + if (ret) { + break; + } + + /* cleanup the block device */ + if (test_and_clear_bit(SSD_INIT_BD, &dev->state)) { + mutex_lock(&dev->gd_mutex); + ssd_cleanup_blkdev(dev); + mutex_unlock(&dev->gd_mutex); + } + + break; + } + + case SSD_CMD_LOAD_DEV: { + + if (test_bit(SSD_INIT_BD, &dev->state)) { + ret = -EINVAL; + break; + } + + ret = ssd_init_smart(dev); + if (ret) { + hio_warn("%s: init info: failed\n", dev->name); + break; + } + + ret = ssd_init_blkdev(dev); + if (ret) { + hio_warn("%s: register block device: failed\n", dev->name); + break; + } + (void)test_and_set_bit(SSD_INIT_BD, &dev->state); + + break; + } + + case SSD_CMD_UPDATE_VP: { + uint32_t val; + uint32_t new_vp, new_vp1 = 0; + + if (test_bit(SSD_INIT_BD, &dev->state)) { + ret = -EINVAL; + break; + } + + if (copy_from_user(&new_vp, argp, sizeof(uint32_t))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (new_vp > dev->hw_info.max_valid_pages || new_vp <= 0) { + ret = -EINVAL; + break; + } + + while (new_vp <= dev->hw_info.max_valid_pages) { + ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, new_vp); + msleep(10); + val = ssd_reg32_read(dev->ctrlp + SSD_VALID_PAGES_REG); + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + new_vp1 = val & 0x3FF; + } else { + new_vp1 = val & 0x7FFF; + } + + if (new_vp1 == new_vp) { + break; + } + + new_vp++; + /*if (new_vp == dev->hw_info.valid_pages) { + new_vp++; + }*/ + } + + if (new_vp1 != new_vp || new_vp > dev->hw_info.max_valid_pages) { + /* restore */ + ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, dev->hw_info.valid_pages); + ret = -EINVAL; + break; + } + + if (copy_to_user(argp, &new_vp, sizeof(uint32_t))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, dev->hw_info.valid_pages); + ret = -EFAULT; + break; + } + + /* new */ + dev->hw_info.valid_pages = new_vp; + dev->hw_info.size = (uint64_t)dev->hw_info.valid_pages * dev->hw_info.page_size; + dev->hw_info.size *= (dev->hw_info.block_count - dev->hw_info.reserved_blks); + dev->hw_info.size *= ((uint64_t)dev->hw_info.nr_data_ch * (uint64_t)dev->hw_info.nr_chip * (uint64_t)dev->hw_info.nr_ctrl); + + break; + } + + case SSD_CMD_FULL_RESET: { + ret = ssd_full_reset(dev); + break; + } + + case SSD_CMD_GET_NR_LOG: { + if (copy_to_user(argp, &dev->internal_log.nr_log, sizeof(dev->internal_log.nr_log))) { + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_LOG: { + uint32_t length = dev->rom_info.log_sz; + + buf = argp; + + if (copy_to_user(buf, dev->internal_log.log, length)) { + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_LOG_LEVEL: { + int level = 0; + if (copy_from_user(&level, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (level >= SSD_LOG_NR_LEVEL || level < SSD_LOG_LEVEL_INFO) { + level = SSD_LOG_LEVEL_ERR; + } + + //just for showing log, no need to protect + log_level = level; + break; + } + + case SSD_CMD_OT_PROTECT: { + int protect = 0; + + if (copy_from_user(&protect, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ssd_set_ot_protect(dev, !!protect); + break; + } + + case SSD_CMD_GET_OT_STATUS: { + int status = ssd_get_ot_status(dev, &status); + + if (copy_to_user(argp, &status, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_CLEAR_LOG: { + ret = ssd_clear_log(dev); + break; + } + + case SSD_CMD_CLEAR_SMART: { + ret = ssd_clear_smart(dev); + break; + } + + case SSD_CMD_SW_LOG: { + struct ssd_sw_log_info sw_log; + + if (copy_from_user(&sw_log, argp, sizeof(struct ssd_sw_log_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = ssd_gen_swlog(dev, sw_log.event, sw_log.data); + break; + } + + case SSD_CMD_GET_LABEL: { + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + ret = -EINVAL; + break; + } + + if (copy_to_user(argp, &dev->label, sizeof(struct ssd_label))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_VERSION: { + struct ssd_version_info ver; + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_version(dev, &ver); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &ver, sizeof(struct ssd_version_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_TEMPERATURE: { + int temp; + + mutex_lock(&dev->fw_mutex); + ret = __ssd_get_temperature(dev, &temp); + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &temp, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_BMSTATUS: { + int status; + + mutex_lock(&dev->fw_mutex); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + status = SSD_BMSTATUS_WARNING; + } else { + status = SSD_BMSTATUS_OK; + } + } else if(dev->protocol_info.ver > SSD_PROTOCOL_V3) { + ret = __ssd_bm_status(dev, &status); + } else { + status = SSD_BMSTATUS_OK; + } + mutex_unlock(&dev->fw_mutex); + if (ret) { + break; + } + + if (copy_to_user(argp, &status, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_GET_LABEL2: { + void *label; + int length; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + label = &dev->label; + length = sizeof(struct ssd_label); + } else { + label = &dev->labelv3; + length = sizeof(struct ssd_labelv3); + } + + if (copy_to_user(argp, label, length)) { + ret = -EFAULT; + break; + } + break; + } + + case SSD_CMD_FLUSH: + ret = ssd_flush(dev); + if (ret) { + hio_warn("%s: ssd_flush: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + case SSD_CMD_SAVE_MD: { + int save_md = 0; + + if (copy_from_user(&save_md, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + dev->save_md = !!save_md; + break; + } + + case SSD_CMD_SET_WMODE: { + int new_wmode = 0; + + if (copy_from_user(&new_wmode, argp, sizeof(int))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + ret = __ssd_set_wmode(dev, new_wmode); + if (ret) { + break; + } + + break; + } + + case SSD_CMD_GET_WMODE: { + if (copy_to_user(argp, &dev->wmode, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_GET_USER_WMODE: { + if (copy_to_user(argp, &dev->user_wmode, sizeof(int))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + break; + } + + case SSD_CMD_DEBUG: { + struct ssd_debug_info db_info; + + if (!finject) { + ret = -EOPNOTSUPP; + break; + } + + if (copy_from_user(&db_info, argp, sizeof(struct ssd_debug_info))) { + hio_warn("%s: copy_from_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + + if (db_info.type < SSD_DEBUG_NONE || db_info.type >= SSD_DEBUG_NR) { + ret = -EINVAL; + break; + } + + /* IO */ + if (db_info.type >= SSD_DEBUG_READ_ERR && db_info.type <= SSD_DEBUG_RW_ERR && + (db_info.data.loc.off + db_info.data.loc.len) > (dev->hw_info.size >> 9)) { + ret = -EINVAL; + break; + } + + memcpy(&dev->db_info, &db_info, sizeof(struct ssd_debug_info)); + +#ifdef SSD_OT_PROTECT + /* temperature */ + if (db_info.type == SSD_DEBUG_NONE) { + ssd_check_temperature(dev, SSD_OT_TEMP); + } else if (db_info.type == SSD_DEBUG_LOG) { + if (db_info.data.log.event == SSD_LOG_OVER_TEMP) { + dev->ot_delay = SSD_OT_DELAY; + } else if (db_info.data.log.event == SSD_LOG_NORMAL_TEMP) { + dev->ot_delay = 0; + } + } +#endif + + /* offline */ + if (db_info.type == SSD_DEBUG_OFFLINE) { + test_and_clear_bit(SSD_ONLINE, &dev->state); + } else if (db_info.type == SSD_DEBUG_NONE) { + (void)test_and_set_bit(SSD_ONLINE, &dev->state); + } + + /* log */ + if (db_info.type == SSD_DEBUG_LOG && dev->event_call && dev->gd) { + dev->event_call(dev->gd, db_info.data.log.event, 0); + } + + break; + } + + case SSD_CMD_DRV_PARAM_INFO: { + struct ssd_drv_param_info drv_param; + + memset(&drv_param, 0, sizeof(struct ssd_drv_param_info)); + + drv_param.mode = mode; + drv_param.status_mask = status_mask; + drv_param.int_mode = int_mode; + drv_param.threaded_irq = threaded_irq; + drv_param.log_level = log_level; + drv_param.wmode = wmode; + drv_param.ot_protect = ot_protect; + drv_param.finject = finject; + + if (copy_to_user(argp, &drv_param, sizeof(struct ssd_drv_param_info))) { + hio_warn("%s: copy_to_user: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + } + + default: + ret = -EINVAL; + break; + } + + return ret; +} + + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) +static int ssd_block_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct ssd_device *dev; + void __user *argp = (void __user *)arg; + int ret = 0; + + if (!inode) { + return -EINVAL; + } + dev = inode->i_bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#else +static int ssd_block_ioctl(struct block_device *bdev, fmode_t mode, + unsigned int cmd, unsigned long arg) +{ + struct ssd_device *dev; + void __user *argp = (void __user *)arg; + int ret = 0; + + if (!bdev) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#endif + + switch (cmd) { + case HDIO_GETGEO: { + struct hd_geometry geo; + geo.cylinders = (dev->hw_info.size & ~0x3f) >> 6; + geo.heads = 4; + geo.sectors = 16; +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) + geo.start = get_start_sect(inode->i_bdev); +#else + geo.start = get_start_sect(bdev); +#endif + if (copy_to_user(argp, &geo, sizeof(geo))) { + ret = -EFAULT; + break; + } + + break; + } + + case BLKFLSBUF: + ret = ssd_flush(dev); + if (ret) { + hio_warn("%s: ssd_flush: failed\n", dev->name); + ret = -EFAULT; + break; + } + break; + + default: + if (!dev->slave) { + ret = ssd_ioctl_common(dev, cmd, arg); + } else { + ret = -EFAULT; + } + break; + } + + return ret; +} + + +static void ssd_free_dev(struct kref *kref) +{ + struct ssd_device *dev; + + if (!kref) { + return; + } + + dev = container_of(kref, struct ssd_device, kref); + + put_disk(dev->gd); + + ssd_put_index(dev->slave, dev->idx); + + kfree(dev); +} + +static void ssd_put(struct ssd_device *dev) +{ + kref_put(&dev->kref, ssd_free_dev); +} + +static int ssd_get(struct ssd_device *dev) +{ + kref_get(&dev->kref); + return 0; +} + +/* block device */ +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) +static int ssd_block_open(struct inode *inode, struct file *filp) +{ + struct ssd_device *dev; + + if (!inode) { + return -EINVAL; + } + + dev = inode->i_bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#else +static int ssd_block_open(struct block_device *bdev, fmode_t mode) +{ + struct ssd_device *dev; + + if (!bdev) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#endif + + /*if (!try_module_get(dev->owner)) + return -ENODEV; + */ + + ssd_get(dev); + + atomic_inc(&dev->refcnt); + + return 0; +} + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) +static int ssd_block_release(struct inode *inode, struct file *filp) +{ + struct ssd_device *dev; + + if (!inode) { + return -EINVAL; + } + + dev = inode->i_bdev->bd_disk->private_data; + if (!dev) { + return -EINVAL; + } +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0)) +static int ssd_block_release(struct gendisk *disk, fmode_t mode) +{ + struct ssd_device *dev; + + if (!disk) { + return -EINVAL; + } + + dev = disk->private_data; + if (!dev) { + return -EINVAL; + } +#else +static void ssd_block_release(struct gendisk *disk, fmode_t mode) +{ + struct ssd_device *dev; + + if (!disk) { + return; + } + + dev = disk->private_data; + if (!dev) { + return; + } +#endif + + atomic_dec(&dev->refcnt); + + ssd_put(dev); + + //module_put(dev->owner); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0)) + return 0; +#endif +} + +static struct block_device_operations ssd_fops = { + .owner = THIS_MODULE, + .open = ssd_block_open, + .release = ssd_block_release, + .ioctl = ssd_block_ioctl, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)) + .getgeo = ssd_block_getgeo, +#endif +}; + +static void ssd_init_trim(ssd_device_t *dev) +{ +#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))) + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + return; + } + queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, dev->rq); + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33)) || (defined RHEL_MAJOR && RHEL_MAJOR >= 6)) + dev->rq->limits.discard_zeroes_data = 1; + dev->rq->limits.discard_alignment = 4096; + dev->rq->limits.discard_granularity = 4096; +#endif + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2_4) { + dev->rq->limits.max_discard_sectors = dev->hw_info.sg_max_sec; + } else { + dev->rq->limits.max_discard_sectors = (dev->hw_info.sg_max_sec) * (dev->hw_info.cmd_max_sg); + } +#endif +} + +static void ssd_cleanup_queue(struct ssd_device *dev) +{ + ssd_wait_io(dev); + + blk_cleanup_queue(dev->rq); + dev->rq = NULL; +} + +static int ssd_init_queue(struct ssd_device *dev) +{ + dev->rq = blk_alloc_queue(GFP_KERNEL); + if (dev->rq == NULL) { + hio_warn("%s: alloc queue: failed\n ", dev->name); + goto out_init_queue; + } + + /* must be first */ + blk_queue_make_request(dev->rq, ssd_make_request); + +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) && !(defined RHEL_MAJOR && RHEL_MAJOR == 6)) + blk_queue_max_hw_segments(dev->rq, dev->hw_info.cmd_max_sg); + blk_queue_max_phys_segments(dev->rq, dev->hw_info.cmd_max_sg); + blk_queue_max_sectors(dev->rq, dev->hw_info.sg_max_sec); +#else + blk_queue_max_segments(dev->rq, dev->hw_info.cmd_max_sg); + blk_queue_max_hw_sectors(dev->rq, dev->hw_info.sg_max_sec); +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)) + blk_queue_hardsect_size(dev->rq, 512); +#else + blk_queue_logical_block_size(dev->rq, 512); +#endif + /* not work for make_request based drivers(bio) */ + blk_queue_max_segment_size(dev->rq, dev->hw_info.sg_max_sec << 9); + + blk_queue_bounce_limit(dev->rq, BLK_BOUNCE_HIGH); + + dev->rq->queuedata = dev; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + blk_queue_issue_flush_fn(dev->rq, ssd_issue_flush_fn); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) + queue_flag_set_unlocked(QUEUE_FLAG_NONROT, dev->rq); +#endif + + ssd_init_trim(dev); + + return 0; + +out_init_queue: + return -ENOMEM; +} + +static void ssd_cleanup_blkdev(struct ssd_device *dev) +{ + del_gendisk(dev->gd); +} + +static int ssd_init_blkdev(struct ssd_device *dev) +{ + if (dev->gd) { + put_disk(dev->gd); + } + + dev->gd = alloc_disk(ssd_minors); + if (!dev->gd) { + hio_warn("%s: alloc_disk fail\n", dev->name); + goto out_alloc_gd; + } + dev->gd->major = dev->major; + dev->gd->first_minor = dev->idx * ssd_minors; + dev->gd->fops = &ssd_fops; + dev->gd->queue = dev->rq; + dev->gd->private_data = dev; + dev->gd->driverfs_dev = &dev->pdev->dev; + snprintf (dev->gd->disk_name, sizeof(dev->gd->disk_name), "%s", dev->name); + + set_capacity(dev->gd, dev->hw_info.size >> 9); + + add_disk(dev->gd); + + return 0; + +out_alloc_gd: + return -ENOMEM; +} + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10)) +static int ssd_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +#else +static long ssd_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +#endif +{ + struct ssd_device *dev; + + if (!file) { + return -EINVAL; + } + + dev = file->private_data; + if (!dev) { + return -EINVAL; + } + + return (long)ssd_ioctl_common(dev, cmd, arg); +} + +static int ssd_open(struct inode *inode, struct file *file) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + int idx; + int ret = -ENODEV; + + if (!inode || !file) { + return -EINVAL; + } + + idx = iminor(inode); + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + if (dev->idx == idx) { + ret = 0; + break; + } + } + + if (ret) { + return ret; + } + + file->private_data = dev; + + ssd_get(dev); + + return 0; +} + +static int ssd_release(struct inode *inode, struct file *file) +{ + struct ssd_device *dev; + + if (!file) { + return -EINVAL; + } + + dev = file->private_data; + if (!dev) { + return -EINVAL; + } + + ssd_put(dev); + + file->private_data = NULL; + + return 0; +} + +static struct file_operations ssd_cfops = { + .owner = THIS_MODULE, + .open = ssd_open, + .release = ssd_release, +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10)) + .ioctl = ssd_ioctl, +#else + .unlocked_ioctl = ssd_ioctl, +#endif +}; + +static void ssd_cleanup_chardev(struct ssd_device *dev) +{ + if (dev->slave) { + return; + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + class_simple_device_remove(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); + devfs_remove("c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,14)) + class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); + devfs_remove("c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)) + class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); + devfs_remove("c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)) + class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); +#else + device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx)); +#endif +} + +static int ssd_init_chardev(struct ssd_device *dev) +{ + int ret = 0; + + if (dev->slave) { + return 0; + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name); + if (ret) { + goto out; + } + class_simple_device_add(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +out: +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,14)) + ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name); + if (ret) { + goto out; + } + class_device_create(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +out: +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)) + ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name); + if (ret) { + goto out; + } + class_device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +out: +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)) + class_device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)) + device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), "c%s", dev->name); +#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)) + device_create_drvdata(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +#else + device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name); +#endif + + return ret; +} + +static int ssd_check_hw(struct ssd_device *dev) +{ + uint32_t test_data = 0x55AA5AA5; + uint32_t read_data; + + ssd_reg32_write(dev->ctrlp + SSD_BRIDGE_TEST_REG, test_data); + read_data = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_TEST_REG); + if (read_data != ~(test_data)) { + //hio_warn("%s: check bridge error: %#x\n", dev->name, read_data); + return -1; + } + + return 0; +} + +static int ssd_check_fw(struct ssd_device *dev) +{ + uint32_t val = 0; + int i; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + for (i=0; ictrlp + SSD_HW_STATUS_REG); + if ((val & 0x1) && ((val >> 8) & 0x1)) { + break; + } + + msleep(SSD_INIT_WAIT); + } + + if (!(val & 0x1)) { + /* controller fw status */ + hio_warn("%s: controller firmware load failed: %#x\n", dev->name, val); + return -1; + } else if (!((val >> 8) & 0x1)) { + /* controller state */ + hio_warn("%s: controller state error: %#x\n", dev->name, val); + return -1; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_RELOAD_FW_REG); + if (val) { + dev->reload_fw = 1; + } + + return 0; +} + +static int ssd_init_fw_info(struct ssd_device *dev) +{ + uint32_t val; + int ret = 0; + + val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_VER_REG); + dev->hw_info.bridge_ver = val & 0xFFF; + if (dev->hw_info.bridge_ver < SSD_FW_MIN) { + hio_warn("%s: bridge firmware version %03X is not supported\n", dev->name, dev->hw_info.bridge_ver); + return -EINVAL; + } + hio_info("%s: bridge firmware version: %03X\n", dev->name, dev->hw_info.bridge_ver); + + ret = ssd_check_fw(dev); + if (ret) { + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_clock(struct ssd_device *dev) +{ + uint32_t val; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_HW_STATUS_REG); + + /* clock status */ + if (!((val >> 4 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_166M_LOST), &dev->hwmon)) { + hio_warn("%s: 166MHz clock losed: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + if (!((val >> 5 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_166M_SKEW), &dev->hwmon)) { + hio_warn("%s: 166MHz clock is skew: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + if (!((val >> 6 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_156M_LOST), &dev->hwmon)) { + hio_warn("%s: 156.25MHz clock lost: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + if (!((val >> 7 ) & 0x1)) { + if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_156M_SKEW), &dev->hwmon)) { + hio_warn("%s: 156.25MHz clock is skew: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val); + } + ret = -1; + } + } + + return ret; +} + +static int ssd_check_volt(struct ssd_device *dev) +{ + int i = 0; + uint64_t val; + uint32_t adc_val; + int ret =0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + for (i=0; ihw_info.nr_ctrl; i++) { + /* 1.0v */ + if (!test_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon)) { + val = ssd_reg_read(dev->ctrlp + SSD_FPGA_1V0_REG0 + i * SSD_CTRL_REG_ZONE_SZ); + adc_val = SSD_FPGA_VOLT_MAX(val); + if (adc_val < SSD_FPGA_1V0_ADC_MIN || adc_val > SSD_FPGA_1V0_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon); + hio_warn("%s: controller %d 1.0V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V0, i, adc_val)); + ret = -1; + } + + adc_val = SSD_FPGA_VOLT_MIN(val); + if (adc_val < SSD_FPGA_1V0_ADC_MIN || adc_val > SSD_FPGA_1V0_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon); + hio_warn("%s: controller %d 1.0V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V0, i, adc_val)); + ret = -2; + } + } + + /* 1.8v */ + if (!test_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon)) { + val = ssd_reg_read(dev->ctrlp + SSD_FPGA_1V8_REG0 + i * SSD_CTRL_REG_ZONE_SZ); + adc_val = SSD_FPGA_VOLT_MAX(val); + if (adc_val < SSD_FPGA_1V8_ADC_MIN || adc_val > SSD_FPGA_1V8_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon); + hio_warn("%s: controller %d 1.8V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V8, i, adc_val)); + ret = -3; + } + + adc_val = SSD_FPGA_VOLT_MIN(val); + if (adc_val < SSD_FPGA_1V8_ADC_MIN || adc_val > SSD_FPGA_1V8_ADC_MAX) { + (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon); + hio_warn("%s: controller %d 1.8V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val)); + ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V8, i, adc_val)); + ret = -4; + } + } + } + + return ret; +} + +static int ssd_check_reset_sync(struct ssd_device *dev) +{ + uint32_t val; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_HW_STATUS_REG); + if (!((val >> 8) & 0x1)) { + /* controller state */ + hio_warn("%s: controller state error: %#x\n", dev->name, val); + return -1; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return 0; + } + + if (((val >> 9 ) & 0x1)) { + hio_warn("%s: controller reset asynchronously: %#x\n", dev->name, val); + ssd_gen_swlog(dev, SSD_LOG_CTRL_RST_SYNC, val); + return -1; + } + + return 0; +} + +static int ssd_check_hw_bh(struct ssd_device *dev) +{ + int ret; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + /* clock status */ + ret = ssd_check_clock(dev); + if (ret) { + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_controller(struct ssd_device *dev) +{ + int ret; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) { + return 0; + } + + /* sync reset */ + ret = ssd_check_reset_sync(dev); + if (ret) { + goto out; + } + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static int ssd_check_controller_bh(struct ssd_device *dev) +{ + uint32_t test_data = 0x55AA5AA5; + uint32_t val; + int reg_base, reg_sz; + int init_wait = 0; + int i; + int ret = 0; + + if (mode != SSD_DRV_MODE_STANDARD) { + return 0; + } + + /* controller */ + val = ssd_reg32_read(dev->ctrlp + SSD_READY_REG); + if (val & 0x1) { + hio_warn("%s: controller 0 not ready\n", dev->name); + return -1; + } + + for (i=0; ihw_info.nr_ctrl; i++) { + reg_base = SSD_CTRL_TEST_REG0 + i * SSD_CTRL_TEST_REG_SZ; + ssd_reg32_write(dev->ctrlp + reg_base, test_data); + val = ssd_reg32_read(dev->ctrlp + reg_base); + if (val != ~(test_data)) { + hio_warn("%s: check controller %d error: %#x\n", dev->name, i, val); + return -1; + } + } + + /* clock */ + ret = ssd_check_volt(dev); + if (ret) { + return ret; + } + + /* ddr */ + if (dev->protocol_info.ver > SSD_PROTOCOL_V3) { + reg_base = SSD_PV3_RAM_STATUS_REG0; + reg_sz = SSD_PV3_RAM_STATUS_REG_SZ; + + for (i=0; ihw_info.nr_ctrl; i++) { +check_ram_status: + val = ssd_reg32_read(dev->ctrlp + reg_base); + + if (!((val >> 1) & 0x1)) { + init_wait++; + if (init_wait <= SSD_RAM_INIT_MAX_WAIT) { + msleep(SSD_INIT_WAIT); + goto check_ram_status; + } else { + hio_warn("%s: controller %d ram init failed: %#x\n", dev->name, i, val); + ssd_gen_swlog(dev, SSD_LOG_DDR_INIT_ERR, i); + return -1; + } + } + + reg_base += reg_sz; + } + } + + /* ch info */ + for (i=0; ictrlp + SSD_CH_INFO_REG); + if (!((val >> 31) & 0x1)) { + break; + } + + msleep(SSD_INIT_WAIT); + } + if ((val >> 31) & 0x1) { + hio_warn("%s: channel info init failed: %#x\n", dev->name, val); + return -1; + } + + return 0; +} + +static int ssd_init_protocol_info(struct ssd_device *dev) +{ + uint32_t val; + + val = ssd_reg32_read(dev->ctrlp + SSD_PROTOCOL_VER_REG); + if (val == (uint32_t)-1) { + hio_warn("%s: protocol version error: %#x\n", dev->name, val); + return -EINVAL; + } + dev->protocol_info.ver = val; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->protocol_info.init_state_reg = SSD_INIT_STATE_REG0; + dev->protocol_info.init_state_reg_sz = SSD_INIT_STATE_REG_SZ; + + dev->protocol_info.chip_info_reg = SSD_CHIP_INFO_REG0; + dev->protocol_info.chip_info_reg_sz = SSD_CHIP_INFO_REG_SZ; + } else { + dev->protocol_info.init_state_reg = SSD_PV3_INIT_STATE_REG0; + dev->protocol_info.init_state_reg_sz = SSD_PV3_INIT_STATE_REG_SZ; + + dev->protocol_info.chip_info_reg = SSD_PV3_CHIP_INFO_REG0; + dev->protocol_info.chip_info_reg_sz = SSD_PV3_CHIP_INFO_REG_SZ; + } + + return 0; +} + +static int ssd_init_hw_info(struct ssd_device *dev) +{ + uint64_t val64; + uint32_t val; + uint32_t nr_ctrl; + int ret = 0; + + /* base info */ + val = ssd_reg32_read(dev->ctrlp + SSD_RESP_INFO_REG); + dev->hw_info.resp_ptr_sz = 16 * (1U << (val & 0xFF)); + dev->hw_info.resp_msg_sz = 16 * (1U << ((val >> 8) & 0xFF)); + + if (0 == dev->hw_info.resp_ptr_sz || 0 == dev->hw_info.resp_msg_sz) { + hio_warn("%s: response info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_INFO_REG); + dev->hw_info.cmd_fifo_sz = 1U << ((val >> 4) & 0xF); + dev->hw_info.cmd_max_sg = 1U << ((val >> 8) & 0xF); + dev->hw_info.sg_max_sec = 1U << ((val >> 12) & 0xF); + dev->hw_info.cmd_fifo_sz_mask = dev->hw_info.cmd_fifo_sz - 1; + + if (0 == dev->hw_info.cmd_fifo_sz || 0 == dev->hw_info.cmd_max_sg || 0 == dev->hw_info.sg_max_sec) { + hio_warn("%s: cmd info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + /* check hw */ + if (ssd_check_hw_bh(dev)) { + hio_warn("%s: check hardware status failed\n", dev->name); + ret = -EINVAL; + goto out; + } + + if (ssd_check_controller(dev)) { + hio_warn("%s: check controller state failed\n", dev->name); + ret = -EINVAL; + goto out; + } + + /* nr controller : read again*/ + val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_INFO_REG); + dev->hw_info.nr_ctrl = (val >> 16) & 0xF; + + /* nr ctrl configured */ + nr_ctrl = (val >> 20) & 0xF; + if (0 == dev->hw_info.nr_ctrl) { + hio_warn("%s: nr controller error: %u\n", dev->name, dev->hw_info.nr_ctrl); + ret = -EINVAL; + goto out; + } else if (0 != nr_ctrl && nr_ctrl != dev->hw_info.nr_ctrl) { + hio_warn("%s: nr controller error: configured %u but found %u\n", dev->name, nr_ctrl, dev->hw_info.nr_ctrl); + if (mode <= SSD_DRV_MODE_STANDARD) { + ret = -EINVAL; + goto out; + } + } + + if (ssd_check_controller_bh(dev)) { + hio_warn("%s: check controller failed\n", dev->name); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_PCB_VER_REG); + dev->hw_info.pcb_ver = (uint8_t) ((val >> 4) & 0xF) + 'A' -1; + if ((val & 0xF) != 0xF) { + dev->hw_info.upper_pcb_ver = (uint8_t) (val & 0xF) + 'A' -1; + } + + if (dev->hw_info.pcb_ver < 'A' || (0 != dev->hw_info.upper_pcb_ver && dev->hw_info.upper_pcb_ver < 'A')) { + hio_warn("%s: PCB version error: %#x %#x\n", dev->name, dev->hw_info.pcb_ver, dev->hw_info.upper_pcb_ver); + ret = -EINVAL; + goto out; + } + + /* channel info */ + if (mode <= SSD_DRV_MODE_DEBUG) { + val = ssd_reg32_read(dev->ctrlp + SSD_CH_INFO_REG); + dev->hw_info.nr_data_ch = val & 0xFF; + dev->hw_info.nr_ch = dev->hw_info.nr_data_ch + ((val >> 8) & 0xFF); + dev->hw_info.nr_chip = (val >> 16) & 0xFF; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + dev->hw_info.max_ch = 1; + while (dev->hw_info.max_ch < dev->hw_info.nr_ch) dev->hw_info.max_ch <<= 1; + } else { + /* set max channel 32 */ + dev->hw_info.max_ch = 32; + } + + if (0 == dev->hw_info.nr_chip) { + //for debug mode + dev->hw_info.nr_chip = 1; + } + + //xx + dev->hw_info.id_size = SSD_NAND_ID_SZ; + dev->hw_info.max_ce = SSD_NAND_MAX_CE; + + if (0 == dev->hw_info.nr_data_ch || 0 == dev->hw_info.nr_ch || 0 == dev->hw_info.nr_chip) { + hio_warn("%s: channel info error: data_ch %u ch %u chip %u\n", dev->name, dev->hw_info.nr_data_ch, dev->hw_info.nr_ch, dev->hw_info.nr_chip); + ret = -EINVAL; + goto out; + } + } + + /* ram info */ + if (mode <= SSD_DRV_MODE_DEBUG) { + val = ssd_reg32_read(dev->ctrlp + SSD_RAM_INFO_REG); + dev->hw_info.ram_size = 0x4000000ull * (1ULL << (val & 0xF)); + dev->hw_info.ram_align = 1U << ((val >> 12) & 0xF); + if (dev->hw_info.ram_align < SSD_RAM_ALIGN) { + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->hw_info.ram_align = SSD_RAM_ALIGN; + } else { + hio_warn("%s: ram align error: %u\n", dev->name, dev->hw_info.ram_align); + ret = -EINVAL; + goto out; + } + } + dev->hw_info.ram_max_len = 0x1000 * (1U << ((val >> 16) & 0xF)); + + if (0 == dev->hw_info.ram_size || 0 == dev->hw_info.ram_align || 0 == dev->hw_info.ram_max_len || dev->hw_info.ram_align > dev->hw_info.ram_max_len) { + hio_warn("%s: ram info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->hw_info.log_sz = SSD_LOG_MAX_SZ; + } else { + val = ssd_reg32_read(dev->ctrlp + SSD_LOG_INFO_REG); + dev->hw_info.log_sz = 0x1000 * (1U << (val & 0xFF)); + } + if (0 == dev->hw_info.log_sz) { + hio_warn("%s: log size error\n", dev->name); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_BBT_BASE_REG); + dev->hw_info.bbt_base = 0x40000ull * (val & 0xFFFF); + dev->hw_info.bbt_size = 0x40000 * (((val >> 16) & 0xFFFF) + 1) / (dev->hw_info.max_ch * dev->hw_info.nr_chip); + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + if (dev->hw_info.bbt_base > dev->hw_info.ram_size || 0 == dev->hw_info.bbt_size) { + hio_warn("%s: bbt info error\n", dev->name); + ret = -EINVAL; + goto out; + } + } + + val = ssd_reg32_read(dev->ctrlp + SSD_ECT_BASE_REG); + dev->hw_info.md_base = 0x40000ull * (val & 0xFFFF); + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + dev->hw_info.md_size = 0x40000 * (((val >> 16) & 0xFFF) + 1) / (dev->hw_info.max_ch * dev->hw_info.nr_chip); + } else { + dev->hw_info.md_size = 0x40000 * (((val >> 16) & 0xFFF) + 1) / (dev->hw_info.nr_chip); + } + dev->hw_info.md_entry_sz = 8 * (1U << ((val >> 28) & 0xF)); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3) { + if (dev->hw_info.md_base > dev->hw_info.ram_size || 0 == dev->hw_info.md_size || + 0 == dev->hw_info.md_entry_sz || dev->hw_info.md_entry_sz > dev->hw_info.md_size) { + hio_warn("%s: md info error\n", dev->name); + ret = -EINVAL; + goto out; + } + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->hw_info.nand_wbuff_base = dev->hw_info.ram_size + 1; + } else { + val = ssd_reg32_read(dev->ctrlp + SSD_NAND_BUFF_BASE); + dev->hw_info.nand_wbuff_base = 0x8000ull * val; + } + } + + /* flash info */ + if (mode <= SSD_DRV_MODE_DEBUG) { + if (dev->hw_info.nr_ctrl > 1) { + val = ssd_reg32_read(dev->ctrlp + SSD_CTRL_VER_REG); + dev->hw_info.ctrl_ver = val & 0xFFF; + hio_info("%s: controller firmware version: %03X\n", dev->name, dev->hw_info.ctrl_ver); + } + + val64 = ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0); + dev->hw_info.nand_vendor_id = ((val64 >> 56) & 0xFF); + dev->hw_info.nand_dev_id = ((val64 >> 48) & 0xFF); + + dev->hw_info.block_count = (((val64 >> 32) & 0xFFFF) + 1); + dev->hw_info.page_count = ((val64>>16) & 0xFFFF); + dev->hw_info.page_size = (val64 & 0xFFFF); + + val = ssd_reg32_read(dev->ctrlp + SSD_BB_INFO_REG); + dev->hw_info.bbf_pages = val & 0xFF; + dev->hw_info.bbf_seek = (val >> 8) & 0x1; + + if (0 == dev->hw_info.block_count || 0 == dev->hw_info.page_count || 0 == dev->hw_info.page_size || dev->hw_info.block_count > INT_MAX) { + hio_warn("%s: flash info error\n", dev->name); + ret = -EINVAL; + goto out; + } + + //xx + dev->hw_info.oob_size = SSD_NAND_OOB_SZ; //(dev->hw_info.page_size) >> 5; + + val = ssd_reg32_read(dev->ctrlp + SSD_VALID_PAGES_REG); + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + dev->hw_info.valid_pages = val & 0x3FF; + dev->hw_info.max_valid_pages = (val>>20) & 0x3FF; + } else { + dev->hw_info.valid_pages = val & 0x7FFF; + dev->hw_info.max_valid_pages = (val>>15) & 0x7FFF; + } + if (0 == dev->hw_info.valid_pages || 0 == dev->hw_info.max_valid_pages || + dev->hw_info.valid_pages > dev->hw_info.max_valid_pages || dev->hw_info.max_valid_pages > dev->hw_info.page_count) { + hio_warn("%s: valid page info error: valid_pages %d, max_valid_pages %d\n", dev->name, dev->hw_info.valid_pages, dev->hw_info.max_valid_pages); + ret = -EINVAL; + goto out; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_RESERVED_BLKS_REG); + dev->hw_info.reserved_blks = val & 0xFFFF; + dev->hw_info.md_reserved_blks = (val >> 16) & 0xFF; + if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) { + dev->hw_info.md_reserved_blks = SSD_BBT_RESERVED; + } + if (dev->hw_info.reserved_blks > dev->hw_info.block_count || dev->hw_info.md_reserved_blks > dev->hw_info.block_count) { + hio_warn("%s: reserved blocks info error: reserved_blks %d, md_reserved_blks %d\n", dev->name, dev->hw_info.reserved_blks, dev->hw_info.md_reserved_blks); + ret = -EINVAL; + goto out; + } + } + + /* size */ + if (mode < SSD_DRV_MODE_DEBUG) { + dev->hw_info.size = (uint64_t)dev->hw_info.valid_pages * dev->hw_info.page_size; + dev->hw_info.size *= (dev->hw_info.block_count - dev->hw_info.reserved_blks); + dev->hw_info.size *= ((uint64_t)dev->hw_info.nr_data_ch * (uint64_t)dev->hw_info.nr_chip * (uint64_t)dev->hw_info.nr_ctrl); + } + + /* extend hardware info */ + val = ssd_reg32_read(dev->ctrlp + SSD_PCB_VER_REG); + dev->hw_info_ext.board_type = (val >> 24) & 0xF; + + dev->hw_info_ext.form_factor = SSD_FORM_FACTOR_FHHL; + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_1) { + dev->hw_info_ext.form_factor = (val >> 31) & 0x1; + } + /* + dev->hw_info_ext.cap_type = (val >> 28) & 0x3; + if (SSD_BM_CAP_VINA != dev->hw_info_ext.cap_type && SSD_BM_CAP_JH != dev->hw_info_ext.cap_type) { + dev->hw_info_ext.cap_type = SSD_BM_CAP_VINA; + }*/ + + /* power loss protect */ + val = ssd_reg32_read(dev->ctrlp + SSD_PLP_INFO_REG); + dev->hw_info_ext.plp_type = (val & 0x3); + if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) { + /* 3 or 4 cap */ + dev->hw_info_ext.cap_type = ((val >> 2)& 0x1); + } + + /* work mode */ + val = ssd_reg32_read(dev->ctrlp + SSD_CH_INFO_REG); + dev->hw_info_ext.work_mode = (val >> 25) & 0x1; + +out: + /* skip error if not in standard mode */ + if (mode != SSD_DRV_MODE_STANDARD) { + ret = 0; + } + return ret; +} + +static void ssd_cleanup_response(struct ssd_device *dev) +{ + int resp_msg_sz = dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * SSD_MSIX_VEC; + int resp_ptr_sz = dev->hw_info.resp_ptr_sz * SSD_MSIX_VEC; + + pci_free_consistent(dev->pdev, resp_ptr_sz, dev->resp_ptr_base, dev->resp_ptr_base_dma); + pci_free_consistent(dev->pdev, resp_msg_sz, dev->resp_msg_base, dev->resp_msg_base_dma); +} + +static int ssd_init_response(struct ssd_device *dev) +{ + int resp_msg_sz = dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * SSD_MSIX_VEC; + int resp_ptr_sz = dev->hw_info.resp_ptr_sz * SSD_MSIX_VEC; + + dev->resp_msg_base = pci_alloc_consistent(dev->pdev, resp_msg_sz, &(dev->resp_msg_base_dma)); + if (!dev->resp_msg_base) { + hio_warn("%s: unable to allocate resp msg DMA buffer\n", dev->name); + goto out_alloc_resp_msg; + } + memset(dev->resp_msg_base, 0xFF, resp_msg_sz); + + dev->resp_ptr_base = pci_alloc_consistent(dev->pdev, resp_ptr_sz, &(dev->resp_ptr_base_dma)); + if (!dev->resp_ptr_base){ + hio_warn("%s: unable to allocate resp ptr DMA buffer\n", dev->name); + goto out_alloc_resp_ptr; + } + memset(dev->resp_ptr_base, 0, resp_ptr_sz); + dev->resp_idx = *(uint32_t *)(dev->resp_ptr_base) = dev->hw_info.cmd_fifo_sz * 2 - 1; + + ssd_reg_write(dev->ctrlp + SSD_RESP_FIFO_REG, dev->resp_msg_base_dma); + ssd_reg_write(dev->ctrlp + SSD_RESP_PTR_REG, dev->resp_ptr_base_dma); + + return 0; + +out_alloc_resp_ptr: + pci_free_consistent(dev->pdev, resp_msg_sz, dev->resp_msg_base, dev->resp_msg_base_dma); +out_alloc_resp_msg: + return -ENOMEM; +} + +static int ssd_cleanup_cmd(struct ssd_device *dev) +{ + int msg_sz = ALIGN(sizeof(struct ssd_rw_msg) + (dev->hw_info.cmd_max_sg - 1) * sizeof(struct ssd_sg_entry), SSD_DMA_ALIGN); + int i; + + for (i=0; i<(int)dev->hw_info.cmd_fifo_sz; i++) { + kfree(dev->cmd[i].sgl); + } + kfree(dev->cmd); + pci_free_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), dev->msg_base, dev->msg_base_dma); + return 0; +} + +static int ssd_init_cmd(struct ssd_device *dev) +{ + int sgl_sz = sizeof(struct scatterlist) * dev->hw_info.cmd_max_sg; + int cmd_sz = sizeof(struct ssd_cmd) * dev->hw_info.cmd_fifo_sz; + int msg_sz = ALIGN(sizeof(struct ssd_rw_msg) + (dev->hw_info.cmd_max_sg - 1) * sizeof(struct ssd_sg_entry), SSD_DMA_ALIGN); + int i; + + spin_lock_init(&dev->cmd_lock); + + dev->msg_base = pci_alloc_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), &dev->msg_base_dma); + if (!dev->msg_base) { + hio_warn("%s: can not alloc cmd msg\n", dev->name); + goto out_alloc_msg; + } + + dev->cmd = kmalloc(cmd_sz, GFP_KERNEL); + if (!dev->cmd) { + hio_warn("%s: can not alloc cmd\n", dev->name); + goto out_alloc_cmd; + } + memset(dev->cmd, 0, cmd_sz); + + for (i=0; i<(int)dev->hw_info.cmd_fifo_sz; i++) { + dev->cmd[i].sgl = kmalloc(sgl_sz, GFP_KERNEL); + if (!dev->cmd[i].sgl) { + hio_warn("%s: can not alloc cmd sgl %d\n", dev->name, i); + goto out_alloc_sgl; + } + + dev->cmd[i].msg = dev->msg_base + (msg_sz * i); + dev->cmd[i].msg_dma = dev->msg_base_dma + ((dma_addr_t)msg_sz * i); + + dev->cmd[i].dev = dev; + dev->cmd[i].tag = i; + dev->cmd[i].flag = 0; + + INIT_LIST_HEAD(&dev->cmd[i].list); + } + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3) { + dev->scmd = ssd_dispatch_cmd; + } else { + ssd_reg_write(dev->ctrlp + SSD_MSG_BASE_REG, dev->msg_base_dma); + if (finject) { + dev->scmd = ssd_send_cmd_db; + } else { + dev->scmd = ssd_send_cmd; + } + } + + return 0; + +out_alloc_sgl: + for (i--; i>=0; i--) { + kfree(dev->cmd[i].sgl); + } + kfree(dev->cmd); +out_alloc_cmd: + pci_free_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), dev->msg_base, dev->msg_base_dma); +out_alloc_msg: + return -ENOMEM; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) +static irqreturn_t ssd_interrupt_check(int irq, void *dev_id) +{ + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + + if (*(uint32_t *)queue->resp_ptr == queue->resp_idx) { + return IRQ_NONE; + } + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t ssd_interrupt_threaded(int irq, void *dev_id) +{ + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + struct ssd_device *dev = (struct ssd_device *)queue->dev; + struct ssd_cmd *cmd; + union ssd_response_msq __msg; + union ssd_response_msq *msg = &__msg; + uint64_t *u64_msg; + uint32_t resp_idx = queue->resp_idx; + uint32_t new_resp_idx = *(uint32_t *)queue->resp_ptr; + uint32_t end_resp_idx; + + if (unlikely(resp_idx == new_resp_idx)) { + return IRQ_NONE; + } + + end_resp_idx = new_resp_idx & queue->resp_idx_mask; + + do { + resp_idx = (resp_idx + 1) & queue->resp_idx_mask; + + /* the resp msg */ + u64_msg = (uint64_t *)(queue->resp_msg + queue->resp_msg_sz * resp_idx); + msg->u64_msg = *u64_msg; + + if (unlikely(msg->u64_msg == (uint64_t)(-1))) { + hio_err("%s: empty resp msg: queue %d idx %u\n", dev->name, queue->idx, resp_idx); + continue; + } + /* clear the resp msg */ + *u64_msg = (uint64_t)(-1); + + cmd = &queue->cmd[msg->resp_msg.tag]; + /*if (unlikely(!cmd->bio)) { + printk(KERN_WARNING "%s: unknown tag %d fun %#x\n", + dev->name, msg->resp_msg.tag, msg->resp_msg.fun); + continue; + }*/ + + if(unlikely(msg->resp_msg.status & (uint32_t)status_mask)) { + cmd->errors = -EIO; + } else { + cmd->errors = 0; + } + cmd->nr_log = msg->log_resp_msg.nr_log; + + ssd_done(cmd); + + if (unlikely(msg->resp_msg.fun != SSD_FUNC_READ_LOG && msg->resp_msg.log > 0)) { + (void)test_and_set_bit(SSD_LOG_HW, &dev->state); + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->log_work); + } + } + + if (unlikely(msg->resp_msg.status)) { + if (msg->resp_msg.fun == SSD_FUNC_READ || msg->resp_msg.fun == SSD_FUNC_WRITE) { + hio_err("%s: I/O error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + /* alarm led */ + ssd_set_alarm(dev); + queue->io_stat.nr_rwerr++; + ssd_gen_swlog(dev, SSD_LOG_EIO, msg->u32_msg[0]); + } else { + hio_info("%s: CMD error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + ssd_gen_swlog(dev, SSD_LOG_ECMD, msg->u32_msg[0]); + } + queue->io_stat.nr_ioerr++; + } + + if (msg->resp_msg.fun == SSD_FUNC_READ || + msg->resp_msg.fun == SSD_FUNC_NAND_READ_WOOB || + msg->resp_msg.fun == SSD_FUNC_NAND_READ) { + + queue->ecc_info.bitflip[msg->resp_msg.bitflip]++; + } + }while (resp_idx != end_resp_idx); + + queue->resp_idx = new_resp_idx; + + return IRQ_HANDLED; +} +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) +static irqreturn_t ssd_interrupt(int irq, void *dev_id, struct pt_regs *regs) +#else +static irqreturn_t ssd_interrupt(int irq, void *dev_id) +#endif +{ + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + struct ssd_device *dev = (struct ssd_device *)queue->dev; + struct ssd_cmd *cmd; + union ssd_response_msq __msg; + union ssd_response_msq *msg = &__msg; + uint64_t *u64_msg; + uint32_t resp_idx = queue->resp_idx; + uint32_t new_resp_idx = *(uint32_t *)queue->resp_ptr; + uint32_t end_resp_idx; + + if (unlikely(resp_idx == new_resp_idx)) { + return IRQ_NONE; + } + +#if (defined SSD_ESCAPE_IRQ) + if (SSD_INT_MSIX != dev->int_mode) { + dev->irq_cpu = smp_processor_id(); + } +#endif + + end_resp_idx = new_resp_idx & queue->resp_idx_mask; + + do { + resp_idx = (resp_idx + 1) & queue->resp_idx_mask; + + /* the resp msg */ + u64_msg = (uint64_t *)(queue->resp_msg + queue->resp_msg_sz * resp_idx); + msg->u64_msg = *u64_msg; + + if (unlikely(msg->u64_msg == (uint64_t)(-1))) { + hio_err("%s: empty resp msg: queue %d idx %u\n", dev->name, queue->idx, resp_idx); + continue; + } + /* clear the resp msg */ + *u64_msg = (uint64_t)(-1); + + cmd = &queue->cmd[msg->resp_msg.tag]; + /*if (unlikely(!cmd->bio)) { + printk(KERN_WARNING "%s: unknown tag %d fun %#x\n", + dev->name, msg->resp_msg.tag, msg->resp_msg.fun); + continue; + }*/ + + if(unlikely(msg->resp_msg.status & (uint32_t)status_mask)) { + cmd->errors = -EIO; + } else { + cmd->errors = 0; + } + cmd->nr_log = msg->log_resp_msg.nr_log; + + ssd_done_bh(cmd); + + if (unlikely(msg->resp_msg.fun != SSD_FUNC_READ_LOG && msg->resp_msg.log > 0)) { + (void)test_and_set_bit(SSD_LOG_HW, &dev->state); + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->log_work); + } + } + + if (unlikely(msg->resp_msg.status)) { + if (msg->resp_msg.fun == SSD_FUNC_READ || msg->resp_msg.fun == SSD_FUNC_WRITE) { + hio_err("%s: I/O error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + /* alarm led */ + ssd_set_alarm(dev); + queue->io_stat.nr_rwerr++; + ssd_gen_swlog(dev, SSD_LOG_EIO, msg->u32_msg[0]); + } else { + hio_info("%s: CMD error %d: tag %d fun %#x\n", + dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun); + + ssd_gen_swlog(dev, SSD_LOG_ECMD, msg->u32_msg[0]); + } + queue->io_stat.nr_ioerr++; + } + + if (msg->resp_msg.fun == SSD_FUNC_READ || + msg->resp_msg.fun == SSD_FUNC_NAND_READ_WOOB || + msg->resp_msg.fun == SSD_FUNC_NAND_READ) { + + queue->ecc_info.bitflip[msg->resp_msg.bitflip]++; + } + }while (resp_idx != end_resp_idx); + + queue->resp_idx = new_resp_idx; + + return IRQ_HANDLED; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) +static irqreturn_t ssd_interrupt_legacy(int irq, void *dev_id, struct pt_regs *regs) +#else +static irqreturn_t ssd_interrupt_legacy(int irq, void *dev_id) +#endif +{ + irqreturn_t ret; + struct ssd_queue *queue = (struct ssd_queue *)dev_id; + struct ssd_device *dev = (struct ssd_device *)queue->dev; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) + ret = ssd_interrupt(irq, dev_id, regs); +#else + ret = ssd_interrupt(irq, dev_id); +#endif + + /* clear intr */ + if (IRQ_HANDLED == ret) { + ssd_reg32_write(dev->ctrlp + SSD_CLEAR_INTR_REG, 1); + } + + return ret; +} + +static void ssd_reset_resp_ptr(struct ssd_device *dev) +{ + int i; + + for (i=0; inr_queue; i++) { + *(uint32_t *)dev->queue[i].resp_ptr = dev->queue[i].resp_idx = (dev->hw_info.cmd_fifo_sz * 2) - 1; + } +} + +static void ssd_free_irq(struct ssd_device *dev) +{ + int i; + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + if (SSD_INT_MSIX == dev->int_mode) { + for (i=0; inr_queue; i++) { + irq_set_affinity_hint(dev->entry[i].vector, NULL); + } + } +#endif + + for (i=0; inr_queue; i++) { + free_irq(dev->entry[i].vector, &dev->queue[i]); + } + + if (SSD_INT_MSIX == dev->int_mode) { + pci_disable_msix(dev->pdev); + } else if (SSD_INT_MSI == dev->int_mode) { + pci_disable_msi(dev->pdev); + } + +} + +static int ssd_init_irq(struct ssd_device *dev) +{ +#if (!defined MODULE) && (defined SSD_MSIX_AFFINITY_FORCE) + const struct cpumask *cpu_mask; + static int cpu_affinity = 0; +#endif +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + const struct cpumask *mask; + static int cpu = 0; + int j; +#endif + int i; + unsigned long flags = 0; + int ret = 0; + + ssd_reg32_write(dev->ctrlp + SSD_INTR_INTERVAL_REG, 0x800); + +#ifdef SSD_ESCAPE_IRQ + dev->irq_cpu = -1; +#endif + + if (int_mode >= SSD_INT_MSIX && pci_find_capability(dev->pdev, PCI_CAP_ID_MSIX)) { + dev->nr_queue = SSD_MSIX_VEC; + for (i=0; inr_queue; i++) { + dev->entry[i].entry = i; + } + for (;;) { + ret = pci_enable_msix(dev->pdev, dev->entry, dev->nr_queue); + if (ret == 0) { + break; + } else if (ret > 0) { + dev->nr_queue = ret; + } else { + hio_warn("%s: can not enable msix\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out; + } + } + +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + mask = (dev_to_node(&dev->pdev->dev) == -1) ? cpu_online_mask : cpumask_of_node(dev_to_node(&dev->pdev->dev)); + if ((0 == cpu) || (!cpumask_intersects(mask, cpumask_of(cpu)))) { + cpu = cpumask_first(mask); + } + for (i=0; inr_queue; i++) { + irq_set_affinity_hint(dev->entry[i].vector, cpumask_of(cpu)); + cpu = cpumask_next(cpu, mask); + if (cpu >= nr_cpu_ids) { + cpu = cpumask_first(mask); + } + } +#endif + + dev->int_mode = SSD_INT_MSIX; + } else if (int_mode >= SSD_INT_MSI && pci_find_capability(dev->pdev, PCI_CAP_ID_MSI)) { + ret = pci_enable_msi(dev->pdev); + if (ret) { + hio_warn("%s: can not enable msi\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out; + } + + dev->nr_queue = 1; + dev->entry[0].vector = dev->pdev->irq; + + dev->int_mode = SSD_INT_MSI; + } else { + dev->nr_queue = 1; + dev->entry[0].vector = dev->pdev->irq; + + dev->int_mode = SSD_INT_LEGACY; + } + + for (i=0; inr_queue; i++) { + if (dev->nr_queue > 1) { + snprintf(dev->queue[i].name, SSD_QUEUE_NAME_LEN, "%s_e100-%d", dev->name, i); + } else { + snprintf(dev->queue[i].name, SSD_QUEUE_NAME_LEN, "%s_e100", dev->name); + } + + dev->queue[i].dev = dev; + dev->queue[i].idx = i; + + dev->queue[i].resp_idx = (dev->hw_info.cmd_fifo_sz * 2) - 1; + dev->queue[i].resp_idx_mask = dev->hw_info.cmd_fifo_sz - 1; + + dev->queue[i].resp_msg_sz = dev->hw_info.resp_msg_sz; + dev->queue[i].resp_msg = dev->resp_msg_base + dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * i; + dev->queue[i].resp_ptr = dev->resp_ptr_base + dev->hw_info.resp_ptr_sz * i; + *(uint32_t *)dev->queue[i].resp_ptr = dev->queue[i].resp_idx; + + dev->queue[i].cmd = dev->cmd; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + flags = IRQF_SHARED; +#else + flags = SA_SHIRQ; +#endif + + for (i=0; inr_queue; i++) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) + if (threaded_irq) { + ret = request_threaded_irq(dev->entry[i].vector, ssd_interrupt_check, ssd_interrupt_threaded, flags, dev->queue[i].name, &dev->queue[i]); + } else if (dev->int_mode == SSD_INT_LEGACY) { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt_legacy, flags, dev->queue[i].name, &dev->queue[i]); + } else { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt, flags, dev->queue[i].name, &dev->queue[i]); + } +#else + if (dev->int_mode == SSD_INT_LEGACY) { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt_legacy, flags, dev->queue[i].name, &dev->queue[i]); + } else { + ret = request_irq(dev->entry[i].vector, &ssd_interrupt, flags, dev->queue[i].name, &dev->queue[i]); + } +#endif + if (ret) { + hio_warn("%s: request irq failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_request_irq; + } + +#if (!defined MODULE) && (defined SSD_MSIX_AFFINITY_FORCE) + cpu_mask = (dev_to_node(&dev->pdev->dev) == -1) ? cpu_online_mask : cpumask_of_node(dev_to_node(&dev->pdev->dev)); + if (SSD_INT_MSIX == dev->int_mode) { + if ((0 == cpu_affinity) || (!cpumask_intersects(mask, cpumask_of(cpu_affinity)))) { + cpu_affinity = cpumask_first(cpu_mask); + } + + irq_set_affinity(dev->entry[i].vector, cpumask_of(cpu_affinity)); + cpu_affinity = cpumask_next(cpu_affinity, cpu_mask); + if (cpu_affinity >= nr_cpu_ids) { + cpu_affinity = cpumask_first(cpu_mask); + } + } +#endif + } + + return ret; + +out_request_irq: +#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6)) + if (SSD_INT_MSIX == dev->int_mode) { + for (j=0; jnr_queue; j++) { + irq_set_affinity_hint(dev->entry[j].vector, NULL); + } + } +#endif + + for (i--; i>=0; i--) { + free_irq(dev->entry[i].vector, &dev->queue[i]); + } + + if (SSD_INT_MSIX == dev->int_mode) { + pci_disable_msix(dev->pdev); + } else if (SSD_INT_MSI == dev->int_mode) { + pci_disable_msi(dev->pdev); + } + +out: + return ret; +} + +static void ssd_initial_log(struct ssd_device *dev) +{ + uint32_t val; + uint32_t speed, width; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return; + } + + val = ssd_reg32_read(dev->ctrlp + SSD_POWER_ON_REG); + if (val) { + ssd_gen_swlog(dev, SSD_LOG_POWER_ON, dev->hw_info.bridge_ver); + } + + val = ssd_reg32_read(dev->ctrlp + SSD_PCIE_LINKSTATUS_REG); + speed = val & 0xF; + width = (val >> 4)& 0x3F; + if (0x1 == speed) { + hio_info("%s: PCIe: 2.5GT/s, x%u\n", dev->name, width); + } else if (0x2 == speed) { + hio_info("%s: PCIe: 5GT/s, x%u\n", dev->name, width); + } else { + hio_info("%s: PCIe: unknown GT/s, x%u\n", dev->name, width); + } + ssd_gen_swlog(dev, SSD_LOG_PCIE_LINK_STATUS, val); + + return; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_hwmon_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_hwmon_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, hwmon_work); +#endif + + if (ssd_check_hw(dev)) { + //hio_err("%s: check hardware failed\n", dev->name); + return; + } + + ssd_check_clock(dev); + ssd_check_volt(dev); + + ssd_mon_boardvolt(dev); +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_tempmon_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_tempmon_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, tempmon_work); +#endif + + if (ssd_check_hw(dev)) { + //hio_err("%s: check hardware failed\n", dev->name); + return; + } + + ssd_mon_temp(dev); +} + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +static void ssd_capmon_worker(void *data) +{ + struct ssd_device *dev = (struct ssd_device *)data; +#else +static void ssd_capmon_worker(struct work_struct *work) +{ + struct ssd_device *dev = container_of(work, struct ssd_device, capmon_work); +#endif + uint32_t cap = 0; + uint32_t cap_threshold = SSD_PL_CAP_THRESHOLD; + int ret = 0; + + if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) { + return; + } + + if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') { + return; + } + + /* fault before? */ + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ret = ssd_check_pl_cap_fast(dev); + if (ret) { + return; + } + } + + /* learn */ + ret = ssd_do_cap_learn(dev, &cap); + if (ret) { + hio_err("%s: cap learn failed\n", dev->name); + ssd_gen_swlog(dev, SSD_LOG_CAP_LEARN_FAULT, 0); + return; + } + + ssd_gen_swlog(dev, SSD_LOG_CAP_STATUS, cap); + + if (SSD_PL_CAP_CP == dev->hw_info_ext.cap_type) { + cap_threshold = SSD_PL_CAP_CP_THRESHOLD; + } + + //use the fw event id? + if (cap < cap_threshold) { + if (!test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_BATTERY_FAULT, 0); + } + } else if (cap >= (cap_threshold + SSD_PL_CAP_THRESHOLD_HYST)) { + if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) { + ssd_gen_swlog(dev, SSD_LOG_BATTERY_OK, 0); + } + } +} + +static void ssd_routine_start(void *data) +{ + struct ssd_device *dev; + + if (!data) { + return; + } + dev = data; + + dev->routine_tick++; + + if (test_bit(SSD_INIT_WORKQ, &dev->state) && !ssd_busy(dev)) { + (void)test_and_set_bit(SSD_LOG_HW, &dev->state); + queue_work(dev->workq, &dev->log_work); + } + + if ((dev->routine_tick % SSD_HWMON_ROUTINE_TICK) == 0 && test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->hwmon_work); + } + + if ((dev->routine_tick % SSD_CAPMON_ROUTINE_TICK) == 0 && test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->capmon_work); + } + + if ((dev->routine_tick % SSD_CAPMON2_ROUTINE_TICK) == 0 && test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon) && test_bit(SSD_INIT_WORKQ, &dev->state)) { + /* CAP fault? check again */ + queue_work(dev->workq, &dev->capmon_work); + } + + if (test_bit(SSD_INIT_WORKQ, &dev->state)) { + queue_work(dev->workq, &dev->tempmon_work); + } + + /* schedule routine */ + mod_timer(&dev->routine_timer, jiffies + msecs_to_jiffies(SSD_ROUTINE_INTERVAL)); +} + +static void ssd_cleanup_routine(struct ssd_device *dev) +{ + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return; + + (void)ssd_del_timer(&dev->routine_timer); + + (void)ssd_del_timer(&dev->bm_timer); +} + +static int ssd_init_routine(struct ssd_device *dev) +{ + if (unlikely(mode != SSD_DRV_MODE_STANDARD)) + return 0; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + INIT_WORK(&dev->bm_work, ssd_bm_worker, dev); + INIT_WORK(&dev->hwmon_work, ssd_hwmon_worker, dev); + INIT_WORK(&dev->capmon_work, ssd_capmon_worker, dev); + INIT_WORK(&dev->tempmon_work, ssd_tempmon_worker, dev); +#else + INIT_WORK(&dev->bm_work, ssd_bm_worker); + INIT_WORK(&dev->hwmon_work, ssd_hwmon_worker); + INIT_WORK(&dev->capmon_work, ssd_capmon_worker); + INIT_WORK(&dev->tempmon_work, ssd_tempmon_worker); +#endif + + /* initial log */ + ssd_initial_log(dev); + + /* schedule bm routine */ + ssd_add_timer(&dev->bm_timer, msecs_to_jiffies(SSD_BM_CAP_LEARNING_DELAY), ssd_bm_routine_start, dev); + + /* schedule routine */ + ssd_add_timer(&dev->routine_timer, msecs_to_jiffies(SSD_ROUTINE_INTERVAL), ssd_routine_start, dev); + + return 0; +} + +static void +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) +__devexit +#endif +ssd_remove_one (struct pci_dev *pdev) +{ + struct ssd_device *dev; + + if (!pdev) { + return; + } + + dev = pci_get_drvdata(pdev); + if (!dev) { + return; + } + + list_del_init(&dev->list); + + ssd_unregister_sysfs(dev); + + /* offline firstly */ + test_and_clear_bit(SSD_ONLINE, &dev->state); + + /* clean work queue first */ + if (!dev->slave) { + test_and_clear_bit(SSD_INIT_WORKQ, &dev->state); + ssd_cleanup_workq(dev); + } + + /* flush cache */ + (void)ssd_flush(dev); + (void)ssd_save_md(dev); + + /* save smart */ + if (!dev->slave) { + ssd_save_smart(dev); + } + + if (test_and_clear_bit(SSD_INIT_BD, &dev->state)) { + ssd_cleanup_blkdev(dev); + } + + if (!dev->slave) { + ssd_cleanup_chardev(dev); + } + + /* clean routine */ + if (!dev->slave) { + ssd_cleanup_routine(dev); + } + + ssd_cleanup_queue(dev); + + ssd_cleanup_tag(dev); + ssd_cleanup_thread(dev); + + ssd_free_irq(dev); + + ssd_cleanup_dcmd(dev); + ssd_cleanup_cmd(dev); + ssd_cleanup_response(dev); + + if (!dev->slave) { + ssd_cleanup_log(dev); + } + + if (dev->reload_fw) { //reload fw + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW); + } + + /* unmap physical adress */ +#ifdef LINUX_SUSE_OS + iounmap(dev->ctrlp); +#else + pci_iounmap(pdev, dev->ctrlp); +#endif + + release_mem_region(dev->mmio_base, dev->mmio_len); + + pci_disable_device(pdev); + + pci_set_drvdata(pdev, NULL); + + ssd_put(dev); +} + +static int +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) +__devinit +#endif +ssd_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct ssd_device *dev; + int ret = 0; + + if (!pdev || !ent) { + ret = -EINVAL; + goto out; + } + + dev = kmalloc(sizeof(struct ssd_device), GFP_KERNEL); + if (!dev) { + ret = -ENOMEM; + goto out_alloc_dev; + } + memset(dev, 0, sizeof(struct ssd_device)); + + dev->owner = THIS_MODULE; + + if (SSD_SLAVE_PORT_DEVID == ent->device) { + dev->slave = 1; + } + + dev->idx = ssd_get_index(dev->slave); + if (dev->idx < 0) { + ret = -ENOMEM; + goto out_get_index; + } + + if (!dev->slave) { + snprintf(dev->name, SSD_DEV_NAME_LEN, SSD_DEV_NAME); + ssd_set_dev_name(&dev->name[strlen(SSD_DEV_NAME)], SSD_DEV_NAME_LEN-strlen(SSD_DEV_NAME), dev->idx); + + dev->major = ssd_major; + dev->cmajor = ssd_cmajor; + } else { + snprintf(dev->name, SSD_DEV_NAME_LEN, SSD_SDEV_NAME); + ssd_set_dev_name(&dev->name[strlen(SSD_SDEV_NAME)], SSD_DEV_NAME_LEN-strlen(SSD_SDEV_NAME), dev->idx); + dev->major = ssd_major_sl; + dev->cmajor = 0; + } + + atomic_set(&(dev->refcnt), 0); + atomic_set(&(dev->tocnt), 0); + + mutex_init(&dev->fw_mutex); + + //xx + mutex_init(&dev->gd_mutex); + + dev->pdev = pdev; + pci_set_drvdata(pdev, dev); + + kref_init(&dev->kref); + + ret = pci_enable_device(pdev); + if (ret) { + hio_warn("%s: can not enable device\n", dev->name); + goto out_enable_device; + } + + pci_set_master(pdev); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)) + ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK); +#else + ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); +#endif + if (ret) { + hio_warn("%s: set dma mask: failed\n", dev->name); + goto out_set_dma_mask; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)) + ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); +#else + ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); +#endif + if (ret) { + hio_warn("%s: set consistent dma mask: failed\n", dev->name); + goto out_set_dma_mask; + } + + dev->mmio_base = pci_resource_start(pdev, 0); + dev->mmio_len = pci_resource_len(pdev, 0); + + if (!request_mem_region(dev->mmio_base, dev->mmio_len, SSD_DEV_NAME)) { + hio_warn("%s: can not reserve MMIO region 0\n", dev->name); + ret = -EBUSY; + goto out_request_mem_region; + } + + /* 2.6.9 kernel bug */ + dev->ctrlp = pci_iomap(pdev, 0, 0); + if (!dev->ctrlp) { + hio_warn("%s: can not remap IO region 0\n", dev->name); + ret = -ENOMEM; + goto out_pci_iomap; + } + + ret = ssd_check_hw(dev); + if (ret) { + hio_err("%s: check hardware failed\n", dev->name); + goto out_check_hw; + } + + ret = ssd_init_protocol_info(dev); + if (ret) { + hio_err("%s: init protocol info failed\n", dev->name); + goto out_init_protocol_info; + } + + /* alarm led ? */ + ssd_clear_alarm(dev); + + ret = ssd_init_fw_info(dev); + if (ret) { + hio_err("%s: init firmware info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_fw_info; + } + + /* slave port ? */ + if (dev->slave) { + goto init_next1; + } + + ret = ssd_init_rom_info(dev); + if (ret) { + hio_err("%s: init rom info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_rom_info; + } + + ret = ssd_init_label(dev); + if (ret) { + hio_err("%s: init label failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_label; + } + + ret = ssd_init_workq(dev); + if (ret) { + hio_warn("%s: init workq failed\n", dev->name); + goto out_init_workq; + } + (void)test_and_set_bit(SSD_INIT_WORKQ, &dev->state); + + ret = ssd_init_log(dev); + if (ret) { + hio_err("%s: init log failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_log; + } + + ret = ssd_init_smart(dev); + if (ret) { + hio_err("%s: init info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_smart; + } + +init_next1: + ret = ssd_init_hw_info(dev); + if (ret) { + hio_err("%s: init hardware info failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_hw_info; + } + + /* slave port ? */ + if (dev->slave) { + goto init_next2; + } + + ret = ssd_init_sensor(dev); + if (ret) { + hio_err("%s: init sensor failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_sensor; + } + + ret = ssd_init_pl_cap(dev); + if (ret) { + hio_err("%s: int pl_cap failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_init_pl_cap; + } + +init_next2: + ret = ssd_check_init_state(dev); + if (ret) { + hio_err("%s: check init state failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_check_init_state; + } + + ret = ssd_init_response(dev); + if (ret) { + hio_warn("%s: init resp_msg failed\n", dev->name); + goto out_init_response; + } + + ret = ssd_init_cmd(dev); + if (ret) { + hio_warn("%s: init msg failed\n", dev->name); + goto out_init_cmd; + } + + ret = ssd_init_dcmd(dev); + if (ret) { + hio_warn("%s: init cmd failed\n", dev->name); + goto out_init_dcmd; + } + + ret = ssd_init_irq(dev); + if (ret) { + hio_warn("%s: init irq failed\n", dev->name); + goto out_init_irq; + } + + ret = ssd_init_thread(dev); + if (ret) { + hio_warn("%s: init thread failed\n", dev->name); + goto out_init_thread; + } + + ret = ssd_init_tag(dev); + if(ret) { + hio_warn("%s: init tags failed\n", dev->name); + goto out_init_tags; + } + + /* */ + (void)test_and_set_bit(SSD_ONLINE, &dev->state); + + ret = ssd_init_queue(dev); + if (ret) { + hio_warn("%s: init queue failed\n", dev->name); + goto out_init_queue; + } + + /* slave port ? */ + if (dev->slave) { + goto init_next3; + } + + ret = ssd_init_ot_protect(dev); + if (ret) { + hio_err("%s: int ot_protect failed\n", dev->name); + /* alarm led */ + ssd_set_alarm(dev); + goto out_int_ot_protect; + } + + ret = ssd_init_wmode(dev); + if (ret) { + hio_warn("%s: init write mode\n", dev->name); + goto out_init_wmode; + } + + /* init routine after hw is ready */ + ret = ssd_init_routine(dev); + if (ret) { + hio_warn("%s: init routine\n", dev->name); + goto out_init_routine; + } + + ret = ssd_init_chardev(dev); + if (ret) { + hio_warn("%s: register char device failed\n", dev->name); + goto out_init_chardev; + } + +init_next3: + ret = ssd_init_blkdev(dev); + if (ret) { + hio_warn("%s: register block device failed\n", dev->name); + goto out_init_blkdev; + } + (void)test_and_set_bit(SSD_INIT_BD, &dev->state); + + ret = ssd_register_sysfs(dev); + if (ret) { + hio_warn("%s: register sysfs failed\n", dev->name); + goto out_register_sysfs; + } + + dev->save_md = 1; + + list_add_tail(&dev->list, &ssd_list); + + return 0; + +out_register_sysfs: + test_and_clear_bit(SSD_INIT_BD, &dev->state); + ssd_cleanup_blkdev(dev); +out_init_blkdev: + /* slave port ? */ + if (!dev->slave) { + ssd_cleanup_chardev(dev); + } +out_init_chardev: + /* slave port ? */ + if (!dev->slave) { + ssd_cleanup_routine(dev); + } +out_init_routine: +out_init_wmode: +out_int_ot_protect: + ssd_cleanup_queue(dev); +out_init_queue: + test_and_clear_bit(SSD_ONLINE, &dev->state); + ssd_cleanup_tag(dev); +out_init_tags: + ssd_cleanup_thread(dev); +out_init_thread: + ssd_free_irq(dev); +out_init_irq: + ssd_cleanup_dcmd(dev); +out_init_dcmd: + ssd_cleanup_cmd(dev); +out_init_cmd: + ssd_cleanup_response(dev); +out_init_response: +out_check_init_state: +out_init_pl_cap: +out_init_sensor: +out_init_hw_info: +out_init_smart: + /* slave port ? */ + if (!dev->slave) { + ssd_cleanup_log(dev); + } +out_init_log: + /* slave port ? */ + if (!dev->slave) { + test_and_clear_bit(SSD_INIT_WORKQ, &dev->state); + ssd_cleanup_workq(dev); + } +out_init_workq: +out_init_label: +out_init_rom_info: +out_init_fw_info: +out_init_protocol_info: +out_check_hw: +#ifdef LINUX_SUSE_OS + iounmap(dev->ctrlp); +#else + pci_iounmap(pdev, dev->ctrlp); +#endif +out_pci_iomap: + release_mem_region(dev->mmio_base, dev->mmio_len); +out_request_mem_region: +out_set_dma_mask: + pci_disable_device(pdev); +out_enable_device: + pci_set_drvdata(pdev, NULL); +out_get_index: + kfree(dev); +out_alloc_dev: +out: + return ret; +} + +static void ssd_cleanup_tasklet(void) +{ + int i; + for_each_online_cpu(i) { + tasklet_kill(&per_cpu(ssd_tasklet, i)); + } +} + +static int ssd_init_tasklet(void) +{ + int i; + + for_each_online_cpu(i) { + INIT_LIST_HEAD(&per_cpu(ssd_doneq, i)); + + if (finject) { + tasklet_init(&per_cpu(ssd_tasklet, i), __ssd_done_db, 0); + } else { + tasklet_init(&per_cpu(ssd_tasklet, i), __ssd_done, 0); + } + } + + return 0; +} + +static struct pci_device_id ssd_pci_tbl[] = { + { 0x10ee, 0x0007, PCI_ANY_ID, PCI_ANY_ID, }, /* g3 */ + { 0x19e5, 0x0007, PCI_ANY_ID, PCI_ANY_ID, }, /* v1 */ + //{ 0x19e5, 0x0008, PCI_ANY_ID, PCI_ANY_ID, }, /* v1 sp*/ + { 0x19e5, 0x0009, PCI_ANY_ID, PCI_ANY_ID, }, /* v2 */ + { 0x19e5, 0x000a, PCI_ANY_ID, PCI_ANY_ID, }, /* v2 dp slave*/ + { 0, } +}; +MODULE_DEVICE_TABLE(pci, ssd_pci_tbl); + +static struct pci_driver ssd_driver = { + .name = MODULE_NAME, + .id_table = ssd_pci_tbl, + .probe = ssd_init_one, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) + .remove = __devexit_p(ssd_remove_one), +#else + .remove = ssd_remove_one, +#endif +}; + +/* notifier block to get a notify on system shutdown/halt/reboot */ +static int ssd_notify_reboot(struct notifier_block *nb, unsigned long event, void *buf) +{ + struct ssd_device *dev = NULL; + struct ssd_device *n = NULL; + + list_for_each_entry_safe(dev, n, &ssd_list, list) { + ssd_gen_swlog(dev, SSD_LOG_POWER_OFF, 0); + + (void)ssd_flush(dev); + (void)ssd_save_md(dev); + + /* slave port ? */ + if (!dev->slave) { + ssd_save_smart(dev); + + ssd_stop_workq(dev); + + if (dev->reload_fw) { + ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW); + } + } + } + + return NOTIFY_OK; +} + +static struct notifier_block ssd_notifier = { + ssd_notify_reboot, NULL, 0 +}; + +static int __init ssd_init_module(void) +{ + int ret = 0; + + hio_info("driver version: %s\n", DRIVER_VERSION); + + ret = ssd_init_index(); + if (ret) { + hio_warn("init index failed\n"); + goto out_init_index; + } + + ret = ssd_init_proc(); + if (ret) { + hio_warn("init proc failed\n"); + goto out_init_proc; + } + + ret = ssd_init_sysfs(); + if (ret) { + hio_warn("init sysfs failed\n"); + goto out_init_sysfs; + } + + ret = ssd_init_tasklet(); + if (ret) { + hio_warn("init tasklet failed\n"); + goto out_init_tasklet; + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + ssd_class = class_simple_create(THIS_MODULE, SSD_DEV_NAME); +#else + ssd_class = class_create(THIS_MODULE, SSD_DEV_NAME); +#endif + if (IS_ERR(ssd_class)) { + ret = PTR_ERR(ssd_class); + goto out_class_create; + } + + if (ssd_cmajor > 0) { + ret = register_chrdev(ssd_cmajor, SSD_CDEV_NAME, &ssd_cfops); + } else { + ret = ssd_cmajor = register_chrdev(ssd_cmajor, SSD_CDEV_NAME, &ssd_cfops); + } + if (ret < 0) { + hio_warn("unable to register chardev major number\n"); + goto out_register_chardev; + } + + if (ssd_major > 0) { + ret = register_blkdev(ssd_major, SSD_DEV_NAME); + } else { + ret = ssd_major = register_blkdev(ssd_major, SSD_DEV_NAME); + } + if (ret < 0) { + hio_warn("unable to register major number\n"); + goto out_register_blkdev; + } + + if (ssd_major_sl > 0) { + ret = register_blkdev(ssd_major_sl, SSD_SDEV_NAME); + } else { + ret = ssd_major_sl = register_blkdev(ssd_major_sl, SSD_SDEV_NAME); + } + if (ret < 0) { + hio_warn("unable to register slave major number\n"); + goto out_register_blkdev_sl; + } + + if (mode < SSD_DRV_MODE_STANDARD || mode > SSD_DRV_MODE_BASE) { + mode = SSD_DRV_MODE_STANDARD; + } + + /* for debug */ + if (mode != SSD_DRV_MODE_STANDARD) { + ssd_minors = 1; + } + + if (int_mode < SSD_INT_LEGACY || int_mode > SSD_INT_MSIX) { + int_mode = SSD_INT_MODE_DEFAULT; + } + + if (threaded_irq) { + int_mode = SSD_INT_MSI; + } + + if (log_level >= SSD_LOG_NR_LEVEL || log_level < SSD_LOG_LEVEL_INFO) { + log_level = SSD_LOG_LEVEL_ERR; + } + + if (wmode < SSD_WMODE_BUFFER || wmode > SSD_WMODE_DEFAULT) { + wmode = SSD_WMODE_DEFAULT; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) + ret = pci_module_init(&ssd_driver); +#else + ret = pci_register_driver(&ssd_driver); +#endif + if (ret) { + hio_warn("pci init failed\n"); + goto out_pci_init; + } + + ret = register_reboot_notifier(&ssd_notifier); + if (ret) { + hio_warn("register reboot notifier failed\n"); + goto out_register_reboot_notifier; + } + + return 0; + +out_register_reboot_notifier: +out_pci_init: + pci_unregister_driver(&ssd_driver); + unregister_blkdev(ssd_major_sl, SSD_SDEV_NAME); +out_register_blkdev_sl: + unregister_blkdev(ssd_major, SSD_DEV_NAME); +out_register_blkdev: + unregister_chrdev(ssd_cmajor, SSD_CDEV_NAME); +out_register_chardev: +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + class_simple_destroy(ssd_class); +#else + class_destroy(ssd_class); +#endif +out_class_create: + ssd_cleanup_tasklet(); +out_init_tasklet: + ssd_cleanup_sysfs(); +out_init_sysfs: + ssd_cleanup_proc(); +out_init_proc: + ssd_cleanup_index(); +out_init_index: + return ret; + +} + +static void __exit ssd_cleanup_module(void) +{ + + hio_info("unload driver: %s\n", DRIVER_VERSION); + /* exiting */ + ssd_exiting = 1; + + unregister_reboot_notifier(&ssd_notifier); + + pci_unregister_driver(&ssd_driver); + + unregister_blkdev(ssd_major_sl, SSD_SDEV_NAME); + unregister_blkdev(ssd_major, SSD_DEV_NAME); + unregister_chrdev(ssd_cmajor, SSD_CDEV_NAME); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)) + class_simple_destroy(ssd_class); +#else + class_destroy(ssd_class); +#endif + + ssd_cleanup_tasklet(); + ssd_cleanup_sysfs(); + ssd_cleanup_proc(); + ssd_cleanup_index(); +} + +int ssd_register_event_notifier(struct block_device *bdev, ssd_event_call event_call) +{ + struct ssd_device *dev; + struct timeval tv; + struct ssd_log *le; + uint64_t cur; + int log_nr; + + if (!bdev || !event_call || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + dev->event_call = event_call; + + do_gettimeofday(&tv); + cur = tv.tv_sec; + + le = (struct ssd_log *)(dev->internal_log.log); + log_nr = dev->internal_log.nr_log; + + while (log_nr--) { + if (le->time <= cur && le->time >= dev->uptime) { + (void)dev->event_call(dev->gd, le->le.event, ssd_parse_log(dev, le, 0)); + } + le++; + } + + return 0; +} + +int ssd_unregister_event_notifier(struct block_device *bdev) +{ + struct ssd_device *dev; + + if (!bdev || !(bdev->bd_disk)) { + return -EINVAL; + } + + dev = bdev->bd_disk->private_data; + dev->event_call = NULL; + + return 0; +} + +EXPORT_SYMBOL(ssd_get_label); +EXPORT_SYMBOL(ssd_get_version); +EXPORT_SYMBOL(ssd_set_otprotect); +EXPORT_SYMBOL(ssd_bm_status); +EXPORT_SYMBOL(ssd_submit_pbio); +EXPORT_SYMBOL(ssd_get_pciaddr); +EXPORT_SYMBOL(ssd_get_temperature); +EXPORT_SYMBOL(ssd_register_event_notifier); +EXPORT_SYMBOL(ssd_unregister_event_notifier); +EXPORT_SYMBOL(ssd_reset); +EXPORT_SYMBOL(ssd_set_wmode); + + + +module_init(ssd_init_module); +module_exit(ssd_cleanup_module); +MODULE_VERSION(DRIVER_VERSION); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huawei SSD DEV Team"); +MODULE_DESCRIPTION("Huawei SSD driver"); --- linux-nvidia-7.0.0.orig/ubuntu/hio/hio.h +++ linux-nvidia-7.0.0/ubuntu/hio/hio.h @@ -0,0 +1,104 @@ +/* +* Huawei SSD device driver +* Copyright (c) 2016, Huawei Technologies Co., Ltd. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _HIO_H +#define _HIO_H + +#include +#include +#include +#include + + + +typedef int (*ssd_event_call)(struct gendisk *, int, int); /* gendisk, event id, event level */ +extern int ssd_register_event_notifier(struct block_device *bdev, ssd_event_call event_call); +/* unregister event notifier before module exit */ +extern int ssd_unregister_event_notifier(struct block_device *bdev); + + +/* label */ +#define SSD_LABEL_FIELD_SZ 32 +#define SSD_SN_SZ 16 + +typedef struct ssd_label +{ + char date[SSD_LABEL_FIELD_SZ]; + char sn[SSD_LABEL_FIELD_SZ]; + char part[SSD_LABEL_FIELD_SZ]; + char desc[SSD_LABEL_FIELD_SZ]; + char other[SSD_LABEL_FIELD_SZ]; + char maf[SSD_LABEL_FIELD_SZ]; +} ssd_label_t; + + +/* version */ +typedef struct ssd_version_info +{ + uint32_t bridge_ver; /* bridge fw version: hex */ + uint32_t ctrl_ver; /* controller fw version: hex */ + uint32_t bm_ver; /* battery manager fw version: hex */ + uint8_t pcb_ver; /* main pcb version: char */ + uint8_t upper_pcb_ver; + uint8_t pad0; + uint8_t pad1; +} ssd_version_info_t; + +extern int ssd_get_label(struct block_device *bdev, struct ssd_label *label); +extern int ssd_get_version(struct block_device *bdev, struct ssd_version_info *ver); +extern int ssd_get_temperature(struct block_device *bdev, int *temp); + + +enum ssd_bmstatus +{ + SSD_BMSTATUS_OK = 0, + SSD_BMSTATUS_CHARGING, + SSD_BMSTATUS_WARNING +}; +extern int ssd_bm_status(struct block_device *bdev, int *status); + +enum ssd_otprotect +{ + SSD_OTPROTECT_OFF = 0, + SSD_OTPROTECT_ON +}; +extern int ssd_set_otprotect(struct block_device *bdev, int otprotect); + +typedef struct pci_addr +{ + uint16_t domain; + uint8_t bus; + uint8_t slot; + uint8_t func; +} pci_addr_t; +extern int ssd_get_pciaddr(struct block_device *bdev, struct pci_addr *paddr); + +/* submit phys bio: phys addr in iovec */ +extern void ssd_submit_pbio(struct request_queue *q, struct bio *bio); + +extern int ssd_reset(struct block_device *bdev); + +enum ssd_write_mode +{ + SSD_WMODE_BUFFER = 0, + SSD_WMODE_BUFFER_EX, + SSD_WMODE_FUA, + /* dummy */ + SSD_WMODE_AUTO, + SSD_WMODE_DEFAULT +}; +extern int ssd_set_wmode(struct block_device *bdev, int wmode); + +#endif + --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/Kconfig +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menuconfig IGH_ECAT + tristate "IgH EtherCAT master driver support" + depends on NET && ETHERNET + default m + help + This section contains options for IgH EtherCAT master support. + +if IGH_ECAT + +config IGH_ECAT_GENERIC_DEVICE + tristate "Enable IgH EtherCAT master generic device driver" + depends on IGH_ECAT + +config IGH_ECAT_ENABLE_EOE + bool "Enable Ethernet over EtherCAT (EoE) support" + depends on IGH_ECAT + default y + +endif # IGH_ECAT --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/Makefile +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +IGH_ECAT_REV := 1.6.8 + +subdir-ccflags-y += -DREV=$(IGH_ECAT_REV) + +obj-$(CONFIG_IGH_ECAT) += devices/ master/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/config.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/config.h @@ -0,0 +1,100 @@ +/* config.h. Generated from config.h.in by configure. */ +/* config.h.in. Generated from configure.ac by autoheader. */ + +/* Debug interfaces enabled */ +/* #undef EC_DEBUG_IF */ + +/* Debug ring enabled */ +/* #undef EC_DEBUG_RING */ + +/* EoE support enabled */ +#define EC_EOE 1 + +/* Use CPU timestamp counter */ +/* #undef EC_HAVE_CYCLES */ + +/* Use vendor id / product code wildcards */ +/* #undef EC_IDENT_WILDCARDS */ + +/* Max. number of Ethernet devices per master */ +#define EC_MAX_NUM_DEVICES 1 + +/* Read alias adresses from register */ +/* #undef EC_REGALIAS */ + +/* RTDM interface enabled */ +/* #undef EC_RTDM */ + +/* Use Xenomai3 RTDM flavour */ +/* #undef EC_RTDM_XENOMAI_V3 */ + +/* Output to syslog in RT context */ +#define EC_RT_SYSLOG 1 + +/* Assign SII to PDI */ +#define EC_SII_ASSIGN 1 + +/* Use hrtimer for scheduling */ +/* #undef EC_USE_HRTIMER */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDIO_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to the sub-directory where libtool stores uninstalled libraries. */ +#define LT_OBJDIR ".libs/" + +/* Name of package */ +#define PACKAGE "ethercat" + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "fp@igh.de" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "ethercat" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "ethercat 1.6.8" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "ethercat" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "1.6.8" + +/* Define to 1 if all of the C89 standard headers exist (not just the ones + required in a freestanding environment). This macro is provided for + backward compatibility; new code need not use it. */ +#define STDC_HEADERS 1 + +/* Version number of package */ +#define VERSION "1.6.8" --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/devices/Makefile +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/devices/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_IGH_ECAT_GENERIC_DEVICE) += ec_generic.o + +ec_generic-objs := generic.o --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/devices/ecdev.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/devices/ecdev.h @@ -0,0 +1,71 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * + * EtherCAT interface for EtherCAT device drivers. + * + * \defgroup DeviceInterface EtherCAT Device Interface + * + * Master interface for EtherCAT-capable network device drivers. Through the + * EtherCAT device interface, EtherCAT-capable network device drivers are able + * to connect their device(s) to the master, pass received frames and notify + * the master about status changes. The master on his part, can send his + * frames through connected devices. + */ + +/****************************************************************************/ + +#ifndef __ECDEV_H__ +#define __ECDEV_H__ + +#include + +/****************************************************************************/ + +struct ec_device; +typedef struct ec_device ec_device_t; /**< \see ec_device */ + +/** Device poll function type. + */ +typedef void (*ec_pollfunc_t)(struct net_device *); + +/***************************************************************************** + * Offering/withdrawal functions + ****************************************************************************/ + +ec_device_t *ecdev_offer(struct net_device *net_dev, ec_pollfunc_t poll, + struct module *module); +void ecdev_withdraw(ec_device_t *device); + +/***************************************************************************** + * Device methods + ****************************************************************************/ + +int ecdev_open(ec_device_t *device); +void ecdev_close(ec_device_t *device); +void ecdev_receive(ec_device_t *device, const void *data, size_t size); +void ecdev_set_link(ec_device_t *device, uint8_t state); +uint8_t ecdev_get_link(const ec_device_t *device); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/devices/generic.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/devices/generic.c @@ -0,0 +1,483 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT generic Ethernet device module. + */ + +/****************************************************************************/ + +#include +#include +#include +#include +#include /* ARPHRD_ETHER */ +#include + +#include "../globals.h" +#include "ecdev.h" + +#define PFX "ec_generic: " + +#define ETH_P_ETHERCAT 0x88A4 + +#define EC_GEN_RX_BUF_SIZE 1600 + +#if defined(CONFIG_SUSE_KERNEL) && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +#include +#else +# ifndef SUSE_VERSION +# define SUSE_VERSION 0 +# endif +# ifndef SUSE_PATCHLEVEL +# define SUSE_PATCHLEVEL 0 +# endif +#endif + +/****************************************************************************/ + +int __init ec_gen_init_module(void); +void __exit ec_gen_cleanup_module(void); +void ec_gen_poll(struct net_device *); + +/****************************************************************************/ + +/** \cond */ + +MODULE_AUTHOR("Florian Pose "); +MODULE_DESCRIPTION("EtherCAT master generic Ethernet device module"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(EC_MASTER_VERSION); + +/** \endcond */ + +struct list_head generic_devices; + +typedef struct { + struct list_head list; + struct net_device *netdev; + struct net_device *used_netdev; + struct socket *socket; + ec_device_t *ecdev; + uint8_t *rx_buf; +} ec_gen_device_t; + +typedef struct { + struct list_head list; + struct net_device *netdev; + char name[IFNAMSIZ]; + int ifindex; + uint8_t dev_addr[ETH_ALEN]; +} ec_gen_interface_desc_t; + +int ec_gen_device_init(ec_gen_device_t *); +void ec_gen_device_clear(ec_gen_device_t *); +int ec_gen_device_create_socket(ec_gen_device_t *, ec_gen_interface_desc_t *); +int ec_gen_device_offer(ec_gen_device_t *, ec_gen_interface_desc_t *); +int ec_gen_device_open(ec_gen_device_t *); +int ec_gen_device_stop(ec_gen_device_t *); +int ec_gen_device_start_xmit(ec_gen_device_t *, struct sk_buff *); +void ec_gen_device_poll(ec_gen_device_t *); + +int offer_device(ec_gen_interface_desc_t *); +void clear_devices(void); + +/****************************************************************************/ + +static int ec_gen_netdev_open(struct net_device *dev) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + return ec_gen_device_open(gendev); +} + +/****************************************************************************/ + +static int ec_gen_netdev_stop(struct net_device *dev) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + return ec_gen_device_stop(gendev); +} + +/****************************************************************************/ + +static int ec_gen_netdev_start_xmit( + struct sk_buff *skb, + struct net_device *dev + ) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + return ec_gen_device_start_xmit(gendev, skb); +} + +/****************************************************************************/ + +void ec_gen_poll(struct net_device *dev) +{ + ec_gen_device_t *gendev = *((ec_gen_device_t **) netdev_priv(dev)); + ec_gen_device_poll(gendev); +} + +/****************************************************************************/ + +static const struct net_device_ops ec_gen_netdev_ops = { + .ndo_open = ec_gen_netdev_open, + .ndo_stop = ec_gen_netdev_stop, + .ndo_start_xmit = ec_gen_netdev_start_xmit, +}; + +/****************************************************************************/ + +/** Init generic device. + */ +int ec_gen_device_init( + ec_gen_device_t *dev + ) +{ + ec_gen_device_t **priv; + char null = 0x00; + + dev->ecdev = NULL; + dev->socket = NULL; + dev->rx_buf = NULL; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) + dev->netdev = alloc_netdev(sizeof(ec_gen_device_t *), &null, + NET_NAME_UNKNOWN, ether_setup); +#else + dev->netdev = alloc_netdev(sizeof(ec_gen_device_t *), &null, ether_setup); +#endif + if (!dev->netdev) { + return -ENOMEM; + } + + dev->netdev->netdev_ops = &ec_gen_netdev_ops; + + priv = netdev_priv(dev->netdev); + *priv = dev; + + return 0; +} + +/****************************************************************************/ + +/** Clear generic device. + */ +void ec_gen_device_clear( + ec_gen_device_t *dev + ) +{ + if (dev->ecdev) { + ecdev_close(dev->ecdev); + ecdev_withdraw(dev->ecdev); + } + if (dev->socket) { + sock_release(dev->socket); + } + free_netdev(dev->netdev); + + if (dev->rx_buf) { + kfree(dev->rx_buf); + } +} + +/****************************************************************************/ + +/** Creates a network socket. + */ +int ec_gen_device_create_socket( + ec_gen_device_t *dev, + ec_gen_interface_desc_t *desc + ) +{ + int ret; + struct sockaddr_ll sa; + + dev->rx_buf = kmalloc(EC_GEN_RX_BUF_SIZE, GFP_KERNEL); + if (!dev->rx_buf) { + return -ENOMEM; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0) + ret = sock_create_kern(&init_net, PF_PACKET, SOCK_RAW, + htons(ETH_P_ETHERCAT), &dev->socket); +#else + ret = sock_create_kern(PF_PACKET, SOCK_RAW, htons(ETH_P_ETHERCAT), + &dev->socket); +#endif + if (ret) { + printk(KERN_ERR PFX "Failed to create socket (ret = %i).\n", ret); + return ret; + } + + printk(KERN_ERR PFX "Binding socket to interface %i (%s).\n", + desc->ifindex, desc->name); + + memset(&sa, 0x00, sizeof(sa)); + sa.sll_family = AF_PACKET; + sa.sll_protocol = htons(ETH_P_ETHERCAT); + sa.sll_ifindex = desc->ifindex; + ret = kernel_bind(dev->socket, (struct sockaddr_unsized *) &sa, sizeof(sa)); + if (ret) { + printk(KERN_ERR PFX "Failed to bind() socket to interface" + " (ret = %i).\n", ret); + sock_release(dev->socket); + dev->socket = NULL; + return ret; + } + + return 0; +} + +/****************************************************************************/ + +/** Offer generic device to master. + */ +int ec_gen_device_offer( + ec_gen_device_t *dev, + ec_gen_interface_desc_t *desc + ) +{ + int ret = 0; + + dev->used_netdev = desc->netdev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) || (SUSE_VERSION == 15 && SUSE_PATCHLEVEL >= 5) + eth_hw_addr_set(dev->netdev, desc->dev_addr); +#else + memcpy(dev->netdev->dev_addr, desc->dev_addr, ETH_ALEN); +#endif + + dev->ecdev = ecdev_offer(dev->netdev, ec_gen_poll, THIS_MODULE); + if (dev->ecdev) { + if (ec_gen_device_create_socket(dev, desc)) { + ecdev_withdraw(dev->ecdev); + dev->ecdev = NULL; + } else if (ecdev_open(dev->ecdev)) { + ecdev_withdraw(dev->ecdev); + dev->ecdev = NULL; + } else { + ecdev_set_link(dev->ecdev, netif_carrier_ok(dev->used_netdev)); // FIXME + ret = 1; + } + } + + return ret; +} + +/****************************************************************************/ + +/** Open the device. + */ +int ec_gen_device_open( + ec_gen_device_t *dev + ) +{ + return 0; +} + +/****************************************************************************/ + +/** Stop the device. + */ +int ec_gen_device_stop( + ec_gen_device_t *dev + ) +{ + return 0; +} + +/****************************************************************************/ + +int ec_gen_device_start_xmit( + ec_gen_device_t *dev, + struct sk_buff *skb + ) +{ + struct msghdr msg; + struct kvec iov; + size_t len = skb->len; + int ret; + + ecdev_set_link(dev->ecdev, netif_carrier_ok(dev->used_netdev)); + + iov.iov_base = skb->data; + iov.iov_len = len; + memset(&msg, 0, sizeof(msg)); + + ret = kernel_sendmsg(dev->socket, &msg, &iov, 1, len); + + return ret == len ? NETDEV_TX_OK : NETDEV_TX_BUSY; +} + +/****************************************************************************/ + +/** Polls the device. + */ +void ec_gen_device_poll( + ec_gen_device_t *dev + ) +{ + struct msghdr msg; + struct kvec iov; + int ret, budget = 10; // FIXME + + ecdev_set_link(dev->ecdev, netif_carrier_ok(dev->used_netdev)); + + do { + iov.iov_base = dev->rx_buf; + iov.iov_len = EC_GEN_RX_BUF_SIZE; + memset(&msg, 0, sizeof(msg)); + + ret = kernel_recvmsg(dev->socket, &msg, &iov, 1, iov.iov_len, + MSG_DONTWAIT); + if (ret > 0) { + ecdev_receive(dev->ecdev, dev->rx_buf, ret); + } else if (ret < 0) { + break; + } + budget--; + } while (budget); +} + +/****************************************************************************/ + +/** Offer device. + */ +int offer_device( + ec_gen_interface_desc_t *desc + ) +{ + ec_gen_device_t *gendev; + int ret = 0; + + gendev = kmalloc(sizeof(ec_gen_device_t), GFP_KERNEL); + if (!gendev) { + return -ENOMEM; + } + + ret = ec_gen_device_init(gendev); + if (ret) { + kfree(gendev); + return ret; + } + + if (ec_gen_device_offer(gendev, desc)) { + list_add_tail(&gendev->list, &generic_devices); + } else { + ec_gen_device_clear(gendev); + kfree(gendev); + } + + return ret; +} + +/****************************************************************************/ + +/** Clear devices. + */ +void clear_devices(void) +{ + ec_gen_device_t *gendev, *next; + + list_for_each_entry_safe(gendev, next, &generic_devices, list) { + list_del(&gendev->list); + ec_gen_device_clear(gendev); + kfree(gendev); + } +} + +/****************************************************************************/ + +/** Module initialization. + * + * Initializes \a master_count masters. + * \return 0 on success, else < 0 + */ +int __init ec_gen_init_module(void) +{ + int ret = 0; + struct list_head descs; + struct net_device *netdev; + ec_gen_interface_desc_t *desc, *next; + + printk(KERN_INFO PFX "EtherCAT master generic Ethernet device module %s\n", + EC_MASTER_VERSION); + + INIT_LIST_HEAD(&generic_devices); + INIT_LIST_HEAD(&descs); + + rcu_read_lock(); + for_each_netdev_rcu(&init_net, netdev) { + if (netdev->type != ARPHRD_ETHER) + continue; + desc = kmalloc(sizeof(ec_gen_interface_desc_t), GFP_ATOMIC); + if (!desc) { + ret = -ENOMEM; + rcu_read_unlock(); + goto out_err; + } + strncpy(desc->name, netdev->name, IFNAMSIZ); + desc->netdev = netdev; + desc->ifindex = netdev->ifindex; + memcpy(desc->dev_addr, netdev->dev_addr, ETH_ALEN); + list_add_tail(&desc->list, &descs); + } + rcu_read_unlock(); + + list_for_each_entry_safe(desc, next, &descs, list) { + ret = offer_device(desc); + if (ret) { + goto out_err; + } + kfree(desc); + } + return ret; + +out_err: + list_for_each_entry_safe(desc, next, &descs, list) { + list_del(&desc->list); + kfree(desc); + } + clear_devices(); + return ret; +} + +/****************************************************************************/ + +/** Module cleanup. + * + * Clears all master instances. + */ +void __exit ec_gen_cleanup_module(void) +{ + clear_devices(); + printk(KERN_INFO PFX "Unloading.\n"); +} + +/****************************************************************************/ + +/** \cond */ + +module_init(ec_gen_init_module); +module_exit(ec_gen_cleanup_module); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/globals.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/globals.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright (C) 2006-2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master. + * + * The file is free software; you can redistribute it and/or modify it under + * the terms of the GNU Lesser General Public License as published by the + * Free Software Foundation; version 2.1 of the License. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + * License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this file. If not, see . + * + *****************************************************************************/ + +/** + \file + Global definitions and macros. +*/ + +/*****************************************************************************/ + +#ifndef __EC_GLOBALS_H__ +#define __EC_GLOBALS_H__ + +#include "config.h" + +/****************************************************************************** + * Overall macros + *****************************************************************************/ + +/** Helper macro for EC_STR(), literates a macro argument. + * + * \param X argument to literate. + */ +#define EC_LIT(X) #X + +/** Converts a macro argument to a string. + * + * \param X argument to stringify. + */ +#define EC_STR(X) EC_LIT(X) + +/** Master version string + */ +#define EC_MASTER_VERSION VERSION " " EC_STR(REV) + +/*****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/include/Makefile.am +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/include/Makefile.am @@ -0,0 +1,26 @@ +#----------------------------------------------------------------------------- +# +# Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH +# +# This file is part of the IgH EtherCAT Master. +# +# The IgH EtherCAT Master is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License version 2, as +# published by the Free Software Foundation. +# +# The IgH EtherCAT Master is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General +# Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with the IgH EtherCAT Master; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +#----------------------------------------------------------------------------- + +include_HEADERS = \ + ecrt.h \ + ectty.h + +#----------------------------------------------------------------------------- --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/include/ecrt.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/include/ecrt.h @@ -0,0 +1,3153 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master userspace library. + * + * The IgH EtherCAT master userspace library is free software; you can + * redistribute it and/or modify it under the terms of the GNU Lesser General + * Public License as published by the Free Software Foundation; version 2.1 + * of the License. + * + * The IgH EtherCAT master userspace library is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with the IgH EtherCAT master userspace library. If not, see + * . + * + ****************************************************************************/ + +/** \file + * + * EtherCAT master application interface. + * + * \defgroup ApplicationInterface EtherCAT Application Interface + * + * EtherCAT interface for realtime applications. This interface is designed + * for realtime modules that want to use EtherCAT. There are functions to + * request a master, to map process data, to communicate with slaves via CoE + * and to configure and activate the bus. + * + * + * Changes in version 1.6.0: + * + * - Added the ecrt_master_scan_progress() method, the + * ec_master_scan_progress_t structure and the EC_HAVE_SCAN_PROGRESS + * definition to check for its existence. + * - Added the EoE configuration methods ecrt_slave_config_eoe_mac_address(), + * ecrt_slave_config_eoe_ip_address(), ecrt_slave_config_eoe_subnet_mask(), + * ecrt_slave_config_eoe_default_gateway(), + * ecrt_slave_config_eoe_dns_address(), + * ecrt_slave_config_eoe_hostname() and the EC_HAVE_SET_IP + * definition to check for its existence. + * - Added ecrt_slave_config_state_timeout() to set the application-layer + * state change timeout and EC_HAVE_STATE_TIMEOUT to check for its + * existence. + * + * Changes since version 1.5.2: + * + * - Added the ecrt_slave_config_flag() method and the EC_HAVE_FLAGS + * definition to check for its existence. + * - Added SoE IDN requests, including the datatype ec_soe_request_t and the + * methods ecrt_slave_config_create_soe_request(), + * ecrt_soe_request_object(), ecrt_soe_request_timeout(), + * ecrt_soe_request_data(), ecrt_soe_request_data_size(), + * ecrt_soe_request_state(), ecrt_soe_request_write() and + * ecrt_soe_request_read(). Use the EC_HAVE_SOE_REQUESTS to check, if the + * functionality is available. + * + * Changes in version 1.5.2: + * + * - Added redundancy_active flag to ec_domain_state_t. + * - Added ecrt_master_link_state() method and ec_master_link_state_t to query + * the state of a redundant link. + * - Added the EC_HAVE_REDUNDANCY define, to check, if the interface contains + * redundancy features. + * - Added ecrt_sdo_request_index() to change SDO index and subindex after + * request creation. + * - Added interface for retrieving CoE emergency messages, i. e. + * ecrt_slave_config_emerg_size(), ecrt_slave_config_emerg_pop(), + * ecrt_slave_config_emerg_clear(), ecrt_slave_config_emerg_overruns() and + * the defines EC_HAVE_EMERGENCY and EC_COE_EMERGENCY_MSG_SIZE. + * - Added interface for direct EtherCAT register access: Added data type + * ec_reg_request_t and methods ecrt_slave_config_create_reg_request(), + * ecrt_reg_request_data(), ecrt_reg_request_state(), + * ecrt_reg_request_write(), ecrt_reg_request_read() and the feature flag + * EC_HAVE_REG_ACCESS. + * - Added method to select the reference clock, + * ecrt_master_select_reference_clock() and the feature flag + * EC_HAVE_SELECT_REF_CLOCK to check, if the method is available. + * - Added method to get the reference clock time, + * ecrt_master_reference_clock_time() and the feature flag + * EC_HAVE_REF_CLOCK_TIME to have the possibility to synchronize the master + * clock to the reference clock. + * - Changed the data types of the shift times in ecrt_slave_config_dc() to + * int32_t to correctly display negative shift times. + * - Added ecrt_slave_config_reg_pdo_entry_pos() and the feature flag + * EC_HAVE_REG_BY_POS for registering PDO entries with non-unique indices + * via their positions in the mapping. + * + * Changes in version 1.5: + * + * - Added the distributed clocks feature and the respective method + * ecrt_slave_config_dc() to configure a slave for cyclic operation, and + * ecrt_master_application_time(), ecrt_master_sync_reference_clock() and + * ecrt_master_sync_slave_clocks() for offset and drift compensation. The + * EC_TIMEVAL2NANO() macro can be used for epoch time conversion, while the + * ecrt_master_sync_monitor_queue() and ecrt_master_sync_monitor_process() + * methods can be used to monitor the synchrony. + * - Improved the callback mechanism. ecrt_master_callbacks() now takes two + * callback functions for sending and receiving datagrams. + * ecrt_master_send_ext() is used to execute the sending of non-application + * datagrams. + * - Added watchdog configuration (method ecrt_slave_config_watchdog(), + * #ec_watchdog_mode_t, \a watchdog_mode parameter in ec_sync_info_t and + * ecrt_slave_config_sync_manager()). + * - Added ecrt_slave_config_complete_sdo() method to download an SDO during + * configuration via CompleteAccess. + * - Added ecrt_master_deactivate() to remove the master configuration. + * - Added ecrt_open_master() and ecrt_master_reserve() separation for + * userspace. + * - Added master information interface (methods ecrt_master(), + * ecrt_master_get_slave(), ecrt_master_get_sync_manager(), + * ecrt_master_get_pdo() and ecrt_master_get_pdo_entry()) to get information + * about the currently connected slaves and the PDO entries provided. + * - Added ecrt_master_sdo_download(), ecrt_master_sdo_download_complete() and + * ecrt_master_sdo_upload() methods to let an application transfer SDOs + * before activating the master. + * - Changed the meaning of the negative return values of + * ecrt_slave_config_reg_pdo_entry() and ecrt_slave_config_sdo*(). + * - Implemented the Vendor-specific over EtherCAT mailbox protocol. See + * ecrt_slave_config_create_voe_handler(). + * - Renamed ec_sdo_request_state_t to #ec_request_state_t, because it is also + * used by VoE handlers. + * - Removed 'const' from argument of ecrt_sdo_request_state(), because the + * userspace library has to modify object internals. + * - Added 64-bit data access macros. + * - Added ecrt_slave_config_idn() method for storing SoE IDN configurations, + * and ecrt_master_read_idn() and ecrt_master_write_idn() to read/write IDNs + * ad-hoc via the user-space library. + * - Added ecrt_master_reset() to initiate retrying to configure slaves. + * + * @{ + */ + +/****************************************************************************/ + +#ifndef __ECRT_H__ +#define __ECRT_H__ + +#ifdef __KERNEL__ +#include +#include +#include +#include // struct in_addr +#else +#include // for size_t +#include +#include // for struct timeval +#include // struct in_addr +#endif + +/***************************************************************************** + * Global definitions + ****************************************************************************/ + +/** EtherCAT realtime interface major version number. + */ +#define ECRT_VER_MAJOR 1 + +/** EtherCAT realtime interface minor version number. + */ +#define ECRT_VER_MINOR 6 + +/** EtherCAT realtime interface version word generator. + */ +#define ECRT_VERSION(a, b) (((a) << 8) + (b)) + +/** EtherCAT realtime interface version word. + */ +#define ECRT_VERSION_MAGIC ECRT_VERSION(ECRT_VER_MAJOR, ECRT_VER_MINOR) + +/***************************************************************************** + * Feature flags + ****************************************************************************/ + +/** Defined, if the redundancy features are available. + * + * I. e. if the \a redundancy_active flag in ec_domain_state_t and the + * ecrt_master_link_state() method are available. + */ +#define EC_HAVE_REDUNDANCY + +/** Defined, if the CoE emergency ring feature is available. + * + * I. e. if the ecrt_slave_config_emerg_*() methods are available. + */ +#define EC_HAVE_EMERGENCY + +/** Defined, if the register access interface is available. + * + * I. e. if the methods ecrt_slave_config_create_reg_request(), + * ecrt_reg_request_data(), ecrt_reg_request_state(), ecrt_reg_request_write() + * and ecrt_reg_request_read() are available. + */ +#define EC_HAVE_REG_ACCESS + +/** Defined if the method ecrt_master_select_reference_clock() is available. + */ +#define EC_HAVE_SELECT_REF_CLOCK + +/** Defined if the method ecrt_master_reference_clock_time() is available. + */ +#define EC_HAVE_REF_CLOCK_TIME + +/** Defined if the method ecrt_slave_config_reg_pdo_entry_pos() is available. + */ +#define EC_HAVE_REG_BY_POS + +/** Defined if the method ecrt_master_sync_reference_clock_to() is available. + */ +#define EC_HAVE_SYNC_TO + +/** Defined if the method ecrt_slave_config_flag() is available. + */ +#define EC_HAVE_FLAGS + +/** Defined if the methods ecrt_slave_config_create_soe_request(), + * ecrt_soe_request_object(), ecrt_soe_request_timeout(), + * ecrt_soe_request_data(), ecrt_soe_request_data_size(), + * ecrt_soe_request_state(), ecrt_soe_request_write() and + * ecrt_soe_request_read() and the datatype ec_soe_request_t are available. + */ +#define EC_HAVE_SOE_REQUESTS + +/** Defined, if the method ecrt_master_scan_progress() and the + * ec_master_scan_progress_t structure are available. + */ +#define EC_HAVE_SCAN_PROGRESS + +/** Defined, if the methods ecrt_slave_config_eoe_mac_address(), + * ecrt_slave_config_eoe_ip_address(), ecrt_slave_config_eoe_subnet_mask(), + * ecrt_slave_config_eoe_default_gateway(), + * ecrt_slave_config_eoe_dns_address(), ecrt_slave_config_eoe_hostname() are + * available. + */ +#define EC_HAVE_SET_IP + +/** Defined, if the method ecrt_slave_config_state_timeout() is available. + */ +#define EC_HAVE_STATE_TIMEOUT + +/****************************************************************************/ + +/** Symbol visibility control macro. + */ +#ifndef EC_PUBLIC_API +# if defined(ethercat_EXPORTS) && !defined(__KERNEL__) +# define EC_PUBLIC_API __attribute__ ((visibility ("default"))) +# else +# define EC_PUBLIC_API +# endif +#endif + +/****************************************************************************/ + +/** End of list marker. + * + * This can be used with ecrt_slave_config_pdos(). + */ +#define EC_END ~0U + +/** Maximum number of sync managers per slave. + */ +#define EC_MAX_SYNC_MANAGERS 16 + +/** Maximum string length. + * + * Used in ec_slave_info_t. + */ +#define EC_MAX_STRING_LENGTH 64 + +/** Maximum number of slave ports. */ +#define EC_MAX_PORTS 4 + +/** Timeval to nanoseconds conversion. + * + * This macro converts a Unix epoch time to EtherCAT DC time. + * + * \see void ecrt_master_application_time() + * + * \param TV struct timeval containing epoch time. + */ +#define EC_TIMEVAL2NANO(TV) \ + (((TV).tv_sec - 946684800ULL) * 1000000000ULL + (TV).tv_usec * 1000ULL) + +/** Size of a CoE emergency message in byte. + * + * \see ecrt_slave_config_emerg_pop(). + */ +#define EC_COE_EMERGENCY_MSG_SIZE 8 + +/***************************************************************************** + * Data types + ****************************************************************************/ + +struct ec_master; +typedef struct ec_master ec_master_t; /**< \see ec_master */ + +struct ec_slave_config; +typedef struct ec_slave_config ec_slave_config_t; /**< \see ec_slave_config */ + +struct ec_domain; +typedef struct ec_domain ec_domain_t; /**< \see ec_domain */ + +struct ec_sdo_request; +typedef struct ec_sdo_request ec_sdo_request_t; /**< \see ec_sdo_request. */ + +struct ec_soe_request; +typedef struct ec_soe_request ec_soe_request_t; /**< \see ec_soe_request. */ + +struct ec_voe_handler; +typedef struct ec_voe_handler ec_voe_handler_t; /**< \see ec_voe_handler. */ + +struct ec_reg_request; +typedef struct ec_reg_request ec_reg_request_t; /**< \see ec_reg_request. */ + +/****************************************************************************/ + +/** Master state. + * + * This is used for the output parameter of ecrt_master_state(). + * + * \see ecrt_master_state(). + */ +typedef struct { + unsigned int slaves_responding; /**< Sum of responding slaves on all + Ethernet devices. */ + unsigned int al_states : 4; /**< Application-layer states of all slaves. + The states are coded in the lower 4 bits. + If a bit is set, it means that at least one + slave in the network is in the corresponding + state: + - Bit 0: \a INIT + - Bit 1: \a PREOP + - Bit 2: \a SAFEOP + - Bit 3: \a OP */ + unsigned int link_up : 1; /**< \a true, if at least one Ethernet link is + up. */ +} ec_master_state_t; + +/****************************************************************************/ + +/** Redundant link state. + * + * This is used for the output parameter of ecrt_master_link_state(). + * + * \see ecrt_master_link_state(). + */ +typedef struct { + unsigned int slaves_responding; /**< Sum of responding slaves on the given + link. */ + unsigned int al_states : 4; /**< Application-layer states of the slaves on + the given link. The states are coded in the + lower 4 bits. If a bit is set, it means + that at least one slave in the network is in + the corresponding state: + - Bit 0: \a INIT + - Bit 1: \a PREOP + - Bit 2: \a SAFEOP + - Bit 3: \a OP */ + unsigned int link_up : 1; /**< \a true, if the given Ethernet link is up. + */ +} ec_master_link_state_t; + +/****************************************************************************/ + +/** Slave configuration state. + * + * This is used as an output parameter of ecrt_slave_config_state(). + * + * \see ecrt_slave_config_state(). + */ +typedef struct { + unsigned int online : 1; /**< The slave is online. */ + unsigned int operational : 1; /**< The slave was brought into \a OP state + using the specified configuration. */ + unsigned int al_state : 4; /**< The application-layer state of the slave. + - 1: \a INIT + - 2: \a PREOP + - 4: \a SAFEOP + - 8: \a OP + + Note that each state is coded in a different + bit! */ +} ec_slave_config_state_t; + +/****************************************************************************/ + +/** Master information. + * + * This is used as an output parameter of ecrt_master(). + * + * \see ecrt_master(). + */ +typedef struct { + unsigned int slave_count; /**< Number of slaves in the network. */ + unsigned int link_up : 1; /**< \a true, if the network link is up. */ + uint8_t scan_busy; /**< \a true, while the master is scanning the network. + */ + uint64_t app_time; /**< Application time. */ +} ec_master_info_t; + +/****************************************************************************/ + +/** Master scan progress information. + * + * This is used as an output parameter of ecrt_master_scan_progress(). + * + * \see ecrt_master_scan_progress(). + */ +typedef struct { + unsigned int slave_count; /**< Number of slaves detected. */ + unsigned int scan_index; /**< Index of the slave that is currently + scanned. If it is less than the \a + slave_count, the network scan is in progress. + */ +} ec_master_scan_progress_t; + +/****************************************************************************/ + +/** EtherCAT slave port descriptor. + */ +typedef enum { + EC_PORT_NOT_IMPLEMENTED, /**< Port is not implemented. */ + EC_PORT_NOT_CONFIGURED, /**< Port is not configured. */ + EC_PORT_EBUS, /**< Port is an E-Bus. */ + EC_PORT_MII /**< Port is a MII. */ +} ec_slave_port_desc_t; + +/****************************************************************************/ + +/** EtherCAT slave port information. + */ +typedef struct { + uint8_t link_up; /**< Link detected. */ + uint8_t loop_closed; /**< Loop closed. */ + uint8_t signal_detected; /**< Detected signal on RX port. */ +} ec_slave_port_link_t; + +/****************************************************************************/ + +/** Slave information. + * + * This is used as an output parameter of ecrt_master_get_slave(). + * + * \see ecrt_master_get_slave(). + */ +typedef struct { + uint16_t position; /**< Offset of the slave in the ring. */ + uint32_t vendor_id; /**< Vendor-ID stored on the slave. */ + uint32_t product_code; /**< Product-Code stored on the slave. */ + uint32_t revision_number; /**< Revision-Number stored on the slave. */ + uint32_t serial_number; /**< Serial-Number stored on the slave. */ + uint16_t alias; /**< The slaves alias if not equal to 0. */ + int16_t current_on_ebus; /**< Used current in mA. */ + struct { + ec_slave_port_desc_t desc; /**< Physical port type. */ + ec_slave_port_link_t link; /**< Port link state. */ + uint32_t receive_time; /**< Receive time on DC transmission delay + measurement. */ + uint16_t next_slave; /**< Ring position of next DC slave on that + port. */ + uint32_t delay_to_next_dc; /**< Delay [ns] to next DC slave. */ + } ports[EC_MAX_PORTS]; /**< Port information. */ + uint8_t al_state; /**< Current state of the slave. */ + uint8_t error_flag; /**< Error flag for that slave. */ + uint8_t sync_count; /**< Number of sync managers. */ + uint16_t sdo_count; /**< Number of SDOs. */ + char name[EC_MAX_STRING_LENGTH]; /**< Name of the slave. */ +} ec_slave_info_t; + +/****************************************************************************/ + +/** Domain working counter interpretation. + * + * This is used in ec_domain_state_t. + */ +typedef enum { + EC_WC_ZERO = 0, /**< No registered process data were exchanged. */ + EC_WC_INCOMPLETE, /**< Some of the registered process data were + exchanged. */ + EC_WC_COMPLETE /**< All registered process data were exchanged. */ +} ec_wc_state_t; + +/****************************************************************************/ + +/** Domain state. + * + * This is used for the output parameter of ecrt_domain_state(). + */ +typedef struct { + unsigned int working_counter; /**< Value of the last working counter. */ + ec_wc_state_t wc_state; /**< Working counter interpretation. */ + unsigned int redundancy_active; /**< Redundant link is in use. */ +} ec_domain_state_t; + +/****************************************************************************/ + +/** Direction type for PDO assignment functions. + */ +typedef enum { + EC_DIR_INVALID, /**< Invalid direction. Do not use this value. */ + EC_DIR_OUTPUT, /**< Values written by the master. */ + EC_DIR_INPUT, /**< Values read by the master. */ + EC_DIR_COUNT /**< Number of directions. For internal use only. */ +} ec_direction_t; + +/****************************************************************************/ + +/** Watchdog mode for sync manager configuration. + * + * Used to specify, if a sync manager's watchdog is to be enabled. + */ +typedef enum { + EC_WD_DEFAULT, /**< Use the default setting of the sync manager. */ + EC_WD_ENABLE, /**< Enable the watchdog. */ + EC_WD_DISABLE, /**< Disable the watchdog. */ +} ec_watchdog_mode_t; + +/****************************************************************************/ + +/** PDO entry configuration information. + * + * This is the data type of the \a entries field in ec_pdo_info_t. + * + * \see ecrt_slave_config_pdos(). + */ +typedef struct { + uint16_t index; /**< PDO entry index. */ + uint8_t subindex; /**< PDO entry subindex. */ + uint8_t bit_length; /**< Size of the PDO entry in bit. */ +} ec_pdo_entry_info_t; + +/****************************************************************************/ + +/** PDO configuration information. + * + * This is the data type of the \a pdos field in ec_sync_info_t. + * + * \see ecrt_slave_config_pdos(). + */ +typedef struct { + uint16_t index; /**< PDO index. */ + unsigned int n_entries; /**< Number of PDO entries in \a entries to map. + Zero means, that the default mapping shall be + used (this can only be done if the slave is + present at configuration time). */ + ec_pdo_entry_info_t const *entries; /**< Array of PDO entries to map. Can + either be \a NULL, or must contain + at least \a n_entries values. */ +} ec_pdo_info_t; + +/****************************************************************************/ + +/** Sync manager configuration information. + * + * This can be use to configure multiple sync managers including the PDO + * assignment and PDO mapping. It is used as an input parameter type in + * ecrt_slave_config_pdos(). + */ +typedef struct { + uint8_t index; /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS for a valid sync manager, + but can also be \a 0xff to mark the end of the list. */ + ec_direction_t dir; /**< Sync manager direction. */ + unsigned int n_pdos; /**< Number of PDOs in \a pdos. */ + ec_pdo_info_t const *pdos; /**< Array with PDOs to assign. This must + contain at least \a n_pdos PDOs. */ + ec_watchdog_mode_t watchdog_mode; /**< Watchdog mode. */ +} ec_sync_info_t; + +/****************************************************************************/ + +/** List record type for PDO entry mass-registration. + * + * This type is used for the array parameter of the + * ecrt_domain_reg_pdo_entry_list() + */ +typedef struct { + uint16_t alias; /**< Slave alias address. */ + uint16_t position; /**< Slave position. */ + uint32_t vendor_id; /**< Slave vendor ID. */ + uint32_t product_code; /**< Slave product code. */ + uint16_t index; /**< PDO entry index. */ + uint8_t subindex; /**< PDO entry subindex. */ + unsigned int *offset; /**< Pointer to a variable to store the PDO entry's + (byte-)offset in the process data. */ + unsigned int *bit_position; /**< Pointer to a variable to store a bit + position (0-7) within the \a offset. Can be + NULL, in which case an error is raised if + the PDO entry does not byte-align. */ +} ec_pdo_entry_reg_t; + +/****************************************************************************/ + +/** Request state. + * + * This is used as return type for ecrt_sdo_request_state() and + * ecrt_voe_handler_state(). + */ +typedef enum { + EC_REQUEST_UNUSED, /**< Not requested. */ + EC_REQUEST_BUSY, /**< Request is being processed. */ + EC_REQUEST_SUCCESS, /**< Request was processed successfully. */ + EC_REQUEST_ERROR, /**< Request processing failed. */ +} ec_request_state_t; + +/****************************************************************************/ + +/** Application-layer state. + */ +typedef enum { + EC_AL_STATE_INIT = 1, /**< Init. */ + EC_AL_STATE_PREOP = 2, /**< Pre-operational. */ + EC_AL_STATE_SAFEOP = 4, /**< Safe-operational. */ + EC_AL_STATE_OP = 8, /**< Operational. */ +} ec_al_state_t; + +/***************************************************************************** + * Global functions + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Returns the version magic of the realtime interface. + * + * \apiusage{master_any,rt_safe} + * + * \return Value of ECRT_VERSION_MAGIC() at EtherCAT master compile time. + */ +EC_PUBLIC_API unsigned int ecrt_version_magic(void); + +/** Requests an EtherCAT master for realtime operation. + * + * Before an application can access an EtherCAT master, it has to reserve one + * for exclusive use. + * + * In userspace, this is a convenience function for ecrt_open_master() and + * ecrt_master_reserve(). + * + * This function has to be the first function an application has to call to + * use EtherCAT. The function takes the index of the master as its argument. + * The first master has index 0, the n-th master has index n - 1. The number + * of masters has to be specified when loading the master module. + * + * \apiusage{master_idle,blocking} + * + * \return Pointer to the reserved master, otherwise \a NULL. + */ +EC_PUBLIC_API ec_master_t *ecrt_request_master( + unsigned int master_index /**< Index of the master to request. */ + ); + +#ifndef __KERNEL__ + +/** Opens an EtherCAT master for userspace access. + * + * This function has to be the first function an application has to call to + * use EtherCAT. The function takes the index of the master as its argument. + * The first master has index 0, the n-th master has index n - 1. The number + * of masters has to be specified when loading the master module. + * + * For convenience, the function ecrt_request_master() can be used. + * + * \apiusage{master_idle,blocking} + * + * \return Pointer to the opened master, otherwise \a NULL. + */ +EC_PUBLIC_API ec_master_t *ecrt_open_master( + unsigned int master_index /**< Index of the master to request. */ + ); + +#endif // #ifndef __KERNEL__ + +/** Releases a requested EtherCAT master. + * + * After use, a master it has to be released to make it available for other + * applications. + * + * This method frees all created data structures. It should not be called in + * realtime context. + * + * If the master was activated, ecrt_master_deactivate() is called internally. + * + * \apiusage{master_any,blocking} + */ +EC_PUBLIC_API void ecrt_release_master( + ec_master_t *master /**< EtherCAT master */ + ); + +/***************************************************************************** + * Master methods + ****************************************************************************/ + +#ifndef __KERNEL__ + +/** Reserves an EtherCAT master for realtime operation. + * + * Before an application can use PDO/domain registration functions or SDO + * request functions on the master, it has to reserve one for exclusive use. + * + * \apiusage{master_idle,blocking} + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_reserve( + ec_master_t *master /**< EtherCAT master */ + ); + +#endif // #ifndef __KERNEL__ + +#ifdef __KERNEL__ + +/** Sets the locking callbacks. + * + * For concurrent master access, i. e. if other instances than the application + * want to send and receive datagrams on the network, the application has to + * provide a callback mechanism. This method takes two function pointers as + * its parameters. Asynchronous master access (like EoE processing) is only + * possible if the callbacks have been set. + * + * The task of the send callback (\a send_cb) is to decide, if the network + * hardware is currently accessible and whether or not to call the + * ecrt_master_send_ext() method. + * + * The task of the receive callback (\a receive_cb) is to decide, if a call to + * ecrt_master_receive() is allowed and to execute it respectively. + * + * \apiusage{master_idle,blocking} + * + * \attention This method has to be called before ecrt_master_activate(). + */ +void ecrt_master_callbacks( + ec_master_t *master, /**< EtherCAT master */ + void (*send_cb)(void *), /**< Datagram sending callback. */ + void (*receive_cb)(void *), /**< Receive callback. */ + void *cb_data /**< Arbitrary pointer passed to the callback functions. + */ + ); + +#endif /* __KERNEL__ */ + +/** Creates a new process data domain. + * + * For process data exchange, at least one process data domain is needed. + * This method creates a new process data domain and returns a pointer to the + * new domain object. This object can be used for registering PDOs and + * exchanging them in cyclic operation. + * + * This method allocates memory and should be called in non-realtime context + * before ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return Pointer to the new domain on success, else NULL. + */ +EC_PUBLIC_API ec_domain_t *ecrt_master_create_domain( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Obtains a slave configuration. + * + * Creates a slave configuration object for the given \a alias and \a position + * tuple and returns it. If a configuration with the same \a alias and \a + * position already exists, it will be re-used. In the latter case, the given + * vendor ID and product code are compared to the stored ones. On mismatch, an + * error message is raised and the function returns \a NULL. + * + * Slaves are addressed with the \a alias and \a position parameters. + * - If \a alias is zero, \a position is interpreted as the desired slave's + * ring position. + * - If \a alias is non-zero, it matches a slave with the given alias. In this + * case, \a position is interpreted as ring offset, starting from the + * aliased slave, so a position of zero means the aliased slave itself and a + * positive value matches the n-th slave behind the aliased one. + * + * If the slave with the given address is found during the configuration, + * its vendor ID and product code are matched against the given value. On + * mismatch, the slave is not configured and an error message is raised. + * + * If different slave configurations are pointing to the same slave during + * configuration, a warning is raised and only the first configuration is + * applied. + * + * This method allocates memory and should be called in non-realtime context + * before ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval >0 Pointer to the slave configuration structure. + * \retval NULL in the error case. + */ +EC_PUBLIC_API ec_slave_config_t *ecrt_master_slave_config( + ec_master_t *master, /**< EtherCAT master */ + uint16_t alias, /**< Slave alias. */ + uint16_t position, /**< Slave position. */ + uint32_t vendor_id, /**< Expected vendor ID. */ + uint32_t product_code /**< Expected product code. */ + ); + +/** Selects the reference clock for distributed clocks. + * + * If this method is not called for a certain master, or if the slave + * configuration pointer is NULL, then the first slave with DC functionality + * will provide the reference clock. + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_select_reference_clock( + ec_master_t *master, /**< EtherCAT master. */ + ec_slave_config_t *sc /**< Slave config of the slave to use as the + * reference slave (or NULL). */ + ); + +/** Obtains master information. + * + * No memory is allocated on the heap in this function. + * + * \apiusage{master_any,rt_safe} + * + * \attention The pointer to this structure must point to a valid variable. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master( + ec_master_t *master, /**< EtherCAT master */ + ec_master_info_t *master_info /**< Structure that will output the + information */ + ); + +/** Obtains network scan progress information. + * + * No memory is allocated on the heap in this function. + * + * \apiusage{master_any,rt_safe} + * + * \attention The pointer to this structure must point to a valid variable. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_scan_progress( + ec_master_t *master, /**< EtherCAT master */ + ec_master_scan_progress_t *progress /**< Structure that will output + the progress information. */ + ); + +/** Obtains slave information. + * + * Tries to find the slave with the given ring position. The obtained + * information is stored in a structure. No memory is allocated on the heap in + * this function. + * + * \apiusage{master_any,blocking} + * + * \attention The pointer to this structure must point to a valid variable. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_get_slave( + ec_master_t *master, /**< EtherCAT master */ + uint16_t slave_position, /**< Slave position. */ + ec_slave_info_t *slave_info /**< Structure that will output the + information */ + ); + +#ifndef __KERNEL__ + +/** Returns the proposed configuration of a slave's sync manager. + * + * Fills a given ec_sync_info_t structure with the attributes of a sync + * manager. The \a pdos field of the return value is left empty. Use + * ecrt_master_get_pdo() to get the PDO information. + * + * \apiusage{master_any,blocking} + * + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_master_get_sync_manager( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + ec_sync_info_t *sync /**< Pointer to output structure. */ + ); + +/** Returns information about a currently assigned PDO. + * + * Fills a given ec_pdo_info_t structure with the attributes of a currently + * assigned PDO of the given sync manager. The \a entries field of the return + * value is left empty. Use ecrt_master_get_pdo_entry() to get the PDO + * entry information. + * + * \apiusage{master_any,blocking} + * + * \retval zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_master_get_pdo( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + uint16_t pos, /**< Zero-based PDO position. */ + ec_pdo_info_t *pdo /**< Pointer to output structure. */ + ); + +/** Returns information about a currently mapped PDO entry. + * + * Fills a given ec_pdo_entry_info_t structure with the attributes of a + * currently mapped PDO entry of the given PDO. + * + * \apiusage{master_any,blocking} + * + * \retval zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_master_get_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + uint16_t pdo_pos, /**< Zero-based PDO position. */ + uint16_t entry_pos, /**< Zero-based PDO entry position. */ + ec_pdo_entry_info_t *entry /**< Pointer to output structure. */ + ); + +#endif /* #ifndef __KERNEL__ */ + +/** Executes an SDO download request to write data to a slave. + * + * This request is processed by the master state machine. This method blocks, + * until the request has been processed and may not be called in realtime + * context. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_sdo_download( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint16_t index, /**< Index of the SDO. */ + uint8_t subindex, /**< Subindex of the SDO. */ + const uint8_t *data, /**< Data buffer to download. */ + size_t data_size, /**< Size of the data buffer. */ + uint32_t *abort_code /**< Abort code of the SDO download. */ + ); + +/** Executes an SDO download request to write data to a slave via complete + * access. + * + * This request is processed by the master state machine. This method blocks, + * until the request has been processed and may not be called in realtime + * context. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_sdo_download_complete( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint16_t index, /**< Index of the SDO. */ + const uint8_t *data, /**< Data buffer to download. */ + size_t data_size, /**< Size of the data buffer. */ + uint32_t *abort_code /**< Abort code of the SDO download. */ + ); + +/** Executes an SDO upload request to read data from a slave. + * + * This request is processed by the master state machine. This method blocks, + * until the request has been processed and may not be called in realtime + * context. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_sdo_upload( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint16_t index, /**< Index of the SDO. */ + uint8_t subindex, /**< Subindex of the SDO. */ + uint8_t *target, /**< Target buffer for the upload. */ + size_t target_size, /**< Size of the target buffer. */ + size_t *result_size, /**< Uploaded data size. */ + uint32_t *abort_code /**< Abort code of the SDO upload. */ + ); + +/** Executes an SoE write request. + * + * Starts writing an IDN and blocks until the request was processed, or an + * error occurred. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_write_idn( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< SoE IDN (see ecrt_slave_config_idn()). */ + const uint8_t *data, /**< Pointer to data to write. */ + size_t data_size, /**< Size of data to write. */ + uint16_t *error_code /**< Pointer to variable, where an SoE error code + can be stored. */ + ); + +/** Executes an SoE read request. + * + * Starts reading an IDN and blocks until the request was processed, or an + * error occurred. + * + * \apiusage{master_any,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_read_idn( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t slave_position, /**< Slave position. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< SoE IDN (see ecrt_slave_config_idn()). */ + uint8_t *target, /**< Pointer to memory where the read data can be + stored. */ + size_t target_size, /**< Size of the memory \a target points to. */ + size_t *result_size, /**< Actual size of the received data. */ + uint16_t *error_code /**< Pointer to variable, where an SoE error code + can be stored. */ + ); + +/** Finishes the configuration phase and prepares for cyclic operation. + * + * This function tells the master that the configuration phase is finished and + * the realtime operation will begin. The function allocates internal memory + * for the domains and calculates the logical FMMU addresses for domain + * members. It tells the master state machine that the configuration is + * now to be applied to the network. + * + * \apiusage{master_idle,blocking} + * + * \attention After this function has been called, the realtime application is + * in charge of cyclically calling ecrt_master_send() and + * ecrt_master_receive() to ensure network communication. Before calling this + * function, the master thread is responsible for that, so these functions may + * not be called! The method itself allocates memory and should not be called + * in realtime context. + * + * \return 0 in case of success, else < 0 + */ +EC_PUBLIC_API int ecrt_master_activate( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Deactivates the master. + * + * Removes the master configuration. All objects created by + * ecrt_master_create_domain(), ecrt_master_slave_config(), ecrt_domain_data() + * ecrt_slave_config_create_sdo_request() and + * ecrt_slave_config_create_voe_handler() are freed, so pointers to them + * become invalid. + * + * \apiusage{master_op,blocking} + * + * This method should not be called in realtime context. + * \return 0 on success, otherwise negative error code. + * \retval 0 Success. + * \retval -EINVAL Master has not been activated before. + */ +EC_PUBLIC_API int ecrt_master_deactivate( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Set interval between calls to ecrt_master_send(). + * + * This information helps the master to decide, how much data can be appended + * to a frame by the master state machine. When the master is configured with + * --enable-hrtimers, this is used to calculate the scheduling of the master + * thread. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 on success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_master_set_send_interval( + ec_master_t *master, /**< EtherCAT master. */ + size_t send_interval /**< Send interval in us */ + ); + +/** Sends all datagrams in the queue. + * + * This method takes all datagrams, that have been queued for transmission, + * puts them into frames, and passes them to the Ethernet device for sending. + * + * Has to be called cyclically by the application after ecrt_master_activate() + * has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_send( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Fetches received frames from the hardware and processes the datagrams. + * + * Queries the network device for received frames by calling the interrupt + * service routine. Extracts received datagrams and dispatches the results to + * the datagram objects in the queue. Received datagrams, and the ones that + * timed out, will be marked, and dequeued. + * + * Has to be called cyclically by the realtime application after + * ecrt_master_activate() has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_receive( + ec_master_t *master /**< EtherCAT master. */ + ); + +#ifdef __KERNEL__ +/** Sends non-application datagrams. + * + * This method has to be called in the send callback function passed via + * ecrt_master_callbacks() to allow the sending of non-application datagrams. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + * \retval -EAGAIN Lock could not be acquired, try again later. + */ +int ecrt_master_send_ext( + ec_master_t *master /**< EtherCAT master. */ + ); +#endif + +/** Reads the current master state. + * + * Stores the master state information in the given \a state structure. + * + * This method returns a global state. For the link-specific states in a + * redundant network topology, use the ecrt_master_link_state() method. + * + * \apiusage{master_any,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_state( + const ec_master_t *master, /**< EtherCAT master. */ + ec_master_state_t *state /**< Structure to store the information. */ + ); + +/** Reads the current state of a redundant link. + * + * Stores the link state information in the given \a state structure. + * + * \apiusage{master_any,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_link_state( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int dev_idx, /**< Index of the device (0 = main device, 1 = + first backup device, ...). */ + ec_master_link_state_t *state /**< Structure to store the information. + */ + ); + +/** Sets the application time. + * + * The master has to know the application's time when operating slaves with + * distributed clocks. The time is not incremented by the master itself, so + * this method has to be called cyclically. + * + * \attention The time passed to this method is used to calculate the phase of + * the slaves' SYNC0/1 interrupts. It should be called constantly at the same + * point of the realtime cycle. So it is recommended to call it at the start + * of the calculations to avoid deviancies due to changing execution times. + * Avoid calling this method before the realtime cycle is established. + * + * The time is used when setting the slaves' System Time Offset and + * Cyclic Operation Start Time registers and when synchronizing the + * DC reference clock to the application time via + * ecrt_master_sync_reference_clock(). + * + * The time is defined as nanoseconds from 2000-01-01 00:00. Converting an + * epoch time can be done with the EC_TIMEVAL2NANO() macro, but is not + * necessary, since the absolute value is not of any interest. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_application_time( + ec_master_t *master, /**< EtherCAT master. */ + uint64_t app_time /**< Application time. */ + ); + +/** Queues the DC reference clock drift compensation datagram for sending. + * + * The reference clock will by synchronized to the application time provided + * by the last call off ecrt_master_application_time(). + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + * \retval 0 Success. + * \retval -ENXIO No reference clock found. + */ +EC_PUBLIC_API int ecrt_master_sync_reference_clock( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Queues the DC reference clock drift compensation datagram for sending. + * + * The reference clock will by synchronized to the time passed in the + * sync_time parameter. + * + * Has to be called by the application after ecrt_master_activate() + * has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise negative error code. + * \retval 0 Success. + * \retval -ENXIO No reference clock found. + */ +EC_PUBLIC_API int ecrt_master_sync_reference_clock_to( + ec_master_t *master, /**< EtherCAT master. */ + uint64_t sync_time /**< Sync reference clock to this time. */ + ); + +/** Queues the DC clock drift compensation datagram for sending. + * + * All slave clocks synchronized to the reference clock. + * + * Has to be called by the application after ecrt_master_activate() + * has returned. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval 0 Success. + * \retval -ENXIO No reference clock found. + */ +EC_PUBLIC_API int ecrt_master_sync_slave_clocks( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Get the lower 32 bit of the reference clock system time. + * + * This method can be used to synchronize the master to the reference clock. + * + * The reference clock system time is queried via the + * ecrt_master_sync_slave_clocks() method, that reads the system time of the + * reference clock and writes it to the slave clocks (so be sure to call it + * cyclically to get valid data). + * + * \attention The returned time is the system time of the reference clock + * minus the transmission delay of the reference clock. + * + * Calling this method makes only sense in realtime context (after master + * activation), when the ecrt_master_sync_slave_clocks() method is called + * cyclically. + * + * \apiusage{master_op,rt_safe} + * + * \retval 0 success, system time was written into \a time. + * \retval -ENXIO No reference clock found. + * \retval -EIO Slave synchronization datagram was not received. + */ +EC_PUBLIC_API int ecrt_master_reference_clock_time( + const ec_master_t *master, /**< EtherCAT master. */ + uint32_t *time /**< Pointer to store the queried system time. */ + ); + +/** Queues the DC synchrony monitoring datagram for sending. + * + * The datagram broadcast-reads all "System time difference" registers (\a + * 0x092c) to get an upper estimation of the DC synchrony. The result can be + * checked with the ecrt_master_sync_monitor_process() method. + * + * \apiusage{master_op,rt_safe} + * + * \return Zero on success, otherwise a negative error code. + */ +EC_PUBLIC_API int ecrt_master_sync_monitor_queue( + ec_master_t *master /**< EtherCAT master. */ + ); + +/** Processes the DC synchrony monitoring datagram. + * + * If the sync monitoring datagram was sent before with + * ecrt_master_sync_monitor_queue(), the result can be queried with this + * method. + * + * \apiusage{master_op,rt_safe} + * + * \return Upper estimation of the maximum time difference in ns, -1 on error. + * \retval (uint32_t)-1 Error. + */ +EC_PUBLIC_API uint32_t ecrt_master_sync_monitor_process( + const ec_master_t *master /**< EtherCAT master. */ + ); + +/** Retry configuring slaves. + * + * Via this method, the application can tell the master to bring all slaves to + * OP state. In general, this is not necessary, because it is automatically + * done by the master. But with special slaves, that can be reconfigured by + * the vendor during runtime, it can be useful. + * + * Calling this method only makes sense in realtime context (after + * activation), because slaves will not be configured before. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_master_reset( + ec_master_t *master /**< EtherCAT master. */ + ); + +/***************************************************************************** + * Slave configuration methods + ****************************************************************************/ + +/** Configure a sync manager. + * + * Sets the direction of a sync manager. This overrides the direction bits + * from the default control register from SII. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_sync_manager( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + ec_direction_t direction, /**< Input/Output. */ + ec_watchdog_mode_t watchdog_mode /** Watchdog mode. */ + ); + +/** Configure a slave's watchdog times. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_watchdog( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t watchdog_divider, /**< Number of 40 ns intervals (register + 0x0400). Used as a base unit for all + slave watchdogs^. If set to zero, the + value is not written, so the default is + used. */ + uint16_t watchdog_intervals /**< Number of base intervals for sync + manager watchdog (register 0x0420). If + set to zero, the value is not written, + so the default is used. */ + ); + +/** Add a PDO to a sync manager's PDO assignment. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_assign_add( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index, /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + uint16_t index /**< Index of the PDO to assign. */ + ); + +/** Clear a sync manager's PDO assignment. + * + * This can be called before assigning PDOs via + * ecrt_slave_config_pdo_assign_add(), to clear the default assignment of a + * sync manager. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_assign_clear( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index /**< Sync manager index. Must be less + than #EC_MAX_SYNC_MANAGERS. */ + ); + +/** Add a PDO entry to the given PDO's mapping. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_mapping_add( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t pdo_index, /**< Index of the PDO. */ + uint16_t entry_index, /**< Index of the PDO entry to add to the PDO's + mapping. */ + uint8_t entry_subindex, /**< Subindex of the PDO entry to add to the + PDO's mapping. */ + uint8_t entry_bit_length /**< Size of the PDO entry in bit. */ + ); + +/** Clear the mapping of a given PDO. + * + * This can be called before mapping PDO entries via + * ecrt_slave_config_pdo_mapping_add(), to clear the default mapping. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \see ecrt_slave_config_pdos() + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_pdo_mapping_clear( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t pdo_index /**< Index of the PDO. */ + ); + +/** Specify a complete PDO configuration. + * + * This function is a convenience wrapper for the functions + * ecrt_slave_config_sync_manager(), ecrt_slave_config_pdo_assign_clear(), + * ecrt_slave_config_pdo_assign_add(), ecrt_slave_config_pdo_mapping_clear() + * and ecrt_slave_config_pdo_mapping_add(), that are better suitable for + * automatic code generation. + * + * The following example shows, how to specify a complete configuration, + * including the PDO mappings. With this information, the master is able to + * reserve the complete process data, even if the slave is not present at + * configuration time: + * + * \code + * ec_pdo_entry_info_t el3162_channel1[] = { + * {0x3101, 1, 8}, // status + * {0x3101, 2, 16} // value + * }; + * + * ec_pdo_entry_info_t el3162_channel2[] = { + * {0x3102, 1, 8}, // status + * {0x3102, 2, 16} // value + * }; + * + * ec_pdo_info_t el3162_pdos[] = { + * {0x1A00, 2, el3162_channel1}, + * {0x1A01, 2, el3162_channel2} + * }; + * + * ec_sync_info_t el3162_syncs[] = { + * {2, EC_DIR_OUTPUT}, + * {3, EC_DIR_INPUT, 2, el3162_pdos}, + * {0xff} + * }; + * + * if (ecrt_slave_config_pdos(sc_ana_in, EC_END, el3162_syncs)) { + * // handle error + * } + * \endcode + * + * The next example shows, how to configure the PDO assignment only. The + * entries for each assigned PDO are taken from the PDO's default mapping. + * Please note, that PDO entry registration will fail, if the PDO + * configuration is left empty and the slave is offline. + * + * \code + * ec_pdo_info_t pdos[] = { + * {0x1600}, // Channel 1 + * {0x1601} // Channel 2 + * }; + * + * ec_sync_info_t syncs[] = { + * {3, EC_DIR_INPUT, 2, pdos}, + * }; + * + * if (ecrt_slave_config_pdos(slave_config_ana_in, 1, syncs)) { + * // handle error + * } + * \endcode + * + * Processing of \a syncs will stop, if + * - the number of processed items reaches \a n_syncs, or + * - the \a index member of an ec_sync_info_t item is 0xff. In this case, + * \a n_syncs should set to a number greater than the number of list items; + * using EC_END is recommended. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return zero on success, else non-zero + */ +EC_PUBLIC_API int ecrt_slave_config_pdos( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int n_syncs, /**< Number of sync manager configurations in + \a syncs. */ + const ec_sync_info_t syncs[] /**< Array of sync manager + configurations. */ + ); + +/** Registers a PDO entry for process data exchange in a domain. + * + * Searches the assigned PDOs for the given PDO entry. An error is raised, if + * the given entry is not mapped. Otherwise, the corresponding sync manager + * and FMMU configurations are provided for slave configuration and the + * respective sync manager's assigned PDOs are appended to the given domain, + * if not already done. The offset of the requested PDO entry's data inside + * the domain's process data is returned. Optionally, the PDO entry bit + * position (0-7) can be retrieved via the \a bit_position output parameter. + * This pointer may be \a NULL, in this case an error is raised if the PDO + * entry does not byte-align. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval >=0 Success: Offset of the PDO entry's process data. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_reg_pdo_entry( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t entry_index, /**< Index of the PDO entry to register. */ + uint8_t entry_subindex, /**< Subindex of the PDO entry to register. */ + ec_domain_t *domain, /**< Domain. */ + unsigned int *bit_position /**< Optional address if bit addressing + is desired */ + ); + +/** Registers a PDO entry using its position. + * + * Similar to ecrt_slave_config_reg_pdo_entry(), but not using PDO indices but + * offsets in the PDO mapping, because PDO entry indices may not be unique + * inside a slave's PDO mapping. An error is raised, if + * one of the given positions is out of range. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval >=0 Success: Offset of the PDO entry's process data. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_reg_pdo_entry_pos( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t sync_index, /**< Sync manager index. */ + unsigned int pdo_pos, /**< Position of the PDO inside the SM. */ + unsigned int entry_pos, /**< Position of the entry inside the PDO. */ + ec_domain_t *domain, /**< Domain. */ + unsigned int *bit_position /**< Optional address if bit addressing + is desired */ + ); + +/** Configure distributed clocks. + * + * Sets the AssignActivate word and the cycle and shift times for the sync + * signals. + * + * The AssignActivate word is vendor-specific and can be taken from the XML + * device description file (Device -> Dc -> AssignActivate). Set this to zero, + * if the slave shall be operated without distributed clocks (default). + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \attention The \a sync1_shift time is ignored. + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_dc( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t assign_activate, /**< AssignActivate word. */ + uint32_t sync0_cycle, /**< SYNC0 cycle time [ns]. */ + int32_t sync0_shift, /**< SYNC0 shift time [ns]. */ + uint32_t sync1_cycle, /**< SYNC1 cycle time [ns]. */ + int32_t sync1_shift /**< SYNC1 shift time [ns]. */ + ); + +/** Add an SDO configuration. + * + * An SDO configuration is stored in the slave configuration object and is + * downloaded to the slave whenever the slave is being configured by the + * master. This usually happens once on master activation, but can be repeated + * subsequently, for example after the slave's power supply failed. + * + * \attention The SDOs for PDO assignment (\p 0x1C10 - \p 0x1C2F) and PDO + * mapping (\p 0x1600 - \p 0x17FF and \p 0x1A00 - \p 0x1BFF) should not be + * configured with this function, because they are part of the slave + * configuration done by the master. Please use ecrt_slave_config_pdos() and + * friends instead. + * + * This is the generic function for adding an SDO configuration. Please note + * that the this function does not do any endianness correction. If + * datatype-specific functions are needed (that automatically correct the + * endianness), have a look at ecrt_slave_config_sdo8(), + * ecrt_slave_config_sdo16() and ecrt_slave_config_sdo32(). + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t index, /**< Index of the SDO to configure. */ + uint8_t subindex, /**< Subindex of the SDO to configure. */ + const uint8_t *data, /**< Pointer to the data. */ + size_t size /**< Size of the \a data. */ + ); + +/** Add a configuration value for an 8-bit SDO. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo8( + ec_slave_config_t *sc, /**< Slave configuration */ + uint16_t sdo_index, /**< Index of the SDO to configure. */ + uint8_t sdo_subindex, /**< Subindex of the SDO to configure. */ + uint8_t value /**< Value to set. */ + ); + +/** Add a configuration value for a 16-bit SDO. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo16( + ec_slave_config_t *sc, /**< Slave configuration */ + uint16_t sdo_index, /**< Index of the SDO to configure. */ + uint8_t sdo_subindex, /**< Subindex of the SDO to configure. */ + uint16_t value /**< Value to set. */ + ); + +/** Add a configuration value for a 32-bit SDO. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_sdo32( + ec_slave_config_t *sc, /**< Slave configuration */ + uint16_t sdo_index, /**< Index of the SDO to configure. */ + uint8_t sdo_subindex, /**< Subindex of the SDO to configure. */ + uint32_t value /**< Value to set. */ + ); + +/** Add configuration data for a complete SDO. + * + * The SDO data are transferred via CompleteAccess. Data for the first + * subindex (0) have to be included. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_sdo(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_complete_sdo( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t index, /**< Index of the SDO to configure. */ + const uint8_t *data, /**< Pointer to the data. */ + size_t size /**< Size of the \a data. */ + ); + +/** Set the size of the CoE emergency ring buffer. + * + * The initial size is zero, so all messages will be dropped. This method can + * be called even after master activation, but it will clear the ring buffer! + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, or negative error code. + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_size( + ec_slave_config_t *sc, /**< Slave configuration. */ + size_t elements /**< Number of records of the CoE emergency ring. */ + ); + +/** Read and remove one record from the CoE emergency ring buffer. + * + * A record consists of 8 bytes: + * + * Byte 0-1: Error code (little endian) + * Byte 2: Error register + * Byte 3-7: Data + * + * Calling this method makes only sense in realtime context (after master + * activation). + * + * \return 0 on success (record popped), or negative error code (i. e. + * -ENOENT, if ring is empty). + * + * \apiusage{master_op,any_context} + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_pop( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t *target /**< Pointer to target memory (at least + EC_COE_EMERGENCY_MSG_SIZE bytes). */ + ); + +/** Clears CoE emergency ring buffer and the overrun counter. + * + * Calling this method makes only sense in realtime context (after master + * activation). + * + * \apiusage{master_op,any_context} + * + * \return 0 on success, or negative error code. + * + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_clear( + ec_slave_config_t *sc /**< Slave configuration. */ + ); + +/** Read the number of CoE emergency overruns. + * + * The overrun counter will be incremented when a CoE emergency message could + * not be stored in the ring buffer and had to be dropped. Call + * ecrt_slave_config_emerg_clear() to reset the counter. + * + * Calling this method makes only sense in realtime context (after master + * activation). + * + * \apiusage{master_op,any_context} + * + * \return Number of overruns since last clear, or negative error code. + * + */ +EC_PUBLIC_API int ecrt_slave_config_emerg_overruns( + const ec_slave_config_t *sc /**< Slave configuration. */ + ); + +/** Create an SDO request to exchange SDOs during realtime operation. + * + * The created SDO request object is freed automatically when the master is + * released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New SDO request, or NULL on error. + */ +EC_PUBLIC_API ec_sdo_request_t *ecrt_slave_config_create_sdo_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint16_t index, /**< SDO index. */ + uint8_t subindex, /**< SDO subindex. */ + size_t size /**< Data size to reserve. */ + ); + +/** Create an SoE request to exchange SoE IDNs during realtime operation. + * + * The created SoE request object is freed automatically when the master is + * released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New SoE request, or NULL on error. + */ +EC_PUBLIC_API ec_soe_request_t *ecrt_slave_config_create_soe_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< Sercos ID-Number. */ + size_t size /**< Data size to reserve. */ + ); + +/** Create an VoE handler to exchange vendor-specific data during realtime + * operation. + * + * The number of VoE handlers per slave configuration is not limited, but + * usually it is enough to create one for sending and one for receiving, if + * both can be done simultaneously. + * + * The created VoE handler object is freed automatically when the master is + * released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New VoE handler, or NULL on error. + */ +EC_PUBLIC_API ec_voe_handler_t *ecrt_slave_config_create_voe_handler( + ec_slave_config_t *sc, /**< Slave configuration. */ + size_t size /**< Data size to reserve. */ + ); + +/** Create a register request to exchange EtherCAT register contents during + * realtime operation. + * + * This interface should not be used to take over master functionality, + * instead it is intended for debugging and monitoring reasons. + * + * The created register request object is freed automatically when the master + * is released. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \return New register request, or NULL on error. + */ +EC_PUBLIC_API ec_reg_request_t *ecrt_slave_config_create_reg_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + size_t size /**< Data size to reserve. */ + ); + +/** Outputs the state of the slave configuration. + * + * Stores the state information in the given \a state structure. The state + * information is updated by the master state machine, so it may take a few + * cycles, until it changes. + * + * \attention If the state of process data exchange shall be monitored in + * realtime, ecrt_domain_state() should be used. + * + * \apiusage{master_op,rt_safe} + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_state( + const ec_slave_config_t *sc, /**< Slave configuration */ + ec_slave_config_state_t *state /**< State object to write to. */ + ); + +/** Add an SoE IDN configuration. + * + * A configuration for a Sercos-over-EtherCAT IDN is stored in the slave + * configuration object and is written to the slave whenever the slave is + * being configured by the master. This usually happens once on master + * activation, but can be repeated subsequently, for example after the slave's + * power supply failed. + * + * The \a idn parameter can be separated into several sections: + * - Bit 15: Standard data (0) or Product data (1) + * - Bit 14 - 12: Parameter set (0 - 7) + * - Bit 11 - 0: Data block number (0 - 4095) + * + * Please note that the this function does not do any endianness correction. + * Multi-byte data have to be passed in EtherCAT endianness (little-endian). + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_idn( + ec_slave_config_t *sc, /**< Slave configuration. */ + uint8_t drive_no, /**< Drive number. */ + uint16_t idn, /**< SoE IDN. */ + ec_al_state_t state, /**< AL state in which to write the IDN (PREOP or + SAFEOP). */ + const uint8_t *data, /**< Pointer to the data. */ + size_t size /**< Size of the \a data. */ + ); + +/** Adds a feature flag to a slave configuration. + * + * Feature flags are a generic way to configure slave-specific behavior. + * + * Multiple calls with the same slave configuration and key will overwrite the + * configuration. + * + * The following flags may be available: + * - AssignToPdi: Zero (default) keeps the slave information interface (SII) + * assigned to EtherCAT (except during transition to PREOP). Non-zero + * assigns the SII to the slave controller side before going to PREOP and + * leaves it there until a write command happens. + * - WaitBeforeSAFEOPms: Number of milliseconds to wait before commanding the + * transition from PREOP to SAFEOP. This can be used as a workaround for + * slaves that need a little time to initialize. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_flag( + ec_slave_config_t *sc, /**< Slave configuration. */ + const char *key, /**< Key as null-terminated ASCII string. */ + int32_t value /**< Value to store. */ + ); + +/** Sets the link/MAC address for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The MAC address is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_mac_address( + ec_slave_config_t *sc, /**< Slave configuration. */ + const unsigned char *mac_address /**< MAC address. */ + ); + +/** Sets the IP address for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The IP address is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * The IP address is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit IPv4 address in network byte order (big endian). + * + * A string-represented IPv4 address can be converted to a `struct in_addr` + * for example via the POSIX function `inet_pton()` (see man 3 inet_pton): + * + * \code{.c} + * #include + * struct in_addr addr; + * if (inet_aton("192.168.0.1", &addr) == 0) { + * fprintf(stderr, "Failed to convert IP address.\n"); + * return -1; + * } + * if (ecrt_slave_config_eoe_ip_address(sc, addr)) { + * fprintf(stderr, "Failed to set IP address.\n"); + * return -1; + * } + * \endcode + * + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_ip_address( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr ip_address /**< IPv4 address. */ + ); + +/** Sets the subnet mask for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The subnet mask is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * The subnet mask is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit mask in network byte order (big endian). + * + * See ecrt_slave_config_eoe_ip_address() on how to convert string-coded masks + * to `struct in_addr`. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_subnet_mask( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr subnet_mask /**< IPv4 subnet mask. */ + ); + +/** Sets the gateway address for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The gateway address is stored in the slave configuration object and will be + * written to the slave during the configuration process. + * + * The address is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit IPv4 address in network byte order (big endian). + * + * See ecrt_slave_config_eoe_ip_address() on how to convert string-coded IPv4 + * addresses to `struct in_addr`. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_default_gateway( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr gateway_address /**< Gateway's IPv4 address. */ + ); + +/** Sets the IPv4 address of the DNS server for Ethernet-over-EtherCAT (EoE) + * operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The DNS server address is stored in the slave configuration object and will + * be written to the slave during the configuration process. + * + * The address is passed by-value as a `struct in_addr`. This structure + * contains the 32-bit IPv4 address in network byte order (big endian). + * + * See ecrt_slave_config_eoe_ip_address() on how to convert string-coded IPv4 + * addresses to `struct in_addr`. + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_dns_address( + ec_slave_config_t *sc, /**< Slave configuration. */ + struct in_addr dns_address /**< IPv4 address of the DNS server. */ + ); + +/** Sets the host name for Ethernet-over-EtherCAT (EoE) operation. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * The host name is stored in the slave configuration object and will + * be written to the slave during the configuration process. + * + * The maximum size of the host name is 32 bytes (including the zero + * terminator). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_eoe_hostname( + ec_slave_config_t *sc, /**< Slave configuration. */ + const char *name /**< Zero-terminated host name. */ + ); + +/** Sets the application-layer state transition timeout in ms. + * + * Change the maximum allowed time for a slave to make an application-layer + * state transition for the given state transition (for example from PREOP to + * SAFEOP). The default values are defined in ETG.2000. + * + * A timeout value of zero ms will restore the default value. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + * + * \retval 0 Success. + * \retval <0 Error code. + */ +EC_PUBLIC_API int ecrt_slave_config_state_timeout( + ec_slave_config_t *sc, /**< Slave configuration. */ + ec_al_state_t from_state, /**< Initial state. */ + ec_al_state_t to_state, /**< Target state. */ + unsigned int timeout_ms /**< Timeout in [ms]. */ + ); + +/***************************************************************************** + * Domain methods + ****************************************************************************/ + +/** Registers a bunch of PDO entries for a domain. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \see ecrt_slave_config_reg_pdo_entry() + * + * \attention The registration array has to be terminated with an empty + * structure, or one with the \a index field set to zero! + * + * \apiusage{master_idle,blocking} + * + * \return 0 on success, else non-zero. + */ +EC_PUBLIC_API int ecrt_domain_reg_pdo_entry_list( + ec_domain_t *domain, /**< Domain. */ + const ec_pdo_entry_reg_t *pdo_entry_regs /**< Array of PDO + registrations. */ + ); + +/** Returns the current size of the domain's process data. + * + * The domain size is calculated after master activation. + * + * \apiusage{master_op,rt_safe} + * + * \return Size of the process data image, or a negative error code. + */ +EC_PUBLIC_API size_t ecrt_domain_size( + const ec_domain_t *domain /**< Domain. */ + ); + +#ifdef __KERNEL__ + +/** Provide external memory to store the domain's process data. + * + * Call this after all PDO entries have been registered and before activating + * the master. + * + * The size of the allocated memory must be at least ecrt_domain_size(), after + * all PDO entries have been registered. + * + * This method has to be called in non-realtime context before + * ecrt_master_activate(). + * + * \apiusage{master_idle,blocking} + */ +void ecrt_domain_external_memory( + ec_domain_t *domain, /**< Domain. */ + uint8_t *memory /**< Address of the memory to store the process + data in. */ + ); + +#endif /* __KERNEL__ */ + +/** Returns the domain's process data. + * + * - In kernel context: If external memory was provided with + * ecrt_domain_external_memory(), the returned pointer will contain the + * address of that memory. Otherwise it will point to the internally allocated + * memory. In the latter case, this method may not be called before + * ecrt_master_activate(). + * + * - In userspace context: This method has to be called after + * ecrt_master_activate() to get the mapped domain process data memory. + * + * \apiusage{master_op,rt_safe} + * + * \return Pointer to the process data memory. + */ +EC_PUBLIC_API uint8_t *ecrt_domain_data( + const ec_domain_t *domain /**< Domain. */ + ); + +/** Determines the states of the domain's datagrams. + * + * Evaluates the working counters of the received datagrams and outputs + * statistics, if necessary. This must be called after ecrt_master_receive() + * is expected to receive the domain datagrams in order to make + * ecrt_domain_state() return the result of the last process data exchange. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_domain_process( + ec_domain_t *domain /**< Domain. */ + ); + +/** (Re-)queues all domain datagrams in the master's datagram queue. + * + * Call this function to mark the domain's datagrams for exchanging at the + * next call of ecrt_master_send(). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_domain_queue( + ec_domain_t *domain /**< Domain. */ + ); + +/** Reads the state of a domain. + * + * Stores the domain state in the given \a state structure. + * + * Using this method, the process data exchange can be monitored in realtime. + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_domain_state( + const ec_domain_t *domain, /**< Domain. */ + ec_domain_state_t *state /**< Pointer to a state object to store the + information. */ + ); + +/***************************************************************************** + * SDO request methods. + ****************************************************************************/ + +/** Set the SDO index and subindex. + * + * \attention If the SDO index and/or subindex is changed while + * ecrt_sdo_request_state() returns EC_REQUEST_BUSY, this may lead to + * unexpected results. + * + * This method is meant to be called in realtime context (after master + * activation). To initialize the SDO request, the index and subindex can be + * set via ecrt_slave_config_create_sdo_request(). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_sdo_request_index( + ec_sdo_request_t *req, /**< SDO request. */ + uint16_t index, /**< SDO index. */ + uint8_t subindex /**< SDO subindex. */ + ); + +/** Set the timeout for an SDO request. + * + * If the request cannot be processed in the specified time, if will be marked + * as failed. + * + * The timeout is permanently stored in the request object and is valid until + * the next call of this method. + * + * The timeout should be defined in non-realtime context, but can also be + * changed afterwards. + * + * \apiusage{master_any,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_sdo_request_timeout( + ec_sdo_request_t *req, /**< SDO request. */ + uint32_t timeout /**< Timeout in milliseconds. Zero means no + timeout. */ + ); + +/** Access to the SDO request's data. + * + * This function returns a pointer to the request's internal SDO data memory. + * + * - After a read operation was successful, integer data can be evaluated + * using the EC_READ_*() macros as usual. Example: + * \code + * uint16_t value = EC_READ_U16(ecrt_sdo_request_data(sdo))); + * \endcode + * - If a write operation shall be triggered, the data have to be written to + * the internal memory. Use the EC_WRITE_*() macros, if you are writing + * integer data. Be sure, that the data fit into the memory. The memory size + * is a parameter of ecrt_slave_config_create_sdo_request(). + * \code + * EC_WRITE_U16(ecrt_sdo_request_data(sdo), 0xFFFF); + * \endcode + * + * \attention The return value can be invalid during a read operation, because + * the internal SDO data memory could be re-allocated if the read SDO data do + * not fit inside. + * + * This method is meant to be called in realtime context (after master + * activation), but can also be used to initialize data before. + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal SDO data memory. + * + */ +EC_PUBLIC_API uint8_t *ecrt_sdo_request_data( + const ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Returns the current SDO data size. + * + * When the SDO request is created, the data size is set to the size of the + * reserved memory. After a read operation the size is set to the size of the + * read data. The size is not modified in any other situation. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_any,rt_safe} + * + * \return SDO data size in bytes. + * + */ +EC_PUBLIC_API size_t ecrt_sdo_request_data_size( + const ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Get the current state of the SDO request. + * + * The user-space implementation fetches incoming data and stores the received + * data size in the request object, so the request is not const. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return Request state. + * + */ +EC_PUBLIC_API ec_request_state_t ecrt_sdo_request_state( +#ifdef __KERNEL__ + const +#endif + ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Schedule an SDO write operation. + * + * \attention This method may not be called while ecrt_sdo_request_state() + * returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -EINVAL Invalid input data, e.g. data size == 0. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_sdo_request() + * too small. + */ +EC_PUBLIC_API int ecrt_sdo_request_write( + ec_sdo_request_t *req /**< SDO request. */ + ); + +/** Schedule an SDO read operation. + * + * \attention This method may not be called while ecrt_sdo_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention After calling this function, the return value of + * ecrt_sdo_request_data() must be considered as invalid while + * ecrt_sdo_request_state() returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_sdo_request_read( + ec_sdo_request_t *req /**< SDO request. */ + ); + +/***************************************************************************** + * SoE request methods. + ****************************************************************************/ + +/** Set the request's drive and Sercos ID numbers. + * + * \attention If the drive number and/or IDN is changed while + * ecrt_soe_request_state() returns EC_REQUEST_BUSY, this may lead to + * unexpected results. + * + * This method is meant to be called in realtime context (after master + * activation). To initialize the SoE request, the drive_no and IDN can be + * set via ecrt_slave_config_create_soe_request(). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_soe_request_idn( + ec_soe_request_t *req, /**< IDN request. */ + uint8_t drive_no, /**< SDO index. */ + uint16_t idn /**< SoE IDN. */ + ); + +/** Set the timeout for an SoE request. + * + * If the request cannot be processed in the specified time, if will be marked + * as failed. + * + * The timeout is permanently stored in the request object and is valid until + * the next call of this method. + * + * The timeout should be defined in non-realtime context, but can also be + * changed afterwards. + * + * \apiusage{master_any,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_soe_request_timeout( + ec_soe_request_t *req, /**< SoE request. */ + uint32_t timeout /**< Timeout in milliseconds. Zero means no + timeout. */ + ); + +/** Access to the SoE request's data. + * + * This function returns a pointer to the request's internal IDN data memory. + * + * - After a read operation was successful, integer data can be evaluated + * using the EC_READ_*() macros as usual. Example: + * \code + * uint16_t value = EC_READ_U16(ecrt_soe_request_data(idn_req))); + * \endcode + * - If a write operation shall be triggered, the data have to be written to + * the internal memory. Use the EC_WRITE_*() macros, if you are writing + * integer data. Be sure, that the data fit into the memory. The memory size + * is a parameter of ecrt_slave_config_create_soe_request(). + * \code + * EC_WRITE_U16(ecrt_soe_request_data(idn_req), 0xFFFF); + * \endcode + * + * \attention The return value can be invalidated during a read operation, + * because the internal IDN data memory could be re-allocated if the read IDN + * data do not fit inside. + * + * This method is meant to be called in realtime context (after master + * activation), but can also be used to initialize data before. + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal IDN data memory. + * + */ +EC_PUBLIC_API uint8_t *ecrt_soe_request_data( + const ec_soe_request_t *req /**< SoE request. */ + ); + +/** Returns the current IDN data size. + * + * When the SoE request is created, the data size is set to the size of the + * reserved memory. After a read operation the size is set to the size of the + * read data. The size is not modified in any other situation. + * + * \apiusage{master_any,rt_safe} + * + * \return IDN data size in bytes. + */ +EC_PUBLIC_API size_t ecrt_soe_request_data_size( + const ec_soe_request_t *req /**< SoE request. */ + ); + +/** Get the current state of the SoE request. + * + * \return Request state. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * In the user-space implementation, the method fetches the size of the + * incoming data, so the request object is not const. + * + * \apiusage{master_op,rt_safe} + */ +EC_PUBLIC_API ec_request_state_t ecrt_soe_request_state( +#ifdef __KERNEL__ + const +#endif + ec_soe_request_t *req /**< SoE request. */ + ); + +/** Schedule an SoE IDN write operation. + * + * \attention This method may not be called while ecrt_soe_request_state() + * returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -EINVAL Invalid input data, e.g. data size == 0. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_soe_request() + * too small. + */ +EC_PUBLIC_API int ecrt_soe_request_write( + ec_soe_request_t *req /**< SoE request. */ + ); + +/** Schedule an SoE IDN read operation. + * + * \attention This method may not be called while ecrt_soe_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention After calling this function, the return value of + * ecrt_soe_request_data() must be considered as invalid while + * ecrt_soe_request_state() returns EC_REQUEST_BUSY. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_soe_request_read( + ec_soe_request_t *req /**< SoE request. */ + ); + +/***************************************************************************** + * VoE handler methods. + ****************************************************************************/ + +/** Sets the VoE header for future send operations. + * + * A VoE message shall contain a 4-byte vendor ID, followed by a 2-byte vendor + * type at as header. These numbers can be set with this function. The values + * are valid and will be used for future send operations until the next call + * of this method. + * + * This method is meant to be called in non-realtime context (before master + * activation) to initialize the header data, but it is also safe to + * change the header later on in realtime context. + * + * \apiusage{master_any,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_send_header( + ec_voe_handler_t *voe, /**< VoE handler. */ + uint32_t vendor_id, /**< Vendor ID. */ + uint16_t vendor_type /**< Vendor-specific type. */ + ); + +/** Reads the header data of a received VoE message. + * + * This method can be used to get the received VoE header information after a + * read operation has succeeded. + * + * The header information is stored at the memory given by the pointer + * parameters. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_received_header( + const ec_voe_handler_t *voe, /**< VoE handler. */ + uint32_t *vendor_id, /**< Vendor ID. */ + uint16_t *vendor_type /**< Vendor-specific type. */ + ); + +/** Access to the VoE handler's data. + * + * This function returns a pointer to the VoE handler's internal memory, that + * points to the actual VoE data right after the VoE header (see + * ecrt_voe_handler_send_header()). + * + * - After a read operation was successful, the memory contains the received + * data. The size of the received data can be determined via + * ecrt_voe_handler_data_size(). + * - Before a write operation is triggered, the data have to be written to the + * internal memory. Be sure, that the data fit into the memory. The reserved + * memory size is a parameter of ecrt_slave_config_create_voe_handler(). + * + * \attention The returned pointer is not necessarily persistent: After a read + * operation, the internal memory may have been reallocated. This can be + * avoided by reserving enough memory via the \a size parameter of + * ecrt_slave_config_create_voe_handler(). + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal memory. + */ +EC_PUBLIC_API uint8_t *ecrt_voe_handler_data( + const ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Returns the current data size. + * + * The data size is the size of the VoE data without the header (see + * ecrt_voe_handler_send_header()). + * + * When the VoE handler is created, the data size is set to the size of the + * reserved memory. At a write operation, the data size is set to the number + * of bytes to write. After a read operation the size is set to the size of + * the read data. The size is not modified in any other situation. + * + * \apiusage{master_any,rt_safe} + * + * \return Data size in bytes. + */ +EC_PUBLIC_API size_t ecrt_voe_handler_data_size( + const ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Start a VoE write operation. + * + * After this function has been called, the ecrt_voe_handler_execute() method + * must be called in every realtime cycle as long as it returns + * EC_REQUEST_BUSY. No other operation may be started while the handler is + * busy. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_voe_handler + * too small. + */ +EC_PUBLIC_API int ecrt_voe_handler_write( + ec_voe_handler_t *voe, /**< VoE handler. */ + size_t size /**< Number of bytes to write (without the VoE header). */ + ); + +/** Start a VoE read operation. + * + * After this function has been called, the ecrt_voe_handler_execute() method + * must be called in every realtime cycle as long as it returns + * EC_REQUEST_BUSY. No other operation may be started while the handler is + * busy. + * + * The state machine queries the slave's send mailbox for new data to be send + * to the master. If no data appear within the EC_VOE_RESPONSE_TIMEOUT + * (defined in master/voe_handler.c), the operation fails. + * + * On success, the size of the read data can be determined via + * ecrt_voe_handler_data_size(), while the VoE header of the received data + * can be retrieved with ecrt_voe_handler_received_header(). + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_read( + ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Start a VoE read operation without querying the sync manager status. + * + * After this function has been called, the ecrt_voe_handler_execute() method + * must be called in every realtime cycle as long as it returns + * EC_REQUEST_BUSY. No other operation may be started while the handler is + * busy. + * + * The state machine queries the slave by sending an empty mailbox. The slave + * fills its data to the master in this mailbox. If no data appear within the + * EC_VOE_RESPONSE_TIMEOUT (defined in master/voe_handler.c), the operation + * fails. + * + * On success, the size of the read data can be determined via + * ecrt_voe_handler_data_size(), while the VoE header of the received data + * can be retrieved with ecrt_voe_handler_received_header(). + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + */ +EC_PUBLIC_API int ecrt_voe_handler_read_nosync( + ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/** Execute the handler. + * + * This method executes the VoE handler. It has to be called in every realtime + * cycle as long as it returns EC_REQUEST_BUSY. + * + * \return Handler state. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + */ +EC_PUBLIC_API ec_request_state_t ecrt_voe_handler_execute( + ec_voe_handler_t *voe /**< VoE handler. */ + ); + +/***************************************************************************** + * Register request methods. + ****************************************************************************/ + +/** Access to the register request's data. + * + * This function returns a pointer to the request's internal memory. + * + * - After a read operation was successful, integer data can be evaluated + * using the EC_READ_*() macros as usual. Example: + * \code + * uint16_t value = EC_READ_U16(ecrt_reg_request_data(reg_request))); + * \endcode + * - If a write operation shall be triggered, the data have to be written to + * the internal memory. Use the EC_WRITE_*() macros, if you are writing + * integer data. Be sure, that the data fit into the memory. The memory size + * is a parameter of ecrt_slave_config_create_reg_request(). + * \code + * EC_WRITE_U16(ecrt_reg_request_data(reg_request), 0xFFFF); + * \endcode + * + * This method is meant to be called in realtime context (after master + * activation), but can also be used to initialize data before. + * + * \apiusage{master_any,rt_safe} + * + * \return Pointer to the internal memory. + * + */ +EC_PUBLIC_API uint8_t *ecrt_reg_request_data( + const ec_reg_request_t *req /**< Register request. */ + ); + +/** Get the current state of the register request. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return Request state. + * + */ +EC_PUBLIC_API ec_request_state_t ecrt_reg_request_state( + const ec_reg_request_t *req /**< Register request. */ + ); + +/** Schedule an register write operation. + * + * \attention This method may not be called while ecrt_reg_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention The \a size parameter is truncated to the size given at request + * creation. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_reg_request + * too small. + */ +EC_PUBLIC_API int ecrt_reg_request_write( + ec_reg_request_t *req, /**< Register request. */ + uint16_t address, /**< Register address. */ + size_t size /**< Size to write. */ + ); + +/** Schedule a register read operation. + * + * \attention This method may not be called while ecrt_reg_request_state() + * returns EC_REQUEST_BUSY. + * + * \attention The \a size parameter is truncated to the size given at request + * creation. + * + * This method is meant to be called in realtime context (after master + * activation). + * + * \apiusage{master_op,rt_safe} + * + * \return 0 on success, otherwise negative error code. + * \retval -ENOBUFS Reserved memory in ecrt_slave_config_create_reg_request + * too small. + */ +EC_PUBLIC_API int ecrt_reg_request_read( + ec_reg_request_t *req, /**< Register request. */ + uint16_t address, /**< Register address. */ + size_t size /**< Size to write. */ + ); + +/***************************************************************************** + * Bitwise read/write macros + ****************************************************************************/ + +/** Read a certain bit of an EtherCAT data byte. + * + * \param DATA EtherCAT data pointer + * \param POS bit position + */ +#define EC_READ_BIT(DATA, POS) ((*((uint8_t *) (DATA)) >> (POS)) & 0x01) + +/** Write a certain bit of an EtherCAT data byte. + * + * \param DATA EtherCAT data pointer + * \param POS bit position + * \param VAL new bit value + */ +#define EC_WRITE_BIT(DATA, POS, VAL) \ + do { \ + if (VAL) *((uint8_t *) (DATA)) |= (1 << (POS)); \ + else *((uint8_t *) (DATA)) &= ~(1 << (POS)); \ + } while (0) + +/***************************************************************************** + * Byte-swapping functions for user space + ****************************************************************************/ + +#ifndef __KERNEL__ + +#if __BYTE_ORDER == __LITTLE_ENDIAN + +#define le16_to_cpu(x) x +#define le32_to_cpu(x) x +#define le64_to_cpu(x) x + +#define cpu_to_le16(x) x +#define cpu_to_le32(x) x +#define cpu_to_le64(x) x + +#elif __BYTE_ORDER == __BIG_ENDIAN + +#define swap16(x) \ + ((uint16_t)( \ + (((uint16_t)(x) & 0x00ffU) << 8) | \ + (((uint16_t)(x) & 0xff00U) >> 8) )) +#define swap32(x) \ + ((uint32_t)( \ + (((uint32_t)(x) & 0x000000ffUL) << 24) | \ + (((uint32_t)(x) & 0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & 0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & 0xff000000UL) >> 24) )) +#define swap64(x) \ + ((uint64_t)( \ + (((uint64_t)(x) & 0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & 0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & 0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & 0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & 0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & 0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & 0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & 0xff00000000000000ULL) >> 56) )) + +#define le16_to_cpu(x) swap16(x) +#define le32_to_cpu(x) swap32(x) +#define le64_to_cpu(x) swap64(x) + +#define cpu_to_le16(x) swap16(x) +#define cpu_to_le32(x) swap32(x) +#define cpu_to_le64(x) swap64(x) + +#endif + +#define le16_to_cpup(x) le16_to_cpu(*((uint16_t *)(x))) +#define le32_to_cpup(x) le32_to_cpu(*((uint32_t *)(x))) +#define le64_to_cpup(x) le64_to_cpu(*((uint64_t *)(x))) + +#endif /* ifndef __KERNEL__ */ + +/***************************************************************************** + * Read macros + ****************************************************************************/ + +/** Read an 8-bit unsigned value from EtherCAT data. + * + * \return EtherCAT data value + */ +#define EC_READ_U8(DATA) \ + ((uint8_t) *((uint8_t *) (DATA))) + +/** Read an 8-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S8(DATA) \ + ((int8_t) *((uint8_t *) (DATA))) + +/** Read a 16-bit unsigned value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_U16(DATA) \ + ((uint16_t) le16_to_cpup((void *) (DATA))) + +/** Read a 16-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S16(DATA) \ + ((int16_t) le16_to_cpup((void *) (DATA))) + +/** Read a 32-bit unsigned value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_U32(DATA) \ + ((uint32_t) le32_to_cpup((void *) (DATA))) + +/** Read a 32-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S32(DATA) \ + ((int32_t) le32_to_cpup((void *) (DATA))) + +/** Read a 64-bit unsigned value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_U64(DATA) \ + ((uint64_t) le64_to_cpup((void *) (DATA))) + +/** Read a 64-bit signed value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_S64(DATA) \ + ((int64_t) le64_to_cpup((void *) (DATA))) + +/***************************************************************************** + * Floating-point read functions and macros (userspace only) + ****************************************************************************/ + +#ifndef __KERNEL__ + +/** Read a 32-bit floating-point value from EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \return EtherCAT data value + */ +EC_PUBLIC_API float ecrt_read_real(const void *data); + +/** Read a 32-bit floating-point value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_REAL(DATA) ecrt_read_real(DATA) + +/** Read a 64-bit floating-point value from EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \return EtherCAT data value + */ +EC_PUBLIC_API double ecrt_read_lreal(const void *data); + +/** Read a 64-bit floating-point value from EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \return EtherCAT data value + */ +#define EC_READ_LREAL(DATA) ecrt_read_lreal(DATA) + +#endif // ifndef __KERNEL__ + +/***************************************************************************** + * Write macros + ****************************************************************************/ + +/** Write an 8-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U8(DATA, VAL) \ + do { \ + *((uint8_t *)(DATA)) = ((uint8_t) (VAL)); \ + } while (0) + +/** Write an 8-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S8(DATA, VAL) EC_WRITE_U8(DATA, VAL) + +/** Write a 16-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U16(DATA, VAL) \ + do { \ + *((uint16_t *) (DATA)) = cpu_to_le16((uint16_t) (VAL)); \ + } while (0) + +/** Write a 16-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S16(DATA, VAL) EC_WRITE_U16(DATA, VAL) + +/** Write a 32-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U32(DATA, VAL) \ + do { \ + *((uint32_t *) (DATA)) = cpu_to_le32((uint32_t) (VAL)); \ + } while (0) + +/** Write a 32-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S32(DATA, VAL) EC_WRITE_U32(DATA, VAL) + +/** Write a 64-bit unsigned value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_U64(DATA, VAL) \ + do { \ + *((uint64_t *) (DATA)) = cpu_to_le64((uint64_t) (VAL)); \ + } while (0) + +/** Write a 64-bit signed value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_S64(DATA, VAL) EC_WRITE_U64(DATA, VAL) + +/***************************************************************************** + * Floating-point write functions and macros (userspace only) + ****************************************************************************/ + +#ifndef __KERNEL__ + +/** Write a 32-bit floating-point value to EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \param value new value + */ +EC_PUBLIC_API void ecrt_write_real(void *data, float value); + +/** Write a 32-bit floating-point value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_REAL(DATA, VAL) ecrt_write_real(DATA, VAL) + +/** Write a 64-bit floating-point value to EtherCAT data. + * + * \apiusage{master_any,rt_safe} + * + * \param data EtherCAT data pointer + * \param value new value + */ +EC_PUBLIC_API void ecrt_write_lreal(void *data, double value); + +/** Write a 64-bit floating-point value to EtherCAT data. + * + * \param DATA EtherCAT data pointer + * \param VAL new value + */ +#define EC_WRITE_LREAL(DATA, VAL) ecrt_write_lreal(DATA, VAL) + +#endif // ifndef __KERNEL__ + +/****************************************************************************/ + +#ifdef __cplusplus +} +#endif + +/****************************************************************************/ + +/** @} */ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/include/ectty.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/include/ectty.h @@ -0,0 +1,106 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master userspace library. + * + * The IgH EtherCAT master userspace library is free software; you can + * redistribute it and/or modify it under the terms of the GNU Lesser General + * Public License as published by the Free Software Foundation; version 2.1 + * of the License. + * + * The IgH EtherCAT master userspace library is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with the IgH EtherCAT master userspace library. If not, see + * . + * + ****************************************************************************/ + +/** \file + * + * EtherCAT virtual TTY interface. + * + * \defgroup TTYInterface EtherCAT Virtual TTY Interface + * + * @{ + */ + +/****************************************************************************/ + +#ifndef __ECTTY_H__ +#define __ECTTY_H__ + +#include + +/***************************************************************************** + * Data types + ****************************************************************************/ + +struct ec_tty; +typedef struct ec_tty ec_tty_t; /**< \see ec_tty */ + +/** Operations on the virtual TTY interface. + */ +typedef struct { + int (*cflag_changed)(void *, tcflag_t); /**< Called when the serial + * settings shall be changed. The + * \a cflag argument contains the + * new settings. */ +} ec_tty_operations_t; + +/***************************************************************************** + * Global functions + ****************************************************************************/ + +/** Create a virtual TTY interface. + * + * \param ops Set of callbacks. + * \param cb_data Arbitrary data, that is passed to any callback. + * + * \return Pointer to the interface object, otherwise an ERR_PTR value. + */ +ec_tty_t *ectty_create( + const ec_tty_operations_t *ops, + void *cb_data + ); + +/***************************************************************************** + * TTY interface methods + ****************************************************************************/ + +/** Releases a virtual TTY interface. + */ +void ectty_free( + ec_tty_t *tty /**< TTY interface. */ + ); + +/** Reads data to send from the TTY interface. + * + * If there are data to send, they are copied into the \a buffer. At maximum, + * \a size bytes are copied. The actual number of bytes copied is returned. + * + * \return Number of bytes copied. + */ +unsigned int ectty_tx_data( + ec_tty_t *tty, /**< TTY interface. */ + uint8_t *buffer, /**< Buffer for data to transmit. */ + size_t size /**< Available space in \a buffer. */ + ); + +/** Pushes received data to the TTY interface. + */ +void ectty_rx_data( + ec_tty_t *tty, /**< TTY interface. */ + const uint8_t *buffer, /**< Buffer with received data. */ + size_t size /**< Number of bytes in \a buffer. */ + ); + +/****************************************************************************/ + +/** @} */ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/Kbuild.in +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/Kbuild.in @@ -0,0 +1,112 @@ +#----------------------------------------------------------------------------- +# +# Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH +# +# This file is part of the IgH EtherCAT Master. +# +# The IgH EtherCAT Master is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License version 2, as +# published by the Free Software Foundation. +# +# The IgH EtherCAT Master is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General +# Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with the IgH EtherCAT Master; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# --- +# +# vi: syntax=make +# +#----------------------------------------------------------------------------- + +src := @abs_srcdir@ +ccflags-y := -I@abs_top_builddir@ + +obj-m := ec_master.o + +ec_master-objs := \ + cdev.o \ + coe_emerg_ring.o \ + datagram.o \ + datagram_pair.o \ + device.o \ + domain.o \ + flag.o \ + fmmu_config.o \ + foe_request.o \ + fsm_change.o \ + fsm_coe.o \ + fsm_foe.o \ + fsm_master.o \ + fsm_pdo.o \ + fsm_pdo_entry.o \ + fsm_sii.o \ + fsm_slave.o \ + fsm_slave_config.o \ + fsm_slave_scan.o \ + fsm_soe.o \ + ioctl.o \ + mailbox.o \ + master.o \ + module.o \ + pdo.o \ + pdo_entry.o \ + pdo_list.o \ + reg_request.o \ + sdo.o \ + sdo_entry.o \ + sdo_request.o \ + slave.o \ + slave_config.o \ + soe_errors.o \ + soe_request.o \ + sync.o \ + sync_config.o \ + voe_handler.o + +ifeq (@ENABLE_EOE@,1) +ec_master-objs += eoe_request.o ethernet.o fsm_eoe.o +endif + +ifeq (@ENABLE_DEBUG_IF@,1) +ec_master-objs += debug.o +endif + +ifeq (@ENABLE_RTDM@,1) + +ifeq (@ENABLE_XENOMAI_V3@, 1) +ec_master-objs += rtdm_xenomai_v3.o +else +ec_master-objs += rtdm.o +endif + +ifeq (@ENABLE_XENOMAI@, 1) +CFLAGS_rtdm.o := @XENOMAI_RTDM_CFLAGS@ +CFLAGS_rtdm-ioctl.o := @XENOMAI_RTDM_CFLAGS@ +endif + +ifeq (@ENABLE_RTAI@, 1) +CFLAGS_rtdm.o := @RTAI_KERNEL_CFLAGS@ +CFLAGS_rtdm-ioctl.o := @RTAI_KERNEL_CFLAGS@ +endif + +ec_master-objs += rtdm-ioctl.o +CFLAGS_rtdm-ioctl.o += -DEC_IOCTL_RTDM + +endif # ENABLE_RTDM + +REV := $(shell if test -s $(src)/../revision; then \ + cat $(src)/../revision; \ + else \ + git -C $(src)/.. describe 2>/dev/null || echo "unknown"; \ + fi) + +CFLAGS_module.o := -DREV=$(REV) + +KBUILD_CFLAGS += -Wmaybe-uninitialized + +#----------------------------------------------------------------------------- --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/Makefile +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/Makefile @@ -0,0 +1,47 @@ +ccflags-y := -I$(src)/../ \ + -Wmaybe-uninitialized + +obj-$(CONFIG_IGH_ECAT) += ec_master.o + +ec_master-$(CONFIG_IGH_ECAT) := \ + cdev.o \ + coe_emerg_ring.o \ + datagram.o \ + datagram_pair.o \ + device.o \ + domain.o \ + flag.o \ + fmmu_config.o \ + foe_request.o \ + fsm_change.o \ + fsm_coe.o \ + fsm_foe.o \ + fsm_master.o \ + fsm_pdo.o \ + fsm_pdo_entry.o \ + fsm_sii.o \ + fsm_slave.o \ + fsm_slave_config.o \ + fsm_slave_scan.o \ + fsm_soe.o \ + ioctl.o \ + mailbox.o \ + master.o \ + module.o \ + pdo.o \ + pdo_entry.o \ + pdo_list.o \ + reg_request.o \ + sdo.o \ + sdo_entry.o \ + sdo_request.o \ + slave.o \ + slave_config.o \ + soe_errors.o \ + soe_request.o \ + sync.o \ + sync_config.o \ + voe_handler.o + +ec_master-$(CONFIG_IGH_ECAT_ENABLE_EOE) += eoe_request.o ethernet.o fsm_eoe.o + --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/Makefile.am +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/Makefile.am @@ -0,0 +1,76 @@ +#----------------------------------------------------------------------------- +# +# Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH +# +# This file is part of the IgH EtherCAT Master. +# +# The IgH EtherCAT Master is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License version 2, as +# published by the Free Software Foundation. +# +# The IgH EtherCAT Master is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General +# Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with the IgH EtherCAT Master; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +#----------------------------------------------------------------------------- + +include $(top_srcdir)/Makefile.kbuild + +# using HEADERS to enable tags target +noinst_HEADERS = \ + cdev.c cdev.h \ + coe_emerg_ring.c coe_emerg_ring.h \ + datagram.c datagram.h \ + datagram_pair.c datagram_pair.h \ + debug.c debug.h \ + device.c device.h \ + domain.c domain.h \ + doxygen.c \ + eoe_request.c eoe_request.h \ + ethernet.c ethernet.h \ + flag.c flag.h \ + fmmu_config.c fmmu_config.h \ + foe.h \ + foe_request.c foe_request.h \ + fsm_change.c fsm_change.h \ + fsm_coe.c fsm_coe.h \ + fsm_eoe.c fsm_eoe.h \ + fsm_foe.c fsm_foe.h \ + fsm_master.c fsm_master.h \ + fsm_pdo.c fsm_pdo.h \ + fsm_pdo_entry.c fsm_pdo_entry.h \ + fsm_sii.c fsm_sii.h \ + fsm_slave.c fsm_slave.h \ + fsm_slave_config.c fsm_slave_config.h \ + fsm_slave_scan.c fsm_slave_scan.h \ + fsm_soe.c fsm_soe.h \ + globals.h \ + ioctl.c ioctl.h \ + mailbox.c mailbox.h \ + master.c master.h \ + module.c \ + pdo.c pdo.h \ + pdo_entry.c pdo_entry.h \ + pdo_list.c pdo_list.h \ + reg_request.c reg_request.h \ + rtdm-ioctl.c \ + rtdm.c rtdm.h \ + rtdm_details.h \ + rtdm_xenomai_v3.c \ + sdo.c sdo.h \ + sdo_entry.c sdo_entry.h \ + sdo_request.c sdo_request.h \ + slave.c slave.h \ + slave_config.c slave_config.h \ + soe_errors.c \ + soe_request.c soe_request.h \ + sync.c sync.h \ + sync_config.c sync_config.h \ + voe_handler.c voe_handler.h + +#----------------------------------------------------------------------------- --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/api_usage_notes.md +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/api_usage_notes.md @@ -0,0 +1,51 @@ +Notes regaring API Usage {#apiusage} +======================== + +There are some restrictions on the +[Application Interface](@ref ApplicationInterface) with respect to the state of +the master instance and the calling context, which are explained in the +following. + +## Rules of Thumb + +All configuration (`ecrt_slave_config_*()`) has to be done in Linux process +context. They can be blocking, so take care when holding locks. After +ecrt_master_activate() ing the master, your application must not alter the +slave configuration. Instead, update process data using ecrt_domain_queue() +and ecrt_domain_process() or use the asynchronous interface like +ecrt_sdo_request_read(). Don't forget to ecrt_master_receive() and +ecrt_master_send(). These functions can be called from non-process context +too, like Xenomai/RTAI applications or custom kernel modules. + +## Master Phase + +The first distinction of cases is whether ecrt_master_activate() has been +called or not. Before ecrt_master_activate() (or after +ecrt_master_deactivate()), the master is in idle phase. Sending and receiving +EtherCAT frames will be done by the master itself, the application (e. g. you) +can store slave configurations for later use. After ecrt_master_activate(), +the master switches into operation mode. The application is now in charge of +steering the communication. Process data can be exchanged under real time +constraints. Altering the slave configuration is not possible anymore. + +| Tag | Description | +|---------------|---------------------------------------------------------------------------------------| +| `master_op` | Master must be in operation phase, so after `ecrt_master_activate()` has been called. | +| `master_idle` | Master must be in idle phase, so before `ecrt_master_activate()` has been called. | +| `master_any` | Master can be in idle or operation phase. | + +## Allowed Context + +The second distinction of cases is the calling context, which means how the +application is run. Most of the functions of the +[Application Interface](@ref ApplicationInterface) have to acquire locks or +allocate memory, so they are potentially sleeping. They are tagged as +`blocking`. Sleeping is not allowed in all contexts, for instance when using +Xenomai/RTAI or a kernel timer. Only a very limited set of functions can be +called from any context, marked as `rt_safe`. They do not allocate memory and +will not block. + +| Tag | Description | +|------------|-----------------------------------------------------------------------------------------------| +| `rt_safe` | Realtime context (RT userspace, atomic/softirq context in kernel, Xenomai/RTAI RT task) safe. | +| `blocking` | Linux process context only (userspace or kernel), might block. | --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/cdev.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/cdev.c @@ -0,0 +1,281 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2020 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master character device. +*/ + +/****************************************************************************/ + +#include +#include +#include + +#include "cdev.h" +#include "master.h" +#include "slave_config.h" +#include "voe_handler.h" +#include "ethernet.h" +#include "ioctl.h" + +/** Set to 1 to enable device operations debugging. + */ +#define DEBUG 0 + +/****************************************************************************/ + +static int eccdev_open(struct inode *, struct file *); +static int eccdev_release(struct inode *, struct file *); +static long eccdev_ioctl(struct file *, unsigned int, unsigned long); +static int eccdev_mmap(struct file *, struct vm_area_struct *); + +/** This is the kernel version from which the .fault member of the + * vm_operations_struct is usable. + */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0) +# define FAULT_RETURN_TYPE int +#else +# define FAULT_RETURN_TYPE vm_fault_t +#endif + +static FAULT_RETURN_TYPE eccdev_vma_fault( +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) + struct vm_area_struct *, +#endif + struct vm_fault *); + +/****************************************************************************/ + +/** File operation callbacks for the EtherCAT character device. + */ +static struct file_operations eccdev_fops = { + .owner = THIS_MODULE, + .open = eccdev_open, + .release = eccdev_release, + .unlocked_ioctl = eccdev_ioctl, + .mmap = eccdev_mmap +}; + +/** Callbacks for a virtual memory area retrieved with ecdevc_mmap(). + */ +struct vm_operations_struct eccdev_vm_ops = { + .fault = eccdev_vma_fault +}; + +/****************************************************************************/ + +/** Private data structure for file handles. + */ +typedef struct { + ec_cdev_t *cdev; /**< Character device. */ + ec_ioctl_context_t ctx; /**< Context. */ +} ec_cdev_priv_t; + +/****************************************************************************/ + +/** Constructor. + * + * \return 0 in case of success, else < 0 + */ +int ec_cdev_init( + ec_cdev_t *cdev, /**< EtherCAT master character device. */ + ec_master_t *master, /**< Parent master. */ + dev_t dev_num /**< Device number. */ + ) +{ + int ret; + + cdev->master = master; + + cdev_init(&cdev->cdev, &eccdev_fops); + cdev->cdev.owner = THIS_MODULE; + + ret = cdev_add(&cdev->cdev, + MKDEV(MAJOR(dev_num), master->index), 1); + if (ret) { + EC_MASTER_ERR(master, "Failed to add character device!\n"); + } + + return ret; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_cdev_clear(ec_cdev_t *cdev /**< EtherCAT XML device */) +{ + cdev_del(&cdev->cdev); +} + +/***************************************************************************** + * File operations + ****************************************************************************/ + +/** Called when the cdev is opened. + */ +int eccdev_open(struct inode *inode, struct file *filp) +{ + ec_cdev_t *cdev = container_of(inode->i_cdev, ec_cdev_t, cdev); + ec_cdev_priv_t *priv; + + priv = kmalloc(sizeof(ec_cdev_priv_t), GFP_KERNEL); + if (!priv) { + EC_MASTER_ERR(cdev->master, + "Failed to allocate memory for private data structure.\n"); + return -ENOMEM; + } + + priv->cdev = cdev; + priv->ctx.writable = (filp->f_mode & FMODE_WRITE) != 0; + priv->ctx.requested = 0; + priv->ctx.process_data = NULL; + priv->ctx.process_data_size = 0; + + filp->private_data = priv; + +#if DEBUG + EC_MASTER_DBG(cdev->master, 0, "File opened.\n"); +#endif + return 0; +} + +/****************************************************************************/ + +/** Called when the cdev is closed. + */ +int eccdev_release(struct inode *inode, struct file *filp) +{ + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) filp->private_data; + ec_master_t *master = priv->cdev->master; + + if (priv->ctx.requested) { + ecrt_release_master(master); + } + + if (priv->ctx.process_data) { + vfree(priv->ctx.process_data); + } + +#if DEBUG + EC_MASTER_DBG(master, 0, "File closed.\n"); +#endif + + kfree(priv); + return 0; +} + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + */ +long eccdev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) filp->private_data; + +#if DEBUG + EC_MASTER_DBG(priv->cdev->master, 0, + "ioctl(filp = 0x%p, cmd = 0x%08x (0x%02x), arg = 0x%lx)\n", + filp, cmd, _IOC_NR(cmd), arg); +#endif + + return ec_ioctl(priv->cdev->master, &priv->ctx, cmd, (void __user *) arg); +} + +/****************************************************************************/ + +#ifndef VM_DONTDUMP +/** VM_RESERVED disappeared in 3.7. + */ +#define VM_DONTDUMP VM_RESERVED +#endif + +/** Memory-map callback for the EtherCAT character device. + * + * The actual mapping will be done in the eccdev_vma_nopage() callback of the + * virtual memory area. + * + * \return Always zero (success). + */ +int eccdev_mmap( + struct file *filp, + struct vm_area_struct *vma + ) +{ + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) filp->private_data; + + EC_MASTER_DBG(priv->cdev->master, 1, "mmap()\n"); + + vma->vm_ops = &eccdev_vm_ops; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + vm_flags_set(vma, VM_DONTDUMP); +#else + vma->vm_flags |= VM_DONTDUMP; /* Pages will not be swapped out */ +#endif + vma->vm_private_data = priv; + + return 0; +} + +/****************************************************************************/ + +/** Page fault callback for a virtual memory area. + * + * Called at the first access on a virtual-memory area retrieved with + * ecdev_mmap(). + * + * \return Zero on success, otherwise a negative error code. + */ +static FAULT_RETURN_TYPE eccdev_vma_fault( +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) + struct vm_area_struct *vma, /**< Virtual memory area. */ +#endif + struct vm_fault *vmf /**< Fault data. */ + ) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) + struct vm_area_struct *vma = vmf->vma; +#endif + unsigned long offset = vmf->pgoff << PAGE_SHIFT; + ec_cdev_priv_t *priv = (ec_cdev_priv_t *) vma->vm_private_data; + struct page *page; + + if (offset >= priv->ctx.process_data_size) { + return VM_FAULT_SIGBUS; + } + + page = vmalloc_to_page(priv->ctx.process_data + offset); + if (!page) { + return VM_FAULT_SIGBUS; + } + + get_page(page); + vmf->page = page; + + EC_MASTER_DBG(priv->cdev->master, 1, "Vma fault," + " offset = %lu, page = %p\n", offset, page); + + return 0; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/cdev.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/cdev.h @@ -0,0 +1,53 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master character device. +*/ + +/****************************************************************************/ + +#ifndef __EC_CDEV_H__ +#define __EC_CDEV_H__ + +#include +#include + +#include "globals.h" + +/****************************************************************************/ + +/** EtherCAT master character device. +*/ +typedef struct { + ec_master_t *master; /**< Master owning the device. */ + struct cdev cdev; /**< Character device. */ +} ec_cdev_t; + +/****************************************************************************/ + +int ec_cdev_init(ec_cdev_t *, ec_master_t *, dev_t); +void ec_cdev_clear(ec_cdev_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/coe_emerg_ring.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/coe_emerg_ring.c @@ -0,0 +1,169 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * vim: expandtab + * + ****************************************************************************/ + +/** \file + * EtherCAT CoE emergency ring buffer methods. + */ + +/****************************************************************************/ + +#include + +#include "coe_emerg_ring.h" + +/****************************************************************************/ + +/** Emergency ring buffer constructor. + */ +void ec_coe_emerg_ring_init( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + ring->sc = sc; + ring->msgs = NULL; + ring->size = 0; + ring->read_index = 0; + ring->write_index = 0; + ring->overruns = 0; +} + +/****************************************************************************/ + +/** Emergency ring buffer destructor. + */ +void ec_coe_emerg_ring_clear( + ec_coe_emerg_ring_t *ring /**< Emergency ring. */ + ) +{ + if (ring->msgs) { + kfree(ring->msgs); + } +} + +/****************************************************************************/ + +/** Set the ring size. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_coe_emerg_ring_size( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + size_t size /**< Maximum number of messages in the ring. */ + ) +{ + ring->size = 0; + + if (size < 0) { + size = 0; + } + + ring->read_index = ring->write_index = 0; + + if (ring->msgs) { + kfree(ring->msgs); + } + ring->msgs = NULL; + + if (size == 0) { + return 0; + } + + ring->msgs = kmalloc(sizeof(ec_coe_emerg_msg_t) * (size + 1), GFP_KERNEL); + if (!ring->msgs) { + return -ENOMEM; + } + + ring->size = size; + return 0; +} + +/****************************************************************************/ + +/** Add a new emergency message. + */ +void ec_coe_emerg_ring_push( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + const u8 *msg /**< Emergency message. */ + ) +{ + if (!ring->size || + (ring->write_index + 1) % (ring->size + 1) == ring->read_index) { + ring->overruns++; + return; + } + + memcpy(ring->msgs[ring->write_index].data, msg, + EC_COE_EMERGENCY_MSG_SIZE); + ring->write_index = (ring->write_index + 1) % (ring->size + 1); +} + +/****************************************************************************/ + +/** Remove an emergency message from the ring. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_coe_emerg_ring_pop( + ec_coe_emerg_ring_t *ring, /**< Emergency ring. */ + u8 *msg /**< Memory to store the emergency message. */ + ) +{ + if (ring->read_index == ring->write_index) { + return -ENOENT; + } + + memcpy(msg, ring->msgs[ring->read_index].data, EC_COE_EMERGENCY_MSG_SIZE); + ring->read_index = (ring->read_index + 1) % (ring->size + 1); + return 0; +} + +/****************************************************************************/ + +/** Clear the ring. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_coe_emerg_ring_clear_ring( + ec_coe_emerg_ring_t *ring /**< Emergency ring. */ + ) +{ + ring->read_index = ring->write_index; + ring->overruns = 0; + return 0; +} + +/****************************************************************************/ + +/** Read the number of overruns. + * + * \return Number of overruns. + */ +int ec_coe_emerg_ring_overruns( + const ec_coe_emerg_ring_t *ring /**< Emergency ring. */ + ) +{ + return ring->overruns; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/coe_emerg_ring.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/coe_emerg_ring.h @@ -0,0 +1,70 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CoE emergency ring buffer structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_COE_EMERG_RING_H__ +#define __EC_COE_EMERG_RING_H__ + +#include "globals.h" + +/****************************************************************************/ + +/** EtherCAT CoE emergency message record. + */ +typedef struct { + u8 data[EC_COE_EMERGENCY_MSG_SIZE]; /**< Message data. */ +} ec_coe_emerg_msg_t; + +/****************************************************************************/ + +/** EtherCAT CoE emergency ring buffer. + */ +typedef struct { + ec_slave_config_t *sc; /**< Slave configuration owning the ring. */ + + ec_coe_emerg_msg_t *msgs; /**< Message ring. */ + size_t size; /**< Ring size. */ + + unsigned int read_index; /**< Read index. */ + unsigned int write_index; /**< Write index. */ + unsigned int overruns; /**< Number of overruns since last reset. */ +} ec_coe_emerg_ring_t; + +/****************************************************************************/ + +void ec_coe_emerg_ring_init(ec_coe_emerg_ring_t *, ec_slave_config_t *); +void ec_coe_emerg_ring_clear(ec_coe_emerg_ring_t *); + +int ec_coe_emerg_ring_size(ec_coe_emerg_ring_t *, size_t); +void ec_coe_emerg_ring_push(ec_coe_emerg_ring_t *, const u8 *); +int ec_coe_emerg_ring_pop(ec_coe_emerg_ring_t *, u8 *); +int ec_coe_emerg_ring_clear_ring(ec_coe_emerg_ring_t *); +int ec_coe_emerg_ring_overruns(const ec_coe_emerg_ring_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/datagram.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/datagram.c @@ -0,0 +1,644 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Methods of an EtherCAT datagram. +*/ + +/****************************************************************************/ + +#include + +#include "datagram.h" +#include "master.h" + +/****************************************************************************/ + +/** \cond */ + +#define EC_FUNC_HEADER \ + ret = ec_datagram_prealloc(datagram, data_size); \ + if (unlikely(ret)) \ + return ret; \ + datagram->index = 0; \ + datagram->working_counter = 0; \ + datagram->state = EC_DATAGRAM_INIT; + +#define EC_FUNC_FOOTER \ + datagram->data_size = data_size; \ + return 0; + +/** \endcond */ + +/****************************************************************************/ + +/** Array of datagram type strings used in ec_datagram_type_string(). + * + * \attention This is indexed by ec_datagram_type_t. + */ +static const char *type_strings[] = { + "?", + "APRD", + "APWR", + "APRW", + "FPRD", + "FPWR", + "FPRW", + "BRD", + "BWR", + "BRW", + "LRD", + "LWR", + "LRW", + "ARMW", + "FRMW" +}; + +/****************************************************************************/ + +/** Constructor. + */ +void ec_datagram_init(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + INIT_LIST_HEAD(&datagram->queue); // mark as unqueued + datagram->device_index = EC_DEVICE_MAIN; + datagram->type = EC_DATAGRAM_NONE; + memset(datagram->address, 0x00, EC_ADDR_LEN); + datagram->data = NULL; + datagram->data_origin = EC_ORIG_INTERNAL; + datagram->mem_size = 0; + datagram->data_size = 0; + datagram->index = 0x00; + datagram->working_counter = 0x0000; + datagram->state = EC_DATAGRAM_INIT; +#ifdef EC_HAVE_CYCLES + datagram->cycles_sent = 0; +#endif + datagram->jiffies_sent = 0; +#ifdef EC_HAVE_CYCLES + datagram->cycles_received = 0; +#endif + datagram->jiffies_received = 0; + datagram->skip_count = 0; + datagram->stats_output_jiffies = 0; + memset(datagram->name, 0x00, EC_DATAGRAM_NAME_SIZE); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_datagram_clear(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + ec_datagram_unqueue(datagram); + + if (datagram->data_origin == EC_ORIG_INTERNAL && datagram->data) { + kfree(datagram->data); + datagram->data = NULL; + } +} + +/****************************************************************************/ + +/** Unqueue datagram. + */ +void ec_datagram_unqueue(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + if (!list_empty(&datagram->queue)) { + list_del_init(&datagram->queue); + } +} + +/****************************************************************************/ + +/** Allocates internal payload memory. + * + * If the allocated memory is already larger than requested, nothing ist done. + * + * \attention If external payload memory has been provided, no range checking + * is done! + * + * \return 0 in case of success, otherwise \a -ENOMEM. + */ +int ec_datagram_prealloc( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + size_t size /**< New payload size in bytes. */ + ) +{ + if (datagram->data_origin == EC_ORIG_EXTERNAL + || size <= datagram->mem_size) + return 0; + + if (datagram->data) { + kfree(datagram->data); + datagram->data = NULL; + datagram->mem_size = 0; + } + + if (!(datagram->data = kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of datagram memory!\n", size); + return -ENOMEM; + } + + datagram->mem_size = size; + return 0; +} + +/****************************************************************************/ + +/** Fills the datagram payload memory with zeros. + */ +void ec_datagram_zero(ec_datagram_t *datagram /**< EtherCAT datagram. */) +{ + memset(datagram->data, 0x00, datagram->data_size); +} + +/****************************************************************************/ + +/** Initializes an EtherCAT APRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_aprd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_APRD; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT APWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_apwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_APWR; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT APRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_aprw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_APRW; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT ARMW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_armw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t ring_position, /**< Auto-increment address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_ARMW; + EC_WRITE_S16(datagram->address, (int16_t) ring_position * (-1)); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FPRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_fprd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FPRD; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FPWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_fpwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FPWR; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FPRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_fprw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FPRW; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT FRMW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_frmw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t configured_address, /**< Configured station address. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + + if (unlikely(configured_address == 0x0000)) + EC_WARN("Using configured station address 0x0000!\n"); + + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_FRMW; + EC_WRITE_U16(datagram->address, configured_address); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT BRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_brd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to read. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_BRD; + EC_WRITE_U16(datagram->address, 0x0000); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT BWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_bwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_BWR; + EC_WRITE_U16(datagram->address, 0x0000); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT BRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_brw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint16_t mem_address, /**< Physical memory address. */ + size_t data_size /**< Number of bytes to write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_BRW; + EC_WRITE_U16(datagram->address, 0x0000); + EC_WRITE_U16(datagram->address + 2, mem_address); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRD datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrd( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size /**< Number of bytes to read/write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRD; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LWR datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lwr( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size /**< Number of bytes to read/write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LWR; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRW datagram. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrw( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size /**< Number of bytes to read/write. */ + ) +{ + int ret; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRW; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRD datagram with external memory. + * + * \attention It is assumed, that the external memory is at least \a data_size + * bytes large. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrd_ext( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size, /**< Number of bytes to read/write. */ + uint8_t *external_memory /**< Pointer to the memory to use. */ + ) +{ + int ret; + datagram->data = external_memory; + datagram->data_origin = EC_ORIG_EXTERNAL; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRD; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LWR datagram with external memory. + * + * \attention It is assumed, that the external memory is at least \a data_size + * bytes large. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lwr_ext( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size, /**< Number of bytes to read/write. */ + uint8_t *external_memory /**< Pointer to the memory to use. */ + ) +{ + int ret; + datagram->data = external_memory; + datagram->data_origin = EC_ORIG_EXTERNAL; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LWR; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Initializes an EtherCAT LRW datagram with external memory. + * + * \attention It is assumed, that the external memory is at least \a data_size + * bytes large. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_datagram_lrw_ext( + ec_datagram_t *datagram, /**< EtherCAT datagram. */ + uint32_t offset, /**< Logical address. */ + size_t data_size, /**< Number of bytes to read/write. */ + uint8_t *external_memory /**< Pointer to the memory to use. */ + ) +{ + int ret; + datagram->data = external_memory; + datagram->data_origin = EC_ORIG_EXTERNAL; + EC_FUNC_HEADER; + datagram->type = EC_DATAGRAM_LRW; + EC_WRITE_U32(datagram->address, offset); + EC_FUNC_FOOTER; +} + +/****************************************************************************/ + +/** Prints the state of a datagram. + * + * Outputs a text message. + */ +void ec_datagram_print_state( + const ec_datagram_t *datagram /**< EtherCAT datagram */ + ) +{ + printk(KERN_CONT "Datagram "); + switch (datagram->state) { + case EC_DATAGRAM_INIT: + printk(KERN_CONT "initialized"); + break; + case EC_DATAGRAM_QUEUED: + printk(KERN_CONT "queued"); + break; + case EC_DATAGRAM_SENT: + printk(KERN_CONT "sent"); + break; + case EC_DATAGRAM_RECEIVED: + printk(KERN_CONT "received"); + break; + case EC_DATAGRAM_TIMED_OUT: + printk(KERN_CONT "timed out"); + break; + case EC_DATAGRAM_ERROR: + printk(KERN_CONT "error"); + break; + default: + printk(KERN_CONT "???"); + } + + printk(KERN_CONT ".\n"); +} + +/****************************************************************************/ + +/** Evaluates the working counter of a single-cast datagram. + * + * Outputs an error message. + */ +void ec_datagram_print_wc_error( + const ec_datagram_t *datagram /**< EtherCAT datagram */ + ) +{ + if (datagram->working_counter == 0) { + printk(KERN_CONT "No response."); + } + else if (datagram->working_counter > 1) { + printk(KERN_CONT "%u slaves responded!", datagram->working_counter); + } + else { + printk(KERN_CONT "Success."); + } + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Outputs datagram statistics at most every second. + */ +void ec_datagram_output_stats( + ec_datagram_t *datagram + ) +{ + if (jiffies - datagram->stats_output_jiffies > HZ) { + datagram->stats_output_jiffies = jiffies; + + if (unlikely(datagram->skip_count)) { + EC_WARN("Datagram %p (%s) was SKIPPED %u time%s.\n", + datagram, datagram->name, + datagram->skip_count, + datagram->skip_count == 1 ? "" : "s"); + datagram->skip_count = 0; + } + } +} + +/****************************************************************************/ + +/** Returns a string describing the datagram type. + * + * \return Pointer on a static memory containing the requested string. + */ +const char *ec_datagram_type_string( + const ec_datagram_t *datagram /**< EtherCAT datagram. */ + ) +{ + return type_strings[datagram->type]; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/datagram.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/datagram.h @@ -0,0 +1,142 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT datagram structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DATAGRAM_H__ +#define __EC_DATAGRAM_H__ + +#include +#include +#include + +#include "globals.h" + +/****************************************************************************/ + +/** EtherCAT datagram type. + */ +typedef enum { + EC_DATAGRAM_NONE = 0x00, /**< Dummy. */ + EC_DATAGRAM_APRD = 0x01, /**< Auto Increment Physical Read. */ + EC_DATAGRAM_APWR = 0x02, /**< Auto Increment Physical Write. */ + EC_DATAGRAM_APRW = 0x03, /**< Auto Increment Physical ReadWrite. */ + EC_DATAGRAM_FPRD = 0x04, /**< Configured Address Physical Read. */ + EC_DATAGRAM_FPWR = 0x05, /**< Configured Address Physical Write. */ + EC_DATAGRAM_FPRW = 0x06, /**< Configured Address Physical ReadWrite. */ + EC_DATAGRAM_BRD = 0x07, /**< Broadcast Read. */ + EC_DATAGRAM_BWR = 0x08, /**< Broadcast Write. */ + EC_DATAGRAM_BRW = 0x09, /**< Broadcast ReadWrite. */ + EC_DATAGRAM_LRD = 0x0A, /**< Logical Read. */ + EC_DATAGRAM_LWR = 0x0B, /**< Logical Write. */ + EC_DATAGRAM_LRW = 0x0C, /**< Logical ReadWrite. */ + EC_DATAGRAM_ARMW = 0x0D, /**< Auto Increment Physical Read Multiple + Write. */ + EC_DATAGRAM_FRMW = 0x0E, /**< Configured Address Physical Read Multiple + Write. */ +} ec_datagram_type_t; + +/****************************************************************************/ + +/** EtherCAT datagram state. + */ +typedef enum { + EC_DATAGRAM_INIT, /**< Initial state of a new datagram. */ + EC_DATAGRAM_QUEUED, /**< Queued for sending. */ + EC_DATAGRAM_SENT, /**< Sent (still in the queue). */ + EC_DATAGRAM_RECEIVED, /**< Received (dequeued). */ + EC_DATAGRAM_TIMED_OUT, /**< Timed out (dequeued). */ + EC_DATAGRAM_ERROR /**< Error while sending/receiving (dequeued). */ +} ec_datagram_state_t; + +/****************************************************************************/ + +/** EtherCAT datagram. + */ +typedef struct { + struct list_head queue; /**< Master datagram queue item, + protected by user-supplied mutex. */ + struct list_head ext_queue; /**< External datagram queue item, protected by ext_queue_sem. */ + struct list_head sent; /**< Master list item for sent datagrams. */ + ec_device_index_t device_index; /**< Device via which the datagram shall + be / was sent. */ + ec_datagram_type_t type; /**< Datagram type (APRD, BWR, etc.). */ + uint8_t address[EC_ADDR_LEN]; /**< Recipient address. */ + uint8_t *data; /**< Datagram payload. */ + ec_origin_t data_origin; /**< Origin of the \a data memory. */ + size_t mem_size; /**< Datagram \a data memory size. */ + size_t data_size; /**< Size of the data in \a data. */ + uint8_t index; /**< Index (set by master). */ + uint16_t working_counter; /**< Working counter. */ + ec_datagram_state_t state; /**< State. */ +#ifdef EC_HAVE_CYCLES + cycles_t cycles_sent; /**< Time, when the datagram was sent. */ +#endif + unsigned long jiffies_sent; /**< Jiffies, when the datagram was sent. */ +#ifdef EC_HAVE_CYCLES + cycles_t cycles_received; /**< Time, when the datagram was received. */ +#endif + unsigned long jiffies_received; /**< Jiffies, when the datagram was + received. */ + unsigned int skip_count; /**< Number of requeues when not yet received. */ + unsigned long stats_output_jiffies; /**< Last statistics output. */ + char name[EC_DATAGRAM_NAME_SIZE]; /**< Description of the datagram. */ +} ec_datagram_t; + +/****************************************************************************/ + +void ec_datagram_init(ec_datagram_t *); +void ec_datagram_clear(ec_datagram_t *); +void ec_datagram_unqueue(ec_datagram_t *); +int ec_datagram_prealloc(ec_datagram_t *, size_t); +void ec_datagram_zero(ec_datagram_t *); + +int ec_datagram_aprd(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_apwr(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_aprw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_armw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_fprd(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_fpwr(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_fprw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_frmw(ec_datagram_t *, uint16_t, uint16_t, size_t); +int ec_datagram_brd(ec_datagram_t *, uint16_t, size_t); +int ec_datagram_bwr(ec_datagram_t *, uint16_t, size_t); +int ec_datagram_brw(ec_datagram_t *, uint16_t, size_t); +int ec_datagram_lrd(ec_datagram_t *, uint32_t, size_t); +int ec_datagram_lwr(ec_datagram_t *, uint32_t, size_t); +int ec_datagram_lrw(ec_datagram_t *, uint32_t, size_t); +int ec_datagram_lrd_ext(ec_datagram_t *, uint32_t, size_t, uint8_t *); +int ec_datagram_lwr_ext(ec_datagram_t *, uint32_t, size_t, uint8_t *); +int ec_datagram_lrw_ext(ec_datagram_t *, uint32_t, size_t, uint8_t *); + +void ec_datagram_print_state(const ec_datagram_t *); +void ec_datagram_print_wc_error(const ec_datagram_t *); +void ec_datagram_output_stats(ec_datagram_t *); +const char *ec_datagram_type_string(const ec_datagram_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/datagram_pair.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/datagram_pair.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT datagram pair methods. +*/ + +/****************************************************************************/ + +#include + +#include "master.h" +#include "datagram_pair.h" + +/****************************************************************************/ + +/** Datagram pair constructor. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_datagram_pair_init( + ec_datagram_pair_t *pair, /**< Datagram pair. */ + ec_domain_t *domain, /**< Parent domain. */ + uint32_t logical_offset, /**< Logical offset. */ + uint8_t *data, /**< Data pointer. */ + size_t data_size, /**< Data size. */ + const unsigned int used[] /**< input/output use count. */ + ) +{ + ec_device_index_t dev_idx; + int ret; + + INIT_LIST_HEAD(&pair->list); + pair->domain = domain; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_init(&pair->datagrams[dev_idx]); + snprintf(pair->datagrams[dev_idx].name, + EC_DATAGRAM_NAME_SIZE, "domain%u-%u-%s", domain->index, + logical_offset, ec_device_names[dev_idx != 0]); + pair->datagrams[dev_idx].device_index = dev_idx; + } + + pair->expected_working_counter = 0U; + + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + /* backup datagrams have their own memory */ + ret = ec_datagram_prealloc(&pair->datagrams[dev_idx], data_size); + if (ret) { + goto out_datagrams; + } + } + +#if EC_MAX_NUM_DEVICES > 1 + if (!(pair->send_buffer = kmalloc(data_size, GFP_KERNEL))) { + EC_MASTER_ERR(domain->master, + "Failed to allocate domain send buffer!\n"); + ret = -ENOMEM; + goto out_datagrams; + } +#endif + + /* The ec_datagram_lxx() calls below can not fail, because either the + * datagram has external memory or it is preallocated. */ + + if (used[EC_DIR_OUTPUT] && used[EC_DIR_INPUT]) { // inputs and outputs + ec_datagram_lrw_ext(&pair->datagrams[EC_DEVICE_MAIN], + logical_offset, data_size, data); + + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_lrw(&pair->datagrams[dev_idx], + logical_offset, data_size); + } + + // If LRW is used, output FMMUs increment the working counter by 2, + // while input FMMUs increment it by 1. + pair->expected_working_counter = + used[EC_DIR_OUTPUT] * 2 + used[EC_DIR_INPUT]; + } else if (used[EC_DIR_OUTPUT]) { // outputs only + ec_datagram_lwr_ext(&pair->datagrams[EC_DEVICE_MAIN], + logical_offset, data_size, data); + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_lwr(&pair->datagrams[dev_idx], + logical_offset, data_size); + } + + pair->expected_working_counter = used[EC_DIR_OUTPUT]; + } else { // inputs only (or nothing) + ec_datagram_lrd_ext(&pair->datagrams[EC_DEVICE_MAIN], + logical_offset, data_size, data); + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_lrd(&pair->datagrams[dev_idx], logical_offset, + data_size); + } + + pair->expected_working_counter = used[EC_DIR_INPUT]; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_zero(&pair->datagrams[dev_idx]); + } + + return 0; + +out_datagrams: + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + ec_datagram_clear(&pair->datagrams[dev_idx]); + } + + return ret; +} + +/****************************************************************************/ + +/** Datagram pair destructor. + */ +void ec_datagram_pair_clear( + ec_datagram_pair_t *pair /**< Datagram pair. */ + ) +{ + unsigned int dev_idx; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(pair->domain->master); + dev_idx++) { + ec_datagram_clear(&pair->datagrams[dev_idx]); + } + +#if EC_MAX_NUM_DEVICES > 1 + if (pair->send_buffer) { + kfree(pair->send_buffer); + } +#endif +} + +/****************************************************************************/ + +/** Process received data. + * + * \return Working counter sum over all devices. + */ +uint16_t ec_datagram_pair_process( + ec_datagram_pair_t *pair, /**< Datagram pair. */ + uint16_t wc_sum[] /**< Working counter sums. */ + ) +{ + unsigned int dev_idx; + uint16_t pair_wc = 0; + + for (dev_idx = 0; dev_idx < ec_master_num_devices(pair->domain->master); + dev_idx++) { + ec_datagram_t *datagram = &pair->datagrams[dev_idx]; + +#ifdef EC_RT_SYSLOG + ec_datagram_output_stats(datagram); +#endif + + if (datagram->state == EC_DATAGRAM_RECEIVED) { + pair_wc += datagram->working_counter; + wc_sum[dev_idx] += datagram->working_counter; + } + } + + return pair_wc; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/datagram_pair.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/datagram_pair.h @@ -0,0 +1,61 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT datagram pair structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DATAGRAM_PAIR_H__ +#define __EC_DATAGRAM_PAIR_H__ + +#include + +#include "globals.h" +#include "datagram.h" + +/****************************************************************************/ + +/** Domain datagram pair. + */ +typedef struct { + struct list_head list; /**< List header. */ + ec_domain_t *domain; /**< Parent domain. */ + ec_datagram_t datagrams[EC_MAX_NUM_DEVICES]; /**< Datagrams. */ +#if EC_MAX_NUM_DEVICES > 1 + uint8_t *send_buffer; +#endif + unsigned int expected_working_counter; /**< Expectord working conter. */ +} ec_datagram_pair_t; + +/****************************************************************************/ + +int ec_datagram_pair_init(ec_datagram_pair_t *, ec_domain_t *, uint32_t, + uint8_t *, size_t, const unsigned int []); +void ec_datagram_pair_clear(ec_datagram_pair_t *); + +uint16_t ec_datagram_pair_process(ec_datagram_pair_t *, uint16_t[]); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/debug.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/debug.c @@ -0,0 +1,258 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Ethernet interface for debugging purposes. +*/ + +/****************************************************************************/ + +#include +#include +#include + +#include "globals.h" +#include "master.h" +#include "debug.h" + +/****************************************************************************/ + +// net_device functions +int ec_dbgdev_open(struct net_device *); +int ec_dbgdev_stop(struct net_device *); +int ec_dbgdev_tx(struct sk_buff *, struct net_device *); +struct net_device_stats *ec_dbgdev_stats(struct net_device *); + +/** Device operations for debug interfaces. + */ +static const struct net_device_ops ec_dbg_netdev_ops = +{ + .ndo_open = ec_dbgdev_open, + .ndo_stop = ec_dbgdev_stop, + .ndo_start_xmit = ec_dbgdev_tx, + .ndo_get_stats = ec_dbgdev_stats, +}; + +/****************************************************************************/ + +/** Debug interface constructor. + * + * Initializes the debug object, creates a net_device and registeres it. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_debug_init( + ec_debug_t *dbg, /**< Debug object. */ + ec_device_t *device, /**< EtherCAT device. */ + const char *name /**< Interface name. */ + ) +{ + dbg->device = device; + dbg->registered = 0; + dbg->opened = 0; + + memset(&dbg->stats, 0, sizeof(struct net_device_stats)); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) + dbg->dev = alloc_netdev(sizeof(ec_debug_t *), name, NET_NAME_UNKNOWN, ether_setup); +#else + dbg->dev = alloc_netdev(sizeof(ec_debug_t *), name, ether_setup); +#endif + if (!(dbg->dev)) + { + EC_MASTER_ERR(device->master, "Unable to allocate net_device" + " for debug object!\n"); + return -ENODEV; + } + + // initialize net_device + dbg->dev->netdev_ops = &ec_dbg_netdev_ops; + + // initialize private data + *((ec_debug_t **) netdev_priv(dbg->dev)) = dbg; + + return 0; +} + +/****************************************************************************/ + +/** Debug interface destructor. + * + * Unregisters the net_device and frees allocated memory. + */ +void ec_debug_clear( + ec_debug_t *dbg /**< debug object */ + ) +{ + ec_debug_unregister(dbg); + free_netdev(dbg->dev); +} + +/****************************************************************************/ + +/** Register debug interface. + */ +void ec_debug_register( + ec_debug_t *dbg, /**< debug object */ + const struct net_device *net_dev /**< 'Real' Ethernet device. */ + ) +{ + int result; + + ec_debug_unregister(dbg); + + // use the Ethernet address of the physical device for the debug device +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) + eth_hw_addr_set(dbg->dev, net_dev->dev_addr); +#else + memcpy(dbg->dev->dev_addr, net_dev->dev_addr, ETH_ALEN); +#endif + + // connect the net_device to the kernel + if ((result = register_netdev(dbg->dev))) { + EC_MASTER_WARN(dbg->device->master, "Unable to register net_device:" + " error %i\n", result); + } else { + dbg->registered = 1; + } +} + +/****************************************************************************/ + +/** Unregister debug interface. + */ +void ec_debug_unregister( + ec_debug_t *dbg /**< debug object */ + ) +{ + if (dbg->registered) { + dbg->opened = 0; + dbg->registered = 0; + unregister_netdev(dbg->dev); + } +} + +/****************************************************************************/ + +/** Sends frame data to the interface. + */ +void ec_debug_send( + ec_debug_t *dbg, /**< debug object */ + const uint8_t *data, /**< frame data */ + size_t size /**< size of the frame data */ + ) +{ + struct sk_buff *skb; + + if (!dbg->opened) + return; + + // allocate socket buffer + if (!(skb = dev_alloc_skb(size))) { + dbg->stats.rx_dropped++; + return; + } + + // copy frame contents into socket buffer + memcpy(skb_put(skb, size), data, size); + + // update device statistics + dbg->stats.rx_packets++; + dbg->stats.rx_bytes += size; + + // pass socket buffer to network stack + skb->dev = dbg->dev; + skb->protocol = eth_type_trans(skb, dbg->dev); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_rx(skb); +} + +/***************************************************************************** + * NET_DEVICE functions + ****************************************************************************/ + +/** Opens the virtual network device. + * + * \return Always zero (success). + */ +int ec_dbgdev_open( + struct net_device *dev /**< debug net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + dbg->opened = 1; + EC_MASTER_INFO(dbg->device->master, "Debug interface %s opened.\n", + dev->name); + return 0; +} + +/****************************************************************************/ + +/** Stops the virtual network device. + * + * \return Always zero (success). + */ +int ec_dbgdev_stop( + struct net_device *dev /**< debug net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + dbg->opened = 0; + EC_MASTER_INFO(dbg->device->master, "Debug interface %s stopped.\n", + dev->name); + return 0; +} + +/****************************************************************************/ + +/** Transmits data via the virtual network device. + * + * \return Always zero (success). + */ +int ec_dbgdev_tx( + struct sk_buff *skb, /**< transmit socket buffer */ + struct net_device *dev /**< EoE net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + + dev_kfree_skb(skb); + dbg->stats.tx_dropped++; + return 0; +} + +/****************************************************************************/ + +/** Gets statistics about the virtual network device. + * + * \return Statistics. + */ +struct net_device_stats *ec_dbgdev_stats( + struct net_device *dev /**< debug net_device */ + ) +{ + ec_debug_t *dbg = *((ec_debug_t **) netdev_priv(dev)); + return &dbg->stats; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/debug.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/debug.h @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Network interface for debugging purposes. +*/ + +/****************************************************************************/ + +#ifndef __EC_DEBUG_H__ +#define __EC_DEBUG_H__ + +#include "../devices/ecdev.h" + +/****************************************************************************/ + +/** Debugging network interface. + */ +typedef struct +{ + ec_device_t *device; /**< Parent device. */ + struct net_device *dev; /**< net_device for virtual ethernet device */ + struct net_device_stats stats; /**< device statistics */ + uint8_t registered; /**< net_device is opened */ + uint8_t opened; /**< net_device is opened */ +} +ec_debug_t; + +/****************************************************************************/ + +int ec_debug_init(ec_debug_t *, ec_device_t *, const char *); +void ec_debug_clear(ec_debug_t *); +void ec_debug_register(ec_debug_t *, const struct net_device *); +void ec_debug_unregister(ec_debug_t *); +void ec_debug_send(ec_debug_t *, const uint8_t *, size_t); + +#endif + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/device.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/device.c @@ -0,0 +1,716 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT device methods. +*/ + +/****************************************************************************/ + +#include +#include +#include +#include + +#include "device.h" +#include "master.h" + +#ifdef EC_DEBUG_RING +#define timersub(a, b, result) \ + do { \ + (result)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ + (result)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ + if ((result)->tv_usec < 0) { \ + --(result)->tv_sec; \ + (result)->tv_usec += 1000000; \ + } \ + } while (0) +#endif + +/****************************************************************************/ + +enum { + /* genet driver needs extra headroom in skb for status block */ + EXTRA_HEADROOM = 64, +}; + +/** Constructor. + * + * \return 0 in case of success, else < 0 + */ +int ec_device_init( + ec_device_t *device, /**< EtherCAT device */ + ec_master_t *master /**< master owning the device */ + ) +{ + int ret; + unsigned int i; + struct ethhdr *eth; +#ifdef EC_DEBUG_IF + char ifname[10]; + char mb = 'x'; +#endif + + device->master = master; + device->dev = NULL; + device->poll = NULL; + device->module = NULL; + device->open = 0; + device->link_state = 0; + for (i = 0; i < EC_TX_RING_SIZE; i++) { + device->tx_skb[i] = NULL; + } + device->tx_ring_index = 0; +#ifdef EC_HAVE_CYCLES + device->cycles_poll = 0; +#endif +#ifdef EC_DEBUG_RING + device->timeval_poll.tv_sec = 0; + device->timeval_poll.tv_usec = 0; +#endif + device->jiffies_poll = 0; + + ec_device_clear_stats(device); + +#ifdef EC_DEBUG_RING + for (i = 0; i < EC_DEBUG_RING_SIZE; i++) { + ec_debug_frame_t *df = &device->debug_frames[i]; + df->dir = TX; + df->t.tv_sec = 0; + df->t.tv_usec = 0; + memset(df->data, 0, EC_MAX_DATA_SIZE); + df->data_size = 0; + } +#endif +#ifdef EC_DEBUG_RING + device->debug_frame_index = 0; + device->debug_frame_count = 0; +#endif + +#ifdef EC_DEBUG_IF + if (device == &master->devices[EC_DEVICE_MAIN]) { + mb = 'm'; + } + else { + mb = 'b'; + } + + sprintf(ifname, "ecdbg%c%u", mb, master->index); + + ret = ec_debug_init(&device->dbg, device, ifname); + if (ret < 0) { + EC_MASTER_ERR(master, "Failed to init debug device!\n"); + goto out_return; + } +#endif + + for (i = 0; i < EC_TX_RING_SIZE; i++) { + if (!(device->tx_skb[i] = dev_alloc_skb(ETH_FRAME_LEN + EXTRA_HEADROOM))) { + EC_MASTER_ERR(master, "Error allocating device socket buffer!\n"); + ret = -ENOMEM; + goto out_tx_ring; + } + + // add Ethernet-II-header + skb_reserve(device->tx_skb[i], ETH_HLEN + EXTRA_HEADROOM); + eth = (struct ethhdr *) skb_push(device->tx_skb[i], ETH_HLEN); + eth->h_proto = htons(0x88A4); + memset(eth->h_dest, 0xFF, ETH_ALEN); + } + + return 0; + +out_tx_ring: + for (i = 0; i < EC_TX_RING_SIZE; i++) { + if (device->tx_skb[i]) { + dev_kfree_skb(device->tx_skb[i]); + } + } +#ifdef EC_DEBUG_IF + ec_debug_clear(&device->dbg); +out_return: +#endif + return ret; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_device_clear( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + + if (device->open) { + ec_device_close(device); + } + for (i = 0; i < EC_TX_RING_SIZE; i++) + dev_kfree_skb(device->tx_skb[i]); +#ifdef EC_DEBUG_IF + ec_debug_clear(&device->dbg); +#endif +} + +/****************************************************************************/ + +/** Associate with net_device. + */ +void ec_device_attach( + ec_device_t *device, /**< EtherCAT device */ + struct net_device *net_dev, /**< net_device structure */ + ec_pollfunc_t poll, /**< pointer to device's poll function */ + struct module *module /**< the device's module */ + ) +{ + unsigned int i; + struct ethhdr *eth; + + ec_device_detach(device); // resets fields + + device->dev = net_dev; + device->poll = poll; + device->module = module; + + for (i = 0; i < EC_TX_RING_SIZE; i++) { + device->tx_skb[i]->dev = net_dev; + eth = (struct ethhdr *) (device->tx_skb[i]->data); + memcpy(eth->h_source, net_dev->dev_addr, ETH_ALEN); + } + +#ifdef EC_DEBUG_IF + ec_debug_register(&device->dbg, net_dev); +#endif +} + +/****************************************************************************/ + +/** Disconnect from net_device. + */ +void ec_device_detach( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + +#ifdef EC_DEBUG_IF + ec_debug_unregister(&device->dbg); +#endif + + device->dev = NULL; + device->poll = NULL; + device->module = NULL; + device->open = 0; + device->link_state = 0; // down + + ec_device_clear_stats(device); + + for (i = 0; i < EC_TX_RING_SIZE; i++) { + device->tx_skb[i]->dev = NULL; + } +} + +/****************************************************************************/ + +/** Opens the EtherCAT device. + * + * \return 0 in case of success, else < 0 + */ +int ec_device_open( + ec_device_t *device /**< EtherCAT device */ + ) +{ + int ret; + + if (!device->dev) { + EC_MASTER_ERR(device->master, "No net_device to open!\n"); + return -ENODEV; + } + + if (device->open) { + EC_MASTER_WARN(device->master, "Device already opened!\n"); + return 0; + } + + device->link_state = 0; + + ec_device_clear_stats(device); + + ret = device->dev->netdev_ops->ndo_open(device->dev); + if (!ret) + device->open = 1; + + return ret; +} + +/****************************************************************************/ + +/** Stops the EtherCAT device. + * + * \return 0 in case of success, else < 0 + */ +int ec_device_close( + ec_device_t *device /**< EtherCAT device */ + ) +{ + int ret; + + if (!device->dev) { + EC_MASTER_ERR(device->master, "No device to close!\n"); + return -ENODEV; + } + + if (!device->open) { + EC_MASTER_WARN(device->master, "Device already closed!\n"); + return 0; + } + + ret = device->dev->netdev_ops->ndo_stop(device->dev); + if (!ret) + device->open = 0; + + return ret; +} + +/****************************************************************************/ + +/** Returns a pointer to the device's transmit memory. + * + * \return pointer to the TX socket buffer + */ +uint8_t *ec_device_tx_data( + ec_device_t *device /**< EtherCAT device */ + ) +{ + /* cycle through socket buffers, because otherwise there is a race + * condition, if multiple frames are sent and the DMA is not scheduled in + * between. */ + device->tx_ring_index++; + device->tx_ring_index %= EC_TX_RING_SIZE; + return device->tx_skb[device->tx_ring_index]->data + ETH_HLEN; +} + +/****************************************************************************/ + +/** Sends the content of the transmit socket buffer. + * + * Cuts the socket buffer content to the (now known) size, and calls the + * start_xmit() function of the assigned net_device. + */ +void ec_device_send( + ec_device_t *device, /**< EtherCAT device */ + size_t size /**< number of bytes to send */ + ) +{ + struct sk_buff *skb = device->tx_skb[device->tx_ring_index]; + + // set the right length for the data + skb->len = ETH_HLEN + size; + + if (unlikely(device->master->debug_level > 1)) { + EC_MASTER_DBG(device->master, 2, "Sending frame:\n"); + ec_print_data(skb->data, ETH_HLEN + size); + } + + // start sending + if (device->dev->netdev_ops->ndo_start_xmit(skb, device->dev) == + NETDEV_TX_OK) + { + device->tx_count++; + device->master->device_stats.tx_count++; + device->tx_bytes += ETH_HLEN + size; + device->master->device_stats.tx_bytes += ETH_HLEN + size; +#ifdef EC_DEBUG_IF + ec_debug_send(&device->dbg, skb->data, ETH_HLEN + size); +#endif +#ifdef EC_DEBUG_RING + ec_device_debug_ring_append( + device, TX, skb->data + ETH_HLEN, size); +#endif + } else { + device->tx_errors++; + } +} + +/****************************************************************************/ + +/** Clears the frame statistics. + */ +void ec_device_clear_stats( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + + // zero frame statistics + device->tx_count = 0; + device->last_tx_count = 0; + device->rx_count = 0; + device->last_rx_count = 0; + device->tx_bytes = 0; + device->last_tx_bytes = 0; + device->rx_bytes = 0; + device->last_rx_bytes = 0; + device->tx_errors = 0; + + for (i = 0; i < EC_RATE_COUNT; i++) { + device->tx_frame_rates[i] = 0; + device->rx_frame_rates[i] = 0; + device->tx_byte_rates[i] = 0; + device->rx_byte_rates[i] = 0; + } +} + +/****************************************************************************/ + +#ifdef EC_DEBUG_RING +/** Appends frame data to the debug ring. + */ +void ec_device_debug_ring_append( + ec_device_t *device, /**< EtherCAT device */ + ec_debug_frame_dir_t dir, /**< direction */ + const void *data, /**< frame data */ + size_t size /**< data size */ + ) +{ + ec_debug_frame_t *df = &device->debug_frames[device->debug_frame_index]; + + df->dir = dir; + if (dir == TX) { + do_gettimeofday(&df->t); + } + else { + df->t = device->timeval_poll; + } + memcpy(df->data, data, size); + df->data_size = size; + + device->debug_frame_index++; + device->debug_frame_index %= EC_DEBUG_RING_SIZE; + if (unlikely(device->debug_frame_count < EC_DEBUG_RING_SIZE)) + device->debug_frame_count++; +} + +/****************************************************************************/ + +/** Outputs the debug ring. + */ +void ec_device_debug_ring_print( + const ec_device_t *device /**< EtherCAT device */ + ) +{ + int i; + unsigned int ring_index; + const ec_debug_frame_t *df; + struct timeval t0, diff; + + // calculate index of the newest frame in the ring to get its time + ring_index = (device->debug_frame_index + EC_DEBUG_RING_SIZE - 1) + % EC_DEBUG_RING_SIZE; + t0 = device->debug_frames[ring_index].t; + + EC_MASTER_DBG(device->master, 1, "Debug ring %u:\n", ring_index); + + // calculate index of the oldest frame in the ring + ring_index = (device->debug_frame_index + EC_DEBUG_RING_SIZE + - device->debug_frame_count) % EC_DEBUG_RING_SIZE; + + for (i = 0; i < device->debug_frame_count; i++) { + df = &device->debug_frames[ring_index]; + timersub(&t0, &df->t, &diff); + + EC_MASTER_DBG(device->master, 1, "Frame %u, dt=%u.%06u s, %s:\n", + i + 1 - device->debug_frame_count, + (unsigned int) diff.tv_sec, + (unsigned int) diff.tv_usec, + (df->dir == TX) ? "TX" : "RX"); + ec_print_data(df->data, df->data_size); + + ring_index++; + ring_index %= EC_DEBUG_RING_SIZE; + } +} +#endif + +/****************************************************************************/ + +/** Calls the poll function of the assigned net_device. + * + * The master itself works without using interrupts. Therefore the processing + * of received data and status changes of the network device has to be + * done by the master calling the ISR "manually". + */ +void ec_device_poll( + ec_device_t *device /**< EtherCAT device */ + ) +{ +#ifdef EC_HAVE_CYCLES + device->cycles_poll = get_cycles(); +#endif + device->jiffies_poll = jiffies; +#ifdef EC_DEBUG_RING + do_gettimeofday(&device->timeval_poll); +#endif + device->poll(device->dev); +} + +/****************************************************************************/ + +/** Update device statistics. + */ +void ec_device_update_stats( + ec_device_t *device /**< EtherCAT device */ + ) +{ + unsigned int i; + + s32 tx_frame_rate = (device->tx_count - device->last_tx_count) * 1000; + s32 rx_frame_rate = (device->rx_count - device->last_rx_count) * 1000; + s32 tx_byte_rate = (device->tx_bytes - device->last_tx_bytes); + s32 rx_byte_rate = (device->rx_bytes - device->last_rx_bytes); + + /* Low-pass filter: + * Y_n = y_(n - 1) + T / tau * (x - y_(n - 1)) | T = 1 + * -> Y_n += (x - y_(n - 1)) / tau + */ + for (i = 0; i < EC_RATE_COUNT; i++) { + s32 n = rate_intervals[i]; + device->tx_frame_rates[i] += + (tx_frame_rate - device->tx_frame_rates[i]) / n; + device->rx_frame_rates[i] += + (rx_frame_rate - device->rx_frame_rates[i]) / n; + device->tx_byte_rates[i] += + (tx_byte_rate - device->tx_byte_rates[i]) / n; + device->rx_byte_rates[i] += + (rx_byte_rate - device->rx_byte_rates[i]) / n; + } + + device->last_tx_count = device->tx_count; + device->last_rx_count = device->rx_count; + device->last_tx_bytes = device->tx_bytes; + device->last_rx_bytes = device->rx_bytes; +} + +/***************************************************************************** + * Device interface + ****************************************************************************/ + +/** Withdraws an EtherCAT device from the master. + * + * The device is disconnected from the master and all device ressources + * are freed. + * + * \attention Before calling this function, the ecdev_stop() function has + * to be called, to be sure that the master does not use the device + * any more. + * \ingroup DeviceInterface + */ +void ecdev_withdraw(ec_device_t *device /**< EtherCAT device */) +{ + ec_master_t *master = device->master; + char dev_str[20], mac_str[20]; + + ec_mac_print(device->dev->dev_addr, mac_str); + + if (device == &master->devices[EC_DEVICE_MAIN]) { + sprintf(dev_str, "main"); + } else if (device == &master->devices[EC_DEVICE_BACKUP]) { + sprintf(dev_str, "backup"); + } else { + EC_MASTER_WARN(master, "%s() called with unknown device %s!\n", + __func__, mac_str); + sprintf(dev_str, "UNKNOWN"); + } + + EC_MASTER_INFO(master, "Releasing %s device %s.\n", dev_str, mac_str); + + down(&master->device_sem); + ec_device_detach(device); + up(&master->device_sem); +} + +/****************************************************************************/ + +/** Opens the network device and makes the master enter IDLE phase. + * + * \return 0 on success, else < 0 + * \ingroup DeviceInterface + */ +int ecdev_open(ec_device_t *device /**< EtherCAT device */) +{ + int ret; + ec_master_t *master = device->master; + unsigned int all_open = 1, dev_idx; + + ret = ec_device_open(device); + if (ret) { + EC_MASTER_ERR(master, "Failed to open device: error %d!\n", ret); + return ret; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(device->master); dev_idx++) { + if (!master->devices[dev_idx].open) { + all_open = 0; + break; + } + } + + if (all_open) { + ret = ec_master_enter_idle_phase(device->master); + if (ret) { + EC_MASTER_ERR(device->master, "Failed to enter IDLE phase!\n"); + return ret; + } + } + + return 0; +} + +/****************************************************************************/ + +/** Makes the master leave IDLE phase and closes the network device. + * + * \return 0 on success, else < 0 + * \ingroup DeviceInterface + */ +void ecdev_close(ec_device_t *device /**< EtherCAT device */) +{ + ec_master_t *master = device->master; + + if (master->phase == EC_IDLE) { + ec_master_leave_idle_phase(master); + } + + if (ec_device_close(device)) { + EC_MASTER_WARN(master, "Failed to close device!\n"); + } +} + +/****************************************************************************/ + +/** Accepts a received frame. + * + * Forwards the received data to the master. The master will analyze the frame + * and dispatch the received commands to the sending instances. + * + * The data have to begin with the Ethernet header (target MAC address). + * + * \ingroup DeviceInterface + */ +void ecdev_receive( + ec_device_t *device, /**< EtherCAT device */ + const void *data, /**< pointer to received data */ + size_t size /**< number of bytes received */ + ) +{ + const void *ec_data = data + ETH_HLEN; + size_t ec_size = size - ETH_HLEN; + + if (unlikely(!data)) { + EC_MASTER_WARN(device->master, "%s() called with NULL data.\n", + __func__); + return; + } + + device->rx_count++; + device->master->device_stats.rx_count++; + device->rx_bytes += size; + device->master->device_stats.rx_bytes += size; + + if (unlikely(device->master->debug_level > 1)) { + EC_MASTER_DBG(device->master, 2, "Received frame:\n"); + ec_print_data(data, size); + } + +#ifdef EC_DEBUG_IF + ec_debug_send(&device->dbg, data, size); +#endif +#ifdef EC_DEBUG_RING + ec_device_debug_ring_append(device, RX, ec_data, ec_size); +#endif + + ec_master_receive_datagrams(device->master, device, ec_data, ec_size); +} + +/****************************************************************************/ + +/** Sets a new link state. + * + * If the device notifies the master about the link being down, the master + * will not try to send frames using this device. + * + * \ingroup DeviceInterface + */ +void ecdev_set_link( + ec_device_t *device, /**< EtherCAT device */ + uint8_t state /**< new link state */ + ) +{ + if (unlikely(!device)) { + EC_WARN("ecdev_set_link() called with null device!\n"); + return; + } + + if (likely(state != device->link_state)) { + device->link_state = state; + EC_MASTER_INFO(device->master, + "Link state of %s changed to %s.\n", + device->dev->name, (state ? "UP" : "DOWN")); + } +} + +/****************************************************************************/ + +/** Reads the link state. + * + * \ingroup DeviceInterface + * + * \return Link state. + */ +uint8_t ecdev_get_link( + const ec_device_t *device /**< EtherCAT device */ + ) +{ + if (unlikely(!device)) { + EC_WARN("ecdev_get_link() called with null device!\n"); + return 0; + } + + return device->link_state; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecdev_withdraw); +EXPORT_SYMBOL(ecdev_open); +EXPORT_SYMBOL(ecdev_close); +EXPORT_SYMBOL(ecdev_receive); +EXPORT_SYMBOL(ecdev_get_link); +EXPORT_SYMBOL(ecdev_set_link); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/device.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/device.h @@ -0,0 +1,150 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT device structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DEVICE_H__ +#define __EC_DEVICE_H__ + +#include + +#include "../devices/ecdev.h" +#include "globals.h" + +/** + * Size of the transmit ring. + * This memory ring is used to transmit frames. It is necessary to use + * different memory regions, because otherwise the network device DMA could + * send the same data twice, if it is called twice. + */ +#define EC_TX_RING_SIZE 2 + +#ifdef EC_DEBUG_IF +#include "debug.h" +#endif + +#ifdef EC_DEBUG_RING +#define EC_DEBUG_RING_SIZE 10 + +typedef enum { + TX, RX +} ec_debug_frame_dir_t; + +typedef struct { + ec_debug_frame_dir_t dir; + struct timeval t; + uint8_t data[EC_MAX_DATA_SIZE]; + unsigned int data_size; +} ec_debug_frame_t; + +#endif + +/****************************************************************************/ + +/** + EtherCAT device. + An EtherCAT device is a network interface card, that is owned by an + EtherCAT master to send and receive EtherCAT frames with. +*/ + +struct ec_device +{ + ec_master_t *master; /**< EtherCAT master */ + struct net_device *dev; /**< pointer to the assigned net_device */ + ec_pollfunc_t poll; /**< pointer to the device's poll function */ + struct module *module; /**< pointer to the device's owning module */ + uint8_t open; /**< true, if the net_device has been opened */ + uint8_t link_state; /**< device link state */ + struct sk_buff *tx_skb[EC_TX_RING_SIZE]; /**< transmit skb ring */ + unsigned int tx_ring_index; /**< last ring entry used to transmit */ +#ifdef EC_HAVE_CYCLES + cycles_t cycles_poll; /**< cycles of last poll */ +#endif +#ifdef EC_DEBUG_RING + struct timeval timeval_poll; +#endif + unsigned long jiffies_poll; /**< jiffies of last poll */ + + // Frame statistics + u64 tx_count; /**< Number of frames sent. */ + u64 last_tx_count; /**< Number of frames sent of last statistics cycle. */ + u64 rx_count; /**< Number of frames received. */ + u64 last_rx_count; /**< Number of frames received of last statistics + cycle. */ + u64 tx_bytes; /**< Number of bytes sent. */ + u64 last_tx_bytes; /**< Number of bytes sent of last statistics cycle. */ + u64 rx_bytes; /**< Number of bytes received. */ + u64 last_rx_bytes; /**< Number of bytes received of last statistics cycle. + */ + u64 tx_errors; /**< Number of transmit errors. */ + s32 tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for + different statistics cycle periods. + */ + s32 rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for + different statistics cycle periods. + */ + s32 tx_byte_rates[EC_RATE_COUNT]; /**< Transmit rates in byte/s for + different statistics cycle periods. */ + s32 rx_byte_rates[EC_RATE_COUNT]; /**< Receive rates in byte/s for + different statistics cycle periods. */ + +#ifdef EC_DEBUG_IF + ec_debug_t dbg; /**< debug device */ +#endif +#ifdef EC_DEBUG_RING + ec_debug_frame_t debug_frames[EC_DEBUG_RING_SIZE]; + unsigned int debug_frame_index; + unsigned int debug_frame_count; +#endif +}; + +/****************************************************************************/ + +int ec_device_init(ec_device_t *, ec_master_t *); +void ec_device_clear(ec_device_t *); + +void ec_device_attach(ec_device_t *, struct net_device *, ec_pollfunc_t, + struct module *); +void ec_device_detach(ec_device_t *); + +int ec_device_open(ec_device_t *); +int ec_device_close(ec_device_t *); + +void ec_device_poll(ec_device_t *); +uint8_t *ec_device_tx_data(ec_device_t *); +void ec_device_send(ec_device_t *, size_t); +void ec_device_clear_stats(ec_device_t *); +void ec_device_update_stats(ec_device_t *); + +#ifdef EC_DEBUG_RING +void ec_device_debug_ring_append(ec_device_t *, ec_debug_frame_dir_t, + const void *, size_t); +void ec_device_debug_ring_print(const ec_device_t *); +#endif + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/domain.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/domain.c @@ -0,0 +1,719 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT domain methods. +*/ + +/****************************************************************************/ + +#include + +#include "globals.h" +#include "master.h" +#include "slave_config.h" + +#include "domain.h" +#include "datagram_pair.h" + +/** Extra debug output for redundancy functions. + */ +#define DEBUG_REDUNDANCY 0 + +/****************************************************************************/ + +// prototypes for private methods +void ec_domain_clear_data(ec_domain_t *); +int ec_domain_add_datagram_pair(ec_domain_t *, uint32_t, size_t, uint8_t *, + const unsigned int []); +int shall_count(const ec_fmmu_config_t *, const ec_fmmu_config_t *); +#if EC_MAX_NUM_DEVICES > 1 +int data_changed(uint8_t *, const ec_datagram_t *, size_t, size_t); +#endif + +/****************************************************************************/ + +/** Domain constructor. + */ +void ec_domain_init( + ec_domain_t *domain, /**< EtherCAT domain. */ + ec_master_t *master, /**< Parent master. */ + unsigned int index /**< Index. */ + ) +{ + unsigned int dev_idx; + + domain->master = master; + domain->index = index; + INIT_LIST_HEAD(&domain->fmmu_configs); + domain->data_size = 0; + domain->data = NULL; + domain->data_origin = EC_ORIG_INTERNAL; + domain->logical_base_address = 0x00000000; + INIT_LIST_HEAD(&domain->datagram_pairs); + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + domain->working_counter[dev_idx] = 0x0000; + } + domain->expected_working_counter = 0x0000; + domain->working_counter_changes = 0; + domain->redundancy_active = 0; + domain->notify_jiffies = 0; +} + +/****************************************************************************/ + +/** Domain destructor. + */ +void ec_domain_clear(ec_domain_t *domain /**< EtherCAT domain */) +{ + ec_datagram_pair_t *datagram_pair, *next_pair; + + // dequeue and free datagrams + list_for_each_entry_safe(datagram_pair, next_pair, + &domain->datagram_pairs, list) { + ec_datagram_pair_clear(datagram_pair); + kfree(datagram_pair); + } + + ec_domain_clear_data(domain); +} + +/****************************************************************************/ + +/** Frees internally allocated memory. + */ +void ec_domain_clear_data( + ec_domain_t *domain /**< EtherCAT domain. */ + ) +{ + if (domain->data_origin == EC_ORIG_INTERNAL && domain->data) { + kfree(domain->data); + } + + domain->data = NULL; + domain->data_origin = EC_ORIG_INTERNAL; +} + +/****************************************************************************/ + +/** Adds an FMMU configuration to the domain. + */ +void ec_domain_add_fmmu_config( + ec_domain_t *domain, /**< EtherCAT domain. */ + ec_fmmu_config_t *fmmu /**< FMMU configuration. */ + ) +{ + fmmu->domain = domain; + + domain->data_size += fmmu->data_size; + list_add_tail(&fmmu->list, &domain->fmmu_configs); + + EC_MASTER_DBG(domain->master, 1, "Domain %u:" + " Added %u bytes, total %zu.\n", + domain->index, fmmu->data_size, domain->data_size); +} + +/****************************************************************************/ + +/** Allocates a domain datagram pair and appends it to the list. + * + * The datagrams' types and expected working counters are determined by the + * number of input and output fmmus that share the datagrams. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_domain_add_datagram_pair( + ec_domain_t *domain, /**< EtherCAT domain. */ + uint32_t logical_offset, /**< Logical offset. */ + size_t data_size, /**< Size of the data. */ + uint8_t *data, /**< Process data. */ + const unsigned int used[] /**< Slave config counter for in/out. */ + ) +{ + ec_datagram_pair_t *datagram_pair; + int ret; + + if (!(datagram_pair = kmalloc(sizeof(ec_datagram_pair_t), GFP_KERNEL))) { + EC_MASTER_ERR(domain->master, + "Failed to allocate domain datagram pair!\n"); + return -ENOMEM; + } + + ret = ec_datagram_pair_init(datagram_pair, domain, logical_offset, data, + data_size, used); + if (ret) { + kfree(datagram_pair); + return ret; + } + + domain->expected_working_counter += + datagram_pair->expected_working_counter; + + EC_MASTER_DBG(domain->master, 1, + "Adding datagram pair with expected WC %u.\n", + datagram_pair->expected_working_counter); + + + list_add_tail(&datagram_pair->list, &domain->datagram_pairs); + return 0; +} + +/****************************************************************************/ + +/** Domain finish helper function. + * + * Detects, if a slave configuration has already been taken into account for + * a datagram's expected working counter calculation. + * + * Walks through the list of all FMMU configurations for the current datagram + * and ends before the current datagram. + * + * \return Non-zero if slave connfig was already counted. + */ +int shall_count( + const ec_fmmu_config_t *cur_fmmu, /**< Current FMMU with direction to + search for. */ + const ec_fmmu_config_t *first_fmmu /**< Datagram's first FMMU. */ + ) +{ + for (; first_fmmu != cur_fmmu; + first_fmmu = list_entry(first_fmmu->list.next, + ec_fmmu_config_t, list)) { + + if (first_fmmu->sc == cur_fmmu->sc + && first_fmmu->dir == cur_fmmu->dir) { + return 0; // was already counted + } + } + + return 1; +} + +/****************************************************************************/ + +/** Finishes a domain. + * + * This allocates the necessary datagrams and writes the correct logical + * addresses to every configured FMMU. + * + * \todo Check for FMMUs that do not fit into any datagram. + * + * \retval 0 Success + * \retval <0 Error code. + */ +int ec_domain_finish( + ec_domain_t *domain, /**< EtherCAT domain. */ + uint32_t base_address /**< Logical base address. */ + ) +{ + uint32_t datagram_offset; + size_t datagram_size; + unsigned int datagram_count; + unsigned int datagram_used[EC_DIR_COUNT]; + ec_fmmu_config_t *fmmu; + const ec_fmmu_config_t *datagram_first_fmmu = NULL; + const ec_datagram_pair_t *datagram_pair; + int ret; + + domain->logical_base_address = base_address; + + if (domain->data_size && domain->data_origin == EC_ORIG_INTERNAL) { + if (!(domain->data = + (uint8_t *) kmalloc(domain->data_size, GFP_KERNEL))) { + EC_MASTER_ERR(domain->master, "Failed to allocate %zu bytes" + " internal memory for domain %u!\n", + domain->data_size, domain->index); + return -ENOMEM; + } + } + + // Cycle through all domain FMMUs and + // - correct the logical base addresses + // - set up the datagrams to carry the process data + // - calculate the datagrams' expected working counters + datagram_offset = 0; + datagram_size = 0; + datagram_count = 0; + datagram_used[EC_DIR_OUTPUT] = 0; + datagram_used[EC_DIR_INPUT] = 0; + + if (!list_empty(&domain->fmmu_configs)) { + datagram_first_fmmu = + list_entry(domain->fmmu_configs.next, ec_fmmu_config_t, list); + } + + list_for_each_entry(fmmu, &domain->fmmu_configs, list) { + + // Correct logical FMMU address + fmmu->logical_start_address += base_address; + + // If the current FMMU's data do not fit in the current datagram, + // allocate a new one. + if (datagram_size + fmmu->data_size > EC_MAX_DATA_SIZE) { + ret = ec_domain_add_datagram_pair(domain, + domain->logical_base_address + datagram_offset, + datagram_size, domain->data + datagram_offset, + datagram_used); + if (ret < 0) + return ret; + + datagram_offset += datagram_size; + datagram_size = 0; + datagram_count++; + datagram_used[EC_DIR_OUTPUT] = 0; + datagram_used[EC_DIR_INPUT] = 0; + datagram_first_fmmu = fmmu; + } + + // Increment Input/Output counter to determine datagram types + // and calculate expected working counters + if (shall_count(fmmu, datagram_first_fmmu)) { + datagram_used[fmmu->dir]++; + } + + datagram_size += fmmu->data_size; + } + + /* Allocate last datagram pair, if data are left (this is also the case if + * the process data fit into a single datagram) */ + if (datagram_size) { + ret = ec_domain_add_datagram_pair(domain, + domain->logical_base_address + datagram_offset, + datagram_size, domain->data + datagram_offset, + datagram_used); + if (ret < 0) + return ret; + datagram_count++; + } + + EC_MASTER_INFO(domain->master, "Domain%u: Logical address 0x%08x," + " %zu byte, expected working counter %u.\n", domain->index, + domain->logical_base_address, domain->data_size, + domain->expected_working_counter); + + list_for_each_entry(datagram_pair, &domain->datagram_pairs, list) { + const ec_datagram_t *datagram = + &datagram_pair->datagrams[EC_DEVICE_MAIN]; + EC_MASTER_INFO(domain->master, " Datagram %s: Logical offset 0x%08x," + " %zu byte, type %s.\n", datagram->name, + EC_READ_U32(datagram->address), datagram->data_size, + ec_datagram_type_string(datagram)); + } + + return 0; +} + +/****************************************************************************/ + +/** Get the number of FMMU configurations of the domain. + */ +unsigned int ec_domain_fmmu_count(const ec_domain_t *domain) +{ + const ec_fmmu_config_t *fmmu; + unsigned int num = 0; + + list_for_each_entry(fmmu, &domain->fmmu_configs, list) { + num++; + } + + return num; +} + +/****************************************************************************/ + +/** Get a certain FMMU configuration via its position in the list. + * + * \return FMMU at position \a pos, or NULL. + */ +const ec_fmmu_config_t *ec_domain_find_fmmu( + const ec_domain_t *domain, /**< EtherCAT domain. */ + unsigned int pos /**< List position. */ + ) +{ + const ec_fmmu_config_t *fmmu; + + list_for_each_entry(fmmu, &domain->fmmu_configs, list) { + if (pos--) + continue; + return fmmu; + } + + return NULL; +} + +/****************************************************************************/ + +#if EC_MAX_NUM_DEVICES > 1 + +/** Process received data. + */ +int data_changed( + uint8_t *send_buffer, + const ec_datagram_t *datagram, + size_t offset, + size_t size + ) +{ + uint8_t *sent = send_buffer + offset; + uint8_t *recv = datagram->data + offset; + size_t i; + + for (i = 0; i < size; i++) { + if (recv[i] != sent[i]) { + return 1; + } + } + + return 0; +} + +#endif + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +int ecrt_domain_reg_pdo_entry_list(ec_domain_t *domain, + const ec_pdo_entry_reg_t *regs) +{ + const ec_pdo_entry_reg_t *reg; + ec_slave_config_t *sc; + int ret; + + EC_MASTER_DBG(domain->master, 1, "ecrt_domain_reg_pdo_entry_list(" + "domain = 0x%p, regs = 0x%p)\n", domain, regs); + + for (reg = regs; reg->index; reg++) { + sc = ecrt_master_slave_config_err(domain->master, reg->alias, + reg->position, reg->vendor_id, reg->product_code); + if (IS_ERR(sc)) + return PTR_ERR(sc); + + ret = ecrt_slave_config_reg_pdo_entry(sc, reg->index, + reg->subindex, domain, reg->bit_position); + if (ret < 0) + return ret; + + *reg->offset = ret; + } + + return 0; +} + +/****************************************************************************/ + +size_t ecrt_domain_size(const ec_domain_t *domain) +{ + return domain->data_size; +} + +/****************************************************************************/ + +void ecrt_domain_external_memory(ec_domain_t *domain, uint8_t *mem) +{ + EC_MASTER_DBG(domain->master, 1, "ecrt_domain_external_memory(" + "domain = 0x%p, mem = 0x%p)\n", domain, mem); + + down(&domain->master->master_sem); + + ec_domain_clear_data(domain); + + domain->data = mem; + domain->data_origin = EC_ORIG_EXTERNAL; + + up(&domain->master->master_sem); +} + +/****************************************************************************/ + +uint8_t *ecrt_domain_data(const ec_domain_t *domain) +{ + return domain->data; +} + +/****************************************************************************/ + +int ecrt_domain_process(ec_domain_t *domain) +{ + uint16_t wc_sum[EC_MAX_NUM_DEVICES] = {}, wc_total; + ec_datagram_pair_t *pair; +#if EC_MAX_NUM_DEVICES > 1 + uint16_t datagram_pair_wc, redundant_wc; + unsigned int datagram_offset; + ec_fmmu_config_t *fmmu = list_first_entry(&domain->fmmu_configs, + ec_fmmu_config_t, list); + unsigned int redundancy; +#endif + unsigned int dev_idx; +#ifdef EC_RT_SYSLOG + unsigned int wc_change; +#endif + +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "domain %u process\n", domain->index); +#endif + + list_for_each_entry(pair, &domain->datagram_pairs, list) { +#if EC_MAX_NUM_DEVICES > 1 + datagram_pair_wc = ec_datagram_pair_process(pair, wc_sum); +#else + ec_datagram_pair_process(pair, wc_sum); +#endif + +#if EC_MAX_NUM_DEVICES > 1 + if (ec_master_num_devices(domain->master) > 1) { + ec_datagram_t *main_datagram = &pair->datagrams[EC_DEVICE_MAIN]; + uint32_t logical_datagram_address = + EC_READ_U32(main_datagram->address); + size_t datagram_size = main_datagram->data_size; + +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "dgram %s log=%u\n", + main_datagram->name, logical_datagram_address); +#endif + + /* Redundancy: Go through FMMU configs to detect data changes. */ + list_for_each_entry_from(fmmu, &domain->fmmu_configs, list) { + ec_datagram_t *backup_datagram = + &pair->datagrams[EC_DEVICE_BACKUP]; + + if (fmmu->dir != EC_DIR_INPUT) { + continue; + } + + if (fmmu->logical_start_address >= + logical_datagram_address + datagram_size) { + // fmmu data contained in next datagram pair + break; + } + + datagram_offset = + fmmu->logical_start_address - logical_datagram_address; + +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, + "input fmmu log=%u size=%u offset=%u\n", + fmmu->logical_start_address, fmmu->data_size, + datagram_offset); + if (domain->master->debug_level > 0) { + ec_print_data(pair->send_buffer + datagram_offset, + fmmu->data_size); + ec_print_data(main_datagram->data + datagram_offset, + fmmu->data_size); + ec_print_data(backup_datagram->data + datagram_offset, + fmmu->data_size); + } +#endif + + if (data_changed(pair->send_buffer, main_datagram, + datagram_offset, fmmu->data_size)) { + /* data changed on main link: no copying necessary. */ +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "main changed\n"); +#endif + } else if (data_changed(pair->send_buffer, backup_datagram, + datagram_offset, fmmu->data_size)) { + /* data changed on backup link: copy to main memory. */ +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, "backup changed\n"); +#endif + memcpy(main_datagram->data + datagram_offset, + backup_datagram->data + datagram_offset, + fmmu->data_size); + } else if (datagram_pair_wc == + pair->expected_working_counter) { + /* no change, but WC complete: use main data. */ +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, + "no change but complete\n"); +#endif + } else { + /* no change and WC incomplete: mark WC as zero to avoid + * data.dependent WC flickering. */ + datagram_pair_wc = 0; +#if DEBUG_REDUNDANCY + EC_MASTER_DBG(domain->master, 1, + "no change and incomplete\n"); +#endif + } + } + } +#endif // EC_MAX_NUM_DEVICES > 1 + } + +#if EC_MAX_NUM_DEVICES > 1 + redundant_wc = 0; + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + redundant_wc += wc_sum[dev_idx]; + } + + redundancy = redundant_wc > 0; + if (redundancy != domain->redundancy_active) { +#ifdef EC_RT_SYSLOG + if (redundancy) { + EC_MASTER_WARN(domain->master, + "Domain %u: Redundant link in use!\n", + domain->index); + } else { + EC_MASTER_INFO(domain->master, + "Domain %u: Redundant link unused again.\n", + domain->index); + } +#endif + domain->redundancy_active = redundancy; + } +#else + domain->redundancy_active = 0; +#endif + +#ifdef EC_RT_SYSLOG + wc_change = 0; +#endif + wc_total = 0; + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + if (wc_sum[dev_idx] != domain->working_counter[dev_idx]) { +#ifdef EC_RT_SYSLOG + wc_change = 1; +#endif + domain->working_counter[dev_idx] = wc_sum[dev_idx]; + } + wc_total += wc_sum[dev_idx]; + } + +#ifdef EC_RT_SYSLOG + if (wc_change) { + domain->working_counter_changes++; + } + + if (domain->working_counter_changes && + jiffies - domain->notify_jiffies > HZ) { + domain->notify_jiffies = jiffies; + if (domain->working_counter_changes == 1) { + EC_MASTER_INFO(domain->master, "Domain %u: Working counter" + " changed to %u/%u", domain->index, + wc_total, domain->expected_working_counter); + } else { + EC_MASTER_INFO(domain->master, "Domain %u: %u working counter" + " changes - now %u/%u", domain->index, + domain->working_counter_changes, + wc_total, domain->expected_working_counter); + } +#if EC_MAX_NUM_DEVICES > 1 + if (ec_master_num_devices(domain->master) > 1) { + printk(KERN_CONT " ("); + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); + dev_idx++) { + printk(KERN_CONT "%u", domain->working_counter[dev_idx]); + if (dev_idx + 1 < ec_master_num_devices(domain->master)) { + printk(KERN_CONT "+"); + } + } + printk(KERN_CONT ")"); + } +#endif + printk(KERN_CONT ".\n"); + + domain->working_counter_changes = 0; + } +#endif + return 0; +} + +/****************************************************************************/ + +int ecrt_domain_queue(ec_domain_t *domain) +{ + ec_datagram_pair_t *datagram_pair; + ec_device_index_t dev_idx; + + list_for_each_entry(datagram_pair, &domain->datagram_pairs, list) { + +#if EC_MAX_NUM_DEVICES > 1 + /* copy main data to send buffer */ + memcpy(datagram_pair->send_buffer, + datagram_pair->datagrams[EC_DEVICE_MAIN].data, + datagram_pair->datagrams[EC_DEVICE_MAIN].data_size); +#endif + ec_master_queue_datagram(domain->master, + &datagram_pair->datagrams[EC_DEVICE_MAIN]); + + /* copy main data to backup datagram */ + for (dev_idx = EC_DEVICE_BACKUP; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + memcpy(datagram_pair->datagrams[dev_idx].data, + datagram_pair->datagrams[EC_DEVICE_MAIN].data, + datagram_pair->datagrams[EC_DEVICE_MAIN].data_size); + ec_master_queue_datagram(domain->master, + &datagram_pair->datagrams[dev_idx]); + } + } + return 0; +} + +/****************************************************************************/ + +int ecrt_domain_state(const ec_domain_t *domain, ec_domain_state_t *state) +{ + unsigned int dev_idx; + uint16_t wc = 0; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + wc += domain->working_counter[dev_idx]; + } + + state->working_counter = wc; + + if (wc) { + if (wc == domain->expected_working_counter) { + state->wc_state = EC_WC_COMPLETE; + } else { + state->wc_state = EC_WC_INCOMPLETE; + } + } else { + state->wc_state = EC_WC_ZERO; + } + + state->redundancy_active = domain->redundancy_active; + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_domain_reg_pdo_entry_list); +EXPORT_SYMBOL(ecrt_domain_size); +EXPORT_SYMBOL(ecrt_domain_external_memory); +EXPORT_SYMBOL(ecrt_domain_data); +EXPORT_SYMBOL(ecrt_domain_process); +EXPORT_SYMBOL(ecrt_domain_queue); +EXPORT_SYMBOL(ecrt_domain_state); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/domain.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/domain.h @@ -0,0 +1,82 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT domain structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_DOMAIN_H__ +#define __EC_DOMAIN_H__ + +#include + +#include "globals.h" +#include "datagram.h" +#include "master.h" +#include "fmmu_config.h" + +/****************************************************************************/ + +/** EtherCAT domain. + * + * Handles the process data and the therefore needed datagrams of a certain + * group of slaves. + */ +struct ec_domain +{ + struct list_head list; /**< List item. */ + ec_master_t *master; /**< EtherCAT master owning the domain. */ + unsigned int index; /**< Index (just a number). */ + + struct list_head fmmu_configs; /**< FMMU configurations contained. */ + size_t data_size; /**< Size of the process data. */ + uint8_t *data; /**< Memory for the process data. */ + ec_origin_t data_origin; /**< Origin of the \a data memory. */ + uint32_t logical_base_address; /**< Logical offset address of the + process data. */ + struct list_head datagram_pairs; /**< Datagrams pairs (main/backup) for + process data exchange. */ + uint16_t working_counter[EC_MAX_NUM_DEVICES]; /**< Last working counter + values. */ + uint16_t expected_working_counter; /**< Expected working counter. */ + unsigned int working_counter_changes; /**< Working counter changes + since last notification. */ + unsigned int redundancy_active; /**< Non-zero, if redundancy is in use. */ + unsigned long notify_jiffies; /**< Time of last notification. */ +}; + +/****************************************************************************/ + +void ec_domain_init(ec_domain_t *, ec_master_t *, unsigned int); +void ec_domain_clear(ec_domain_t *); + +void ec_domain_add_fmmu_config(ec_domain_t *, ec_fmmu_config_t *); +int ec_domain_finish(ec_domain_t *, uint32_t); + +unsigned int ec_domain_fmmu_count(const ec_domain_t *); +const ec_fmmu_config_t *ec_domain_find_fmmu(const ec_domain_t *, unsigned int); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/doxygen.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/doxygen.c @@ -0,0 +1,82 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +// This file only contains the doxygen mainpage. + +/** \file + * Doxygen mainpage only. + */ + +/****************************************************************************/ + +/** + \mainpage + + \section sec_general General information + + This HTML contains the complete code documentation. + + The API documentations are in the modules + section. + + A list of all native network card drivers can be found + here. + + A second userspace library can be used for a dry-run mode + or simulating Process Data. + + For information how to build and install, see the INSTALL file in the source + root. + + \section sec_contact Contact + + \verbatim + Florian Pose + Ingenieurgemeinschaft IgH + Nordsternstraße 66 + D-45329 Essen + http://igh.de + \endverbatim + + \section sec_license License + + \verbatim + Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + + This file is part of the IgH EtherCAT Master. + + The IgH EtherCAT Master is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License version 2, as + published by the Free Software Foundation. + + The IgH EtherCAT Master is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + Public License for more details. + + You should have received a copy of the GNU General Public License along + with the IgH EtherCAT Master; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + \endverbatim +*/ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/eoe_request.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/eoe_request.c @@ -0,0 +1,80 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Ethernet-over-EtherCAT request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "eoe_request.h" + +/****************************************************************************/ + +/** EoE request constructor. + */ +void ec_eoe_request_init( + ec_eoe_request_t *req /**< EoE request. */ + ) +{ + INIT_LIST_HEAD(&req->list); + req->state = EC_INT_REQUEST_INIT; + req->jiffies_sent = 0U; + + req->mac_address_included = 0; + req->ip_address_included = 0; + req->subnet_mask_included = 0; + req->gateway_included = 0; + req->dns_included = 0; + req->name_included = 0; + + memset(req->mac_address, 0x00, ETH_ALEN); + req->ip_address.s_addr = 0; + req->subnet_mask.s_addr = 0; + req->gateway.s_addr = 0; + req->dns.s_addr = 0; + req->name[0] = 0x00; + + req->result = 0x0000; +} + +/****************************************************************************/ + +/** Checks if EoE request has something to set. + */ +int ec_eoe_request_valid( + const ec_eoe_request_t *req /**< EoE request. */ + ) +{ + return + req->mac_address_included || + req->ip_address_included || + req->subnet_mask_included || + req->gateway_included || + req->dns_included || + req->name_included; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/eoe_request.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/eoe_request.h @@ -0,0 +1,70 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2014 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT EoE request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_EOE_REQUEST_H__ +#define __EC_EOE_REQUEST_H__ + +#include +#include // ETH_ALEN + +#include "globals.h" + +/****************************************************************************/ + +/** Ethernet-over-EtherCAT set IP parameter request. + */ +typedef struct { + struct list_head list; /**< List item. */ + ec_internal_request_state_t state; /**< Request state. */ + unsigned long jiffies_sent; /**< Jiffies, when the request was sent. */ + + uint8_t mac_address_included; + uint8_t ip_address_included; + uint8_t subnet_mask_included; + uint8_t gateway_included; + uint8_t dns_included; + uint8_t name_included; + + unsigned char mac_address[ETH_ALEN]; + struct in_addr ip_address; + struct in_addr subnet_mask; + struct in_addr gateway; + struct in_addr dns; + char name[EC_MAX_HOSTNAME_SIZE]; + + uint16_t result; +} ec_eoe_request_t; + +/****************************************************************************/ + +void ec_eoe_request_init(ec_eoe_request_t *); +int ec_eoe_request_valid(const ec_eoe_request_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/ethernet.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/ethernet.c @@ -0,0 +1,886 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Ethernet over EtherCAT (EoE). +*/ + +/****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "globals.h" +#include "master.h" +#include "slave.h" +#include "mailbox.h" +#include "ethernet.h" + +#if defined(CONFIG_SUSE_KERNEL) && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +#include +#else +# ifndef SUSE_VERSION +# define SUSE_VERSION 0 +# endif +# ifndef SUSE_PATCHLEVEL +# define SUSE_PATCHLEVEL 0 +# endif +#endif + +/****************************************************************************/ + +/** Defines the debug level of EoE processing. + * + * 0 = No debug messages. + * 1 = Output warnings. + * 2 = Output actions. + * 3 = Output actions and frame data. + */ +#define EOE_DEBUG_LEVEL 1 + +/** Size of the EoE tx queue. + */ +#define EC_EOE_TX_QUEUE_SIZE 100 + +/** Number of tries. + */ +#define EC_EOE_TRIES 100 + +/****************************************************************************/ + +// prototypes for private methods +void ec_eoe_flush(ec_eoe_t *); +int ec_eoe_send(ec_eoe_t *); + +/****************************************************************************/ + +// state functions +void ec_eoe_state_rx_start(ec_eoe_t *); +void ec_eoe_state_rx_check(ec_eoe_t *); +void ec_eoe_state_rx_fetch(ec_eoe_t *); +void ec_eoe_state_tx_start(ec_eoe_t *); +void ec_eoe_state_tx_sent(ec_eoe_t *); + +// net_device functions +int ec_eoedev_open(struct net_device *); +int ec_eoedev_stop(struct net_device *); +int ec_eoedev_tx(struct sk_buff *, struct net_device *); +struct net_device_stats *ec_eoedev_stats(struct net_device *); + +/****************************************************************************/ + +/** Device operations for EoE interfaces. + */ +static const struct net_device_ops ec_eoedev_ops = { + .ndo_open = ec_eoedev_open, + .ndo_stop = ec_eoedev_stop, + .ndo_start_xmit = ec_eoedev_tx, + .ndo_get_stats = ec_eoedev_stats, +}; + +/****************************************************************************/ + +/** EoE constructor. + * + * Initializes the EoE handler, creates a net_device and registers it. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_eoe_init( + ec_eoe_t *eoe, /**< EoE handler */ + ec_slave_t *slave /**< EtherCAT slave */ + ) +{ + ec_eoe_t **priv; + int ret = 0; + char name[EC_DATAGRAM_NAME_SIZE]; + u8 mac_addr[ETH_ALEN] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55}; + + eoe->slave = slave; + + ec_datagram_init(&eoe->datagram); + eoe->queue_datagram = 0; + eoe->state = ec_eoe_state_rx_start; + eoe->opened = 0; + eoe->rx_skb = NULL; + eoe->rx_expected_fragment = 0; + INIT_LIST_HEAD(&eoe->tx_queue); + eoe->tx_frame = NULL; + eoe->tx_queue_active = 0; + eoe->tx_queue_size = EC_EOE_TX_QUEUE_SIZE; + eoe->tx_queued_frames = 0; + + eoe->tx_frame_number = 0xFF; + memset(&eoe->stats, 0, sizeof(struct net_device_stats)); + + eoe->rx_counter = 0; + eoe->tx_counter = 0; + eoe->rx_rate = 0; + eoe->tx_rate = 0; + eoe->rate_jiffies = 0; + eoe->rx_idle = 1; + eoe->tx_idle = 1; + + /* device name eoe[as], because networking scripts don't + * like hyphens etc. in interface names. */ + if (slave->effective_alias) { + snprintf(name, EC_DATAGRAM_NAME_SIZE, + "eoe%ua%u", slave->master->index, slave->effective_alias); + } else { + snprintf(name, EC_DATAGRAM_NAME_SIZE, + "eoe%us%u", slave->master->index, slave->ring_position); + } + + snprintf(eoe->datagram.name, EC_DATAGRAM_NAME_SIZE, name); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) + eoe->dev = alloc_netdev(sizeof(ec_eoe_t *), name, NET_NAME_UNKNOWN, + ether_setup); +#else + eoe->dev = alloc_netdev(sizeof(ec_eoe_t *), name, ether_setup); +#endif + if (!eoe->dev) { + EC_SLAVE_ERR(slave, "Unable to allocate net_device %s" + " for EoE handler!\n", name); + ret = -ENODEV; + goto out_return; + } + + // initialize net_device + eoe->dev->netdev_ops = &ec_eoedev_ops; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) || (SUSE_VERSION == 15 && SUSE_PATCHLEVEL >= 5) + eth_hw_addr_set(eoe->dev, mac_addr); +#else + memcpy(eoe->dev->dev_addr, mac_addr, sizeof(mac_addr)); +#endif + + // initialize private data + priv = netdev_priv(eoe->dev); + *priv = eoe; + + // Usually setting the MTU appropriately makes the upper layers + // do the frame fragmenting. In some cases this doesn't work + // so the MTU is left on the Ethernet standard value and fragmenting + // is done "manually". +#if 0 + eoe->dev->mtu = slave->configured_rx_mailbox_size - ETH_HLEN - 10; +#endif + + // connect the net_device to the kernel + ret = register_netdev(eoe->dev); + if (ret) { + EC_SLAVE_ERR(slave, "Unable to register net_device:" + " error %i\n", ret); + goto out_free; + } + + // make the last address octet unique + mac_addr[ETH_ALEN - 1] = (uint8_t) eoe->dev->ifindex; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) || (SUSE_VERSION == 15 && SUSE_PATCHLEVEL >= 5) + eth_hw_addr_set(eoe->dev, mac_addr); +#else + memcpy(eoe->dev->dev_addr, mac_addr, sizeof(mac_addr)); +#endif + + return 0; + + out_free: + free_netdev(eoe->dev); + eoe->dev = NULL; + out_return: + return ret; +} + +/****************************************************************************/ + +/** EoE destructor. + * + * Unregisteres the net_device and frees allocated memory. + */ +void ec_eoe_clear(ec_eoe_t *eoe /**< EoE handler */) +{ + unregister_netdev(eoe->dev); // possibly calls close callback + + // empty transmit queue + ec_eoe_flush(eoe); + + if (eoe->tx_frame) { + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + } + + if (eoe->rx_skb) + dev_kfree_skb(eoe->rx_skb); + + free_netdev(eoe->dev); + + ec_datagram_clear(&eoe->datagram); +} + +/****************************************************************************/ + +/** Empties the transmit queue. + */ +void ec_eoe_flush(ec_eoe_t *eoe /**< EoE handler */) +{ + ec_eoe_frame_t *frame, *next; + struct list_head tx_queue; + + netif_tx_lock_bh(eoe->dev); + + list_replace_init(&eoe->tx_queue, &tx_queue); + eoe->tx_queued_frames = 0; + + netif_tx_unlock_bh(eoe->dev); + + list_for_each_entry_safe(frame, next, &tx_queue, queue) { + list_del(&frame->queue); + dev_kfree_skb(frame->skb); + kfree(frame); + } +} + +/****************************************************************************/ + +/** Sends a frame or the next fragment. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_eoe_send(ec_eoe_t *eoe /**< EoE handler */) +{ + size_t remaining_size, current_size, complete_offset; + unsigned int last_fragment; + uint8_t *data; +#if EOE_DEBUG_LEVEL >= 3 + unsigned int i; +#endif + + remaining_size = eoe->tx_frame->skb->len - eoe->tx_offset; + + if (remaining_size <= eoe->slave->configured_tx_mailbox_size - 10) { + current_size = remaining_size; + last_fragment = 1; + } else { + current_size = ((eoe->slave->configured_tx_mailbox_size - 10) / 32) * 32; + last_fragment = 0; + } + + if (eoe->tx_fragment_number) { + complete_offset = eoe->tx_offset / 32; + } + else { + // complete size in 32 bit blocks, rounded up. + complete_offset = remaining_size / 32 + 1; + } + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s TX sending fragment %u%s" + " with %zu octets (%zu). %u frames queued.\n", + eoe->dev->name, eoe->tx_fragment_number, + last_fragment ? "" : "+", current_size, complete_offset, + eoe->tx_queued_frames); +#endif + +#if EOE_DEBUG_LEVEL >= 3 + EC_SLAVE_DBG(eoe->slave, 0, ""); + for (i = 0; i < current_size; i++) { + printk(KERN_CONT "%02X ", + eoe->tx_frame->skb->data[eoe->tx_offset + i]); + if ((i + 1) % 16 == 0) { + printk(KERN_CONT "\n"); + EC_SLAVE_DBG(eoe->slave, 0, ""); + } + } + printk(KERN_CONT "\n"); +#endif + + data = ec_slave_mbox_prepare_send(eoe->slave, &eoe->datagram, + EC_MBOX_TYPE_EOE, current_size + 4); + if (IS_ERR(data)) + return PTR_ERR(data); + + EC_WRITE_U8 (data, EC_EOE_FRAMETYPE_INIT_REQ); // Initiate EoE Request + EC_WRITE_U8 (data + 1, last_fragment); + EC_WRITE_U16(data + 2, ((eoe->tx_fragment_number & 0x3F) | + (complete_offset & 0x3F) << 6 | + (eoe->tx_frame_number & 0x0F) << 12)); + + memcpy(data + 4, eoe->tx_frame->skb->data + eoe->tx_offset, current_size); + eoe->queue_datagram = 1; + + eoe->tx_offset += current_size; + eoe->tx_fragment_number++; + return 0; +} + +/****************************************************************************/ + +/** Runs the EoE state machine. + */ +void ec_eoe_run(ec_eoe_t *eoe /**< EoE handler */) +{ + if (!eoe->opened) + return; + + // if the datagram was not sent, or is not yet received, skip this cycle + if (eoe->queue_datagram || eoe->datagram.state == EC_DATAGRAM_SENT) + return; + + // call state function + eoe->state(eoe); + + // update statistics + if (jiffies - eoe->rate_jiffies > HZ) { + eoe->rx_rate = eoe->rx_counter; + eoe->tx_rate = eoe->tx_counter; + eoe->rx_counter = 0; + eoe->tx_counter = 0; + eoe->rate_jiffies = jiffies; + } + + ec_datagram_output_stats(&eoe->datagram); +} + +/****************************************************************************/ + +/** Queues the datagram, if necessary. + */ +void ec_eoe_queue(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->queue_datagram) { + ec_master_queue_datagram_ext(eoe->slave->master, &eoe->datagram); + eoe->queue_datagram = 0; + } +} + +/****************************************************************************/ + +/** Returns the state of the device. + * + * \return 1 if the device is "up", 0 if it is "down" + */ +int ec_eoe_is_open(const ec_eoe_t *eoe /**< EoE handler */) +{ + return eoe->opened; +} + +/****************************************************************************/ + +/** Returns the idle state. + * + * \retval 1 The device is idle. + * \retval 0 The device is busy. + */ +int ec_eoe_is_idle(const ec_eoe_t *eoe /**< EoE handler */) +{ + return eoe->rx_idle && eoe->tx_idle; +} + +/***************************************************************************** + * STATE PROCESSING FUNCTIONS + ****************************************************************************/ + +/** State: RX_START. + * + * Starts a new receiving sequence by queueing a datagram that checks the + * slave's mailbox for a new EoE datagram. + * + * \todo Use both devices. + */ +void ec_eoe_state_rx_start(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->slave->error_flag || + !eoe->slave->master->devices[EC_DEVICE_MAIN].link_state) { + eoe->rx_idle = 1; + eoe->tx_idle = 1; + return; + } + + ec_slave_mbox_prepare_check(eoe->slave, &eoe->datagram); + eoe->queue_datagram = 1; + eoe->state = ec_eoe_state_rx_check; +} + +/****************************************************************************/ + +/** State: RX_CHECK. + * + * Processes the checking datagram sent in RX_START and issues a receive + * datagram, if new data is available. + */ +void ec_eoe_state_rx_check(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->datagram.state != EC_DATAGRAM_RECEIVED) { + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Failed to receive mbox" + " check datagram for %s.\n", eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + if (!ec_slave_mbox_check(&eoe->datagram)) { + eoe->rx_idle = 1; + eoe->state = ec_eoe_state_tx_start; + return; + } + + eoe->rx_idle = 0; + ec_slave_mbox_prepare_fetch(eoe->slave, &eoe->datagram); + eoe->queue_datagram = 1; + eoe->state = ec_eoe_state_rx_fetch; +} + +/****************************************************************************/ + +/** State: RX_FETCH. + * + * Checks if the requested data of RX_CHECK was received and processes the EoE + * datagram. + */ +void ec_eoe_state_rx_fetch(ec_eoe_t *eoe /**< EoE handler */) +{ + size_t rec_size, data_size; + uint8_t *data, frame_type, last_fragment, time_appended, mbox_prot; + uint8_t fragment_offset, fragment_number; +#if EOE_DEBUG_LEVEL >= 2 + uint8_t frame_number; +#endif + off_t offset; +#if EOE_DEBUG_LEVEL >= 3 + unsigned int i; +#endif + + if (eoe->datagram.state != EC_DATAGRAM_RECEIVED) { + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Failed to receive mbox" + " fetch datagram for %s.\n", eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + data = ec_slave_mbox_fetch(eoe->slave, &eoe->datagram, + &mbox_prot, &rec_size); + if (IS_ERR(data)) { + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Invalid mailbox response for %s.\n", + eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_EOE) { // FIXME mailbox handler necessary + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Other mailbox protocol response for %s.\n", + eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + + frame_type = EC_READ_U16(data) & 0x000F; + + if (frame_type != EC_EOE_FRAMETYPE_INIT_REQ) { // EoE Fragment Data +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "%s: Other frame received." + " Dropping.\n", eoe->dev->name); +#endif + eoe->stats.rx_dropped++; + eoe->state = ec_eoe_state_tx_start; + return; + } + + // EoE Fragment Request received + + last_fragment = (EC_READ_U16(data) >> 8) & 0x0001; + time_appended = (EC_READ_U16(data) >> 9) & 0x0001; + fragment_number = EC_READ_U16(data + 2) & 0x003F; + fragment_offset = (EC_READ_U16(data + 2) >> 6) & 0x003F; +#if EOE_DEBUG_LEVEL >= 2 + frame_number = (EC_READ_U16(data + 2) >> 12) & 0x000F; +#endif + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s RX fragment %u%s, offset %u," + " frame %u%s, %zu octets\n", eoe->dev->name, fragment_number, + last_fragment ? "" : "+", fragment_offset, frame_number, + time_appended ? ", + timestamp" : "", + time_appended ? rec_size - 8 : rec_size - 4); +#endif + +#if EOE_DEBUG_LEVEL >= 3 + EC_SLAVE_DBG(eoe->slave, 0, ""); + for (i = 0; i < rec_size - 4; i++) { + printk(KERN_CONT "%02X ", data[i + 4]); + if ((i + 1) % 16 == 0) { + printk(KERN_CONT "\n"); + EC_SLAVE_DBG(eoe->slave, 0, ""); + } + } + printk(KERN_CONT "\n"); +#endif + + data_size = time_appended ? rec_size - 8 : rec_size - 4; + + if (!fragment_number) { + if (eoe->rx_skb) { + EC_SLAVE_WARN(eoe->slave, "EoE RX freeing old socket buffer.\n"); + dev_kfree_skb(eoe->rx_skb); + } + + // new socket buffer + if (!(eoe->rx_skb = dev_alloc_skb(fragment_offset * 32))) { + if (printk_ratelimit()) + EC_SLAVE_WARN(eoe->slave, "EoE RX low on mem," + " frame dropped.\n"); + eoe->stats.rx_dropped++; + eoe->state = ec_eoe_state_tx_start; + return; + } + + eoe->rx_skb_offset = 0; + eoe->rx_skb_size = fragment_offset * 32; + eoe->rx_expected_fragment = 0; + } + else { + if (!eoe->rx_skb) { + eoe->stats.rx_dropped++; + eoe->state = ec_eoe_state_tx_start; + return; + } + + offset = fragment_offset * 32; + if (offset != eoe->rx_skb_offset || + offset + data_size > eoe->rx_skb_size || + fragment_number != eoe->rx_expected_fragment) { + dev_kfree_skb(eoe->rx_skb); + eoe->rx_skb = NULL; + eoe->stats.rx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Fragmenting error at %s.\n", + eoe->dev->name); +#endif + eoe->state = ec_eoe_state_tx_start; + return; + } + } + + // copy fragment into socket buffer + memcpy(skb_put(eoe->rx_skb, data_size), data + 4, data_size); + eoe->rx_skb_offset += data_size; + + if (last_fragment) { + // update statistics + eoe->stats.rx_packets++; + eoe->stats.rx_bytes += eoe->rx_skb->len; + eoe->rx_counter += eoe->rx_skb->len; + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s RX frame completed" + " with %u octets.\n", eoe->dev->name, eoe->rx_skb->len); +#endif + + // pass socket buffer to network stack + eoe->rx_skb->dev = eoe->dev; + eoe->rx_skb->protocol = eth_type_trans(eoe->rx_skb, eoe->dev); + eoe->rx_skb->ip_summed = CHECKSUM_UNNECESSARY; + if (netif_rx(eoe->rx_skb)) { + EC_SLAVE_WARN(eoe->slave, "EoE RX netif_rx failed.\n"); + } + eoe->rx_skb = NULL; + + eoe->state = ec_eoe_state_tx_start; + } + else { + eoe->rx_expected_fragment++; +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s RX expecting fragment %u\n", + eoe->dev->name, eoe->rx_expected_fragment); +#endif + eoe->state = ec_eoe_state_rx_start; + } +} + +/****************************************************************************/ + +/** State: TX START. + * + * Starts a new transmit sequence. If no data is available, a new receive + * sequence is started instead. + * + * \todo Use both devices. + */ +void ec_eoe_state_tx_start(ec_eoe_t *eoe /**< EoE handler */) +{ +#if EOE_DEBUG_LEVEL >= 2 + unsigned int wakeup = 0; +#endif + + if (eoe->slave->error_flag || + !eoe->slave->master->devices[EC_DEVICE_MAIN].link_state) { + eoe->rx_idle = 1; + eoe->tx_idle = 1; + return; + } + + netif_tx_lock_bh(eoe->dev); + + if (!eoe->tx_queued_frames || list_empty(&eoe->tx_queue)) { + netif_tx_unlock_bh(eoe->dev); + eoe->tx_idle = 1; + // no data available. + // start a new receive immediately. + ec_eoe_state_rx_start(eoe); + return; + } + + // take the first frame out of the queue + eoe->tx_frame = list_entry(eoe->tx_queue.next, ec_eoe_frame_t, queue); + list_del(&eoe->tx_frame->queue); + if (!eoe->tx_queue_active && + eoe->tx_queued_frames == eoe->tx_queue_size / 2) { + netif_wake_queue(eoe->dev); + eoe->tx_queue_active = 1; +#if EOE_DEBUG_LEVEL >= 2 + wakeup = 1; +#endif + } + + eoe->tx_queued_frames--; + netif_tx_unlock_bh(eoe->dev); + + eoe->tx_idle = 0; + + eoe->tx_frame_number++; + eoe->tx_frame_number %= 16; + eoe->tx_fragment_number = 0; + eoe->tx_offset = 0; + + if (ec_eoe_send(eoe)) { + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + eoe->tx_frame = NULL; + eoe->stats.tx_errors++; + eoe->state = ec_eoe_state_rx_start; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Send error at %s.\n", eoe->dev->name); +#endif + return; + } + +#if EOE_DEBUG_LEVEL >= 2 + if (wakeup) + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s waking up TX queue...\n", + eoe->dev->name); +#endif + + eoe->tries = EC_EOE_TRIES; + eoe->state = ec_eoe_state_tx_sent; +} + +/****************************************************************************/ + +/** State: TX SENT. + * + * Checks is the previous transmit datagram succeded and sends the next + * fragment, if necessary. + */ +void ec_eoe_state_tx_sent(ec_eoe_t *eoe /**< EoE handler */) +{ + if (eoe->datagram.state != EC_DATAGRAM_RECEIVED) { + if (eoe->tries) { + eoe->tries--; // try again + eoe->queue_datagram = 1; + } else { + eoe->stats.tx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Failed to receive send" + " datagram for %s after %u tries.\n", + eoe->dev->name, EC_EOE_TRIES); +#endif + eoe->state = ec_eoe_state_rx_start; + } + return; + } + + if (eoe->datagram.working_counter != 1) { + if (eoe->tries) { + eoe->tries--; // try again + eoe->queue_datagram = 1; + } else { + eoe->stats.tx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "No sending response" + " for %s after %u tries.\n", + eoe->dev->name, EC_EOE_TRIES); +#endif + eoe->state = ec_eoe_state_rx_start; + } + return; + } + + // frame completely sent + if (eoe->tx_offset >= eoe->tx_frame->skb->len) { + eoe->stats.tx_packets++; + eoe->stats.tx_bytes += eoe->tx_frame->skb->len; + eoe->tx_counter += eoe->tx_frame->skb->len; + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + eoe->tx_frame = NULL; + eoe->state = ec_eoe_state_rx_start; + } + else { // send next fragment + if (ec_eoe_send(eoe)) { + dev_kfree_skb(eoe->tx_frame->skb); + kfree(eoe->tx_frame); + eoe->tx_frame = NULL; + eoe->stats.tx_errors++; +#if EOE_DEBUG_LEVEL >= 1 + EC_SLAVE_WARN(eoe->slave, "Send error at %s.\n", eoe->dev->name); +#endif + eoe->state = ec_eoe_state_rx_start; + } + } +} + +/***************************************************************************** + * NET_DEVICE functions + ****************************************************************************/ + +/** Opens the virtual network device. + * + * \return Always zero (success). + */ +int ec_eoedev_open(struct net_device *dev /**< EoE net_device */) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + ec_eoe_flush(eoe); + eoe->opened = 1; + eoe->rx_idle = 0; + eoe->tx_idle = 0; + netif_start_queue(dev); + eoe->tx_queue_active = 1; +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "%s opened.\n", dev->name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Stops the virtual network device. + * + * \return Always zero (success). + */ +int ec_eoedev_stop(struct net_device *dev /**< EoE net_device */) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + netif_stop_queue(dev); + eoe->rx_idle = 1; + eoe->tx_idle = 1; + eoe->tx_queue_active = 0; + eoe->opened = 0; + ec_eoe_flush(eoe); +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "%s stopped.\n", dev->name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Transmits data via the virtual network device. + * + * \return Zero on success, non-zero on failure. + */ +int ec_eoedev_tx(struct sk_buff *skb, /**< transmit socket buffer */ + struct net_device *dev /**< EoE net_device */ + ) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + ec_eoe_frame_t *frame; + +#if 0 + if (skb->len > eoe->slave->configured_tx_mailbox_size - 10) { + EC_SLAVE_WARN(eoe->slave, "EoE TX frame (%u octets)" + " exceeds MTU. dropping.\n", skb->len); + dev_kfree_skb(skb); + eoe->stats.tx_dropped++; + return 0; + } +#endif + + WARN_ON_ONCE(skb_get_queue_mapping(skb) != 0); + lockdep_assert_held(&netdev_get_tx_queue(dev, 0)->_xmit_lock); + + if (!(frame = + (ec_eoe_frame_t *) kmalloc(sizeof(ec_eoe_frame_t), GFP_ATOMIC))) { + if (printk_ratelimit()) + EC_SLAVE_WARN(eoe->slave, "EoE TX: low on mem. frame dropped.\n"); + return 1; + } + + frame->skb = skb; + + list_add_tail(&frame->queue, &eoe->tx_queue); + eoe->tx_queued_frames++; + if (eoe->tx_queued_frames == eoe->tx_queue_size) { + netif_stop_queue(dev); + eoe->tx_queue_active = 0; + } + +#if EOE_DEBUG_LEVEL >= 2 + EC_SLAVE_DBG(eoe->slave, 0, "EoE %s TX queued frame" + " with %u octets (%u frames queued).\n", + eoe->dev->name, skb->len, eoe->tx_queued_frames); + if (!eoe->tx_queue_active) + EC_SLAVE_WARN(eoe->slave, "EoE TX queue is now full.\n"); +#endif + + return 0; +} + +/****************************************************************************/ + +/** Gets statistics about the virtual network device. + * + * \return Statistics. + */ +struct net_device_stats *ec_eoedev_stats( + struct net_device *dev /**< EoE net_device */ + ) +{ + ec_eoe_t *eoe = *((ec_eoe_t **) netdev_priv(dev)); + return &eoe->stats; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/ethernet.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/ethernet.h @@ -0,0 +1,122 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Ethernet over EtherCAT (EoE) +*/ + +/****************************************************************************/ + +#ifndef __EC_ETHERNET_H__ +#define __EC_ETHERNET_H__ + +#include +#include + +#include "globals.h" +#include "slave.h" +#include "datagram.h" + +/****************************************************************************/ + +/** EoE frame types. + */ +enum { + EC_EOE_FRAMETYPE_INIT_REQ = 0x00, /** Initiate EoE Request. */ + EC_EOE_FRAMETYPE_SET_IP_REQ = 0x02, /** Set IP Parameter Request. */ + EC_EOE_FRAMETYPE_SET_IP_RES = 0x03, /** Set IP Parameter Response. */ + EC_EOE_FRAMETYPE_FILT_REQ = 0x04, /** Set Address Filter Request. */ + EC_EOE_FRAMETYPE_FILT_RES = 0x05, /** Set Address Filter Response. */ +}; + +/*****************************************************************************/ + +/** + Queued frame structure. +*/ + +typedef struct +{ + struct list_head queue; /**< list item */ + struct sk_buff *skb; /**< socket buffer */ +} +ec_eoe_frame_t; + +/****************************************************************************/ + +typedef struct ec_eoe ec_eoe_t; /**< \see ec_eoe */ + +/** + Ethernet over EtherCAT (EoE) handler. + The master creates one of these objects for each slave that supports the + EoE protocol. +*/ + +struct ec_eoe +{ + struct list_head list; /**< list item */ + ec_slave_t *slave; /**< pointer to the corresponding slave */ + ec_datagram_t datagram; /**< datagram */ + unsigned int queue_datagram; /**< the datagram is ready for queuing */ + void (*state)(ec_eoe_t *); /**< state function for the state machine */ + struct net_device *dev; /**< net_device for virtual ethernet device */ + struct net_device_stats stats; /**< device statistics */ + unsigned int opened; /**< net_device is opened */ + unsigned long rate_jiffies; /**< time of last rate output */ + + struct sk_buff *rx_skb; /**< current rx socket buffer */ + off_t rx_skb_offset; /**< current write pointer in the socket buffer */ + size_t rx_skb_size; /**< size of the allocated socket buffer memory */ + uint8_t rx_expected_fragment; /**< next expected fragment number */ + uint32_t rx_counter; /**< octets received during last second */ + uint32_t rx_rate; /**< receive rate (bps) */ + unsigned int rx_idle; /**< Idle flag. */ + + struct list_head tx_queue; /**< queue for frames to send */ + unsigned int tx_queue_size; /**< Transmit queue size. */ + unsigned int tx_queue_active; /**< kernel netif queue started */ + unsigned int tx_queued_frames; /**< number of frames in the queue */ + ec_eoe_frame_t *tx_frame; /**< current TX frame */ + uint8_t tx_frame_number; /**< number of the transmitted frame */ + uint8_t tx_fragment_number; /**< number of the fragment */ + size_t tx_offset; /**< number of octets sent */ + uint32_t tx_counter; /**< octets transmitted during last second */ + uint32_t tx_rate; /**< transmit rate (bps) */ + unsigned int tx_idle; /**< Idle flag. */ + + unsigned int tries; /**< Tries. */ +}; + +/****************************************************************************/ + +int ec_eoe_init(ec_eoe_t *, ec_slave_t *); +void ec_eoe_clear(ec_eoe_t *); +void ec_eoe_run(ec_eoe_t *); +void ec_eoe_queue(ec_eoe_t *); +int ec_eoe_is_open(const ec_eoe_t *); +int ec_eoe_is_idle(const ec_eoe_t *); + +/****************************************************************************/ + +#endif + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/flag.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/flag.c @@ -0,0 +1,69 @@ +/***************************************************************************** + * + * Copyright (C) 2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Slave Configuration Feature Flag. + */ + +/****************************************************************************/ + +#include + +#include "flag.h" + +/****************************************************************************/ + +/** SDO request constructor. + */ +int ec_flag_init( + ec_flag_t *flag, /**< Feature flag. */ + const char *key, /**< Feature key. */ + int32_t value /**< Feature value. */ + ) +{ + if (!key || strlen(key) == 0) { + return -EINVAL; + } + + if (!(flag->key = (uint8_t *) kmalloc(strlen(key) + 1, GFP_KERNEL))) { + return -ENOMEM; + } + + strcpy(flag->key, key); // no strncpy, buffer is alloc'ed with strlen + flag->value = value; + return 0; +} + +/****************************************************************************/ + +/** SDO request destructor. + */ +void ec_flag_clear( + ec_flag_t *flag /**< Feature flag. */ + ) +{ + if (flag->key) { + kfree(flag->key); + flag->key = NULL; + } +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/flag.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/flag.h @@ -0,0 +1,51 @@ +/***************************************************************************** + * + * Copyright (C) 2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT Slave Configuration Feature Flag. +*/ + +/****************************************************************************/ + +#ifndef __EC_FLAG_H__ +#define __EC_FLAG_H__ + +#include + +/****************************************************************************/ + +/** Slave configutation feature flag. + */ +typedef struct { + struct list_head list; /**< List item. */ + char *key; /**< Flag key (null-terminated ASCII string. */ + int32_t value; /**< Flag value (meaning depends on key). */ +} ec_flag_t; + +/****************************************************************************/ + +int ec_flag_init(ec_flag_t *, const char *, int32_t); +void ec_flag_clear(ec_flag_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fmmu_config.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fmmu_config.c @@ -0,0 +1,91 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT FMMU configuration methods. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "slave_config.h" +#include "master.h" + +#include "fmmu_config.h" + +/****************************************************************************/ + +/** FMMU configuration constructor. + * + * Inits an FMMU configuration, sets the logical start address and adds the + * process data size for the mapped PDOs of the given direction to the domain + * data size. + */ +void ec_fmmu_config_init( + ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */ + ec_slave_config_t *sc, /**< EtherCAT slave configuration. */ + ec_domain_t *domain, /**< EtherCAT domain. */ + uint8_t sync_index, /**< Sync manager index to use. */ + ec_direction_t dir /**< PDO direction. */ + ) +{ + INIT_LIST_HEAD(&fmmu->list); + fmmu->sc = sc; + fmmu->sync_index = sync_index; + fmmu->dir = dir; + + fmmu->logical_start_address = domain->data_size; + fmmu->data_size = ec_pdo_list_total_size( + &sc->sync_configs[sync_index].pdos); + + ec_domain_add_fmmu_config(domain, fmmu); +} + +/****************************************************************************/ + +/** Initializes an FMMU configuration page. + * + * The referenced memory (\a data) must be at least EC_FMMU_PAGE_SIZE bytes. + */ +void ec_fmmu_config_page( + const ec_fmmu_config_t *fmmu, /**< EtherCAT FMMU configuration. */ + const ec_sync_t *sync, /**< Sync manager. */ + uint8_t *data /**> Configuration page memory. */ + ) +{ + EC_CONFIG_DBG(fmmu->sc, 1, "FMMU: LogAddr 0x%08X, Size %3u," + " PhysAddr 0x%04X, SM%u, Dir %s\n", + fmmu->logical_start_address, fmmu->data_size, + sync->physical_start_address, fmmu->sync_index, + fmmu->dir == EC_DIR_INPUT ? "in" : "out"); + + EC_WRITE_U32(data, fmmu->logical_start_address); + EC_WRITE_U16(data + 4, fmmu->data_size); // size of fmmu + EC_WRITE_U8 (data + 6, 0x00); // logical start bit + EC_WRITE_U8 (data + 7, 0x07); // logical end bit + EC_WRITE_U16(data + 8, sync->physical_start_address); + EC_WRITE_U8 (data + 10, 0x00); // physical start bit + EC_WRITE_U8 (data + 11, fmmu->dir == EC_DIR_INPUT ? 0x01 : 0x02); + EC_WRITE_U16(data + 12, 0x0001); // enable + EC_WRITE_U16(data + 14, 0x0000); // reserved +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fmmu_config.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fmmu_config.h @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT FMMU configuration structure. + */ + +/****************************************************************************/ + +#ifndef __EC_FMMU_CONFIG_H__ +#define __EC_FMMU_CONFIG_H__ + +#include "globals.h" +#include "sync.h" + +/****************************************************************************/ + +/** FMMU configuration. + */ +typedef struct { + struct list_head list; /**< List node used by domain. */ + const ec_slave_config_t *sc; /**< EtherCAT slave config. */ + const ec_domain_t *domain; /**< Domain. */ + uint8_t sync_index; /**< Index of sync manager to use. */ + ec_direction_t dir; /**< FMMU direction. */ + uint32_t logical_start_address; /**< Logical start address. */ + unsigned int data_size; /**< Covered PDO size. */ +} ec_fmmu_config_t; + +/****************************************************************************/ + +void ec_fmmu_config_init(ec_fmmu_config_t *, ec_slave_config_t *, + ec_domain_t *, uint8_t, ec_direction_t); + +void ec_fmmu_config_page(const ec_fmmu_config_t *, const ec_sync_t *, + uint8_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/foe.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/foe.h @@ -0,0 +1,54 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * FoE defines. + */ + +#ifndef __FOE_H__ +#define __FOE_H__ + +/****************************************************************************/ + +/** FoE error enumeration type. + */ +typedef enum { + FOE_BUSY = 0, /**< Busy. */ + FOE_READY = 1, /**< Ready. */ + FOE_IDLE = 2, /**< Idle. */ + FOE_WC_ERROR = 3, /**< Working counter error. */ + FOE_RECEIVE_ERROR = 4, /**< Receive error. */ + FOE_PROT_ERROR = 5, /**< Protocol error. */ + FOE_NODATA_ERROR = 6, /**< No data error. */ + FOE_PACKETNO_ERROR = 7, /**< Packet number error. */ + FOE_OPCODE_ERROR = 8, /**< OpCode error. */ + FOE_TIMEOUT_ERROR = 9, /**< Timeout error. */ + FOE_SEND_RX_DATA_ERROR = 10, /**< Error sending received data. */ + FOE_RX_DATA_ACK_ERROR = 11, /**< Error acknowledging received data. */ + FOE_ACK_ERROR = 12, /**< Acknowledge error. */ + FOE_MBOX_FETCH_ERROR = 13, /**< Error fetching data from mailbox. */ + FOE_READ_NODATA_ERROR = 14, /**< No data while reading. */ + FOE_MBOX_PROT_ERROR = 15, /**< Mailbox protocol error. */ +} ec_foe_error_t; + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/foe_request.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/foe_request.c @@ -0,0 +1,195 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * Copyright (C) 2020 Florian Pose, IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * File-over-EtherCAT request functions. + */ + +/****************************************************************************/ + +#include +#include +#include +#include + +#include "foe_request.h" +#include "foe.h" + +/****************************************************************************/ + +/** Default timeout in ms to wait for FoE transfer responses. + */ +#define EC_FOE_REQUEST_RESPONSE_TIMEOUT 3000 + +/****************************************************************************/ + +// prototypes for private methods +void ec_foe_request_clear_data(ec_foe_request_t *); + +/****************************************************************************/ + +/** FoE request constructor. + */ +void ec_foe_request_init( + ec_foe_request_t *req, /**< FoE request. */ + uint8_t* file_name /** filename */) +{ + INIT_LIST_HEAD(&req->list); + req->buffer = NULL; + req->file_name = file_name; + req->buffer_size = 0; + req->data_size = 0; + req->dir = EC_DIR_INVALID; + req->issue_timeout = 0; // no timeout + req->response_timeout = EC_FOE_REQUEST_RESPONSE_TIMEOUT; + req->state = EC_INT_REQUEST_INIT; + req->result = FOE_BUSY; + req->error_code = 0x00000000; +} + +/****************************************************************************/ + +/** FoE request destructor. + */ +void ec_foe_request_clear( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + ec_foe_request_clear_data(req); +} + +/****************************************************************************/ + +/** FoE request destructor. + */ +void ec_foe_request_clear_data( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + if (req->buffer) { + vfree(req->buffer); + req->buffer = NULL; + } + + req->buffer_size = 0; + req->data_size = 0; +} + +/****************************************************************************/ + +/** Pre-allocates the data memory. + * + * If the internal \a buffer_size is already bigger than \a size, nothing is + * done. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_request_alloc( + ec_foe_request_t *req, /**< FoE request. */ + size_t size /**< Data size to allocate. */ + ) +{ + if (size <= req->buffer_size) { + return 0; + } + + ec_foe_request_clear_data(req); + + if (!(req->buffer = (uint8_t *) vmalloc(size))) { + EC_ERR("Failed to allocate %zu bytes of FoE memory.\n", size); + return -ENOMEM; + } + + req->buffer_size = size; + req->data_size = 0; + return 0; +} + +/****************************************************************************/ + +/** Copies FoE data from an external source. + * + * If the \a buffer_size is to small, new memory is allocated. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_request_copy_data( + ec_foe_request_t *req, /**< FoE request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + int ret; + + ret = ec_foe_request_alloc(req, size); + if (ret) { + return ret; + } + + memcpy(req->buffer, source, size); + req->data_size = size; + return 0; +} + +/****************************************************************************/ + +/** Checks, if the timeout was exceeded. + * + * \return non-zero if the timeout was exceeded, else zero. + */ +int ec_foe_request_timed_out( + const ec_foe_request_t *req /**< FoE request. */ + ) +{ + return req->issue_timeout + && jiffies - req->jiffies_start > HZ * req->issue_timeout / 1000; +} + +/****************************************************************************/ + +/** Prepares a read request (slave to master). + */ +void ec_foe_request_read( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + req->dir = EC_DIR_INPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->result = FOE_BUSY; + req->jiffies_start = jiffies; +} + +/****************************************************************************/ + +/** Prepares a write request (master to slave). + */ +void ec_foe_request_write( + ec_foe_request_t *req /**< FoE request. */ + ) +{ + req->dir = EC_DIR_OUTPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->result = FOE_BUSY; + req->jiffies_start = jiffies; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/foe_request.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/foe_request.h @@ -0,0 +1,78 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT FoE request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_FOE_REQUEST_H__ +#define __EC_FOE_REQUEST_H__ + +#include + +#include "../include/ecrt.h" + +#include "globals.h" + +/****************************************************************************/ + +/** FoE request. + */ +typedef struct { + struct list_head list; /**< List item. */ + uint8_t *buffer; /**< Pointer to FoE data. */ + size_t buffer_size; /**< Size of FoE data memory. */ + size_t data_size; /**< Size of FoE data. */ + + uint32_t issue_timeout; /**< Maximum time in ms, the processing of the + request may take. */ + uint32_t response_timeout; /**< Maximum time in ms, the transfer is + retried, if the slave does not respond. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means downloading to + the slave, EC_DIR_INPUT means uploading from the + slave. */ + ec_internal_request_state_t state; /**< FoE request state. */ + unsigned long jiffies_start; /**< Jiffies, when the request was issued. */ + unsigned long jiffies_sent; /**< Jiffies, when the upload/download + request was sent. */ + uint8_t *file_name; /**< Pointer to the filename. */ + uint32_t result; /**< FoE request abort code. Zero on success. */ + uint32_t error_code; /**< Error code from an FoE Error Request. */ +} ec_foe_request_t; + +/****************************************************************************/ + +void ec_foe_request_init(ec_foe_request_t *, uint8_t *file_name); +void ec_foe_request_clear(ec_foe_request_t *); + +int ec_foe_request_alloc(ec_foe_request_t *, size_t); +int ec_foe_request_copy_data(ec_foe_request_t *, const uint8_t *, size_t); +int ec_foe_request_timed_out(const ec_foe_request_t *); + +void ec_foe_request_write(ec_foe_request_t *); +void ec_foe_request_read(ec_foe_request_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_change.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_change.c @@ -0,0 +1,615 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT state change FSM. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "fsm_change.h" +#include "slave_config.h" + +/****************************************************************************/ + +unsigned int ec_fsm_change_timeout_ms(const ec_fsm_change_t *); + +void ec_fsm_change_state_start(ec_fsm_change_t *); +void ec_fsm_change_state_check(ec_fsm_change_t *); +void ec_fsm_change_state_status(ec_fsm_change_t *); +void ec_fsm_change_state_start_code(ec_fsm_change_t *); +void ec_fsm_change_state_code(ec_fsm_change_t *); +void ec_fsm_change_state_ack(ec_fsm_change_t *); +void ec_fsm_change_state_check_ack(ec_fsm_change_t *); +void ec_fsm_change_state_end(ec_fsm_change_t *); +void ec_fsm_change_state_error(ec_fsm_change_t *); + +/****************************************************************************/ + +/** + Constructor. +*/ + +void ec_fsm_change_init(ec_fsm_change_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + fsm->state = NULL; + fsm->datagram = datagram; + fsm->spontaneous_change = 0; +} + +/****************************************************************************/ + +/** + Destructor. +*/ + +void ec_fsm_change_clear(ec_fsm_change_t *fsm /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** Get timeout in ms. + * + * For defaults see ETG2000_S_R_V1i0i15 section 5.3.6.2. + */ +unsigned int ec_fsm_change_timeout_ms( + const ec_fsm_change_t *fsm /**< finite state machine */ + ) +{ + ec_slave_state_t from = fsm->old_state; + ec_slave_state_t to = fsm->requested_state; + + /* Search for specified timeout in slave configuration */ + if (fsm->slave->config) { + unsigned int timeout_ms = + ec_slave_config_al_timeout(fsm->slave->config, from, to); + if (timeout_ms) { + return timeout_ms; + } + } + + /* No specific timeout found. Use defaults from spec. */ + + if (from == EC_SLAVE_STATE_INIT && + (to == EC_SLAVE_STATE_PREOP || to == EC_SLAVE_STATE_BOOT)) { + return 3000; // PreopTimeout + } + if ((from == EC_SLAVE_STATE_PREOP && to == EC_SLAVE_STATE_SAFEOP) || + (from == EC_SLAVE_STATE_SAFEOP && to == EC_SLAVE_STATE_OP)) { + return 10000; // SafeopOpTimeout + } + if (to == EC_SLAVE_STATE_INIT || + ((from == EC_SLAVE_STATE_OP || from == EC_SLAVE_STATE_SAFEOP) + && to == EC_SLAVE_STATE_PREOP)) { + return 5000; // BackToInitTimeout + } + if (from == EC_SLAVE_STATE_OP && to == EC_SLAVE_STATE_SAFEOP) { + return 200; // BackToSafeopTimeout + } + + return 10000; // default [ms] +} + +/****************************************************************************/ + +/** + Starts the change state machine. +*/ + +void ec_fsm_change_start(ec_fsm_change_t *fsm, /**< finite state machine */ + ec_slave_t *slave, /**< EtherCAT slave */ + ec_slave_state_t state /**< requested state */ + ) +{ + fsm->mode = EC_FSM_CHANGE_MODE_FULL; + fsm->slave = slave; + fsm->requested_state = state; + fsm->state = ec_fsm_change_state_start; +} + +/****************************************************************************/ + +/** + Starts the change state machine to only acknowlegde a slave's state. +*/ + +void ec_fsm_change_ack(ec_fsm_change_t *fsm, /**< finite state machine */ + ec_slave_t *slave /**< EtherCAT slave */ + ) +{ + fsm->mode = EC_FSM_CHANGE_MODE_ACK_ONLY; + fsm->slave = slave; + fsm->requested_state = EC_SLAVE_STATE_UNKNOWN; + fsm->state = ec_fsm_change_state_start_code; +} + +/****************************************************************************/ + +/** + Executes the current state of the state machine. + \return false, if the state machine has terminated +*/ + +int ec_fsm_change_exec(ec_fsm_change_t *fsm /**< finite state machine */) +{ + fsm->state(fsm); + + return fsm->state != ec_fsm_change_state_end + && fsm->state != ec_fsm_change_state_error; +} + +/****************************************************************************/ + +/** + Returns, if the state machine terminated with success. + \return non-zero if successful. +*/ + +int ec_fsm_change_success(ec_fsm_change_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_change_state_end; +} + +/***************************************************************************** + * state change state machine + ****************************************************************************/ + +/** + Change state: START. +*/ + +void ec_fsm_change_state_start(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + fsm->take_time = 1; + fsm->old_state = fsm->slave->current_state; + + // write new state to slave + ec_datagram_fpwr(datagram, slave->station_address, 0x0120, 2); + EC_WRITE_U16(datagram->data, fsm->requested_state); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_check; +} + +/****************************************************************************/ + +/** + Change state: CHECK. +*/ + +void ec_fsm_change_state_check(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + if (datagram->working_counter == 0) { + if (datagram->jiffies_received - fsm->jiffies_start >= 3 * HZ) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to set state %s: ", state_str); + ec_datagram_print_wc_error(datagram); + return; + } + + // repeat writing new state to slave + ec_datagram_fpwr(datagram, slave->station_address, 0x0120, 2); + EC_WRITE_U16(datagram->data, fsm->requested_state); + fsm->retries = EC_FSM_RETRIES; + return; + } + + if (unlikely(datagram->working_counter > 1)) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to set state %s: ", state_str); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->take_time = 1; + + // read AL status from slave + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->spontaneous_change = 0; + fsm->state = ec_fsm_change_state_status; +} + +/****************************************************************************/ + +/** + Change state: STATUS. +*/ + +void ec_fsm_change_state_status(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + unsigned int timeout_ms; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state checking datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + char req_state[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, req_state, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to check state %s: ", req_state); + ec_datagram_print_wc_error(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + slave->current_state = EC_READ_U8(datagram->data); + + if (slave->current_state == fsm->requested_state) { + // state has been set successfully + fsm->state = ec_fsm_change_state_end; + return; + } + + if (slave->current_state != fsm->old_state) { // state changed + char req_state[EC_STATE_STRING_SIZE], cur_state[EC_STATE_STRING_SIZE]; + + ec_state_string(slave->current_state, cur_state, 0); + + if ((slave->current_state & 0x0F) != (fsm->old_state & 0x0F)) { + // Slave spontaneously changed its state just before the new state + // was written. Accept current state as old state and wait for + // state change + fsm->spontaneous_change = 1; + fsm->old_state = slave->current_state; + EC_SLAVE_WARN(slave, "Changed to %s in the meantime.\n", + cur_state); + goto check_again; + } + + // state change error + + slave->error_flag = 1; + ec_state_string(fsm->requested_state, req_state, 0); + + EC_SLAVE_ERR(slave, "Failed to set %s state, slave refused state" + " change (%s).\n", req_state, cur_state); + + ec_fsm_change_state_start_code(fsm); + return; + } + + // still old state + + timeout_ms = ec_fsm_change_timeout_ms(fsm); + if (datagram->jiffies_received - fsm->jiffies_start >= + timeout_ms * HZ / 1000) { + // timeout while checking + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(fsm->requested_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Timeout after %u ms while setting state %s.\n", + timeout_ms, state_str); + return; + } + + check_again: + // no timeout yet. check again + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; +} + +/****************************************************************************/ + +/** Enter reading AL status code. + */ +void ec_fsm_change_state_start_code( + ec_fsm_change_t *fsm /**< finite state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + // fetch AL status error code + ec_datagram_fprd(datagram, slave->station_address, 0x0134, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_code; +} + +/****************************************************************************/ + +/** + Application layer status messages. +*/ + +const ec_code_msg_t al_status_messages[] = { + {0x0000, "No error"}, + {0x0001, "Unspecified error"}, + {0x0002, "No Memory"}, + {0x0011, "Invalid requested state change"}, + {0x0012, "Unknown requested state"}, + {0x0013, "Bootstrap not supported"}, + {0x0014, "No valid firmware"}, + {0x0015, "Invalid mailbox configuration"}, + {0x0016, "Invalid mailbox configuration"}, + {0x0017, "Invalid sync manager configuration"}, + {0x0018, "No valid inputs available"}, + {0x0019, "No valid outputs"}, + {0x001A, "Synchronization error"}, + {0x001B, "Sync manager watchdog"}, + {0x001C, "Invalid sync manager types"}, + {0x001D, "Invalid output configuration"}, + {0x001E, "Invalid input configuration"}, + {0x001F, "Invalid watchdog configuration"}, + {0x0020, "Slave needs cold start"}, + {0x0021, "Slave needs INIT"}, + {0x0022, "Slave needs PREOP"}, + {0x0023, "Slave needs SAFEOP"}, + {0x0024, "Invalid Input Mapping"}, + {0x0025, "Invalid Output Mapping"}, + {0x0026, "Inconsistent Settings"}, + {0x0027, "Freerun not supported"}, + {0x0028, "Synchronization not supported"}, + {0x0029, "Freerun needs 3 Buffer Mode"}, + {0x002A, "Background Watchdog"}, + {0x002B, "No Valid Inputs and Outputs"}, + {0x002C, "Fatal Sync Error"}, + {0x002D, "No Sync Error"}, + {0x0030, "Invalid DC SYNCH configuration"}, + {0x0031, "Invalid DC latch configuration"}, + {0x0032, "PLL error"}, + {0x0033, "DC Sync IO Error"}, + {0x0034, "DC Sync Timeout Error"}, + {0x0035, "DC Invalid Sync Cycle Time"}, + {0x0036, "DC Sync0 Cycle Time"}, + {0x0037, "DC Sync1 Cycle Time"}, + {0x0041, "MBX_AOE"}, + {0x0042, "MBX_EOE"}, + {0x0043, "MBX_COE"}, + {0x0044, "MBX_FOE"}, + {0x0045, "MBX_SOE"}, + {0x004F, "MBX_VOE"}, + {0x0050, "EEPROM No Access"}, + {0x0051, "EEPROM Error"}, + {0x0060, "Slave Restarted Locally"}, + {0xffff} +}; + + +/****************************************************************************/ + +/** + Change state: CODE. +*/ + +void ec_fsm_change_state_code(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + uint32_t code; + const ec_code_msg_t *al_msg; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to receive" + " AL status code datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(fsm->slave, "Reception of AL status code" + " datagram failed: "); + ec_datagram_print_wc_error(datagram); + } else { + code = EC_READ_U16(datagram->data); + for (al_msg = al_status_messages; al_msg->code != 0xffff; al_msg++) { + if (al_msg->code != code) { + continue; + } + + EC_SLAVE_ERR(fsm->slave, "AL status message 0x%04X: \"%s\".\n", + al_msg->code, al_msg->message); + break; + } + if (al_msg->code == 0xffff) { /* not found in our list. */ + EC_SLAVE_ERR(fsm->slave, "Unknown AL status code 0x%04X.\n", + code); + } + } + + // acknowledge "old" slave state + ec_datagram_fpwr(datagram, fsm->slave->station_address, 0x0120, 2); + EC_WRITE_U16(datagram->data, fsm->slave->current_state); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_ack; +} + +/****************************************************************************/ + +/** + Change state: ACK. +*/ + +void ec_fsm_change_state_ack(ec_fsm_change_t *fsm /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state ack datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Reception of state ack datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->take_time = 1; + + // read new AL status + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_change_state_check_ack; +} + +/****************************************************************************/ + +/** + Change state: CHECK ACK. +*/ + +void ec_fsm_change_state_check_ack(ec_fsm_change_t *fsm + /**< finite state machine */) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + unsigned int timeout_ms; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Failed to receive state ack check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Reception of state ack check datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + slave->current_state = EC_READ_U8(datagram->data); + + if (!(slave->current_state & EC_SLAVE_STATE_ACK_ERR)) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, state_str, 0); + if (fsm->mode == EC_FSM_CHANGE_MODE_FULL) { + fsm->state = ec_fsm_change_state_error; + } + else { // EC_FSM_CHANGE_MODE_ACK_ONLY + fsm->state = ec_fsm_change_state_end; + } + EC_SLAVE_INFO(slave, "Acknowledged state %s.\n", state_str); + return; + } + + timeout_ms = ec_fsm_change_timeout_ms(fsm); + if (datagram->jiffies_received - fsm->jiffies_start >= + timeout_ms * HZ / 1000) { + // timeout while checking + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, state_str, 0); + fsm->state = ec_fsm_change_state_error; + EC_SLAVE_ERR(slave, "Timeout after %u ms while acknowledging" + " state %s.\n", timeout_ms, state_str); + return; + } + + // reread new AL status + ec_datagram_fprd(datagram, slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; +} + +/****************************************************************************/ + +/** + State: ERROR. +*/ + +void ec_fsm_change_state_error(ec_fsm_change_t *fsm + /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** + State: END. +*/ + +void ec_fsm_change_state_end(ec_fsm_change_t *fsm + /**< finite state machine */) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_change.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_change.h @@ -0,0 +1,84 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT state change FSM. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_CHANGE_H__ +#define __EC_FSM_CHANGE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" + +/****************************************************************************/ + +/** + Mode of the change state machine. +*/ + +typedef enum { + EC_FSM_CHANGE_MODE_FULL, /**< full state change */ + EC_FSM_CHANGE_MODE_ACK_ONLY /**< only state acknowledgement */ +} +ec_fsm_change_mode_t; + +/****************************************************************************/ + +typedef struct ec_fsm_change ec_fsm_change_t; /**< \see ec_fsm_change */ + +/** + EtherCAT state change FSM. +*/ + +struct ec_fsm_change +{ + ec_slave_t *slave; /**< slave the FSM runs on */ + ec_datagram_t *datagram; /**< datagram used in the state machine */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_change_t *); /**< slave state change state function */ + ec_fsm_change_mode_t mode; /**< full state change, or ack only. */ + ec_slave_state_t requested_state; /**< input: state */ + ec_slave_state_t old_state; /**< prior slave state */ + unsigned long jiffies_start; /**< change timer */ + uint8_t take_time; /**< take sending timestamp */ + uint8_t spontaneous_change; /**< spontaneous state change detected */ +}; + +/****************************************************************************/ + +void ec_fsm_change_init(ec_fsm_change_t *, ec_datagram_t *); +void ec_fsm_change_clear(ec_fsm_change_t *); + +void ec_fsm_change_start(ec_fsm_change_t *, ec_slave_t *, ec_slave_state_t); +void ec_fsm_change_ack(ec_fsm_change_t *, ec_slave_t *); + +int ec_fsm_change_exec(ec_fsm_change_t *); +int ec_fsm_change_success(ec_fsm_change_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_coe.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_coe.c @@ -0,0 +1,2537 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT CoE state machines. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_coe.h" +#include "slave_config.h" + +/****************************************************************************/ + +/** Maximum time in ms to wait for responses when reading out the dictionary. + */ +#define EC_FSM_COE_DICT_TIMEOUT 1000 + +/** CoE download request header size. + */ +#define EC_COE_DOWN_REQ_HEADER_SIZE 10 + +/** CoE download segment request header size. + */ +#define EC_COE_DOWN_SEG_REQ_HEADER_SIZE 3 + +/** Minimum size of download segment. + */ +#define EC_COE_DOWN_SEG_MIN_DATA_SIZE 7 + +/** Enable debug output for CoE retries. + */ +#define DEBUG_RETRIES 0 + +/** Enable warning output if transfers take too long. + */ +#define DEBUG_LONG 0 + +/****************************************************************************/ + +// prototypes for private methods +void ec_canopen_abort_msg(const ec_slave_t *, uint32_t); +int ec_fsm_coe_check_emergency(const ec_fsm_coe_t *, const uint8_t *, size_t); +int ec_fsm_coe_prepare_dict(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_dict_prepare_desc(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_dict_prepare_entry(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_prepare_down_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_prepare_segment_request(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_prepare_up(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_prepare_segment_request(ec_fsm_coe_t *, ec_datagram_t *); + +/****************************************************************************/ + +void ec_fsm_coe_dict_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_desc_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_desc_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_desc_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_entry_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_entry_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_dict_entry_response(ec_fsm_coe_t *, ec_datagram_t *); + +void ec_fsm_coe_down_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_seg_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_down_seg_response(ec_fsm_coe_t *, ec_datagram_t *); + +void ec_fsm_coe_up_start(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_response(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_seg_request(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_seg_check(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_up_seg_response(ec_fsm_coe_t *, ec_datagram_t *); + +void ec_fsm_coe_end(ec_fsm_coe_t *, ec_datagram_t *); +void ec_fsm_coe_error(ec_fsm_coe_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** SDO abort messages. + * + * The "abort SDO transfer request" supplies an abort code, which can be + * translated to clear text. This table does the mapping of the codes and + * messages. + */ +const ec_code_msg_t sdo_abort_messages[] = { + {0x05030000, "Toggle bit not changed"}, + {0x05040000, "SDO protocol timeout"}, + {0x05040001, "Client/Server command specifier not valid or unknown"}, + {0x05040005, "Out of memory"}, + {0x06010000, "Unsupported access to an object"}, + {0x06010001, "Attempt to read a write-only object"}, + {0x06010002, "Attempt to write a read-only object"}, + {0x06020000, "This object does not exist in the object directory"}, + {0x06040041, "The object cannot be mapped into the PDO"}, + {0x06040042, "The number and length of the objects to be mapped would" + " exceed the PDO length"}, + {0x06040043, "General parameter incompatibility reason"}, + {0x06040047, "Gerneral internal incompatibility in device"}, + {0x06060000, "Access failure due to a hardware error"}, + {0x06070010, "Data type does not match, length of service parameter does" + " not match"}, + {0x06070012, "Data type does not match, length of service parameter too" + " high"}, + {0x06070013, "Data type does not match, length of service parameter too" + " low"}, + {0x06090011, "Subindex does not exist"}, + {0x06090030, "Value range of parameter exceeded"}, + {0x06090031, "Value of parameter written too high"}, + {0x06090032, "Value of parameter written too low"}, + {0x06090036, "Maximum value is less than minimum value"}, + {0x08000000, "General error"}, + {0x08000020, "Data cannot be transferred or stored to the application"}, + {0x08000021, "Data cannot be transferred or stored to the application" + " because of local control"}, + {0x08000022, "Data cannot be transferred or stored to the application" + " because of the present device state"}, + {0x08000023, "Object dictionary dynamic generation fails or no object" + " dictionary is present"}, + {} +}; + +/****************************************************************************/ + +/** Outputs an SDO abort message. + */ +void ec_canopen_abort_msg( + const ec_slave_t *slave, /**< Slave. */ + uint32_t abort_code /**< Abort code to search for. */ + ) +{ + const ec_code_msg_t *abort_msg; + + for (abort_msg = sdo_abort_messages; abort_msg->code; abort_msg++) { + if (abort_msg->code == abort_code) { + EC_SLAVE_ERR(slave, "SDO abort message 0x%08X: \"%s\".\n", + abort_msg->code, abort_msg->message); + return; + } + } + + EC_SLAVE_ERR(slave, "Unknown SDO abort code 0x%08X.\n", abort_code); +} + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_coe_init( + ec_fsm_coe_t *fsm /**< Finite state machine */ + ) +{ + fsm->state = NULL; + fsm->datagram = NULL; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_coe_clear( + ec_fsm_coe_t *fsm /**< Finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** Starts reading a slaves' SDO dictionary. + */ +void ec_fsm_coe_dictionary( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_slave_t *slave /**< EtherCAT slave */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_coe_dict_start; +} + +/****************************************************************************/ + +/** Starts to transfer an SDO to/from a slave. + */ +void ec_fsm_coe_transfer( + ec_fsm_coe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_sdo_request_t *request /**< SDO request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + + if (request->dir == EC_DIR_OUTPUT) { + fsm->state = ec_fsm_coe_down_start; + } + else { + fsm->state = ec_fsm_coe_up_start; + } +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if the datagram was used, else 0. + */ +int ec_fsm_coe_exec( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_coe_end && fsm->state != ec_fsm_coe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * \return non-zero if successful. + */ +int ec_fsm_coe_success( + const ec_fsm_coe_t *fsm /**< Finite state machine */ + ) +{ + return fsm->state == ec_fsm_coe_end; +} + +/****************************************************************************/ + +/** Check if the received data are a CoE emergency request. + * + * If the check is positive, the emergency request is output. + * + * \return The data were an emergency request. + */ +int ec_fsm_coe_check_emergency( + const ec_fsm_coe_t *fsm, /**< Finite state machine */ + const uint8_t *data, /**< CoE mailbox data. */ + size_t size /**< CoE mailbox data size. */ + ) +{ + if (size < 2 || ((EC_READ_U16(data) >> 12) & 0x0F) != 0x01) + return 0; + + if (size < 10) { + EC_SLAVE_WARN(fsm->slave, "Received incomplete CoE Emergency" + " request:\n"); + ec_print_data(data, size); + return 1; + } + + { + ec_slave_config_t *sc = fsm->slave->config; + if (sc) { + ec_coe_emerg_ring_push(&sc->emerg_ring, data + 2); + } + } + + EC_SLAVE_WARN(fsm->slave, "CoE Emergency Request received:\n" + "Error code 0x%04X, Error register 0x%02X, data:\n", + EC_READ_U16(data + 2), EC_READ_U8(data + 4)); + ec_print_data(data + 5, 5); + return 1; +} + +/***************************************************************************** + * CoE dictionary state machine + ****************************************************************************/ + +/** Prepare a dictionary request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_prepare_dict( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data = ec_slave_mbox_prepare_send(slave, datagram, + EC_MBOX_TYPE_COE, 8); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x8 << 12); // SDO information + EC_WRITE_U8 (data + 2, 0x01); // Get OD List Request + EC_WRITE_U8 (data + 3, 0x00); + EC_WRITE_U16(data + 4, 0x0000); + EC_WRITE_U16(data + 6, 0x0001); // deliver all SDOs! + + fsm->state = ec_fsm_coe_dict_request; + return 0; +} + +/****************************************************************************/ + +/** CoE state: DICT START. + */ +void ec_fsm_coe_dict_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_SLAVE_ERR(slave, "Slave does not support CoE!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + if (slave->sii.has_general && !slave->sii.coe_details.enable_sdo_info) { + EC_SLAVE_ERR(slave, "Slave does not support" + " SDO information service!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_prepare_dict(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** CoE state: DICT REQUEST. + * \todo Timeout behavior + */ +void ec_fsm_coe_dict_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_prepare_dict(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE dictionary" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE dictionary request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; +} + +/****************************************************************************/ + +/** CoE state: DICT CHECK. + */ +void ec_fsm_coe_dict_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave,"Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_FSM_COE_DICT_TIMEOUT) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for" + " SDO dictionary list response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_response; +} + +/****************************************************************************/ + +/** Prepare an object description request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_dict_prepare_desc( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u8 *data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + 8); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x8 << 12); // SDO information + EC_WRITE_U8 (data + 2, 0x03); // Get object description request + EC_WRITE_U8 (data + 3, 0x00); + EC_WRITE_U16(data + 4, 0x0000); + EC_WRITE_U16(data + 6, fsm->sdo->index); // SDO index + + fsm->state = ec_fsm_coe_dict_desc_request; + return 0; +} + +/****************************************************************************/ + +/** + CoE state: DICT RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + size_t rec_size; + unsigned int sdo_count, i; + uint16_t sdo_index, fragments_left; + ec_sdo_t *sdo; + bool first_segment; + size_t index_list_offset; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE dictionary" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE dictionary response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; + return; + } + + if (rec_size < 3) { + EC_SLAVE_ERR(slave, "Received corrupted SDO dictionary response" + " (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x8 && // SDO information + (EC_READ_U8(data + 2) & 0x7F) == 0x07) { // error response + EC_SLAVE_ERR(slave, "SDO information error response!\n"); + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Incomplete SDO information" + " error response:\n"); + ec_print_data(data, rec_size); + } else { + ec_canopen_abort_msg(slave, EC_READ_U32(data + 6)); + } + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x8 || // SDO information + (EC_READ_U8 (data + 2) & 0x7F) != 0x02) { // Get OD List response + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO list response!" + " Retrying...\n"); + ec_print_data(data, rec_size); + } + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; + return; + } + + first_segment = list_empty(&slave->sdo_dictionary) ? true : false; + index_list_offset = first_segment ? 8 : 6; + + if (rec_size < index_list_offset || rec_size % 2) { + EC_SLAVE_ERR(slave, "Invalid data size %zu!\n", rec_size); + ec_print_data(data, rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + sdo_count = (rec_size - index_list_offset) / 2; + + for (i = 0; i < sdo_count; i++) { + sdo_index = EC_READ_U16(data + index_list_offset + i * 2); + if (!sdo_index) { + EC_SLAVE_DBG(slave, 1, "SDO dictionary contains index 0x0000.\n"); + continue; + } + + if (!(sdo = (ec_sdo_t *) kmalloc(sizeof(ec_sdo_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate memory for SDO!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + ec_sdo_init(sdo, slave, sdo_index); + list_add_tail(&sdo->list, &slave->sdo_dictionary); + } + + fragments_left = EC_READ_U16(data + 4); + if (fragments_left) { + EC_SLAVE_DBG(slave, 1, "SDO list fragments left: %u\n", + fragments_left); + } + + if (EC_READ_U8(data + 2) & 0x80 || fragments_left) { + // more messages waiting. check again. + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_check; + return; + } + + if (list_empty(&slave->sdo_dictionary)) { + // no SDOs in dictionary. finished. + fsm->state = ec_fsm_coe_end; // success + return; + } + + // fetch SDO descriptions + fsm->sdo = list_entry(slave->sdo_dictionary.next, ec_sdo_t, list); + + fsm->retries = EC_FSM_RETRIES; + if (ec_fsm_coe_dict_prepare_desc(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** + CoE state: DICT DESC REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_desc_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_dict_prepare_desc(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO" + " description request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO description" + " request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_check; +} + +/****************************************************************************/ + +/** + CoE state: DICT DESC CHECK. +*/ + +void ec_fsm_coe_dict_desc_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_FSM_COE_DICT_TIMEOUT) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for" + " SDO 0x%04x object description response.\n", + fsm->sdo->index); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_response; +} + +/****************************************************************************/ + +/** Prepare an entry description request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_dict_prepare_entry( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u8 *data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + 10); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x8 << 12); // SDO information + EC_WRITE_U8 (data + 2, 0x05); // Get entry description request + EC_WRITE_U8 (data + 3, 0x00); + EC_WRITE_U16(data + 4, 0x0000); + EC_WRITE_U16(data + 6, fsm->sdo->index); // SDO index + EC_WRITE_U8 (data + 8, fsm->subindex); // SDO subindex + EC_WRITE_U8 (data + 9, 0x01); // value info (access rights only) + + fsm->state = ec_fsm_coe_dict_entry_request; + return 0; +} + +/****************************************************************************/ + +/** + CoE state: DICT DESC RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_desc_response( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_t *sdo = fsm->sdo; + uint8_t *data, mbox_prot; + size_t rec_size, name_size; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO description" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO description" + " response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_check; + return; + } + + if (rec_size < 3) { + EC_SLAVE_ERR(slave, "Received corrupted SDO description response" + " (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x8 && // SDO information + (EC_READ_U8 (data + 2) & 0x7F) == 0x07) { // error response + EC_SLAVE_ERR(slave, "SDO information error response while" + " fetching SDO 0x%04X!\n", sdo->index); + ec_canopen_abort_msg(slave, EC_READ_U32(data + 6)); + fsm->state = ec_fsm_coe_error; + return; + } + + if (rec_size < 8) { + EC_SLAVE_ERR(slave, "Received corrupted SDO" + " description response (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x8 || // SDO information + (EC_READ_U8 (data + 2) & 0x7F) != 0x04 || // Object desc. response + EC_READ_U16(data + 6) != sdo->index) { // SDO index + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid object description response while" + " fetching SDO 0x%04X!\n", sdo->index); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_desc_check; + return; + } + + if (rec_size < 12) { + EC_SLAVE_ERR(slave, "Invalid data size!\n"); + ec_print_data(data, rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + sdo->max_subindex = EC_READ_U8(data + 10); + sdo->object_code = EC_READ_U8(data + 11); + + name_size = rec_size - 12; + if (name_size) { + if (!(sdo->name = kmalloc(name_size + 1, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate SDO name!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + memcpy(sdo->name, data + 12, name_size); + sdo->name[name_size] = 0; + } + + if (EC_READ_U8(data + 2) & 0x80) { + EC_SLAVE_ERR(slave, "Fragment follows (not implemented)!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + // start fetching entries + + fsm->subindex = 0; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_dict_prepare_entry(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** + CoE state: DICT ENTRY REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_entry_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_dict_prepare_entry(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO entry" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO entry request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_check; +} + +/****************************************************************************/ + +/** + CoE state: DICT ENTRY CHECK. +*/ + +void ec_fsm_coe_dict_entry_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_FSM_COE_DICT_TIMEOUT) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for" + " SDO entry 0x%04x:%x description response.\n", + fsm->sdo->index, fsm->subindex); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_response; +} + +/****************************************************************************/ + +/** + CoE state: DICT ENTRY RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_dict_entry_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_t *sdo = fsm->sdo; + uint8_t *data, mbox_prot; + size_t rec_size, data_size; + ec_sdo_entry_t *entry; + u16 word; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE SDO" + " description response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE SDO description" + " response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol" + " 0x%02X as response.\n", mbox_prot); + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_check; + return; + } + + if (rec_size < 3) { + EC_SLAVE_ERR(slave, "Received corrupted SDO entry" + " description response (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x8 && // SDO information + (EC_READ_U8 (data + 2) & 0x7F) == 0x07) { // error response + EC_SLAVE_WARN(slave, "SDO information error response while" + " fetching SDO entry 0x%04X:%02X!\n", + sdo->index, fsm->subindex); + ec_canopen_abort_msg(slave, EC_READ_U32(data + 6)); + + /* There may be gaps in the subindices, so try to continue with next + * subindex. */ + + } else { + + if (rec_size < 9) { + EC_SLAVE_ERR(slave, "Received corrupted SDO entry" + " description response (size %zu).\n", rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x8 || // SDO information + (EC_READ_U8(data + 2) & 0x7F) != 0x06 || // Entry desc. response + EC_READ_U16(data + 6) != sdo->index || // SDO index + EC_READ_U8(data + 8) != fsm->subindex) { // SDO subindex + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid entry description response" + " while fetching SDO entry 0x%04X:%02X!\n", + sdo->index, fsm->subindex); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_dict_entry_check; + return; + } + + if (rec_size < 16) { + EC_SLAVE_ERR(slave, "Invalid data size %zu!\n", rec_size); + ec_print_data(data, rec_size); + fsm->state = ec_fsm_coe_error; + return; + } + + data_size = rec_size - 16; + + if (!(entry = (ec_sdo_entry_t *) + kmalloc(sizeof(ec_sdo_entry_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate entry!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + + ec_sdo_entry_init(entry, sdo, fsm->subindex); + entry->data_type = EC_READ_U16(data + 10); + entry->bit_length = EC_READ_U16(data + 12); + + // read access rights + word = EC_READ_U16(data + 14); + entry->read_access[EC_SDO_ENTRY_ACCESS_PREOP] = word & 0x0001; + entry->read_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + (word >> 1) & 0x0001; + entry->read_access[EC_SDO_ENTRY_ACCESS_OP] = (word >> 2) & 0x0001; + entry->write_access[EC_SDO_ENTRY_ACCESS_PREOP] = (word >> 3) & 0x0001; + entry->write_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + (word >> 4) & 0x0001; + entry->write_access[EC_SDO_ENTRY_ACCESS_OP] = (word >> 5) & 0x0001; + + if (data_size) { + uint8_t *desc; + if (!(desc = kmalloc(data_size + 1, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate SDO entry name!\n"); + fsm->state = ec_fsm_coe_error; + return; + } + memcpy(desc, data + 16, data_size); + desc[data_size] = 0; + entry->description = desc; + } + + list_add_tail(&entry->list, &sdo->entries); + } + + if (fsm->subindex < sdo->max_subindex) { + + fsm->subindex++; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_dict_prepare_entry(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + + return; + } + + // another SDO description to fetch? + if (fsm->sdo->list.next != &slave->sdo_dictionary) { + + fsm->sdo = list_entry(fsm->sdo->list.next, ec_sdo_t, list); + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_dict_prepare_desc(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + + return; + } + + fsm->state = ec_fsm_coe_end; +} + +/***************************************************************************** + * CoE state machine + ****************************************************************************/ + +/** Prepare a donwnload request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_prepare_down_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + u8 *data; + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + uint8_t data_set_size; + + if (request->data_size > 0 && request->data_size <= 4) { + // use expedited transfer mode for lengths between 1 and 4 bytes + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + EC_COE_DOWN_REQ_HEADER_SIZE); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + return PTR_ERR(data); + } + + fsm->remaining = 0; + + data_set_size = 4 - request->data_size; + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8 (data + 2, (0x3 // size specified, expedited + | data_set_size << 2 + | ((request->complete_access ? 1 : 0) << 4) + | 0x1 << 5)); // Download request + EC_WRITE_U16(data + 3, request->index); + EC_WRITE_U8 (data + 5, + request->complete_access ? 0x00 : request->subindex); + memcpy(data + 6, request->data, request->data_size); + memset(data + 6 + request->data_size, 0x00, 4 - request->data_size); + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Expedited download request:\n"); + ec_print_data(data, EC_COE_DOWN_REQ_HEADER_SIZE); + } + } + else { // data_size < 1 or data_size > 4, use normal transfer type + size_t data_size, + max_data_size = + slave->configured_rx_mailbox_size - EC_MBOX_HEADER_SIZE, + required_data_size = + EC_COE_DOWN_REQ_HEADER_SIZE + request->data_size; + + if (max_data_size < required_data_size) { + // segmenting needed + data_size = max_data_size; + } else { + data_size = required_data_size; + } + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + data_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + return PTR_ERR(data); + } + + fsm->offset = 0; + fsm->remaining = request->data_size; + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8(data + 2, + 0x1 // size indicator, normal + | ((request->complete_access ? 1 : 0) << 4) + | 0x1 << 5); // Download request + EC_WRITE_U16(data + 3, request->index); + EC_WRITE_U8 (data + 5, + request->complete_access ? 0x00 : request->subindex); + EC_WRITE_U32(data + 6, request->data_size); + + if (data_size > EC_COE_DOWN_REQ_HEADER_SIZE) { + size_t segment_size = data_size - EC_COE_DOWN_REQ_HEADER_SIZE; + memcpy(data + EC_COE_DOWN_REQ_HEADER_SIZE, + request->data, segment_size); + fsm->offset += segment_size; + fsm->remaining -= segment_size; + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Normal download request:\n"); + ec_print_data(data, data_size); + } + } + + fsm->state = ec_fsm_coe_down_request; + return 0; +} + +/****************************************************************************/ + +/** CoE state: DOWN START. + */ +void ec_fsm_coe_down_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + + if (fsm->slave->master->debug_level) { + char subidxstr[10]; + if (request->complete_access) { + subidxstr[0] = 0x00; + } else { + sprintf(subidxstr, ":%02X", request->subindex); + } + EC_SLAVE_DBG(slave, 1, "Downloading SDO 0x%04X%s.\n", + request->index, subidxstr); + ec_print_data(request->data, request->data_size); + } + + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_SLAVE_ERR(slave, "Slave does not support CoE!\n"); + request->errno = EPROTONOSUPPORT; + fsm->state = ec_fsm_coe_error; + return; + } + + if (slave->configured_rx_mailbox_size < + EC_MBOX_HEADER_SIZE + EC_COE_DOWN_REQ_HEADER_SIZE) { + EC_SLAVE_ERR(slave, "Mailbox too small!\n"); + request->errno = ENOBUFS; + fsm->state = ec_fsm_coe_error; + return; + } + + + fsm->request->jiffies_sent = jiffies; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_coe_prepare_down_start(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ + +/** + CoE state: DOWN REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_down_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_prepare_down_start(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE download" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < fsm->request->response_timeout) { +#if DEBUG_RETRIES + EC_SLAVE_DBG(slave, 1, "Slave did not respond to SDO" + " download request. Retrying after %lu ms...\n", + diff_ms); +#endif + // no response; send request datagram again + if (ec_fsm_coe_prepare_down_start(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + } + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE download request" + " for SDO 0x%04x:%x failed with timeout after %lu ms: ", + fsm->request->index, fsm->request->subindex, diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + +#if DEBUG_LONG + if (diff_ms > 200) { + EC_SLAVE_WARN(slave, "SDO 0x%04x:%x download took %lu ms.\n", + fsm->request->index, fsm->request->subindex, diff_ms); + } +#endif + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; +} + +/****************************************************************************/ + +/** CoE state: DOWN CHECK. + */ +void ec_fsm_coe_down_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting" + " for SDO 0x%04x:%x download response.\n", diff_ms, + fsm->request->index, fsm->request->subindex); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_response; +} + +/****************************************************************************/ + +/** Prepare a download segment request. + */ +void ec_fsm_coe_down_prepare_segment_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + size_t max_segment_size = + slave->configured_rx_mailbox_size + - EC_MBOX_HEADER_SIZE + - EC_COE_DOWN_SEG_REQ_HEADER_SIZE; + size_t data_size; + uint8_t last_segment, seg_data_size, *data; + + if (fsm->remaining > max_segment_size) { + fsm->segment_size = max_segment_size; + last_segment = 0; + } else { + fsm->segment_size = fsm->remaining; + last_segment = 1; + } + + if (fsm->segment_size > EC_COE_DOWN_SEG_MIN_DATA_SIZE) { + seg_data_size = 0x00; + data_size = EC_COE_DOWN_SEG_REQ_HEADER_SIZE + fsm->segment_size; + } else { + seg_data_size = EC_COE_DOWN_SEG_MIN_DATA_SIZE - fsm->segment_size; + data_size = EC_COE_DOWN_SEG_REQ_HEADER_SIZE + + EC_COE_DOWN_SEG_MIN_DATA_SIZE; + } + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + data_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8(data + 2, (last_segment ? 1 : 0) + | (seg_data_size << 1) + | (fsm->toggle << 4) + | (0x00 << 5)); // Download segment request + memcpy(data + EC_COE_DOWN_SEG_REQ_HEADER_SIZE, + request->data + fsm->offset, fsm->segment_size); + if (fsm->segment_size < EC_COE_DOWN_SEG_MIN_DATA_SIZE) { + memset(data + EC_COE_DOWN_SEG_REQ_HEADER_SIZE + fsm->segment_size, + 0x00, EC_COE_DOWN_SEG_MIN_DATA_SIZE - fsm->segment_size); + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Download segment request:\n"); + ec_print_data(data, data_size); + } + + fsm->state = ec_fsm_coe_down_seg_check; +} + +/****************************************************************************/ + +/** + CoE state: DOWN RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_down_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + size_t rec_size; + ec_sdo_request_t *request = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE download" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE download response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; + return; + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Download response:\n"); + ec_print_data(data, rec_size); + } + + if (rec_size < 6) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received data are too small (%zu bytes):\n", + rec_size); + ec_print_data(data, rec_size); + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8 (data + 2) >> 5 == 0x4) { // abort SDO transfer request + char subidxstr[10]; + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + if (request->complete_access) { + subidxstr[0] = 0x00; + } else { + sprintf(subidxstr, ":%02X", request->subindex); + } + EC_SLAVE_ERR(slave, "SDO download 0x%04X%s (%zu bytes) aborted.\n", + request->index, subidxstr, request->data_size); + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Incomplete abort command:\n"); + ec_print_data(data, rec_size); + } else { + fsm->request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, fsm->request->abort_code); + } + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || // SDO response + EC_READ_U8 (data + 2) >> 5 != 0x3 || // Download response + EC_READ_U16(data + 3) != request->index || // index + EC_READ_U8 (data + 5) != request->subindex) { // subindex + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO download response!" + " Retrying...\n"); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; + return; + } + + if (fsm->remaining) { // more segments to download + fsm->toggle = 0; + ec_fsm_coe_down_prepare_segment_request(fsm, datagram); + } else { + fsm->state = ec_fsm_coe_end; // success + } +} + +/****************************************************************************/ + +/** + CoE state: DOWN SEG CHECK. +*/ + +void ec_fsm_coe_down_seg_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox segment check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for SDO download" + " segment response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_seg_response; +} + +/****************************************************************************/ + +/** + CoE state: DOWN SEG RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_down_seg_response( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + size_t rec_size; + ec_sdo_request_t *request = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE download response" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE download response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_check; + return; + } + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Download response:\n"); + ec_print_data(data, rec_size); + } + + if (rec_size < 6) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received data are too small (%zu bytes):\n", + rec_size); + ec_print_data(data, rec_size); + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8 (data + 2) >> 5 == 0x4) { // abort SDO transfer request + char subidxstr[10]; + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + if (request->complete_access) { + subidxstr[0] = 0x00; + } else { + sprintf(subidxstr, ":%02X", request->subindex); + } + EC_SLAVE_ERR(slave, "SDO download 0x%04X%s (%zu bytes) aborted.\n", + request->index, subidxstr, request->data_size); + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Incomplete abort command:\n"); + ec_print_data(data, rec_size); + } else { + fsm->request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, fsm->request->abort_code); + } + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || + ((EC_READ_U8(data + 2) >> 5) != 0x01)) { // segment response + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO download response!" + " Retrying...\n"); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_down_seg_check; + return; + } + + if (((EC_READ_U8(data + 2) >> 4) & 0x01) != fsm->toggle) { + EC_SLAVE_ERR(slave, "Invalid toggle received during" + " segmented download:\n"); + ec_print_data(data, rec_size); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->offset += fsm->segment_size; + fsm->remaining -= fsm->segment_size; + + if (fsm->remaining) { // more segments to download + fsm->toggle = !fsm->toggle; + ec_fsm_coe_down_prepare_segment_request(fsm, datagram); + } else { + fsm->state = ec_fsm_coe_end; // success + } +} + +/****************************************************************************/ + +/** Prepare an upload request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_fsm_coe_prepare_up( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + ec_master_t *master = slave->master; + + u8 *data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_COE, + 10); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + return PTR_ERR(data); + } + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8 (data + 2, 0x2 << 5); // initiate upload request + EC_WRITE_U16(data + 3, request->index); + EC_WRITE_U8 (data + 5, request->subindex); + memset(data + 6, 0x00, 4); + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Upload request:\n"); + ec_print_data(data, 10); + } + + fsm->state = ec_fsm_coe_up_request; + return 0; +} + +/****************************************************************************/ + +/** + CoE state: UP START. +*/ + +void ec_fsm_coe_up_start( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->request; + + EC_SLAVE_DBG(slave, 1, "Uploading SDO 0x%04X:%02X.\n", + request->index, request->subindex); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_SLAVE_ERR(slave, "Slave does not support CoE!\n"); + request->errno = EPROTONOSUPPORT; + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->retries = EC_FSM_RETRIES; + fsm->request->jiffies_sent = jiffies; + + if (ec_fsm_coe_prepare_up(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } +} + +/****************************************************************************/ +/** + CoE state: UP REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_coe_prepare_up(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload request: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < fsm->request->response_timeout) { +#if DEBUG_RETRIES + EC_SLAVE_DBG(slave, 1, "Slave did not respond to" + " SDO upload request. Retrying after %lu ms...\n", + diff_ms); +#endif + // no response; send request datagram again + if (ec_fsm_coe_prepare_up(fsm, datagram)) { + fsm->state = ec_fsm_coe_error; + } + return; + } + } + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload request for" + " SDO 0x%04x:%x failed with timeout after %lu ms: ", + fsm->request->index, fsm->request->subindex, diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + +#if DEBUG_LONG + if (diff_ms > 200) { + EC_SLAVE_WARN(slave, "SDO 0x%04x:%x upload took %lu ms.\n", + fsm->request->index, fsm->request->subindex, diff_ms); + } +#endif + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_check; +} + +/****************************************************************************/ + +/** + CoE state: UP CHECK. +*/ + +void ec_fsm_coe_up_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting for" + " SDO 0x%04x:%x upload response.\n", diff_ms, + fsm->request->index, fsm->request->subindex); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_response; +} + +/****************************************************************************/ + +/** Prepare an SDO upload segment request. + */ +void ec_fsm_coe_up_prepare_segment_request( + ec_fsm_coe_t *fsm, /**< Finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data = + ec_slave_mbox_prepare_send(fsm->slave, datagram, EC_MBOX_TYPE_COE, + 10); + if (IS_ERR(data)) { + fsm->request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + EC_WRITE_U16(data, 0x2 << 12); // SDO request + EC_WRITE_U8 (data + 2, (fsm->toggle << 4 // toggle + | 0x3 << 5)); // upload segment request + memset(data + 3, 0x00, 7); + + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(fsm->slave, 1, "Upload segment request:\n"); + ec_print_data(data, 10); + } +} + +/****************************************************************************/ + +/** + CoE state: UP RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint16_t rec_index; + uint8_t *data, mbox_prot, rec_subindex; + size_t rec_size, data_size; + ec_sdo_request_t *request = fsm->request; + unsigned int expedited, size_specified; + int ret; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload response" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Upload response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_WARN(slave, "Received mailbox protocol 0x%02X" + " as response.\n", mbox_prot); + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_check; + return; + } + + if (rec_size < 6) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received currupted SDO upload response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8(data + 2) >> 5 == 0x4) { // abort SDO transfer request + EC_SLAVE_ERR(slave, "SDO upload 0x%04X:%02X aborted.\n", + request->index, request->subindex); + if (rec_size >= 10) { + request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, request->abort_code); + } else { + EC_SLAVE_ERR(slave, "No abort message.\n"); + } + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || // SDO response + EC_READ_U8(data + 2) >> 5 != 0x2) { // upload response + EC_SLAVE_ERR(slave, "Received unknown response while" + " uploading SDO 0x%04X:%02X.\n", + request->index, request->subindex); + ec_print_data(data, rec_size); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + rec_index = EC_READ_U16(data + 3); + rec_subindex = EC_READ_U8(data + 5); + + if (rec_index != request->index || rec_subindex != request->subindex) { + EC_SLAVE_ERR(slave, "Received upload response for wrong SDO" + " (0x%04X:%02X, requested: 0x%04X:%02X).\n", + rec_index, rec_subindex, request->index, request->subindex); + ec_print_data(data, rec_size); + + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_check; + return; + } + + // normal or expedited? + expedited = EC_READ_U8(data + 2) & 0x02; + + if (expedited) { + size_specified = EC_READ_U8(data + 2) & 0x01; + if (size_specified) { + fsm->complete_size = 4 - ((EC_READ_U8(data + 2) & 0x0C) >> 2); + } else { + fsm->complete_size = 4; + } + + if (rec_size < 6 + fsm->complete_size) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received corrupted SDO expedited upload" + " response (only %zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + ret = ec_sdo_request_copy_data(request, data + 6, fsm->complete_size); + if (ret) { + request->errno = -ret; + fsm->state = ec_fsm_coe_error; + return; + } + } else { // normal + if (rec_size < 10) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Received currupted SDO normal upload" + " response (only %zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + data_size = rec_size - 10; + fsm->complete_size = EC_READ_U32(data + 6); + + ret = ec_sdo_request_alloc(request, fsm->complete_size); + if (ret) { + request->errno = -ret; + fsm->state = ec_fsm_coe_error; + return; + } + + ret = ec_sdo_request_copy_data(request, data + 10, data_size); + if (ret) { + request->errno = -ret; + fsm->state = ec_fsm_coe_error; + return; + } + + fsm->toggle = 0; + + if (data_size < fsm->complete_size) { + EC_SLAVE_DBG(slave, 1, "SDO data incomplete (%zu / %u)." + " Segmenting...\n", data_size, fsm->complete_size); + ec_fsm_coe_up_prepare_segment_request(fsm, datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_request; + return; + } + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Uploaded data:\n"); + ec_print_data(request->data, request->data_size); + } + + fsm->state = ec_fsm_coe_end; // success +} + +/****************************************************************************/ + +/** + CoE state: UP REQUEST. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_seg_request( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_fsm_coe_up_prepare_segment_request(fsm, datagram); + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload segment" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload segment" + " request failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_check; +} + +/****************************************************************************/ + +/** + CoE state: UP CHECK. +*/ + +void ec_fsm_coe_up_seg_check( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE mailbox check" + " datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE mailbox check datagram" + " failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= fsm->request->response_timeout) { + fsm->request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Timeout while waiting for SDO upload" + " segment response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_response; +} + +/****************************************************************************/ + +/** + CoE state: UP RESPONSE. + \todo Timeout behavior +*/ + +void ec_fsm_coe_up_seg_response( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint8_t *data, mbox_prot; + size_t rec_size, data_size; + ec_sdo_request_t *request = fsm->request; + unsigned int last_segment; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Failed to receive CoE upload segment" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + EC_SLAVE_ERR(slave, "Reception of CoE upload segment" + " response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + request->errno = PTR_ERR(data); + fsm->state = ec_fsm_coe_error; + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Upload segment response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_COE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (ec_fsm_coe_check_emergency(fsm, data, rec_size)) { + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_check; + return; + } + + if (rec_size < 10) { + EC_SLAVE_ERR(slave, "Received currupted SDO upload" + " segment response!\n"); + ec_print_data(data, rec_size); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 == 0x2 && // SDO request + EC_READ_U8 (data + 2) >> 5 == 0x4) { // abort SDO transfer request + EC_SLAVE_ERR(slave, "SDO upload 0x%04X:%02X aborted.\n", + request->index, request->subindex); + request->abort_code = EC_READ_U32(data + 6); + ec_canopen_abort_msg(slave, request->abort_code); + request->errno = EIO; + fsm->state = ec_fsm_coe_error; + return; + } + + if (EC_READ_U16(data) >> 12 != 0x3 || // SDO response + EC_READ_U8 (data + 2) >> 5 != 0x0) { // upload segment response + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Invalid SDO upload segment response!\n"); + ec_print_data(data, rec_size); + } + // check for CoE response again + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_check; + return; + } + + data_size = rec_size - 3; /* Header of segment upload is smaller than + normal upload */ + if (rec_size == 10) { + uint8_t seg_size = (EC_READ_U8(data + 2) & 0xE) >> 1; + data_size -= seg_size; + } + + if (request->data_size + data_size > fsm->complete_size) { + EC_SLAVE_ERR(slave, "SDO upload 0x%04X:%02X failed: Fragment" + " exceeding complete size!\n", + request->index, request->subindex); + request->errno = ENOBUFS; + fsm->state = ec_fsm_coe_error; + return; + } + + memcpy(request->data + request->data_size, data + 3, data_size); + request->data_size += data_size; + + last_segment = EC_READ_U8(data + 2) & 0x01; + if (!last_segment) { + fsm->toggle = !fsm->toggle; + ec_fsm_coe_up_prepare_segment_request(fsm, datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_coe_up_seg_request; + return; + } + + if (request->data_size != fsm->complete_size) { + EC_SLAVE_WARN(slave, "SDO upload 0x%04X:%02X: Assembled data" + " size (%zu) does not match complete size (%u)!\n", + request->index, request->subindex, + request->data_size, fsm->complete_size); + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Uploaded data:\n"); + ec_print_data(request->data, request->data_size); + } + + fsm->state = ec_fsm_coe_end; // success +} + +/****************************************************************************/ + +/** + State: ERROR. +*/ + +void ec_fsm_coe_error( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** + State: END. +*/ + +void ec_fsm_coe_end( + ec_fsm_coe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_coe.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_coe.h @@ -0,0 +1,74 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CoE state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_COE_H__ +#define __EC_FSM_COE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "sdo.h" +#include "sdo_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_coe ec_fsm_coe_t; /**< \see ec_fsm_coe */ + +/** Finite state machines for the CANopen over EtherCAT protocol. + */ +struct ec_fsm_coe { + ec_slave_t *slave; /**< slave the FSM runs on */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_coe_t *, ec_datagram_t *); /**< CoE state function */ + ec_datagram_t *datagram; /**< Datagram used in last step. */ + unsigned long jiffies_start; /**< CoE timestamp. */ + ec_sdo_t *sdo; /**< current SDO */ + uint8_t subindex; /**< current subindex */ + ec_sdo_request_t *request; /**< SDO request */ + uint32_t complete_size; /**< Used when segmenting. */ + uint8_t toggle; /**< toggle bit for segment commands */ + uint32_t offset; /**< Data offset during segmented download. */ + uint32_t remaining; /**< Remaining bytes during segmented download. */ + size_t segment_size; /**< Current segment size. */ +}; + +/****************************************************************************/ + +void ec_fsm_coe_init(ec_fsm_coe_t *); +void ec_fsm_coe_clear(ec_fsm_coe_t *); + +void ec_fsm_coe_dictionary(ec_fsm_coe_t *, ec_slave_t *); +void ec_fsm_coe_transfer(ec_fsm_coe_t *, ec_slave_t *, ec_sdo_request_t *); + +int ec_fsm_coe_exec(ec_fsm_coe_t *, ec_datagram_t *); +int ec_fsm_coe_success(const ec_fsm_coe_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_eoe.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_eoe.c @@ -0,0 +1,509 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2014 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT EoE state machines. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_eoe.h" + +/****************************************************************************/ + +/** Maximum time to wait for a set IP parameter response. + */ +#define EC_EOE_RESPONSE_TIMEOUT 3000 // [ms] + +/****************************************************************************/ + +// prototypes for private functions +void memcpy_swap32(void *, const void *); + +int ec_fsm_eoe_prepare_set(ec_fsm_eoe_t *, ec_datagram_t *); + +void ec_fsm_eoe_set_ip_start(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_set_ip_request(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_set_ip_check(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_set_ip_response(ec_fsm_eoe_t *, ec_datagram_t *); + +void ec_fsm_eoe_end(ec_fsm_eoe_t *, ec_datagram_t *); +void ec_fsm_eoe_error(ec_fsm_eoe_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Host-architecture-independent 32-bit swap function. + * + * The internal storage of struct in_addr is always big-endian. + * The mailbox protocol format to supply IPv4 adresses is little-endian + * (Yuck!). So we need a swap function, that is independent of the CPU + * architecture. ntohl()/htonl() can not be used, because they evaluate to + * NOPs if the host architecture matches the target architecture! + */ +void memcpy_swap32(void *dst, const void *src) +{ + int i; + for (i = 0; i < 4; i++) { + ((u8 *) dst)[i] = ((const u8 *) src)[3 - i]; + } +} + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_eoe_init( + ec_fsm_eoe_t *fsm /**< finite state machine */ + ) +{ + fsm->slave = NULL; + fsm->retries = 0; + fsm->state = NULL; + fsm->datagram = NULL; + fsm->jiffies_start = 0; + fsm->request = NULL; + fsm->frame_type_retries = 0; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_eoe_clear( + ec_fsm_eoe_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** Starts to set the EoE IP partameters of a slave. + */ +void ec_fsm_eoe_set_ip_param( + ec_fsm_eoe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_eoe_request_t *request /**< EoE request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + fsm->state = ec_fsm_eoe_set_ip_start; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if the datagram was used, else 0. + */ +int ec_fsm_eoe_exec( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_eoe_end && fsm->state != ec_fsm_eoe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * + * \return non-zero if successful. + */ +int ec_fsm_eoe_success(const ec_fsm_eoe_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_eoe_end; +} + +/***************************************************************************** + * EoE set IP parameter state machine + ****************************************************************************/ + +/** Prepare a set IP parameters operation. + * + * \return 0 on success, otherwise a negative error code. + */ +int ec_fsm_eoe_prepare_set( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data, *cur; + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_eoe_request_t *req = fsm->request; + + // Note: based on wireshark packet filter it suggests that the EOE_INIT + // information is a fixed size with fixed information positions. + // see: packet-ecatmb.h and packet-ecatmb.c + // However, TwinCAT 2.1 testing also indicates that if a piece of + // information is missing then all subsequent items are ignored + // Also, if you want DHCP, then only set the mac address. + size_t size = 8 + // header + flags + ETH_ALEN + // mac address + 4 + // ip address + 4 + // subnet mask + 4 + // gateway + 4 + // dns server + EC_MAX_HOSTNAME_SIZE; // dns name + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_EOE, + size); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + // zero data + memset(data, 0, size); + + // header + EC_WRITE_U8(data, EC_EOE_FRAMETYPE_SET_IP_REQ); // Set IP parameter req. + EC_WRITE_U8(data + 1, 0x00); // not used + EC_WRITE_U16(data + 2, 0x0000); // not used + + EC_WRITE_U32(data + 4, + ((req->mac_address_included != 0) << 0) | + ((req->ip_address_included != 0) << 1) | + ((req->subnet_mask_included != 0) << 2) | + ((req->gateway_included != 0) << 3) | + ((req->dns_included != 0) << 4) | + ((req->name_included != 0) << 5) + ); + + cur = data + 8; + + if (req->mac_address_included) { + memcpy(cur, req->mac_address, ETH_ALEN); + } + cur += ETH_ALEN; + + if (req->ip_address_included) { + memcpy_swap32(cur, &req->ip_address); + } + cur += 4; + + if (req->subnet_mask_included) { + memcpy_swap32(cur, &req->subnet_mask); + } + cur += 4; + + if (req->gateway_included) { + memcpy_swap32(cur, &req->gateway); + } + cur += 4; + + if (req->dns_included) { + memcpy_swap32(cur, &req->dns); + } + cur += 4; + + if (req->name_included) { + memcpy(cur, req->name, EC_MAX_HOSTNAME_SIZE); + } + cur += EC_MAX_HOSTNAME_SIZE; + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Set IP parameter request:\n"); + ec_print_data(data, cur - data); + } + + fsm->request->jiffies_sent = jiffies; + + return 0; +} + +/****************************************************************************/ + +/** EoE state: SET IP START. + */ +void ec_fsm_eoe_set_ip_start( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + EC_SLAVE_DBG(slave, 1, "Setting IP parameters.\n"); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_EOE)) { + EC_SLAVE_ERR(slave, "Slave does not support EoE!\n"); + fsm->state = ec_fsm_eoe_error; + return; + } + + if (ec_fsm_eoe_prepare_set(fsm, datagram)) { + fsm->state = ec_fsm_eoe_error; + return; + } + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_request; +} + +/****************************************************************************/ + +/** EoE state: SET IP REQUEST. + */ +void ec_fsm_eoe_set_ip_request( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_eoe_prepare_set(fsm, datagram)) { + fsm->state = ec_fsm_eoe_error; + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Failed to receive EoE set IP parameter" + " request: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + unsigned long diff_ms = + (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (!fsm->datagram->working_counter) { + if (diff_ms < EC_EOE_RESPONSE_TIMEOUT) { + // no response; send request datagram again + if (ec_fsm_eoe_prepare_set(fsm, datagram)) { + fsm->state = ec_fsm_eoe_error; + } + return; + } + } + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Reception of EoE set IP parameter request" + " failed after %lu ms: ", diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_check; + fsm->frame_type_retries = 10; +} + +/****************************************************************************/ + +/** EoE state: SET IP CHECK. + */ +void ec_fsm_eoe_set_ip_check( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Failed to receive EoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Reception of EoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_EOE_RESPONSE_TIMEOUT) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting for" + " set IP parameter response.\n", diff_ms); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_response; +} + +/****************************************************************************/ + +/** EoE state: SET IP RESPONSE. + */ +void ec_fsm_eoe_set_ip_response( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint8_t *data, mbox_prot, frame_type; + size_t rec_size; + ec_eoe_request_t *req = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Failed to receive EoE read response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Reception of EoE read response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_eoe_error; + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Set IP parameter response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_EOE) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + if (rec_size < 4) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_ERR(slave, "Received currupted EoE set IP parameter response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + return; + } + + frame_type = EC_READ_U8(data) & 0x0f; + + if (frame_type != EC_EOE_FRAMETYPE_SET_IP_RES) { + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Received no set IP parameter response" + " (frame type %x).\n", frame_type); + ec_print_data(data, rec_size); + } + if (fsm->frame_type_retries--) { + // there may be an EoE segment left in the mailbox. + // discard it and receive again. + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_eoe_set_ip_check; + return; + } + else { + EC_SLAVE_ERR(slave, "Received no set IP parameter response.\n"); + fsm->state = ec_fsm_eoe_error; + return; + } + } + + req->result = EC_READ_U16(data + 2); // result code 0x0000 means success + + if (req->result) { + fsm->state = ec_fsm_eoe_error; + EC_SLAVE_DBG(slave, 1, "EoE set IP parameters failed with result code" + " 0x%04X.\n", req->result); + } else { + fsm->state = ec_fsm_eoe_end; // success + } +} + +/****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_eoe_error( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_eoe_end( + ec_fsm_eoe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_eoe.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_eoe.h @@ -0,0 +1,67 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2014 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT EoE set IP parameter state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_EOE_H__ +#define __EC_FSM_EOE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "eoe_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_eoe ec_fsm_eoe_t; /**< \see ec_fsm_eoe */ + +/** Finite state machines for the Ethernet over EtherCAT protocol. + */ +struct ec_fsm_eoe { + ec_slave_t *slave; /**< slave the FSM runs on */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_eoe_t *, ec_datagram_t *); /**< EoE state function */ + ec_datagram_t *datagram; /**< Datagram used in the previous step. */ + unsigned long jiffies_start; /**< Timestamp. */ + ec_eoe_request_t *request; /**< EoE request */ + unsigned int frame_type_retries; /**< retries upon wrong frame type. */ +}; + +/****************************************************************************/ + +void ec_fsm_eoe_init(ec_fsm_eoe_t *); +void ec_fsm_eoe_clear(ec_fsm_eoe_t *); + +void ec_fsm_eoe_set_ip_param(ec_fsm_eoe_t *, ec_slave_t *, + ec_eoe_request_t *); + +int ec_fsm_eoe_exec(ec_fsm_eoe_t *, ec_datagram_t *); +int ec_fsm_eoe_success(const ec_fsm_eoe_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_foe.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_foe.c @@ -0,0 +1,915 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * 2013 Florian Pose + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT FoE state machines. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_foe.h" +#include "foe.h" + +/****************************************************************************/ + +/** Maximum time in ms to wait for responses when reading out the dictionary. + */ +#define EC_FSM_FOE_TIMEOUT 3000 + +/** Size of the FoE header. + */ +#define EC_FOE_HEADER_SIZE 6 +// uint8_t OpCode +// uint8_t reserved +// uint32_t PacketNo, Password, ErrorCode + +//#define DEBUG_FOE + +/****************************************************************************/ + +/** FoE OpCodes. + */ +enum { + EC_FOE_OPCODE_RRQ = 1, /**< Read request. */ + EC_FOE_OPCODE_WRQ = 2, /**< Write request. */ + EC_FOE_OPCODE_DATA = 3, /**< Data. */ + EC_FOE_OPCODE_ACK = 4, /**< Acknowledge. */ + EC_FOE_OPCODE_ERR = 5, /**< Error. */ + EC_FOE_OPCODE_BUSY = 6 /**< Busy. */ +}; + +/****************************************************************************/ + +int ec_foe_prepare_data_send(ec_fsm_foe_t *, ec_datagram_t *); +int ec_foe_prepare_wrq_send(ec_fsm_foe_t *, ec_datagram_t *); +int ec_foe_prepare_rrq_send(ec_fsm_foe_t *, ec_datagram_t *); +int ec_foe_prepare_send_ack(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_foe_set_tx_error(ec_fsm_foe_t *, uint32_t); +void ec_foe_set_rx_error(ec_fsm_foe_t *, uint32_t); + +void ec_fsm_foe_end(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_error(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_wrq_sent(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_rrq_sent(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_ack_check(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_ack_read(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_data_sent(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_state_data_check(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_data_read(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_state_sent_ack(ec_fsm_foe_t *, ec_datagram_t *); + +void ec_fsm_foe_write_start(ec_fsm_foe_t *, ec_datagram_t *); +void ec_fsm_foe_read_start(ec_fsm_foe_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_foe_init( + ec_fsm_foe_t *fsm /**< finite state machine */ + ) +{ + fsm->state = NULL; + fsm->datagram = NULL; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_foe_clear(ec_fsm_foe_t *fsm /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1, if the datagram was used, else 0. + */ +int ec_fsm_foe_exec( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_foe_end && fsm->state != ec_fsm_foe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * \return non-zero if successful. + */ +int ec_fsm_foe_success(const ec_fsm_foe_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_foe_end; +} + +/****************************************************************************/ + +/** Prepares an FoE transfer. + */ +void ec_fsm_foe_transfer( + ec_fsm_foe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_foe_request_t *request /**< Sdo request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + + if (request->dir == EC_DIR_OUTPUT) { + fsm->tx_buffer = fsm->request->buffer; + fsm->tx_buffer_size = fsm->request->data_size; + fsm->tx_buffer_offset = 0; + + fsm->tx_filename = fsm->request->file_name; + fsm->tx_filename_len = strlen(fsm->tx_filename); + + fsm->state = ec_fsm_foe_write_start; + } + else { + fsm->rx_buffer = fsm->request->buffer; + fsm->rx_buffer_size = fsm->request->buffer_size; + + fsm->rx_filename = fsm->request->file_name; + fsm->rx_filename_len = strlen(fsm->rx_filename); + + fsm->state = ec_fsm_foe_read_start; + } +} + +/****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_foe_error( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_foe_end( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif +} + +/****************************************************************************/ + +/** Sends a file or the next fragment. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_data_send( + ec_fsm_foe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t remaining_size, current_size; + uint8_t *data; + + remaining_size = fsm->tx_buffer_size - fsm->tx_buffer_offset; + + if (remaining_size < fsm->slave->configured_tx_mailbox_size + - EC_MBOX_HEADER_SIZE - EC_FOE_HEADER_SIZE) { + current_size = remaining_size; + fsm->tx_last_packet = 1; + } else { + current_size = fsm->slave->configured_tx_mailbox_size + - EC_MBOX_HEADER_SIZE - EC_FOE_HEADER_SIZE; + } + + data = ec_slave_mbox_prepare_send(fsm->slave, + datagram, EC_MBOX_TYPE_FOE, current_size + EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16(data, EC_FOE_OPCODE_DATA); // OpCode = DataBlock req. + EC_WRITE_U32(data + 2, fsm->tx_packet_no); // PacketNo, Password + + memcpy(data + EC_FOE_HEADER_SIZE, + fsm->tx_buffer + fsm->tx_buffer_offset, current_size); + fsm->tx_current_size = current_size; + + return 0; +} + +/****************************************************************************/ + +/** Prepare a write request (WRQ) with filename + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_wrq_send( + ec_fsm_foe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t current_size; + uint8_t *data; + + fsm->tx_buffer_offset = 0; + fsm->tx_current_size = 0; + fsm->tx_packet_no = 0; + fsm->tx_last_packet = 0; + + current_size = fsm->tx_filename_len; + + data = ec_slave_mbox_prepare_send(fsm->slave, datagram, + EC_MBOX_TYPE_FOE, current_size + EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16( data, EC_FOE_OPCODE_WRQ); // fsm write request + EC_WRITE_U32( data + 2, fsm->tx_packet_no ); + + memcpy(data + EC_FOE_HEADER_SIZE, fsm->tx_filename, current_size); + + return 0; +} + +/****************************************************************************/ + +/** Initializes the FoE write state machine. + */ +void ec_fsm_foe_write_start( + ec_fsm_foe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + fsm->tx_buffer_offset = 0; + fsm->tx_current_size = 0; + fsm->tx_packet_no = 0; + fsm->tx_last_packet = 0; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (!(slave->sii.mailbox_protocols & EC_MBOX_FOE)) { + ec_foe_set_tx_error(fsm, FOE_MBOX_PROT_ERROR); + EC_SLAVE_ERR(slave, "Slave does not support FoE!\n"); + return; + } + + if (ec_foe_prepare_wrq_send(fsm, datagram)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + return; + } + + fsm->state = ec_fsm_foe_state_wrq_sent; +} + +/****************************************************************************/ + +/** Check for acknowledge. + */ +void ec_fsm_foe_state_ack_check( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE mailbox check datagram" + " failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + // slave did not put anything in the mailbox yet + unsigned long diff_ms = (fsm->datagram->jiffies_received - + fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_FSM_FOE_TIMEOUT) { + ec_foe_set_tx_error(fsm, FOE_TIMEOUT_ERROR); + EC_SLAVE_ERR(slave, "Timeout while waiting for ack response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_ack_read; +} + +/****************************************************************************/ + +/** Acknowledge a read operation. + */ +void ec_fsm_foe_state_ack_read( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t *data, mbox_prot; + uint8_t opCode; + size_t rec_size; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE ack response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE ack response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + return; + } + + if (mbox_prot != EC_MBOX_TYPE_FOE) { + ec_foe_set_tx_error(fsm, FOE_MBOX_PROT_ERROR); + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + return; + } + + opCode = EC_READ_U8(data); + + if (opCode == EC_FOE_OPCODE_BUSY) { + // slave not ready + if (ec_foe_prepare_data_send(fsm, datagram)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + EC_SLAVE_ERR(slave, "Slave is busy.\n"); + return; + } + fsm->state = ec_fsm_foe_state_data_sent; + return; + } + + if (opCode == EC_FOE_OPCODE_ACK) { + fsm->tx_packet_no++; + fsm->tx_buffer_offset += fsm->tx_current_size; + + if (fsm->tx_last_packet) { + fsm->state = ec_fsm_foe_end; + return; + } + + if (ec_foe_prepare_data_send(fsm, datagram)) { + ec_foe_set_tx_error(fsm, FOE_PROT_ERROR); + return; + } + fsm->state = ec_fsm_foe_state_data_sent; + return; + } + ec_foe_set_tx_error(fsm, FOE_ACK_ERROR); +} + +/****************************************************************************/ + +/** State: WRQ SENT. + * + * Checks is the previous transmit datagram succeded and sends the next + * fragment, if necessary. + */ +void ec_fsm_foe_state_wrq_sent( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE WRQ: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + // slave did not put anything in the mailbox yet + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE WRQ failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_ack_check; +} + +/****************************************************************************/ + +/** State: WRQ SENT. + * + * Checks is the previous transmit datagram succeded and sends the next + * fragment, if necessary. + */ +void ec_fsm_foe_state_data_sent( + ec_fsm_foe_t *fsm, /**< Foe statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_tx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE ack response datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_tx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE data send failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); + fsm->jiffies_start = jiffies; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_ack_check; +} + +/****************************************************************************/ + +/** Prepare a read request (RRQ) with filename + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_rrq_send( + ec_fsm_foe_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t current_size; + uint8_t *data; + + current_size = fsm->rx_filename_len; + + data = ec_slave_mbox_prepare_send(fsm->slave, datagram, + EC_MBOX_TYPE_FOE, current_size + EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16(data, EC_FOE_OPCODE_RRQ); // fsm read request + EC_WRITE_U32(data + 2, 0x00000000); // no passwd + memcpy(data + EC_FOE_HEADER_SIZE, fsm->rx_filename, current_size); + + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(fsm->slave, 1, "FoE Read Request:\n"); + ec_print_data(data, current_size + EC_FOE_HEADER_SIZE); + } + + return 0; +} + +/****************************************************************************/ + +/** Prepare to send an acknowledge. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_foe_prepare_send_ack( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data; + + data = ec_slave_mbox_prepare_send(fsm->slave, datagram, + EC_MBOX_TYPE_FOE, EC_FOE_HEADER_SIZE); + if (IS_ERR(data)) { + return -1; + } + + EC_WRITE_U16(data, EC_FOE_OPCODE_ACK); + EC_WRITE_U32(data + 2, fsm->rx_expected_packet_no); + + return 0; +} + +/****************************************************************************/ + +/** State: RRQ SENT. + * + * Checks is the previous transmit datagram succeeded and sends the next + * fragment, if necessary. + */ +void ec_fsm_foe_state_rrq_sent( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE RRQ: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + // slave did not put anything in the mailbox yet + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE RRQ failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_data_check; +} + +/****************************************************************************/ + +/** Starting state for read operations. + */ +void ec_fsm_foe_read_start( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + fsm->rx_buffer_offset = 0; + fsm->rx_expected_packet_no = 1; + fsm->rx_last_packet = 0; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (!(slave->sii.mailbox_protocols & EC_MBOX_FOE)) { + ec_foe_set_tx_error(fsm, FOE_MBOX_PROT_ERROR); + EC_SLAVE_ERR(slave, "Slave does not support FoE!\n"); + return; + } + + if (ec_foe_prepare_rrq_send(fsm, datagram)) { + ec_foe_set_rx_error(fsm, FOE_PROT_ERROR); + return; + } + + fsm->state = ec_fsm_foe_state_rrq_sent; +} + +/****************************************************************************/ + +/** Check for data. + */ +void ec_fsm_foe_state_data_check( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE DATA READ: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE DATA READ: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = (fsm->datagram->jiffies_received - + fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_FSM_FOE_TIMEOUT) { + ec_foe_set_tx_error(fsm, FOE_TIMEOUT_ERROR); + EC_SLAVE_ERR(slave, "Timeout while waiting for ack response.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_data_read; +} + +/****************************************************************************/ + +/** Start reading data. + */ +void ec_fsm_foe_state_data_read( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + size_t rec_size; + uint8_t *data, opCode, packet_no, mbox_prot; + + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to receive FoE DATA READ datagram: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE DATA READ failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + ec_foe_set_rx_error(fsm, FOE_MBOX_FETCH_ERROR); + return; + } + + if (mbox_prot != EC_MBOX_TYPE_FOE) { + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + ec_foe_set_rx_error(fsm, FOE_PROT_ERROR); + return; + } + + opCode = EC_READ_U8(data); + + if (opCode == EC_FOE_OPCODE_BUSY) { + if (ec_foe_prepare_send_ack(fsm, datagram)) { + ec_foe_set_rx_error(fsm, FOE_PROT_ERROR); + } + return; + } + + if (opCode == EC_FOE_OPCODE_ERR) { + fsm->request->error_code = EC_READ_U32(data + 2); + EC_SLAVE_ERR(slave, "Received FoE Error Request (code 0x%08x).\n", + fsm->request->error_code); + if (rec_size > 6) { + uint8_t text[256]; + strncpy(text, data + 6, min(rec_size - 6, sizeof(text))); + EC_SLAVE_ERR(slave, "FoE Error Text: %s\n", text); + } + ec_foe_set_rx_error(fsm, FOE_OPCODE_ERROR); + return; + } + + if (opCode != EC_FOE_OPCODE_DATA) { + EC_SLAVE_ERR(slave, "Received OPCODE %x, expected %x.\n", + opCode, EC_FOE_OPCODE_DATA); + fsm->request->error_code = 0x00000000; + ec_foe_set_rx_error(fsm, FOE_OPCODE_ERROR); + return; + } + + packet_no = EC_READ_U16(data + 2); + if (packet_no != fsm->rx_expected_packet_no) { + EC_SLAVE_ERR(slave, "Received unexpected packet number.\n"); + ec_foe_set_rx_error(fsm, FOE_PACKETNO_ERROR); + return; + } + + rec_size -= EC_FOE_HEADER_SIZE; + + if (fsm->rx_buffer_size >= fsm->rx_buffer_offset + rec_size) { + memcpy(fsm->rx_buffer + fsm->rx_buffer_offset, + data + EC_FOE_HEADER_SIZE, rec_size); + fsm->rx_buffer_offset += rec_size; + } + + fsm->rx_last_packet = + (rec_size + EC_MBOX_HEADER_SIZE + EC_FOE_HEADER_SIZE + != slave->configured_rx_mailbox_size); + + if (fsm->rx_last_packet || + (slave->configured_rx_mailbox_size - EC_MBOX_HEADER_SIZE + - EC_FOE_HEADER_SIZE + fsm->rx_buffer_offset) + <= fsm->rx_buffer_size) { + // either it was the last packet or a new packet will fit into the + // delivered buffer +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "last_packet=true\n"); +#endif + if (ec_foe_prepare_send_ack(fsm, datagram)) { + ec_foe_set_rx_error(fsm, FOE_RX_DATA_ACK_ERROR); + return; + } + + fsm->state = ec_fsm_foe_state_sent_ack; + } + else { + // no more data fits into the delivered buffer + // ... wait for new read request + EC_SLAVE_ERR(slave, "Data do not fit in receive buffer!\n"); + printk(KERN_CONT " rx_buffer_size = %d\n", fsm->rx_buffer_size); + printk(KERN_CONT "rx_buffer_offset = %d\n", fsm->rx_buffer_offset); + printk(KERN_CONT " rec_size = %zd\n", rec_size); + printk(KERN_CONT " rx_mailbox_size = %d\n", + slave->configured_rx_mailbox_size); + printk(KERN_CONT " rx_last_packet = %d\n", fsm->rx_last_packet); + fsm->request->result = FOE_READY; + } +} + +/****************************************************************************/ + +/** Sent an acknowledge. + */ +void ec_fsm_foe_state_sent_ack( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + +#ifdef DEBUG_FOE + EC_SLAVE_DBG(fsm->slave, 0, "%s()\n", __func__); +#endif + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + ec_foe_set_rx_error(fsm, FOE_RECEIVE_ERROR); + EC_SLAVE_ERR(slave, "Failed to send FoE ACK: "); + ec_datagram_print_state(fsm->datagram); + return; + } + + if (fsm->datagram->working_counter != 1) { + // slave did not put anything into the mailbox yet + ec_foe_set_rx_error(fsm, FOE_WC_ERROR); + EC_SLAVE_ERR(slave, "Reception of FoE ACK failed: "); + ec_datagram_print_wc_error(fsm->datagram); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + if (fsm->rx_last_packet) { + fsm->rx_expected_packet_no = 0; + fsm->request->data_size = fsm->rx_buffer_offset; + fsm->state = ec_fsm_foe_end; + } + else { + fsm->rx_expected_packet_no++; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_foe_state_data_check; + } +} + +/****************************************************************************/ + +/** Set an error code and go to the send error state. + */ +void ec_foe_set_tx_error( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + uint32_t errorcode /**< FoE error code. */ + ) +{ + fsm->request->result = errorcode; + fsm->state = ec_fsm_foe_error; +} + +/****************************************************************************/ + +/** Set an error code and go to the receive error state. + */ +void ec_foe_set_rx_error( + ec_fsm_foe_t *fsm, /**< FoE statemachine. */ + uint32_t errorcode /**< FoE error code. */ + ) +{ + fsm->request->result = errorcode; + fsm->state = ec_fsm_foe_error; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_foe.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_foe.h @@ -0,0 +1,87 @@ +/***************************************************************************** + * + * Copyright (C) 2008 Olav Zarges, imc Messsysteme GmbH + * 2009-2012 Florian Pose + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT FoE state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_FOE_H__ +#define __EC_FSM_FOE_H__ + +#include "globals.h" +#include "../include/ecrt.h" +#include "datagram.h" +#include "slave.h" +#include "foe_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_foe ec_fsm_foe_t; /**< \see ec_fsm_foe */ + +/** Finite state machines for the CANopen-over-EtherCAT protocol. + */ +struct ec_fsm_foe { + ec_slave_t *slave; /**< Slave the FSM runs on. */ + unsigned int retries; /**< Retries upon datagram timeout */ + + void (*state)(ec_fsm_foe_t *, ec_datagram_t *); /**< FoE state function. + */ + ec_datagram_t *datagram; /**< Datagram used in previous step. */ + unsigned long jiffies_start; /**< FoE timestamp. */ + uint8_t subindex; /**< Current subindex. */ + ec_foe_request_t *request; /**< FoE request. */ + uint8_t toggle; /**< Toggle bit for segment commands. */ + + uint8_t *tx_buffer; /**< Buffer with data to transmit. */ + uint32_t tx_buffer_size; /**< Size of data to transmit. */ + uint32_t tx_buffer_offset; /**< Offset of data to tranmit next. */ + uint32_t tx_last_packet; /**< Current packet is last one to send. */ + uint32_t tx_packet_no; /**< FoE packet number. */ + uint32_t tx_current_size; /**< Size of current packet to send. */ + uint8_t *tx_filename; /**< Name of file to transmit. */ + uint32_t tx_filename_len; /**< Lenth of transmit file name. */ + + uint8_t *rx_buffer; /**< Buffer for received data. */ + uint32_t rx_buffer_size; /**< Size of receive buffer. */ + uint32_t rx_buffer_offset; /**< Offset in receive buffer. */ + uint32_t rx_expected_packet_no; /**< Expected receive packet number. */ + uint32_t rx_last_packet; /**< Current packet is the last to receive. */ + uint8_t *rx_filename; /**< Name of the file to receive. */ + uint32_t rx_filename_len; /**< Length of the receive file name. */ +}; + +/****************************************************************************/ + +void ec_fsm_foe_init(ec_fsm_foe_t *); +void ec_fsm_foe_clear(ec_fsm_foe_t *); + +int ec_fsm_foe_exec(ec_fsm_foe_t *, ec_datagram_t *); +int ec_fsm_foe_success(const ec_fsm_foe_t *); + +void ec_fsm_foe_transfer(ec_fsm_foe_t *, ec_slave_t *, ec_foe_request_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_master.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_master.c @@ -0,0 +1,1472 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT master state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" +#ifdef EC_EOE +#include "ethernet.h" +#endif + +#include "fsm_master.h" +#include "fsm_foe.h" + +/****************************************************************************/ + +/** Time difference [ns] to tolerate without setting a new system time offset. + */ +#define EC_SYSTEM_TIME_TOLERANCE_NS 1000000 + +/****************************************************************************/ + +// prototypes for private methods +void ec_fsm_master_restart(ec_fsm_master_t *); +int ec_fsm_master_action_process_sii(ec_fsm_master_t *); +int ec_fsm_master_action_process_int_request(ec_fsm_master_t *); +void ec_fsm_master_action_idle(ec_fsm_master_t *); +void ec_fsm_master_action_next_slave_state(ec_fsm_master_t *); +void ec_fsm_master_action_configure(ec_fsm_master_t *); +u64 ec_fsm_master_dc_offset32(ec_fsm_master_t *, u64, u64, unsigned long); +u64 ec_fsm_master_dc_offset64(ec_fsm_master_t *, u64, u64, unsigned long); + +/****************************************************************************/ + +void ec_fsm_master_state_start(ec_fsm_master_t *); +void ec_fsm_master_state_broadcast(ec_fsm_master_t *); +void ec_fsm_master_state_read_state(ec_fsm_master_t *); +void ec_fsm_master_state_acknowledge(ec_fsm_master_t *); +void ec_fsm_master_state_configure_slave(ec_fsm_master_t *); +void ec_fsm_master_state_clear_addresses(ec_fsm_master_t *); +void ec_fsm_master_state_dc_measure_delays(ec_fsm_master_t *); +void ec_fsm_master_state_scan_slave(ec_fsm_master_t *); +void ec_fsm_master_state_dc_read_offset(ec_fsm_master_t *); +void ec_fsm_master_state_dc_write_offset(ec_fsm_master_t *); +void ec_fsm_master_state_assign_sii(ec_fsm_master_t *); +void ec_fsm_master_state_write_sii(ec_fsm_master_t *); +void ec_fsm_master_state_sdo_dictionary(ec_fsm_master_t *); +void ec_fsm_master_state_sdo_request(ec_fsm_master_t *); +void ec_fsm_master_state_soe_request(ec_fsm_master_t *); + +void ec_fsm_master_enter_clear_addresses(ec_fsm_master_t *); +void ec_fsm_master_enter_write_system_times(ec_fsm_master_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_master_init( + ec_fsm_master_t *fsm, /**< Master state machine. */ + ec_master_t *master, /**< EtherCAT master. */ + ec_datagram_t *datagram /**< Datagram object to use. */ + ) +{ + fsm->master = master; + fsm->datagram = datagram; + + // inits the member variables state, idle, dev_idx, link_state, + // slaves_responding, slave_states and rescan_required + ec_fsm_master_reset(fsm); + + fsm->retries = 0; + fsm->scan_jiffies = 0; + fsm->slave = NULL; + fsm->sii_request = NULL; + fsm->sii_index = 0; + fsm->sdo_request = NULL; + fsm->soe_request = NULL; + + // init sub-state-machines + ec_fsm_coe_init(&fsm->fsm_coe); + ec_fsm_soe_init(&fsm->fsm_soe); + ec_fsm_pdo_init(&fsm->fsm_pdo, &fsm->fsm_coe); +#ifdef EC_EOE + ec_fsm_eoe_init(&fsm->fsm_eoe); +#endif + ec_fsm_change_init(&fsm->fsm_change, fsm->datagram); + ec_fsm_slave_config_init(&fsm->fsm_slave_config, fsm->datagram, + &fsm->fsm_change, &fsm->fsm_coe, &fsm->fsm_soe, &fsm->fsm_pdo, + &fsm->fsm_eoe); + ec_fsm_slave_scan_init(&fsm->fsm_slave_scan, fsm->datagram, + &fsm->fsm_slave_config, &fsm->fsm_pdo); + ec_fsm_sii_init(&fsm->fsm_sii, fsm->datagram); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_master_clear( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + // clear sub-state machines + ec_fsm_coe_clear(&fsm->fsm_coe); + ec_fsm_soe_clear(&fsm->fsm_soe); + ec_fsm_pdo_clear(&fsm->fsm_pdo); +#ifdef EC_EOE + ec_fsm_eoe_clear(&fsm->fsm_eoe); +#endif + ec_fsm_change_clear(&fsm->fsm_change); + ec_fsm_slave_config_clear(&fsm->fsm_slave_config); + ec_fsm_slave_scan_clear(&fsm->fsm_slave_scan); + ec_fsm_sii_clear(&fsm->fsm_sii); +} + +/****************************************************************************/ + +/** Reset state machine. + */ +void ec_fsm_master_reset( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_device_index_t dev_idx; + + fsm->state = ec_fsm_master_state_start; + fsm->idle = 0; + fsm->dev_idx = EC_DEVICE_MAIN; + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(fsm->master); dev_idx++) { + fsm->link_state[dev_idx] = 0; + fsm->slaves_responding[dev_idx] = 0; + fsm->slave_states[dev_idx] = EC_SLAVE_STATE_UNKNOWN; + } + + fsm->rescan_required = 0; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * If the state machine's datagram is not sent or received yet, the execution + * of the state machine is delayed to the next cycle. + * + * \return true, if the state machine was executed + */ +int ec_fsm_master_exec( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + if (fsm->datagram->state == EC_DATAGRAM_SENT + || fsm->datagram->state == EC_DATAGRAM_QUEUED) { + // datagram was not sent or received yet. + return 0; + } + + fsm->state(fsm); + return 1; +} + +/****************************************************************************/ + +/** + * \return true, if the state machine is in an idle phase + */ +int ec_fsm_master_idle( + const ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + return fsm->idle; +} + +/****************************************************************************/ + +/** Restarts the master state machine. + */ +void ec_fsm_master_restart( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + fsm->dev_idx = EC_DEVICE_MAIN; + fsm->state = ec_fsm_master_state_start; + fsm->state(fsm); // execute immediately +} + +/***************************************************************************** + * Master state machine + ****************************************************************************/ + +/** Master state: START. + * + * Starts with getting slave count and slave states. + */ +void ec_fsm_master_state_start( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + fsm->idle = 1; + + // check for emergency requests + if (!list_empty(&master->emerg_reg_requests)) { + ec_reg_request_t *request; + + // get first request + request = list_entry(master->emerg_reg_requests.next, + ec_reg_request_t, list); + list_del_init(&request->list); // dequeue + request->state = EC_INT_REQUEST_BUSY; + + if (request->transfer_size > fsm->datagram->mem_size) { + EC_MASTER_ERR(master, "Emergency request data too large!\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + fsm->state(fsm); // continue + return; + } + + if (request->dir != EC_DIR_OUTPUT) { + EC_MASTER_ERR(master, "Emergency requests must be" + " write requests!\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + fsm->state(fsm); // continue + return; + } + + EC_MASTER_DBG(master, 1, "Writing emergency register request...\n"); + ec_datagram_apwr(fsm->datagram, request->ring_position, + request->address, request->transfer_size); + memcpy(fsm->datagram->data, request->data, request->transfer_size); + fsm->datagram->device_index = EC_DEVICE_MAIN; + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&master->request_queue); + return; + } + + ec_datagram_brd(fsm->datagram, 0x0130, 2); + ec_datagram_zero(fsm->datagram); + fsm->datagram->device_index = fsm->dev_idx; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_broadcast; +} + +/****************************************************************************/ + +/** Master state: BROADCAST. + * + * Processes the broadcast read slave count and slaves states. + */ +void ec_fsm_master_state_broadcast( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + unsigned int i, size; + ec_slave_t *slave; + ec_master_t *master = fsm->master; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + // bus topology change? + if (datagram->working_counter != fsm->slaves_responding[fsm->dev_idx]) { + fsm->rescan_required = 1; + fsm->slaves_responding[fsm->dev_idx] = datagram->working_counter; + EC_MASTER_INFO(master, "%u slave(s) responding on %s device. " + "Re-scanning on next possibility.\n", + fsm->slaves_responding[fsm->dev_idx], + ec_device_names[fsm->dev_idx != 0]); + } + + if (fsm->link_state[fsm->dev_idx] && + !master->devices[fsm->dev_idx].link_state) { + ec_device_index_t dev_idx; + + EC_MASTER_DBG(master, 1, "Master state machine detected " + "link down on %s device. Clearing slave list.\n", + ec_device_names[fsm->dev_idx != 0]); + +#ifdef EC_EOE + ec_master_eoe_stop(master); + ec_master_clear_eoe_handlers(master); +#endif + ec_master_clear_slaves(master); + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + fsm->slave_states[dev_idx] = 0x00; + fsm->slaves_responding[dev_idx] = 0; /* Reset to trigger rescan on + next link up. */ + } + } + fsm->link_state[fsm->dev_idx] = master->devices[fsm->dev_idx].link_state; + + if (datagram->state == EC_DATAGRAM_RECEIVED && + fsm->slaves_responding[fsm->dev_idx]) { + uint8_t states = EC_READ_U8(datagram->data); + if (states != fsm->slave_states[fsm->dev_idx]) { + // slave states changed + char state_str[EC_STATE_STRING_SIZE]; + fsm->slave_states[fsm->dev_idx] = states; + ec_state_string(states, state_str, 1); + EC_MASTER_INFO(master, "Slave states on %s device: %s.\n", + ec_device_names[fsm->dev_idx != 0], state_str); + } + } else { + fsm->slave_states[fsm->dev_idx] = 0x00; + } + + fsm->dev_idx++; + if (fsm->dev_idx < ec_master_num_devices(master)) { + // check number of responding slaves on next device + fsm->state = ec_fsm_master_state_start; + fsm->state(fsm); // execute immediately + return; + } + + if (fsm->rescan_required) { + down(&master->scan_sem); + if (!master->allow_scan) { + up(&master->scan_sem); + } else { + unsigned int count = 0, next_dev_slave, ring_position; + ec_device_index_t dev_idx; + + master->scan_busy = 1; + master->scan_index = 0; + up(&master->scan_sem); + + EC_MASTER_INFO(master, "Re-scanning now.\n"); + + // clear all slaves and scan the bus + fsm->rescan_required = 0; + fsm->idle = 0; + fsm->scan_jiffies = jiffies; + +#ifdef EC_EOE + ec_master_eoe_stop(master); + ec_master_clear_eoe_handlers(master); +#endif + ec_master_clear_slaves(master); + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + count += fsm->slaves_responding[dev_idx]; + } + + if (!count) { + // no slaves present -> finish state machine. + master->scan_busy = 0; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + size = sizeof(ec_slave_t) * count; + if (!(master->slaves = + (ec_slave_t *) kmalloc(size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %u bytes" + " of slave memory!\n", size); + master->scan_busy = 0; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + // init slaves + dev_idx = EC_DEVICE_MAIN; + next_dev_slave = fsm->slaves_responding[dev_idx]; + ring_position = 0; + for (i = 0; i < count; i++, ring_position++) { + slave = master->slaves + i; + while (i >= next_dev_slave) { + dev_idx++; + next_dev_slave += fsm->slaves_responding[dev_idx]; + ring_position = 0; + } + + ec_slave_init(slave, master, dev_idx, ring_position, i + 1); + + // do not force reconfiguration in operation phase to avoid + // unnecesssary process data interruptions + if (master->phase != EC_OPERATION) { + slave->force_config = 1; + } + } + master->slave_count = count; + master->fsm_slave = master->slaves; + + /* start with first device with slaves responding; at least one + * has responding slaves, otherwise count would be zero. */ + fsm->dev_idx = EC_DEVICE_MAIN; + while (!fsm->slaves_responding[fsm->dev_idx]) { + fsm->dev_idx++; + } + + ec_fsm_master_enter_clear_addresses(fsm); + return; + } + } + + if (master->slave_count) { + + // application applied configurations + if (master->config_changed) { + master->config_changed = 0; + + EC_MASTER_DBG(master, 1, "Configuration changed.\n"); + + fsm->slave = master->slaves; // begin with first slave + ec_fsm_master_enter_write_system_times(fsm); + + } else { + // fetch state from first slave + fsm->slave = master->slaves; + ec_datagram_fprd(fsm->datagram, fsm->slave->station_address, + 0x0130, 2); + ec_datagram_zero(datagram); + fsm->datagram->device_index = fsm->slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_read_state; + } + } else { + ec_fsm_master_restart(fsm); + } +} + +/****************************************************************************/ + +/** Check for pending SII write requests and process one. + * + * \return non-zero, if an SII write request is processed. + */ +int ec_fsm_master_action_process_sii( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_sii_write_request_t *request; + ec_slave_config_t *config; + ec_flag_t *flag; + int assign_to_pdi; + + // search the first request to be processed + while (1) { + if (list_empty(&master->sii_requests)) + break; + + // get first request + request = list_entry(master->sii_requests.next, + ec_sii_write_request_t, list); + list_del_init(&request->list); // dequeue + request->state = EC_INT_REQUEST_BUSY; + + assign_to_pdi = 0; + config = request->slave->config; + if (config) { + flag = ec_slave_config_find_flag(config, "AssignToPdi"); + if (flag) { + assign_to_pdi = flag->value; + } + } + + if (assign_to_pdi) { + fsm->sii_request = request; + EC_SLAVE_DBG(request->slave, 1, + "Assigning SII back to EtherCAT.\n"); + ec_datagram_fpwr(fsm->datagram, request->slave->station_address, + 0x0500, 0x01); + EC_WRITE_U8(fsm->datagram->data, 0x00); // EtherCAT + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_assign_sii; + return 1; + } + + // found pending SII write operation. execute it! + EC_SLAVE_DBG(request->slave, 1, "Writing SII data...\n"); + fsm->sii_request = request; + fsm->sii_index = 0; + ec_fsm_sii_write(&fsm->fsm_sii, request->slave, request->offset, + request->words, EC_FSM_SII_USE_CONFIGURED_ADDRESS); + fsm->state = ec_fsm_master_state_write_sii; + fsm->state(fsm); // execute immediately + return 1; + } + + return 0; +} + +/****************************************************************************/ + +/** Check for pending internal SDO/SoE requests and process one. + * + * \return non-zero, if an SDO request is processed. + */ +int ec_fsm_master_action_process_int_request( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_slave_t *slave; + ec_sdo_request_t *sdo_req; + ec_soe_request_t *soe_req; + + // search for internal requests to be processed + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + + if (!slave->config) { + continue; + } + + list_for_each_entry(sdo_req, &slave->config->sdo_requests, list) { + if (sdo_req->state == EC_INT_REQUEST_QUEUED) { + + if (ec_sdo_request_timed_out(sdo_req)) { + sdo_req->state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_DBG(slave, 1, "Internal SDO request" + " timed out.\n"); + continue; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + sdo_req->state = EC_INT_REQUEST_FAILURE; + continue; + } + + sdo_req->state = EC_INT_REQUEST_BUSY; + EC_SLAVE_DBG(slave, 1, "Processing internal" + " SDO request...\n"); + fsm->idle = 0; + fsm->sdo_request = sdo_req; + fsm->slave = slave; + fsm->state = ec_fsm_master_state_sdo_request; + ec_fsm_coe_transfer(&fsm->fsm_coe, slave, sdo_req); + ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram); + return 1; + } + } + + list_for_each_entry(soe_req, &slave->config->soe_requests, list) { + if (soe_req->state == EC_INT_REQUEST_QUEUED) { + + if (ec_soe_request_timed_out(soe_req)) { + soe_req->state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_DBG(slave, 1, "Internal SoE request" + " timed out.\n"); + continue; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + soe_req->state = EC_INT_REQUEST_FAILURE; + continue; + } + + soe_req->state = EC_INT_REQUEST_BUSY; + EC_SLAVE_DBG(slave, 1, "Processing internal" + " SoE request...\n"); + fsm->idle = 0; + fsm->soe_request = soe_req; + fsm->slave = slave; + fsm->state = ec_fsm_master_state_soe_request; + ec_fsm_soe_transfer(&fsm->fsm_soe, slave, soe_req); + ec_fsm_soe_exec(&fsm->fsm_soe, fsm->datagram); + return 1; + } + } + } + return 0; +} + +/****************************************************************************/ + +/** Master action: IDLE. + * + * Does secondary work. + */ +void ec_fsm_master_action_idle( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_slave_t *slave; + + // Check for pending internal SDO or SoE requests + if (ec_fsm_master_action_process_int_request(fsm)) { + return; + } + + // enable processing of requests + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_fsm_slave_set_ready(&slave->fsm); + } + + // check, if slaves have an SDO dictionary to read out. + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + if (!(slave->sii.mailbox_protocols & EC_MBOX_COE) + || (slave->sii.has_general + && !slave->sii.coe_details.enable_sdo_info) + || slave->sdo_dictionary_fetched + || slave->current_state == EC_SLAVE_STATE_INIT + || slave->current_state == EC_SLAVE_STATE_UNKNOWN + || jiffies - slave->jiffies_preop < EC_WAIT_SDO_DICT * HZ + ) continue; + + EC_SLAVE_DBG(slave, 1, "Fetching SDO dictionary.\n"); + + slave->sdo_dictionary_fetched = 1; + + // start fetching SDO dictionary + fsm->idle = 0; + fsm->slave = slave; + fsm->state = ec_fsm_master_state_sdo_dictionary; + ec_fsm_coe_dictionary(&fsm->fsm_coe, slave); + ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; + return; + } + + // check for pending SII write operations. + if (ec_fsm_master_action_process_sii(fsm)) { + return; // SII write request found + } + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master action: Get state of next slave. + */ +void ec_fsm_master_action_next_slave_state( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + // is there another slave to query? + fsm->slave++; + if (fsm->slave < master->slaves + master->slave_count) { + // fetch state from next slave + fsm->idle = 1; + ec_datagram_fprd(fsm->datagram, + fsm->slave->station_address, 0x0130, 2); + ec_datagram_zero(fsm->datagram); + fsm->datagram->device_index = fsm->slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_read_state; + return; + } + + // all slaves processed + ec_fsm_master_action_idle(fsm); +} + +/****************************************************************************/ + +/** Master action: Configure. + */ +void ec_fsm_master_action_configure( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_slave_t *slave = fsm->slave; + + if (master->config_changed) { + master->config_changed = 0; + + // abort iterating through slaves, + // first compensate DC system time offsets, + // then begin configuring at slave 0 + EC_MASTER_DBG(master, 1, "Configuration changed" + " (aborting state check).\n"); + + fsm->slave = master->slaves; // begin with first slave + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + // Does the slave have to be configured? + if ((slave->current_state != slave->requested_state + || slave->force_config) && !slave->error_flag) { + + // Start slave configuration + down(&master->config_sem); + master->config_busy = 1; + up(&master->config_sem); + + if (master->debug_level) { + char old_state[EC_STATE_STRING_SIZE], + new_state[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, old_state, 0); + ec_state_string(slave->requested_state, new_state, 0); + EC_SLAVE_DBG(slave, 1, "Changing state from %s to %s%s.\n", + old_state, new_state, + slave->force_config ? " (forced)" : ""); + } + + fsm->idle = 0; + fsm->state = ec_fsm_master_state_configure_slave; + ec_fsm_slave_config_start(&fsm->fsm_slave_config, slave); + fsm->state(fsm); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; + return; + } + + // process next slave + ec_fsm_master_action_next_slave_state(fsm); +} + +/****************************************************************************/ + +/** Master state: READ STATE. + * + * Fetches the AL state of a slave. + */ +void ec_fsm_master_state_read_state( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive AL state datagram: "); + ec_datagram_print_state(datagram); + ec_fsm_master_restart(fsm); + return; + } + + // did the slave not respond to its station address? + if (datagram->working_counter != 1) { + if (!slave->error_flag) { + slave->error_flag = 1; + EC_SLAVE_DBG(slave, 1, "Slave did not respond to state query.\n"); + } + ec_fsm_master_restart(fsm); + return; + } + + // A single slave responded + ec_slave_set_state(slave, EC_READ_U8(datagram->data)); + + if (!slave->error_flag) { + // Check, if new slave state has to be acknowledged + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + fsm->idle = 0; + fsm->state = ec_fsm_master_state_acknowledge; + ec_fsm_change_ack(&fsm->fsm_change, slave); + fsm->state(fsm); // execute immediately + return; + } + + // No acknowlegde necessary; check for configuration + ec_fsm_master_action_configure(fsm); + return; + } + + // slave has error flag set; process next one + ec_fsm_master_action_next_slave_state(fsm); +} + +/****************************************************************************/ + +/** Master state: ACKNOWLEDGE. + */ +void ec_fsm_master_state_acknowledge( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_change_exec(&fsm->fsm_change)) { + return; + } + + if (!ec_fsm_change_success(&fsm->fsm_change)) { + fsm->slave->error_flag = 1; + EC_SLAVE_ERR(slave, "Failed to acknowledge state change.\n"); + } + + ec_fsm_master_action_configure(fsm); +} + +/****************************************************************************/ + +/** Start clearing slave addresses. + */ +void ec_fsm_master_enter_clear_addresses( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + // broadcast clear all station addresses + ec_datagram_bwr(fsm->datagram, 0x0010, 2); + EC_WRITE_U16(fsm->datagram->data, 0x0000); + fsm->datagram->device_index = fsm->dev_idx; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_clear_addresses; +} + +/****************************************************************************/ + +/** Master state: CLEAR ADDRESSES. + */ +void ec_fsm_master_state_clear_addresses( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_MASTER_ERR(master, "Failed to receive address" + " clearing datagram on %s link: ", + ec_device_names[fsm->dev_idx != 0]); + ec_datagram_print_state(datagram); + master->scan_busy = 0; + master->scan_index = master->slave_count; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + if (datagram->working_counter != fsm->slaves_responding[fsm->dev_idx]) { + EC_MASTER_WARN(master, "Failed to clear station addresses on %s link:" + " Cleared %u of %u", + ec_device_names[fsm->dev_idx != 0], datagram->working_counter, + fsm->slaves_responding[fsm->dev_idx]); + } + + EC_MASTER_DBG(master, 1, "Sending broadcast-write" + " to measure transmission delays on %s link.\n", + ec_device_names[fsm->dev_idx != 0]); + + ec_datagram_bwr(datagram, 0x0900, 1); + ec_datagram_zero(datagram); + fsm->datagram->device_index = fsm->dev_idx; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_dc_measure_delays; +} + +/****************************************************************************/ + +/** Master state: DC MEASURE DELAYS. + */ +void ec_fsm_master_state_dc_measure_delays( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_MASTER_ERR(master, "Failed to receive delay measuring datagram" + " on %s link: ", ec_device_names[fsm->dev_idx != 0]); + ec_datagram_print_state(datagram); + master->scan_busy = 0; + master->scan_index = master->slave_count; + wake_up_interruptible(&master->scan_queue); + ec_fsm_master_restart(fsm); + return; + } + + EC_MASTER_DBG(master, 1, "%u slaves responded to delay measuring" + " on %s link.\n", + datagram->working_counter, ec_device_names[fsm->dev_idx != 0]); + + do { + fsm->dev_idx++; + } while (fsm->dev_idx < ec_master_num_devices(master) && + !fsm->slaves_responding[fsm->dev_idx]); + if (fsm->dev_idx < ec_master_num_devices(master)) { + ec_fsm_master_enter_clear_addresses(fsm); + return; + } + + EC_MASTER_INFO(master, "Scanning bus.\n"); + + // begin scanning of slaves + fsm->slave = master->slaves; + master->scan_index = 0; + EC_MASTER_DBG(master, 1, "Scanning slave %u on %s link.\n", + fsm->slave->ring_position, + ec_device_names[fsm->slave->device_index != 0]); + fsm->state = ec_fsm_master_state_scan_slave; + ec_fsm_slave_scan_start(&fsm->fsm_slave_scan, fsm->slave); + ec_fsm_slave_scan_exec(&fsm->fsm_slave_scan); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; +} + +/****************************************************************************/ + +/** Master state: SCAN SLAVE. + * + * Executes the sub-statemachine for the scanning of a slave. + */ +void ec_fsm_master_state_scan_slave( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; +#ifdef EC_EOE + ec_slave_t *slave = fsm->slave; +#endif + + if (ec_fsm_slave_scan_exec(&fsm->fsm_slave_scan)) { + return; + } + +#ifdef EC_EOE + if (slave->sii.mailbox_protocols & EC_MBOX_EOE) { + // create EoE handler for this slave + ec_eoe_t *eoe; + if (!(eoe = kmalloc(sizeof(ec_eoe_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate EoE handler memory!\n"); + } else if (ec_eoe_init(eoe, slave)) { + EC_SLAVE_ERR(slave, "Failed to init EoE handler!\n"); + kfree(eoe); + } else { + list_add_tail(&eoe->list, &master->eoe_handlers); + } + } +#endif + + // another slave to fetch? + fsm->slave++; + master->scan_index++; + if (fsm->slave < master->slaves + master->slave_count) { + EC_MASTER_DBG(master, 1, "Scanning slave %u on %s link.\n", + fsm->slave->ring_position, + ec_device_names[fsm->slave->device_index != 0]); + ec_fsm_slave_scan_start(&fsm->fsm_slave_scan, fsm->slave); + ec_fsm_slave_scan_exec(&fsm->fsm_slave_scan); // execute immediately + fsm->datagram->device_index = fsm->slave->device_index; + return; + } + + EC_MASTER_INFO(master, "Bus scanning completed in %lu ms.\n", + (jiffies - fsm->scan_jiffies) * 1000 / HZ); + + master->scan_busy = 0; + master->scan_index = master->slave_count; + wake_up_interruptible(&master->scan_queue); + + ec_master_calc_dc(master); + + // Attach slave configurations + ec_master_attach_slave_configs(master); + +#ifdef EC_EOE + // check if EoE processing has to be started + ec_master_eoe_start(master); +#endif + + if (master->slave_count) { + master->config_changed = 0; + + fsm->slave = master->slaves; // begin with first slave + ec_fsm_master_enter_write_system_times(fsm); + } else { + ec_fsm_master_restart(fsm); + } +} + +/****************************************************************************/ + +/** Master state: CONFIGURE SLAVE. + * + * Starts configuring a slave. + */ +void ec_fsm_master_state_configure_slave( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + if (ec_fsm_slave_config_exec(&fsm->fsm_slave_config)) { + return; + } + + fsm->slave->force_config = 0; + + // configuration finished + master->config_busy = 0; + wake_up_interruptible(&master->config_queue); + + if (!ec_fsm_slave_config_success(&fsm->fsm_slave_config)) { + // TODO: mark slave_config as failed. + } + + fsm->idle = 1; + ec_fsm_master_action_next_slave_state(fsm); +} + +/****************************************************************************/ + +/** Start writing DC system times. + */ +void ec_fsm_master_enter_write_system_times( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + + if (master->dc_ref_time) { + + while (fsm->slave < master->slaves + master->slave_count) { + if (!fsm->slave->base_dc_supported + || !fsm->slave->has_dc_system_time) { + fsm->slave++; + continue; + } + + EC_SLAVE_DBG(fsm->slave, 1, "Checking system time offset.\n"); + + // read DC system time (0x0910, 64 bit) + // gap (64 bit) + // and time offset (0x0920, 64 bit) + ec_datagram_fprd(fsm->datagram, fsm->slave->station_address, + 0x0910, 24); + fsm->datagram->device_index = fsm->slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_dc_read_offset; + return; + } + + } else { + if (master->active) { + EC_MASTER_WARN(master, "No application time received up to now," + " but master already active.\n"); + } else { + EC_MASTER_DBG(master, 1, "No app_time received up to now.\n"); + } + } + + // scanning and setting system times complete + ec_master_request_op(master); + EC_MASTER_DBG(master, 1, "After requesting OP, rescan_required is %u.\n", + fsm->rescan_required); + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Configure 32 bit time offset. + * + * \return New offset. + */ +u64 ec_fsm_master_dc_offset32( + ec_fsm_master_t *fsm, /**< Master state machine. */ + u64 system_time, /**< System time register. */ + u64 old_offset, /**< Time offset register. */ + unsigned long jiffies_since_read /**< Jiffies for correction. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u32 correction, system_time32, old_offset32, new_offset; + s32 time_diff; + + system_time32 = (u32) system_time; + old_offset32 = (u32) old_offset; + + // correct read system time by elapsed time since read operation + correction = jiffies_since_read * 1000 / HZ * 1000000; + system_time32 += correction; + time_diff = (u32) slave->master->app_time - system_time32; + + EC_SLAVE_DBG(slave, 1, "DC 32 bit system time offset calculation:" + " system_time=%u (corrected with %u)," + " app_time=%llu, diff=%i\n", + system_time32, correction, + slave->master->app_time, time_diff); + + if (EC_ABS(time_diff) > EC_SYSTEM_TIME_TOLERANCE_NS) { + new_offset = time_diff + old_offset32; + EC_SLAVE_DBG(slave, 1, "Setting time offset to %u (was %u)\n", + new_offset, old_offset32); + return (u64) new_offset; + } else { + EC_SLAVE_DBG(slave, 1, "Not touching time offset.\n"); + return old_offset; + } +} + +/****************************************************************************/ + +/** Configure 64 bit time offset. + * + * \return New offset. + */ +u64 ec_fsm_master_dc_offset64( + ec_fsm_master_t *fsm, /**< Master state machine. */ + u64 system_time, /**< System time register. */ + u64 old_offset, /**< Time offset register. */ + unsigned long jiffies_since_read /**< Jiffies for correction. */ + ) +{ + ec_slave_t *slave = fsm->slave; + u64 new_offset, correction; + s64 time_diff; + + // correct read system time by elapsed time since read operation + correction = (u64) (jiffies_since_read * 1000 / HZ) * 1000000; + system_time += correction; + time_diff = fsm->slave->master->app_time - system_time; + + EC_SLAVE_DBG(slave, 1, "DC 64 bit system time offset calculation:" + " system_time=%llu (corrected with %llu)," + " app_time=%llu, diff=%lli\n", + system_time, correction, + slave->master->app_time, time_diff); + + if (EC_ABS(time_diff) > EC_SYSTEM_TIME_TOLERANCE_NS) { + new_offset = time_diff + old_offset; + EC_SLAVE_DBG(slave, 1, "Setting time offset to %llu (was %llu)\n", + new_offset, old_offset); + } else { + new_offset = old_offset; + EC_SLAVE_DBG(slave, 1, "Not touching time offset.\n"); + } + + return new_offset; +} + +/****************************************************************************/ + +/** Master state: DC READ OFFSET. + */ +void ec_fsm_master_state_dc_read_offset( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + u64 system_time, old_offset, new_offset; + unsigned long jiffies_since_read; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive DC times datagram: "); + ec_datagram_print_state(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to get DC times: "); + ec_datagram_print_wc_error(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + system_time = EC_READ_U64(datagram->data); // 0x0910 + old_offset = EC_READ_U64(datagram->data + 16); // 0x0920 + jiffies_since_read = jiffies - datagram->jiffies_sent; + + if (slave->base_dc_range == EC_DC_32) { + new_offset = ec_fsm_master_dc_offset32(fsm, + system_time, old_offset, jiffies_since_read); + } else { + new_offset = ec_fsm_master_dc_offset64(fsm, + system_time, old_offset, jiffies_since_read); + } + + // set DC system time offset and transmission delay + ec_datagram_fpwr(datagram, slave->station_address, 0x0920, 12); + EC_WRITE_U64(datagram->data, new_offset); + EC_WRITE_U32(datagram->data + 8, slave->transmission_delay); + fsm->datagram->device_index = slave->device_index; + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_master_state_dc_write_offset; +} + +/****************************************************************************/ + +/** Master state: DC WRITE OFFSET. + */ +void ec_fsm_master_state_dc_write_offset( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, + "Failed to receive DC system time offset datagram: "); + ec_datagram_print_state(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_ERR(slave, "Failed to set DC system time offset: "); + ec_datagram_print_wc_error(datagram); + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); + return; + } + + fsm->slave++; + ec_fsm_master_enter_write_system_times(fsm); +} + +/****************************************************************************/ + +/** Master state: ASSIGN SII. + */ +void ec_fsm_master_state_assign_sii( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_sii_write_request_t *request = fsm->sii_request; + ec_slave_t *slave = request->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + goto cont; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_ERR(slave, "Failed to assign SII back to EtherCAT: "); + ec_datagram_print_wc_error(datagram); + goto cont; + } + +cont: + // found pending SII write operation. execute it! + EC_SLAVE_DBG(slave, 1, "Writing SII data (after assignment)...\n"); + fsm->sii_index = 0; + ec_fsm_sii_write(&fsm->fsm_sii, slave, request->offset, + request->words, EC_FSM_SII_USE_CONFIGURED_ADDRESS); + fsm->state = ec_fsm_master_state_write_sii; + fsm->state(fsm); // execute immediately +} + +/****************************************************************************/ + +/** Master state: WRITE SII. + */ +void ec_fsm_master_state_write_sii( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_master_t *master = fsm->master; + ec_sii_write_request_t *request = fsm->sii_request; + ec_slave_t *slave = request->slave; + + if (ec_fsm_sii_exec(&fsm->fsm_sii)) return; + + if (!ec_fsm_sii_success(&fsm->fsm_sii)) { + EC_SLAVE_ERR(slave, "Failed to write SII data.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + ec_fsm_master_restart(fsm); + return; + } + + fsm->sii_index++; + if (fsm->sii_index < request->nwords) { + ec_fsm_sii_write(&fsm->fsm_sii, slave, + request->offset + fsm->sii_index, + request->words + fsm->sii_index, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute immediately + return; + } + + // finished writing SII + EC_SLAVE_DBG(slave, 1, "Finished writing %zu words of SII data.\n", + request->nwords); + + if (request->offset <= 4 && request->offset + request->nwords > 4) { + // alias was written + slave->sii.alias = EC_READ_U16(request->words + 4); + // TODO: read alias from register 0x0012 + slave->effective_alias = slave->sii.alias; + } + // TODO: Evaluate other SII contents! + + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&master->request_queue); + + // check for another SII write request + if (ec_fsm_master_action_process_sii(fsm)) + return; // processing another request + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master state: SDO DICTIONARY. + */ +void ec_fsm_master_state_sdo_dictionary( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = fsm->master; + + if (ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram)) { + return; + } + + if (!ec_fsm_coe_success(&fsm->fsm_coe)) { + ec_fsm_master_restart(fsm); + return; + } + + // SDO dictionary fetching finished + + if (master->debug_level) { + unsigned int sdo_count, entry_count; + ec_slave_sdo_dict_info(slave, &sdo_count, &entry_count); + EC_SLAVE_DBG(slave, 1, "Fetched %u SDOs and %u entries.\n", + sdo_count, entry_count); + } + + // attach pdo names from dictionary + ec_slave_attach_pdo_names(slave); + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master state: SDO REQUEST. + */ +void ec_fsm_master_state_sdo_request( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_sdo_request_t *request = fsm->sdo_request; + + if (!request) { + // configuration was cleared in the meantime + ec_fsm_master_restart(fsm); + return; + } + + if (ec_fsm_coe_exec(&fsm->fsm_coe, fsm->datagram)) { + return; + } + + if (!ec_fsm_coe_success(&fsm->fsm_coe)) { + EC_SLAVE_DBG(fsm->slave, 1, + "Failed to process internal SDO request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->master->request_queue); + ec_fsm_master_restart(fsm); + return; + } + + // SDO request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&fsm->master->request_queue); + + EC_SLAVE_DBG(fsm->slave, 1, "Finished internal SDO request.\n"); + + // check for another SDO/SoE request + if (ec_fsm_master_action_process_int_request(fsm)) { + return; // processing another request + } + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ + +/** Master state: SoE REQUEST. + */ +void ec_fsm_master_state_soe_request( + ec_fsm_master_t *fsm /**< Master state machine. */ + ) +{ + ec_soe_request_t *request = fsm->soe_request; + + if (!request) { + // configuration was cleared in the meantime + ec_fsm_master_restart(fsm); + return; + } + + if (ec_fsm_soe_exec(&fsm->fsm_soe, fsm->datagram)) { + return; + } + + if (!ec_fsm_soe_success(&fsm->fsm_soe)) { + EC_SLAVE_DBG(fsm->slave, 1, + "Failed to process internal SoE request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->master->request_queue); + ec_fsm_master_restart(fsm); + return; + } + + // SoE request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&fsm->master->request_queue); + + EC_SLAVE_DBG(fsm->slave, 1, "Finished internal SoE request.\n"); + + // check for another CoE/SoE request + if (ec_fsm_master_action_process_int_request(fsm)) { + return; // processing another request + } + + ec_fsm_master_restart(fsm); +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_master.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_master.h @@ -0,0 +1,107 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_MASTER_H__ +#define __EC_FSM_MASTER_H__ + +#include "globals.h" +#include "datagram.h" +#include "foe_request.h" +#include "sdo_request.h" +#include "soe_request.h" +#include "fsm_slave_config.h" +#include "fsm_slave_scan.h" +#include "fsm_pdo.h" + +/****************************************************************************/ + +/** SII write request. + */ +typedef struct { + struct list_head list; /**< List head. */ + ec_slave_t *slave; /**< EtherCAT slave. */ + uint16_t offset; /**< SII word offset. */ + size_t nwords; /**< Number of words. */ + const uint16_t *words; /**< Pointer to the data words. */ + ec_internal_request_state_t state; /**< State of the request. */ +} ec_sii_write_request_t; + +/****************************************************************************/ + +typedef struct ec_fsm_master ec_fsm_master_t; /**< \see ec_fsm_master */ + +/** Finite state machine of an EtherCAT master. + */ +struct ec_fsm_master { + ec_master_t *master; /**< master the FSM runs on */ + ec_datagram_t *datagram; /**< datagram used in the state machine */ + unsigned int retries; /**< retries on datagram timeout. */ + + void (*state)(ec_fsm_master_t *); /**< master state function */ + ec_device_index_t dev_idx; /**< Current device index (for scanning etc.). + */ + int idle; /**< state machine is in idle phase */ + unsigned long scan_jiffies; /**< beginning of slave scanning */ + uint8_t link_state[EC_MAX_NUM_DEVICES]; /**< Last link state for every + device. */ + unsigned int slaves_responding[EC_MAX_NUM_DEVICES]; /**< Number of + responding slaves + for every device. */ + unsigned int rescan_required; /**< A bus rescan is required. */ + ec_slave_state_t slave_states[EC_MAX_NUM_DEVICES]; /**< AL states of + responding slaves for + every device. */ + ec_slave_t *slave; /**< current slave */ + ec_sii_write_request_t *sii_request; /**< SII write request */ + off_t sii_index; /**< index to SII write request data */ + ec_sdo_request_t *sdo_request; /**< SDO request to process. */ + ec_soe_request_t *soe_request; /**< SoE request to process. */ + + ec_fsm_coe_t fsm_coe; /**< CoE state machine */ + ec_fsm_soe_t fsm_soe; /**< SoE state machine */ + ec_fsm_pdo_t fsm_pdo; /**< PDO configuration state machine. */ + ec_fsm_eoe_t fsm_eoe; /**< EoE state machine */ + ec_fsm_change_t fsm_change; /**< State change state machine */ + ec_fsm_slave_config_t fsm_slave_config; /**< slave state machine */ + ec_fsm_slave_scan_t fsm_slave_scan; /**< slave state machine */ + ec_fsm_sii_t fsm_sii; /**< SII state machine */ +}; + +/****************************************************************************/ + +void ec_fsm_master_init(ec_fsm_master_t *, ec_master_t *, ec_datagram_t *); +void ec_fsm_master_clear(ec_fsm_master_t *); + +void ec_fsm_master_reset(ec_fsm_master_t *); + +int ec_fsm_master_exec(ec_fsm_master_t *); +int ec_fsm_master_idle(const ec_fsm_master_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_pdo.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_pdo.c @@ -0,0 +1,806 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT PDO configuration state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_pdo.h" + +/****************************************************************************/ + +// prototypes for private methods +void ec_fsm_pdo_print(const ec_fsm_pdo_t *); +int ec_fsm_pdo_running(const ec_fsm_pdo_t *); +ec_pdo_t *ec_fsm_pdo_conf_action_next_pdo(const ec_fsm_pdo_t *, + const struct list_head *); + +/****************************************************************************/ + +void ec_fsm_pdo_read_state_start(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_state_pdo_count(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_state_pdo(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_state_pdo_entries(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_read_action_next_sync(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_read_action_next_pdo(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_conf_state_start(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_read_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_zero_pdo_count(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_assign_pdo(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_state_set_pdo_count(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_conf_action_next_sync(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_pdo_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_check_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_next_pdo_mapping(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_check_assignment(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_conf_action_assign_pdo(ec_fsm_pdo_t *, ec_datagram_t *); + +void ec_fsm_pdo_state_end(ec_fsm_pdo_t *, ec_datagram_t *); +void ec_fsm_pdo_state_error(ec_fsm_pdo_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_pdo_init( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_fsm_coe_t *fsm_coe /**< CoE state machine to use */ + ) +{ + fsm->fsm_coe = fsm_coe; + ec_fsm_pdo_entry_init(&fsm->fsm_pdo_entry, fsm_coe); + ec_pdo_list_init(&fsm->pdos); + ec_sdo_request_init(&fsm->request); + ec_pdo_init(&fsm->slave_pdo); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_pdo_clear( + ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + ec_fsm_pdo_entry_clear(&fsm->fsm_pdo_entry); + ec_pdo_list_clear(&fsm->pdos); + ec_sdo_request_clear(&fsm->request); + ec_pdo_clear(&fsm->slave_pdo); +} + +/****************************************************************************/ + +/** Print the current and desired PDO assignment. + */ +void ec_fsm_pdo_print( + const ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + printk(KERN_CONT "Currently assigned PDOs: "); + ec_pdo_list_print(&fsm->sync->pdos); + printk(KERN_CONT ". PDOs to assign: "); + ec_pdo_list_print(&fsm->pdos); + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Start reading the PDO configuration. + */ +void ec_fsm_pdo_start_reading( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_pdo_read_state_start; +} + +/****************************************************************************/ + +/** Start writing the PDO configuration. + */ +void ec_fsm_pdo_start_configuration( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_pdo_conf_state_start; +} + +/****************************************************************************/ + +/** Get running state. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_running( + const ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + return fsm->state != ec_fsm_pdo_state_end + && fsm->state != ec_fsm_pdo_state_error; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * If the state machine's datagram is not sent or received yet, the execution + * of the state machine is delayed to the next cycle. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_exec( + ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + fsm->state(fsm, datagram); + + return ec_fsm_pdo_running(fsm); +} + +/****************************************************************************/ + +/** Get execution result. + * + * \return true, if the state machine terminated gracefully + */ +int ec_fsm_pdo_success( + const ec_fsm_pdo_t *fsm /**< PDO configuration state machine. */ + ) +{ + return fsm->state == ec_fsm_pdo_state_end; +} + +/***************************************************************************** + * Reading state funtions. + ****************************************************************************/ + +/** Start reading PDO assignment. + */ +void ec_fsm_pdo_read_state_start( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // read PDO assignment for first sync manager not reserved for mailbox + fsm->sync_index = 1; // next is 2 + ec_fsm_pdo_read_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Read PDO assignment of next sync manager. + */ +void ec_fsm_pdo_read_action_next_sync( + ec_fsm_pdo_t *fsm, /**< finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + fsm->sync_index++; + + for (; fsm->sync_index < EC_MAX_SYNC_MANAGERS; fsm->sync_index++) { + if (!(fsm->sync = ec_slave_get_sync(slave, fsm->sync_index))) + continue; + + EC_SLAVE_DBG(slave, 1, "Reading PDO assignment of SM%u.\n", + fsm->sync_index); + + ec_pdo_list_clear_pdos(&fsm->pdos); + + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, 0); + ecrt_sdo_request_read(&fsm->request); + fsm->state = ec_fsm_pdo_read_state_pdo_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + EC_SLAVE_DBG(slave, 1, "Reading of PDO configuration finished.\n"); + + ec_pdo_list_clear_pdos(&fsm->pdos); + fsm->state = ec_fsm_pdo_state_end; +} + +/****************************************************************************/ + +/** Count assigned PDOs. + */ +void ec_fsm_pdo_read_state_pdo_count( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read number of assigned PDOs" + " for SM%u.\n", fsm->sync_index); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + if (fsm->request.data_size != sizeof(uint8_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu returned" + " when uploading SDO 0x%04X:%02X.\n", fsm->request.data_size, + fsm->request.index, fsm->request.subindex); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + fsm->pdo_count = EC_READ_U8(fsm->request.data); + + EC_SLAVE_DBG(fsm->slave, 1, "%u PDOs assigned.\n", fsm->pdo_count); + + // read first PDO + fsm->pdo_pos = 1; + ec_fsm_pdo_read_action_next_pdo(fsm, datagram); +} + +/****************************************************************************/ + +/** Read next PDO. + */ +void ec_fsm_pdo_read_action_next_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (fsm->pdo_pos <= fsm->pdo_count) { + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, + fsm->pdo_pos); + ecrt_sdo_request_read(&fsm->request); + fsm->state = ec_fsm_pdo_read_state_pdo; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // finished reading PDO configuration + + ec_pdo_list_copy(&fsm->sync->pdos, &fsm->pdos); + ec_pdo_list_clear_pdos(&fsm->pdos); + + // next sync manager + ec_fsm_pdo_read_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Fetch PDO information. + */ +void ec_fsm_pdo_read_state_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read index of" + " assigned PDO %u from SM%u.\n", + fsm->pdo_pos, fsm->sync_index); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + if (fsm->request.data_size != sizeof(uint16_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu returned" + " when uploading SDO 0x%04X:%02X.\n", fsm->request.data_size, + fsm->request.index, fsm->request.subindex); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + if (!(fsm->pdo = (ec_pdo_t *) + kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_SLAVE_ERR(fsm->slave, "Failed to allocate PDO.\n"); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + ec_pdo_init(fsm->pdo); + fsm->pdo->index = EC_READ_U16(fsm->request.data); + fsm->pdo->sync_index = fsm->sync_index; + + EC_SLAVE_DBG(fsm->slave, 1, "PDO 0x%04X.\n", fsm->pdo->index); + + list_add_tail(&fsm->pdo->list, &fsm->pdos.list); + + fsm->state = ec_fsm_pdo_read_state_pdo_entries; + ec_fsm_pdo_entry_start_reading(&fsm->fsm_pdo_entry, fsm->slave, fsm->pdo); + fsm->state(fsm, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Fetch PDO information. + */ +void ec_fsm_pdo_read_state_pdo_entries( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_pdo_entry_exec(&fsm->fsm_pdo_entry, datagram)) { + return; + } + + if (!ec_fsm_pdo_entry_success(&fsm->fsm_pdo_entry)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read mapped PDO entries" + " for PDO 0x%04X.\n", fsm->pdo->index); + ec_fsm_pdo_read_action_next_sync(fsm, datagram); + return; + } + + // next PDO + fsm->pdo_pos++; + ec_fsm_pdo_read_action_next_pdo(fsm, datagram); +} + +/***************************************************************************** + * Writing state functions. + ****************************************************************************/ + +/** Start PDO configuration. + */ +void ec_fsm_pdo_conf_state_start( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (!fsm->slave->config) { + fsm->state = ec_fsm_pdo_state_end; + return; + } + + fsm->sync_index = 1; // next is 2 + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Assign next PDO. + * + * \return Next PDO, or NULL. + */ +ec_pdo_t *ec_fsm_pdo_conf_action_next_pdo( + const ec_fsm_pdo_t *fsm, /**< PDO configuration state machine. */ + const struct list_head *list /**< current PDO list item */ + ) +{ + list = list->next; + if (list == &fsm->pdos.list) + return NULL; // no next PDO + return list_entry(list, ec_pdo_t, list); +} + +/****************************************************************************/ + +/** Get the next sync manager for a pdo configuration. + */ +void ec_fsm_pdo_conf_action_next_sync( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + fsm->sync_index++; + + for (; fsm->sync_index < EC_MAX_SYNC_MANAGERS; fsm->sync_index++) { + if (!fsm->slave->config) { + // slave configuration removed in the meantime + fsm->state = ec_fsm_pdo_state_error; + return; + } + + if (ec_pdo_list_copy(&fsm->pdos, + &fsm->slave->config->sync_configs[fsm->sync_index].pdos)) + { + fsm->state = ec_fsm_pdo_state_error; + return; + } + + if (!(fsm->sync = ec_slave_get_sync(fsm->slave, fsm->sync_index))) { + if (!list_empty(&fsm->pdos.list)) + EC_SLAVE_WARN(fsm->slave, "PDOs configured for SM%u," + " but slave does not provide the" + " sync manager information!\n", + fsm->sync_index); + continue; + } + + // get first configured PDO + if (!(fsm->pdo = + ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdos.list))) { + // no pdos configured + ec_fsm_pdo_conf_action_check_assignment(fsm, datagram); + return; + } + + ec_fsm_pdo_conf_action_pdo_mapping(fsm, datagram); + return; + } + + fsm->state = ec_fsm_pdo_state_end; +} + +/****************************************************************************/ + +/** Check if the mapping has to be read, otherwise start to configure it. + */ +void ec_fsm_pdo_conf_action_pdo_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + const ec_pdo_t *assigned_pdo; + + fsm->slave_pdo.index = fsm->pdo->index; + + if ((assigned_pdo = ec_slave_find_pdo(fsm->slave, fsm->pdo->index))) { + ec_pdo_copy_entries(&fsm->slave_pdo, assigned_pdo); + } else { // configured PDO is not assigned and thus unknown + ec_pdo_clear_entries(&fsm->slave_pdo); + } + + if (list_empty(&fsm->slave_pdo.entries)) { + EC_SLAVE_DBG(fsm->slave, 1, "Reading mapping of PDO 0x%04X.\n", + fsm->pdo->index); + + // pdo mapping is unknown; start loading it + ec_fsm_pdo_entry_start_reading(&fsm->fsm_pdo_entry, fsm->slave, + &fsm->slave_pdo); + fsm->state = ec_fsm_pdo_conf_state_read_mapping; + fsm->state(fsm, datagram); // execute immediately + return; + } + + // pdo mapping is known, check if it most be re-configured + ec_fsm_pdo_conf_action_check_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Execute the PDO entry state machine to read the current PDO's mapping. + */ +void ec_fsm_pdo_conf_state_read_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_pdo_entry_exec(&fsm->fsm_pdo_entry, datagram)) { + return; + } + + if (!ec_fsm_pdo_entry_success(&fsm->fsm_pdo_entry)) + EC_SLAVE_WARN(fsm->slave, + "Failed to read PDO entries for PDO 0x%04X.\n", + fsm->pdo->index); + + // check if the mapping must be re-configured + ec_fsm_pdo_conf_action_check_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Check if the mapping has to be re-configured. + * + * \todo Display mapping differences. + */ +void ec_fsm_pdo_conf_action_check_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // check, if slave supports PDO configuration + if ((fsm->slave->sii.mailbox_protocols & EC_MBOX_COE) + && fsm->slave->sii.has_general + && fsm->slave->sii.coe_details.enable_pdo_configuration) { + + // always write PDO mapping + ec_fsm_pdo_entry_start_configuration(&fsm->fsm_pdo_entry, fsm->slave, + fsm->pdo, &fsm->slave_pdo); + fsm->state = ec_fsm_pdo_conf_state_mapping; + fsm->state(fsm, datagram); // execure immediately + return; + } + else if (!ec_pdo_equal_entries(fsm->pdo, &fsm->slave_pdo)) { + EC_SLAVE_WARN(fsm->slave, "Slave does not support" + " changing the PDO mapping!\n"); + EC_SLAVE_WARN(fsm->slave, ""); + printk(KERN_CONT "Currently mapped PDO entries: "); + ec_pdo_print_entries(&fsm->slave_pdo); + printk(KERN_CONT ". Entries to map: "); + ec_pdo_print_entries(fsm->pdo); + printk(KERN_CONT "\n"); + } + + ec_fsm_pdo_conf_action_next_pdo_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Let the PDO entry state machine configure the current PDO's mapping. + */ +void ec_fsm_pdo_conf_state_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_pdo_entry_exec(&fsm->fsm_pdo_entry, datagram)) { + return; + } + + if (!ec_fsm_pdo_entry_success(&fsm->fsm_pdo_entry)) + EC_SLAVE_WARN(fsm->slave, + "Failed to configure mapping of PDO 0x%04X.\n", + fsm->pdo->index); + + ec_fsm_pdo_conf_action_next_pdo_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Check mapping of next PDO, otherwise configure assignment. + */ +void ec_fsm_pdo_conf_action_next_pdo_mapping( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // get next configured PDO + if (!(fsm->pdo = ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdo->list))) { + // no more configured pdos + ec_fsm_pdo_conf_action_check_assignment(fsm, datagram); + return; + } + + ec_fsm_pdo_conf_action_pdo_mapping(fsm, datagram); +} + +/****************************************************************************/ + +/** Check if the PDO assignment of the current SM has to be re-configured. + */ +void ec_fsm_pdo_conf_action_check_assignment( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if ((fsm->slave->sii.mailbox_protocols & EC_MBOX_COE) + && fsm->slave->sii.has_general + && fsm->slave->sii.coe_details.enable_pdo_assign) { + + // always write PDO assignment + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(fsm->slave, 1, "Setting PDO assignment of SM%u:\n", + fsm->sync_index); + EC_SLAVE_DBG(fsm->slave, 1, ""); ec_fsm_pdo_print(fsm); + } + + if (ec_sdo_request_alloc(&fsm->request, 2)) { + fsm->state = ec_fsm_pdo_state_error; + return; + } + + // set mapped PDO count to zero + EC_WRITE_U8(fsm->request.data, 0); // zero PDOs mapped + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Setting number of assigned" + " PDOs to zero.\n"); + + fsm->state = ec_fsm_pdo_conf_state_zero_pdo_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + else if (!ec_pdo_list_equal(&fsm->sync->pdos, &fsm->pdos)) { + EC_SLAVE_WARN(fsm->slave, "Slave does not support assigning PDOs!\n"); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_print(fsm); + } + + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); +} + +/****************************************************************************/ + +/** Set the number of assigned PDOs to zero. + */ +void ec_fsm_pdo_conf_state_zero_pdo_count( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to clear PDO assignment of SM%u.\n", + fsm->sync_index); + EC_SLAVE_WARN(fsm->slave, ""); + ec_fsm_pdo_print(fsm); + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); + return; + } + + // the sync manager's assigned PDOs have been cleared + ec_pdo_list_clear_pdos(&fsm->sync->pdos); + + // assign all PDOs belonging to the current sync manager + + // find first PDO + if (!(fsm->pdo = ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdos.list))) { + // check for mapping to be altered + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); + return; + } + + // assign first PDO + fsm->pdo_pos = 1; + ec_fsm_pdo_conf_action_assign_pdo(fsm, datagram); +} + +/****************************************************************************/ + +/** Assign a PDO. + */ +void ec_fsm_pdo_conf_action_assign_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + EC_WRITE_U16(fsm->request.data, fsm->pdo->index); + fsm->request.data_size = 2; + ecrt_sdo_request_index(&fsm->request, + 0x1C10 + fsm->sync_index, fsm->pdo_pos); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Assigning PDO 0x%04X at position %u.\n", + fsm->pdo->index, fsm->pdo_pos); + + fsm->state = ec_fsm_pdo_conf_state_assign_pdo; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Add a PDO to the sync managers PDO assignment. + */ +void ec_fsm_pdo_conf_state_assign_pdo( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to assign PDO 0x%04X at position %u" + " of SM%u.\n", + fsm->pdo->index, fsm->pdo_pos, fsm->sync_index); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_print(fsm); + fsm->state = ec_fsm_pdo_state_error; + return; + } + + // find next PDO + if (!(fsm->pdo = ec_fsm_pdo_conf_action_next_pdo(fsm, &fsm->pdo->list))) { + // no more PDOs to assign, set PDO count + EC_WRITE_U8(fsm->request.data, fsm->pdo_pos); + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, 0x1C10 + fsm->sync_index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, + "Setting number of assigned PDOs to %u.\n", + fsm->pdo_pos); + + fsm->state = ec_fsm_pdo_conf_state_set_pdo_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // add next PDO to assignment + fsm->pdo_pos++; + ec_fsm_pdo_conf_action_assign_pdo(fsm, datagram); +} + +/****************************************************************************/ + +/** Set the number of assigned PDOs. + */ +void ec_fsm_pdo_conf_state_set_pdo_count( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to set number of" + " assigned PDOs of SM%u.\n", fsm->sync_index); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_print(fsm); + fsm->state = ec_fsm_pdo_state_error; + return; + } + + // PDOs have been configured + ec_pdo_list_copy(&fsm->sync->pdos, &fsm->pdos); + + EC_SLAVE_DBG(fsm->slave, 1, "Successfully configured" + " PDO assignment of SM%u.\n", fsm->sync_index); + + // check if PDO mapping has to be altered + ec_fsm_pdo_conf_action_next_sync(fsm, datagram); +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_pdo_state_error( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_pdo_state_end( + ec_fsm_pdo_t *fsm, /**< Finite state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_pdo.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_pdo.h @@ -0,0 +1,76 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT PDO configuration state machine structures. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_PDO_H__ +#define __EC_FSM_PDO_H__ + +#include "globals.h" +#include "datagram.h" +#include "fsm_coe.h" +#include "fsm_pdo_entry.h" + +/****************************************************************************/ + +/** + * \see ec_fsm_pdo + */ +typedef struct ec_fsm_pdo ec_fsm_pdo_t; + +/** PDO configuration state machine. + */ +struct ec_fsm_pdo +{ + void (*state)(ec_fsm_pdo_t *, ec_datagram_t *); /**< State function. */ + ec_fsm_coe_t *fsm_coe; /**< CoE state machine to use. */ + ec_fsm_pdo_entry_t fsm_pdo_entry; /**< PDO entry state machine. */ + ec_pdo_list_t pdos; /**< PDO configuration. */ + ec_sdo_request_t request; /**< SDO request. */ + ec_pdo_t slave_pdo; /**< PDO actually appearing in a slave. */ + + ec_slave_t *slave; /**< Slave the FSM runs on. */ + uint8_t sync_index; /**< Current sync manager index. */ + ec_sync_t *sync; /**< Current sync manager. */ + ec_pdo_t *pdo; /**< Current PDO. */ + unsigned int pdo_pos; /**< Assignment position of current PDOs. */ + unsigned int pdo_count; /**< Number of assigned PDOs. */ +}; + +/****************************************************************************/ + +void ec_fsm_pdo_init(ec_fsm_pdo_t *, ec_fsm_coe_t *); +void ec_fsm_pdo_clear(ec_fsm_pdo_t *); + +void ec_fsm_pdo_start_reading(ec_fsm_pdo_t *, ec_slave_t *); +void ec_fsm_pdo_start_configuration(ec_fsm_pdo_t *, ec_slave_t *); + +int ec_fsm_pdo_exec(ec_fsm_pdo_t *, ec_datagram_t *); +int ec_fsm_pdo_success(const ec_fsm_pdo_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_pdo_entry.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_pdo_entry.c @@ -0,0 +1,541 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT PDO mapping state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_pdo_entry.h" + +/****************************************************************************/ + +// prototypes for private methods +void ec_fsm_pdo_entry_print(const ec_fsm_pdo_entry_t *); +int ec_fsm_pdo_entry_running(const ec_fsm_pdo_entry_t *); +ec_pdo_entry_t *ec_fsm_pdo_entry_conf_next_entry(const ec_fsm_pdo_entry_t *, + const struct list_head *); + +/****************************************************************************/ + +void ec_fsm_pdo_entry_read_state_start(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_read_state_count(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_read_state_entry(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +void ec_fsm_pdo_entry_read_action_next(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +void ec_fsm_pdo_entry_conf_state_start(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_conf_state_zero_entry_count(ec_fsm_pdo_entry_t *, + ec_datagram_t *); +void ec_fsm_pdo_entry_conf_state_map_entry(ec_fsm_pdo_entry_t *, + ec_datagram_t *); +void ec_fsm_pdo_entry_conf_state_set_entry_count(ec_fsm_pdo_entry_t *, + ec_datagram_t *); + +void ec_fsm_pdo_entry_conf_action_map(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +void ec_fsm_pdo_entry_state_end(ec_fsm_pdo_entry_t *, ec_datagram_t *); +void ec_fsm_pdo_entry_state_error(ec_fsm_pdo_entry_t *, ec_datagram_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_pdo_entry_init( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_fsm_coe_t *fsm_coe /**< CoE state machine to use. */ + ) +{ + fsm->fsm_coe = fsm_coe; + ec_sdo_request_init(&fsm->request); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_pdo_entry_clear( + ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + ec_sdo_request_clear(&fsm->request); +} + +/****************************************************************************/ + +/** Print the current and desired PDO mapping. + */ +void ec_fsm_pdo_entry_print( + const ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + printk(KERN_CONT "Currently mapped PDO entries: "); + ec_pdo_print_entries(fsm->cur_pdo); + printk(KERN_CONT ". Entries to map: "); + ec_pdo_print_entries(fsm->source_pdo); + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Start reading a PDO's entries. + */ +void ec_fsm_pdo_entry_start_reading( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_slave_t *slave, /**< Slave to configure. */ + ec_pdo_t *pdo /**< PDO to read entries for. */ + ) +{ + fsm->slave = slave; + fsm->target_pdo = pdo; + + ec_pdo_clear_entries(fsm->target_pdo); + + fsm->state = ec_fsm_pdo_entry_read_state_start; +} + +/****************************************************************************/ + +/** Start PDO mapping state machine. + */ +void ec_fsm_pdo_entry_start_configuration( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_slave_t *slave, /**< Slave to configure. */ + const ec_pdo_t *pdo, /**< PDO with the desired entries. */ + const ec_pdo_t *cur_pdo /**< Current PDO mapping. */ + ) +{ + fsm->slave = slave; + fsm->source_pdo = pdo; + fsm->cur_pdo = cur_pdo; + + if (fsm->slave->master->debug_level) { + EC_SLAVE_DBG(slave, 1, "Changing mapping of PDO 0x%04X.\n", + pdo->index); + EC_SLAVE_DBG(slave, 1, ""); ec_fsm_pdo_entry_print(fsm); + } + + fsm->state = ec_fsm_pdo_entry_conf_state_start; +} + +/****************************************************************************/ + +/** Get running state. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_entry_running( + const ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + return fsm->state != ec_fsm_pdo_entry_state_end + && fsm->state != ec_fsm_pdo_entry_state_error; +} + +/****************************************************************************/ + +/** Executes the current state. + * + * \return false, if state machine has terminated + */ +int ec_fsm_pdo_entry_exec( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + fsm->state(fsm, datagram); + + return ec_fsm_pdo_entry_running(fsm); +} + +/****************************************************************************/ + +/** Get execution result. + * + * \return true, if the state machine terminated gracefully + */ +int ec_fsm_pdo_entry_success( + const ec_fsm_pdo_entry_t *fsm /**< PDO mapping state machine. */ + ) +{ + return fsm->state == ec_fsm_pdo_entry_state_end; +} + +/***************************************************************************** + * Reading state functions. + ****************************************************************************/ + +/** Request reading the number of mapped PDO entries. + */ +void ec_fsm_pdo_entry_read_state_start( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ecrt_sdo_request_index(&fsm->request, fsm->target_pdo->index, 0); + ecrt_sdo_request_read(&fsm->request); + + fsm->state = ec_fsm_pdo_entry_read_state_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Read number of mapped PDO entries. + */ +void ec_fsm_pdo_entry_read_state_count( + ec_fsm_pdo_entry_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, + "Failed to read number of mapped PDO entries.\n"); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + if (fsm->request.data_size != sizeof(uint8_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu at uploading" + " SDO 0x%04X:%02X.\n", + fsm->request.data_size, fsm->request.index, + fsm->request.subindex); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + fsm->entry_count = EC_READ_U8(fsm->request.data); + + EC_SLAVE_DBG(fsm->slave, 1, "%u PDO entries mapped.\n", fsm->entry_count); + + // read first PDO entry + fsm->entry_pos = 1; + ec_fsm_pdo_entry_read_action_next(fsm, datagram); +} + +/****************************************************************************/ + +/** Read next PDO entry. + */ +void ec_fsm_pdo_entry_read_action_next( + ec_fsm_pdo_entry_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (fsm->entry_pos <= fsm->entry_count) { + ecrt_sdo_request_index(&fsm->request, fsm->target_pdo->index, + fsm->entry_pos); + ecrt_sdo_request_read(&fsm->request); + fsm->state = ec_fsm_pdo_entry_read_state_entry; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // finished reading entries. + fsm->state = ec_fsm_pdo_entry_state_end; +} + +/****************************************************************************/ + +/** Read PDO entry information. + */ +void ec_fsm_pdo_entry_read_state_entry( + ec_fsm_pdo_entry_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "Failed to read mapped PDO entry.\n"); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + if (fsm->request.data_size != sizeof(uint32_t)) { + EC_SLAVE_ERR(fsm->slave, "Invalid data size %zu at" + " uploading SDO 0x%04X:%02X.\n", + fsm->request.data_size, fsm->request.index, + fsm->request.subindex); + fsm->state = ec_fsm_pdo_entry_state_error; + } else { + uint32_t pdo_entry_info; + ec_pdo_entry_t *pdo_entry; + + pdo_entry_info = EC_READ_U32(fsm->request.data); + + if (!(pdo_entry = (ec_pdo_entry_t *) + kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_SLAVE_ERR(fsm->slave, "Failed to allocate PDO entry.\n"); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + ec_pdo_entry_init(pdo_entry); + pdo_entry->index = pdo_entry_info >> 16; + pdo_entry->subindex = (pdo_entry_info >> 8) & 0xFF; + pdo_entry->bit_length = pdo_entry_info & 0xFF; + + if (!pdo_entry->index && !pdo_entry->subindex) { + if (ec_pdo_entry_set_name(pdo_entry, "Gap")) { + ec_pdo_entry_clear(pdo_entry); + kfree(pdo_entry); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + } + + EC_SLAVE_DBG(fsm->slave, 1, + "PDO entry 0x%04X:%02X, %u bit, \"%s\".\n", + pdo_entry->index, pdo_entry->subindex, + pdo_entry->bit_length, + pdo_entry->name ? pdo_entry->name : "???"); + + list_add_tail(&pdo_entry->list, &fsm->target_pdo->entries); + + // next PDO entry + fsm->entry_pos++; + ec_fsm_pdo_entry_read_action_next(fsm, datagram); + } +} + +/***************************************************************************** + * Configuration state functions. + ****************************************************************************/ + +/** Start PDO mapping. + */ +void ec_fsm_pdo_entry_conf_state_start( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_sdo_request_alloc(&fsm->request, 4)) { + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + // set mapped PDO entry count to zero + EC_WRITE_U8(fsm->request.data, 0); + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, fsm->source_pdo->index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Setting entry count to zero.\n"); + + fsm->state = ec_fsm_pdo_entry_conf_state_zero_entry_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Process next PDO entry. + * + * \return Next PDO entry, or NULL. + */ +ec_pdo_entry_t *ec_fsm_pdo_entry_conf_next_entry( + const ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + const struct list_head *list /**< current entry list item */ + ) +{ + list = list->next; + if (list == &fsm->source_pdo->entries) + return NULL; // no next entry + return list_entry(list, ec_pdo_entry_t, list); +} + +/****************************************************************************/ + +/** Set the number of mapped entries to zero. + */ +void ec_fsm_pdo_entry_conf_state_zero_entry_count( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to clear PDO mapping.\n"); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_entry_print(fsm); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + // find first entry + if (!(fsm->entry = ec_fsm_pdo_entry_conf_next_entry( + fsm, &fsm->source_pdo->entries))) { + + EC_SLAVE_DBG(fsm->slave, 1, "No entries to map.\n"); + + fsm->state = ec_fsm_pdo_entry_state_end; // finished + return; + } + + // add first entry + fsm->entry_pos = 1; + ec_fsm_pdo_entry_conf_action_map(fsm, datagram); +} + +/****************************************************************************/ + +/** Starts to add a PDO entry. + */ +void ec_fsm_pdo_entry_conf_action_map( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint32_t value; + + EC_SLAVE_DBG(fsm->slave, 1, "Mapping PDO entry 0x%04X:%02X (%u bit)" + " at position %u.\n", + fsm->entry->index, fsm->entry->subindex, + fsm->entry->bit_length, fsm->entry_pos); + + value = fsm->entry->index << 16 + | fsm->entry->subindex << 8 | fsm->entry->bit_length; + EC_WRITE_U32(fsm->request.data, value); + fsm->request.data_size = 4; + ecrt_sdo_request_index(&fsm->request, fsm->source_pdo->index, + fsm->entry_pos); + ecrt_sdo_request_write(&fsm->request); + + fsm->state = ec_fsm_pdo_entry_conf_state_map_entry; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately +} + +/****************************************************************************/ + +/** Add a PDO entry. + */ +void ec_fsm_pdo_entry_conf_state_map_entry( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to map PDO entry" + " 0x%04X:%02X (%u bit) to position %u.\n", + fsm->entry->index, fsm->entry->subindex, + fsm->entry->bit_length, fsm->entry_pos); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_entry_print(fsm); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + // find next entry + if (!(fsm->entry = ec_fsm_pdo_entry_conf_next_entry( + fsm, &fsm->entry->list))) { + + // No more entries to add. Write entry count. + EC_WRITE_U8(fsm->request.data, fsm->entry_pos); + fsm->request.data_size = 1; + ecrt_sdo_request_index(&fsm->request, fsm->source_pdo->index, 0); + ecrt_sdo_request_write(&fsm->request); + + EC_SLAVE_DBG(fsm->slave, 1, "Setting number of PDO entries to %u.\n", + fsm->entry_pos); + + fsm->state = ec_fsm_pdo_entry_conf_state_set_entry_count; + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request); + ec_fsm_coe_exec(fsm->fsm_coe, datagram); // execute immediately + return; + } + + // add next entry + fsm->entry_pos++; + ec_fsm_pdo_entry_conf_action_map(fsm, datagram); +} + +/****************************************************************************/ + +/** Set the number of entries. + */ +void ec_fsm_pdo_entry_conf_state_set_entry_count( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_WARN(fsm->slave, "Failed to set number of entries.\n"); + EC_SLAVE_WARN(fsm->slave, ""); ec_fsm_pdo_entry_print(fsm); + fsm->state = ec_fsm_pdo_entry_state_error; + return; + } + + EC_SLAVE_DBG(fsm->slave, 1, "Successfully configured" + " mapping for PDO 0x%04X.\n", fsm->source_pdo->index); + + fsm->state = ec_fsm_pdo_entry_state_end; // finished +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_pdo_entry_state_error( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_pdo_entry_state_end( + ec_fsm_pdo_entry_t *fsm, /**< PDO mapping state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_pdo_entry.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_pdo_entry.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT PDO entry configuration state machine structures. + */ + +/****************************************************************************/ + +#ifndef __EC_FSM_PDO_ENTRY_H__ +#define __EC_FSM_PDO_ENTRY_H__ + +#include "globals.h" +#include "datagram.h" +#include "fsm_coe.h" + +/****************************************************************************/ + +/** + * \see ec_fsm_pdo_entry + */ +typedef struct ec_fsm_pdo_entry ec_fsm_pdo_entry_t; + +/** PDO configuration state machine. + */ +struct ec_fsm_pdo_entry +{ + void (*state)(ec_fsm_pdo_entry_t *, ec_datagram_t *); /**< state function + */ + ec_fsm_coe_t *fsm_coe; /**< CoE state machine to use */ + ec_sdo_request_t request; /**< SDO request. */ + + ec_slave_t *slave; /**< Slave the FSM runs on. */ + ec_pdo_t *target_pdo; /**< PDO to read the mapping for. */ + const ec_pdo_t *source_pdo; /**< PDO with desired mapping. */ + const ec_pdo_t *cur_pdo; /**< PDO with current mapping (display only). */ + const ec_pdo_entry_t *entry; /**< Current entry. */ + unsigned int entry_count; /**< Number of entries. */ + unsigned int entry_pos; /**< Position in PDO mapping. */ +}; + +/****************************************************************************/ + +void ec_fsm_pdo_entry_init(ec_fsm_pdo_entry_t *, ec_fsm_coe_t *); +void ec_fsm_pdo_entry_clear(ec_fsm_pdo_entry_t *); + +void ec_fsm_pdo_entry_start_reading(ec_fsm_pdo_entry_t *, ec_slave_t *, + ec_pdo_t *); +void ec_fsm_pdo_entry_start_configuration(ec_fsm_pdo_entry_t *, ec_slave_t *, + const ec_pdo_t *, const ec_pdo_t *); + +int ec_fsm_pdo_entry_exec(ec_fsm_pdo_entry_t *, ec_datagram_t *); +int ec_fsm_pdo_entry_success(const ec_fsm_pdo_entry_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_sii.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_sii.c @@ -0,0 +1,482 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave information interface FSM. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "mailbox.h" +#include "master.h" +#include "fsm_sii.h" + +/** Read/write timeout [ms]. + * + * Used to calculate timeouts bsed on the jiffies counter. + * + * \attention Must be more than 10 to avoid problems on kernels that run with + * a timer interupt frequency of 100 Hz. + */ +#define SII_TIMEOUT 20 + +/** Time before evaluating answer at writing [ms]. + */ +#define SII_INHIBIT 5 + +//#define SII_DEBUG + +/****************************************************************************/ + +void ec_fsm_sii_state_start_reading(ec_fsm_sii_t *); +void ec_fsm_sii_state_read_check(ec_fsm_sii_t *); +void ec_fsm_sii_state_read_fetch(ec_fsm_sii_t *); +void ec_fsm_sii_state_start_writing(ec_fsm_sii_t *); +void ec_fsm_sii_state_write_check(ec_fsm_sii_t *); +void ec_fsm_sii_state_write_check2(ec_fsm_sii_t *); +void ec_fsm_sii_state_end(ec_fsm_sii_t *); +void ec_fsm_sii_state_error(ec_fsm_sii_t *); + +/****************************************************************************/ + +/** + Constructor. +*/ + +void ec_fsm_sii_init(ec_fsm_sii_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< datagram structure to use */ + ) +{ + fsm->state = NULL; + fsm->datagram = datagram; +} + +/****************************************************************************/ + +/** + Destructor. +*/ + +void ec_fsm_sii_clear(ec_fsm_sii_t *fsm /**< finite state machine */) +{ +} + +/****************************************************************************/ + +/** + Initializes the SII read state machine. +*/ + +void ec_fsm_sii_read(ec_fsm_sii_t *fsm, /**< finite state machine */ + ec_slave_t *slave, /**< slave to read from */ + uint16_t word_offset, /**< offset to read from */ + ec_fsm_sii_addressing_t mode /**< addressing scheme */ + ) +{ + fsm->state = ec_fsm_sii_state_start_reading; + fsm->slave = slave; + fsm->word_offset = word_offset; + fsm->mode = mode; +} + +/****************************************************************************/ + +/** + Initializes the SII write state machine. +*/ + +void ec_fsm_sii_write(ec_fsm_sii_t *fsm, /**< finite state machine */ + ec_slave_t *slave, /**< slave to read from */ + uint16_t word_offset, /**< offset to read from */ + const uint16_t *value, /**< pointer to 2 bytes of data */ + ec_fsm_sii_addressing_t mode /**< addressing scheme */ + ) +{ + fsm->state = ec_fsm_sii_state_start_writing; + fsm->slave = slave; + fsm->word_offset = word_offset; + fsm->mode = mode; + memcpy(fsm->value, value, 2); +} + +/****************************************************************************/ + +/** + Executes the SII state machine. + \return false, if the state machine has terminated +*/ + +int ec_fsm_sii_exec(ec_fsm_sii_t *fsm /**< finite state machine */) +{ + fsm->state(fsm); + + return fsm->state != ec_fsm_sii_state_end + && fsm->state != ec_fsm_sii_state_error; +} + +/****************************************************************************/ + +/** + Returns, if the master startup state machine terminated with success. + \return non-zero if successful. +*/ + +int ec_fsm_sii_success(ec_fsm_sii_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_sii_state_end; +} + +/***************************************************************************** + * state functions + ****************************************************************************/ + +/** + SII state: START READING. + Starts reading the slave information interface. +*/ + +void ec_fsm_sii_state_start_reading( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + // initiate read operation + switch (fsm->mode) { + case EC_FSM_SII_USE_INCREMENT_ADDRESS: + ec_datagram_apwr(datagram, fsm->slave->ring_position, 0x502, 4); + break; + case EC_FSM_SII_USE_CONFIGURED_ADDRESS: + ec_datagram_fpwr(datagram, fsm->slave->station_address, 0x502, 4); + break; + } + + EC_WRITE_U8 (datagram->data, 0x80); // two address octets + EC_WRITE_U8 (datagram->data + 1, 0x01); // request read operation + EC_WRITE_U16(datagram->data + 2, fsm->word_offset); + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "reading SII data, word %u:\n", + fsm->word_offset); + ec_print_data(datagram->data, 4); +#endif + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_read_check; +} + +/****************************************************************************/ + +/** + SII state: READ CHECK. + Checks, if the SII-read-datagram has been sent and issues a fetch datagram. +*/ + +void ec_fsm_sii_state_read_check( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to receive SII read datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Reception of SII read datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->jiffies_start = datagram->jiffies_sent; + fsm->check_once_more = 1; + + // issue check/fetch datagram + switch (fsm->mode) { + case EC_FSM_SII_USE_INCREMENT_ADDRESS: + ec_datagram_aprd(datagram, fsm->slave->ring_position, 0x502, 10); + break; + case EC_FSM_SII_USE_CONFIGURED_ADDRESS: + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x502, 10); + break; + } + + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_read_fetch; +} + +/****************************************************************************/ + +/** + SII state: READ FETCH. + Fetches the result of an SII-read datagram. +*/ +void ec_fsm_sii_state_read_fetch( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to receive SII check/fetch datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Reception of SII check/fetch datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "checking SII read state:\n"); + ec_print_data(datagram->data, 10); +#endif + + if (EC_READ_U8(datagram->data + 1) & 0x20) { + EC_SLAVE_ERR(fsm->slave, "Error on last command while" + " reading from SII word 0x%04x.\n", fsm->word_offset); + fsm->state = ec_fsm_sii_state_error; + return; + } + + // check "busy bit" + if (EC_READ_U8(datagram->data + 1) & 0x81) { /* busy bit or + read operation busy */ + // still busy... timeout? + unsigned long diff_ms = + (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= SII_TIMEOUT) { + if (fsm->check_once_more) { + fsm->check_once_more = 0; + } else { + EC_SLAVE_ERR(fsm->slave, "SII: Read timeout.\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + } + + // issue check/fetch datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + + // SII value received. + memcpy(fsm->value, datagram->data + 6, 4); + fsm->state = ec_fsm_sii_state_end; +} + +/****************************************************************************/ + +/** + SII state: START WRITING. + Starts writing a word through the slave information interface. +*/ + +void ec_fsm_sii_state_start_writing( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + // initiate write operation + ec_datagram_fpwr(datagram, fsm->slave->station_address, 0x502, 8); + EC_WRITE_U8 (datagram->data, 0x81); /* two address octets + + enable write access */ + EC_WRITE_U8 (datagram->data + 1, 0x02); // request write operation + EC_WRITE_U16(datagram->data + 2, fsm->word_offset); + memset(datagram->data + 4, 0x00, 2); + memcpy(datagram->data + 6, fsm->value, 2); + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "writing SII data:\n"); + ec_print_data(datagram->data, 8); +#endif + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_write_check; +} + +/****************************************************************************/ + +/** + SII state: WRITE CHECK. +*/ + +void ec_fsm_sii_state_write_check( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to receive SII write datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, "Reception of SII write datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + fsm->jiffies_start = datagram->jiffies_sent; + fsm->check_once_more = 1; + + // issue check datagram + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x502, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_sii_state_write_check2; +} + +/****************************************************************************/ + +/** + SII state: WRITE CHECK 2. +*/ + +void ec_fsm_sii_state_write_check2( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + unsigned long diff_ms; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to receive SII write check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->state = ec_fsm_sii_state_error; + EC_SLAVE_ERR(fsm->slave, + "Reception of SII write check datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "checking SII write state:\n"); + ec_print_data(datagram->data, 2); +#endif + + if (EC_READ_U8(datagram->data + 1) & 0x20) { + EC_SLAVE_ERR(fsm->slave, "SII: Error on last SII command!\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + + /* FIXME: some slaves never answer with the busy flag set... + * wait a few ms for the write operation to complete. */ + diff_ms = (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + if (diff_ms < SII_INHIBIT) { +#ifdef SII_DEBUG + EC_SLAVE_DBG(fsm->slave, 0, "too early.\n"); +#endif + // issue check datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + + if (EC_READ_U8(datagram->data + 1) & 0x82) { /* busy bit or + write operation busy bit */ + // still busy... timeout? + if (diff_ms >= SII_TIMEOUT) { + if (fsm->check_once_more) { + fsm->check_once_more = 0; + } else { + EC_SLAVE_ERR(fsm->slave, "SII: Write timeout.\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + } + + // issue check datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + + if (EC_READ_U8(datagram->data + 1) & 0x40) { + EC_SLAVE_ERR(fsm->slave, "SII: Write operation failed!\n"); + fsm->state = ec_fsm_sii_state_error; + return; + } + + // success + fsm->state = ec_fsm_sii_state_end; +} + +/****************************************************************************/ + +/** + State: ERROR. +*/ + +void ec_fsm_sii_state_error( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** + State: END. +*/ + +void ec_fsm_sii_state_end( + ec_fsm_sii_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_sii.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_sii.h @@ -0,0 +1,82 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave information interface FSM structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SII_H__ +#define __EC_FSM_SII_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" + +/****************************************************************************/ + +/** SII access addressing mode. + */ +typedef enum { + EC_FSM_SII_USE_INCREMENT_ADDRESS, /**< Use auto-increment addressing. */ + EC_FSM_SII_USE_CONFIGURED_ADDRESS /**< Use configured addresses. */ +} ec_fsm_sii_addressing_t; + +/****************************************************************************/ + +typedef struct ec_fsm_sii ec_fsm_sii_t; /**< \see ec_fsm_sii */ + +/** + Slave information interface FSM. +*/ + +struct ec_fsm_sii +{ + ec_slave_t *slave; /**< slave the FSM runs on */ + ec_datagram_t *datagram; /**< datagram used in the state machine */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_sii_t *); /**< SII state function */ + uint16_t word_offset; /**< input: word offset in SII */ + ec_fsm_sii_addressing_t mode; /**< reading via APRD or NPRD */ + uint8_t value[4]; /**< raw SII value (32bit) */ + unsigned long jiffies_start; /**< Start timestamp. */ + uint8_t check_once_more; /**< one more try after timeout */ +}; + +/****************************************************************************/ + +void ec_fsm_sii_init(ec_fsm_sii_t *, ec_datagram_t *); +void ec_fsm_sii_clear(ec_fsm_sii_t *); + +void ec_fsm_sii_read(ec_fsm_sii_t *, ec_slave_t *, + uint16_t, ec_fsm_sii_addressing_t); +void ec_fsm_sii_write(ec_fsm_sii_t *, ec_slave_t *, uint16_t, + const uint16_t *, ec_fsm_sii_addressing_t); + +int ec_fsm_sii_exec(ec_fsm_sii_t *); +int ec_fsm_sii_success(ec_fsm_sii_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_slave.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_slave.c @@ -0,0 +1,685 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT slave (SDO) state machine. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_slave.h" + +/****************************************************************************/ + +void ec_fsm_slave_state_idle(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_ready(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_sdo(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_sdo_request(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_reg(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_reg_request(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_foe(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_foe_request(ec_fsm_slave_t *, ec_datagram_t *); +int ec_fsm_slave_action_process_soe(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_soe_request(ec_fsm_slave_t *, ec_datagram_t *); +#ifdef EC_EOE +int ec_fsm_slave_action_process_eoe(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_state_eoe_request(ec_fsm_slave_t *, ec_datagram_t *); +#endif + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_slave_init( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + fsm->slave = slave; + INIT_LIST_HEAD(&fsm->list); // mark as unlisted + + fsm->state = ec_fsm_slave_state_idle; + fsm->datagram = NULL; + fsm->sdo_request = NULL; + fsm->reg_request = NULL; + fsm->foe_request = NULL; + fsm->soe_request = NULL; +#ifdef EC_EOE + fsm->eoe_request = NULL; +#endif + + // Init sub-state-machines + ec_fsm_coe_init(&fsm->fsm_coe); + ec_fsm_foe_init(&fsm->fsm_foe); + ec_fsm_soe_init(&fsm->fsm_soe); +#ifdef EC_EOE + ec_fsm_eoe_init(&fsm->fsm_eoe); +#endif +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_slave_clear( + ec_fsm_slave_t *fsm /**< Master state machine. */ + ) +{ + // signal requests that are currently in operation + + if (fsm->sdo_request) { + fsm->sdo_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + + if (fsm->reg_request) { + fsm->reg_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + + if (fsm->foe_request) { + fsm->foe_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + + if (fsm->soe_request) { + fsm->soe_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } + +#ifdef EC_EOE + if (fsm->eoe_request) { + fsm->soe_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&fsm->slave->master->request_queue); + } +#endif + + // clear sub-state machines + ec_fsm_coe_clear(&fsm->fsm_coe); + ec_fsm_foe_clear(&fsm->fsm_foe); + ec_fsm_soe_clear(&fsm->fsm_soe); +#ifdef EC_EOE + ec_fsm_eoe_clear(&fsm->fsm_eoe); +#endif +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if \a datagram was used, else 0. + */ +int ec_fsm_slave_exec( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< New datagram to use. */ + ) +{ + int datagram_used; + + fsm->state(fsm, datagram); + + datagram_used = fsm->state != ec_fsm_slave_state_idle && + fsm->state != ec_fsm_slave_state_ready; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Sets the current state of the state machine to READY + */ +void ec_fsm_slave_set_ready( + ec_fsm_slave_t *fsm /**< Slave state machine. */ + ) +{ + if (fsm->state == ec_fsm_slave_state_idle) { + EC_SLAVE_DBG(fsm->slave, 1, "Ready for requests.\n"); + fsm->state = ec_fsm_slave_state_ready; + } +} + +/****************************************************************************/ + +/** Returns, if the FSM is currently not busy and ready to execute. + * + * \return Non-zero if ready. + */ +int ec_fsm_slave_is_ready( + const ec_fsm_slave_t *fsm /**< Slave state machine. */ + ) +{ + return fsm->state == ec_fsm_slave_state_ready; +} + +/***************************************************************************** + * Slave state machine + ****************************************************************************/ + +/** Slave state: IDLE. + */ +void ec_fsm_slave_state_idle( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // do nothing +} + +/****************************************************************************/ + +/** Slave state: READY. + */ +void ec_fsm_slave_state_ready( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + // Check for pending external SDO requests + if (ec_fsm_slave_action_process_sdo(fsm, datagram)) { + return; + } + + // Check for pending external register requests + if (ec_fsm_slave_action_process_reg(fsm, datagram)) { + return; + } + + // Check for pending FoE requests + if (ec_fsm_slave_action_process_foe(fsm, datagram)) { + return; + } + + // Check for pending SoE requests + if (ec_fsm_slave_action_process_soe(fsm, datagram)) { + return; + } + +#ifdef EC_EOE + // Check for pending EoE IP parameter requests + if (ec_fsm_slave_action_process_eoe(fsm, datagram)) { + return; + } +#endif +} + +/****************************************************************************/ + +/** Check for pending SDO requests and process one. + * + * \return non-zero, if an SDO request is processed. + */ +int ec_fsm_slave_action_process_sdo( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request; + + if (list_empty(&slave->sdo_requests)) { + return 0; + } + + // take the first request to be processed + request = list_entry(slave->sdo_requests.next, ec_sdo_request_t, list); + list_del_init(&request->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting SDO request," + " slave has error flag set.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + EC_SLAVE_WARN(slave, "Aborting SDO request, slave is in INIT.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + fsm->sdo_request = request; + request->state = EC_INT_REQUEST_BUSY; + + // Found pending SDO request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing SDO request...\n"); + + // Start SDO transfer + fsm->state = ec_fsm_slave_state_sdo_request; + ec_fsm_coe_transfer(&fsm->fsm_coe, slave, request); + ec_fsm_coe_exec(&fsm->fsm_coe, datagram); // execute immediately + return 1; +} + +/****************************************************************************/ + +/** Slave state: SDO_REQUEST. + */ +void ec_fsm_slave_state_sdo_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_sdo_request_t *request = fsm->sdo_request; + + if (ec_fsm_coe_exec(&fsm->fsm_coe, datagram)) { + return; + } + + if (!ec_fsm_coe_success(&fsm->fsm_coe)) { + EC_SLAVE_ERR(slave, "Failed to process SDO request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->sdo_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + EC_SLAVE_DBG(slave, 1, "Finished SDO request.\n"); + + // SDO request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&slave->master->request_queue); + fsm->sdo_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +/** Check for pending register requests and process one. + * + * \return non-zero, if a register request is processed. + */ +int ec_fsm_slave_action_process_reg( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_reg_request_t *reg; + + fsm->reg_request = NULL; + + if (slave->config) { + // search the first internal register request to be processed + list_for_each_entry(reg, &slave->config->reg_requests, list) { + if (reg->state == EC_INT_REQUEST_QUEUED) { + fsm->reg_request = reg; + break; + } + } + } + + if (!fsm->reg_request && !list_empty(&slave->reg_requests)) { + // take the first external request to be processed + fsm->reg_request = + list_entry(slave->reg_requests.next, ec_reg_request_t, list); + list_del_init(&fsm->reg_request->list); // dequeue + } + + if (!fsm->reg_request) { // no register request to process + return 0; + } + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting register request," + " slave has error flag set.\n"); + fsm->reg_request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->reg_request = NULL; + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + // Found pending register request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing register request...\n"); + + fsm->reg_request->state = EC_INT_REQUEST_BUSY; + + // Start register access + if (fsm->reg_request->dir == EC_DIR_INPUT) { + ec_datagram_fprd(datagram, slave->station_address, + fsm->reg_request->address, fsm->reg_request->transfer_size); + ec_datagram_zero(datagram); + } else { + ec_datagram_fpwr(datagram, slave->station_address, + fsm->reg_request->address, fsm->reg_request->transfer_size); + memcpy(datagram->data, fsm->reg_request->data, + fsm->reg_request->transfer_size); + } + datagram->device_index = slave->device_index; + fsm->state = ec_fsm_slave_state_reg_request; + return 1; +} + +/****************************************************************************/ + +/** Slave state: Register request. + */ +void ec_fsm_slave_state_reg_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_reg_request_t *reg = fsm->reg_request; + + if (!reg) { + // configuration was cleared in the meantime + fsm->state = ec_fsm_slave_state_ready; + fsm->reg_request = NULL; + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_ERR(slave, "Failed to receive register" + " request datagram: "); + ec_datagram_print_state(fsm->datagram); + reg->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->reg_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + if (fsm->datagram->working_counter == 1) { + if (reg->dir == EC_DIR_INPUT) { // read request + memcpy(reg->data, fsm->datagram->data, reg->transfer_size); + } + + reg->state = EC_INT_REQUEST_SUCCESS; + EC_SLAVE_DBG(slave, 1, "Register request successful.\n"); + } else { + reg->state = EC_INT_REQUEST_FAILURE; + ec_datagram_print_state(fsm->datagram); + EC_SLAVE_ERR(slave, "Register request failed" + " (working counter is %u).\n", + fsm->datagram->working_counter); + } + + wake_up_all(&slave->master->request_queue); + fsm->reg_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +/** Check for pending FoE requests and process one. + * + * \return non-zero, if an FoE request is processed. + */ +int ec_fsm_slave_action_process_foe( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_foe_request_t *request; + + if (list_empty(&slave->foe_requests)) { + return 0; + } + + // take the first request to be processed + request = list_entry(slave->foe_requests.next, ec_foe_request_t, list); + list_del_init(&request->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting FoE request," + " slave has error flag set.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + request->state = EC_INT_REQUEST_BUSY; + fsm->foe_request = request; + + EC_SLAVE_DBG(slave, 1, "Processing FoE request.\n"); + + fsm->state = ec_fsm_slave_state_foe_request; + ec_fsm_foe_transfer(&fsm->fsm_foe, slave, request); + ec_fsm_foe_exec(&fsm->fsm_foe, datagram); + return 1; +} + +/****************************************************************************/ + +/** Slave state: FOE REQUEST. + */ +void ec_fsm_slave_state_foe_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_foe_request_t *request = fsm->foe_request; + + if (ec_fsm_foe_exec(&fsm->fsm_foe, datagram)) { + return; + } + + if (!ec_fsm_foe_success(&fsm->fsm_foe)) { + EC_SLAVE_ERR(slave, "Failed to handle FoE request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->foe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + // finished transferring FoE + EC_SLAVE_DBG(slave, 1, "Successfully transferred %zu bytes of FoE" + " data.\n", request->data_size); + + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&slave->master->request_queue); + fsm->foe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +/** Check for pending SoE requests and process one. + * + * \return non-zero, if a request is processed. + */ +int ec_fsm_slave_action_process_soe( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req; + + if (list_empty(&slave->soe_requests)) { + return 0; + } + + // take the first request to be processed + req = list_entry(slave->soe_requests.next, ec_soe_request_t, list); + list_del_init(&req->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting SoE request," + " slave has error flag set.\n"); + req->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + EC_SLAVE_WARN(slave, "Aborting SoE request, slave is in INIT.\n"); + req->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + fsm->soe_request = req; + req->state = EC_INT_REQUEST_BUSY; + + // Found pending request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing SoE request...\n"); + + // Start SoE transfer + fsm->state = ec_fsm_slave_state_soe_request; + ec_fsm_soe_transfer(&fsm->fsm_soe, slave, req); + ec_fsm_soe_exec(&fsm->fsm_soe, datagram); // execute immediately + return 1; +} + +/****************************************************************************/ + +/** Slave state: SOE_REQUEST. + */ +void ec_fsm_slave_state_soe_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *request = fsm->soe_request; + + if (ec_fsm_soe_exec(&fsm->fsm_soe, datagram)) { + return; + } + + if (!ec_fsm_soe_success(&fsm->fsm_soe)) { + EC_SLAVE_ERR(slave, "Failed to process SoE request.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->soe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; + return; + } + + EC_SLAVE_DBG(slave, 1, "Finished SoE request.\n"); + + // SoE request finished + request->state = EC_INT_REQUEST_SUCCESS; + wake_up_all(&slave->master->request_queue); + fsm->soe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ + +#ifdef EC_EOE +/** Check for pending EoE IP parameter requests and process one. + * + * \return non-zero, if a request is processed. + */ +int ec_fsm_slave_action_process_eoe( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_eoe_request_t *request; + + if (list_empty(&slave->eoe_requests)) { + return 0; + } + + // take the first request to be processed + request = list_entry(slave->eoe_requests.next, ec_eoe_request_t, list); + list_del_init(&request->list); // dequeue + + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + EC_SLAVE_WARN(slave, "Aborting EoE request," + " slave has error flag set.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + if (slave->current_state == EC_SLAVE_STATE_INIT) { + EC_SLAVE_WARN(slave, "Aborting EoE request, slave is in INIT.\n"); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&slave->master->request_queue); + fsm->state = ec_fsm_slave_state_idle; + return 0; + } + + fsm->eoe_request = request; + request->state = EC_INT_REQUEST_BUSY; + + // Found pending request. Execute it! + EC_SLAVE_DBG(slave, 1, "Processing EoE request...\n"); + + // Start EoE command + fsm->state = ec_fsm_slave_state_eoe_request; + ec_fsm_eoe_set_ip_param(&fsm->fsm_eoe, slave, request); + ec_fsm_eoe_exec(&fsm->fsm_eoe, datagram); // execute immediately + return 1; +} + +/****************************************************************************/ + +/** Slave state: EOE_REQUEST. + */ +void ec_fsm_slave_state_eoe_request( + ec_fsm_slave_t *fsm, /**< Slave state machine. */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_eoe_request_t *req = fsm->eoe_request; + + if (ec_fsm_eoe_exec(&fsm->fsm_eoe, datagram)) { + return; + } + + if (ec_fsm_eoe_success(&fsm->fsm_eoe)) { + req->state = EC_INT_REQUEST_SUCCESS; + EC_SLAVE_DBG(slave, 1, "Finished EoE request.\n"); + } + else { + req->state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to process EoE request.\n"); + } + + wake_up_all(&slave->master->request_queue); + fsm->eoe_request = NULL; + fsm->state = ec_fsm_slave_state_ready; +} + +/****************************************************************************/ +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_slave.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_slave.h @@ -0,0 +1,87 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave request state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SLAVE_H__ +#define __EC_FSM_SLAVE_H__ + +#include "globals.h" +#include "datagram.h" +#include "sdo_request.h" +#include "reg_request.h" +#ifdef EC_EOE +#include "eoe_request.h" +#endif +#include "fsm_coe.h" +#include "fsm_foe.h" +#include "fsm_soe.h" +#ifdef EC_EOE +#include "fsm_eoe.h" +#endif + +/****************************************************************************/ + +typedef struct ec_fsm_slave ec_fsm_slave_t; /**< \see ec_fsm_slave */ + +/** Finite state machine of an EtherCAT slave. + */ +struct ec_fsm_slave { + ec_slave_t *slave; /**< slave the FSM runs on */ + struct list_head list; /**< Used for execution list. */ + + void (*state)(ec_fsm_slave_t *, ec_datagram_t *); /**< State function. */ + ec_datagram_t *datagram; /**< Previous state datagram. */ + ec_sdo_request_t *sdo_request; /**< SDO request to process. */ + ec_reg_request_t *reg_request; /**< Register request to process. */ + ec_foe_request_t *foe_request; /**< FoE request to process. */ + off_t foe_index; /**< Index to FoE write request data. */ + ec_soe_request_t *soe_request; /**< SoE request to process. */ +#ifdef EC_EOE + ec_eoe_request_t *eoe_request; /**< SoE request to process. */ +#endif + + ec_fsm_coe_t fsm_coe; /**< CoE state machine. */ + ec_fsm_foe_t fsm_foe; /**< FoE state machine. */ + ec_fsm_soe_t fsm_soe; /**< SoE state machine. */ +#ifdef EC_EOE + ec_fsm_eoe_t fsm_eoe; /**< EoE state machine. */ +#endif +}; + +/****************************************************************************/ + +void ec_fsm_slave_init(ec_fsm_slave_t *, ec_slave_t *); +void ec_fsm_slave_clear(ec_fsm_slave_t *); + +int ec_fsm_slave_exec(ec_fsm_slave_t *, ec_datagram_t *); +void ec_fsm_slave_set_ready(ec_fsm_slave_t *); +int ec_fsm_slave_is_ready(const ec_fsm_slave_t *); + +/****************************************************************************/ + + +#endif // __EC_FSM_SLAVE_H__ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_slave_config.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_slave_config.c @@ -0,0 +1,1864 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** \file + * + * EtherCAT slave configuration state machine. + */ + +/****************************************************************************/ + +#include + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" +#include "fsm_slave_config.h" + +/****************************************************************************/ + +/** Maximum clock difference (in ns) before going to SAFEOP. + * + * Wait for DC time difference to drop under this absolute value before + * requesting SAFEOP. + */ +#define EC_DC_MAX_SYNC_DIFF_NS 10000 + +/** Maximum time (in ms) to wait for clock discipline. + */ +#define EC_DC_SYNC_WAIT_MS 5000 + +/** Time offset (in ns), that is added to cyclic start time. + */ +#define EC_DC_START_OFFSET 100000000ULL + +/****************************************************************************/ + +// prototypes for private methods +int ec_fsm_slave_config_running(const ec_fsm_slave_config_t *); + +/****************************************************************************/ + +void ec_fsm_slave_config_state_start(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_init(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_clear_fmmus(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_clear_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_clear_assign(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_mbox_sync(ec_fsm_slave_config_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_config_state_assign_pdi(ec_fsm_slave_config_t *); +#endif +void ec_fsm_slave_config_state_boot_preop(ec_fsm_slave_config_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_config_state_assign_ethercat(ec_fsm_slave_config_t *); +#endif +void ec_fsm_slave_config_state_sdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_soe_conf_preop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_eoe_ip_param(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_watchdog_divider(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_watchdog(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_pdo_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_pdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_fmmu(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_cycle(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_sync_check(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_start(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_dc_assign(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_wait_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_soe_conf_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_op(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_enter_init(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_clear_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_dc_clear_assign(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_mbox_sync(ec_fsm_slave_config_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_config_enter_assign_pdi(ec_fsm_slave_config_t *); +#endif +void ec_fsm_slave_config_enter_boot_preop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_sdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_soe_conf_preop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_eoe_ip_param(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_pdo_conf(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_watchdog_divider(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_watchdog(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_pdo_sync(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_fmmu(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_dc_cycle(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_wait_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_soe_conf_safeop(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_enter_op(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_state_end(ec_fsm_slave_config_t *); +void ec_fsm_slave_config_state_error(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_reconfigure(ec_fsm_slave_config_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_slave_config_init( + ec_fsm_slave_config_t *fsm, /**< slave state machine */ + ec_datagram_t *datagram, /**< datagram structure to use */ + ec_fsm_change_t *fsm_change, /**< State change state machine to use. */ + ec_fsm_coe_t *fsm_coe, /**< CoE state machine to use. */ + ec_fsm_soe_t *fsm_soe, /**< SoE state machine to use. */ + ec_fsm_pdo_t *fsm_pdo, /**< PDO configuration state machine to use. */ + ec_fsm_eoe_t *fsm_eoe /**< EoE state machine to use. */ + ) +{ + ec_sdo_request_init(&fsm->request_copy); + ec_soe_request_init(&fsm->soe_request_copy); + + fsm->datagram = datagram; + fsm->fsm_change = fsm_change; + fsm->fsm_coe = fsm_coe; + fsm->fsm_soe = fsm_soe; + fsm->fsm_pdo = fsm_pdo; + fsm->fsm_eoe = fsm_eoe; + + fsm->wait_ms = 0; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_slave_config_clear( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_sdo_request_clear(&fsm->request_copy); + ec_soe_request_clear(&fsm->soe_request_copy); +} + +/****************************************************************************/ + +/** Start slave configuration state machine. + */ +void ec_fsm_slave_config_start( + ec_fsm_slave_config_t *fsm, /**< slave state machine */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_slave_config_state_start; +} + +/****************************************************************************/ + +/** + * \return false, if state machine has terminated + */ +int ec_fsm_slave_config_running( + const ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + return fsm->state != ec_fsm_slave_config_state_end + && fsm->state != ec_fsm_slave_config_state_error; +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * If the state machine's datagram is not sent or received yet, the execution + * of the state machine is delayed to the next cycle. + * + * \return false, if state machine has terminated + */ +int ec_fsm_slave_config_exec( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + if (fsm->datagram->state == EC_DATAGRAM_SENT + || fsm->datagram->state == EC_DATAGRAM_QUEUED) { + // datagram was not sent or received yet. + return ec_fsm_slave_config_running(fsm); + } + + fsm->state(fsm); + return ec_fsm_slave_config_running(fsm); +} + +/****************************************************************************/ + +/** + * \return true, if the state machine terminated gracefully + */ +int ec_fsm_slave_config_success( + const ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + return fsm->state == ec_fsm_slave_config_state_end; +} + +/***************************************************************************** + * Slave configuration state machine + ****************************************************************************/ + +/** Slave configuration state: START. + */ +void ec_fsm_slave_config_state_start( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + EC_SLAVE_DBG(fsm->slave, 1, "Configuring...\n"); + ec_fsm_slave_config_enter_init(fsm); +} + +/****************************************************************************/ + +/** Start state change to INIT. + */ +void ec_fsm_slave_config_enter_init( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_fsm_change_start(fsm->fsm_change, fsm->slave, EC_SLAVE_STATE_INIT); + ec_fsm_change_exec(fsm->fsm_change); + fsm->state = ec_fsm_slave_config_state_init; +} + +/****************************************************************************/ + +/** Slave configuration state: INIT. + */ +void ec_fsm_slave_config_state_init( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + if (ec_fsm_change_exec(fsm->fsm_change)) return; + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + EC_SLAVE_DBG(slave, 1, "Now in INIT.\n"); + + if (!slave->base_fmmu_count) { // skip FMMU configuration + ec_fsm_slave_config_enter_clear_sync(fsm); + return; + } + + EC_SLAVE_DBG(slave, 1, "Clearing FMMU configurations...\n"); + + // clear FMMU configurations + ec_datagram_fpwr(datagram, slave->station_address, + 0x0600, EC_FMMU_PAGE_SIZE * slave->base_fmmu_count); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_clear_fmmus; +} + +/****************************************************************************/ + +/** Slave configuration state: CLEAR FMMU. + */ +void ec_fsm_slave_config_state_clear_fmmus( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed receive FMMU clearing datagram.\n"); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to clear FMMUs: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_clear_sync(fsm); +} + +/****************************************************************************/ + +/** Clear the sync manager configurations. + */ +void ec_fsm_slave_config_enter_clear_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + size_t sync_size; + + if (!slave->base_sync_count) { + // no sync managers + ec_fsm_slave_config_enter_dc_clear_assign(fsm); + return; + } + + EC_SLAVE_DBG(slave, 1, "Clearing sync manager configurations...\n"); + + sync_size = EC_SYNC_PAGE_SIZE * slave->base_sync_count; + + // clear sync manager configurations + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, sync_size); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_clear_sync; +} + +/****************************************************************************/ + +/** Slave configuration state: CLEAR SYNC. + */ +void ec_fsm_slave_config_state_clear_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed receive sync manager" + " clearing datagram.\n"); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to clear sync manager configurations: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_dc_clear_assign(fsm); +} + +/****************************************************************************/ + +/** Clear the DC assignment. + */ +void ec_fsm_slave_config_enter_dc_clear_assign( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + + if (!slave->base_dc_supported || !slave->has_dc_system_time) { + ec_fsm_slave_config_enter_mbox_sync(fsm); + return; + } + + EC_SLAVE_DBG(slave, 1, "Clearing DC assignment...\n"); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0980, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_clear_assign; +} + +/****************************************************************************/ + +/** Slave configuration state: CLEAR DC ASSIGN. + */ +void ec_fsm_slave_config_state_dc_clear_assign( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed receive DC assignment" + " clearing datagram.\n"); + return; + } + + if (datagram->working_counter != 1) { + // clearing the DC assignment does not succeed on simple slaves + EC_SLAVE_DBG(fsm->slave, 1, "Failed to clear DC assignment: "); + ec_datagram_print_wc_error(datagram); + } + + ec_fsm_slave_config_enter_mbox_sync(fsm); +} + +/****************************************************************************/ + +/** Check for mailbox sync managers to be configured. + */ +void ec_fsm_slave_config_enter_mbox_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + unsigned int i; + + // slave is now in INIT + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + if (!slave->sii.mailbox_protocols) { + // no mailbox protocols supported + EC_SLAVE_DBG(slave, 1, "Slave does not support" + " mailbox communication.\n"); +#ifdef EC_SII_ASSIGN + ec_fsm_slave_config_enter_assign_pdi(fsm); +#else + ec_fsm_slave_config_enter_boot_preop(fsm); +#endif + return; + } + + EC_SLAVE_DBG(slave, 1, "Configuring mailbox sync managers...\n"); + + if (slave->requested_state == EC_SLAVE_STATE_BOOT) { + ec_sync_t sync; + + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * 2); + ec_datagram_zero(datagram); + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.boot_rx_mailbox_offset; + sync.control_register = 0x26; + sync.enable = 1; + ec_sync_page(&sync, 0, slave->sii.boot_rx_mailbox_size, + EC_DIR_INVALID, // use default direction + 0, // no PDO xfer + datagram->data); + slave->configured_rx_mailbox_offset = + slave->sii.boot_rx_mailbox_offset; + slave->configured_rx_mailbox_size = + slave->sii.boot_rx_mailbox_size; + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.boot_tx_mailbox_offset; + sync.control_register = 0x22; + sync.enable = 1; + ec_sync_page(&sync, 1, slave->sii.boot_tx_mailbox_size, + EC_DIR_INVALID, // use default direction + 0, // no PDO xfer + datagram->data + EC_SYNC_PAGE_SIZE); + slave->configured_tx_mailbox_offset = + slave->sii.boot_tx_mailbox_offset; + slave->configured_tx_mailbox_size = + slave->sii.boot_tx_mailbox_size; + + } else if (slave->sii.sync_count >= 2) { // mailbox configuration provided + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * slave->sii.sync_count); + ec_datagram_zero(datagram); + + for (i = 0; i < 2; i++) { + ec_sync_page(&slave->sii.syncs[i], i, + slave->sii.syncs[i].default_length, + NULL, // use default sync manager configuration + 0, // no PDO xfer + datagram->data + EC_SYNC_PAGE_SIZE * i); + } + + slave->configured_rx_mailbox_offset = + slave->sii.syncs[0].physical_start_address; + slave->configured_rx_mailbox_size = + slave->sii.syncs[0].default_length; + slave->configured_tx_mailbox_offset = + slave->sii.syncs[1].physical_start_address; + slave->configured_tx_mailbox_size = + slave->sii.syncs[1].default_length; + } else { // no mailbox sync manager configurations provided + ec_sync_t sync; + + EC_SLAVE_DBG(slave, 1, "Slave does not provide" + " mailbox sync manager configurations.\n"); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * 2); + ec_datagram_zero(datagram); + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.std_rx_mailbox_offset; + sync.control_register = 0x26; + sync.enable = 1; + ec_sync_page(&sync, 0, slave->sii.std_rx_mailbox_size, + NULL, // use default sync manager configuration + 0, // no PDO xfer + datagram->data); + slave->configured_rx_mailbox_offset = + slave->sii.std_rx_mailbox_offset; + slave->configured_rx_mailbox_size = + slave->sii.std_rx_mailbox_size; + + ec_sync_init(&sync, slave); + sync.physical_start_address = slave->sii.std_tx_mailbox_offset; + sync.control_register = 0x22; + sync.enable = 1; + ec_sync_page(&sync, 1, slave->sii.std_tx_mailbox_size, + NULL, // use default sync manager configuration + 0, // no PDO xfer + datagram->data + EC_SYNC_PAGE_SIZE); + slave->configured_tx_mailbox_offset = + slave->sii.std_tx_mailbox_offset; + slave->configured_tx_mailbox_size = + slave->sii.std_tx_mailbox_size; + } + + fsm->take_time = 1; + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_mbox_sync; +} + +/****************************************************************************/ + +/** Slave configuration state: SYNC. + * + * \todo Timeout for response. + */ +void ec_fsm_slave_config_state_mbox_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive sync manager" + " configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (fsm->take_time) { + fsm->take_time = 0; + fsm->jiffies_start = datagram->jiffies_sent; + } + + /* Because the sync manager configurations are cleared during the last + * cycle, some slaves do not immediately respond to the mailbox sync + * manager configuration datagram. Therefore, resend the datagram for + * a certain time, if the slave does not respond. + */ + if (datagram->working_counter == 0) { + unsigned long diff = datagram->jiffies_received - fsm->jiffies_start; + + if (diff >= HZ) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Timeout while configuring" + " mailbox sync managers.\n"); + return; + } else { + EC_SLAVE_DBG(slave, 1, "Resending after %u ms...\n", + (unsigned int) diff * 1000 / HZ); + } + + // send configuration datagram again + fsm->retries = EC_FSM_RETRIES; + return; + } + else if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set sync managers: "); + ec_datagram_print_wc_error(datagram); + return; + } + +#ifdef EC_SII_ASSIGN + ec_fsm_slave_config_enter_assign_pdi(fsm); +#else + ec_fsm_slave_config_enter_boot_preop(fsm); +#endif +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** Assign SII to PDI. + */ +void ec_fsm_slave_config_enter_assign_pdi( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (fsm->slave->requested_state != EC_SLAVE_STATE_BOOT) { + EC_SLAVE_DBG(slave, 1, "Assigning SII access to PDI.\n"); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0500, 0x01); + EC_WRITE_U8(datagram->data, 0x01); // PDI + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_assign_pdi; + } + else { + ec_fsm_slave_config_enter_boot_preop(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: ASSIGN_PDI. + */ +void ec_fsm_slave_config_state_assign_pdi( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_WARN(slave, "Failed receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + goto cont_preop; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to assign SII to PDI: "); + ec_datagram_print_wc_error(datagram); + } + +cont_preop: + ec_fsm_slave_config_enter_boot_preop(fsm); +} + +#endif + +/****************************************************************************/ + +/** Request PREOP state. + */ +void ec_fsm_slave_config_enter_boot_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + fsm->state = ec_fsm_slave_config_state_boot_preop; + + if (fsm->slave->requested_state != EC_SLAVE_STATE_BOOT) { + ec_fsm_change_start(fsm->fsm_change, + fsm->slave, EC_SLAVE_STATE_PREOP); + } else { // BOOT + ec_fsm_change_start(fsm->fsm_change, + fsm->slave, EC_SLAVE_STATE_BOOT); + } + + ec_fsm_change_exec(fsm->fsm_change); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: BOOT/PREOP. + */ +void ec_fsm_slave_config_state_boot_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; +#ifdef EC_SII_ASSIGN + int assign_to_pdi; + ec_slave_config_t *config; + ec_flag_t *flag; +#endif + + if (ec_fsm_change_exec(fsm->fsm_change)) { + return; + } + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + // slave is now in BOOT or PREOP + slave->jiffies_preop = fsm->datagram->jiffies_received; + + EC_SLAVE_DBG(slave, 1, "Now in %s.\n", + slave->requested_state != EC_SLAVE_STATE_BOOT ? "PREOP" : "BOOT"); + +#ifdef EC_SII_ASSIGN + assign_to_pdi = 0; + config = fsm->slave->config; + if (config) { + flag = ec_slave_config_find_flag(config, "AssignToPdi"); + if (flag) { + assign_to_pdi = flag->value; + } + } + + if (assign_to_pdi) { + EC_SLAVE_DBG(slave, 1, "Skipping SII assignment back to EtherCAT.\n"); + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_sdo_conf(fsm); + } + else { + EC_SLAVE_DBG(slave, 1, "Assigning SII access back to EtherCAT.\n"); + + ec_datagram_fpwr(fsm->datagram, slave->station_address, 0x0500, 0x01); + EC_WRITE_U8(fsm->datagram->data, 0x00); // EtherCAT + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_assign_ethercat; + } +#else + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_sdo_conf(fsm); +#endif +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** Slave configuration state: ASSIGN_ETHERCAT. + */ +void ec_fsm_slave_config_state_assign_ethercat( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_WARN(slave, "Failed receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + goto cont_sdo_conf; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to assign SII back to EtherCAT: "); + ec_datagram_print_wc_error(datagram); + } + +cont_sdo_conf: + if (slave->current_state == slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_sdo_conf(fsm); +} + +#endif + +/****************************************************************************/ + +/** Check for SDO configurations to be applied. + */ +void ec_fsm_slave_config_enter_sdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (!slave->config) { + ec_fsm_slave_config_enter_pdo_sync(fsm); + return; + } + + // No CoE configuration to be applied? + if (list_empty(&slave->config->sdo_configs)) { // skip SDO configuration + ec_fsm_slave_config_enter_soe_conf_preop(fsm); + return; + } + + // start SDO configuration + fsm->state = ec_fsm_slave_config_state_sdo_conf; + fsm->request = list_entry(fsm->slave->config->sdo_configs.next, + ec_sdo_request_t, list); + ec_sdo_request_copy(&fsm->request_copy, fsm->request); + ecrt_sdo_request_write(&fsm->request_copy); + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request_copy); + ec_fsm_coe_exec(fsm->fsm_coe, fsm->datagram); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: SDO_CONF. + */ +void ec_fsm_slave_config_state_sdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + if (ec_fsm_coe_exec(fsm->fsm_coe, fsm->datagram)) { + return; + } + + if (!ec_fsm_coe_success(fsm->fsm_coe)) { + EC_SLAVE_ERR(fsm->slave, "SDO configuration failed.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + // Another SDO to configure? + if (fsm->request->list.next != &fsm->slave->config->sdo_configs) { + fsm->request = list_entry(fsm->request->list.next, + ec_sdo_request_t, list); + ec_sdo_request_copy(&fsm->request_copy, fsm->request); + ecrt_sdo_request_write(&fsm->request_copy); + ec_fsm_coe_transfer(fsm->fsm_coe, fsm->slave, &fsm->request_copy); + ec_fsm_coe_exec(fsm->fsm_coe, fsm->datagram); // execute immediately + return; + } + + // All SDOs are now configured. + ec_fsm_slave_config_enter_soe_conf_preop(fsm); +} + +/****************************************************************************/ + +/** Check for SoE configurations to be applied. + */ +void ec_fsm_slave_config_enter_soe_conf_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req; + + if (!slave->config) { + ec_fsm_slave_config_enter_pdo_sync(fsm); + return; + } + + list_for_each_entry(req, &slave->config->soe_configs, list) { + if (req->al_state == EC_AL_STATE_PREOP) { + // start SoE configuration + fsm->state = ec_fsm_slave_config_state_soe_conf_preop; + fsm->soe_request = req; + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // No SoE configuration to be applied in PREOP + ec_fsm_slave_config_enter_eoe_ip_param(fsm); +} + +/****************************************************************************/ + +/** Slave configuration state: SOE_CONF. + */ +void ec_fsm_slave_config_state_soe_conf_preop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram)) { + return; + } + + if (!ec_fsm_soe_success(fsm->fsm_soe)) { + EC_SLAVE_ERR(slave, "SoE configuration failed.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + // Another IDN to configure in PREOP? + while (fsm->soe_request->list.next != &fsm->slave->config->soe_configs) { + fsm->soe_request = list_entry(fsm->soe_request->list.next, + ec_soe_request_t, list); + if (fsm->soe_request->al_state == EC_AL_STATE_PREOP) { + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // All PREOP IDNs are now configured. + ec_fsm_slave_config_enter_eoe_ip_param(fsm); +} + +/****************************************************************************/ + +/** EOE_IP_PARAM entry function. + */ +void ec_fsm_slave_config_enter_eoe_ip_param( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +#ifdef EC_EOE + ec_slave_t *slave = fsm->slave; + ec_eoe_request_t *request = &slave->config->eoe_ip_param_request; + + if (ec_eoe_request_valid(request)) { + EC_SLAVE_DBG(slave, 1, "Setting EoE IP parameters...\n"); + + // Start EoE command + fsm->state = ec_fsm_slave_config_state_eoe_ip_param; + ec_fsm_eoe_set_ip_param(fsm->fsm_eoe, slave, request); + ec_fsm_eoe_exec(fsm->fsm_eoe, fsm->datagram); // execute immediately + return; + } +#endif + + ec_fsm_slave_config_enter_pdo_conf(fsm); +} + +/****************************************************************************/ + +/** Slave configuration state: EOE_IP_PARAM. + */ +void ec_fsm_slave_config_state_eoe_ip_param( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +#ifdef EC_EOE + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_eoe_exec(fsm->fsm_eoe, fsm->datagram)) { + return; + } + + if (ec_fsm_eoe_success(fsm->fsm_eoe)) { + EC_SLAVE_DBG(slave, 1, "Finished setting EoE IP parameters.\n"); + } + else { + EC_SLAVE_ERR(slave, "Failed to set EoE IP parameters.\n"); + } +#endif + ec_fsm_slave_config_enter_pdo_conf(fsm); +} + +/****************************************************************************/ + +/** PDO_CONF entry function. + */ +void ec_fsm_slave_config_enter_pdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + // Start configuring PDOs + ec_fsm_pdo_start_configuration(fsm->fsm_pdo, fsm->slave); + fsm->state = ec_fsm_slave_config_state_pdo_conf; + fsm->state(fsm); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: PDO_CONF. + */ +void ec_fsm_slave_config_state_pdo_conf( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + // TODO check for config here + + if (ec_fsm_pdo_exec(fsm->fsm_pdo, fsm->datagram)) { + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (!ec_fsm_pdo_success(fsm->fsm_pdo)) { + EC_SLAVE_WARN(fsm->slave, "PDO configuration failed.\n"); + } + + ec_fsm_slave_config_enter_watchdog_divider(fsm); +} + +/****************************************************************************/ + +/** WATCHDOG_DIVIDER entry function. + */ +void ec_fsm_slave_config_enter_watchdog_divider( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + ec_slave_config_t *config = slave->config; + + if (config && config->watchdog_divider) { + EC_SLAVE_DBG(slave, 1, "Setting watchdog divider to %u.\n", + config->watchdog_divider); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0400, 2); + EC_WRITE_U16(datagram->data, config->watchdog_divider); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_watchdog_divider; + } else { + ec_fsm_slave_config_enter_watchdog(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: WATCHDOG_DIVIDER. + */ +void ec_fsm_slave_config_state_watchdog_divider( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive watchdog divider" + " configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + EC_SLAVE_WARN(slave, "Failed to set watchdog divider: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_watchdog(fsm); +} + +/****************************************************************************/ + +/** WATCHDOG entry function + */ +void ec_fsm_slave_config_enter_watchdog( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (config && config->watchdog_intervals) { + EC_SLAVE_DBG(slave, 1, "Setting process data" + " watchdog intervals to %u.\n", config->watchdog_intervals); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0420, 2); + EC_WRITE_U16(datagram->data, config->watchdog_intervals); + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_watchdog; + } else { + ec_fsm_slave_config_enter_pdo_sync(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: WATCHDOG. + */ + +void ec_fsm_slave_config_state_watchdog( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive sync manager" + " watchdog configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to set process data" + " watchdog intervals: "); + ec_datagram_print_wc_error(datagram); + } + + ec_fsm_slave_config_enter_pdo_sync(fsm); +} + +/****************************************************************************/ + +/** Check for PDO sync managers to be configured. + */ +void ec_fsm_slave_config_enter_pdo_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + unsigned int i, j, offset, num_pdo_syncs; + uint8_t sync_index; + const ec_sync_t *sync; + uint16_t size; + + if (slave->sii.mailbox_protocols) { + offset = 2; // slave has mailboxes + } else { + offset = 0; + } + + if (slave->sii.sync_count <= offset) { + // no PDO sync managers to configure + ec_fsm_slave_config_enter_fmmu(fsm); + return; + } + + num_pdo_syncs = slave->sii.sync_count - offset; + + // configure sync managers for process data + ec_datagram_fpwr(datagram, slave->station_address, + 0x0800 + EC_SYNC_PAGE_SIZE * offset, + EC_SYNC_PAGE_SIZE * num_pdo_syncs); + ec_datagram_zero(datagram); + + for (i = 0; i < num_pdo_syncs; i++) { + const ec_sync_config_t *sync_config; + uint8_t pdo_xfer = 0; + sync_index = i + offset; + sync = &slave->sii.syncs[sync_index]; + + if (slave->config) { + const ec_slave_config_t *sc = slave->config; + sync_config = &sc->sync_configs[sync_index]; + size = ec_pdo_list_total_size(&sync_config->pdos); + + // determine, if PDOs shall be transferred via this SM + // inthat case, enable sync manager in every case + for (j = 0; j < sc->used_fmmus; j++) { + if (sc->fmmu_configs[j].sync_index == sync_index) { + pdo_xfer = 1; + break; + } + } + + } else { + sync_config = NULL; + size = sync->default_length; + } + + ec_sync_page(sync, sync_index, size, sync_config, pdo_xfer, + datagram->data + EC_SYNC_PAGE_SIZE * i); + } + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_pdo_sync; +} + +/****************************************************************************/ + +/** Configure PDO sync managers. + */ +void ec_fsm_slave_config_state_pdo_sync( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive process data sync" + " manager configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set process data sync managers: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_fmmu(fsm); +} + +/****************************************************************************/ + +/** Check for FMMUs to be configured. + */ +void ec_fsm_slave_config_enter_fmmu( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_datagram_t *datagram = fsm->datagram; + unsigned int i; + const ec_fmmu_config_t *fmmu; + const ec_sync_t *sync; + + if (!slave->config) { + ec_fsm_slave_config_enter_wait_safeop(fsm); + return; + } + + if (slave->base_fmmu_count < slave->config->used_fmmus) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Slave has less FMMUs (%u)" + " than requested (%u).\n", slave->base_fmmu_count, + slave->config->used_fmmus); + return; + } + + if (!slave->base_fmmu_count) { // skip FMMU configuration + ec_fsm_slave_config_enter_dc_cycle(fsm); + return; + } + + // configure FMMUs + ec_datagram_fpwr(datagram, slave->station_address, + 0x0600, EC_FMMU_PAGE_SIZE * slave->base_fmmu_count); + ec_datagram_zero(datagram); + for (i = 0; i < slave->config->used_fmmus; i++) { + fmmu = &slave->config->fmmu_configs[i]; + if (!(sync = ec_slave_get_sync(slave, fmmu->sync_index))) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to determine PDO sync manager" + " for FMMU!\n"); + return; + } + ec_fmmu_config_page(fmmu, sync, + datagram->data + EC_FMMU_PAGE_SIZE * i); + } + + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_fmmu; +} + +/****************************************************************************/ + +/** Slave configuration state: FMMU. + */ +void ec_fsm_slave_config_state_fmmu( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive FMMUs datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set FMMUs: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_dc_cycle(fsm); +} + +/****************************************************************************/ + +/** Check for DC to be configured. + */ +void ec_fsm_slave_config_enter_dc_cycle( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (config->dc_assign_activate) { + if (!slave->base_dc_supported || !slave->has_dc_system_time) { + EC_SLAVE_WARN(slave, "Slave seems not to support" + " distributed clocks!\n"); + } + + EC_SLAVE_DBG(slave, 1, "Setting DC cycle times to %u / %u.\n", + config->dc_sync[0].cycle_time, config->dc_sync[1].cycle_time); + + // set DC cycle times + ec_datagram_fpwr(datagram, slave->station_address, 0x09A0, 8); + EC_WRITE_U32(datagram->data, config->dc_sync[0].cycle_time); + EC_WRITE_U32(datagram->data + 4, config->dc_sync[1].cycle_time); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_cycle; + } else { + // DC are unused + ec_fsm_slave_config_enter_wait_safeop(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: DC CYCLE. + */ +void ec_fsm_slave_config_state_dc_cycle( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC cycle times datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set DC cycle times: "); + ec_datagram_print_wc_error(datagram); + return; + } + + EC_SLAVE_DBG(slave, 1, "Checking for synchrony.\n"); + + fsm->jiffies_start = jiffies; + ec_datagram_fprd(datagram, slave->station_address, 0x092c, 4); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_sync_check; +} + +/****************************************************************************/ + +/** Slave configuration state: DC SYNC CHECK. + */ +void ec_fsm_slave_config_state_dc_sync_check( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_slave_config_t *config = slave->config; + uint32_t abs_sync_diff; + unsigned long diff_ms; + ec_sync_signal_t *sync0 = &config->dc_sync[0]; + ec_sync_signal_t *sync1 = &config->dc_sync[1]; + u64 start_time; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC sync check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to check DC synchrony: "); + ec_datagram_print_wc_error(datagram); + return; + } + + abs_sync_diff = EC_READ_U32(datagram->data) & 0x7fffffff; + diff_ms = (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + + if (abs_sync_diff > EC_DC_MAX_SYNC_DIFF_NS) { + + if (diff_ms >= EC_DC_SYNC_WAIT_MS) { + EC_SLAVE_WARN(slave, "Slave did not sync after %lu ms.\n", + diff_ms); + } else { + EC_SLAVE_DBG(slave, 1, "Sync after %4lu ms: %10u ns\n", + diff_ms, abs_sync_diff); + + // check synchrony again + ec_datagram_fprd(datagram, slave->station_address, 0x092c, 4); + fsm->retries = EC_FSM_RETRIES; + return; + } + } else { + EC_SLAVE_DBG(slave, 1, "%u ns difference after %lu ms.\n", + abs_sync_diff, diff_ms); + } + + // set DC start time (roughly in the future, not in-phase) + start_time = master->app_time + EC_DC_START_OFFSET; // now + X ns + + if (sync0->cycle_time) { + // find correct phase + if (master->dc_ref_time) { + u64 diff, start; + u32 remainder, cycle; + + diff = start_time - master->dc_ref_time; + cycle = sync0->cycle_time + sync1->cycle_time; + remainder = do_div(diff, cycle); + + start = start_time + cycle - remainder + sync0->shift_time; + + EC_SLAVE_DBG(slave, 1, " ref_time=%llu\n", master->dc_ref_time); + EC_SLAVE_DBG(slave, 1, " app_time=%llu\n", master->app_time); + EC_SLAVE_DBG(slave, 1, " start_time=%llu\n", start_time); + EC_SLAVE_DBG(slave, 1, " cycle=%u\n", cycle); + EC_SLAVE_DBG(slave, 1, " shift_time=%i\n", sync0->shift_time); + EC_SLAVE_DBG(slave, 1, " remainder=%u\n", remainder); + EC_SLAVE_DBG(slave, 1, " start=%llu\n", start); + start_time = start; + } else { + EC_SLAVE_WARN(slave, "No application time supplied." + " Cyclic start time will not be in phase.\n"); + } + } + + EC_SLAVE_DBG(slave, 1, "Setting DC cyclic operation" + " start time to %llu.\n", start_time); + + ec_datagram_fpwr(datagram, slave->station_address, 0x0990, 8); + EC_WRITE_U64(datagram->data, start_time); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_start; +} + +/****************************************************************************/ + +/** Slave configuration state: DC START. + */ +void ec_fsm_slave_config_state_dc_start( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + ec_slave_config_t *config = slave->config; + + if (!config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC start time datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to set DC start time: "); + ec_datagram_print_wc_error(datagram); + return; + } + + EC_SLAVE_DBG(slave, 1, "Setting DC AssignActivate to 0x%04x.\n", + config->dc_assign_activate); + + // assign sync unit to EtherCAT or PDI + ec_datagram_fpwr(datagram, slave->station_address, 0x0980, 2); + EC_WRITE_U16(datagram->data, config->dc_assign_activate); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_config_state_dc_assign; +} + +/****************************************************************************/ + +/** Slave configuration state: DC ASSIGN. + */ +void ec_fsm_slave_config_state_dc_assign( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DC activation datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + EC_SLAVE_ERR(slave, "Failed to activate DC: "); + ec_datagram_print_wc_error(datagram); + return; + } + + ec_fsm_slave_config_enter_wait_safeop(fsm); +} + +/****************************************************************************/ + +/** Wait before SAFEOP transition. + * + * The feature flag WaitBeforeSAFEOPms can be used to add a wait time before + * going to SAFEOP. This can be used as a workaround for slaves that need some + * extra time for initialisation. + */ +void ec_fsm_slave_config_enter_wait_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_config_t *config = fsm->slave->config; + fsm->wait_ms = 0UL; + if (config) { + ec_flag_t *flag = ec_slave_config_find_flag(config, + "WaitBeforeSAFEOPms"); + if (flag && flag->value > 0) { + fsm->wait_ms = (unsigned long) flag->value; + } + } + + if (fsm->wait_ms > 0) { + fsm->state = ec_fsm_slave_config_state_wait_safeop; + + /* dummy read */ + ec_datagram_fprd(fsm->datagram, fsm->slave->station_address, + 0x0600, 1); + + fsm->jiffies_start = jiffies; + } + else { + ec_fsm_slave_config_enter_safeop(fsm); + } +} + +/****************************************************************************/ + +/** Slave configuration state: WAIT SAFEOP. + */ +void ec_fsm_slave_config_state_wait_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + unsigned long diff = jiffies - fsm->jiffies_start; + + if (diff * 1000 / HZ < fsm->wait_ms) { + return; + } + + ec_fsm_slave_config_enter_safeop(fsm); +} + +/****************************************************************************/ + +/** Request SAFEOP state. + */ +void ec_fsm_slave_config_enter_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + fsm->state = ec_fsm_slave_config_state_safeop; + ec_fsm_change_start(fsm->fsm_change, fsm->slave, EC_SLAVE_STATE_SAFEOP); + ec_fsm_change_exec(fsm->fsm_change); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: SAFEOP. + */ +void ec_fsm_slave_config_state_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_change_exec(fsm->fsm_change)) return; + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + // slave is now in SAFEOP + + EC_SLAVE_DBG(slave, 1, "Now in SAFEOP.\n"); + + if (fsm->slave->current_state == fsm->slave->requested_state) { + fsm->state = ec_fsm_slave_config_state_end; // successful + EC_SLAVE_DBG(slave, 1, "Finished configuration.\n"); + return; + } + + ec_fsm_slave_config_enter_soe_conf_safeop(fsm); +} + +/****************************************************************************/ + +/** Check for SoE configurations to be applied in SAFEOP. + */ +void ec_fsm_slave_config_enter_soe_conf_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req; + + if (!slave->config) { + ec_fsm_slave_config_enter_op(fsm); + return; + } + + list_for_each_entry(req, &slave->config->soe_configs, list) { + if (req->al_state == EC_AL_STATE_SAFEOP) { + // start SoE configuration + fsm->state = ec_fsm_slave_config_state_soe_conf_safeop; + fsm->soe_request = req; + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // No SoE configuration to be applied in SAFEOP + ec_fsm_slave_config_enter_op(fsm); +} + +/****************************************************************************/ + +/** Slave configuration state: SOE_CONF. + */ +void ec_fsm_slave_config_state_soe_conf_safeop( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram)) { + return; + } + + if (!ec_fsm_soe_success(fsm->fsm_soe)) { + EC_SLAVE_ERR(slave, "SoE configuration failed.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + if (!fsm->slave->config) { // config removed in the meantime + ec_fsm_slave_config_reconfigure(fsm); + return; + } + + // Another IDN to configure in SAFEOP? + while (fsm->soe_request->list.next != &fsm->slave->config->soe_configs) { + fsm->soe_request = list_entry(fsm->soe_request->list.next, + ec_soe_request_t, list); + if (fsm->soe_request->al_state == EC_AL_STATE_SAFEOP) { + ec_soe_request_copy(&fsm->soe_request_copy, fsm->soe_request); + ec_soe_request_write(&fsm->soe_request_copy); + ec_fsm_soe_transfer(fsm->fsm_soe, fsm->slave, + &fsm->soe_request_copy); + ec_fsm_soe_exec(fsm->fsm_soe, fsm->datagram); + return; + } + } + + // All SAFEOP IDNs are now configured. + ec_fsm_slave_config_enter_op(fsm); +} + +/****************************************************************************/ + +/** Bring slave to OP. + */ +void ec_fsm_slave_config_enter_op( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + // set state to OP + fsm->state = ec_fsm_slave_config_state_op; + ec_fsm_change_start(fsm->fsm_change, fsm->slave, EC_SLAVE_STATE_OP); + ec_fsm_change_exec(fsm->fsm_change); // execute immediately +} + +/****************************************************************************/ + +/** Slave configuration state: OP + */ +void ec_fsm_slave_config_state_op( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (ec_fsm_change_exec(fsm->fsm_change)) return; + + if (!ec_fsm_change_success(fsm->fsm_change)) { + if (!fsm->fsm_change->spontaneous_change) + slave->error_flag = 1; + fsm->state = ec_fsm_slave_config_state_error; + return; + } + + // slave is now in OP + + EC_SLAVE_DBG(slave, 1, "Now in OP. Finished configuration.\n"); + + fsm->state = ec_fsm_slave_config_state_end; // successful +} + +/****************************************************************************/ + +/** Reconfigure the slave starting at INIT. + */ +void ec_fsm_slave_config_reconfigure( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ + EC_SLAVE_DBG(fsm->slave, 1, "Slave configuration detached during " + "configuration. Reconfiguring."); + + ec_fsm_slave_config_enter_init(fsm); // reconfigure +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_slave_config_state_error( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_slave_config_state_end( + ec_fsm_slave_config_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_slave_config.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_slave_config.h @@ -0,0 +1,81 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + \file + EtherCAT slave configuration state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SLAVE_CONFIG_H__ +#define __EC_FSM_SLAVE_CONFIG_H__ + +#include "globals.h" +#include "slave.h" +#include "datagram.h" +#include "fsm_change.h" +#include "fsm_coe.h" +#include "fsm_pdo.h" +#include "fsm_eoe.h" + +/****************************************************************************/ + +/** \see ec_fsm_slave_config */ +typedef struct ec_fsm_slave_config ec_fsm_slave_config_t; + +/** Finite state machine to configure an EtherCAT slave. + */ +struct ec_fsm_slave_config +{ + ec_datagram_t *datagram; /**< Datagram used in the state machine. */ + ec_fsm_change_t *fsm_change; /**< State change state machine. */ + ec_fsm_coe_t *fsm_coe; /**< CoE state machine. */ + ec_fsm_soe_t *fsm_soe; /**< SoE state machine. */ + ec_fsm_pdo_t *fsm_pdo; /**< PDO configuration state machine. */ + ec_fsm_eoe_t *fsm_eoe; /**< EoE state machine. */ + + ec_slave_t *slave; /**< Slave the FSM runs on. */ + void (*state)(ec_fsm_slave_config_t *); /**< State function. */ + unsigned int retries; /**< Retries on datagram timeout. */ + ec_sdo_request_t *request; /**< SDO request for SDO configuration. */ + ec_sdo_request_t request_copy; /**< Copied SDO request. */ + ec_soe_request_t *soe_request; /**< SDO request for SDO configuration. */ + ec_soe_request_t soe_request_copy; /**< Copied SDO request. */ + unsigned long jiffies_start; /**< For timeout calculations. */ + unsigned int take_time; /**< Store jiffies after datagram reception. */ + unsigned long wait_ms; /**< Wait time (used to wait before SAFEOP). */ +}; + +/****************************************************************************/ + +void ec_fsm_slave_config_init(ec_fsm_slave_config_t *, ec_datagram_t *, + ec_fsm_change_t *, ec_fsm_coe_t *, ec_fsm_soe_t *, ec_fsm_pdo_t *, + ec_fsm_eoe_t *); +void ec_fsm_slave_config_clear(ec_fsm_slave_config_t *); + +void ec_fsm_slave_config_start(ec_fsm_slave_config_t *, ec_slave_t *); + +int ec_fsm_slave_config_exec(ec_fsm_slave_config_t *); +int ec_fsm_slave_config_success(const ec_fsm_slave_config_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_slave_scan.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_slave_scan.c @@ -0,0 +1,1121 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave state machines. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "slave_config.h" + +#include "fsm_slave_scan.h" + +/****************************************************************************/ + +// prototypes for private methods +int ec_fsm_slave_scan_running(const ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_sii_size(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_assign_sii(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_datalink(ec_fsm_slave_scan_t *); +#ifdef EC_REGALIAS +void ec_fsm_slave_scan_enter_regalias(ec_fsm_slave_scan_t *); +#endif +void ec_fsm_slave_scan_enter_preop(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_enter_pdos(ec_fsm_slave_scan_t *); + +/****************************************************************************/ + +void ec_fsm_slave_scan_state_start(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_address(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_state(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_base(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_dc_cap(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_dc_times(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_datalink(ec_fsm_slave_scan_t *); +#ifdef EC_SII_ASSIGN +void ec_fsm_slave_scan_state_assign_sii(ec_fsm_slave_scan_t *); +#endif +void ec_fsm_slave_scan_state_sii_size(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_sii_data(ec_fsm_slave_scan_t *); +#ifdef EC_REGALIAS +void ec_fsm_slave_scan_state_regalias(ec_fsm_slave_scan_t *); +#endif +void ec_fsm_slave_scan_state_preop(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_sync(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_pdos(ec_fsm_slave_scan_t *); + +void ec_fsm_slave_scan_state_end(ec_fsm_slave_scan_t *); +void ec_fsm_slave_scan_state_error(ec_fsm_slave_scan_t *); + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_slave_scan_init( + ec_fsm_slave_scan_t *fsm, /**< Slave scanning state machine. */ + ec_datagram_t *datagram, /**< Datagram to use. */ + ec_fsm_slave_config_t *fsm_slave_config, /**< Slave configuration + state machine to use. */ + ec_fsm_pdo_t *fsm_pdo /**< PDO configuration machine to use. */ + ) +{ + fsm->datagram = datagram; + fsm->fsm_slave_config = fsm_slave_config; + fsm->fsm_pdo = fsm_pdo; + + // init sub state machines + ec_fsm_sii_init(&fsm->fsm_sii, fsm->datagram); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_slave_scan_clear(ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + // clear sub state machines + ec_fsm_sii_clear(&fsm->fsm_sii); +} + +/****************************************************************************/ + +/** + * Start slave scan state machine. + */ + +void ec_fsm_slave_scan_start( + ec_fsm_slave_scan_t *fsm, /**< slave state machine */ + ec_slave_t *slave /**< slave to configure */ + ) +{ + fsm->slave = slave; + fsm->state = ec_fsm_slave_scan_state_start; +} + +/****************************************************************************/ + +/** + \return false, if state machine has terminated +*/ + +int ec_fsm_slave_scan_running( + const ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + return fsm->state != ec_fsm_slave_scan_state_end + && fsm->state != ec_fsm_slave_scan_state_error; +} + +/****************************************************************************/ + +/** + Executes the current state of the state machine. + If the state machine's datagram is not sent or received yet, the execution + of the state machine is delayed to the next cycle. + \return false, if state machine has terminated +*/ + +int ec_fsm_slave_scan_exec(ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + if (fsm->datagram->state == EC_DATAGRAM_SENT + || fsm->datagram->state == EC_DATAGRAM_QUEUED) { + // datagram was not sent or received yet. + return ec_fsm_slave_scan_running(fsm); + } + + fsm->state(fsm); + return ec_fsm_slave_scan_running(fsm); +} + +/****************************************************************************/ + +/** + \return true, if the state machine terminated gracefully +*/ + +int ec_fsm_slave_scan_success(const ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + return fsm->state == ec_fsm_slave_scan_state_end; +} + +/***************************************************************************** + * slave scan state machine + ****************************************************************************/ + +/** + Slave scan state: START. + First state of the slave state machine. Writes the station address to the + slave, according to its ring position. +*/ + +void ec_fsm_slave_scan_state_start(ec_fsm_slave_scan_t *fsm /**< slave state machine */) +{ + // write station address + ec_datagram_apwr(fsm->datagram, fsm->slave->ring_position, 0x0010, 2); + EC_WRITE_U16(fsm->datagram->data, fsm->slave->station_address); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_address; +} + +/****************************************************************************/ + +/** + Slave scan state: ADDRESS. +*/ + +void ec_fsm_slave_scan_state_address( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(fsm->slave, + "Failed to receive station address datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(fsm->slave, "Failed to write station address: "); + ec_datagram_print_wc_error(datagram); + return; + } + + // Read AL state + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x0130, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_state; +} + +/****************************************************************************/ + +/** + Slave scan state: STATE. +*/ + +void ec_fsm_slave_scan_state_state( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive AL state datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read AL state: "); + ec_datagram_print_wc_error(datagram); + return; + } + + slave->current_state = EC_READ_U8(datagram->data); + if (slave->current_state & EC_SLAVE_STATE_ACK_ERR) { + char state_str[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, state_str, 0); + EC_SLAVE_WARN(slave, "Slave has state error bit set (%s)!\n", + state_str); + } + + // read base data + ec_datagram_fprd(datagram, fsm->slave->station_address, 0x0000, 12); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_base; +} + +/****************************************************************************/ + +/** Slave scan state: BASE. + */ +void ec_fsm_slave_scan_state_base( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + u8 octet; + int i; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive base data datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read base data: "); + ec_datagram_print_wc_error(datagram); + return; + } + + slave->base_type = EC_READ_U8 (datagram->data); + slave->base_revision = EC_READ_U8 (datagram->data + 1); + slave->base_build = EC_READ_U16(datagram->data + 2); + + slave->base_fmmu_count = EC_READ_U8 (datagram->data + 4); + if (slave->base_fmmu_count > EC_MAX_FMMUS) { + EC_SLAVE_WARN(slave, "Slave has more FMMUs (%u) than the master can" + " handle (%u).\n", slave->base_fmmu_count, EC_MAX_FMMUS); + slave->base_fmmu_count = EC_MAX_FMMUS; + } + + slave->base_sync_count = EC_READ_U8(datagram->data + 5); + if (slave->base_sync_count > EC_MAX_SYNC_MANAGERS) { + EC_SLAVE_WARN(slave, "Slave provides more sync managers (%u)" + " than the master can handle (%u).\n", + slave->base_sync_count, EC_MAX_SYNC_MANAGERS); + slave->base_sync_count = EC_MAX_SYNC_MANAGERS; + } + + octet = EC_READ_U8(datagram->data + 7); + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].desc = (octet >> (2 * i)) & 0x03; + } + + octet = EC_READ_U8(datagram->data + 8); + slave->base_fmmu_bit_operation = octet & 0x01; + slave->base_dc_supported = (octet >> 2) & 0x01; + slave->base_dc_range = ((octet >> 3) & 0x01) ? EC_DC_64 : EC_DC_32; + + if (slave->base_dc_supported) { + // read DC capabilities + ec_datagram_fprd(datagram, slave->station_address, 0x0910, + slave->base_dc_range == EC_DC_64 ? 8 : 4); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_dc_cap; + } else { + ec_fsm_slave_scan_enter_datalink(fsm); + } +} + +/****************************************************************************/ + +/** + Slave scan state: DC CAPABILITIES. +*/ + +void ec_fsm_slave_scan_state_dc_cap( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive system time datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter == 1) { + slave->has_dc_system_time = 1; + EC_SLAVE_DBG(slave, 1, "Slave has the System Time register.\n"); + } else if (datagram->working_counter == 0) { + EC_SLAVE_DBG(slave, 1, "Slave has no System Time register; delay " + "measurement only.\n"); + } else { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to determine, if system time register is " + "supported: "); + ec_datagram_print_wc_error(datagram); + return; + } + + // read DC port receive times + ec_datagram_fprd(datagram, slave->station_address, 0x0900, 16); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_dc_times; +} + +/****************************************************************************/ + +/** + Slave scan state: DC TIMES. +*/ + +void ec_fsm_slave_scan_state_dc_times( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + int i; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive system time datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to get DC receive times: "); + ec_datagram_print_wc_error(datagram); + return; + } + + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].receive_time = EC_READ_U32(datagram->data + 4 * i); + } + + ec_fsm_slave_scan_enter_datalink(fsm); +} + +/****************************************************************************/ + +/** + Slave scan entry function: DATALINK. +*/ + +void ec_fsm_slave_scan_enter_datalink( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + // read data link status + ec_datagram_fprd(datagram, slave->station_address, 0x0110, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_datalink; +} + +/****************************************************************************/ + +/** Enter slave scan state SII_SIZE. + */ +void ec_fsm_slave_scan_enter_sii_size( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + // Start fetching SII size + + EC_SLAVE_DBG(fsm->slave, 1, "Determining SII size.\n"); + + fsm->sii_offset = EC_FIRST_SII_CATEGORY_OFFSET; // first category header + ec_fsm_sii_read(&fsm->fsm_sii, fsm->slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + fsm->state = ec_fsm_slave_scan_state_sii_size; + fsm->state(fsm); // execute state immediately +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** Enter slave scan state ASSIGN_SII. + */ +void ec_fsm_slave_scan_enter_assign_sii( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + EC_SLAVE_DBG(slave, 1, "Assigning SII access to EtherCAT.\n"); + + // assign SII to ECAT + ec_datagram_fpwr(datagram, slave->station_address, 0x0500, 1); + EC_WRITE_U8(datagram->data, 0x00); // EtherCAT + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_assign_sii; +} + +#endif + +/****************************************************************************/ + +/** + Slave scan state: DATALINK. +*/ + +void ec_fsm_slave_scan_state_datalink( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + uint16_t dl_status; + unsigned int i; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive DL status datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read DL status: "); + ec_datagram_print_wc_error(datagram); + return; + } + + dl_status = EC_READ_U16(datagram->data); + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].link.link_up = + dl_status & (1 << (4 + i)) ? 1 : 0; + slave->ports[i].link.loop_closed = + dl_status & (1 << (8 + i * 2)) ? 1 : 0; + slave->ports[i].link.signal_detected = + dl_status & (1 << (9 + i * 2)) ? 1 : 0; + } + +#ifdef EC_SII_ASSIGN + ec_fsm_slave_scan_enter_assign_sii(fsm); +#else + ec_fsm_slave_scan_enter_sii_size(fsm); +#endif +} + +/****************************************************************************/ + +#ifdef EC_SII_ASSIGN + +/** + Slave scan state: ASSIGN_SII. +*/ + +void ec_fsm_slave_scan_state_assign_sii( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + return; + } + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + EC_SLAVE_WARN(slave, "Failed to receive SII assignment datagram: "); + ec_datagram_print_state(datagram); + // Try to go on, probably assignment is correct + goto continue_with_sii_size; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_WARN(slave, "Failed to assign SII to EtherCAT: "); + ec_datagram_print_wc_error(datagram); + // Try to go on, probably assignment is correct + } + +continue_with_sii_size: + ec_fsm_slave_scan_enter_sii_size(fsm); +} + +#endif + +/****************************************************************************/ + +/** + Slave scan state: SII SIZE. +*/ + +void ec_fsm_slave_scan_state_sii_size( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint16_t cat_type, cat_size; + + if (ec_fsm_sii_exec(&fsm->fsm_sii)) + return; + + if (!ec_fsm_sii_success(&fsm->fsm_sii)) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to determine SII content size:" + " Reading word offset 0x%04x failed. Assuming %u words.\n", + fsm->sii_offset, EC_FIRST_SII_CATEGORY_OFFSET); + slave->sii_nwords = EC_FIRST_SII_CATEGORY_OFFSET; + goto alloc_sii; + } + + cat_type = EC_READ_U16(fsm->fsm_sii.value); + cat_size = EC_READ_U16(fsm->fsm_sii.value + 2); + + if (cat_type != 0xFFFF) { // not the last category + off_t next_offset = 2UL + fsm->sii_offset + cat_size; + + EC_SLAVE_DBG(slave, 1, "Found category type %u with size %u." + " Proceeding to offset %zd.\n", + cat_type, cat_size, (ssize_t)next_offset); + + if (next_offset >= EC_MAX_SII_SIZE) { + EC_SLAVE_WARN(slave, "SII size exceeds %u words" + " (0xffff limiter missing?).\n", EC_MAX_SII_SIZE); + // cut off category data... + slave->sii_nwords = EC_FIRST_SII_CATEGORY_OFFSET; + goto alloc_sii; + } + fsm->sii_offset = next_offset; + ec_fsm_sii_read(&fsm->fsm_sii, slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute state immediately + return; + } + + slave->sii_nwords = fsm->sii_offset + 1; + +alloc_sii: + if (slave->sii_words) { + EC_SLAVE_WARN(slave, "Freeing old SII data...\n"); + kfree(slave->sii_words); + } + + if (!(slave->sii_words = + (uint16_t *) kmalloc(slave->sii_nwords * 2, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate %zu words of SII data.\n", + slave->sii_nwords); + slave->sii_nwords = 0; + slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + return; + } + + // Start fetching SII contents + + fsm->state = ec_fsm_slave_scan_state_sii_data; + fsm->sii_offset = 0x0000; + ec_fsm_sii_read(&fsm->fsm_sii, slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute state immediately +} + +/****************************************************************************/ + +/** + Slave scan state: SII DATA. +*/ + +void ec_fsm_slave_scan_state_sii_data(ec_fsm_slave_scan_t *fsm + /**< slave state machine */) +{ + ec_slave_t *slave = fsm->slave; + uint16_t *cat_word, cat_type, cat_size; + + if (ec_fsm_sii_exec(&fsm->fsm_sii)) return; + + if (!ec_fsm_sii_success(&fsm->fsm_sii)) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to fetch SII contents.\n"); + return; + } + + // 2 words fetched + + if (fsm->sii_offset + 2 <= slave->sii_nwords) { // 2 words fit + memcpy(slave->sii_words + fsm->sii_offset, fsm->fsm_sii.value, 4); + } else { // copy the last word + memcpy(slave->sii_words + fsm->sii_offset, fsm->fsm_sii.value, 2); + } + + if (fsm->sii_offset + 2 < slave->sii_nwords) { + // fetch the next 2 words + fsm->sii_offset += 2; + ec_fsm_sii_read(&fsm->fsm_sii, slave, fsm->sii_offset, + EC_FSM_SII_USE_CONFIGURED_ADDRESS); + ec_fsm_sii_exec(&fsm->fsm_sii); // execute state immediately + return; + } + + // Evaluate SII contents + + ec_slave_clear_sync_managers(slave); + + slave->sii.alias = + EC_READ_U16(slave->sii_words + 0x0004); + slave->effective_alias = slave->sii.alias; + slave->sii.vendor_id = + EC_READ_U32(slave->sii_words + 0x0008); + slave->sii.product_code = + EC_READ_U32(slave->sii_words + 0x000A); + slave->sii.revision_number = + EC_READ_U32(slave->sii_words + 0x000C); + slave->sii.serial_number = + EC_READ_U32(slave->sii_words + 0x000E); + slave->sii.boot_rx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x0014); + slave->sii.boot_rx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x0015); + slave->sii.boot_tx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x0016); + slave->sii.boot_tx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x0017); + slave->sii.std_rx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x0018); + slave->sii.std_rx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x0019); + slave->sii.std_tx_mailbox_offset = + EC_READ_U16(slave->sii_words + 0x001A); + slave->sii.std_tx_mailbox_size = + EC_READ_U16(slave->sii_words + 0x001B); + slave->sii.mailbox_protocols = + EC_READ_U16(slave->sii_words + 0x001C); + if (slave->sii.mailbox_protocols) { + int need_delim = 0; + uint16_t all = EC_MBOX_AOE | EC_MBOX_COE | EC_MBOX_FOE | + EC_MBOX_SOE | EC_MBOX_VOE; + if ((slave->sii.mailbox_protocols & all) && + slave->master->debug_level >= 1) { + EC_SLAVE_DBG(slave, 1, "Slave announces to support "); + if (slave->sii.mailbox_protocols & EC_MBOX_AOE) { + printk(KERN_CONT "AoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_COE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "CoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_FOE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "FoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_SOE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "SoE"); + need_delim = 1; + } + if (slave->sii.mailbox_protocols & EC_MBOX_VOE) { + if (need_delim) { + printk(KERN_CONT ", "); + } + printk(KERN_CONT "VoE"); + need_delim = 1; + } + printk(KERN_CONT ".\n"); + } + if (slave->sii.mailbox_protocols & ~all) { + EC_SLAVE_DBG(slave, 1, "Slave announces to support unknown" + " mailbox protocols 0x%04X.", + slave->sii.mailbox_protocols & ~all); + } + } + else { + EC_SLAVE_DBG(slave, 1, "Slave announces to support no mailbox" + " protocols."); + } + + if (slave->sii.boot_rx_mailbox_offset == 0xffff || + slave->sii.boot_rx_mailbox_size == 0xffff || + slave->sii.boot_tx_mailbox_offset == 0xffff || + slave->sii.boot_tx_mailbox_size == 0xffff || + slave->sii.std_rx_mailbox_offset == 0xffff || + slave->sii.std_rx_mailbox_size == 0xffff || + slave->sii.std_tx_mailbox_offset == 0xffff || + slave->sii.std_tx_mailbox_size == 0xffff) { + slave->sii.mailbox_protocols = 0x0000; + EC_SLAVE_ERR(slave, "Invalid mailbox settings in SII." + " Disabling mailbox communication."); + } + + if (slave->sii_nwords == EC_FIRST_SII_CATEGORY_OFFSET) { + // sii does not contain category data + fsm->state = ec_fsm_slave_scan_state_end; + return; + } + + if (slave->sii_nwords < EC_FIRST_SII_CATEGORY_OFFSET + 1) { + EC_SLAVE_ERR(slave, "Unexpected end of SII data:" + " First category header missing.\n"); + goto end; + } + + // evaluate category data + cat_word = slave->sii_words + EC_FIRST_SII_CATEGORY_OFFSET; + while (EC_READ_U16(cat_word) != 0xFFFF) { + + // type and size words must fit + if (cat_word + 2 - slave->sii_words > slave->sii_nwords) { + EC_SLAVE_ERR(slave, "Unexpected end of SII data:" + " Category header incomplete.\n"); + goto end; + } + + cat_type = EC_READ_U16(cat_word) & 0x7FFF; + cat_size = EC_READ_U16(cat_word + 1); + cat_word += 2; + + if (cat_word + cat_size - slave->sii_words > slave->sii_nwords) { + EC_SLAVE_WARN(slave, "Unexpected end of SII data:" + " Category data incomplete.\n"); + goto end; + } + + switch (cat_type) { + case 0x000A: + if (ec_slave_fetch_sii_strings(slave, (uint8_t *) cat_word, + cat_size * 2)) + goto end; + break; + case 0x001E: + if (ec_slave_fetch_sii_general(slave, (uint8_t *) cat_word, + cat_size * 2)) + goto end; + break; + case 0x0028: + break; + case 0x0029: + if (ec_slave_fetch_sii_syncs(slave, (uint8_t *) cat_word, + cat_size * 2)) + goto end; + break; + case 0x0032: + if (ec_slave_fetch_sii_pdos( slave, (uint8_t *) cat_word, + cat_size * 2, EC_DIR_INPUT)) // TxPDO + goto end; + break; + case 0x0033: + if (ec_slave_fetch_sii_pdos( slave, (uint8_t *) cat_word, + cat_size * 2, EC_DIR_OUTPUT)) // RxPDO + goto end; + break; + default: + EC_SLAVE_DBG(slave, 1, "Unknown category type 0x%04X.\n", + cat_type); + } + + cat_word += cat_size; + if (cat_word - slave->sii_words >= slave->sii_nwords) { + EC_SLAVE_WARN(slave, "Unexpected end of SII data:" + " Next category header missing.\n"); + goto end; + } + } + +#ifdef EC_REGALIAS + ec_fsm_slave_scan_enter_regalias(fsm); +#else + if (slave->sii.mailbox_protocols & EC_MBOX_COE) { + ec_fsm_slave_scan_enter_preop(fsm); + } else { + fsm->state = ec_fsm_slave_scan_state_end; + } +#endif + return; + +end: + EC_SLAVE_ERR(slave, "Failed to analyze category data.\n"); + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; +} + +/****************************************************************************/ + +#ifdef EC_REGALIAS + +/** Slave scan entry function: REGALIAS. + */ +void ec_fsm_slave_scan_enter_regalias( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + // read alias from register + EC_SLAVE_DBG(slave, 1, "Reading alias from register.\n"); + ec_datagram_fprd(datagram, slave->station_address, 0x0012, 2); + ec_datagram_zero(datagram); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_regalias; +} + +/****************************************************************************/ + +/** Slave scan state: REGALIAS. + */ +void ec_fsm_slave_scan_state_regalias( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive register alias datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + EC_SLAVE_DBG(slave, 1, "Failed to read register alias.\n"); + } else { + slave->effective_alias = EC_READ_U16(datagram->data); + EC_SLAVE_DBG(slave, 1, "Read alias %u from register.\n", + slave->effective_alias); + } + + if (slave->sii.mailbox_protocols & EC_MBOX_COE) { + ec_fsm_slave_scan_enter_preop(fsm); + } else { + fsm->state = ec_fsm_slave_scan_state_end; + } +} + +#endif // defined EC_REGALIAS + +/****************************************************************************/ + +/** Enter slave scan state PREOP. + */ +void ec_fsm_slave_scan_enter_preop( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + uint8_t current_state = slave->current_state & EC_SLAVE_STATE_MASK; + + if (current_state != EC_SLAVE_STATE_PREOP + && current_state != EC_SLAVE_STATE_SAFEOP + && current_state != EC_SLAVE_STATE_OP) { + if (slave->master->debug_level) { + char str[EC_STATE_STRING_SIZE]; + ec_state_string(current_state, str, 0); + EC_SLAVE_DBG(slave, 0, "Slave is not in the state" + " to do mailbox com (%s), setting to PREOP.\n", str); + } + + fsm->state = ec_fsm_slave_scan_state_preop; + ec_slave_request_state(slave, EC_SLAVE_STATE_PREOP); + ec_fsm_slave_config_start(fsm->fsm_slave_config, slave); + ec_fsm_slave_config_exec(fsm->fsm_slave_config); + } else { + EC_SLAVE_DBG(slave, 1, "Reading mailbox" + " sync manager configuration.\n"); + + /* Scan current sync manager configuration to get configured mailbox + * sizes. */ + ec_datagram_fprd(fsm->datagram, slave->station_address, 0x0800, + EC_SYNC_PAGE_SIZE * 2); + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_slave_scan_state_sync; + } +} + +/****************************************************************************/ + +/** Slave scan state: PREOP. + */ +void ec_fsm_slave_scan_state_preop( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + if (ec_fsm_slave_config_exec(fsm->fsm_slave_config)) + return; + + if (!ec_fsm_slave_config_success(fsm->fsm_slave_config)) { + fsm->state = ec_fsm_slave_scan_state_error; + return; + } + + ec_fsm_slave_scan_enter_pdos(fsm); +} + +/****************************************************************************/ + +/** Slave scan state: SYNC. + */ +void ec_fsm_slave_scan_state_sync( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_datagram_t *datagram = fsm->datagram; + ec_slave_t *slave = fsm->slave; + uint16_t tx_offset, tx_size, rx_offset, rx_size; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to receive sync manager" + " configuration datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + fsm->slave->error_flag = 1; + fsm->state = ec_fsm_slave_scan_state_error; + EC_SLAVE_ERR(slave, "Failed to read DL status: "); + ec_datagram_print_wc_error(datagram); + return; + } + + rx_offset = EC_READ_U16(datagram->data); + rx_size = EC_READ_U16(datagram->data + 2); + tx_offset = EC_READ_U16(datagram->data + 8); + tx_size = EC_READ_U16(datagram->data + 10); + + if (rx_size == 0xffff) { + fsm->state = ec_fsm_slave_scan_state_error; + slave->sii.mailbox_protocols = 0x0000; + EC_SLAVE_ERR(slave, "Invalid RX mailbox size (%u) configured." + " Disabling mailbox communication.", rx_size); + return; + } + + if (tx_size == 0xffff) { + fsm->state = ec_fsm_slave_scan_state_error; + slave->sii.mailbox_protocols = 0x0000; + EC_SLAVE_ERR(slave, "Invalid TX mailbox size (%u) configured." + " Disabling mailbox communication.", tx_size); + return; + } + + slave->configured_rx_mailbox_offset = rx_offset; + slave->configured_rx_mailbox_size = rx_size; + slave->configured_tx_mailbox_offset = tx_offset; + slave->configured_tx_mailbox_size = tx_size; + + EC_SLAVE_DBG(slave, 1, "Mailbox configuration:\n"); + EC_SLAVE_DBG(slave, 1, " RX offset=0x%04x size=%u\n", + slave->configured_rx_mailbox_offset, + slave->configured_rx_mailbox_size); + EC_SLAVE_DBG(slave, 1, " TX offset=0x%04x size=%u\n", + slave->configured_tx_mailbox_offset, + slave->configured_tx_mailbox_size); + + ec_fsm_slave_scan_enter_pdos(fsm); +} + +/****************************************************************************/ + +/** Enter slave scan state PDOS. + */ +void ec_fsm_slave_scan_enter_pdos( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + ec_slave_t *slave = fsm->slave; + + EC_SLAVE_DBG(slave, 1, "Scanning PDO assignment and mapping.\n"); + fsm->state = ec_fsm_slave_scan_state_pdos; + ec_fsm_pdo_start_reading(fsm->fsm_pdo, slave); + ec_fsm_pdo_exec(fsm->fsm_pdo, fsm->datagram); // execute immediately +} + +/****************************************************************************/ + +/** Slave scan state: PDOS. + */ +void ec_fsm_slave_scan_state_pdos( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ + if (ec_fsm_pdo_exec(fsm->fsm_pdo, fsm->datagram)) { + return; + } + + if (!ec_fsm_pdo_success(fsm->fsm_pdo)) { + fsm->state = ec_fsm_slave_scan_state_error; + return; + } + + // reading PDO configuration finished + fsm->state = ec_fsm_slave_scan_state_end; +} + +/***************************************************************************** + * Common state functions + ****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_slave_scan_state_error( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_slave_scan_state_end( + ec_fsm_slave_scan_t *fsm /**< slave state machine */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_slave_scan.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_slave_scan.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave scanning state machine. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SLAVE_SCAN_H__ +#define __EC_FSM_SLAVE_SCAN_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "fsm_sii.h" +#include "fsm_change.h" +#include "fsm_coe.h" +#include "fsm_pdo.h" + +/****************************************************************************/ + +/** \see ec_fsm_slave_scan */ +typedef struct ec_fsm_slave_scan ec_fsm_slave_scan_t; + +/** Finite state machine for scanning an EtherCAT slave. + */ +struct ec_fsm_slave_scan +{ + ec_slave_t *slave; /**< Slave the FSM runs on. */ + ec_datagram_t *datagram; /**< Datagram used in the state machine. */ + ec_fsm_slave_config_t *fsm_slave_config; /**< Slave configuration state + machine to use. */ + ec_fsm_pdo_t *fsm_pdo; /**< PDO configuration state machine to use. */ + unsigned int retries; /**< Retries on datagram timeout. */ + + void (*state)(ec_fsm_slave_scan_t *); /**< State function. */ + uint16_t sii_offset; /**< SII offset in words. */ + + ec_fsm_sii_t fsm_sii; /**< SII state machine. */ +}; + +/****************************************************************************/ + +void ec_fsm_slave_scan_init(ec_fsm_slave_scan_t *, ec_datagram_t *, + ec_fsm_slave_config_t *, ec_fsm_pdo_t *); +void ec_fsm_slave_scan_clear(ec_fsm_slave_scan_t *); + +void ec_fsm_slave_scan_start(ec_fsm_slave_scan_t *, ec_slave_t *); + +int ec_fsm_slave_scan_exec(ec_fsm_slave_scan_t *); +int ec_fsm_slave_scan_success(const ec_fsm_slave_scan_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_soe.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_soe.c @@ -0,0 +1,844 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2020 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT SoE state machines. +*/ + +/****************************************************************************/ + +#include "globals.h" +#include "master.h" +#include "mailbox.h" +#include "fsm_soe.h" + +/****************************************************************************/ + +/** SoE operations + */ +enum { + OPCODE_READ_REQUEST = 0x01, /**< Read request. */ + OPCODE_READ_RESPONSE = 0x02, /**< Read response. */ + OPCODE_WRITE_REQUEST = 0x03, /**< Write request. */ + OPCODE_WRITE_RESPONSE = 0x04 /**< Write response. */ +}; + +/** Size of all SoE headers. + */ +#define EC_SOE_SIZE 0x04 + +/** SoE header size. + */ +#define EC_SOE_HEADER_SIZE (EC_MBOX_HEADER_SIZE + EC_SOE_SIZE) + +/** SoE response timeout [ms]. + */ +#define EC_SOE_RESPONSE_TIMEOUT 1000 + +/****************************************************************************/ + +// prototypes for private methods +void ec_print_soe_error(const ec_slave_t *, uint16_t); +void ec_fsm_soe_print_error(ec_fsm_soe_t *); +int ec_fsm_soe_prepare_read(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_next_fragment(ec_fsm_soe_t *, ec_datagram_t *); + +/****************************************************************************/ + +void ec_fsm_soe_read_start(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_read_request(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_read_check(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_read_response(ec_fsm_soe_t *, ec_datagram_t *); + +void ec_fsm_soe_write_start(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_request(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_check(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_write_response(ec_fsm_soe_t *, ec_datagram_t *); + +void ec_fsm_soe_end(ec_fsm_soe_t *, ec_datagram_t *); +void ec_fsm_soe_error(ec_fsm_soe_t *, ec_datagram_t *); + +/****************************************************************************/ + +extern const ec_code_msg_t soe_error_codes[]; + +/****************************************************************************/ + +/** Outputs an SoE error code. +*/ +void ec_print_soe_error(const ec_slave_t *slave, uint16_t error_code) +{ + const ec_code_msg_t *error_msg; + + for (error_msg = soe_error_codes; error_msg->code; error_msg++) { + if (error_msg->code == error_code) { + EC_SLAVE_ERR(slave, "SoE error 0x%04X: \"%s\".\n", + error_msg->code, error_msg->message); + return; + } + } + + EC_SLAVE_ERR(slave, "Unknown SoE error 0x%04X.\n", error_code); +} + +/****************************************************************************/ + +/** Constructor. + */ +void ec_fsm_soe_init( + ec_fsm_soe_t *fsm /**< finite state machine */ + ) +{ + fsm->state = NULL; + fsm->datagram = NULL; + fsm->fragment_size = 0; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_fsm_soe_clear( + ec_fsm_soe_t *fsm /**< finite state machine */ + ) +{ +} + +/****************************************************************************/ + +/** Starts to transfer an IDN to/from a slave. + */ +void ec_fsm_soe_transfer( + ec_fsm_soe_t *fsm, /**< State machine. */ + ec_slave_t *slave, /**< EtherCAT slave. */ + ec_soe_request_t *request /**< SoE request. */ + ) +{ + fsm->slave = slave; + fsm->request = request; + + if (request->dir == EC_DIR_OUTPUT) { + fsm->state = ec_fsm_soe_write_start; + } else { + fsm->state = ec_fsm_soe_read_start; + } +} + +/****************************************************************************/ + +/** Executes the current state of the state machine. + * + * \return 1 if the datagram was used, else 0. + */ +int ec_fsm_soe_exec( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + int datagram_used = 0; + + if (fsm->datagram && + (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT)) { + // datagram not received yet + return datagram_used; + } + + fsm->state(fsm, datagram); + + datagram_used = + fsm->state != ec_fsm_soe_end && fsm->state != ec_fsm_soe_error; + + if (datagram_used) { + fsm->datagram = datagram; + } else { + fsm->datagram = NULL; + } + + return datagram_used; +} + +/****************************************************************************/ + +/** Returns, if the state machine terminated with success. + * + * \return non-zero if successful. + */ +int ec_fsm_soe_success(const ec_fsm_soe_t *fsm /**< Finite state machine */) +{ + return fsm->state == ec_fsm_soe_end; +} + +/****************************************************************************/ + +/** Output information about a failed SoE transfer. + */ +void ec_fsm_soe_print_error(ec_fsm_soe_t *fsm /**< Finite state machine */) +{ + ec_soe_request_t *request = fsm->request; + + EC_SLAVE_ERR(fsm->slave, ""); + + if (request->dir == EC_DIR_OUTPUT) { + printk(KERN_CONT "Writing"); + } else { + printk(KERN_CONT "Reading"); + } + + printk(KERN_CONT " IDN 0x%04X failed.\n", request->idn); +} + +/***************************************************************************** + * SoE read state machine + ****************************************************************************/ + +/** Prepare a read operation. + * + * \return 0 on success, otherwise a negative error code. + */ +int ec_fsm_soe_prepare_read( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + uint8_t *data; + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_soe_request_t *request = fsm->request; + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_SOE, + EC_SOE_SIZE); + if (IS_ERR(data)) { + return PTR_ERR(data); + } + + EC_WRITE_U8(data, OPCODE_READ_REQUEST | (request->drive_no & 0x07) << 5); + EC_WRITE_U8(data + 1, 1 << 6); // request value + EC_WRITE_U16(data + 2, request->idn); + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC read request:\n"); + ec_print_data(data, EC_SOE_SIZE); + } + + fsm->request->jiffies_sent = jiffies; + fsm->state = ec_fsm_soe_read_request; + + return 0; +} + +/****************************************************************************/ + +/** SoE state: READ START. + */ +void ec_fsm_soe_read_start( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *request = fsm->request; + + EC_SLAVE_DBG(slave, 1, "Reading IDN 0x%04X of drive %u.\n", request->idn, + request->drive_no); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_SOE)) { + EC_SLAVE_ERR(slave, "Slave does not support SoE!\n"); + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + request->data_size = 0; + fsm->retries = EC_FSM_RETRIES; + + if (ec_fsm_soe_prepare_read(fsm, datagram)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + } +} + +/****************************************************************************/ + +/** SoE state: READ REQUEST. + */ +void ec_fsm_soe_read_request( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + if (ec_fsm_soe_prepare_read(fsm, datagram)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + } + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE read request: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < EC_SOE_RESPONSE_TIMEOUT) { + // no response; send request datagram again + if (ec_fsm_soe_prepare_read(fsm, datagram)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + } + return; + } + } + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE read request" + " failed after %lu ms: ", diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_read_check; +} + +/****************************************************************************/ + +/** CoE state: READ CHECK. + */ +void ec_fsm_soe_read_check( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE mailbox check datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (fsm->datagram->jiffies_received - fsm->jiffies_start) * + 1000 / HZ; + if (diff_ms >= EC_SOE_RESPONSE_TIMEOUT) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting for" + " read response.\n", diff_ms); + ec_fsm_soe_print_error(fsm); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_read_response; +} + +/****************************************************************************/ + +/** SoE state: READ RESPONSE. + */ +void ec_fsm_soe_read_response( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + uint8_t *data, mbox_prot, header, opcode, incomplete, error_flag, + value_included; + size_t rec_size, data_size; + ec_soe_request_t *req = fsm->request; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE read response datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE read response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC read response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_SOE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + ec_fsm_soe_print_error(fsm); + return; + } + + if (rec_size < EC_SOE_SIZE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received currupted SoE read response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + return; + } + + header = EC_READ_U8(data); + opcode = header & 0x7; + incomplete = (header >> 3) & 1; + error_flag = (header >> 4) & 1; + + if (opcode != OPCODE_READ_RESPONSE) { + EC_SLAVE_ERR(slave, "Received no read response (opcode %x).\n", + opcode); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + if (error_flag) { + req->error_code = EC_READ_U16(data + rec_size - 2); + EC_SLAVE_ERR(slave, "Received error response:\n"); + ec_print_soe_error(slave, req->error_code); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } else { + req->error_code = 0x0000; + } + + value_included = (EC_READ_U8(data + 1) >> 6) & 1; + if (!value_included) { + EC_SLAVE_ERR(slave, "No value included!\n"); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + data_size = rec_size - EC_SOE_SIZE; + if (ec_soe_request_append_data(req, + data + EC_SOE_SIZE, data_size)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (incomplete) { + EC_SLAVE_DBG(slave, 1, "SoE data incomplete. Waiting for fragment" + " at offset %zu.\n", req->data_size); + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_read_check; + } else { + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "IDN data:\n"); + ec_print_data(req->data, req->data_size); + } + + fsm->state = ec_fsm_soe_end; // success + } +} + +/***************************************************************************** + * SoE write state machine + ****************************************************************************/ + +/** Write next fragment. + */ +void ec_fsm_soe_write_next_fragment( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_soe_request_t *req = fsm->request; + uint8_t incomplete, *data; + size_t max_fragment_size, remaining_size; + uint16_t fragments_left; + + remaining_size = req->data_size - fsm->offset; + max_fragment_size = slave->configured_rx_mailbox_size - EC_SOE_HEADER_SIZE; + incomplete = remaining_size > max_fragment_size; + fsm->fragment_size = incomplete ? max_fragment_size : remaining_size; + fragments_left = remaining_size / fsm->fragment_size - 1; + if (remaining_size % fsm->fragment_size) { + fragments_left++; + } + + data = ec_slave_mbox_prepare_send(slave, datagram, EC_MBOX_TYPE_SOE, + EC_SOE_SIZE + fsm->fragment_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + EC_WRITE_U8(data, OPCODE_WRITE_REQUEST | incomplete << 3 | + (req->drive_no & 0x07) << 5); + EC_WRITE_U8(data + 1, 1 << 6); // only value included + EC_WRITE_U16(data + 2, incomplete ? fragments_left : req->idn); + memcpy(data + EC_SOE_SIZE, req->data + fsm->offset, fsm->fragment_size); + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC write request:\n"); + ec_print_data(data, EC_SOE_SIZE + fsm->fragment_size); + } + + fsm->state = ec_fsm_soe_write_request; +} + +/****************************************************************************/ + +/** SoE state: WRITE START. + */ +void ec_fsm_soe_write_start( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_soe_request_t *req = fsm->request; + + EC_SLAVE_DBG(slave, 1, "Writing IDN 0x%04X of drive %u (%zu byte).\n", + req->idn, req->drive_no, req->data_size); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_SOE)) { + EC_SLAVE_ERR(slave, "Slave does not support SoE!\n"); + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (slave->configured_rx_mailbox_size <= EC_SOE_HEADER_SIZE) { + EC_SLAVE_ERR(slave, "Mailbox size (%u) too small for SoE write.\n", + slave->configured_rx_mailbox_size); + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + fsm->offset = 0; + fsm->retries = EC_FSM_RETRIES; + ec_fsm_soe_write_next_fragment(fsm, datagram); + req->jiffies_sent = jiffies; +} + +/****************************************************************************/ + +/** SoE state: WRITE REQUEST. + */ +void ec_fsm_soe_write_request( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + unsigned long diff_ms; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_fsm_soe_write_next_fragment(fsm, datagram); + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE write request: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + diff_ms = (jiffies - fsm->request->jiffies_sent) * 1000 / HZ; + + if (fsm->datagram->working_counter != 1) { + if (!fsm->datagram->working_counter) { + if (diff_ms < EC_SOE_RESPONSE_TIMEOUT) { + // no response; send request datagram again + ec_fsm_soe_write_next_fragment(fsm, datagram); + return; + } + } + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE write request" + " failed after %lu ms: ", diff_ms); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + // fragment successfully sent + fsm->offset += fsm->fragment_size; + + if (fsm->offset < fsm->request->data_size) { + // next fragment + fsm->retries = EC_FSM_RETRIES; + ec_fsm_soe_write_next_fragment(fsm, datagram); + fsm->request->jiffies_sent = jiffies; + } else { + // all fragments sent; query response + fsm->jiffies_start = fsm->datagram->jiffies_sent; + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_write_check; + } +} + +/****************************************************************************/ + +/** CoE state: WRITE CHECK. + */ +void ec_fsm_soe_write_check( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + return; + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE write request datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE write request datagram: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (!ec_slave_mbox_check(fsm->datagram)) { + unsigned long diff_ms = + (datagram->jiffies_received - fsm->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_SOE_RESPONSE_TIMEOUT) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Timeout after %lu ms while waiting" + " for write response.\n", diff_ms); + ec_fsm_soe_print_error(fsm); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + fsm->retries = EC_FSM_RETRIES; + fsm->state = ec_fsm_soe_write_response; +} + +/****************************************************************************/ + +/** SoE state: WRITE RESPONSE. + */ +void ec_fsm_soe_write_response( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ + ec_slave_t *slave = fsm->slave; + ec_master_t *master = slave->master; + ec_soe_request_t *req = fsm->request; + uint8_t *data, mbox_prot, opcode, error_flag; + uint16_t idn; + size_t rec_size; + + if (fsm->datagram->state == EC_DATAGRAM_TIMED_OUT && fsm->retries--) { + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + return; // FIXME: request again? + } + + if (fsm->datagram->state != EC_DATAGRAM_RECEIVED) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Failed to receive SoE write" + " response datagram: "); + ec_datagram_print_state(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + if (fsm->datagram->working_counter != 1) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Reception of SoE write response failed: "); + ec_datagram_print_wc_error(fsm->datagram); + ec_fsm_soe_print_error(fsm); + return; + } + + data = ec_slave_mbox_fetch(slave, fsm->datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + fsm->state = ec_fsm_soe_error; + ec_fsm_soe_print_error(fsm); + return; + } + + if (master->debug_level) { + EC_SLAVE_DBG(slave, 0, "SSC write response:\n"); + ec_print_data(data, rec_size); + } + + if (mbox_prot != EC_MBOX_TYPE_SOE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received mailbox protocol 0x%02X as response.\n", + mbox_prot); + ec_fsm_soe_print_error(fsm); + return; + } + + if (rec_size < EC_SOE_SIZE) { + fsm->state = ec_fsm_soe_error; + EC_SLAVE_ERR(slave, "Received corrupted SoE write response" + " (%zu bytes)!\n", rec_size); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + return; + } + + opcode = EC_READ_U8(data) & 0x7; + if (opcode != OPCODE_WRITE_RESPONSE) { + EC_SLAVE_ERR(slave, "Received no write response" + " (opcode %x).\n", opcode); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + idn = EC_READ_U16(data + 2); + if (idn != req->idn) { + EC_SLAVE_ERR(slave, "Received response for" + " wrong IDN 0x%04x.\n", idn); + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + return; + } + + error_flag = (EC_READ_U8(data) >> 4) & 1; + if (error_flag) { + if (rec_size < EC_SOE_SIZE + 2) { + EC_SLAVE_ERR(slave, "Received corrupted error response" + " - error flag set, but received size is %zu.\n", + rec_size); + } else { + req->error_code = EC_READ_U16(data + EC_SOE_SIZE); + EC_SLAVE_ERR(slave, "Received error response:\n"); + ec_print_soe_error(slave, req->error_code); + } + ec_print_data(data, rec_size); + ec_fsm_soe_print_error(fsm); + fsm->state = ec_fsm_soe_error; + } else { + req->error_code = 0x0000; + fsm->state = ec_fsm_soe_end; // success + } +} + +/****************************************************************************/ + +/** State: ERROR. + */ +void ec_fsm_soe_error( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ + +/** State: END. + */ +void ec_fsm_soe_end( + ec_fsm_soe_t *fsm, /**< finite state machine */ + ec_datagram_t *datagram /**< Datagram to use. */ + ) +{ +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/fsm_soe.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/fsm_soe.h @@ -0,0 +1,67 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CoE state machines. +*/ + +/****************************************************************************/ + +#ifndef __EC_FSM_SOE_H__ +#define __EC_FSM_SOE_H__ + +#include "globals.h" +#include "datagram.h" +#include "slave.h" +#include "soe_request.h" + +/****************************************************************************/ + +typedef struct ec_fsm_soe ec_fsm_soe_t; /**< \see ec_fsm_soe */ + +/** Finite state machines for the Sercos over EtherCAT protocol. + */ +struct ec_fsm_soe { + ec_slave_t *slave; /**< slave the FSM runs on */ + unsigned int retries; /**< retries upon datagram timeout */ + + void (*state)(ec_fsm_soe_t *, ec_datagram_t *); /**< CoE state function */ + ec_datagram_t *datagram; /**< Datagram used in the previous step. */ + unsigned long jiffies_start; /**< Timestamp. */ + ec_soe_request_t *request; /**< SoE request */ + off_t offset; /**< IDN data offset during fragmented write. */ + size_t fragment_size; /**< Size of the current fragment. */ +}; + +/****************************************************************************/ + +void ec_fsm_soe_init(ec_fsm_soe_t *); +void ec_fsm_soe_clear(ec_fsm_soe_t *); + +void ec_fsm_soe_transfer(ec_fsm_soe_t *, ec_slave_t *, ec_soe_request_t *); + +int ec_fsm_soe_exec(ec_fsm_soe_t *, ec_datagram_t *); +int ec_fsm_soe_success(const ec_fsm_soe_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/globals.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/globals.h @@ -0,0 +1,314 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2021 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master. + * + * The file is free software; you can redistribute it and/or modify it under + * the terms of the GNU Lesser General Public License as published by the + * Free Software Foundation; version 2.1 of the License. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + * License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this file. If not, see . + * + ****************************************************************************/ + +/** \file + * Global definitions and macros. + */ + +/****************************************************************************/ + +#ifndef __EC_MASTER_GLOBALS_H__ +#define __EC_MASTER_GLOBALS_H__ + +#include "../globals.h" +#include "../include/ecrt.h" + +/***************************************************************************** + * EtherCAT master + ****************************************************************************/ + +/** Datagram timeout in microseconds. */ +#define EC_IO_TIMEOUT 500 + +/** Time to send a byte in nanoseconds. + * + * t_ns = 1 / (100 MBit/s / 8 bit/byte) = 80 ns/byte + */ +#define EC_BYTE_TRANSMISSION_TIME_NS 80 + +/** Number of state machine retries on datagram timeout. */ +#define EC_FSM_RETRIES 3 + +/** Seconds to wait before fetching SDO dictionary + after slave entered PREOP state. */ +#define EC_WAIT_SDO_DICT 3 + +/** Minimum size of a buffer used with ec_state_string(). */ +#define EC_STATE_STRING_SIZE 32 + +/** Maximum SII size in words, to avoid infinite reading. */ +#define EC_MAX_SII_SIZE 4096 + +/** Number of statistic rate intervals to maintain. */ +#define EC_RATE_COUNT 3 + +/***************************************************************************** + * EtherCAT protocol + ****************************************************************************/ + +/** Size of an EtherCAT frame header. */ +#define EC_FRAME_HEADER_SIZE 2 + +/** Size of an EtherCAT datagram header. */ +#define EC_DATAGRAM_HEADER_SIZE 10 + +/** Size of an EtherCAT datagram footer. */ +#define EC_DATAGRAM_FOOTER_SIZE 2 + +/** Size of the EtherCAT address field. */ +#define EC_ADDR_LEN 4 + +/** Resulting maximum data size of a single datagram in a frame. */ +#define EC_MAX_DATA_SIZE (ETH_DATA_LEN - EC_FRAME_HEADER_SIZE \ + - EC_DATAGRAM_HEADER_SIZE - EC_DATAGRAM_FOOTER_SIZE) + +/** Mailbox header size. */ +#define EC_MBOX_HEADER_SIZE 6 + +/** Word offset of first SII category. */ +#define EC_FIRST_SII_CATEGORY_OFFSET 0x40 + +/** Size of a sync manager configuration page. */ +#define EC_SYNC_PAGE_SIZE 8 + +/** Maximum number of FMMUs per slave. */ +#define EC_MAX_FMMUS 16 + +/** Size of an FMMU configuration page. */ +#define EC_FMMU_PAGE_SIZE 16 + +/** Number of DC sync signals. */ +#define EC_SYNC_SIGNAL_COUNT 2 + +/** Size of the datagram description string. + * + * This is also used as the maximum lenth of EoE device names. + **/ +#define EC_DATAGRAM_NAME_SIZE 20 + +/** Maximum hostname size. + * + * Used inside the EoE set IP parameter request. + */ +#define EC_MAX_HOSTNAME_SIZE 32 + +/** Slave state mask. + * + * Apply this mask to a slave state byte to get the slave state without + * the error flag. + */ +#define EC_SLAVE_STATE_MASK 0x0F + +/** State of an EtherCAT slave. + */ +typedef enum { + EC_SLAVE_STATE_UNKNOWN = 0x00, + /**< unknown state */ + EC_SLAVE_STATE_INIT = 0x01, + /**< INIT state (no mailbox communication, no IO) */ + EC_SLAVE_STATE_PREOP = 0x02, + /**< PREOP state (mailbox communication, no IO) */ + EC_SLAVE_STATE_BOOT = 0x03, + /**< Bootstrap state (mailbox communication, firmware update) */ + EC_SLAVE_STATE_SAFEOP = 0x04, + /**< SAFEOP (mailbox communication and input update) */ + EC_SLAVE_STATE_OP = 0x08, + /**< OP (mailbox communication and input/output update) */ + EC_SLAVE_STATE_ACK_ERR = 0x10 + /**< Acknowledge/Error bit (no actual state) */ +} ec_slave_state_t; + +/** Supported mailbox protocols. + * + * Not to mix up with the mailbox type field in the mailbox header defined in + * master/mailbox.h. + */ +enum { + EC_MBOX_AOE = 0x01, /**< ADS over EtherCAT */ + EC_MBOX_EOE = 0x02, /**< Ethernet over EtherCAT */ + EC_MBOX_COE = 0x04, /**< CANopen over EtherCAT */ + EC_MBOX_FOE = 0x08, /**< File-Access over EtherCAT */ + EC_MBOX_SOE = 0x10, /**< Servo-Profile over EtherCAT */ + EC_MBOX_VOE = 0x20 /**< Vendor specific */ +}; + +/** Slave information interface CANopen over EtherCAT details flags. + */ +typedef struct { + uint8_t enable_sdo : 1; /**< Enable SDO access. */ + uint8_t enable_sdo_info : 1; /**< SDO information service available. */ + uint8_t enable_pdo_assign : 1; /**< PDO mapping configurable. */ + uint8_t enable_pdo_configuration : 1; /**< PDO configuration possible. */ + uint8_t enable_upload_at_startup : 1; /**< ?. */ + uint8_t enable_sdo_complete_access : 1; /**< Complete access possible. */ +} ec_sii_coe_details_t; + +/** Slave information interface general flags. + */ +typedef struct { + uint8_t enable_safeop : 1; /**< ?. */ + uint8_t enable_not_lrw : 1; /**< Slave does not support LRW. */ +} ec_sii_general_flags_t; + +/** EtherCAT slave distributed clocks range. + */ +typedef enum { + EC_DC_32, /**< 32 bit. */ + EC_DC_64 /*< 64 bit for system time, system time offset and + port 0 receive time. */ +} ec_slave_dc_range_t; + +/** EtherCAT slave sync signal configuration. + */ +typedef struct { + uint32_t cycle_time; /**< Cycle time [ns]. */ + int32_t shift_time; /**< Shift time [ns]. */ +} ec_sync_signal_t; + +/** Access states for SDO entries. + * + * The access rights are managed per AL state. + */ +enum { + EC_SDO_ENTRY_ACCESS_PREOP, /**< Access rights in PREOP. */ + EC_SDO_ENTRY_ACCESS_SAFEOP, /**< Access rights in SAFEOP. */ + EC_SDO_ENTRY_ACCESS_OP, /**< Access rights in OP. */ + EC_SDO_ENTRY_ACCESS_COUNT /**< Number of states. */ +}; + +/** Master devices. + */ +typedef enum { + EC_DEVICE_MAIN, /**< Main device. */ + EC_DEVICE_BACKUP /**< Backup device */ +} ec_device_index_t; + +extern const char *ec_device_names[2]; // only main and backup! + +/****************************************************************************/ + +/** Convenience macro for printing EtherCAT-specific information to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_INFO(fmt, args...) \ + printk(KERN_INFO "EtherCAT: " fmt, ##args) + +/** Convenience macro for printing EtherCAT-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT ERROR: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_ERR(fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR: " fmt, ##args) + +/** Convenience macro for printing EtherCAT-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT WARNING: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_WARN(fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING: " fmt, ##args) + +/** Convenience macro for printing EtherCAT debug messages to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT DEBUG: ". + * + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_DBG(fmt, args...) \ + printk(KERN_DEBUG "EtherCAT DEBUG: " fmt, ##args) + +/****************************************************************************/ + +/** Absolute value. + */ +#define EC_ABS(X) ((X) >= 0 ? (X) : -(X)) + +/****************************************************************************/ + +extern char *ec_master_version_str; + +/****************************************************************************/ + +unsigned int ec_master_count(void); +void ec_print_data(const uint8_t *, size_t); +void ec_print_data_diff(const uint8_t *, const uint8_t *, size_t); +size_t ec_state_string(uint8_t, char *, uint8_t); +ssize_t ec_mac_print(const uint8_t *, char *); +int ec_mac_is_zero(const uint8_t *); + +ec_master_t *ecrt_request_master_err(unsigned int); + +/****************************************************************************/ + +/** Code/Message pair. + * + * Some EtherCAT datagrams support reading a status code to display a certain + * message. This type allows to map a code to a message string. + */ +typedef struct { + uint32_t code; /**< Code. */ + const char *message; /**< Message belonging to \a code. */ +} ec_code_msg_t; + +/****************************************************************************/ + +/** Generic request state. + * + * \attention If ever changing this, please be sure to adjust the \a + * state_table in master/sdo_request.c. + */ +typedef enum { + EC_INT_REQUEST_INIT, + EC_INT_REQUEST_QUEUED, + EC_INT_REQUEST_BUSY, + EC_INT_REQUEST_SUCCESS, + EC_INT_REQUEST_FAILURE +} ec_internal_request_state_t; + +/****************************************************************************/ + +extern const ec_request_state_t ec_request_state_translation_table[]; + +/****************************************************************************/ + +/** Origin type. + */ +typedef enum { + EC_ORIG_INTERNAL, /**< Internal. */ + EC_ORIG_EXTERNAL /**< External. */ +} ec_origin_t; + +/****************************************************************************/ + +typedef struct ec_slave ec_slave_t; /**< \see ec_slave. */ + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/ioctl.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/ioctl.c @@ -0,0 +1,5591 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + \file + EtherCAT master character device. +*/ + +/****************************************************************************/ + +#include +#include + +#include "master.h" +#include "slave_config.h" +#include "voe_handler.h" +#include "ethernet.h" +#include "ioctl.h" + +/** Set to 1 to enable ioctl() latency tracing. + * + * Requires CPU timestamp counter! + */ +#define DEBUG_LATENCY 0 + +/** Optional compiler attributes fo ioctl() functions. + */ +#if 0 +#define ATTRIBUTES __attribute__ ((__noinline__)) +#else +#define ATTRIBUTES +#endif + +#ifdef EC_IOCTL_RTDM +# include "rtdm_details.h" +/* RTDM does not support locking yet, + * therefore no send/receive callbacks are set too. */ +# define ec_ioctl_lock(lock) do {} while(0) +# define ec_ioctl_unlock(lock) do {} while(0) +# define ec_ioctl_lock_interruptible(lock) (0) +# define ec_copy_to_user(to, from, n, ctx) \ + rtdm_safe_copy_to_user(ec_ioctl_to_rtdm(ctx), to, from, n) +# define ec_copy_from_user(to, from, n, ctx) \ + rtdm_safe_copy_from_user(ec_ioctl_to_rtdm(ctx), to, from, n) +#else +# define ec_ioctl_lock(lock) rt_mutex_lock(lock) +# define ec_ioctl_unlock(lock) rt_mutex_unlock(lock) +# if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) || \ + (defined(CONFIG_PREEMPT_RT_FULL) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) +# define ec_ioctl_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock) +# else +# define ec_ioctl_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock, 0) +# endif +# define ec_copy_to_user(to, from, n, ctx) copy_to_user(to, from, n) +# define ec_copy_from_user(to, from, n, ctx) copy_from_user(to, from, n) +#endif // EC_IOCTL_RTDM + +/****************************************************************************/ + +/** Copies a string to an ioctl structure. + */ +static void ec_ioctl_strcpy( + char *target, /**< Target. */ + const char *source /**< Source. */ + ) +{ + if (source) { + strncpy(target, source, EC_IOCTL_STRING_SIZE); + target[EC_IOCTL_STRING_SIZE - 1] = 0; + } else { + target[0] = 0; + } +} + +/****************************************************************************/ + +/** Get module information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_module( + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_module_t data; + + data.ioctl_version_magic = EC_IOCTL_VERSION_MAGIC; + data.master_count = ec_master_count(); + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get master information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_master_t io; + unsigned int dev_idx, j; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + io.slave_count = master->slave_count; + io.scan_index = master->scan_index; + io.config_count = ec_master_config_count(master); + io.domain_count = ec_master_domain_count(master); +#ifdef EC_EOE + io.eoe_handler_count = ec_master_eoe_handler_count(master); +#else + io.eoe_handler_count = 0; +#endif + io.phase = (uint8_t) master->phase; + io.active = (uint8_t) master->active; + io.scan_busy = master->scan_busy; + + up(&master->master_sem); + + if (down_interruptible(&master->device_sem)) { + return -EINTR; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + ec_device_t *device = &master->devices[dev_idx]; + + if (device->dev) { + memcpy(io.devices[dev_idx].address, device->dev->dev_addr, + ETH_ALEN); + } else { + memcpy(io.devices[dev_idx].address, master->macs[dev_idx], + ETH_ALEN); + } + io.devices[dev_idx].attached = device->dev ? 1 : 0; + io.devices[dev_idx].link_state = device->link_state ? 1 : 0; + io.devices[dev_idx].tx_count = device->tx_count; + io.devices[dev_idx].rx_count = device->rx_count; + io.devices[dev_idx].tx_bytes = device->tx_bytes; + io.devices[dev_idx].rx_bytes = device->rx_bytes; + io.devices[dev_idx].tx_errors = device->tx_errors; + for (j = 0; j < EC_RATE_COUNT; j++) { + io.devices[dev_idx].tx_frame_rates[j] = + device->tx_frame_rates[j]; + io.devices[dev_idx].rx_frame_rates[j] = + device->rx_frame_rates[j]; + io.devices[dev_idx].tx_byte_rates[j] = + device->tx_byte_rates[j]; + io.devices[dev_idx].rx_byte_rates[j] = + device->rx_byte_rates[j]; + } + } + io.num_devices = ec_master_num_devices(master); + + io.tx_count = master->device_stats.tx_count; + io.rx_count = master->device_stats.rx_count; + io.tx_bytes = master->device_stats.tx_bytes; + io.rx_bytes = master->device_stats.rx_bytes; + for (j = 0; j < EC_RATE_COUNT; j++) { + io.tx_frame_rates[j] = + master->device_stats.tx_frame_rates[j]; + io.rx_frame_rates[j] = + master->device_stats.rx_frame_rates[j]; + io.tx_byte_rates[j] = + master->device_stats.tx_byte_rates[j]; + io.rx_byte_rates[j] = + master->device_stats.rx_byte_rates[j]; + io.loss_rates[j] = + master->device_stats.loss_rates[j]; + } + + up(&master->device_sem); + + io.app_time = master->app_time; + io.dc_ref_time = master->dc_ref_time; + io.ref_clock = + master->dc_ref_clock ? master->dc_ref_clock->ring_position : 0xffff; + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Get slave information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_t data; + const ec_slave_t *slave; + int i; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", data.position); + return -EINVAL; + } + + data.device_index = slave->device_index; + data.vendor_id = slave->sii.vendor_id; + data.product_code = slave->sii.product_code; + data.revision_number = slave->sii.revision_number; + data.serial_number = slave->sii.serial_number; + data.alias = slave->effective_alias; + data.boot_rx_mailbox_offset = slave->sii.boot_rx_mailbox_offset; + data.boot_rx_mailbox_size = slave->sii.boot_rx_mailbox_size; + data.boot_tx_mailbox_offset = slave->sii.boot_tx_mailbox_offset; + data.boot_tx_mailbox_size = slave->sii.boot_tx_mailbox_size; + data.std_rx_mailbox_offset = slave->sii.std_rx_mailbox_offset; + data.std_rx_mailbox_size = slave->sii.std_rx_mailbox_size; + data.std_tx_mailbox_offset = slave->sii.std_tx_mailbox_offset; + data.std_tx_mailbox_size = slave->sii.std_tx_mailbox_size; + data.mailbox_protocols = slave->sii.mailbox_protocols; + data.has_general_category = slave->sii.has_general; + data.coe_details = slave->sii.coe_details; + data.general_flags = slave->sii.general_flags; + data.current_on_ebus = slave->sii.current_on_ebus; + for (i = 0; i < EC_MAX_PORTS; i++) { + data.ports[i].desc = slave->ports[i].desc; + data.ports[i].link.link_up = slave->ports[i].link.link_up; + data.ports[i].link.loop_closed = slave->ports[i].link.loop_closed; + data.ports[i].link.signal_detected = + slave->ports[i].link.signal_detected; + data.ports[i].receive_time = slave->ports[i].receive_time; + if (slave->ports[i].next_slave) { + data.ports[i].next_slave = + slave->ports[i].next_slave->ring_position; + } else { + data.ports[i].next_slave = 0xffff; + } + data.ports[i].delay_to_next_dc = slave->ports[i].delay_to_next_dc; + } + data.fmmu_bit = slave->base_fmmu_bit_operation; + data.dc_supported = slave->base_dc_supported; + data.dc_range = slave->base_dc_range; + data.has_dc_system_time = slave->has_dc_system_time; + data.transmission_delay = slave->transmission_delay; + data.al_state = slave->current_state; + data.error_flag = slave->error_flag; + + data.sync_count = slave->sii.sync_count; + data.sdo_count = ec_slave_sdo_count(slave); + data.sii_nwords = slave->sii_nwords; + ec_ioctl_strcpy(data.group, slave->sii.group); + ec_ioctl_strcpy(data.image, slave->sii.image); + ec_ioctl_strcpy(data.order, slave->sii.order); + ec_ioctl_strcpy(data.name, slave->sii.name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave sync manager information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sync( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_sync_t data; + const ec_slave_t *slave; + const ec_sync_t *sync; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sync_index >= slave->sii.sync_count) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not exist!\n", + data.sync_index); + return -EINVAL; + } + + sync = &slave->sii.syncs[data.sync_index]; + + data.physical_start_address = sync->physical_start_address; + data.default_size = sync->default_length; + data.control_register = sync->control_register; + data.enable = sync->enable; + data.pdo_count = ec_pdo_list_count(&sync->pdos); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave sync manager PDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sync_pdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_sync_pdo_t data; + const ec_slave_t *slave; + const ec_sync_t *sync; + const ec_pdo_t *pdo; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sync_index >= slave->sii.sync_count) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not exist!\n", + data.sync_index); + return -EINVAL; + } + + sync = &slave->sii.syncs[data.sync_index]; + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sync->pdos, data.pdo_pos))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not contain a PDO with " + "position %u!\n", data.sync_index, data.pdo_pos); + return -EINVAL; + } + + data.index = pdo->index; + data.entry_count = ec_pdo_entry_count(pdo); + ec_ioctl_strcpy(data.name, pdo->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave sync manager PDO entry information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sync_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_slave_sync_pdo_entry_t data; + const ec_slave_t *slave; + const ec_sync_t *sync; + const ec_pdo_t *pdo; + const ec_pdo_entry_t *entry; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sync_index >= slave->sii.sync_count) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not exist!\n", + data.sync_index); + return -EINVAL; + } + + sync = &slave->sii.syncs[data.sync_index]; + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sync->pdos, data.pdo_pos))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Sync manager %u does not contain a PDO with " + "position %u!\n", data.sync_index, data.pdo_pos); + return -EINVAL; + } + + if (!(entry = ec_pdo_find_entry_by_pos_const( + pdo, data.entry_pos))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "PDO 0x%04X does not contain an entry with " + "position %u!\n", data.pdo_pos, data.entry_pos); + return -EINVAL; + } + + data.index = entry->index; + data.subindex = entry->subindex; + data.bit_length = entry->bit_length; + ec_ioctl_strcpy(data.name, entry->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get domain information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_domain_t data; + const ec_domain_t *domain; + unsigned int dev_idx; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(domain = ec_master_find_domain_const(master, data.index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u does not exist!\n", data.index); + return -EINVAL; + } + + data.data_size = domain->data_size; + data.logical_base_address = domain->logical_base_address; + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(domain->master); dev_idx++) { + data.working_counter[dev_idx] = domain->working_counter[dev_idx]; + } + data.expected_working_counter = domain->expected_working_counter; + data.fmmu_count = ec_domain_fmmu_count(domain); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get domain FMMU information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_fmmu( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_domain_fmmu_t data; + const ec_domain_t *domain; + const ec_fmmu_config_t *fmmu; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(domain = ec_master_find_domain_const(master, data.domain_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u does not exist!\n", + data.domain_index); + return -EINVAL; + } + + if (!(fmmu = ec_domain_find_fmmu(domain, data.fmmu_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u has less than %u" + " fmmu configurations.\n", + data.domain_index, data.fmmu_index + 1); + return -EINVAL; + } + + data.slave_config_alias = fmmu->sc->alias; + data.slave_config_position = fmmu->sc->position; + data.sync_index = fmmu->sync_index; + data.dir = fmmu->dir; + data.logical_address = fmmu->logical_start_address; + data.data_size = fmmu->data_size; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get domain data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< Userspace address to store the results. */ + ) +{ + ec_ioctl_domain_data_t data; + const ec_domain_t *domain; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(domain = ec_master_find_domain_const(master, data.domain_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Domain %u does not exist!\n", + data.domain_index); + return -EINVAL; + } + + if (domain->data_size != data.data_size) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Data size mismatch %u/%zu!\n", + data.data_size, domain->data_size); + return -EFAULT; + } + + if (copy_to_user((void __user *) data.target, domain->data, + domain->data_size)) { + up(&master->master_sem); + return -EFAULT; + } + + up(&master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** Set master debug level. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master_debug( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + return ec_master_debug_level(master, (unsigned long) arg); +} + +/****************************************************************************/ + +/** Issue a bus scan. + * + * \return Always zero (success). + */ +static ATTRIBUTES int ec_ioctl_master_rescan( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + EC_MASTER_DBG(master, 1, "Got rescan command via ioctl()." + " Re-scanning on next possibility.\n"); + master->fsm.rescan_required = 1; + return 0; +} + +/****************************************************************************/ + +/** Set slave state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_state_t data; + ec_slave_t *slave; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + ec_slave_request_state(slave, data.al_state); + + up(&master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** Get slave SDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_t data; + const ec_slave_t *slave; + const ec_sdo_t *sdo; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (!(sdo = ec_slave_get_sdo_by_pos_const( + slave, data.sdo_position))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO %u does not exist!\n", data.sdo_position); + return -EINVAL; + } + + data.sdo_index = sdo->index; + data.max_subindex = sdo->max_subindex; + ec_ioctl_strcpy(data.name, sdo->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave SDO entry information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_entry_t data; + const ec_slave_t *slave; + const ec_sdo_t *sdo; + const ec_sdo_entry_t *entry; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (data.sdo_spec <= 0) { + if (!(sdo = ec_slave_get_sdo_by_pos_const( + slave, -data.sdo_spec))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO %u does not exist!\n", -data.sdo_spec); + return -EINVAL; + } + } else { + if (!(sdo = ec_slave_get_sdo_const( + slave, data.sdo_spec))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO 0x%04X does not exist!\n", + data.sdo_spec); + return -EINVAL; + } + } + + if (!(entry = ec_sdo_get_entry_const( + sdo, data.sdo_entry_subindex))) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "SDO entry 0x%04X:%02X does not exist!\n", + sdo->index, data.sdo_entry_subindex); + return -EINVAL; + } + + data.data_type = entry->data_type; + data.bit_length = entry->bit_length; + data.read_access[EC_SDO_ENTRY_ACCESS_PREOP] = + entry->read_access[EC_SDO_ENTRY_ACCESS_PREOP]; + data.read_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + entry->read_access[EC_SDO_ENTRY_ACCESS_SAFEOP]; + data.read_access[EC_SDO_ENTRY_ACCESS_OP] = + entry->read_access[EC_SDO_ENTRY_ACCESS_OP]; + data.write_access[EC_SDO_ENTRY_ACCESS_PREOP] = + entry->write_access[EC_SDO_ENTRY_ACCESS_PREOP]; + data.write_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = + entry->write_access[EC_SDO_ENTRY_ACCESS_SAFEOP]; + data.write_access[EC_SDO_ENTRY_ACCESS_OP] = + entry->write_access[EC_SDO_ENTRY_ACCESS_OP]; + ec_ioctl_strcpy(data.description, entry->description); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Upload SDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo_upload( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_upload_t data; + uint8_t *target; + int ret; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (!(target = kmalloc(data.target_size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes" + " for SDO upload.\n", data.target_size); + return -ENOMEM; + } + + ret = ecrt_master_sdo_upload(master, data.slave_position, + data.sdo_index, data.sdo_entry_subindex, target, + data.target_size, &data.data_size, &data.abort_code); + + if (!ret) { + if (copy_to_user((void __user *) data.target, + target, data.data_size)) { + kfree(target); + return -EFAULT; + } + } + + kfree(target); + + if (__copy_to_user((void __user *) arg, &data, sizeof(data))) { + return -EFAULT; + } + + return ret; +} + +/****************************************************************************/ + +/** Download SDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sdo_download( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sdo_download_t data; + uint8_t *sdo_data; + int retval; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (!(sdo_data = kmalloc(data.data_size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes" + " for SDO download.\n", data.data_size); + return -ENOMEM; + } + + if (copy_from_user(sdo_data, (void __user *) data.data, data.data_size)) { + kfree(sdo_data); + return -EFAULT; + } + + if (data.complete_access) { + retval = ecrt_master_sdo_download_complete(master, data.slave_position, + data.sdo_index, sdo_data, data.data_size, &data.abort_code); + } else { + retval = ecrt_master_sdo_download(master, data.slave_position, + data.sdo_index, data.sdo_entry_subindex, sdo_data, + data.data_size, &data.abort_code); + } + + kfree(sdo_data); + + if (__copy_to_user((void __user *) arg, &data, sizeof(data))) { + retval = -EFAULT; + } + + return retval; +} + +/****************************************************************************/ + +/** Read a slave's SII. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sii_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sii_t data; + const ec_slave_t *slave; + int retval; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(slave = ec_master_find_slave_const( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + return -EINVAL; + } + + if (!data.nwords + || data.offset + data.nwords > slave->sii_nwords) { + up(&master->master_sem); + EC_SLAVE_ERR(slave, "Invalid SII read offset/size %u/%u for slave SII" + " size %zu!\n", data.offset, data.nwords, slave->sii_nwords); + return -EINVAL; + } + + if (copy_to_user((void __user *) data.words, + slave->sii_words + data.offset, data.nwords * 2)) + retval = -EFAULT; + else + retval = 0; + + up(&master->master_sem); + return retval; +} + +/****************************************************************************/ + +/** Write a slave's SII. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_sii_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_sii_t data; + ec_slave_t *slave; + unsigned int byte_size; + uint16_t *words; + ec_sii_write_request_t request; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (!data.nwords) { + return 0; + } + + byte_size = sizeof(uint16_t) * data.nwords; + if (!(words = kmalloc(byte_size, GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate %u bytes" + " for SII contents.\n", byte_size); + return -ENOMEM; + } + + if (copy_from_user(words, + (void __user *) data.words, byte_size)) { + kfree(words); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(words); + return -EINTR; + } + + if (!(slave = ec_master_find_slave( + master, 0, data.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + data.slave_position); + kfree(words); + return -EINVAL; + } + + // init SII write request + INIT_LIST_HEAD(&request.list); + request.slave = slave; + request.words = words; + request.offset = data.offset; + request.nwords = data.nwords; + request.state = EC_INT_REQUEST_QUEUED; + + // schedule SII write request. + list_add_tail(&request.list, &master->sii_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + kfree(words); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + kfree(words); + + return request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} + +/****************************************************************************/ + +/** Read a slave's registers. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_reg_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_reg_t io; + ec_slave_t *slave; + ec_reg_request_t request; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (!io.size) { + return 0; + } + + // init register request + ret = ec_reg_request_init(&request, io.size); + if (ret) { + return ret; + } + + ret = ecrt_reg_request_read(&request, io.address, io.size); + if (ret) { + return ret; + } + + if (down_interruptible(&master->master_sem)) { + ec_reg_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave( + master, 0, io.slave_position))) { + up(&master->master_sem); + ec_reg_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + // schedule request. + list_add_tail(&request.list, &slave->reg_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_reg_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + if (request.state == EC_INT_REQUEST_SUCCESS) { + if (copy_to_user((void __user *) io.data, request.data, io.size)) { + return -EFAULT; + } + } + ec_reg_request_clear(&request); + + return request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} + +/****************************************************************************/ + +/** Write a slave's registers. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_reg_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_reg_t io; + ec_slave_t *slave; + ec_reg_request_t request; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (!io.size) { + return 0; + } + + // init register request + ret = ec_reg_request_init(&request, io.size); + if (ret) { + return ret; + } + + if (copy_from_user(request.data, (void __user *) io.data, io.size)) { + ec_reg_request_clear(&request); + return -EFAULT; + } + + ret = ecrt_reg_request_write(&request, io.address, io.size); + if (ret) { + return ret; + } + + if (down_interruptible(&master->master_sem)) { + ec_reg_request_clear(&request); + return -EINTR; + } + + if (io.emergency) { + request.ring_position = io.slave_position; + // schedule request. + list_add_tail(&request.list, &master->emerg_reg_requests); + } + else { + if (!(slave = ec_master_find_slave(master, 0, io.slave_position))) { + up(&master->master_sem); + ec_reg_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + // schedule request. + list_add_tail(&request.list, &slave->reg_requests); + } + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_reg_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + ec_reg_request_clear(&request); + + return request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} + +/****************************************************************************/ + +/** Get slave configuration information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_t data; + const ec_slave_config_t *sc; + uint8_t i; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config_const( + master, data.config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + data.config_index); + return -EINVAL; + } + + data.alias = sc->alias; + data.position = sc->position; + data.vendor_id = sc->vendor_id; + data.product_code = sc->product_code; + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) { + data.syncs[i].dir = sc->sync_configs[i].dir; + data.syncs[i].watchdog_mode = sc->sync_configs[i].watchdog_mode; + data.syncs[i].pdo_count = + ec_pdo_list_count(&sc->sync_configs[i].pdos); + } + data.watchdog_divider = sc->watchdog_divider; + data.watchdog_intervals = sc->watchdog_intervals; + data.sdo_count = ec_slave_config_sdo_count(sc); + data.idn_count = ec_slave_config_idn_count(sc); + data.flag_count = ec_slave_config_flag_count(sc); + data.slave_position = sc->slave ? sc->slave->ring_position : -1; + data.dc_assign_activate = sc->dc_assign_activate; + for (i = 0; i < EC_SYNC_SIGNAL_COUNT; i++) { + data.dc_sync[i] = sc->dc_sync[i]; + } + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration PDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_pdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_pdo_t data; + const ec_slave_config_t *sc; + const ec_pdo_t *pdo; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (data.sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_MASTER_ERR(master, "Invalid sync manager index %u!\n", + data.sync_index); + return -EINVAL; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config_const( + master, data.config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + data.config_index); + return -EINVAL; + } + + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sc->sync_configs[data.sync_index].pdos, + data.pdo_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid PDO position!\n"); + return -EINVAL; + } + + data.index = pdo->index; + data.entry_count = ec_pdo_entry_count(pdo); + ec_ioctl_strcpy(data.name, pdo->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration PDO entry information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_pdo_entry_t data; + const ec_slave_config_t *sc; + const ec_pdo_t *pdo; + const ec_pdo_entry_t *entry; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (data.sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_MASTER_ERR(master, "Invalid sync manager index %u!\n", + data.sync_index); + return -EINVAL; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config_const( + master, data.config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + data.config_index); + return -EINVAL; + } + + if (!(pdo = ec_pdo_list_find_pdo_by_pos_const( + &sc->sync_configs[data.sync_index].pdos, + data.pdo_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid PDO position!\n"); + return -EINVAL; + } + + if (!(entry = ec_pdo_find_entry_by_pos_const( + pdo, data.entry_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Entry not found!\n"); + return -EINVAL; + } + + data.index = entry->index; + data.subindex = entry->subindex; + data.bit_length = entry->bit_length; + ec_ioctl_strcpy(data.name, entry->name); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration SDO information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_sdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_sdo_t *ioctl; + const ec_slave_config_t *sc; + const ec_sdo_request_t *req; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const( + master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + if (!(req = ec_slave_config_get_sdo_by_pos_const( + sc, ioctl->sdo_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid SDO position!\n"); + kfree(ioctl); + return -EINVAL; + } + + ioctl->index = req->index; + ioctl->subindex = req->subindex; + ioctl->size = req->data_size; + memcpy(ioctl->data, req->data, + min((u32) ioctl->size, (u32) EC_MAX_SDO_DATA_SIZE)); + ioctl->complete_access = req->complete_access; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration IDN information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_idn( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_idn_t *ioctl; + const ec_slave_config_t *sc; + const ec_soe_request_t *req; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const( + master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + if (!(req = ec_slave_config_get_idn_by_pos_const( + sc, ioctl->idn_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid IDN position!\n"); + kfree(ioctl); + return -EINVAL; + } + + ioctl->drive_no = req->drive_no; + ioctl->idn = req->idn; + ioctl->state = req->al_state; + ioctl->size = req->data_size; + memcpy(ioctl->data, req->data, + min((u32) ioctl->size, (u32) EC_MAX_IDN_DATA_SIZE)); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +/****************************************************************************/ + +/** Get slave configuration feature flag information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_flag( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_config_flag_t *ioctl; + const ec_slave_config_t *sc; + const ec_flag_t *flag; + size_t size; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const( + master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + if (!(flag = ec_slave_config_get_flag_by_pos_const( + sc, ioctl->flag_pos))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Invalid flag position!\n"); + kfree(ioctl); + return -EINVAL; + } + + size = min((u32) strlen(flag->key), (u32) EC_MAX_FLAG_KEY_SIZE - 1); + memcpy(ioctl->key, flag->key, size); + ioctl->key[size] = 0x00; + ioctl->value = flag->value; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Get configured EoE IP parameters for a given slave configuration. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_config_ip( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_eoe_ip_t *ioctl; + const ec_slave_config_t *sc; + const ec_eoe_request_t *req; + + if (!(ioctl = kmalloc(sizeof(*ioctl), GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(ioctl, (void __user *) arg, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(ioctl); + return -EINTR; + } + + if (!(sc = ec_master_get_config_const(master, ioctl->config_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave config %u does not exist!\n", + ioctl->config_index); + kfree(ioctl); + return -EINVAL; + } + + req = &sc->eoe_ip_param_request; + + ioctl->mac_address_included = req->mac_address_included; + ioctl->ip_address_included = req->ip_address_included; + ioctl->subnet_mask_included = req->subnet_mask_included; + ioctl->gateway_included = req->gateway_included; + ioctl->dns_included = req->dns_included; + ioctl->name_included = req->name_included; + + memcpy(ioctl->mac_address, req->mac_address, EC_ETH_ALEN); + ioctl->ip_address = req->ip_address; + ioctl->subnet_mask = req->subnet_mask; + ioctl->gateway = req->gateway; + ioctl->dns = req->dns; + strncpy(ioctl->name, req->name, EC_MAX_HOSTNAME_SIZE); + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, ioctl, sizeof(*ioctl))) { + kfree(ioctl); + return -EFAULT; + } + + kfree(ioctl); + return 0; +} + +#endif + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Get EoE handler information. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_eoe_handler( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_eoe_handler_t data; + const ec_eoe_t *eoe; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(eoe = ec_master_get_eoe_handler_const(master, data.eoe_index))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "EoE handler %u does not exist!\n", + data.eoe_index); + return -EINVAL; + } + + if (eoe->slave) { + data.slave_position = eoe->slave->ring_position; + } else { + data.slave_position = 0xffff; + } + snprintf(data.name, EC_DATAGRAM_NAME_SIZE, eoe->dev->name); + data.open = eoe->opened; + data.rx_bytes = eoe->stats.tx_bytes; + data.rx_rate = eoe->tx_rate; + data.tx_bytes = eoe->stats.rx_bytes; + data.tx_rate = eoe->tx_rate; + data.tx_queued_frames = eoe->tx_queued_frames; + data.tx_queue_size = eoe->tx_queue_size; + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +#endif + +/****************************************************************************/ + +#ifdef EC_EOE +/** Request EoE IP parameter setting. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_eoe_ip_param( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_eoe_ip_t io; + ec_eoe_request_t req; + ec_slave_t *slave; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + // init EoE request + ec_eoe_request_init(&req); + + req.mac_address_included = io.mac_address_included; + req.ip_address_included = io.ip_address_included; + req.subnet_mask_included = io.subnet_mask_included; + req.gateway_included = io.gateway_included; + req.dns_included = io.dns_included; + req.name_included = io.name_included; + + memcpy(req.mac_address, io.mac_address, EC_ETH_ALEN); + req.ip_address = io.ip_address; + req.subnet_mask = io.subnet_mask; + req.gateway = io.gateway; + req.dns = io.dns; + memcpy(req.name, io.name, EC_MAX_HOSTNAME_SIZE); + + req.state = EC_INT_REQUEST_QUEUED; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(slave = ec_master_find_slave( + master, 0, io.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + EC_MASTER_DBG(master, 1, "Scheduling EoE request.\n"); + + // schedule request. + list_add_tail(&req.list, &slave->eoe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + req.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (req.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&req.list); + up(&master->master_sem); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, req.state != EC_INT_REQUEST_BUSY); + + io.result = req.result; + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) { + return -EFAULT; + } + + return req.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; +} +#endif + +/*****************************************************************************/ + +/** Request the master from userspace. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_master_t *m; + int ret = 0; + + m = ecrt_request_master_err(master->index); + if (IS_ERR(m)) { + ret = PTR_ERR(m); + } else { + ctx->requested = 1; + } + + return ret; +} + +/****************************************************************************/ + +/** Create a domain. + * + * \return Domain index on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_create_domain( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_domain_t *domain; + + if (unlikely(!ctx->requested)) + return -EPERM; + + domain = ecrt_master_create_domain_err(master); + if (IS_ERR(domain)) + return PTR_ERR(domain); + + return domain->index; +} + +/****************************************************************************/ + +/** Create a slave configuration. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_create_slave_config( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc, *entry; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + sc = ecrt_master_slave_config_err(master, data.alias, data.position, + data.vendor_id, data.product_code); + if (IS_ERR(sc)) + return PTR_ERR(sc); + + data.config_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + list_for_each_entry(entry, &master->configs, list) { + if (entry == sc) + break; + data.config_index++; + } + + up(&master->master_sem); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Select the DC reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_select_ref_clock( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + unsigned long config_index = (unsigned long) arg; + ec_slave_config_t *sc = NULL; + int ret = 0; + + if (unlikely(!ctx->requested)) { + ret = -EPERM; + goto out_return; + } + + if (down_interruptible(&master->master_sem)) { + ret = -EINTR; + goto out_return; + } + + if (config_index != 0xFFFFFFFF) { + if (!(sc = ec_master_get_config(master, config_index))) { + ret = -ENOENT; + goto out_up; + } + } + + ecrt_master_select_reference_clock(master, sc); + +out_up: + up(&master->master_sem); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Activates the master. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_activate( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_master_activate_t io; + ec_domain_t *domain; + off_t offset; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + io.process_data = NULL; + + /* Get the sum of the domains' process data sizes. */ + + ctx->process_data_size = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + list_for_each_entry(domain, &master->domains, list) { + ctx->process_data_size += ecrt_domain_size(domain); + } + + up(&master->master_sem); + + if (ctx->process_data_size) { + ctx->process_data = vmalloc(ctx->process_data_size); + if (!ctx->process_data) { + ctx->process_data_size = 0; + return -ENOMEM; + } + + /* Set the memory as external process data memory for the + * domains. + */ + offset = 0; + list_for_each_entry(domain, &master->domains, list) { + ecrt_domain_external_memory(domain, + ctx->process_data + offset); + offset += ecrt_domain_size(domain); + } + +#if defined(EC_IOCTL_RTDM) && !defined(EC_RTDM_XENOMAI_V3) + /* RTDM uses a different approach for memory-mapping, which has to be + * initiated by the kernel. + */ + ret = ec_rtdm_mmap(ctx, &io.process_data); + if (ret < 0) { + EC_MASTER_ERR(master, "Failed to map process data" + " memory to user space (code %i).\n", ret); + return ret; + } +#endif + } + + io.process_data_size = ctx->process_data_size; + +#ifndef EC_IOCTL_RTDM + /* RTDM does not support locking yet. */ + ecrt_master_callbacks(master, ec_master_internal_send_cb, + ec_master_internal_receive_cb, master); +#endif + + ret = ecrt_master_activate(master); + if (ret < 0) + return ret; + + if (copy_to_user((void __user *) arg, &io, + sizeof(ec_ioctl_master_activate_t))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Deactivates the master. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_deactivate( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + if (unlikely(!ctx->requested)) + return -EPERM; + + return ecrt_master_deactivate(master); +} + +/****************************************************************************/ + +/** Set max. number of databytes in a cycle + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_set_send_interval( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + size_t send_interval; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&send_interval, (void __user *) arg, + sizeof(send_interval))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + ec_master_set_send_interval(master, send_interval); + + up(&master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** Send frames. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_send( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_send(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Receive frames. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_receive( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_receive(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Get the master state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_master_state_t data; + int ret; + + ret = ecrt_master_state(master, &data); + if (ret) + return ret; + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get the link state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_master_link_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_link_state_t ioctl; + ec_master_link_state_t state; + int ret; + + if (ec_copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl), ctx)) { + return -EFAULT; + } + + ret = ecrt_master_link_state(master, ioctl.dev_idx, &state); + if (ret < 0) { + return ret; + } + + if (ec_copy_to_user((void __user *) ioctl.state, + &state, sizeof(state), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Set the master DC application time. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_app_time( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + uint64_t time; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&time, (void __user *) arg, sizeof(time), ctx)) { + return -EFAULT; + } + + return ecrt_master_application_time(master, time); +} + +/****************************************************************************/ + +/** Sync the reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_ref( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_reference_clock(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Sync the reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_ref_to( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + uint64_t time; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&time, (void __user *) arg, sizeof(time), ctx)) { + return -EFAULT; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_reference_clock_to(master, time); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Sync the slave clocks. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_slaves( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_slave_clocks(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Get the system time of the reference clock. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_ref_clock_time( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + uint32_t time; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + ret = ecrt_master_reference_clock_time(master, &time); + if (ret) { + return ret; + } + + if (ec_copy_to_user((void __user *) arg, &time, sizeof(time), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Queue the sync monitoring datagram. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_mon_queue( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_master_sync_monitor_queue(master); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Processes the sync monitoring datagram. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sync_mon_process( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + uint32_t time_diff; + + if (unlikely(!ctx->requested)) + return -EPERM; + + time_diff = ecrt_master_sync_monitor_process(master); + + if (ec_copy_to_user((void __user *) arg, &time_diff, + sizeof(time_diff), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Reset configuration. + * + * \return Always zero (success). + */ +static ATTRIBUTES int ec_ioctl_reset( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ +#ifdef EC_IOCTL_RTDM + /* Xenomai/LXRT is like NMI context, so we do a two-stage schedule. */ + irq_work_queue(&master->sc_reset_work_kicker); +#else + schedule_work(&master->sc_reset_work); +#endif + return 0; +} + +/****************************************************************************/ + +/** Configure a sync manager. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_sync( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc; + unsigned int i; + int ret = 0; + + if (unlikely(!ctx->requested)) { + ret = -EPERM; + goto out_return; + } + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + ret = -EFAULT; + goto out_return; + } + + if (down_interruptible(&master->master_sem)) { + ret = -EINTR; + goto out_return; + } + + if (!(sc = ec_master_get_config(master, data.config_index))) { + ret = -ENOENT; + goto out_up; + } + + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) { + if (data.syncs[i].config_this) { + ret = ecrt_slave_config_sync_manager(sc, i, data.syncs[i].dir, + data.syncs[i].watchdog_mode); + if (ret) { + goto out_up; + } + } + } + +out_up: + up(&master->master_sem); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Configure a slave's watchdogs. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_watchdog( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc; + int ret = 0; + + if (unlikely(!ctx->requested)) { + ret = -EPERM; + goto out_return; + } + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + ret = -EFAULT; + goto out_return; + } + + if (down_interruptible(&master->master_sem)) { + ret = -EINTR; + goto out_return; + } + + if (!(sc = ec_master_get_config(master, data.config_index))) { + ret = -ENOENT; + goto out_up; + } + + ret = ecrt_slave_config_watchdog(sc, + data.watchdog_divider, data.watchdog_intervals); + +out_up: + up(&master->master_sem); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Add a PDO to the assignment. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_add_pdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_pdo_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_assign_add(sc, data.sync_index, data.index); +} + +/****************************************************************************/ + +/** Clears the PDO assignment. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_clear_pdos( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_pdo_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_assign_clear(sc, data.sync_index); +} + +/****************************************************************************/ + +/** Add an entry to a PDO's mapping. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_add_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_add_pdo_entry_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_mapping_add(sc, data.pdo_index, + data.entry_index, data.entry_subindex, data.entry_bit_length); +} + +/****************************************************************************/ + +/** Clears the mapping of a PDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_clear_entries( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_pdo_t data; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + return ecrt_slave_config_pdo_mapping_clear(sc, data.index); +} + +/****************************************************************************/ + +/** Registers a PDO entry. + * + * \return Process data offset on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_reg_pdo_entry( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_pdo_entry_t data; + ec_slave_config_t *sc; + ec_domain_t *domain; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + if (!(domain = ec_master_find_domain(master, data.domain_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc or domain could be invalidated */ + + ret = ecrt_slave_config_reg_pdo_entry(sc, data.entry_index, + data.entry_subindex, domain, &data.bit_position); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return ret; +} + +/****************************************************************************/ + +/** Registers a PDO entry by its position. + * + * \return Process data offset on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_reg_pdo_pos( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_pdo_pos_t io; + ec_slave_config_t *sc; + ec_domain_t *domain; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, io.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + if (!(domain = ec_master_find_domain(master, io.domain_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc or domain could be invalidated */ + + ret = ecrt_slave_config_reg_pdo_entry_pos(sc, io.sync_index, + io.pdo_pos, io.entry_pos, domain, &io.bit_position); + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) + return -EFAULT; + + return ret; +} + +/****************************************************************************/ + +/** Sets the DC AssignActivate word and the sync signal times. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_dc( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_config_t data; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + ret = ecrt_slave_config_dc(sc, data.dc_assign_activate, + data.dc_sync[0].cycle_time, + data.dc_sync[0].shift_time, + data.dc_sync[1].cycle_time, + data.dc_sync[1].shift_time); + + up(&master->master_sem); + + return ret; +} + +/****************************************************************************/ + +/** Configures an SDO. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_sdo( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_sdo_t data; + ec_slave_config_t *sc; + uint8_t *sdo_data = NULL; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) + return -EFAULT; + + if (!data.size) + return -EINVAL; + + if (!(sdo_data = kmalloc(data.size, GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(sdo_data, (void __user *) data.data, data.size)) { + kfree(sdo_data); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(sdo_data); + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, data.config_index))) { + up(&master->master_sem); + kfree(sdo_data); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + if (data.complete_access) { + ret = ecrt_slave_config_complete_sdo(sc, + data.index, sdo_data, data.size); + } else { + ret = ecrt_slave_config_sdo(sc, data.index, data.subindex, sdo_data, + data.size); + } + kfree(sdo_data); + return ret; +} + +/****************************************************************************/ + +/** Set the emergency ring buffer size. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_size( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) + return -EFAULT; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, io.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + ret = ecrt_slave_config_emerg_size(sc, io.size); + + up(&master->master_sem); + + return ret; +} + +/****************************************************************************/ + +/** Get an emergency message from the ring. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_pop( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + u8 msg[EC_COE_EMERGENCY_MSG_SIZE]; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because configuration will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + ret = ecrt_slave_config_emerg_pop(sc, msg); + if (ret < 0) { + return ret; + } + + if (ec_copy_to_user((void __user *) io.target, msg, sizeof(msg), ctx)) { + return -EFAULT; + } + + return ret; +} + +/****************************************************************************/ + +/** Clear the emergency ring. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_clear( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because configuration will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + return ecrt_slave_config_emerg_clear(sc); +} + +/****************************************************************************/ + +/** Get the number of emergency overruns. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_emerg_overruns( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_emerg_t io; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because configuration will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + ret = ecrt_slave_config_emerg_overruns(sc); + if (ret < 0) { + return ret; + } + + io.overruns = ret; + + if (ec_copy_to_user((void __user *) arg, &io, sizeof(io), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Create an SDO request. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_sdo_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + data.request_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + sc = ec_master_get_config(master, data.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(req, &sc->sdo_requests, list) { + data.request_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + req = ecrt_slave_config_create_sdo_request_err(sc, data.sdo_index, + data.sdo_subindex, data.size); + if (IS_ERR(req)) + return PTR_ERR(req); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Create an SoE request. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_soe_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + data.request_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + sc = ec_master_get_config(master, data.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(req, &sc->soe_requests, list) { + data.request_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + req = ecrt_slave_config_create_soe_request_err(sc, data.drive_no, + data.idn, data.size); + if (IS_ERR(req)) { + return PTR_ERR(req); + } + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Create a register request. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_reg_request( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + io.request_index = 0; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + sc = ec_master_get_config(master, io.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(reg, &sc->reg_requests, list) { + io.request_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + reg = ecrt_slave_config_create_reg_request_err(sc, io.mem_size); + if (IS_ERR(reg)) { + return PTR_ERR(reg); + } + + if (copy_to_user((void __user *) arg, &io, sizeof(io))) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Create a VoE handler. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_create_voe_handler( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&data, (void __user *) arg, sizeof(data))) { + return -EFAULT; + } + + data.voe_index = 0; + + if (down_interruptible(&master->master_sem)) + return -EINTR; + + sc = ec_master_get_config(master, data.config_index); + if (!sc) { + up(&master->master_sem); + return -ENOENT; + } + + list_for_each_entry(voe, &sc->voe_handlers, list) { + data.voe_index++; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + voe = ecrt_slave_config_create_voe_handler_err(sc, data.size); + if (IS_ERR(voe)) + return PTR_ERR(voe); + + if (copy_to_user((void __user *) arg, &data, sizeof(data))) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Get the slave configuration's state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_state_t data; + const ec_slave_config_t *sc; + ec_slave_config_state_t state; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because sc will not be deleted in the + * meantime. */ + + if (!(sc = ec_master_get_config_const(master, data.config_index))) { + return -ENOENT; + } + + ret = ecrt_slave_config_state(sc, &state); + if (ret) + return ret; + + if (ec_copy_to_user((void __user *) data.state, + &state, sizeof(state), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Configures an IDN. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_idn( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_idn_t ioctl; + ec_slave_config_t *sc; + uint8_t *data = NULL; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) + return -EFAULT; + + if (!ioctl.size) + return -EINVAL; + + if (!(data = kmalloc(ioctl.size, GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(data, (void __user *) ioctl.data, ioctl.size)) { + kfree(data); + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + kfree(data); + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, ioctl.config_index))) { + up(&master->master_sem); + kfree(data); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + ret = ecrt_slave_config_idn( + sc, ioctl.drive_no, ioctl.idn, ioctl.al_state, data, ioctl.size); + kfree(data); + return ret; +} + +/****************************************************************************/ + +/** Configures a feature flag. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_flag( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_flag_t ioctl; + ec_slave_config_t *sc; + uint8_t *key; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + if (!ioctl.key_size) { + return -EINVAL; + } + + if (!(key = kmalloc(ioctl.key_size + 1, GFP_KERNEL))) { + return -ENOMEM; + } + + if (copy_from_user(key, (void __user *) ioctl.key, ioctl.key_size)) { + kfree(key); + return -EFAULT; + } + key[ioctl.key_size] = '\0'; + + if (down_interruptible(&master->master_sem)) { + kfree(key); + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, ioctl.config_index))) { + up(&master->master_sem); + kfree(key); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + ret = ecrt_slave_config_flag(sc, key, ioctl.value); + kfree(key); + return ret; +} + +/****************************************************************************/ + +/** Sets an AL state transition timeout. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_state_timeout( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sc_state_timeout_t ioctl; + ec_slave_config_t *sc; + int ret; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, ioctl.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + ret = ecrt_slave_config_state_timeout(sc, ioctl.from_state, + ioctl.to_state, ioctl.timeout_ms); + return ret; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Configures EoE IP parameters. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sc_ip( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_eoe_ip_t io; + ec_slave_config_t *sc; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + if (!(sc = ec_master_get_config(master, io.config_index))) { + up(&master->master_sem); + return -ENOENT; + } + + up(&master->master_sem); /** \todo sc could be invalidated */ + + /* the kernel versions of the EoE set IP methods never fail. */ + if (io.mac_address_included) { + ecrt_slave_config_eoe_mac_address(sc, io.mac_address); + } + if (io.ip_address_included) { + ecrt_slave_config_eoe_ip_address(sc, io.ip_address); + } + if (io.subnet_mask_included) { + ecrt_slave_config_eoe_subnet_mask(sc, io.subnet_mask); + } + if (io.gateway_included) { + ecrt_slave_config_eoe_default_gateway(sc, io.gateway); + } + if (io.dns_included) { + ecrt_slave_config_eoe_dns_address(sc, io.dns); + } + if (io.name_included) { + ecrt_slave_config_eoe_hostname(sc, io.name); + } + + return 0; +} + +#endif + +/****************************************************************************/ + +/** Gets the domain's data size. + * + * \return Domain size, or a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_size( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + const ec_domain_t *domain; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + list_for_each_entry(domain, &master->domains, list) { + if (domain->index == (unsigned long) arg) { + size_t size = ecrt_domain_size(domain); + up(&master->master_sem); + return size; + } + } + + up(&master->master_sem); + return -ENOENT; +} + +/****************************************************************************/ + +/** Gets the domain's offset in the total process data. + * + * \return Domain offset, or a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_offset( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + int offset = 0; + const ec_domain_t *domain; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + list_for_each_entry(domain, &master->domains, list) { + if (domain->index == (unsigned long) arg) { + up(&master->master_sem); + return offset; + } + offset += ecrt_domain_size(domain); + } + + up(&master->master_sem); + return -ENOENT; +} + +/****************************************************************************/ + +/** Process the domain. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_process( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_domain_t *domain; + + if (unlikely(!ctx->requested)) + return -EPERM; + + /* no locking of master_sem needed, because domain will not be deleted in + * the meantime. */ + + if (!(domain = ec_master_find_domain(master, (unsigned long) arg))) { + return -ENOENT; + } + + return ecrt_domain_process(domain); +} + +/****************************************************************************/ + +/** Queue the domain. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_queue( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_domain_t *domain; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + /* no locking of master_sem needed, because domain will not be deleted in + * the meantime. */ + + if (!(domain = ec_master_find_domain(master, (unsigned long) arg))) { + return -ENOENT; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + ret = ecrt_domain_queue(domain); + ec_ioctl_unlock(&master->io_mutex); + return ret; +} + +/****************************************************************************/ + +/** Get the domain state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_domain_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_domain_state_t data; + const ec_domain_t *domain; + ec_domain_state_t state; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because domain will not be deleted in + * the meantime. */ + + if (!(domain = ec_master_find_domain_const(master, data.domain_index))) { + return -ENOENT; + } + + ret = ecrt_domain_state(domain, &state); + if (ret) + return ret; + + if (ec_copy_to_user((void __user *) data.state, &state, sizeof(state), + ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Sets an SDO request's SDO index and subindex. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_index( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_sdo_request_index(req, data.sdo_index, data.sdo_subindex); +} + +/****************************************************************************/ + +/** Sets an SDO request's timeout. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_timeout( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_sdo_request_timeout(req, data.timeout); +} + +/****************************************************************************/ + +/** Gets an SDO request's state. + * + * Also pre-fetches the size of incoming data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + data.state = ecrt_sdo_request_state(req); + if (data.state == EC_REQUEST_SUCCESS && req->dir == EC_DIR_INPUT) + data.size = ecrt_sdo_request_data_size(req); + else + data.size = 0; + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Starts an SDO read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_sdo_request_read(req); +} + +/****************************************************************************/ + +/** Starts an SDO write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + if (!data.size) { + EC_MASTER_ERR(master, "SDO download: Data size may not be zero!\n"); + return -EINVAL; + } + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + if (data.size > req->mem_size) + return -ENOBUFS; + + if (ec_copy_from_user(req->data, (void __user *) data.data, + data.size, ctx)) + return -EFAULT; + + req->data_size = data.size; + return ecrt_sdo_request_write(req); +} + +/****************************************************************************/ + +/** Read SDO data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_sdo_request_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_sdo_request_t data; + ec_slave_config_t *sc; + ec_sdo_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_sdo_request(sc, data.request_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) data.data, ecrt_sdo_request_data(req), + ecrt_sdo_request_data_size(req), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Sets an SoE request's drive number and IDN. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_index( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_soe_request_idn(req, data.drive_no, data.idn); +} + +/****************************************************************************/ + +/** Sets an CoE request's timeout. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_timeout( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_soe_request_timeout(req, data.timeout); +} + +/****************************************************************************/ + +/** Gets an SoE request's state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + data.state = ecrt_soe_request_state(req); + if (data.state == EC_REQUEST_SUCCESS && req->dir == EC_DIR_INPUT) { + data.size = ecrt_soe_request_data_size(req); + } + else { + data.size = 0; + } + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Starts an SoE IDN read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + return ecrt_soe_request_read(req); +} + +/****************************************************************************/ + +/** Starts an SoE IDN write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + if (!data.size) { + EC_MASTER_ERR(master, "IDN write: Data size may not be zero!\n"); + return -EINVAL; + } + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + if (data.size > req->mem_size) + return -ENOBUFS; + + if (ec_copy_from_user(req->data, (void __user *) data.data, + data.size, ctx)) + return -EFAULT; + + req->data_size = data.size; + return ecrt_soe_request_write(req); +} + +/****************************************************************************/ + +/** Read SoE IDN data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_soe_request_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_soe_request_t data; + ec_slave_config_t *sc; + ec_soe_request_t *req; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor req will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(req = ec_slave_config_find_soe_request(sc, data.request_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) data.data, ecrt_soe_request_data(req), + ecrt_soe_request_data_size(req), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Read register data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + if (io.mem_size <= 0) { + return 0; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) io.data, ecrt_reg_request_data(reg), + min(reg->mem_size, io.mem_size), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Gets an register request's state. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_state( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + io.state = ecrt_reg_request_state(reg); + io.new_data = io.state == EC_REQUEST_SUCCESS && reg->dir == EC_DIR_INPUT; + + if (ec_copy_to_user((void __user *) arg, &io, sizeof(io), ctx)) { + return -EFAULT; + } + + return 0; +} + +/****************************************************************************/ + +/** Starts an register write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + if (io.transfer_size > reg->mem_size) { + return -ENOBUFS; + } + + if (ec_copy_from_user(reg->data, (void __user *) io.data, + io.transfer_size, ctx)) { + return -EFAULT; + } + + return ecrt_reg_request_write(reg, io.address, io.transfer_size); +} + +/****************************************************************************/ + +/** Starts an register read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_reg_request_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_reg_request_t io; + ec_slave_config_t *sc; + ec_reg_request_t *reg; + + if (unlikely(!ctx->requested)) { + return -EPERM; + } + + if (ec_copy_from_user(&io, (void __user *) arg, sizeof(io), ctx)) { + return -EFAULT; + } + + /* no locking of master_sem needed, because neither sc nor reg will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, io.config_index))) { + return -ENOENT; + } + + if (!(reg = ec_slave_config_find_reg_request(sc, io.request_index))) { + return -ENOENT; + } + + if (io.transfer_size > reg->mem_size) { + return -ENOBUFS; + } + + return ecrt_reg_request_read(reg, io.address, io.transfer_size); +} + +/****************************************************************************/ + +/** Sets the VoE send header. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_send_header( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + uint32_t vendor_id; + uint16_t vendor_type; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + if (ec_copy_from_user(&vendor_id, data.vendor_id, sizeof(vendor_id), ctx)) + return -EFAULT; + + if (ec_copy_from_user(&vendor_type, data.vendor_type, + sizeof(vendor_type), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + return ecrt_voe_handler_send_header(voe, vendor_id, vendor_type); +} + +/****************************************************************************/ + +/** Gets the received VoE header. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_rec_header( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + uint32_t vendor_id; + uint16_t vendor_type; + int ret; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + ret = ecrt_voe_handler_received_header(voe, &vendor_id, &vendor_type); + if (ret) + return ret; + + if (likely(data.vendor_id)) + if (ec_copy_to_user(data.vendor_id, &vendor_id, + sizeof(vendor_id), ctx)) + return -EFAULT; + + if (likely(data.vendor_type)) + if (ec_copy_to_user(data.vendor_type, &vendor_type, + sizeof(vendor_type), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Starts a VoE read operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + return ecrt_voe_handler_read(voe); +} + +/****************************************************************************/ + +/** Starts a VoE read operation without sending a sync message first. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_read_nosync( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + return ecrt_voe_handler_read_nosync(voe); +} + +/****************************************************************************/ + +/** Starts a VoE write operation. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + if (data.size) { + if (data.size > ec_voe_handler_mem_size(voe)) + return -ENOBUFS; + + if (ec_copy_from_user(ecrt_voe_handler_data(voe), + (void __user *) data.data, data.size, ctx)) + return -EFAULT; + } + + return ecrt_voe_handler_write(voe, data.size); +} + +/****************************************************************************/ + +/** Executes the VoE state machine. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_exec( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + if (ec_ioctl_lock_interruptible(&master->io_mutex)) + return -EINTR; + + data.state = ecrt_voe_handler_execute(voe); + ec_ioctl_unlock(&master->io_mutex); + if (data.state == EC_REQUEST_SUCCESS && voe->dir == EC_DIR_INPUT) + data.size = ecrt_voe_handler_data_size(voe); + else + data.size = 0; + + if (ec_copy_to_user((void __user *) arg, &data, sizeof(data), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Reads the received VoE data. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_voe_data( + ec_master_t *master, /**< EtherCAT master. */ + void *arg, /**< ioctl() argument. */ + ec_ioctl_context_t *ctx /**< Private data structure of file handle. */ + ) +{ + ec_ioctl_voe_t data; + ec_slave_config_t *sc; + ec_voe_handler_t *voe; + + if (unlikely(!ctx->requested)) + return -EPERM; + + if (ec_copy_from_user(&data, (void __user *) arg, sizeof(data), ctx)) + return -EFAULT; + + /* no locking of master_sem needed, because neither sc nor voe will not be + * deleted in the meantime. */ + + if (!(sc = ec_master_get_config(master, data.config_index))) { + return -ENOENT; + } + + if (!(voe = ec_slave_config_find_voe_handler(sc, data.voe_index))) { + return -ENOENT; + } + + if (ec_copy_to_user((void __user *) data.data, ecrt_voe_handler_data(voe), + ecrt_voe_handler_data_size(voe), ctx)) + return -EFAULT; + + return 0; +} + +/****************************************************************************/ + +/** Read a file from a slave via FoE. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_foe_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_foe_t io; + ec_foe_request_t request; + ec_slave_t *slave; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + ec_foe_request_init(&request, io.file_name); + ret = ec_foe_request_alloc(&request, 10000); // FIXME + if (ret) { + ec_foe_request_clear(&request); + return ret; + } + + ec_foe_request_read(&request); + + if (down_interruptible(&master->master_sem)) { + ec_foe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, io.slave_position))) { + up(&master->master_sem); + ec_foe_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling FoE read request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->foe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_foe_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + io.result = request.result; + io.error_code = request.error_code; + + if (request.state != EC_INT_REQUEST_SUCCESS) { + io.data_size = 0; + ret = -EIO; + } else { + if (request.data_size > io.buffer_size) { + EC_SLAVE_ERR(slave, "%s(): Buffer too small.\n", __func__); + ec_foe_request_clear(&request); + return -ENOBUFS; + } + io.data_size = request.data_size; + if (copy_to_user((void __user *) io.buffer, + request.buffer, io.data_size)) { + ec_foe_request_clear(&request); + return -EFAULT; + } + ret = 0; + } + + if (__copy_to_user((void __user *) arg, &io, sizeof(io))) { + ret = -EFAULT; + } + + ec_foe_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +/** Write a file to a slave via FoE + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_foe_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_foe_t io; + ec_foe_request_t request; + ec_slave_t *slave; + int ret; + + if (copy_from_user(&io, (void __user *) arg, sizeof(io))) { + return -EFAULT; + } + + ec_foe_request_init(&request, io.file_name); + + ret = ec_foe_request_alloc(&request, io.buffer_size); + if (ret) { + ec_foe_request_clear(&request); + return ret; + } + + if (copy_from_user(request.buffer, + (void __user *) io.buffer, io.buffer_size)) { + ec_foe_request_clear(&request); + return -EFAULT; + } + + request.data_size = io.buffer_size; + ec_foe_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_foe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, io.slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + io.slave_position); + ec_foe_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling FoE write request.\n"); + + // schedule FoE write request. + list_add_tail(&request.list, &slave->foe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_foe_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + io.result = request.result; + io.error_code = request.error_code; + + ret = request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; + + if (__copy_to_user((void __user *) arg, &io, sizeof(io))) { + ret = -EFAULT; + } + + ec_foe_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +/** Read an SoE IDN. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_soe_read( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_soe_read_t ioctl; + u8 *data; + int retval; + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + data = kmalloc(ioctl.mem_size, GFP_KERNEL); + if (!data) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes of IDN data.\n", + ioctl.mem_size); + return -ENOMEM; + } + + retval = ecrt_master_read_idn(master, ioctl.slave_position, + ioctl.drive_no, ioctl.idn, data, ioctl.mem_size, &ioctl.data_size, + &ioctl.error_code); + if (retval) { + kfree(data); + return retval; + } + + if (copy_to_user((void __user *) ioctl.data, + data, ioctl.data_size)) { + kfree(data); + return -EFAULT; + } + kfree(data); + + if (__copy_to_user((void __user *) arg, &ioctl, sizeof(ioctl))) { + retval = -EFAULT; + } + + EC_MASTER_DBG(master, 1, "Finished SoE read request.\n"); + return retval; +} + +/****************************************************************************/ + +/** Write an IDN to a slave via SoE. + * + * \return Zero on success, otherwise a negative error code. + */ +static ATTRIBUTES int ec_ioctl_slave_soe_write( + ec_master_t *master, /**< EtherCAT master. */ + void *arg /**< ioctl() argument. */ + ) +{ + ec_ioctl_slave_soe_write_t ioctl; + u8 *data; + int retval; + + if (copy_from_user(&ioctl, (void __user *) arg, sizeof(ioctl))) { + return -EFAULT; + } + + data = kmalloc(ioctl.data_size, GFP_KERNEL); + if (!data) { + EC_MASTER_ERR(master, "Failed to allocate %zu bytes of IDN data.\n", + ioctl.data_size); + return -ENOMEM; + } + if (copy_from_user(data, (void __user *) ioctl.data, ioctl.data_size)) { + kfree(data); + return -EFAULT; + } + + retval = ecrt_master_write_idn(master, ioctl.slave_position, + ioctl.drive_no, ioctl.idn, data, ioctl.data_size, + &ioctl.error_code); + kfree(data); + if (retval) { + return retval; + } + + if (__copy_to_user((void __user *) arg, &ioctl, sizeof(ioctl))) { + retval = -EFAULT; + } + + EC_MASTER_DBG(master, 1, "Finished SoE write request.\n"); + return retval; +} + +/***************************************************************************** + * ioctl() file operation functions + ****************************************************************************/ + +/** ioctl() function to use. + * + * For RTDM, there will be ec_ioctl_rtdm_rt and ec_ioctl_rtdm_nrt. + * For "normal" cdev, there will be ec_ioctl_rt only. + */ +#ifndef EC_IOCTL_RTDM +static long ec_ioctl_nrt( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */); +#endif + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + * Both RT and nRT context. + * + * \return ioctl() return code. + */ +static long ec_ioctl_both( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */ + ) +{ + int ret; + + switch (cmd) { + case EC_IOCTL_MODULE: + ret = ec_ioctl_module(arg, ctx); + break; + case EC_IOCTL_MASTER_RESCAN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_master_rescan(master, arg); + break; + case EC_IOCTL_MASTER_STATE: + ret = ec_ioctl_master_state(master, arg, ctx); + break; + case EC_IOCTL_MASTER_LINK_STATE: + ret = ec_ioctl_master_link_state(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_TIMEOUT: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_timeout(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_DATA: + ret = ec_ioctl_sdo_request_data(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_TIMEOUT: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_timeout(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_DATA: + ret = ec_ioctl_soe_request_data(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_DATA: + ret = ec_ioctl_reg_request_data(master, arg, ctx); + break; + case EC_IOCTL_VOE_SEND_HEADER: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_send_header(master, arg, ctx); + break; + case EC_IOCTL_VOE_DATA: + ret = ec_ioctl_voe_data(master, arg, ctx); + break; + default: +#ifdef EC_IOCTL_RTDM + ret = -ENOTTY; +#else + /* chain non-rt commands for normal cdev */ + ret = ec_ioctl_nrt(master, ctx, cmd, arg); +#endif + break; + } + + return ret; +} + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + * RTDM: RT only. + * + * \return ioctl() return code. + */ +#ifdef EC_IOCTL_RTDM +long ec_ioctl_rtdm_rt +#else +long ec_ioctl +#endif + ( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */ + ) +{ +#if DEBUG_LATENCY + cycles_t a = get_cycles(), b; + unsigned int t; +#endif + long ret; + + switch (cmd) { + case EC_IOCTL_SEND: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_send(master, arg, ctx); + break; + case EC_IOCTL_RECEIVE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_receive(master, arg, ctx); + break; + case EC_IOCTL_APP_TIME: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_app_time(master, arg, ctx); + break; + case EC_IOCTL_SYNC_REF: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_ref(master, arg, ctx); + break; + case EC_IOCTL_SYNC_REF_TO: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_ref_to(master, arg, ctx); + break; + case EC_IOCTL_SYNC_SLAVES: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_slaves(master, arg, ctx); + break; + case EC_IOCTL_REF_CLOCK_TIME: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_ref_clock_time(master, arg, ctx); + break; + case EC_IOCTL_SYNC_MON_QUEUE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_mon_queue(master, arg, ctx); + break; + case EC_IOCTL_SYNC_MON_PROCESS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sync_mon_process(master, arg, ctx); + break; + case EC_IOCTL_RESET: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_reset(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_POP: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_emerg_pop(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_CLEAR: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_emerg_clear(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_OVERRUNS: + ret = ec_ioctl_sc_emerg_overruns(master, arg, ctx); + break; + case EC_IOCTL_SC_STATE: + ret = ec_ioctl_sc_state(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_PROCESS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_domain_process(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_QUEUE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_domain_queue(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_STATE: + ret = ec_ioctl_domain_state(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_INDEX: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_index(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_STATE: + ret = ec_ioctl_sdo_request_state(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_read(master, arg, ctx); + break; + case EC_IOCTL_SDO_REQUEST_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sdo_request_write(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_IDN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_index(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_STATE: + ret = ec_ioctl_soe_request_state(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_read(master, arg, ctx); + break; + case EC_IOCTL_SOE_REQUEST_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_soe_request_write(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_STATE: + ret = ec_ioctl_reg_request_state(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_reg_request_write(master, arg, ctx); + break; + case EC_IOCTL_REG_REQUEST_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_reg_request_read(master, arg, ctx); + break; + case EC_IOCTL_VOE_REC_HEADER: + ret = ec_ioctl_voe_rec_header(master, arg, ctx); + break; + case EC_IOCTL_VOE_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_read(master, arg, ctx); + break; + case EC_IOCTL_VOE_READ_NOSYNC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_read_nosync(master, arg, ctx); + break; + case EC_IOCTL_VOE_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_write(master, arg, ctx); + break; + case EC_IOCTL_VOE_EXEC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_voe_exec(master, arg, ctx); + break; + default: + ret = ec_ioctl_both(master, ctx, cmd, arg); + break; + } + +#if DEBUG_LATENCY + b = get_cycles(); + t = (unsigned int) ((b - a) * 1000LL) / cpu_khz; + if (t > 50) { + EC_MASTER_WARN(master, "ioctl(0x%02x) took %u us.\n", + _IOC_NR(cmd), t); + } +#endif + + return ret; +} + +/****************************************************************************/ + +/** Called when an ioctl() command is issued. + * nRT context only. + * + * \return ioctl() return code. + */ +#ifdef EC_IOCTL_RTDM +long ec_ioctl_rtdm_nrt +#else +static long ec_ioctl_nrt +#endif + ( + ec_master_t *master, /**< EtherCAT master. */ + ec_ioctl_context_t *ctx, /**< Device context. */ + unsigned int cmd, /**< ioctl() command identifier. */ + void *arg /**< ioctl() argument. */ + ) +{ +#if DEBUG_LATENCY && !defined(EC_IOCTL_RTDM) + cycles_t a = get_cycles(), b; + unsigned int t; +#endif + int ret; + + switch (cmd) { + case EC_IOCTL_MASTER: + ret = ec_ioctl_master(master, arg); + break; + case EC_IOCTL_SLAVE: + ret = ec_ioctl_slave(master, arg); + break; + case EC_IOCTL_SLAVE_SYNC: + ret = ec_ioctl_slave_sync(master, arg); + break; + case EC_IOCTL_SLAVE_SYNC_PDO: + ret = ec_ioctl_slave_sync_pdo(master, arg); + break; + case EC_IOCTL_SLAVE_SYNC_PDO_ENTRY: + ret = ec_ioctl_slave_sync_pdo_entry(master, arg); + break; + case EC_IOCTL_DOMAIN: + ret = ec_ioctl_domain(master, arg); + break; + case EC_IOCTL_DOMAIN_FMMU: + ret = ec_ioctl_domain_fmmu(master, arg); + break; + case EC_IOCTL_DOMAIN_DATA: + ret = ec_ioctl_domain_data(master, arg); + break; + case EC_IOCTL_MASTER_DEBUG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_master_debug(master, arg); + break; + case EC_IOCTL_SLAVE_STATE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_state(master, arg); + break; + case EC_IOCTL_SLAVE_SDO: + ret = ec_ioctl_slave_sdo(master, arg); + break; + case EC_IOCTL_SLAVE_SDO_ENTRY: + ret = ec_ioctl_slave_sdo_entry(master, arg); + break; + case EC_IOCTL_SLAVE_SDO_UPLOAD: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_sdo_upload(master, arg); + break; + case EC_IOCTL_SLAVE_SDO_DOWNLOAD: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_sdo_download(master, arg); + break; + case EC_IOCTL_SLAVE_SII_READ: + ret = ec_ioctl_slave_sii_read(master, arg); + break; + case EC_IOCTL_SLAVE_SII_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_sii_write(master, arg); + break; + case EC_IOCTL_SLAVE_REG_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_reg_read(master, arg); + break; + case EC_IOCTL_SLAVE_REG_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_reg_write(master, arg); + break; + case EC_IOCTL_SLAVE_FOE_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_foe_read(master, arg); + break; + case EC_IOCTL_SLAVE_FOE_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_foe_write(master, arg); + break; + case EC_IOCTL_SLAVE_SOE_READ: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_soe_read(master, arg); + break; + case EC_IOCTL_SLAVE_SOE_WRITE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_soe_write(master, arg); + break; +#ifdef EC_EOE + case EC_IOCTL_SLAVE_EOE_IP_PARAM: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_slave_eoe_ip_param(master, arg); + break; +#endif + case EC_IOCTL_CONFIG: + ret = ec_ioctl_config(master, arg); + break; + case EC_IOCTL_CONFIG_PDO: + ret = ec_ioctl_config_pdo(master, arg); + break; + case EC_IOCTL_CONFIG_PDO_ENTRY: + ret = ec_ioctl_config_pdo_entry(master, arg); + break; + case EC_IOCTL_CONFIG_SDO: + ret = ec_ioctl_config_sdo(master, arg); + break; + case EC_IOCTL_CONFIG_IDN: + ret = ec_ioctl_config_idn(master, arg); + break; + case EC_IOCTL_CONFIG_FLAG: + ret = ec_ioctl_config_flag(master, arg); + break; +#ifdef EC_EOE + case EC_IOCTL_CONFIG_EOE_IP_PARAM: + ret = ec_ioctl_config_ip(master, arg); + break; + case EC_IOCTL_EOE_HANDLER: + ret = ec_ioctl_eoe_handler(master, arg); + break; +#endif + + /* Application interface */ + + case EC_IOCTL_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_request(master, arg, ctx); + break; + case EC_IOCTL_CREATE_DOMAIN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_create_domain(master, arg, ctx); + break; + case EC_IOCTL_CREATE_SLAVE_CONFIG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_create_slave_config(master, arg, ctx); + break; + case EC_IOCTL_SELECT_REF_CLOCK: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_select_ref_clock(master, arg, ctx); + break; + case EC_IOCTL_ACTIVATE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_activate(master, arg, ctx); + break; + case EC_IOCTL_DEACTIVATE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_deactivate(master, arg, ctx); + break; + case EC_IOCTL_SC_SYNC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_sync(master, arg, ctx); + break; + case EC_IOCTL_SC_WATCHDOG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_watchdog(master, arg, ctx); + break; + case EC_IOCTL_SC_ADD_PDO: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_add_pdo(master, arg, ctx); + break; + case EC_IOCTL_SC_CLEAR_PDOS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_clear_pdos(master, arg, ctx); + break; + case EC_IOCTL_SC_ADD_ENTRY: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_add_entry(master, arg, ctx); + break; + case EC_IOCTL_SC_CLEAR_ENTRIES: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_clear_entries(master, arg, ctx); + break; + case EC_IOCTL_SC_REG_PDO_ENTRY: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_reg_pdo_entry(master, arg, ctx); + break; + case EC_IOCTL_SC_REG_PDO_POS: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_reg_pdo_pos(master, arg, ctx); + break; + case EC_IOCTL_SC_DC: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_dc(master, arg, ctx); + break; + case EC_IOCTL_SC_SDO: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_sdo(master, arg, ctx); + break; + case EC_IOCTL_SC_EMERG_SIZE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_emerg_size(master, arg, ctx); + break; + case EC_IOCTL_SC_SDO_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_sdo_request(master, arg, ctx); + break; + case EC_IOCTL_SC_SOE_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_soe_request(master, arg, ctx); + break; + case EC_IOCTL_SC_REG_REQUEST: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_reg_request(master, arg, ctx); + break; + case EC_IOCTL_SC_VOE: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_create_voe_handler(master, arg, ctx); + break; + case EC_IOCTL_SC_IDN: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_idn(master, arg, ctx); + break; + case EC_IOCTL_SC_FLAG: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_flag(master, arg, ctx); + break; + case EC_IOCTL_SC_STATE_TIMEOUT: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_state_timeout(master, arg, ctx); + break; +#ifdef EC_EOE + case EC_IOCTL_SC_EOE_IP_PARAM: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_sc_ip(master, arg, ctx); + break; +#endif + case EC_IOCTL_DOMAIN_SIZE: + ret = ec_ioctl_domain_size(master, arg, ctx); + break; + case EC_IOCTL_DOMAIN_OFFSET: + ret = ec_ioctl_domain_offset(master, arg, ctx); + break; + case EC_IOCTL_SET_SEND_INTERVAL: + if (!ctx->writable) { + ret = -EPERM; + break; + } + ret = ec_ioctl_set_send_interval(master, arg, ctx); + break; + default: +#ifdef EC_IOCTL_RTDM + ret = ec_ioctl_both(master, ctx, cmd, arg); +#else + ret = -ENOTTY; +#endif + break; + } + +#if DEBUG_LATENCY && !defined(EC_IOCTL_RTDM) + b = get_cycles(); + t = (unsigned int) ((b - a) * 1000LL) / cpu_khz; + if (t > 50) { + EC_MASTER_WARN(master, "ioctl(0x%02x) took %u us.\n", + _IOC_NR(cmd), t); + } +#endif + + return ret; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/ioctl.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/ioctl.h @@ -0,0 +1,879 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT master. + * + * The file is free software; you can redistribute it and/or modify it under + * the terms of the GNU Lesser General Public License as published by the + * Free Software Foundation; version 2.1 of the License. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + * License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this file. If not, see . + * + ****************************************************************************/ + +/** + \file + EtherCAT master character device IOCTL commands. +*/ + +/****************************************************************************/ + +#ifndef __EC_IOCTL_H__ +#define __EC_IOCTL_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** \cond */ + +#define EC_IOCTL_TYPE 0xa4 + +#define EC_IO(nr) _IO(EC_IOCTL_TYPE, nr) +#define EC_IOR(nr, type) _IOR(EC_IOCTL_TYPE, nr, type) +#define EC_IOW(nr, type) _IOW(EC_IOCTL_TYPE, nr, type) +#define EC_IOWR(nr, type) _IOWR(EC_IOCTL_TYPE, nr, type) + +/** EtherCAT master ioctl() version magic. + * + * Increment this when changing the ioctl interface! + */ +#define EC_IOCTL_VERSION_MAGIC 37 + +// Command-line tool +#define EC_IOCTL_MODULE EC_IOR(0x00, ec_ioctl_module_t) +#define EC_IOCTL_MASTER EC_IOR(0x01, ec_ioctl_master_t) +#define EC_IOCTL_SLAVE EC_IOWR(0x02, ec_ioctl_slave_t) +#define EC_IOCTL_SLAVE_SYNC EC_IOWR(0x03, ec_ioctl_slave_sync_t) +#define EC_IOCTL_SLAVE_SYNC_PDO EC_IOWR(0x04, ec_ioctl_slave_sync_pdo_t) +#define EC_IOCTL_SLAVE_SYNC_PDO_ENTRY EC_IOWR(0x05, ec_ioctl_slave_sync_pdo_entry_t) +#define EC_IOCTL_DOMAIN EC_IOWR(0x06, ec_ioctl_domain_t) +#define EC_IOCTL_DOMAIN_FMMU EC_IOWR(0x07, ec_ioctl_domain_fmmu_t) +#define EC_IOCTL_DOMAIN_DATA EC_IOWR(0x08, ec_ioctl_domain_data_t) +#define EC_IOCTL_MASTER_DEBUG EC_IO(0x09) +#define EC_IOCTL_MASTER_RESCAN EC_IO(0x0a) +#define EC_IOCTL_SLAVE_STATE EC_IOW(0x0b, ec_ioctl_slave_state_t) +#define EC_IOCTL_SLAVE_SDO EC_IOWR(0x0c, ec_ioctl_slave_sdo_t) +#define EC_IOCTL_SLAVE_SDO_ENTRY EC_IOWR(0x0d, ec_ioctl_slave_sdo_entry_t) +#define EC_IOCTL_SLAVE_SDO_UPLOAD EC_IOWR(0x0e, ec_ioctl_slave_sdo_upload_t) +#define EC_IOCTL_SLAVE_SDO_DOWNLOAD EC_IOWR(0x0f, ec_ioctl_slave_sdo_download_t) +#define EC_IOCTL_SLAVE_SII_READ EC_IOWR(0x10, ec_ioctl_slave_sii_t) +#define EC_IOCTL_SLAVE_SII_WRITE EC_IOW(0x11, ec_ioctl_slave_sii_t) +#define EC_IOCTL_SLAVE_REG_READ EC_IOWR(0x12, ec_ioctl_slave_reg_t) +#define EC_IOCTL_SLAVE_REG_WRITE EC_IOW(0x13, ec_ioctl_slave_reg_t) +#define EC_IOCTL_SLAVE_FOE_READ EC_IOWR(0x14, ec_ioctl_slave_foe_t) +#define EC_IOCTL_SLAVE_FOE_WRITE EC_IOW(0x15, ec_ioctl_slave_foe_t) +#define EC_IOCTL_SLAVE_SOE_READ EC_IOWR(0x16, ec_ioctl_slave_soe_read_t) +#define EC_IOCTL_SLAVE_SOE_WRITE EC_IOWR(0x17, ec_ioctl_slave_soe_write_t) +#ifdef EC_EOE +#define EC_IOCTL_SLAVE_EOE_IP_PARAM EC_IOW(0x18, ec_ioctl_eoe_ip_t) +#endif +#define EC_IOCTL_CONFIG EC_IOWR(0x19, ec_ioctl_config_t) +#define EC_IOCTL_CONFIG_PDO EC_IOWR(0x1a, ec_ioctl_config_pdo_t) +#define EC_IOCTL_CONFIG_PDO_ENTRY EC_IOWR(0x1b, ec_ioctl_config_pdo_entry_t) +#define EC_IOCTL_CONFIG_SDO EC_IOWR(0x1c, ec_ioctl_config_sdo_t) +#define EC_IOCTL_CONFIG_IDN EC_IOWR(0x1d, ec_ioctl_config_idn_t) +#define EC_IOCTL_CONFIG_FLAG EC_IOWR(0x1e, ec_ioctl_config_flag_t) +#ifdef EC_EOE +#define EC_IOCTL_CONFIG_EOE_IP_PARAM EC_IOWR(0x1f, ec_ioctl_eoe_ip_t) +#define EC_IOCTL_EOE_HANDLER EC_IOWR(0x20, ec_ioctl_eoe_handler_t) +#endif + +// Application interface +#define EC_IOCTL_REQUEST EC_IO(0x21) +#define EC_IOCTL_CREATE_DOMAIN EC_IO(0x22) +#define EC_IOCTL_CREATE_SLAVE_CONFIG EC_IOWR(0x23, ec_ioctl_config_t) +#define EC_IOCTL_SELECT_REF_CLOCK EC_IOW(0x24, uint32_t) +#define EC_IOCTL_ACTIVATE EC_IOR(0x25, ec_ioctl_master_activate_t) +#define EC_IOCTL_DEACTIVATE EC_IO(0x26) +#define EC_IOCTL_SEND EC_IO(0x27) +#define EC_IOCTL_RECEIVE EC_IO(0x28) +#define EC_IOCTL_MASTER_STATE EC_IOR(0x29, ec_master_state_t) +#define EC_IOCTL_MASTER_LINK_STATE EC_IOWR(0x2a, ec_ioctl_link_state_t) +#define EC_IOCTL_APP_TIME EC_IOW(0x2b, uint64_t) +#define EC_IOCTL_SYNC_REF EC_IO(0x2c) +#define EC_IOCTL_SYNC_REF_TO EC_IOW(0x2d, uint64_t) +#define EC_IOCTL_SYNC_SLAVES EC_IO(0x2e) +#define EC_IOCTL_REF_CLOCK_TIME EC_IOR(0x2f, uint32_t) +#define EC_IOCTL_SYNC_MON_QUEUE EC_IO(0x30) +#define EC_IOCTL_SYNC_MON_PROCESS EC_IOR(0x31, uint32_t) +#define EC_IOCTL_RESET EC_IO(0x32) +#define EC_IOCTL_SC_SYNC EC_IOW(0x33, ec_ioctl_config_t) +#define EC_IOCTL_SC_WATCHDOG EC_IOW(0x34, ec_ioctl_config_t) +#define EC_IOCTL_SC_ADD_PDO EC_IOW(0x35, ec_ioctl_config_pdo_t) +#define EC_IOCTL_SC_CLEAR_PDOS EC_IOW(0x36, ec_ioctl_config_pdo_t) +#define EC_IOCTL_SC_ADD_ENTRY EC_IOW(0x37, ec_ioctl_add_pdo_entry_t) +#define EC_IOCTL_SC_CLEAR_ENTRIES EC_IOW(0x38, ec_ioctl_config_pdo_t) +#define EC_IOCTL_SC_REG_PDO_ENTRY EC_IOWR(0x39, ec_ioctl_reg_pdo_entry_t) +#define EC_IOCTL_SC_REG_PDO_POS EC_IOWR(0x3a, ec_ioctl_reg_pdo_pos_t) +#define EC_IOCTL_SC_DC EC_IOW(0x3b, ec_ioctl_config_t) +#define EC_IOCTL_SC_SDO EC_IOW(0x3c, ec_ioctl_sc_sdo_t) +#define EC_IOCTL_SC_EMERG_SIZE EC_IOW(0x3d, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_EMERG_POP EC_IOWR(0x3e, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_EMERG_CLEAR EC_IOW(0x3f, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_EMERG_OVERRUNS EC_IOWR(0x40, ec_ioctl_sc_emerg_t) +#define EC_IOCTL_SC_SDO_REQUEST EC_IOWR(0x41, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SC_SOE_REQUEST EC_IOWR(0x42, ec_ioctl_soe_request_t) +#define EC_IOCTL_SC_REG_REQUEST EC_IOWR(0x43, ec_ioctl_reg_request_t) +#define EC_IOCTL_SC_VOE EC_IOWR(0x44, ec_ioctl_voe_t) +#define EC_IOCTL_SC_STATE EC_IOWR(0x45, ec_ioctl_sc_state_t) +#define EC_IOCTL_SC_IDN EC_IOW(0x46, ec_ioctl_sc_idn_t) +#define EC_IOCTL_SC_FLAG EC_IOW(0x47, ec_ioctl_sc_flag_t) +#ifdef EC_EOE +#define EC_IOCTL_SC_EOE_IP_PARAM EC_IOW(0x48, ec_ioctl_eoe_ip_t) +#endif +#define EC_IOCTL_SC_STATE_TIMEOUT EC_IOW(0x49, ec_ioctl_sc_state_timeout_t) +#define EC_IOCTL_DOMAIN_SIZE EC_IO(0x4a) +#define EC_IOCTL_DOMAIN_OFFSET EC_IO(0x4b) +#define EC_IOCTL_DOMAIN_PROCESS EC_IO(0x4c) +#define EC_IOCTL_DOMAIN_QUEUE EC_IO(0x4d) +#define EC_IOCTL_DOMAIN_STATE EC_IOWR(0x4e, ec_ioctl_domain_state_t) +#define EC_IOCTL_SDO_REQUEST_INDEX EC_IOWR(0x4f, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_TIMEOUT EC_IOWR(0x50, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_STATE EC_IOWR(0x51, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_READ EC_IOWR(0x52, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_WRITE EC_IOWR(0x53, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SDO_REQUEST_DATA EC_IOWR(0x54, ec_ioctl_sdo_request_t) +#define EC_IOCTL_SOE_REQUEST_IDN EC_IOWR(0x55, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_TIMEOUT EC_IOWR(0x56, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_STATE EC_IOWR(0x57, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_READ EC_IOWR(0x58, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_WRITE EC_IOWR(0x59, ec_ioctl_soe_request_t) +#define EC_IOCTL_SOE_REQUEST_DATA EC_IOWR(0x5a, ec_ioctl_soe_request_t) +#define EC_IOCTL_REG_REQUEST_DATA EC_IOWR(0x5b, ec_ioctl_reg_request_t) +#define EC_IOCTL_REG_REQUEST_STATE EC_IOWR(0x5c, ec_ioctl_reg_request_t) +#define EC_IOCTL_REG_REQUEST_WRITE EC_IOWR(0x5d, ec_ioctl_reg_request_t) +#define EC_IOCTL_REG_REQUEST_READ EC_IOWR(0x5e, ec_ioctl_reg_request_t) +#define EC_IOCTL_VOE_SEND_HEADER EC_IOW(0x5f, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_REC_HEADER EC_IOWR(0x60, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_READ EC_IOW(0x61, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_READ_NOSYNC EC_IOW(0x62, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_WRITE EC_IOWR(0x63, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_EXEC EC_IOWR(0x64, ec_ioctl_voe_t) +#define EC_IOCTL_VOE_DATA EC_IOWR(0x65, ec_ioctl_voe_t) +#define EC_IOCTL_SET_SEND_INTERVAL EC_IOW(0x66, size_t) + +/****************************************************************************/ + +#define EC_IOCTL_STRING_SIZE 64 + +/****************************************************************************/ + +typedef struct { + uint32_t ioctl_version_magic; + uint32_t master_count; +} ec_ioctl_module_t; + +/****************************************************************************/ + +typedef struct { + uint32_t slave_count; + uint32_t scan_index; + uint32_t config_count; + uint32_t domain_count; + uint32_t eoe_handler_count; + uint8_t phase; + uint8_t active; + uint8_t scan_busy; + struct ec_ioctl_device { + uint8_t address[6]; + uint8_t attached; + uint8_t link_state; + uint64_t tx_count; + uint64_t rx_count; + uint64_t tx_bytes; + uint64_t rx_bytes; + uint64_t tx_errors; + int32_t tx_frame_rates[EC_RATE_COUNT]; + int32_t rx_frame_rates[EC_RATE_COUNT]; + int32_t tx_byte_rates[EC_RATE_COUNT]; + int32_t rx_byte_rates[EC_RATE_COUNT]; + } devices[EC_MAX_NUM_DEVICES]; + uint32_t num_devices; + uint64_t tx_count; + uint64_t rx_count; + uint64_t tx_bytes; + uint64_t rx_bytes; + int32_t tx_frame_rates[EC_RATE_COUNT]; + int32_t rx_frame_rates[EC_RATE_COUNT]; + int32_t tx_byte_rates[EC_RATE_COUNT]; + int32_t rx_byte_rates[EC_RATE_COUNT]; + int32_t loss_rates[EC_RATE_COUNT]; + uint64_t app_time; + uint64_t dc_ref_time; + uint16_t ref_clock; +} ec_ioctl_master_t; + +/****************************************************************************/ + +typedef struct { + // input + uint16_t position; + + // outputs + unsigned int device_index; + uint32_t vendor_id; + uint32_t product_code; + uint32_t revision_number; + uint32_t serial_number; + uint16_t alias; + uint16_t boot_rx_mailbox_offset; + uint16_t boot_rx_mailbox_size; + uint16_t boot_tx_mailbox_offset; + uint16_t boot_tx_mailbox_size; + uint16_t std_rx_mailbox_offset; + uint16_t std_rx_mailbox_size; + uint16_t std_tx_mailbox_offset; + uint16_t std_tx_mailbox_size; + uint16_t mailbox_protocols; + uint8_t has_general_category; + ec_sii_coe_details_t coe_details; + ec_sii_general_flags_t general_flags; + int16_t current_on_ebus; + struct { + ec_slave_port_desc_t desc; + ec_slave_port_link_t link; + uint32_t receive_time; + uint16_t next_slave; + uint32_t delay_to_next_dc; + } ports[EC_MAX_PORTS]; + uint8_t fmmu_bit; + uint8_t dc_supported; + ec_slave_dc_range_t dc_range; + uint8_t has_dc_system_time; + uint32_t transmission_delay; + uint8_t al_state; + uint8_t error_flag; + uint8_t sync_count; + uint16_t sdo_count; + uint32_t sii_nwords; + char group[EC_IOCTL_STRING_SIZE]; + char image[EC_IOCTL_STRING_SIZE]; + char order[EC_IOCTL_STRING_SIZE]; + char name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint32_t sync_index; + + // outputs + uint16_t physical_start_address; + uint16_t default_size; + uint8_t control_register; + uint8_t enable; + uint8_t pdo_count; +} ec_ioctl_slave_sync_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint32_t sync_index; + uint32_t pdo_pos; + + // outputs + uint16_t index; + uint8_t entry_count; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sync_pdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint32_t sync_index; + uint32_t pdo_pos; + uint32_t entry_pos; + + // outputs + uint16_t index; + uint8_t subindex; + uint8_t bit_length; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sync_pdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t index; + + // outputs + uint32_t data_size; + uint32_t logical_base_address; + uint16_t working_counter[EC_MAX_NUM_DEVICES]; + uint16_t expected_working_counter; + uint32_t fmmu_count; +} ec_ioctl_domain_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t domain_index; + uint32_t fmmu_index; + + // outputs + uint16_t slave_config_alias; + uint16_t slave_config_position; + uint8_t sync_index; + ec_direction_t dir; + uint32_t logical_address; + uint32_t data_size; +} ec_ioctl_domain_fmmu_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t domain_index; + uint32_t data_size; + uint8_t *target; +} ec_ioctl_domain_data_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t al_state; +} ec_ioctl_slave_state_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t sdo_position; + + // outputs + uint16_t sdo_index; + uint8_t max_subindex; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + int sdo_spec; // positive: index, negative: list position + uint8_t sdo_entry_subindex; + + // outputs + uint16_t data_type; + uint16_t bit_length; + uint8_t read_access[EC_SDO_ENTRY_ACCESS_COUNT]; + uint8_t write_access[EC_SDO_ENTRY_ACCESS_COUNT]; + int8_t description[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_slave_sdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t sdo_index; + uint8_t sdo_entry_subindex; + size_t target_size; + uint8_t *target; + + // outputs + size_t data_size; + uint32_t abort_code; +} ec_ioctl_slave_sdo_upload_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t sdo_index; + uint8_t sdo_entry_subindex; + uint8_t complete_access; + size_t data_size; + uint8_t *data; + + // outputs + uint32_t abort_code; +} ec_ioctl_slave_sdo_download_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t offset; + uint32_t nwords; + uint16_t *words; +} ec_ioctl_slave_sii_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t emergency; + uint16_t address; + size_t size; + uint8_t *data; +} ec_ioctl_slave_reg_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint16_t offset; + size_t buffer_size; + uint8_t *buffer; + + // outputs + size_t data_size; + uint32_t result; + uint32_t error_code; + char file_name[32]; +} ec_ioctl_slave_foe_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t drive_no; + uint16_t idn; + size_t mem_size; + uint8_t *data; + + // outputs + size_t data_size; + uint16_t error_code; +} ec_ioctl_slave_soe_read_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint16_t slave_position; + uint8_t drive_no; + uint16_t idn; + size_t data_size; + uint8_t *data; + + // outputs + uint16_t error_code; +} ec_ioctl_slave_soe_write_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // outputs + uint16_t alias; + uint16_t position; + uint32_t vendor_id; + uint32_t product_code; + struct { + ec_direction_t dir; + ec_watchdog_mode_t watchdog_mode; + uint32_t pdo_count; + uint8_t config_this; + } syncs[EC_MAX_SYNC_MANAGERS]; + uint16_t watchdog_divider; + uint16_t watchdog_intervals; + uint32_t sdo_count; + uint32_t idn_count; + uint32_t flag_count; + int32_t slave_position; + uint16_t dc_assign_activate; + ec_sync_signal_t dc_sync[EC_SYNC_SIGNAL_COUNT]; +} ec_ioctl_config_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint8_t sync_index; + uint16_t pdo_pos; + + // outputs + uint16_t index; + uint8_t entry_count; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_config_pdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint8_t sync_index; + uint16_t pdo_pos; + uint8_t entry_pos; + + // outputs + uint16_t index; + uint8_t subindex; + uint8_t bit_length; + int8_t name[EC_IOCTL_STRING_SIZE]; +} ec_ioctl_config_pdo_entry_t; + +/****************************************************************************/ + +/** Maximum size for displayed SDO data. + * \todo Make this dynamic. + */ +#define EC_MAX_SDO_DATA_SIZE 1024 + +typedef struct { + // inputs + uint32_t config_index; + uint32_t sdo_pos; + + // outputs + uint16_t index; + uint8_t subindex; + size_t size; + uint8_t data[EC_MAX_SDO_DATA_SIZE]; + uint8_t complete_access; +} ec_ioctl_config_sdo_t; + +/****************************************************************************/ + +/** Maximum size for displayed IDN data. + * \todo Make this dynamic. + */ +#define EC_MAX_IDN_DATA_SIZE 1024 + +typedef struct { + // inputs + uint32_t config_index; + uint32_t idn_pos; + + // outputs + uint8_t drive_no; + uint16_t idn; + ec_al_state_t state; + size_t size; + uint8_t data[EC_MAX_IDN_DATA_SIZE]; +} ec_ioctl_config_idn_t; + +/****************************************************************************/ + +/** Maximum size for key. + */ +#define EC_MAX_FLAG_KEY_SIZE 128 + +typedef struct { + // inputs + uint32_t config_index; + uint32_t flag_pos; + + // outputs + char key[EC_MAX_FLAG_KEY_SIZE]; + int32_t value; +} ec_ioctl_config_flag_t; + +/****************************************************************************/ + +#ifdef EC_EOE + +typedef struct { + // input + uint16_t eoe_index; + + // outputs + char name[EC_DATAGRAM_NAME_SIZE]; + uint16_t slave_position; + uint8_t open; + uint32_t rx_bytes; + uint32_t rx_rate; + uint32_t tx_bytes; + uint32_t tx_rate; + uint32_t tx_queued_frames; + uint32_t tx_queue_size; +} ec_ioctl_eoe_handler_t; + +#endif + +/****************************************************************************/ + +#define EC_ETH_ALEN 6 +#ifdef ETH_ALEN +#if ETH_ALEN != EC_ETH_ALEN +#error Ethernet address length mismatch +#endif +#endif + +typedef struct { + // input + uint16_t slave_position; + uint16_t config_index; // alternatively + + uint8_t mac_address_included; + uint8_t ip_address_included; + uint8_t subnet_mask_included; + uint8_t gateway_included; + uint8_t dns_included; + uint8_t name_included; + + unsigned char mac_address[EC_ETH_ALEN]; + struct in_addr ip_address; + struct in_addr subnet_mask; + struct in_addr gateway; + struct in_addr dns; + char name[EC_MAX_HOSTNAME_SIZE]; + + // output + uint16_t result; +} ec_ioctl_eoe_ip_t; + +/*****************************************************************************/ + +typedef struct { + // outputs + void *process_data; + size_t process_data_size; +} ec_ioctl_master_activate_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint16_t pdo_index; + uint16_t entry_index; + uint8_t entry_subindex; + uint8_t entry_bit_length; +} ec_ioctl_add_pdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint16_t entry_index; + uint8_t entry_subindex; + uint32_t domain_index; + + // outputs + unsigned int bit_position; +} ec_ioctl_reg_pdo_entry_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint32_t sync_index; + uint32_t pdo_pos; + uint32_t entry_pos; + uint32_t domain_index; + + // outputs + unsigned int bit_position; +} ec_ioctl_reg_pdo_pos_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint16_t index; + uint8_t subindex; + const uint8_t *data; + size_t size; + uint8_t complete_access; +} ec_ioctl_sc_sdo_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + size_t size; + uint8_t *target; + + // outputs + int32_t overruns; +} ec_ioctl_sc_emerg_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // outputs + ec_slave_config_state_t *state; +} ec_ioctl_sc_state_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + uint8_t drive_no; + uint16_t idn; + ec_al_state_t al_state; + const uint8_t *data; + size_t size; +} ec_ioctl_sc_idn_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + size_t key_size; + char *key; + int32_t value; +} ec_ioctl_sc_flag_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + ec_al_state_t from_state; + ec_al_state_t to_state; + uint32_t timeout_ms; +} ec_ioctl_sc_state_timeout_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t domain_index; + + // outputs + ec_domain_state_t *state; +} ec_ioctl_domain_state_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // inputs/outputs + uint32_t request_index; + uint16_t sdo_index; + uint8_t sdo_subindex; + size_t size; + uint8_t *data; + uint32_t timeout; + ec_request_state_t state; +} ec_ioctl_sdo_request_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // inputs/outputs + uint32_t request_index; + uint8_t drive_no; + uint16_t idn; + size_t size; + uint8_t *data; + uint32_t timeout; + ec_request_state_t state; +} ec_ioctl_soe_request_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + size_t mem_size; + + // inputs/outputs + uint32_t request_index; + uint8_t *data; + ec_request_state_t state; + uint8_t new_data; + uint16_t address; + size_t transfer_size; +} ec_ioctl_reg_request_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t config_index; + + // inputs/outputs + uint32_t voe_index; + uint32_t *vendor_id; + uint16_t *vendor_type; + size_t size; + uint8_t *data; + ec_request_state_t state; +} ec_ioctl_voe_t; + +/****************************************************************************/ + +typedef struct { + // inputs + uint32_t dev_idx; + + // outputs + ec_master_link_state_t *state; +} ec_ioctl_link_state_t; + +/****************************************************************************/ + +#ifdef __KERNEL__ + +/** Context data structure for file handles. + */ +typedef struct { + unsigned int writable; /**< Device was opened with write permission. */ + unsigned int requested; /**< Master was requested via this file handle. */ + uint8_t *process_data; /**< Total process data area. */ + size_t process_data_size; /**< Size of the \a process_data. */ +} ec_ioctl_context_t; + +long ec_ioctl(ec_master_t *, ec_ioctl_context_t *, unsigned int, + void __user *); + +#ifdef EC_RTDM + +long ec_ioctl_rtdm_rt(ec_master_t *, ec_ioctl_context_t *, unsigned int, + void __user *); +long ec_ioctl_rtdm_nrt(ec_master_t *, ec_ioctl_context_t *, unsigned int, + void __user *); + +#ifndef EC_RTDM_XENOMAI_V3 +int ec_rtdm_mmap(ec_ioctl_context_t *, void **); +#endif + +#endif + +#endif + +/****************************************************************************/ + +/** \endcond */ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/mailbox.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/mailbox.c @@ -0,0 +1,203 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Mailbox functionality. +*/ + +/****************************************************************************/ + +#include +#include + +#include "mailbox.h" +#include "datagram.h" +#include "master.h" + +/****************************************************************************/ + +/** + Prepares a mailbox-send datagram. + \return Pointer to mailbox datagram data, or ERR_PTR() code. +*/ + +uint8_t *ec_slave_mbox_prepare_send(const ec_slave_t *slave, /**< slave */ + ec_datagram_t *datagram, /**< datagram */ + uint8_t type, /**< mailbox protocol */ + size_t size /**< size of the data */ + ) +{ + size_t total_size; + int ret; + + if (unlikely(!slave->sii.mailbox_protocols)) { + EC_SLAVE_ERR(slave, "Slave does not support mailbox" + " communication!\n"); + return ERR_PTR(-EPROTONOSUPPORT); + } + + total_size = EC_MBOX_HEADER_SIZE + size; + + if (unlikely(total_size > slave->configured_rx_mailbox_size)) { + EC_SLAVE_ERR(slave, "Data size (%zu) does not fit in mailbox (%u)!\n", + total_size, slave->configured_rx_mailbox_size); + return ERR_PTR(-ENOBUFS); + } + + ret = ec_datagram_fpwr(datagram, slave->station_address, + slave->configured_rx_mailbox_offset, + slave->configured_rx_mailbox_size); + if (ret) + return ERR_PTR(ret); + + EC_WRITE_U16(datagram->data, size); // mailbox service data length + EC_WRITE_U16(datagram->data + 2, slave->station_address); // station addr. + EC_WRITE_U8 (datagram->data + 4, 0x00); // channel & priority + EC_WRITE_U8 (datagram->data + 5, type); // underlying protocol type + + return datagram->data + EC_MBOX_HEADER_SIZE; +} + +/****************************************************************************/ + +/** + Prepares a datagram for checking the mailbox state. + \todo Determine sync manager used for receive mailbox + \return 0 in case of success, else < 0 +*/ + +int ec_slave_mbox_prepare_check(const ec_slave_t *slave, /**< slave */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + int ret = ec_datagram_fprd(datagram, slave->station_address, 0x808, 8); + if (ret) + return ret; + + ec_datagram_zero(datagram); + return 0; +} + +/****************************************************************************/ + +/** + Processes a mailbox state checking datagram. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_mbox_check(const ec_datagram_t *datagram /**< datagram */) +{ + return EC_READ_U8(datagram->data + 5) & 8 ? 1 : 0; +} + +/****************************************************************************/ + +/** + Prepares a datagram to fetch mailbox data. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_mbox_prepare_fetch(const ec_slave_t *slave, /**< slave */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + int ret = ec_datagram_fprd(datagram, slave->station_address, + slave->configured_tx_mailbox_offset, + slave->configured_tx_mailbox_size); + if (ret) + return ret; + + ec_datagram_zero(datagram); + return 0; +} + +/****************************************************************************/ + +/** + Mailbox error codes. +*/ + +const ec_code_msg_t mbox_error_messages[] = { + {0x00000001, "MBXERR_SYNTAX"}, + {0x00000002, "MBXERR_UNSUPPORTEDPROTOCOL"}, + {0x00000003, "MBXERR_INVAILDCHANNEL"}, + {0x00000004, "MBXERR_SERVICENOTSUPPORTED"}, + {0x00000005, "MBXERR_INVALIDHEADER"}, + {0x00000006, "MBXERR_SIZETOOSHORT"}, + {0x00000007, "MBXERR_NOMOREMEMORY"}, + {0x00000008, "MBXERR_INVALIDSIZE"}, + {} +}; + +/****************************************************************************/ + +/** Processes received mailbox data. + * + * \return Pointer to the received data, or ERR_PTR() code. + */ +uint8_t *ec_slave_mbox_fetch(const ec_slave_t *slave, /**< slave */ + const ec_datagram_t *datagram, /**< datagram */ + uint8_t *type, /**< expected mailbox protocol */ + size_t *size /**< size of the received data */ + ) +{ + size_t data_size; + + data_size = EC_READ_U16(datagram->data); + + if (data_size + EC_MBOX_HEADER_SIZE > slave->configured_tx_mailbox_size) { + EC_SLAVE_ERR(slave, "Corrupt mailbox response received!\n"); + ec_print_data(datagram->data, slave->configured_tx_mailbox_size); + return ERR_PTR(-EPROTO); + } + + *type = EC_READ_U8(datagram->data + 5) & 0x0F; + *size = data_size; + + if (*type == 0x00) { + const ec_code_msg_t *mbox_msg; + uint16_t code = EC_READ_U16(datagram->data + 8); + + EC_SLAVE_ERR(slave, "Mailbox error response received - "); + + for (mbox_msg = mbox_error_messages; mbox_msg->code; mbox_msg++) { + if (mbox_msg->code != code) + continue; + printk(KERN_CONT "Code 0x%04X: \"%s\".\n", + mbox_msg->code, mbox_msg->message); + break; + } + + if (!mbox_msg->code) { + printk(KERN_CONT "Unknown error reply code 0x%04X.\n", code); + } + + if (slave->master->debug_level) + ec_print_data(datagram->data + EC_MBOX_HEADER_SIZE, data_size); + + return ERR_PTR(-EPROTO); + } + + return datagram->data + EC_MBOX_HEADER_SIZE; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/mailbox.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/mailbox.h @@ -0,0 +1,64 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Mailbox functionality. +*/ + +/****************************************************************************/ + +#ifndef __EC_MAILBOX_H__ +#define __EC_MAILBOX_H__ + +#include "slave.h" + +/****************************************************************************/ + +/** Size of the mailbox header. + */ +#define EC_MBOX_HEADER_SIZE 6 + +/** Mailbox types. + * + * These are used in the 'Type' field of the mailbox header. + */ +enum { + EC_MBOX_TYPE_EOE = 0x02, + EC_MBOX_TYPE_COE = 0x03, + EC_MBOX_TYPE_FOE = 0x04, + EC_MBOX_TYPE_SOE = 0x05, + EC_MBOX_TYPE_VOE = 0x0f, +}; + +/****************************************************************************/ + +uint8_t *ec_slave_mbox_prepare_send(const ec_slave_t *, ec_datagram_t *, + uint8_t, size_t); +int ec_slave_mbox_prepare_check(const ec_slave_t *, ec_datagram_t *); +int ec_slave_mbox_check(const ec_datagram_t *); +int ec_slave_mbox_prepare_fetch(const ec_slave_t *, ec_datagram_t *); +uint8_t *ec_slave_mbox_fetch(const ec_slave_t *, const ec_datagram_t *, + uint8_t *, size_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/master.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/master.c @@ -0,0 +1,3350 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2020 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * vim: expandtab + * + ****************************************************************************/ + +/** + \file + EtherCAT master methods. +*/ + +/****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "globals.h" +#include "slave.h" +#include "slave_config.h" +#include "device.h" +#include "datagram.h" + +#ifdef EC_EOE +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) +#include // struct sched_param +#include // sched_setscheduler +#endif +#include "ethernet.h" +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0) || \ + (defined(CONFIG_PREEMPT_RT_FULL) && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) +# define ec_rt_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock) +#else +# define ec_rt_lock_interruptible(lock) \ + rt_mutex_lock_interruptible(lock, 0) +#endif + +#include "master.h" + +/****************************************************************************/ + +/** Set to 1 to enable external datagram injection debugging. + */ +#define DEBUG_INJECT 0 + +/** Always output corrupted frames. + */ +#define FORCE_OUTPUT_CORRUPTED 0 + +/** SDO injection timeout in microseconds. */ +#define EC_SDO_INJECTION_TIMEOUT 10000 + +#ifdef EC_HAVE_CYCLES + +/** Frame timeout in cycles. + */ +static cycles_t timeout_cycles; + +/** Timeout for external datagram injection [cycles]. + */ +static cycles_t ext_injection_timeout_cycles; + +#else + +/** Frame timeout in jiffies. + */ +static unsigned long timeout_jiffies; + +/** Timeout for external datagram injection [jiffies]. + */ +static unsigned long ext_injection_timeout_jiffies; + +#endif + +/** List of intervals for statistics [s]. + */ +const unsigned int rate_intervals[] = { + 1, 10, 60 +}; + +/****************************************************************************/ + +void ec_master_clear_config(ec_master_t *); +void ec_master_clear_slave_configs(ec_master_t *); +void ec_master_clear_domains(ec_master_t *); +int ec_master_thread_start(ec_master_t *, int (*)(void *), const char *); +void ec_master_thread_stop(ec_master_t *); +void ec_master_inject_external_datagrams(ec_master_t *); +ec_datagram_t *ec_master_get_external_datagram(ec_master_t *); +void ec_master_exec_slave_fsms(ec_master_t *); +void ec_master_send_datagrams(ec_master_t *, ec_device_index_t); +int ec_master_calc_topology_rec(ec_master_t *, ec_slave_t *, unsigned int *); +void ec_master_calc_topology(ec_master_t *); +void ec_master_calc_transmission_delays(ec_master_t *); +static int ec_master_idle_thread(void *); +static int ec_master_operation_thread(void *); +#ifdef EC_EOE +static int ec_master_eoe_thread(void *); +#endif +void ec_master_find_dc_ref_clock(ec_master_t *); +void ec_master_clear_device_stats(ec_master_t *); +void ec_master_update_device_stats(ec_master_t *); +void ec_master_nanosleep(const unsigned long); +static void sc_reset_task_kicker(struct irq_work *work); +static void sc_reset_task(struct work_struct *work); + +/****************************************************************************/ + +/** Static variables initializer. +*/ +void ec_master_init_static(void) +{ +#ifdef EC_HAVE_CYCLES + timeout_cycles = (cycles_t) EC_IO_TIMEOUT /* us */ * (cpu_khz / 1000); + ext_injection_timeout_cycles = + (cycles_t) EC_SDO_INJECTION_TIMEOUT /* us */ * (cpu_khz / 1000); +#else + // one jiffy may always elapse between time measurement + timeout_jiffies = max(EC_IO_TIMEOUT * HZ / 1000000, 1); + ext_injection_timeout_jiffies = + max(EC_SDO_INJECTION_TIMEOUT * HZ / 1000000, 1); +#endif +} + +/****************************************************************************/ + +/** + Master constructor. + \return 0 in case of success, else < 0 +*/ + +int ec_master_init(ec_master_t *master, /**< EtherCAT master */ + unsigned int index, /**< master index */ + const uint8_t *main_mac, /**< MAC address of main device */ + const uint8_t *backup_mac, /**< MAC address of backup device */ + dev_t device_number, /**< Character device number. */ + struct class *class, /**< Device class. */ + unsigned int debug_level, /**< Debug level (module parameter). */ + unsigned int run_on_cpu /**< bind created kernel threads to a cpu */ + ) +{ + int ret; + unsigned int dev_idx, i; + + master->index = index; + master->reserved = 0; + + sema_init(&master->master_sem, 1); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < EC_MAX_NUM_DEVICES; dev_idx++) { + master->macs[dev_idx] = NULL; + } + + master->macs[EC_DEVICE_MAIN] = main_mac; + +#if EC_MAX_NUM_DEVICES > 1 + master->macs[EC_DEVICE_BACKUP] = backup_mac; + master->num_devices = 1 + !ec_mac_is_zero(backup_mac); +#else + if (!ec_mac_is_zero(backup_mac)) { + EC_MASTER_WARN(master, "Ignoring backup MAC address!"); + } +#endif + + ec_master_clear_device_stats(master); + + sema_init(&master->device_sem, 1); + + master->phase = EC_ORPHANED; + master->active = 0; + master->config_changed = 0; + master->injection_seq_fsm = 0; + master->injection_seq_rt = 0; + + master->slaves = NULL; + master->slave_count = 0; + + INIT_LIST_HEAD(&master->configs); + INIT_LIST_HEAD(&master->domains); + + master->app_time = 0ULL; + master->dc_ref_time = 0ULL; + + master->scan_busy = 0; + master->scan_index = 0; + master->allow_scan = 1; + sema_init(&master->scan_sem, 1); + init_waitqueue_head(&master->scan_queue); + + master->config_busy = 0; + sema_init(&master->config_sem, 1); + init_waitqueue_head(&master->config_queue); + + INIT_LIST_HEAD(&master->datagram_queue); + master->datagram_index = 0; + + INIT_LIST_HEAD(&master->ext_datagram_queue); + sema_init(&master->ext_queue_sem, 1); + + master->ext_ring_idx_rt = 0; + master->ext_ring_idx_fsm = 0; + + // init external datagram ring + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_t *datagram = &master->ext_datagram_ring[i]; + ec_datagram_init(datagram); + snprintf(datagram->name, EC_DATAGRAM_NAME_SIZE, "ext-%u", i); + } + + // send interval in IDLE phase + ec_master_set_send_interval(master, 1000000 / HZ); + + master->fsm_slave = NULL; + INIT_LIST_HEAD(&master->fsm_exec_list); + master->fsm_exec_count = 0U; + + master->debug_level = debug_level; + master->run_on_cpu = run_on_cpu; + master->stats.timeouts = 0; + master->stats.corrupted = 0; + master->stats.unmatched = 0; + master->stats.output_jiffies = 0; + + master->thread = NULL; + +#ifdef EC_EOE + master->eoe_thread = NULL; + INIT_LIST_HEAD(&master->eoe_handlers); +#endif + + rt_mutex_init(&master->io_mutex); + master->send_cb = NULL; + master->receive_cb = NULL; + master->cb_data = NULL; + master->app_send_cb = NULL; + master->app_receive_cb = NULL; + master->app_cb_data = NULL; + + INIT_LIST_HEAD(&master->sii_requests); + INIT_LIST_HEAD(&master->emerg_reg_requests); + + init_waitqueue_head(&master->request_queue); + + // init devices + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ret = ec_device_init(&master->devices[dev_idx], master); + if (ret < 0) { + goto out_clear_devices; + } + } + + // init state machine datagram + ec_datagram_init(&master->fsm_datagram); + snprintf(master->fsm_datagram.name, EC_DATAGRAM_NAME_SIZE, "master-fsm"); + ret = ec_datagram_prealloc(&master->fsm_datagram, EC_MAX_DATA_SIZE); + if (ret < 0) { + ec_datagram_clear(&master->fsm_datagram); + EC_MASTER_ERR(master, "Failed to allocate FSM datagram.\n"); + goto out_clear_devices; + } + + // create state machine object + ec_fsm_master_init(&master->fsm, master, &master->fsm_datagram); + + // alloc external datagram ring + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_t *datagram = &master->ext_datagram_ring[i]; + ret = ec_datagram_prealloc(datagram, EC_MAX_DATA_SIZE); + if (ret) { + EC_MASTER_ERR(master, "Failed to allocate external" + " datagram %u.\n", i); + goto out_clear_ext_datagrams; + } + } + + // init reference sync datagram + ec_datagram_init(&master->ref_sync_datagram); + snprintf(master->ref_sync_datagram.name, EC_DATAGRAM_NAME_SIZE, + "refsync"); + ret = ec_datagram_prealloc(&master->ref_sync_datagram, 4); + if (ret < 0) { + ec_datagram_clear(&master->ref_sync_datagram); + EC_MASTER_ERR(master, "Failed to allocate reference" + " synchronisation datagram.\n"); + goto out_clear_ext_datagrams; + } + + // init sync datagram + ec_datagram_init(&master->sync_datagram); + snprintf(master->sync_datagram.name, EC_DATAGRAM_NAME_SIZE, "sync"); + ret = ec_datagram_prealloc(&master->sync_datagram, 4); + if (ret < 0) { + ec_datagram_clear(&master->sync_datagram); + EC_MASTER_ERR(master, "Failed to allocate" + " synchronisation datagram.\n"); + goto out_clear_ref_sync; + } + + // init sync monitor datagram + ec_datagram_init(&master->sync_mon_datagram); + snprintf(master->sync_mon_datagram.name, EC_DATAGRAM_NAME_SIZE, + "syncmon"); + ret = ec_datagram_brd(&master->sync_mon_datagram, 0x092c, 4); + if (ret < 0) { + ec_datagram_clear(&master->sync_mon_datagram); + EC_MASTER_ERR(master, "Failed to allocate sync" + " monitoring datagram.\n"); + goto out_clear_sync; + } + + master->dc_ref_config = NULL; + master->dc_ref_clock = NULL; + + INIT_WORK(&master->sc_reset_work, sc_reset_task); + init_irq_work(&master->sc_reset_work_kicker, sc_reset_task_kicker); + + // init character device + ret = ec_cdev_init(&master->cdev, master, device_number); + if (ret) + goto out_clear_sync_mon; + + master->class_device = device_create(class, NULL, + MKDEV(MAJOR(device_number), master->index), NULL, + "EtherCAT%u", master->index); + if (IS_ERR(master->class_device)) { + EC_MASTER_ERR(master, "Failed to create class device!\n"); + ret = PTR_ERR(master->class_device); + goto out_clear_cdev; + } + +#ifdef EC_RTDM + // init RTDM device + ret = ec_rtdm_dev_init(&master->rtdm_dev, master); + if (ret) { + goto out_unregister_class_device; + } +#endif + + return 0; + +#ifdef EC_RTDM +out_unregister_class_device: + device_unregister(master->class_device); +#endif +out_clear_cdev: + ec_cdev_clear(&master->cdev); +out_clear_sync_mon: + ec_datagram_clear(&master->sync_mon_datagram); +out_clear_sync: + ec_datagram_clear(&master->sync_datagram); +out_clear_ref_sync: + ec_datagram_clear(&master->ref_sync_datagram); +out_clear_ext_datagrams: + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_clear(&master->ext_datagram_ring[i]); + } + ec_fsm_master_clear(&master->fsm); + ec_datagram_clear(&master->fsm_datagram); +out_clear_devices: + for (; dev_idx > 0; dev_idx--) { + ec_device_clear(&master->devices[dev_idx - 1]); + } + return ret; +} + +/****************************************************************************/ + +/** Destructor. +*/ +void ec_master_clear( + ec_master_t *master /**< EtherCAT master */ + ) +{ + unsigned int dev_idx, i; + +#ifdef EC_RTDM + ec_rtdm_dev_clear(&master->rtdm_dev); +#endif + + device_unregister(master->class_device); + + ec_cdev_clear(&master->cdev); + + irq_work_sync(&master->sc_reset_work_kicker); + cancel_work_sync(&master->sc_reset_work); + +#ifdef EC_EOE + ec_master_clear_eoe_handlers(master); +#endif + ec_master_clear_domains(master); + ec_master_clear_slave_configs(master); + ec_master_clear_slaves(master); + + ec_datagram_clear(&master->sync_mon_datagram); + ec_datagram_clear(&master->sync_datagram); + ec_datagram_clear(&master->ref_sync_datagram); + + for (i = 0; i < EC_EXT_RING_SIZE; i++) { + ec_datagram_clear(&master->ext_datagram_ring[i]); + } + + ec_fsm_master_clear(&master->fsm); + ec_datagram_clear(&master->fsm_datagram); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ec_device_clear(&master->devices[dev_idx]); + } +} + +/****************************************************************************/ + +#ifdef EC_EOE +/** Clear and free all EoE handlers. + */ +void ec_master_clear_eoe_handlers( + ec_master_t *master /**< EtherCAT master */ + ) +{ + ec_eoe_t *eoe, *next; + + list_for_each_entry_safe(eoe, next, &master->eoe_handlers, list) { + list_del(&eoe->list); + ec_eoe_clear(eoe); + kfree(eoe); + } +} +#endif + +/****************************************************************************/ + +/** Clear all slave configurations. + */ +void ec_master_clear_slave_configs(ec_master_t *master) +{ + ec_slave_config_t *sc, *next; + + master->dc_ref_config = NULL; + master->fsm.sdo_request = NULL; // mark sdo_request as invalid + + list_for_each_entry_safe(sc, next, &master->configs, list) { + list_del(&sc->list); + ec_slave_config_clear(sc); + kfree(sc); + } +} + +/****************************************************************************/ + +/** Clear all slaves. + */ +void ec_master_clear_slaves(ec_master_t *master) +{ + ec_slave_t *slave; + + master->dc_ref_clock = NULL; + + // External requests are obsolete, so we wake pending waiters and remove + // them from the list. + + while (!list_empty(&master->sii_requests)) { + ec_sii_write_request_t *request = + list_entry(master->sii_requests.next, + ec_sii_write_request_t, list); + list_del_init(&request->list); // dequeue + EC_MASTER_WARN(master, "Discarding SII request, slave %u about" + " to be deleted.\n", request->slave->ring_position); + request->state = EC_INT_REQUEST_FAILURE; + wake_up_all(&master->request_queue); + } + + master->fsm_slave = NULL; + INIT_LIST_HEAD(&master->fsm_exec_list); + master->fsm_exec_count = 0; + + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_slave_clear(slave); + } + + if (master->slaves) { + kfree(master->slaves); + master->slaves = NULL; + } + + master->slave_count = 0; +} + +/****************************************************************************/ + +/** Clear all domains. + */ +void ec_master_clear_domains(ec_master_t *master) +{ + ec_domain_t *domain, *next; + + list_for_each_entry_safe(domain, next, &master->domains, list) { + list_del(&domain->list); + ec_domain_clear(domain); + kfree(domain); + } +} + +/****************************************************************************/ + +/** Clear the configuration applied by the application. + */ +void ec_master_clear_config( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + down(&master->master_sem); + ec_master_clear_domains(master); + ec_master_clear_slave_configs(master); + up(&master->master_sem); +} + +/****************************************************************************/ + +/** Internal sending callback. + */ +void ec_master_internal_send_cb( + void *cb_data /**< Callback data. */ + ) +{ + ec_master_t *master = (ec_master_t *) cb_data; + if (ec_rt_lock_interruptible(&master->io_mutex)) + return; + ecrt_master_send_ext(master); + rt_mutex_unlock(&master->io_mutex); +} + +/****************************************************************************/ + +/** Internal receiving callback. + */ +void ec_master_internal_receive_cb( + void *cb_data /**< Callback data. */ + ) +{ + ec_master_t *master = (ec_master_t *) cb_data; + if (ec_rt_lock_interruptible(&master->io_mutex)) + return; + ecrt_master_receive(master); + rt_mutex_unlock(&master->io_mutex); +} + +/****************************************************************************/ + +/** Starts the master thread. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_master_thread_start( + ec_master_t *master, /**< EtherCAT master */ + int (*thread_func)(void *), /**< thread function to start */ + const char *name /**< Thread name. */ + ) +{ + EC_MASTER_INFO(master, "Starting %s thread.\n", name); + master->thread = kthread_create(thread_func, master, name); + if (IS_ERR(master->thread)) { + int err = (int) PTR_ERR(master->thread); + EC_MASTER_ERR(master, "Failed to start master thread (error %i)!\n", + err); + master->thread = NULL; + return err; + } + if (0xffffffff != master->run_on_cpu) { + EC_MASTER_INFO(master, " binding thread to cpu %u\n",master->run_on_cpu); + kthread_bind(master->thread,master->run_on_cpu); + } + /* Ignoring return value of wake_up_process */ + (void) wake_up_process(master->thread); + + return 0; +} + +/****************************************************************************/ + +/** Stops the master thread. + */ +void ec_master_thread_stop( + ec_master_t *master /**< EtherCAT master */ + ) +{ + unsigned long sleep_jiffies; + + if (!master->thread) { + EC_MASTER_WARN(master, "%s(): Already finished!\n", __func__); + return; + } + + EC_MASTER_DBG(master, 1, "Stopping master thread.\n"); + + kthread_stop(master->thread); + master->thread = NULL; + EC_MASTER_INFO(master, "Master thread exited.\n"); + + if (master->fsm_datagram.state != EC_DATAGRAM_SENT) { + return; + } + + // wait for FSM datagram + sleep_jiffies = max(HZ / 100, 1); // 10 ms, at least 1 jiffy + schedule_timeout(sleep_jiffies); +} + +/****************************************************************************/ + +/** Transition function from ORPHANED to IDLE phase. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_master_enter_idle_phase( + ec_master_t *master /**< EtherCAT master */ + ) +{ + int ret; + ec_device_index_t dev_idx; + + EC_MASTER_DBG(master, 1, "ORPHANED -> IDLE.\n"); + + master->send_cb = ec_master_internal_send_cb; + master->receive_cb = ec_master_internal_receive_cb; + master->cb_data = master; + + master->phase = EC_IDLE; + + // reset number of responding slaves to trigger scanning + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + master->fsm.slaves_responding[dev_idx] = 0; + } + + ret = ec_master_thread_start(master, ec_master_idle_thread, + "EtherCAT-IDLE"); + if (ret) + master->phase = EC_ORPHANED; + + return ret; +} + +/****************************************************************************/ + +/** Transition function from IDLE to ORPHANED phase. + */ +void ec_master_leave_idle_phase(ec_master_t *master /**< EtherCAT master */) +{ + EC_MASTER_DBG(master, 1, "IDLE -> ORPHANED.\n"); + + master->phase = EC_ORPHANED; + +#ifdef EC_EOE + ec_master_eoe_stop(master); +#endif + ec_master_thread_stop(master); + + down(&master->master_sem); + ec_master_clear_slaves(master); + up(&master->master_sem); + + ec_fsm_master_reset(&master->fsm); +} + +/****************************************************************************/ + +/** Transition function from IDLE to OPERATION phase. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_master_enter_operation_phase( + ec_master_t *master /**< EtherCAT master */ + ) +{ + int ret = 0; + ec_slave_t *slave; + + EC_MASTER_DBG(master, 1, "IDLE -> OPERATION.\n"); + + down(&master->config_sem); + if (master->config_busy) { + up(&master->config_sem); + + // wait for slave configuration to complete + ret = wait_event_interruptible(master->config_queue, + !master->config_busy); + if (ret) { + EC_MASTER_INFO(master, "Finishing slave configuration" + " interrupted by signal.\n"); + goto out_return; + } + + EC_MASTER_DBG(master, 1, "Waiting for pending slave" + " configuration returned.\n"); + } else { + up(&master->config_sem); + } + + down(&master->scan_sem); + master->allow_scan = 0; // 'lock' the slave list + if (!master->scan_busy) { + up(&master->scan_sem); + } else { + up(&master->scan_sem); + + // wait for slave scan to complete + ret = wait_event_interruptible(master->scan_queue, + !master->scan_busy); + if (ret) { + EC_MASTER_INFO(master, "Waiting for slave scan" + " interrupted by signal.\n"); + goto out_allow; + } + + EC_MASTER_DBG(master, 1, "Waiting for pending" + " slave scan returned.\n"); + } + + // set states for all slaves + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_slave_request_state(slave, EC_SLAVE_STATE_PREOP); + } + + master->phase = EC_OPERATION; + master->app_send_cb = NULL; + master->app_receive_cb = NULL; + master->app_cb_data = NULL; + return ret; + +out_allow: + master->allow_scan = 1; +out_return: + return ret; +} + +/****************************************************************************/ + +/** Transition function from OPERATION to IDLE phase. + */ +void ec_master_leave_operation_phase( + ec_master_t *master /**< EtherCAT master */ + ) +{ + if (master->active) { + ecrt_master_deactivate(master); // also clears config + } else { + ec_master_clear_config(master); + } + + /* Re-allow scanning for IDLE phase. */ + master->allow_scan = 1; + + EC_MASTER_DBG(master, 1, "OPERATION -> IDLE.\n"); + + master->phase = EC_IDLE; +} + +/****************************************************************************/ + +/** Injects external datagrams that fit into the datagram queue. + */ +void ec_master_inject_external_datagrams( + ec_master_t *master /**< EtherCAT master */ + ) +{ + ec_datagram_t *datagram; + size_t queue_size = 0, new_queue_size = 0; +#if DEBUG_INJECT + unsigned int datagram_count = 0; +#endif + + if (master->ext_ring_idx_rt == master->ext_ring_idx_fsm) { + // nothing to inject + return; + } + + list_for_each_entry(datagram, &master->datagram_queue, queue) { + if (datagram->state == EC_DATAGRAM_QUEUED) { + queue_size += datagram->data_size; + } + } + +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Injecting datagrams, queue_size=%zu\n", + queue_size); +#endif + + while (master->ext_ring_idx_rt != master->ext_ring_idx_fsm) { + datagram = &master->ext_datagram_ring[master->ext_ring_idx_rt]; + + if (datagram->state != EC_DATAGRAM_INIT) { + // skip datagram + master->ext_ring_idx_rt = + (master->ext_ring_idx_rt + 1) % EC_EXT_RING_SIZE; + continue; + } + + new_queue_size = queue_size + datagram->data_size; + if (new_queue_size <= master->max_queue_size) { +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Injecting datagram %s" + " size=%zu, queue_size=%zu\n", datagram->name, + datagram->data_size, new_queue_size); + datagram_count++; +#endif +#ifdef EC_HAVE_CYCLES + datagram->cycles_sent = 0; +#endif + datagram->jiffies_sent = 0; + ec_master_queue_datagram(master, datagram); + queue_size = new_queue_size; + } + else if (datagram->data_size > master->max_queue_size) { + datagram->state = EC_DATAGRAM_ERROR; + EC_MASTER_ERR(master, "External datagram %s is too large," + " size=%zu, max_queue_size=%zu\n", + datagram->name, datagram->data_size, + master->max_queue_size); + } + else { // datagram does not fit in the current cycle +#ifdef EC_HAVE_CYCLES + cycles_t cycles_now = get_cycles(); + + if (cycles_now - datagram->cycles_sent + > ext_injection_timeout_cycles) +#else + if (jiffies - datagram->jiffies_sent + > ext_injection_timeout_jiffies) +#endif + { +#if defined EC_RT_SYSLOG || DEBUG_INJECT + unsigned int time_us; +#endif + + datagram->state = EC_DATAGRAM_ERROR; + +#if defined EC_RT_SYSLOG || DEBUG_INJECT +#ifdef EC_HAVE_CYCLES + time_us = (unsigned int) + ((cycles_now - datagram->cycles_sent) * 1000LL) + / cpu_khz; +#else + time_us = (unsigned int) + ((jiffies - datagram->jiffies_sent) * 1000000 / HZ); +#endif + EC_MASTER_ERR(master, "Timeout %u us: Injecting" + " external datagram %s size=%zu," + " max_queue_size=%zu\n", time_us, datagram->name, + datagram->data_size, master->max_queue_size); +#endif + } + else { +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Deferred injecting" + " external datagram %s size=%u, queue_size=%u\n", + datagram->name, datagram->data_size, queue_size); +#endif + break; + } + } + + master->ext_ring_idx_rt = + (master->ext_ring_idx_rt + 1) % EC_EXT_RING_SIZE; + } + +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Injected %u datagrams.\n", datagram_count); +#endif +} + +/****************************************************************************/ + +/** Sets the expected interval between calls to ecrt_master_send + * and calculates the maximum amount of data to queue. + */ +void ec_master_set_send_interval( + ec_master_t *master, /**< EtherCAT master */ + unsigned int send_interval /**< Send interval */ + ) +{ + master->send_interval = send_interval; + master->max_queue_size = + (send_interval * 1000) / EC_BYTE_TRANSMISSION_TIME_NS; + master->max_queue_size -= master->max_queue_size / 10; +} + +/****************************************************************************/ + +/** Searches for a free datagram in the external datagram ring. + * + * \return Next free datagram, or NULL. + */ +ec_datagram_t *ec_master_get_external_datagram( + ec_master_t *master /**< EtherCAT master */ + ) +{ + if ((master->ext_ring_idx_fsm + 1) % EC_EXT_RING_SIZE != + master->ext_ring_idx_rt) { + ec_datagram_t *datagram = + &master->ext_datagram_ring[master->ext_ring_idx_fsm]; + return datagram; + } + else { + return NULL; + } +} + +/****************************************************************************/ + +/** Places a datagram in the datagram queue. + */ +void ec_master_queue_datagram( + ec_master_t *master, /**< EtherCAT master */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + ec_datagram_t *queued_datagram; + + /* It is possible, that a datagram in the queue is re-initialized with the + * ec_datagram_() methods and then shall be queued with this method. + * In that case, the state is already reset to EC_DATAGRAM_INIT. Check if + * the datagram is queued to avoid duplicate queuing (which results in an + * infinite loop!). Set the state to EC_DATAGRAM_QUEUED again, probably + * causing an unmatched datagram. */ + list_for_each_entry(queued_datagram, &master->datagram_queue, queue) { + if (queued_datagram == datagram) { + datagram->skip_count++; +#ifdef EC_RT_SYSLOG + EC_MASTER_DBG(master, 1, + "Datagram %p already queued (skipping).\n", datagram); +#endif + datagram->state = EC_DATAGRAM_QUEUED; + return; + } + } + + list_add_tail(&datagram->queue, &master->datagram_queue); + datagram->state = EC_DATAGRAM_QUEUED; +} + +/****************************************************************************/ + +/** Places a datagram in the non-application datagram queue. + */ +void ec_master_queue_datagram_ext( + ec_master_t *master, /**< EtherCAT master */ + ec_datagram_t *datagram /**< datagram */ + ) +{ + down(&master->ext_queue_sem); + list_add_tail(&datagram->ext_queue, &master->ext_datagram_queue); + up(&master->ext_queue_sem); +} + +/****************************************************************************/ + +/** Sends the datagrams in the queue for a certain device. + * + */ +void ec_master_send_datagrams( + ec_master_t *master, /**< EtherCAT master */ + ec_device_index_t device_index /**< Device index. */ + ) +{ + ec_datagram_t *datagram, *next; + size_t datagram_size; + uint8_t *frame_data, *cur_data = NULL; + void *follows_word; +#ifdef EC_HAVE_CYCLES + cycles_t cycles_start, cycles_sent, cycles_end; +#endif + unsigned long jiffies_sent; + unsigned int frame_count, more_datagrams_waiting; + struct list_head sent_datagrams; + +#ifdef EC_HAVE_CYCLES + cycles_start = get_cycles(); +#endif + frame_count = 0; + INIT_LIST_HEAD(&sent_datagrams); + + EC_MASTER_DBG(master, 2, "%s(device_index = %u)\n", + __func__, device_index); + + do { + frame_data = NULL; + follows_word = NULL; + more_datagrams_waiting = 0; + + // fill current frame with datagrams + list_for_each_entry(datagram, &master->datagram_queue, queue) { + if (datagram->state != EC_DATAGRAM_QUEUED || + datagram->device_index != device_index) { + continue; + } + + if (!frame_data) { + // fetch pointer to transmit socket buffer + frame_data = + ec_device_tx_data(&master->devices[device_index]); + cur_data = frame_data + EC_FRAME_HEADER_SIZE; + } + + // does the current datagram fit in the frame? + datagram_size = EC_DATAGRAM_HEADER_SIZE + datagram->data_size + + EC_DATAGRAM_FOOTER_SIZE; + if (cur_data - frame_data + datagram_size > ETH_DATA_LEN) { + more_datagrams_waiting = 1; + break; + } + + list_add_tail(&datagram->sent, &sent_datagrams); + datagram->index = master->datagram_index++; + + EC_MASTER_DBG(master, 2, "Adding datagram 0x%02X\n", + datagram->index); + + // set "datagram following" flag in previous datagram + if (follows_word) { + EC_WRITE_U16(follows_word, + EC_READ_U16(follows_word) | 0x8000); + } + + // EtherCAT datagram header + EC_WRITE_U8 (cur_data, datagram->type); + EC_WRITE_U8 (cur_data + 1, datagram->index); + memcpy(cur_data + 2, datagram->address, EC_ADDR_LEN); + EC_WRITE_U16(cur_data + 6, datagram->data_size & 0x7FF); + EC_WRITE_U16(cur_data + 8, 0x0000); + follows_word = cur_data + 6; + cur_data += EC_DATAGRAM_HEADER_SIZE; + + // EtherCAT datagram data + memcpy(cur_data, datagram->data, datagram->data_size); + cur_data += datagram->data_size; + + // EtherCAT datagram footer + EC_WRITE_U16(cur_data, 0x0000); // reset working counter + cur_data += EC_DATAGRAM_FOOTER_SIZE; + } + + if (list_empty(&sent_datagrams)) { + EC_MASTER_DBG(master, 2, "nothing to send.\n"); + break; + } + + // EtherCAT frame header + EC_WRITE_U16(frame_data, ((cur_data - frame_data + - EC_FRAME_HEADER_SIZE) & 0x7FF) | 0x1000); + + // pad frame + while (cur_data - frame_data < ETH_ZLEN - ETH_HLEN) + EC_WRITE_U8(cur_data++, 0x00); + + EC_MASTER_DBG(master, 2, "frame size: %zu\n", cur_data - frame_data); + + // send frame + ec_device_send(&master->devices[device_index], + cur_data - frame_data); +#ifdef EC_HAVE_CYCLES + cycles_sent = get_cycles(); +#endif + jiffies_sent = jiffies; + + // set datagram states and sending timestamps + list_for_each_entry_safe(datagram, next, &sent_datagrams, sent) { + datagram->state = EC_DATAGRAM_SENT; +#ifdef EC_HAVE_CYCLES + datagram->cycles_sent = cycles_sent; +#endif + datagram->jiffies_sent = jiffies_sent; + list_del_init(&datagram->sent); // empty list of sent datagrams + } + + frame_count++; + } + while (more_datagrams_waiting); + +#ifdef EC_HAVE_CYCLES + if (unlikely(master->debug_level > 1)) { + cycles_end = get_cycles(); + EC_MASTER_DBG(master, 0, "%s()" + " sent %u frames in %uus.\n", __func__, frame_count, + (unsigned int) (cycles_end - cycles_start) * 1000 / cpu_khz); + } +#endif +} + +/****************************************************************************/ + +/** Processes a received frame. + * + * This function is called by the network driver for every received frame. + * + * \return 0 in case of success, else < 0 + */ +void ec_master_receive_datagrams( + ec_master_t *master, /**< EtherCAT master */ + ec_device_t *device, /**< EtherCAT device */ + const uint8_t *frame_data, /**< frame data */ + size_t size /**< size of the received data */ + ) +{ + size_t frame_size, data_size; + uint8_t datagram_type, datagram_index; + unsigned int cmd_follows, matched; + const uint8_t *cur_data; + ec_datagram_t *datagram; + + if (unlikely(size < EC_FRAME_HEADER_SIZE)) { + if (master->debug_level || FORCE_OUTPUT_CORRUPTED) { + EC_MASTER_DBG(master, 0, "Corrupted frame received" + " on %s (size %zu < %u byte):\n", + device->dev->name, size, EC_FRAME_HEADER_SIZE); + ec_print_data(frame_data, size); + } + master->stats.corrupted++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + return; + } + + cur_data = frame_data; + + // check length of entire frame + frame_size = EC_READ_U16(cur_data) & 0x07FF; + cur_data += EC_FRAME_HEADER_SIZE; + + if (unlikely(frame_size > size)) { + if (master->debug_level || FORCE_OUTPUT_CORRUPTED) { + EC_MASTER_DBG(master, 0, "Corrupted frame received" + " on %s (invalid frame size %zu for " + "received size %zu):\n", device->dev->name, + frame_size, size); + ec_print_data(frame_data, size); + } + master->stats.corrupted++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + return; + } + + cmd_follows = 1; + while (cmd_follows) { + // process datagram header + datagram_type = EC_READ_U8 (cur_data); + datagram_index = EC_READ_U8 (cur_data + 1); + data_size = EC_READ_U16(cur_data + 6) & 0x07FF; + cmd_follows = EC_READ_U16(cur_data + 6) & 0x8000; + cur_data += EC_DATAGRAM_HEADER_SIZE; + + if (unlikely(cur_data - frame_data + + data_size + EC_DATAGRAM_FOOTER_SIZE > size)) { + if (master->debug_level || FORCE_OUTPUT_CORRUPTED) { + EC_MASTER_DBG(master, 0, "Corrupted frame received" + " on %s (invalid data size %zu):\n", + device->dev->name, data_size); + ec_print_data(frame_data, size); + } + master->stats.corrupted++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + return; + } + + // search for matching datagram in the queue + matched = 0; + list_for_each_entry(datagram, &master->datagram_queue, queue) { + if (datagram->index == datagram_index + && datagram->state == EC_DATAGRAM_SENT + && datagram->type == datagram_type + && datagram->data_size == data_size) { + matched = 1; + break; + } + } + + // no matching datagram was found + if (!matched) { + master->stats.unmatched++; +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); +#endif + + if (unlikely(master->debug_level > 0)) { + EC_MASTER_DBG(master, 0, "UNMATCHED datagram:\n"); + ec_print_data(cur_data - EC_DATAGRAM_HEADER_SIZE, + EC_DATAGRAM_HEADER_SIZE + data_size + + EC_DATAGRAM_FOOTER_SIZE); +#ifdef EC_DEBUG_RING + ec_device_debug_ring_print(&master->devices[EC_DEVICE_MAIN]); +#endif + } + + cur_data += data_size + EC_DATAGRAM_FOOTER_SIZE; + continue; + } + + if (datagram->type != EC_DATAGRAM_APWR && + datagram->type != EC_DATAGRAM_FPWR && + datagram->type != EC_DATAGRAM_BWR && + datagram->type != EC_DATAGRAM_LWR) { + // copy received data into the datagram memory, + // if something has been read + memcpy(datagram->data, cur_data, data_size); + } + cur_data += data_size; + + // set the datagram's working counter + datagram->working_counter = EC_READ_U16(cur_data); + cur_data += EC_DATAGRAM_FOOTER_SIZE; + + // dequeue the received datagram + datagram->state = EC_DATAGRAM_RECEIVED; +#ifdef EC_HAVE_CYCLES + datagram->cycles_received = + master->devices[EC_DEVICE_MAIN].cycles_poll; +#endif + datagram->jiffies_received = + master->devices[EC_DEVICE_MAIN].jiffies_poll; + list_del_init(&datagram->queue); + } +} + +/****************************************************************************/ + +/** Output master statistics. + * + * This function outputs statistical data on demand, but not more often than + * necessary. The output happens at most once a second. + */ +void ec_master_output_stats(ec_master_t *master /**< EtherCAT master */) +{ + if (unlikely(jiffies - master->stats.output_jiffies >= HZ)) { + master->stats.output_jiffies = jiffies; + + if (master->stats.timeouts) { + EC_MASTER_WARN(master, "%u datagram%s TIMED OUT!\n", + master->stats.timeouts, + master->stats.timeouts == 1 ? "" : "s"); + master->stats.timeouts = 0; + } + if (master->stats.corrupted) { + EC_MASTER_WARN(master, "%u frame%s CORRUPTED!\n", + master->stats.corrupted, + master->stats.corrupted == 1 ? "" : "s"); + master->stats.corrupted = 0; + } + if (master->stats.unmatched) { + EC_MASTER_WARN(master, "%u datagram%s UNMATCHED!\n", + master->stats.unmatched, + master->stats.unmatched == 1 ? "" : "s"); + master->stats.unmatched = 0; + } + } +} + +/****************************************************************************/ + +/** Clears the common device statistics. + */ +void ec_master_clear_device_stats( + ec_master_t *master /**< EtherCAT master */ + ) +{ + unsigned int i; + + // zero frame statistics + master->device_stats.tx_count = 0; + master->device_stats.last_tx_count = 0; + master->device_stats.rx_count = 0; + master->device_stats.last_rx_count = 0; + master->device_stats.tx_bytes = 0; + master->device_stats.last_tx_bytes = 0; + master->device_stats.rx_bytes = 0; + master->device_stats.last_rx_bytes = 0; + master->device_stats.last_loss = 0; + + for (i = 0; i < EC_RATE_COUNT; i++) { + master->device_stats.tx_frame_rates[i] = 0; + master->device_stats.rx_frame_rates[i] = 0; + master->device_stats.tx_byte_rates[i] = 0; + master->device_stats.rx_byte_rates[i] = 0; + master->device_stats.loss_rates[i] = 0; + } + + master->device_stats.jiffies = 0; +} + +/****************************************************************************/ + +/** Updates the common device statistics. + */ +void ec_master_update_device_stats( + ec_master_t *master /**< EtherCAT master */ + ) +{ + ec_device_stats_t *s = &master->device_stats; + s32 tx_frame_rate, rx_frame_rate, tx_byte_rate, rx_byte_rate, loss_rate; + u64 loss; + unsigned int i, dev_idx; + + // frame statistics + if (likely(jiffies - s->jiffies < HZ)) { + return; + } + + tx_frame_rate = (s->tx_count - s->last_tx_count) * 1000; + rx_frame_rate = (s->rx_count - s->last_rx_count) * 1000; + tx_byte_rate = s->tx_bytes - s->last_tx_bytes; + rx_byte_rate = s->rx_bytes - s->last_rx_bytes; + loss = s->tx_count - s->rx_count; + loss_rate = (loss - s->last_loss) * 1000; + + /* Low-pass filter: + * Y_n = y_(n - 1) + T / tau * (x - y_(n - 1)) | T = 1 + * -> Y_n += (x - y_(n - 1)) / tau + */ + for (i = 0; i < EC_RATE_COUNT; i++) { + s32 n = rate_intervals[i]; + s->tx_frame_rates[i] += (tx_frame_rate - s->tx_frame_rates[i]) / n; + s->rx_frame_rates[i] += (rx_frame_rate - s->rx_frame_rates[i]) / n; + s->tx_byte_rates[i] += (tx_byte_rate - s->tx_byte_rates[i]) / n; + s->rx_byte_rates[i] += (rx_byte_rate - s->rx_byte_rates[i]) / n; + s->loss_rates[i] += (loss_rate - s->loss_rates[i]) / n; + } + + s->last_tx_count = s->tx_count; + s->last_rx_count = s->rx_count; + s->last_tx_bytes = s->tx_bytes; + s->last_rx_bytes = s->rx_bytes; + s->last_loss = loss; + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ec_device_update_stats(&master->devices[dev_idx]); + } + + s->jiffies = jiffies; +} + +/****************************************************************************/ + +#ifdef EC_USE_HRTIMER + +/* + * Sleep related functions: + */ +static enum hrtimer_restart ec_master_nanosleep_wakeup(struct hrtimer *timer) +{ + struct hrtimer_sleeper *t = + container_of(timer, struct hrtimer_sleeper, timer); + struct task_struct *task = t->task; + + t->task = NULL; + if (task) + wake_up_process(task); + + return HRTIMER_NORESTART; +} + +/****************************************************************************/ + +void ec_master_nanosleep(const unsigned long nsecs) +{ + struct hrtimer_sleeper t; + enum hrtimer_mode mode = HRTIMER_MODE_REL; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 15, 0) + hrtimer_setup(&t.timer, ec_master_nanosleep_wakeup, + CLOCK_MONOTONIC, mode); +#else + hrtimer_init(&t.timer, CLOCK_MONOTONIC, mode); + t.timer.function = ec_master_nanosleep_wakeup; +#endif + t.task = current; + hrtimer_set_expires(&t.timer, ktime_set(0, nsecs)); + + do { + set_current_state(TASK_INTERRUPTIBLE); + hrtimer_start(&t.timer, hrtimer_get_expires(&t.timer), mode); + + if (likely(t.task)) + schedule(); + + hrtimer_cancel(&t.timer); + mode = HRTIMER_MODE_ABS; + + } while (t.task && !signal_pending(current)); +} + +#endif // EC_USE_HRTIMER + +/****************************************************************************/ + +/** Execute slave FSMs. + */ +void ec_master_exec_slave_fsms( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_datagram_t *datagram; + ec_fsm_slave_t *fsm, *next; + unsigned int count = 0; + + list_for_each_entry_safe(fsm, next, &master->fsm_exec_list, list) { + if (!fsm->datagram) { + EC_MASTER_WARN(master, "Slave %u FSM has zero datagram." + "This is a bug!\n", fsm->slave->ring_position); + list_del_init(&fsm->list); + master->fsm_exec_count--; + return; + } + + if (fsm->datagram->state == EC_DATAGRAM_INIT || + fsm->datagram->state == EC_DATAGRAM_QUEUED || + fsm->datagram->state == EC_DATAGRAM_SENT) { + // previous datagram was not sent or received yet. + // wait until next thread execution + return; + } + + datagram = ec_master_get_external_datagram(master); + if (!datagram) { + // no free datagrams at the moment + EC_MASTER_WARN(master, "No free datagram during" + " slave FSM execution. This is a bug!\n"); + continue; + } + +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "Executing slave %u FSM.\n", + fsm->slave->ring_position); +#endif + if (ec_fsm_slave_exec(fsm, datagram)) { + // FSM consumed datagram +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "FSM consumed datagram %s\n", + datagram->name); +#endif + master->ext_ring_idx_fsm = + (master->ext_ring_idx_fsm + 1) % EC_EXT_RING_SIZE; + } + else { + // FSM finished + list_del_init(&fsm->list); + master->fsm_exec_count--; +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "FSM finished. %u remaining.\n", + master->fsm_exec_count); +#endif + } + } + + while (master->fsm_exec_count < EC_EXT_RING_SIZE / 2 + && count < master->slave_count) { + + if (ec_fsm_slave_is_ready(&master->fsm_slave->fsm)) { + datagram = ec_master_get_external_datagram(master); + + if (ec_fsm_slave_exec(&master->fsm_slave->fsm, datagram)) { + master->ext_ring_idx_fsm = + (master->ext_ring_idx_fsm + 1) % EC_EXT_RING_SIZE; + list_add_tail(&master->fsm_slave->fsm.list, + &master->fsm_exec_list); + master->fsm_exec_count++; +#if DEBUG_INJECT + EC_MASTER_DBG(master, 1, "New slave %u FSM" + " consumed datagram %s, now %u FSMs in list.\n", + master->fsm_slave->ring_position, datagram->name, + master->fsm_exec_count); +#endif + } + } + + master->fsm_slave++; + if (master->fsm_slave >= master->slaves + master->slave_count) { + master->fsm_slave = master->slaves; + } + count++; + } +} + +/****************************************************************************/ + +/** Master kernel thread function for IDLE phase. + */ +static int ec_master_idle_thread(void *priv_data) +{ + ec_master_t *master = (ec_master_t *) priv_data; + int fsm_exec; +#ifdef EC_USE_HRTIMER + size_t sent_bytes; +#endif + + // send interval in IDLE phase + ec_master_set_send_interval(master, 1000000 / HZ); + + EC_MASTER_DBG(master, 1, "Idle thread running with send interval = %u us," + " max data size=%zu\n", master->send_interval, + master->max_queue_size); + + while (!kthread_should_stop()) { + ec_datagram_output_stats(&master->fsm_datagram); + + // receive + if (ec_rt_lock_interruptible(&master->io_mutex)) + break; + ecrt_master_receive(master); + rt_mutex_unlock(&master->io_mutex); + + // execute master & slave state machines + if (down_interruptible(&master->master_sem)) { + break; + } + + fsm_exec = ec_fsm_master_exec(&master->fsm); + + ec_master_exec_slave_fsms(master); + + up(&master->master_sem); + + // queue and send + if (ec_rt_lock_interruptible(&master->io_mutex)) + break; + if (fsm_exec) { + ec_master_queue_datagram(master, &master->fsm_datagram); + } + ecrt_master_send(master); +#ifdef EC_USE_HRTIMER + sent_bytes = master->devices[EC_DEVICE_MAIN].tx_skb[ + master->devices[EC_DEVICE_MAIN].tx_ring_index]->len; +#endif + rt_mutex_unlock(&master->io_mutex); + + if (ec_fsm_master_idle(&master->fsm)) { +#ifdef EC_USE_HRTIMER + ec_master_nanosleep(master->send_interval * 1000); +#else + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); +#endif + } else { +#ifdef EC_USE_HRTIMER + ec_master_nanosleep(sent_bytes * EC_BYTE_TRANSMISSION_TIME_NS); +#else + schedule(); +#endif + } + } + + EC_MASTER_DBG(master, 1, "Master IDLE thread exiting...\n"); + + return 0; +} + +/****************************************************************************/ + +/** Master kernel thread function for OPERATION phase. + */ +static int ec_master_operation_thread(void *priv_data) +{ + ec_master_t *master = (ec_master_t *) priv_data; + + EC_MASTER_DBG(master, 1, "Operation thread running" + " with fsm interval = %u us, max data size=%zu\n", + master->send_interval, master->max_queue_size); + + while (!kthread_should_stop()) { + ec_datagram_output_stats(&master->fsm_datagram); + + if (master->injection_seq_rt == master->injection_seq_fsm) { + // output statistics + ec_master_output_stats(master); + + // execute master & slave state machines + if (down_interruptible(&master->master_sem)) { + break; + } + + if (ec_fsm_master_exec(&master->fsm)) { + // Inject datagrams (let the RT thread queue them, see + // ecrt_master_send()) + master->injection_seq_fsm++; + } + + ec_master_exec_slave_fsms(master); + + up(&master->master_sem); + } + +#ifdef EC_USE_HRTIMER + // the op thread should not work faster than the sending RT thread + ec_master_nanosleep(master->send_interval * 1000); +#else + if (ec_fsm_master_idle(&master->fsm)) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } + else { + schedule(); + } +#endif + } + + EC_MASTER_DBG(master, 1, "Master OP thread exiting...\n"); + return 0; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/* compatibility for priority changes */ +static inline void set_normal_priority(struct task_struct *p, int nice) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) + sched_set_normal(p, nice); +#else + struct sched_param param = { .sched_priority = 0 }; + sched_setscheduler(p, SCHED_NORMAL, ¶m); + set_user_nice(p, nice); +#endif +} + +/****************************************************************************/ + +/** Starts Ethernet over EtherCAT processing on demand. + */ +void ec_master_eoe_start(ec_master_t *master /**< EtherCAT master */) +{ + if (master->eoe_thread) { + EC_MASTER_WARN(master, "EoE already running!\n"); + return; + } + + if (list_empty(&master->eoe_handlers)) + return; + + if (!master->send_cb || !master->receive_cb) { + EC_MASTER_WARN(master, "No EoE processing" + " because of missing callbacks!\n"); + return; + } + + EC_MASTER_INFO(master, "Starting EoE thread.\n"); + master->eoe_thread = kthread_run(ec_master_eoe_thread, master, + "EtherCAT-EoE"); + if (IS_ERR(master->eoe_thread)) { + int err = (int) PTR_ERR(master->eoe_thread); + EC_MASTER_ERR(master, "Failed to start EoE thread (error %i)!\n", + err); + master->eoe_thread = NULL; + return; + } + + set_normal_priority(master->eoe_thread, 0); +} + +/****************************************************************************/ + +/** Stops the Ethernet over EtherCAT processing. + */ +void ec_master_eoe_stop(ec_master_t *master /**< EtherCAT master */) +{ + if (master->eoe_thread) { + EC_MASTER_INFO(master, "Stopping EoE thread.\n"); + + kthread_stop(master->eoe_thread); + master->eoe_thread = NULL; + EC_MASTER_INFO(master, "EoE thread exited.\n"); + } +} + +/****************************************************************************/ + +/** Does the Ethernet over EtherCAT processing. + */ +static int ec_master_eoe_thread(void *priv_data) +{ + ec_master_t *master = (ec_master_t *) priv_data; + ec_eoe_t *eoe; + unsigned int none_open, sth_to_send, all_idle; + + EC_MASTER_DBG(master, 1, "EoE thread running.\n"); + + while (!kthread_should_stop()) { + none_open = 1; + all_idle = 1; + + list_for_each_entry(eoe, &master->eoe_handlers, list) { + if (ec_eoe_is_open(eoe)) { + none_open = 0; + break; + } + } + if (none_open) + goto schedule; + + // receive datagrams + master->receive_cb(master->cb_data); + + // actual EoE processing + sth_to_send = 0; + list_for_each_entry(eoe, &master->eoe_handlers, list) { + ec_eoe_run(eoe); + if (eoe->queue_datagram) { + sth_to_send = 1; + } + if (!ec_eoe_is_idle(eoe)) { + all_idle = 0; + } + } + + if (sth_to_send) { + list_for_each_entry(eoe, &master->eoe_handlers, list) { + ec_eoe_queue(eoe); + } + // (try to) send datagrams + master->send_cb(master->cb_data); + } + +schedule: + if (all_idle) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); + } else { + schedule(); + } + } + + EC_MASTER_DBG(master, 1, "EoE thread exiting...\n"); + return 0; +} + +#endif + +/****************************************************************************/ + +/** Attaches the slave configurations to the slaves. + */ +void ec_master_attach_slave_configs( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_slave_config_t *sc; + + list_for_each_entry(sc, &master->configs, list) { + ec_slave_config_attach(sc); + } +} + +/****************************************************************************/ + +/** Common implementation for ec_master_find_slave() + * and ec_master_find_slave_const(). + */ +#define EC_FIND_SLAVE \ + do { \ + if (alias) { \ + for (; slave < master->slaves + master->slave_count; \ + slave++) { \ + if (slave->effective_alias == alias) \ + break; \ + } \ + if (slave == master->slaves + master->slave_count) \ + return NULL; \ + } \ + \ + slave += position; \ + if (slave < master->slaves + master->slave_count) { \ + return slave; \ + } else { \ + return NULL; \ + } \ + } while (0) + +/** Finds a slave in the bus, given the alias and position. + * + * \return Search result, or NULL. + */ +ec_slave_t *ec_master_find_slave( + ec_master_t *master, /**< EtherCAT master. */ + uint16_t alias, /**< Slave alias. */ + uint16_t position /**< Slave position. */ + ) +{ + ec_slave_t *slave = master->slaves; + EC_FIND_SLAVE; +} + +/** Finds a slave in the bus, given the alias and position. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_slave_t *ec_master_find_slave_const( + const ec_master_t *master, /**< EtherCAT master. */ + uint16_t alias, /**< Slave alias. */ + uint16_t position /**< Slave position. */ + ) +{ + const ec_slave_t *slave = master->slaves; + EC_FIND_SLAVE; +} + +/****************************************************************************/ + +/** Get the number of slave configurations provided by the application. + * + * \return Number of configurations. + */ +unsigned int ec_master_config_count( + const ec_master_t *master /**< EtherCAT master. */ + ) +{ + const ec_slave_config_t *sc; + unsigned int count = 0; + + list_for_each_entry(sc, &master->configs, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Common implementation for ec_master_get_config() + * and ec_master_get_config_const(). + */ +#define EC_FIND_CONFIG \ + do { \ + list_for_each_entry(sc, &master->configs, list) { \ + if (pos--) \ + continue; \ + return sc; \ + } \ + return NULL; \ + } while (0) + +/** Get a slave configuration via its position in the list. + * + * \return Slave configuration or \a NULL. + */ +ec_slave_config_t *ec_master_get_config( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int pos /**< List position. */ + ) +{ + ec_slave_config_t *sc; + EC_FIND_CONFIG; +} + +/** Get a slave configuration via its position in the list. + * + * Const version. + * + * \return Slave configuration or \a NULL. + */ +const ec_slave_config_t *ec_master_get_config_const( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int pos /**< List position. */ + ) +{ + const ec_slave_config_t *sc; + EC_FIND_CONFIG; +} + +/****************************************************************************/ + +/** Get the number of domains. + * + * \return Number of domains. + */ +unsigned int ec_master_domain_count( + const ec_master_t *master /**< EtherCAT master. */ + ) +{ + const ec_domain_t *domain; + unsigned int count = 0; + + list_for_each_entry(domain, &master->domains, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Common implementation for ec_master_find_domain() and + * ec_master_find_domain_const(). + */ +#define EC_FIND_DOMAIN \ + do { \ + list_for_each_entry(domain, &master->domains, list) { \ + if (index--) \ + continue; \ + return domain; \ + } \ + \ + return NULL; \ + } while (0) + +/** Get a domain via its position in the list. + * + * \return Domain pointer, or \a NULL if not found. + */ +ec_domain_t *ec_master_find_domain( + ec_master_t *master, /**< EtherCAT master. */ + unsigned int index /**< Domain index. */ + ) +{ + ec_domain_t *domain; + EC_FIND_DOMAIN; +} + +/** Get a domain via its position in the list. + * + * Const version. + * + * \return Domain pointer, or \a NULL if not found. + */ +const ec_domain_t *ec_master_find_domain_const( + const ec_master_t *master, /**< EtherCAT master. */ + unsigned int index /**< Domain index. */ + ) +{ + const ec_domain_t *domain; + EC_FIND_DOMAIN; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +/** Get the number of EoE handlers. + * + * \return Number of EoE handlers. + */ +uint16_t ec_master_eoe_handler_count( + const ec_master_t *master /**< EtherCAT master. */ + ) +{ + const ec_eoe_t *eoe; + unsigned int count = 0; + + list_for_each_entry(eoe, &master->eoe_handlers, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Get an EoE handler via its position in the list. + * + * Const version. + * + * \return EoE handler pointer, or \a NULL if not found. + */ +const ec_eoe_t *ec_master_get_eoe_handler_const( + const ec_master_t *master, /**< EtherCAT master. */ + uint16_t index /**< EoE handler index. */ + ) +{ + const ec_eoe_t *eoe; + + list_for_each_entry(eoe, &master->eoe_handlers, list) { + if (index--) + continue; + return eoe; + } + + return NULL; +} + +#endif + +/****************************************************************************/ + +/** Set the debug level. + * + * \retval 0 Success. + * \retval -EINVAL Invalid debug level. + */ +int ec_master_debug_level( + ec_master_t *master, /**< EtherCAT master. */ + unsigned int level /**< Debug level. May be 0, 1 or 2. */ + ) +{ + if (level > 2) { + EC_MASTER_ERR(master, "Invalid debug level %u!\n", level); + return -EINVAL; + } + + if (level != master->debug_level) { + master->debug_level = level; + EC_MASTER_INFO(master, "Master debug level set to %u.\n", + master->debug_level); + } + + return 0; +} + +/****************************************************************************/ + +/** Finds the DC reference clock. + */ +void ec_master_find_dc_ref_clock( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_slave_t *slave, *ref = NULL; + + if (master->dc_ref_config) { + // Use application-selected reference clock + slave = master->dc_ref_config->slave; + + if (slave) { + if (slave->base_dc_supported && slave->has_dc_system_time) { + ref = slave; + } + else { + EC_MASTER_WARN(master, "Slave %u can not act as a" + " DC reference clock!", slave->ring_position); + } + } + else { + EC_MASTER_WARN(master, "DC reference clock config (%u-%u)" + " has no slave attached!\n", master->dc_ref_config->alias, + master->dc_ref_config->position); + } + } + else { + // Use first slave with DC support as reference clock + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + if (slave->base_dc_supported && slave->has_dc_system_time) { + ref = slave; + break; + } + } + + } + + master->dc_ref_clock = ref; + + if (ref) { + EC_MASTER_INFO(master, "Using slave %u as DC reference clock.\n", + ref->ring_position); + } + else { + EC_MASTER_INFO(master, "No DC reference clock found.\n"); + } + + // These calls always succeed, because the + // datagrams have been pre-allocated. + ec_datagram_fpwr(&master->ref_sync_datagram, + ref ? ref->station_address : 0xffff, 0x0910, 4); + ec_datagram_frmw(&master->sync_datagram, + ref ? ref->station_address : 0xffff, 0x0910, 4); +} + +/****************************************************************************/ + +/** Calculates the bus topology; recursion function. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_master_calc_topology_rec( + ec_master_t *master, /**< EtherCAT master. */ + ec_slave_t *port0_slave, /**< Slave at port 0. */ + unsigned int *slave_position /**< Slave position. */ + ) +{ + ec_slave_t *slave = master->slaves + *slave_position; + unsigned int port_index; + int ret; + + static const unsigned int next_table[EC_MAX_PORTS] = { + 3, 2, 0, 1 + }; + + slave->ports[0].next_slave = port0_slave; + + port_index = 3; + while (port_index != 0) { + if (!slave->ports[port_index].link.loop_closed) { + *slave_position = *slave_position + 1; + if (*slave_position < master->slave_count) { + slave->ports[port_index].next_slave = + master->slaves + *slave_position; + ret = ec_master_calc_topology_rec(master, + slave, slave_position); + if (ret) { + return ret; + } + } else { + return -1; + } + } + + port_index = next_table[port_index]; + } + + return 0; +} + +/****************************************************************************/ + +/** Calculates the bus topology. + */ +void ec_master_calc_topology( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + unsigned int slave_position = 0; + + if (master->slave_count == 0) + return; + + if (ec_master_calc_topology_rec(master, NULL, &slave_position)) + EC_MASTER_ERR(master, "Failed to calculate bus topology.\n"); +} + +/****************************************************************************/ + +/** Calculates the bus transmission delays. + */ +void ec_master_calc_transmission_delays( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + ec_slave_t *slave; + + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + ec_slave_calc_port_delays(slave); + } + + if (master->dc_ref_clock) { + uint32_t delay = 0; + ec_slave_calc_transmission_delays_rec(master->dc_ref_clock, &delay); + } +} + +/****************************************************************************/ + +/** Distributed-clocks calculations. + */ +void ec_master_calc_dc( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + // find DC reference clock + ec_master_find_dc_ref_clock(master); + + // calculate bus topology + ec_master_calc_topology(master); + + ec_master_calc_transmission_delays(master); +} + +/****************************************************************************/ + +/** Request OP state for configured slaves. + */ +void ec_master_request_op( + ec_master_t *master /**< EtherCAT master. */ + ) +{ + unsigned int i; + ec_slave_t *slave; + + if (!master->active) + return; + + EC_MASTER_DBG(master, 1, "Requesting OP...\n"); + + // request OP for all configured slaves + for (i = 0; i < master->slave_count; i++) { + slave = master->slaves + i; + if (slave->config) { + ec_slave_request_state(slave, EC_SLAVE_STATE_OP); + } + } + + // always set DC reference clock to OP + if (master->dc_ref_clock) { + ec_slave_request_state(master->dc_ref_clock, EC_SLAVE_STATE_OP); + } +} + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +/** Same as ecrt_master_create_domain(), but with ERR_PTR() return value. + * + * \return New domain, or ERR_PTR() return value. + */ +ec_domain_t *ecrt_master_create_domain_err( + ec_master_t *master /**< master */ + ) +{ + ec_domain_t *domain, *last_domain; + unsigned int index; + + EC_MASTER_DBG(master, 1, "ecrt_master_create_domain(master = 0x%p)\n", + master); + + if (!(domain = + (ec_domain_t *) kmalloc(sizeof(ec_domain_t), GFP_KERNEL))) { + EC_MASTER_ERR(master, "Error allocating domain memory!\n"); + return ERR_PTR(-ENOMEM); + } + + down(&master->master_sem); + + if (list_empty(&master->domains)) { + index = 0; + } else { + last_domain = list_entry(master->domains.prev, ec_domain_t, list); + index = last_domain->index + 1; + } + + ec_domain_init(domain, master, index); + list_add_tail(&domain->list, &master->domains); + + up(&master->master_sem); + + EC_MASTER_DBG(master, 1, "Created domain %u.\n", domain->index); + + return domain; +} + +/****************************************************************************/ + +ec_domain_t *ecrt_master_create_domain( + ec_master_t *master /**< master */ + ) +{ + ec_domain_t *d = ecrt_master_create_domain_err(master); + return IS_ERR(d) ? NULL : d; +} + +/****************************************************************************/ + +int ecrt_master_activate(ec_master_t *master) +{ + uint32_t domain_offset; + ec_domain_t *domain; + int ret; +#ifdef EC_EOE + int eoe_was_running; +#endif + + EC_MASTER_DBG(master, 1, "ecrt_master_activate(master = 0x%p)\n", master); + + if (master->active) { + EC_MASTER_WARN(master, "%s: Master already active!\n", __func__); + return 0; + } + + down(&master->master_sem); + + // finish all domains + domain_offset = 0; + list_for_each_entry(domain, &master->domains, list) { + ret = ec_domain_finish(domain, domain_offset); + if (ret < 0) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Failed to finish domain 0x%p!\n", domain); + return ret; + } + domain_offset += domain->data_size; + } + + up(&master->master_sem); + + // restart EoE process and master thread with new locking + + ec_master_thread_stop(master); +#ifdef EC_EOE + eoe_was_running = master->eoe_thread != NULL; + ec_master_eoe_stop(master); +#endif + + EC_MASTER_DBG(master, 1, "FSM datagram is %p.\n", &master->fsm_datagram); + + master->injection_seq_fsm = 0; + master->injection_seq_rt = 0; + + master->send_cb = master->app_send_cb; + master->receive_cb = master->app_receive_cb; + master->cb_data = master->app_cb_data; + +#ifdef EC_EOE + if (eoe_was_running) { + ec_master_eoe_start(master); + } +#endif + ret = ec_master_thread_start(master, ec_master_operation_thread, + "EtherCAT-OP"); + if (ret < 0) { + EC_MASTER_ERR(master, "Failed to start master thread!\n"); + return ret; + } + + /* Allow scanning after a topology change. */ + master->allow_scan = 1; + + master->active = 1; + + // notify state machine, that the configuration shall now be applied + master->config_changed = 1; + + return 0; +} + +/****************************************************************************/ + +int ecrt_master_deactivate(ec_master_t *master) +{ + ec_slave_t *slave; +#ifdef EC_EOE + ec_eoe_t *eoe; + int eoe_was_running; +#endif + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p)\n", __func__, master); + + if (!master->active) { + EC_MASTER_WARN(master, "%s: Master not active.\n", __func__); + return -EINVAL; + } + + ec_master_thread_stop(master); +#ifdef EC_EOE + eoe_was_running = master->eoe_thread != NULL; + ec_master_eoe_stop(master); +#endif + + master->send_cb = ec_master_internal_send_cb; + master->receive_cb = ec_master_internal_receive_cb; + master->cb_data = master; + + ec_master_clear_config(master); + + for (slave = master->slaves; + slave < master->slaves + master->slave_count; + slave++) { + + // set states for all slaves + ec_slave_request_state(slave, EC_SLAVE_STATE_PREOP); + + // mark for reconfiguration, because the master could have no + // possibility for a reconfiguration between two sequential operation + // phases. + slave->force_config = 1; + } + +#ifdef EC_EOE + // ... but leave EoE slaves in OP + list_for_each_entry(eoe, &master->eoe_handlers, list) { + if (ec_eoe_is_open(eoe)) + ec_slave_request_state(eoe->slave, EC_SLAVE_STATE_OP); + } +#endif + + master->app_time = 0ULL; + master->dc_ref_time = 0ULL; + +#ifdef EC_EOE + if (eoe_was_running) { + ec_master_eoe_start(master); + } +#endif + if (ec_master_thread_start(master, ec_master_idle_thread, + "EtherCAT-IDLE")) { + EC_MASTER_WARN(master, "Failed to restart master thread!\n"); + } + + /* Disallow scanning to get into the same state like after a master + * request (after ec_master_enter_operation_phase() is called). */ + master->allow_scan = 0; + + master->active = 0; + return 0; +} + +/****************************************************************************/ + +int ecrt_master_send(ec_master_t *master) +{ + ec_datagram_t *datagram, *n; + ec_device_index_t dev_idx; + + if (master->injection_seq_rt != master->injection_seq_fsm) { + // inject datagram produced by master FSM + ec_master_queue_datagram(master, &master->fsm_datagram); + master->injection_seq_rt = master->injection_seq_fsm; + } + + ec_master_inject_external_datagrams(master); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + if (unlikely(!master->devices[dev_idx].link_state)) { + // link is down, no datagram can be sent + list_for_each_entry_safe(datagram, n, + &master->datagram_queue, queue) { + if (datagram->device_index == dev_idx) { + datagram->state = EC_DATAGRAM_ERROR; + list_del_init(&datagram->queue); + } + } + + if (!master->devices[dev_idx].dev) { + continue; + } + + // query link state + ec_device_poll(&master->devices[dev_idx]); + + // clear frame statistics + ec_device_clear_stats(&master->devices[dev_idx]); + continue; + } + + // send frames + ec_master_send_datagrams(master, dev_idx); + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_receive(ec_master_t *master) +{ + unsigned int dev_idx; + ec_datagram_t *datagram, *next; + + // receive datagrams + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + ec_device_poll(&master->devices[dev_idx]); + } + ec_master_update_device_stats(master); + + // dequeue all datagrams that timed out + list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) { + if (datagram->state != EC_DATAGRAM_SENT) continue; + +#ifdef EC_HAVE_CYCLES + if (master->devices[EC_DEVICE_MAIN].cycles_poll - + datagram->cycles_sent > timeout_cycles) { +#else + if (master->devices[EC_DEVICE_MAIN].jiffies_poll - + datagram->jiffies_sent > timeout_jiffies) { +#endif + list_del_init(&datagram->queue); + datagram->state = EC_DATAGRAM_TIMED_OUT; + master->stats.timeouts++; + +#ifdef EC_RT_SYSLOG + ec_master_output_stats(master); + + if (unlikely(master->debug_level > 0)) { + unsigned int time_us; +#ifdef EC_HAVE_CYCLES + time_us = (unsigned int) + (master->devices[EC_DEVICE_MAIN].cycles_poll - + datagram->cycles_sent) * 1000 / cpu_khz; +#else + time_us = (unsigned int) + ((master->devices[EC_DEVICE_MAIN].jiffies_poll - + datagram->jiffies_sent) * 1000000 / HZ); +#endif + EC_MASTER_DBG(master, 0, "TIMED OUT datagram %p," + " index %02X waited %u us.\n", + datagram, datagram->index, time_us); + } +#endif /* RT_SYSLOG */ + } + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_send_ext(ec_master_t *master) +{ + ec_datagram_t *datagram, *next; + + if (down_trylock(&master->ext_queue_sem)) + return -EAGAIN; + + list_for_each_entry_safe(datagram, next, &master->ext_datagram_queue, + ext_queue) { + list_del_init(&datagram->ext_queue); + ec_master_queue_datagram(master, datagram); + } + up(&master->ext_queue_sem); + + return ecrt_master_send(master); +} + +/****************************************************************************/ + +/** Same as ecrt_master_slave_config(), but with ERR_PTR() return value. + */ +ec_slave_config_t *ecrt_master_slave_config_err(ec_master_t *master, + uint16_t alias, uint16_t position, uint32_t vendor_id, + uint32_t product_code) +{ + ec_slave_config_t *sc; + unsigned int found = 0; + + + EC_MASTER_DBG(master, 1, "ecrt_master_slave_config(master = 0x%p," + " alias = %u, position = %u, vendor_id = 0x%08x," + " product_code = 0x%08x)\n", + master, alias, position, vendor_id, product_code); + + list_for_each_entry(sc, &master->configs, list) { + if (sc->alias == alias && sc->position == position) { + found = 1; + break; + } + } + + if (found) { // config with same alias/position already existing + if (sc->vendor_id != vendor_id || sc->product_code != product_code) { + EC_MASTER_ERR(master, "Slave type mismatch. Slave was" + " configured as 0x%08X/0x%08X before. Now configuring" + " with 0x%08X/0x%08X.\n", sc->vendor_id, sc->product_code, + vendor_id, product_code); + return ERR_PTR(-ENOENT); + } + } else { + EC_MASTER_DBG(master, 1, "Creating slave configuration for %u:%u," + " 0x%08X/0x%08X.\n", + alias, position, vendor_id, product_code); + + if (!(sc = (ec_slave_config_t *) kmalloc(sizeof(ec_slave_config_t), + GFP_KERNEL))) { + EC_MASTER_ERR(master, "Failed to allocate memory" + " for slave configuration.\n"); + return ERR_PTR(-ENOMEM); + } + + ec_slave_config_init(sc, master, + alias, position, vendor_id, product_code); + + down(&master->master_sem); + + // try to find the addressed slave + ec_slave_config_attach(sc); + ec_slave_config_load_default_sync_config(sc); + list_add_tail(&sc->list, &master->configs); + + up(&master->master_sem); + } + + return sc; +} + +/****************************************************************************/ + +ec_slave_config_t *ecrt_master_slave_config(ec_master_t *master, + uint16_t alias, uint16_t position, uint32_t vendor_id, + uint32_t product_code) +{ + ec_slave_config_t *sc = ecrt_master_slave_config_err(master, alias, + position, vendor_id, product_code); + return IS_ERR(sc) ? NULL : sc; +} + +/****************************************************************************/ + +int ecrt_master_select_reference_clock(ec_master_t *master, + ec_slave_config_t *sc) +{ + if (sc) { + ec_slave_t *slave = sc->slave; + + // output an early warning + if (slave && + (!slave->base_dc_supported || !slave->has_dc_system_time)) { + EC_MASTER_WARN(master, "Slave %u can not act as" + " a reference clock!", slave->ring_position); + } + } + + master->dc_ref_config = sc; + return 0; +} + +/****************************************************************************/ + +int ecrt_master(ec_master_t *master, ec_master_info_t *master_info) +{ + EC_MASTER_DBG(master, 1, "ecrt_master(master = 0x%p," + " master_info = 0x%p)\n", master, master_info); + + master_info->slave_count = master->slave_count; + master_info->link_up = master->devices[EC_DEVICE_MAIN].link_state; + master_info->scan_busy = master->scan_busy; + master_info->app_time = master->app_time; + return 0; +} + +/****************************************************************************/ + +int ecrt_master_scan_progress(ec_master_t *master, + ec_master_scan_progress_t *progress) +{ + EC_MASTER_DBG(master, 1, "ecrt_master_scan_progress(master = 0x%p," + " progress = 0x%p)\n", master, progress); + + progress->slave_count = master->slave_count; + progress->scan_index = master->scan_index; + return 0; +} + +/****************************************************************************/ + +int ecrt_master_get_slave(ec_master_t *master, uint16_t slave_position, + ec_slave_info_t *slave_info) +{ + const ec_slave_t *slave; + unsigned int i; + int ret = 0; + + if (down_interruptible(&master->master_sem)) { + return -EINTR; + } + + slave = ec_master_find_slave_const(master, 0, slave_position); + + if (slave == NULL) { + ret = -ENOENT; + goto out_get_slave; + } + + slave_info->position = slave->ring_position; + slave_info->vendor_id = slave->sii.vendor_id; + slave_info->product_code = slave->sii.product_code; + slave_info->revision_number = slave->sii.revision_number; + slave_info->serial_number = slave->sii.serial_number; + slave_info->alias = slave->effective_alias; + slave_info->current_on_ebus = slave->sii.current_on_ebus; + + for (i = 0; i < EC_MAX_PORTS; i++) { + slave_info->ports[i].desc = slave->ports[i].desc; + slave_info->ports[i].link.link_up = slave->ports[i].link.link_up; + slave_info->ports[i].link.loop_closed = + slave->ports[i].link.loop_closed; + slave_info->ports[i].link.signal_detected = + slave->ports[i].link.signal_detected; + slave_info->ports[i].receive_time = slave->ports[i].receive_time; + if (slave->ports[i].next_slave) { + slave_info->ports[i].next_slave = + slave->ports[i].next_slave->ring_position; + } else { + slave_info->ports[i].next_slave = 0xffff; + } + slave_info->ports[i].delay_to_next_dc = + slave->ports[i].delay_to_next_dc; + } + + slave_info->al_state = slave->current_state; + slave_info->error_flag = slave->error_flag; + slave_info->sync_count = slave->sii.sync_count; + slave_info->sdo_count = ec_slave_sdo_count(slave); + if (slave->sii.name) { + strncpy(slave_info->name, slave->sii.name, EC_MAX_STRING_LENGTH); + } else { + slave_info->name[0] = 0; + } + +out_get_slave: + up(&master->master_sem); + + return ret; +} + +/****************************************************************************/ + +void ecrt_master_callbacks(ec_master_t *master, + void (*send_cb)(void *), void (*receive_cb)(void *), void *cb_data) +{ + EC_MASTER_DBG(master, 1, "ecrt_master_callbacks(master = 0x%p," + " send_cb = 0x%p, receive_cb = 0x%p, cb_data = 0x%p)\n", + master, send_cb, receive_cb, cb_data); + + master->app_send_cb = send_cb; + master->app_receive_cb = receive_cb; + master->app_cb_data = cb_data; +} + +/****************************************************************************/ + +int ecrt_master_state(const ec_master_t *master, ec_master_state_t *state) +{ + ec_device_index_t dev_idx; + + state->slaves_responding = 0U; + state->al_states = 0; + state->link_up = 0U; + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + /* Announce sum of responding slaves on all links. */ + state->slaves_responding += master->fsm.slaves_responding[dev_idx]; + + /* Binary-or slave states of all links. */ + state->al_states |= master->fsm.slave_states[dev_idx]; + + /* Signal link up if at least one device has link. */ + state->link_up |= master->devices[dev_idx].link_state; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_link_state(const ec_master_t *master, unsigned int dev_idx, + ec_master_link_state_t *state) +{ + if (dev_idx >= ec_master_num_devices(master)) { + return -EINVAL; + } + + state->slaves_responding = master->fsm.slaves_responding[dev_idx]; + state->al_states = master->fsm.slave_states[dev_idx]; + state->link_up = master->devices[dev_idx].link_state; + + return 0; +} + +/****************************************************************************/ + +int ecrt_master_application_time(ec_master_t *master, uint64_t app_time) +{ + master->app_time = app_time; + + if (unlikely(!master->dc_ref_time)) { + master->dc_ref_time = app_time; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_reference_clock_time(const ec_master_t *master, + uint32_t *time) +{ + if (!master->dc_ref_clock) { + return -ENXIO; + } + + if (master->sync_datagram.state != EC_DATAGRAM_RECEIVED) { + return -EIO; + } + + // Get returned datagram time, transmission delay removed. + *time = EC_READ_U32(master->sync_datagram.data) - + master->dc_ref_clock->transmission_delay; + + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_reference_clock(ec_master_t *master) +{ + if (master->dc_ref_clock) { + EC_WRITE_U32(master->ref_sync_datagram.data, master->app_time); + ec_master_queue_datagram(master, &master->ref_sync_datagram); + } else { + return -ENXIO; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_reference_clock_to( + ec_master_t *master, + uint64_t sync_time + ) +{ + if (master->dc_ref_clock) { + EC_WRITE_U32(master->ref_sync_datagram.data, sync_time); + ec_master_queue_datagram(master, &master->ref_sync_datagram); + } else { + return -ENXIO; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_slave_clocks(ec_master_t *master) +{ + if (master->dc_ref_clock) { + ec_datagram_zero(&master->sync_datagram); + ec_master_queue_datagram(master, &master->sync_datagram); + } else { + return -ENXIO; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_master_sync_monitor_queue(ec_master_t *master) +{ + ec_datagram_zero(&master->sync_mon_datagram); + ec_master_queue_datagram(master, &master->sync_mon_datagram); + return 0; +} + +/****************************************************************************/ + +uint32_t ecrt_master_sync_monitor_process(const ec_master_t *master) +{ + if (master->sync_mon_datagram.state == EC_DATAGRAM_RECEIVED) { + return EC_READ_U32(master->sync_mon_datagram.data) & 0x7fffffff; + } else { + return 0xffffffff; + } +} + +/****************************************************************************/ + +int ecrt_master_sdo_download(ec_master_t *master, uint16_t slave_position, + uint16_t index, uint8_t subindex, const uint8_t *data, + size_t data_size, uint32_t *abort_code) +{ + ec_sdo_request_t request; + ec_slave_t *slave; + int ret; + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p," + " slave_position = %u, index = 0x%04X, subindex = 0x%02X," + " data = 0x%p, data_size = %zu, abort_code = 0x%p)\n", + __func__, master, slave_position, index, subindex, + data, data_size, abort_code); + + ec_sdo_request_init(&request); + ecrt_sdo_request_index(&request, index, subindex); + ret = ec_sdo_request_alloc(&request, data_size); + if (ret) { + ec_sdo_request_clear(&request); + return ret; + } + + memcpy(request.data, data, data_size); + request.data_size = data_size; + ecrt_sdo_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_sdo_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + ec_sdo_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SDO download request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->sdo_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_sdo_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + *abort_code = request.abort_code; + + if (request.state == EC_INT_REQUEST_SUCCESS) { + ret = 0; + } else if (request.errno) { + ret = -request.errno; + } else { + ret = -EIO; + } + + ec_sdo_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_sdo_download_complete(ec_master_t *master, + uint16_t slave_position, uint16_t index, const uint8_t *data, + size_t data_size, uint32_t *abort_code) +{ + ec_sdo_request_t request; + ec_slave_t *slave; + int ret; + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p," + " slave_position = %u, index = 0x%04X," + " data = 0x%p, data_size = %zu, abort_code = 0x%p)\n", + __func__, master, slave_position, index, data, data_size, + abort_code); + + ec_sdo_request_init(&request); + ecrt_sdo_request_index(&request, index, 0); + ret = ec_sdo_request_alloc(&request, data_size); + if (ret) { + ec_sdo_request_clear(&request); + return ret; + } + + request.complete_access = 1; + memcpy(request.data, data, data_size); + request.data_size = data_size; + ecrt_sdo_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_sdo_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + ec_sdo_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SDO download request" + " (complete access).\n"); + + // schedule request. + list_add_tail(&request.list, &slave->sdo_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_sdo_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + *abort_code = request.abort_code; + + if (request.state == EC_INT_REQUEST_SUCCESS) { + ret = 0; + } else if (request.errno) { + ret = -request.errno; + } else { + ret = -EIO; + } + + ec_sdo_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_sdo_upload(ec_master_t *master, uint16_t slave_position, + uint16_t index, uint8_t subindex, uint8_t *target, + size_t target_size, size_t *result_size, uint32_t *abort_code) +{ + ec_sdo_request_t request; + ec_slave_t *slave; + int ret = 0; + + EC_MASTER_DBG(master, 1, "%s(master = 0x%p," + " slave_position = %u, index = 0x%04X, subindex = 0x%02X," + " target = 0x%p, target_size = %zu, result_size = 0x%p," + " abort_code = 0x%p)\n", + __func__, master, slave_position, index, subindex, + target, target_size, result_size, abort_code); + + ec_sdo_request_init(&request); + ecrt_sdo_request_index(&request, index, subindex); + ecrt_sdo_request_read(&request); + + if (down_interruptible(&master->master_sem)) { + ec_sdo_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + ec_sdo_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SDO upload request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->sdo_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_sdo_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + *abort_code = request.abort_code; + + if (request.state != EC_INT_REQUEST_SUCCESS) { + *result_size = 0; + if (request.errno) { + ret = -request.errno; + } else { + ret = -EIO; + } + } else { + if (request.data_size > target_size) { + EC_SLAVE_ERR(slave, "%s(): Buffer too small.\n", __func__); + ret = -ENOBUFS; + } + else { + memcpy(target, request.data, request.data_size); + *result_size = request.data_size; + ret = 0; + } + } + + ec_sdo_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_write_idn(ec_master_t *master, uint16_t slave_position, + uint8_t drive_no, uint16_t idn, const uint8_t *data, size_t data_size, + uint16_t *error_code) +{ + ec_soe_request_t request; + ec_slave_t *slave; + int ret; + + if (drive_no > 7) { + EC_MASTER_ERR(master, "Invalid drive number!\n"); + return -EINVAL; + } + + ec_soe_request_init(&request); + ec_soe_request_set_drive_no(&request, drive_no); + ec_soe_request_set_idn(&request, idn); + + ret = ec_soe_request_alloc(&request, data_size); + if (ret) { + ec_soe_request_clear(&request); + return ret; + } + + memcpy(request.data, data, data_size); + request.data_size = data_size; + ec_soe_request_write(&request); + + if (down_interruptible(&master->master_sem)) { + ec_soe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", + slave_position); + ec_soe_request_clear(&request); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SoE write request.\n"); + + // schedule SoE write request. + list_add_tail(&request.list, &slave->soe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + // abort request + list_del(&request.list); + up(&master->master_sem); + ec_soe_request_clear(&request); + return -EINTR; + } + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + if (error_code) { + *error_code = request.error_code; + } + ret = request.state == EC_INT_REQUEST_SUCCESS ? 0 : -EIO; + ec_soe_request_clear(&request); + + return ret; +} + +/****************************************************************************/ + +int ecrt_master_read_idn(ec_master_t *master, uint16_t slave_position, + uint8_t drive_no, uint16_t idn, uint8_t *target, size_t target_size, + size_t *result_size, uint16_t *error_code) +{ + ec_soe_request_t request; + ec_slave_t *slave; + int ret; + + if (drive_no > 7) { + EC_MASTER_ERR(master, "Invalid drive number!\n"); + return -EINVAL; + } + + ec_soe_request_init(&request); + ec_soe_request_set_drive_no(&request, drive_no); + ec_soe_request_set_idn(&request, idn); + ec_soe_request_read(&request); + + if (down_interruptible(&master->master_sem)) { + ec_soe_request_clear(&request); + return -EINTR; + } + + if (!(slave = ec_master_find_slave(master, 0, slave_position))) { + up(&master->master_sem); + ec_soe_request_clear(&request); + EC_MASTER_ERR(master, "Slave %u does not exist!\n", slave_position); + return -EINVAL; + } + + EC_SLAVE_DBG(slave, 1, "Scheduling SoE read request.\n"); + + // schedule request. + list_add_tail(&request.list, &slave->soe_requests); + + up(&master->master_sem); + + // wait for processing through FSM + if (wait_event_interruptible(master->request_queue, + request.state != EC_INT_REQUEST_QUEUED)) { + // interrupted by signal + down(&master->master_sem); + if (request.state == EC_INT_REQUEST_QUEUED) { + list_del(&request.list); + up(&master->master_sem); + ec_soe_request_clear(&request); + return -EINTR; + } + // request already processing: interrupt not possible. + up(&master->master_sem); + } + + // wait until master FSM has finished processing + wait_event(master->request_queue, request.state != EC_INT_REQUEST_BUSY); + + if (error_code) { + *error_code = request.error_code; + } + + if (request.state != EC_INT_REQUEST_SUCCESS) { + if (result_size) { + *result_size = 0; + } + ret = -EIO; + } else { // success + if (request.data_size > target_size) { + EC_SLAVE_ERR(slave, "%s(): Buffer too small.\n", __func__); + ret = -ENOBUFS; + } + else { // data fits in buffer + if (result_size) { + *result_size = request.data_size; + } + memcpy(target, request.data, request.data_size); + ret = 0; + } + } + + ec_soe_request_clear(&request); + return ret; +} + +/****************************************************************************/ + +int ecrt_master_reset(ec_master_t *master) +{ + ec_slave_config_t *sc; + + list_for_each_entry(sc, &master->configs, list) { + if (sc->slave) { + ec_slave_request_state(sc->slave, EC_SLAVE_STATE_OP); + } + } + return 0; +} + +/****************************************************************************/ + +static void sc_reset_task_kicker(struct irq_work *work) +{ + struct ec_master *master = + container_of(work, struct ec_master, sc_reset_work_kicker); + schedule_work(&master->sc_reset_work); +} + +/****************************************************************************/ + +static void sc_reset_task(struct work_struct *work) +{ + struct ec_master *master = + container_of(work, struct ec_master, sc_reset_work); + + down(&master->master_sem); + ecrt_master_reset(master); + up(&master->master_sem); +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_master_create_domain); +EXPORT_SYMBOL(ecrt_master_activate); +EXPORT_SYMBOL(ecrt_master_deactivate); +EXPORT_SYMBOL(ecrt_master_send); +EXPORT_SYMBOL(ecrt_master_send_ext); +EXPORT_SYMBOL(ecrt_master_receive); +EXPORT_SYMBOL(ecrt_master_callbacks); +EXPORT_SYMBOL(ecrt_master); +EXPORT_SYMBOL(ecrt_master_scan_progress); +EXPORT_SYMBOL(ecrt_master_get_slave); +EXPORT_SYMBOL(ecrt_master_slave_config); +EXPORT_SYMBOL(ecrt_master_select_reference_clock); +EXPORT_SYMBOL(ecrt_master_state); +EXPORT_SYMBOL(ecrt_master_link_state); +EXPORT_SYMBOL(ecrt_master_application_time); +EXPORT_SYMBOL(ecrt_master_sync_reference_clock); +EXPORT_SYMBOL(ecrt_master_sync_reference_clock_to); +EXPORT_SYMBOL(ecrt_master_sync_slave_clocks); +EXPORT_SYMBOL(ecrt_master_reference_clock_time); +EXPORT_SYMBOL(ecrt_master_sync_monitor_queue); +EXPORT_SYMBOL(ecrt_master_sync_monitor_process); +EXPORT_SYMBOL(ecrt_master_sdo_download); +EXPORT_SYMBOL(ecrt_master_sdo_download_complete); +EXPORT_SYMBOL(ecrt_master_sdo_upload); +EXPORT_SYMBOL(ecrt_master_write_idn); +EXPORT_SYMBOL(ecrt_master_read_idn); +EXPORT_SYMBOL(ecrt_master_reset); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/master.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/master.h @@ -0,0 +1,386 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT master structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_MASTER_H__ +#define __EC_MASTER_H__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "device.h" +#include "domain.h" +#include "ethernet.h" +#include "fsm_master.h" +#include "cdev.h" + +#ifdef EC_RTDM +#include "rtdm.h" +#endif + +/****************************************************************************/ + +/** Convenience macro for printing master-specific information to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_INFO(master, fmt, args...) \ + printk(KERN_INFO "EtherCAT %u: " fmt, master->index, ##args) + +/** Convenience macro for printing master-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_ERR(master, fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR %u: " fmt, master->index, ##args) + +/** Convenience macro for printing master-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_WARN(master, fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING %u: " fmt, master->index, ##args) + +/** Convenience macro for printing master-specific debug messages to syslog. + * + * This will print the message in \a fmt with a prefixed "EtherCAT : ", + * where INDEX is the master index. + * + * \param master EtherCAT master + * \param level Debug level. Master's debug level must be >= \a level for + * output. + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_MASTER_DBG(master, level, fmt, args...) \ + do { \ + if (master->debug_level >= level) { \ + printk(KERN_DEBUG "EtherCAT DEBUG %u: " fmt, \ + master->index, ##args); \ + } \ + } while (0) + + +/** Size of the external datagram ring. + * + * The external datagram ring is used for slave FSMs. + */ +#define EC_EXT_RING_SIZE 32 + +/** Maximum number of masters. + */ +#define EC_MAX_MASTERS 32 + +/****************************************************************************/ + +/** EtherCAT master phase. + */ +typedef enum { + EC_ORPHANED, /**< Orphaned phase. The master has no Ethernet device + attached. */ + EC_IDLE, /**< Idle phase. An Ethernet device is attached, but the master + is not in use, yet. */ + EC_OPERATION /**< Operation phase. The master was requested by a realtime + application. */ +} ec_master_phase_t; + +/****************************************************************************/ + +/** Cyclic statistics. + */ +typedef struct { + unsigned int timeouts; /**< datagram timeouts */ + unsigned int corrupted; /**< corrupted frames */ + unsigned int unmatched; /**< unmatched datagrams (received, but not + queued any longer) */ + unsigned long output_jiffies; /**< time of last output */ +} ec_stats_t; + +/****************************************************************************/ + +/** Device statistics. + */ +typedef struct { + u64 tx_count; /**< Number of frames sent. */ + u64 last_tx_count; /**< Number of frames sent of last statistics cycle. */ + u64 rx_count; /**< Number of frames received. */ + u64 last_rx_count; /**< Number of frames received of last statistics + cycle. */ + u64 tx_bytes; /**< Number of bytes sent. */ + u64 last_tx_bytes; /**< Number of bytes sent of last statistics cycle. */ + u64 rx_bytes; /**< Number of bytes received. */ + u64 last_rx_bytes; /**< Number of bytes received of last statistics cycle. + */ + u64 last_loss; /**< Tx/Rx difference of last statistics cycle. */ + s32 tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for + different statistics cycle periods. + */ + s32 rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for + different statistics cycle periods. + */ + s32 tx_byte_rates[EC_RATE_COUNT]; /**< Transmit rates in byte/s for + different statistics cycle periods. */ + s32 rx_byte_rates[EC_RATE_COUNT]; /**< Receive rates in byte/s for + different statistics cycle periods. */ + s32 loss_rates[EC_RATE_COUNT]; /**< Frame loss rates for different + statistics cycle periods. */ + unsigned long jiffies; /**< Jiffies of last statistic cycle. */ +} ec_device_stats_t; + +/****************************************************************************/ + +#if EC_MAX_NUM_DEVICES < 1 +#error Invalid number of devices +#endif + +/****************************************************************************/ + +/** EtherCAT master. + * + * Manages slaves, domains and IO. + */ +struct ec_master { + unsigned int index; /**< Index. */ + unsigned int reserved; /**< \a True, if the master is in use. */ + + ec_cdev_t cdev; /**< Master character device. */ + struct device *class_device; /**< Master class device. */ + +#ifdef EC_RTDM + ec_rtdm_dev_t rtdm_dev; /**< RTDM device. */ +#endif + + struct semaphore master_sem; /**< Master semaphore. */ + + ec_device_t devices[EC_MAX_NUM_DEVICES]; /**< EtherCAT devices. */ + const uint8_t *macs[EC_MAX_NUM_DEVICES]; /**< Device MAC addresses. */ +#if EC_MAX_NUM_DEVICES > 1 + unsigned int num_devices; /**< Number of devices. Access this always via + ec_master_num_devices(), because it may be + optimized! */ +#endif + struct semaphore device_sem; /**< Device semaphore. */ + ec_device_stats_t device_stats; /**< Device statistics. */ + + ec_fsm_master_t fsm; /**< Master state machine. */ + ec_datagram_t fsm_datagram; /**< Datagram used for state machines. */ + ec_master_phase_t phase; /**< Master phase. */ + unsigned int active; /**< Master has been activated. */ + unsigned int config_changed; /**< The configuration changed. */ + unsigned int injection_seq_fsm; /**< Datagram injection sequence number + for the FSM side. */ + unsigned int injection_seq_rt; /**< Datagram injection sequence number + for the realtime side. */ + + ec_slave_t *slaves; /**< Array of slaves on the bus. */ + unsigned int slave_count; /**< Number of slaves on the bus. */ + + /* Configuration applied by the application. */ + struct list_head configs; /**< List of slave configurations. */ + struct list_head domains; /**< List of domains. */ + + u64 app_time; /**< Time of the last ecrt_master_sync() call. */ + u64 dc_ref_time; /**< Common reference timestamp for DC start times. */ + ec_datagram_t ref_sync_datagram; /**< Datagram used for synchronizing the + reference clock to the master clock. */ + ec_datagram_t sync_datagram; /**< Datagram used for DC drift + compensation. */ + ec_datagram_t sync_mon_datagram; /**< Datagram used for DC synchronisation + monitoring. */ + ec_slave_config_t *dc_ref_config; /**< Application-selected DC reference + clock slave config. */ + ec_slave_t *dc_ref_clock; /**< DC reference clock slave. */ + + unsigned int scan_busy; /**< Current scan state. */ + unsigned int scan_index; /**< Index of slave currently scanned. */ + unsigned int allow_scan; /**< \a True, if slave scanning is allowed. */ + struct semaphore scan_sem; /**< Semaphore protecting the \a scan_busy + variable and the \a allow_scan flag. */ + wait_queue_head_t scan_queue; /**< Queue for processes that wait for + slave scanning. */ + + unsigned int config_busy; /**< State of slave configuration. */ + struct semaphore config_sem; /**< Semaphore protecting the \a config_busy + variable and the allow_config flag. */ + wait_queue_head_t config_queue; /**< Queue for processes that wait for + slave configuration. */ + + struct list_head datagram_queue; /**< Datagram queue. */ + uint8_t datagram_index; /**< Current datagram index. */ + + struct list_head ext_datagram_queue; /**< Queue for non-application + datagrams. */ + struct semaphore ext_queue_sem; /**< Semaphore protecting the \a + ext_datagram_queue. */ + + ec_datagram_t ext_datagram_ring[EC_EXT_RING_SIZE]; /**< External datagram + ring. */ + unsigned int ext_ring_idx_rt; /**< Index in external datagram ring for RT + side. */ + unsigned int ext_ring_idx_fsm; /**< Index in external datagram ring for + FSM side. */ + unsigned int send_interval; /**< Interval between two calls to + ecrt_master_send(). */ + size_t max_queue_size; /**< Maximum size of datagram queue */ + + ec_slave_t *fsm_slave; /**< Slave that is queried next for FSM exec. */ + struct list_head fsm_exec_list; /**< Slave FSM execution list. */ + unsigned int fsm_exec_count; /**< Number of entries in execution list. */ + + unsigned int debug_level; /**< Master debug level. */ + unsigned int run_on_cpu; /**< bind kernel threads to this cpu */ + ec_stats_t stats; /**< Cyclic statistics. */ + + struct task_struct *thread; /**< Master thread. */ + +#ifdef EC_EOE + struct task_struct *eoe_thread; /**< EoE thread. */ + struct list_head eoe_handlers; /**< Ethernet over EtherCAT handlers. */ +#endif + + struct rt_mutex io_mutex; /**< Mutex used in \a IDLE and \a OP phase. */ + + void (*send_cb)(void *); /**< Current send datagrams callback. */ + void (*receive_cb)(void *); /**< Current receive datagrams callback. */ + void *cb_data; /**< Current callback data. */ + void (*app_send_cb)(void *); /**< Application's send datagrams + callback. */ + void (*app_receive_cb)(void *); /**< Application's receive datagrams + callback. */ + void *app_cb_data; /**< Application callback data. */ + + struct list_head sii_requests; /**< SII write requests. */ + struct list_head emerg_reg_requests; /**< Emergency register access + requests. */ + + wait_queue_head_t request_queue; /**< Wait queue for external requests + from user space. */ + struct work_struct sc_reset_work; /**< Task to reset slave configuration. */ + struct irq_work sc_reset_work_kicker; /**< NMI-Safe kicker to trigger + reset task above. */ +}; + +/****************************************************************************/ + +// static funtions +void ec_master_init_static(void); + +// master creation/deletion +int ec_master_init(ec_master_t *, unsigned int, const uint8_t *, + const uint8_t *, dev_t, struct class *, unsigned int, unsigned int); +void ec_master_clear(ec_master_t *); + +/** Number of Ethernet devices. + */ +#if EC_MAX_NUM_DEVICES > 1 +#define ec_master_num_devices(MASTER) ((MASTER)->num_devices) +#else +#define ec_master_num_devices(MASTER) 1 +#endif + +// phase transitions +int ec_master_enter_idle_phase(ec_master_t *); +void ec_master_leave_idle_phase(ec_master_t *); +int ec_master_enter_operation_phase(ec_master_t *); +void ec_master_leave_operation_phase(ec_master_t *); + +#ifdef EC_EOE +// EoE +void ec_master_eoe_start(ec_master_t *); +void ec_master_eoe_stop(ec_master_t *); +#endif + +// datagram IO +void ec_master_receive_datagrams(ec_master_t *, ec_device_t *, + const uint8_t *, size_t); +void ec_master_queue_datagram(ec_master_t *, ec_datagram_t *); +void ec_master_queue_datagram_ext(ec_master_t *, ec_datagram_t *); + +// misc. +void ec_master_set_send_interval(ec_master_t *, unsigned int); +void ec_master_attach_slave_configs(ec_master_t *); +ec_slave_t *ec_master_find_slave(ec_master_t *, uint16_t, uint16_t); +const ec_slave_t *ec_master_find_slave_const(const ec_master_t *, uint16_t, + uint16_t); +void ec_master_output_stats(ec_master_t *); +#ifdef EC_EOE +void ec_master_clear_eoe_handlers(ec_master_t *); +#endif +void ec_master_clear_slaves(ec_master_t *); + +unsigned int ec_master_config_count(const ec_master_t *); +ec_slave_config_t *ec_master_get_config( + const ec_master_t *, unsigned int); +const ec_slave_config_t *ec_master_get_config_const( + const ec_master_t *, unsigned int); +unsigned int ec_master_domain_count(const ec_master_t *); +ec_domain_t *ec_master_find_domain(ec_master_t *, unsigned int); +const ec_domain_t *ec_master_find_domain_const(const ec_master_t *, + unsigned int); +#ifdef EC_EOE +uint16_t ec_master_eoe_handler_count(const ec_master_t *); +const ec_eoe_t *ec_master_get_eoe_handler_const(const ec_master_t *, uint16_t); +#endif + +int ec_master_debug_level(ec_master_t *, unsigned int); + +ec_domain_t *ecrt_master_create_domain_err(ec_master_t *); +ec_slave_config_t *ecrt_master_slave_config_err(ec_master_t *, uint16_t, + uint16_t, uint32_t, uint32_t); + +void ec_master_calc_dc(ec_master_t *); +void ec_master_request_op(ec_master_t *); + +void ec_master_internal_send_cb(void *); +void ec_master_internal_receive_cb(void *); + +extern const unsigned int rate_intervals[EC_RATE_COUNT]; // see master.c + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/module.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/module.c @@ -0,0 +1,681 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT master driver module. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "globals.h" +#include "master.h" +#include "device.h" + +/****************************************************************************/ + +/****************************************************************************/ + +int __init ec_init_module(void); +void __exit ec_cleanup_module(void); + +static int ec_mac_parse(uint8_t *, const char *, int); + +// prototypes for private functions +int ec_mac_equal(const uint8_t *, const uint8_t *); +int ec_mac_is_broadcast(const uint8_t *); + +/****************************************************************************/ + +static char *main_devices[EC_MAX_MASTERS]; /**< Main devices parameter. */ +static unsigned int master_count; /**< Number of masters. */ +static char *backup_devices[EC_MAX_MASTERS]; /**< Backup devices parameter. */ +static unsigned int backup_count; /**< Number of backup devices. */ +static unsigned int debug_level; /**< Debug level parameter. */ +static unsigned int run_on_cpu = 0xffffffff; /**< Bind created kernel threads + to a cpu. Default do not bind. + */ + +static ec_master_t *masters; /**< Array of masters. */ +static struct semaphore master_sem; /**< Master semaphore. */ + +dev_t device_number; /**< Device number for master cdevs. */ +struct class *class; /**< Device class. */ + +static uint8_t macs[EC_MAX_MASTERS][2][ETH_ALEN]; /**< MAC addresses. */ + +char *ec_master_version_str = EC_MASTER_VERSION; /**< Version string. */ + +/****************************************************************************/ + +/** \cond */ + +MODULE_AUTHOR("Florian Pose "); +MODULE_DESCRIPTION("EtherCAT master driver module"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(EC_MASTER_VERSION); + +module_param_array(main_devices, charp, &master_count, S_IRUGO); +MODULE_PARM_DESC(main_devices, "MAC addresses of main devices"); +module_param_array(backup_devices, charp, &backup_count, S_IRUGO); +MODULE_PARM_DESC(backup_devices, "MAC addresses of backup devices"); +module_param_named(debug_level, debug_level, uint, S_IRUGO); +MODULE_PARM_DESC(debug_level, "Debug level"); +module_param_named(run_on_cpu, run_on_cpu, uint, S_IRUGO); +MODULE_PARM_DESC(run_on_cpu, "Bind kthreads to a specific cpu"); + +/** \endcond */ + +/****************************************************************************/ + +/** Module initialization. + * + * Initializes \a master_count masters. + * \return 0 on success, else < 0 + */ +int __init ec_init_module(void) +{ + int i, ret = 0; + + EC_INFO("Master driver %s\n", EC_MASTER_VERSION); + + sema_init(&master_sem, 1); + + if (master_count) { + if (alloc_chrdev_region(&device_number, + 0, master_count, "EtherCAT")) { + EC_ERR("Failed to obtain device number(s)!\n"); + ret = -EBUSY; + goto out_return; + } + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0) + class = class_create(THIS_MODULE, "EtherCAT"); +#else + class = class_create("EtherCAT"); +#endif + if (IS_ERR(class)) { + EC_ERR("Failed to create device class.\n"); + ret = PTR_ERR(class); + goto out_cdev; + } + + // zero MAC addresses + memset(macs, 0x00, sizeof(uint8_t) * EC_MAX_MASTERS * 2 * ETH_ALEN); + + // process MAC parameters + for (i = 0; i < master_count; i++) { + ret = ec_mac_parse(macs[i][0], main_devices[i], 0); + if (ret) + goto out_class; + + if (i < backup_count) { + ret = ec_mac_parse(macs[i][1], backup_devices[i], 1); + if (ret) + goto out_class; + } + } + + // initialize static master variables + ec_master_init_static(); + + if (master_count) { + if (!(masters = kmalloc(sizeof(ec_master_t) * master_count, + GFP_KERNEL))) { + EC_ERR("Failed to allocate memory" + " for EtherCAT masters.\n"); + ret = -ENOMEM; + goto out_class; + } + } + + for (i = 0; i < master_count; i++) { + ret = ec_master_init(&masters[i], i, macs[i][0], macs[i][1], + device_number, class, debug_level, run_on_cpu); + if (ret) + goto out_free_masters; + } + + EC_INFO("%u master%s waiting for devices.\n", + master_count, (master_count == 1 ? "" : "s")); + return ret; + +out_free_masters: + for (i--; i >= 0; i--) + ec_master_clear(&masters[i]); + kfree(masters); +out_class: + class_destroy(class); +out_cdev: + if (master_count) + unregister_chrdev_region(device_number, master_count); +out_return: + return ret; +} + +/****************************************************************************/ + +/** Module cleanup. + * + * Clears all master instances. + */ +void __exit ec_cleanup_module(void) +{ + unsigned int i; + + for (i = 0; i < master_count; i++) { + ec_master_clear(&masters[i]); + } + + if (master_count) + kfree(masters); + + class_destroy(class); + + if (master_count) + unregister_chrdev_region(device_number, master_count); + + EC_INFO("Master module cleaned up.\n"); +} + +/****************************************************************************/ + +/** Get the number of masters. + */ +unsigned int ec_master_count(void) +{ + return master_count; +} + +/***************************************************************************** + * MAC address functions + ****************************************************************************/ + +/** + * \return true, if two MAC addresses are equal. + */ +int ec_mac_equal( + const uint8_t *mac1, /**< First MAC address. */ + const uint8_t *mac2 /**< Second MAC address. */ + ) +{ + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) + if (mac1[i] != mac2[i]) + return 0; + + return 1; +} + +/****************************************************************************/ + +/** Maximum MAC string size. + */ +#define EC_MAX_MAC_STRING_SIZE (3 * ETH_ALEN) + +/** Print a MAC address to a buffer. + * + * The buffer size must be at least EC_MAX_MAC_STRING_SIZE. + * + * \return number of bytes written. + */ +ssize_t ec_mac_print( + const uint8_t *mac, /**< MAC address */ + char *buffer /**< Target buffer. */ + ) +{ + off_t off = 0; + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) { + off += sprintf(buffer + off, "%02X", mac[i]); + if (i < ETH_ALEN - 1) off += sprintf(buffer + off, ":"); + } + + return off; +} + +/****************************************************************************/ + +/** + * \return true, if the MAC address is all-zero. + */ +int ec_mac_is_zero( + const uint8_t *mac /**< MAC address. */ + ) +{ + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) + if (mac[i]) + return 0; + + return 1; +} + +/****************************************************************************/ + +/** + * \return true, if the given MAC address is the broadcast address. + */ +int ec_mac_is_broadcast( + const uint8_t *mac /**< MAC address. */ + ) +{ + unsigned int i; + + for (i = 0; i < ETH_ALEN; i++) + if (mac[i] != 0xff) + return 0; + + return 1; +} + +/****************************************************************************/ + +/** Parse a MAC address from a string. + * + * The MAC address must match the regular expression + * "([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2}". + * + * \return 0 on success, else < 0 + */ +static int ec_mac_parse(uint8_t *mac, const char *src, int allow_empty) +{ + unsigned int i, value; + const char *orig = src; + char *rem; + + if (!strlen(src)) { + if (allow_empty){ + return 0; + } else { + EC_ERR("MAC address may not be empty.\n"); + return -EINVAL; + } + } + + for (i = 0; i < ETH_ALEN; i++) { + value = simple_strtoul(src, &rem, 16); + if (rem != src + 2 + || value > 0xFF + || (i < ETH_ALEN - 1 && *rem != ':')) { + EC_ERR("Invalid MAC address \"%s\".\n", orig); + return -EINVAL; + } + mac[i] = value; + if (i < ETH_ALEN - 1) { + src = rem + 1; // skip colon + } + } + + return 0; +} + +/****************************************************************************/ + +/** Outputs frame contents for debugging purposes. + * If the data block is larger than 256 bytes, only the first 128 + * and the last 128 bytes will be shown + */ +void ec_print_data(const uint8_t *data, /**< pointer to data */ + size_t size /**< number of bytes to output */ + ) +{ + unsigned int i; + + EC_DBG(""); + for (i = 0; i < size; i++) { + printk(KERN_CONT "%02X ", data[i]); + + if ((i + 1) % 16 == 0 && i < size - 1) { + printk(KERN_CONT "\n"); + EC_DBG(""); + } + + if (i + 1 == 128 && size > 256) { + printk(KERN_CONT "dropped %zu bytes\n", size - 128 - i); + i = size - 128; + EC_DBG(""); + } + } + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Outputs frame contents and differences for debugging purposes. + */ +void ec_print_data_diff(const uint8_t *d1, /**< first data */ + const uint8_t *d2, /**< second data */ + size_t size /** number of bytes to output */ + ) +{ + unsigned int i; + + EC_DBG(""); + for (i = 0; i < size; i++) { + if (d1[i] == d2[i]) { + printk(KERN_CONT ".. "); + } + else { + printk(KERN_CONT "%02X ", d2[i]); + } + if ((i + 1) % 16 == 0) { + printk(KERN_CONT "\n"); + EC_DBG(""); + } + } + printk(KERN_CONT "\n"); +} + +/****************************************************************************/ + +/** Prints slave states in clear text. + * + * \return Size of the created string. + */ +size_t ec_state_string(uint8_t states, /**< slave states */ + char *buffer, /**< target buffer + (min. EC_STATE_STRING_SIZE bytes) */ + uint8_t multi /**< Show multi-state mask. */ + ) +{ + off_t off = 0; + unsigned int first = 1; + + if (!states) { + off += sprintf(buffer + off, "(unknown)"); + return off; + } + + if (multi) { // multiple slaves + if (states & EC_SLAVE_STATE_INIT) { + off += sprintf(buffer + off, "INIT"); + first = 0; + } + if (states & EC_SLAVE_STATE_PREOP) { + if (!first) off += sprintf(buffer + off, ", "); + off += sprintf(buffer + off, "PREOP"); + first = 0; + } + if (states & EC_SLAVE_STATE_SAFEOP) { + if (!first) off += sprintf(buffer + off, ", "); + off += sprintf(buffer + off, "SAFEOP"); + first = 0; + } + if (states & EC_SLAVE_STATE_OP) { + if (!first) off += sprintf(buffer + off, ", "); + off += sprintf(buffer + off, "OP"); + } + } else { // single slave + if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_INIT) { + off += sprintf(buffer + off, "INIT"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_PREOP) { + off += sprintf(buffer + off, "PREOP"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_BOOT) { + off += sprintf(buffer + off, "BOOT"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_SAFEOP) { + off += sprintf(buffer + off, "SAFEOP"); + } else if ((states & EC_SLAVE_STATE_MASK) == EC_SLAVE_STATE_OP) { + off += sprintf(buffer + off, "OP"); + } else { + off += sprintf(buffer + off, "(invalid)"); + } + first = 0; + } + + if (states & EC_SLAVE_STATE_ACK_ERR) { + if (!first) off += sprintf(buffer + off, " + "); + off += sprintf(buffer + off, "ERROR"); + } + + return off; +} + +/***************************************************************************** + * Device interface + ****************************************************************************/ + +/** Device names. + */ +const char *ec_device_names[2] = { + "main", + "backup" +}; + +/** Offers an EtherCAT device to a certain master. + * + * The master decides, if it wants to use the device for EtherCAT operation, + * or not. It is important, that the offered net_device is not used by the + * kernel IP stack. If the master, accepted the offer, the address of the + * newly created EtherCAT device is returned, else \a NULL is returned. + * + * \return Pointer to device, if accepted, or NULL if declined. + * \ingroup DeviceInterface + */ +ec_device_t *ecdev_offer( + struct net_device *net_dev, /**< net_device to offer */ + ec_pollfunc_t poll, /**< device poll function */ + struct module *module /**< pointer to the module */ + ) +{ + ec_master_t *master; + char str[EC_MAX_MAC_STRING_SIZE]; + unsigned int i, dev_idx; + + for (i = 0; i < master_count; i++) { + master = &masters[i]; + ec_mac_print(net_dev->dev_addr, str); + + if (down_interruptible(&master->device_sem)) { + EC_MASTER_WARN(master, "%s() interrupted!\n", __func__); + return NULL; + } + + for (dev_idx = EC_DEVICE_MAIN; + dev_idx < ec_master_num_devices(master); dev_idx++) { + if (!master->devices[dev_idx].dev + && (ec_mac_equal(master->macs[dev_idx], net_dev->dev_addr) + || ec_mac_is_broadcast(master->macs[dev_idx]))) { + + EC_INFO("Accepting %s as %s device for master %u.\n", + str, ec_device_names[dev_idx != 0], master->index); + + ec_device_attach(&master->devices[dev_idx], + net_dev, poll, module); + up(&master->device_sem); + + snprintf(net_dev->name, IFNAMSIZ, "ec%c%u", + ec_device_names[dev_idx != 0][0], master->index); + + return &master->devices[dev_idx]; // offer accepted + } + } + + up(&master->device_sem); + + EC_MASTER_DBG(master, 1, "Master declined device %s.\n", str); + } + + return NULL; // offer declined +} + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +/** Request a master. + * + * Same as ecrt_request_master(), but with ERR_PTR() return value. + * + * \return Requested master. + */ +ec_master_t *ecrt_request_master_err( + unsigned int master_index /**< Master index. */ + ) +{ + ec_master_t *master, *errptr = NULL; + unsigned int dev_idx = EC_DEVICE_MAIN; + + EC_INFO("Requesting master %u...\n", master_index); + + if (master_index >= master_count) { + EC_ERR("Invalid master index %u.\n", master_index); + errptr = ERR_PTR(-EINVAL); + goto out_return; + } + master = &masters[master_index]; + + if (down_interruptible(&master_sem)) { + errptr = ERR_PTR(-EINTR); + goto out_return; + } + + if (master->reserved) { + up(&master_sem); + EC_MASTER_ERR(master, "Master already in use!\n"); + errptr = ERR_PTR(-EBUSY); + goto out_return; + } + master->reserved = 1; + up(&master_sem); + + if (down_interruptible(&master->device_sem)) { + errptr = ERR_PTR(-EINTR); + goto out_release; + } + + if (master->phase != EC_IDLE) { + up(&master->device_sem); + EC_MASTER_ERR(master, "Master still waiting for devices!\n"); + errptr = ERR_PTR(-ENODEV); + goto out_release; + } + + for (; dev_idx < ec_master_num_devices(master); dev_idx++) { + ec_device_t *device = &master->devices[dev_idx]; + if (!try_module_get(device->module)) { + up(&master->device_sem); + EC_MASTER_ERR(master, "Device module is unloading!\n"); + errptr = ERR_PTR(-ENODEV); + goto out_module_put; + } + } + + up(&master->device_sem); + + if (ec_master_enter_operation_phase(master)) { + EC_MASTER_ERR(master, "Failed to enter OPERATION phase!\n"); + errptr = ERR_PTR(-EIO); + goto out_module_put; + } + + EC_INFO("Successfully requested master %u.\n", master_index); + return master; + + out_module_put: + for (; dev_idx > 0; dev_idx--) { + ec_device_t *device = &master->devices[dev_idx - 1]; + module_put(device->module); + } + out_release: + master->reserved = 0; + out_return: + return errptr; +} + +/****************************************************************************/ + +ec_master_t *ecrt_request_master(unsigned int master_index) +{ + ec_master_t *master = ecrt_request_master_err(master_index); + return IS_ERR(master) ? NULL : master; +} + +/****************************************************************************/ + +void ecrt_release_master(ec_master_t *master) +{ + unsigned int dev_idx; + + EC_MASTER_INFO(master, "Releasing master...\n"); + + if (!master->reserved) { + EC_MASTER_WARN(master, "%s(): Master was was not requested!\n", + __func__); + return; + } + + ec_master_leave_operation_phase(master); + + for (dev_idx = EC_DEVICE_MAIN; dev_idx < ec_master_num_devices(master); + dev_idx++) { + module_put(master->devices[dev_idx].module); + } + + master->reserved = 0; + + EC_MASTER_INFO(master, "Released.\n"); +} + +/****************************************************************************/ + +unsigned int ecrt_version_magic(void) +{ + return ECRT_VERSION_MAGIC; +} + +/****************************************************************************/ + +/** Global request state type translation table. + * + * Translates an internal request state to an external one. + */ +const ec_request_state_t ec_request_state_translation_table[] = { + EC_REQUEST_UNUSED, // EC_INT_REQUEST_INIT, + EC_REQUEST_BUSY, // EC_INT_REQUEST_QUEUED, + EC_REQUEST_BUSY, // EC_INT_REQUEST_BUSY, + EC_REQUEST_SUCCESS, // EC_INT_REQUEST_SUCCESS, + EC_REQUEST_ERROR // EC_INT_REQUEST_FAILURE +}; + +/****************************************************************************/ + +/** \cond */ + +module_init(ec_init_module); +module_exit(ec_cleanup_module); + +EXPORT_SYMBOL(ecdev_offer); + +EXPORT_SYMBOL(ecrt_request_master); +EXPORT_SYMBOL(ecrt_release_master); +EXPORT_SYMBOL(ecrt_version_magic); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/pdo.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/pdo.c @@ -0,0 +1,309 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT process data object methods. +*/ + +/****************************************************************************/ + +#include +#include + +#include "pdo.h" + +/****************************************************************************/ + +/** PDO constructor. + */ +void ec_pdo_init( + ec_pdo_t *pdo /**< EtherCAT PDO */ + ) +{ + pdo->sync_index = -1; // not assigned + pdo->name = NULL; + INIT_LIST_HEAD(&pdo->entries); +} + +/****************************************************************************/ + +/** PDO copy constructor. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_init_copy( + ec_pdo_t *pdo, /**< PDO to create. */ + const ec_pdo_t *other_pdo /**< PDO to copy from. */ + ) +{ + int ret = 0; + + pdo->index = other_pdo->index; + pdo->sync_index = other_pdo->sync_index; + pdo->name = NULL; + INIT_LIST_HEAD(&pdo->entries); + + ret = ec_pdo_set_name(pdo, other_pdo->name); + if (ret < 0) + goto out_return; + + ret = ec_pdo_copy_entries(pdo, other_pdo); + if (ret < 0) + goto out_clear; + + return 0; + +out_clear: + ec_pdo_clear(pdo); +out_return: + return ret; +} + +/****************************************************************************/ + +/** PDO destructor. + */ +void ec_pdo_clear(ec_pdo_t *pdo /**< EtherCAT PDO. */) +{ + if (pdo->name) + kfree(pdo->name); + + ec_pdo_clear_entries(pdo); +} + +/****************************************************************************/ + +/** Clear PDO entry list. + */ +void ec_pdo_clear_entries(ec_pdo_t *pdo /**< EtherCAT PDO. */) +{ + ec_pdo_entry_t *entry, *next; + + // free all PDO entries + list_for_each_entry_safe(entry, next, &pdo->entries, list) { + list_del(&entry->list); + ec_pdo_entry_clear(entry); + kfree(entry); + } +} + +/****************************************************************************/ + +/** Set PDO name. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_set_name( + ec_pdo_t *pdo, /**< PDO. */ + const char *name /**< New name. */ + ) +{ + unsigned int len; + + if (pdo->name && name && !strcmp(pdo->name, name)) + return 0; + + if (pdo->name) + kfree(pdo->name); + + if (name && (len = strlen(name))) { + if (!(pdo->name = (char *) kmalloc(len + 1, GFP_KERNEL))) { + EC_ERR("Failed to allocate PDO name.\n"); + return -ENOMEM; + } + memcpy(pdo->name, name, len + 1); + } else { + pdo->name = NULL; + } + + return 0; +} + +/****************************************************************************/ + +/** Add a new PDO entry to the configuration. + * + * \retval Pointer to the added entry, otherwise a ERR_PTR() code. + */ +ec_pdo_entry_t *ec_pdo_add_entry( + ec_pdo_t *pdo, /**< PDO. */ + uint16_t index, /**< New entry's index. */ + uint8_t subindex, /**< New entry's subindex. */ + uint8_t bit_length /**< New entry's bit length. */ + ) +{ + ec_pdo_entry_t *entry; + + if (!(entry = kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate memory for PDO entry.\n"); + return ERR_PTR(-ENOMEM); + } + + ec_pdo_entry_init(entry); + entry->index = index; + entry->subindex = subindex; + entry->bit_length = bit_length; + list_add_tail(&entry->list, &pdo->entries); + return entry; +} + +/****************************************************************************/ + +/** Copy PDO entries from another PDO. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_copy_entries( + ec_pdo_t *pdo, /**< PDO whos entries shall be replaced. */ + const ec_pdo_t *other /**< Pdo with entries to copy. */ + ) +{ + ec_pdo_entry_t *entry, *other_entry; + int ret; + + ec_pdo_clear_entries(pdo); + + list_for_each_entry(other_entry, &other->entries, list) { + if (!(entry = (ec_pdo_entry_t *) + kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate memory for PDO entry copy.\n"); + return -ENOMEM; + } + + ret = ec_pdo_entry_init_copy(entry, other_entry); + if (ret < 0) { + kfree(entry); + return ret; + } + + list_add_tail(&entry->list, &pdo->entries); + } + + return 0; +} + +/****************************************************************************/ + +/** Compares the entries of two PDOs. + * + * \retval 1 The entries of the given PDOs are equal. + * \retval 0 The entries of the given PDOs differ. + */ +int ec_pdo_equal_entries( + const ec_pdo_t *pdo1, /**< First PDO. */ + const ec_pdo_t *pdo2 /**< Second PDO. */ + ) +{ + const struct list_head *head1, *head2, *item1, *item2; + const ec_pdo_entry_t *entry1, *entry2; + + head1 = item1 = &pdo1->entries; + head2 = item2 = &pdo2->entries; + + while (1) { + item1 = item1->next; + item2 = item2->next; + + if ((item1 == head1) ^ (item2 == head2)) // unequal lengths + return 0; + if (item1 == head1) // both finished + break; + + entry1 = list_entry(item1, ec_pdo_entry_t, list); + entry2 = list_entry(item2, ec_pdo_entry_t, list); + if (!ec_pdo_entry_equal(entry1, entry2)) + return 0; + } + + return 1; +} + +/****************************************************************************/ + +/** Get the number of PDO entries. + * + * \return Number of PDO entries. + */ +unsigned int ec_pdo_entry_count( + const ec_pdo_t *pdo /**< PDO. */ + ) +{ + const ec_pdo_entry_t *entry; + unsigned int num = 0; + + list_for_each_entry(entry, &pdo->entries, list) { + num++; + } + + return num; +} + +/****************************************************************************/ + +/** Finds a PDO entry via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_pdo_entry_t *ec_pdo_find_entry_by_pos_const( + const ec_pdo_t *pdo, /**< PDO. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_pdo_entry_t *entry; + + list_for_each_entry(entry, &pdo->entries, list) { + if (pos--) + continue; + return entry; + } + + return NULL; +} + +/****************************************************************************/ + +/** Outputs the PDOs in the list. + */ +void ec_pdo_print_entries( + const ec_pdo_t *pdo /**< PDO. */ + ) +{ + const ec_pdo_entry_t *entry; + + if (list_empty(&pdo->entries)) { + printk(KERN_CONT "(none)"); + } else { + list_for_each_entry(entry, &pdo->entries, list) { + printk(KERN_CONT "0x%04X:%02X/%u", + entry->index, entry->subindex, entry->bit_length); + if (entry->list.next != &pdo->entries) + printk(KERN_CONT " "); + } + } +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/pdo.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/pdo.h @@ -0,0 +1,67 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT Process data object structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_PDO_H__ +#define __EC_PDO_H__ + +#include + +#include "globals.h" +#include "pdo_entry.h" + +/****************************************************************************/ + +/** PDO description. + */ +typedef struct { + struct list_head list; /**< List item. */ + uint16_t index; /**< PDO index. */ + int8_t sync_index; /**< Assigned sync manager. \todo remove? */ + char *name; /**< PDO name. */ + struct list_head entries; /**< List of PDO entries. */ +} ec_pdo_t; + +/****************************************************************************/ + +void ec_pdo_init(ec_pdo_t *); +int ec_pdo_init_copy(ec_pdo_t *, const ec_pdo_t *); +void ec_pdo_clear(ec_pdo_t *); +void ec_pdo_clear_entries(ec_pdo_t *); +int ec_pdo_set_name(ec_pdo_t *, const char *); +ec_pdo_entry_t *ec_pdo_add_entry(ec_pdo_t *, uint16_t, uint8_t, uint8_t); +int ec_pdo_copy_entries(ec_pdo_t *, const ec_pdo_t *); +int ec_pdo_equal_entries(const ec_pdo_t *, const ec_pdo_t *); +unsigned int ec_pdo_entry_count(const ec_pdo_t *); +const ec_pdo_entry_t *ec_pdo_find_entry_by_pos_const( + const ec_pdo_t *, unsigned int); + +void ec_pdo_print_entries(const ec_pdo_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/pdo_entry.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/pdo_entry.c @@ -0,0 +1,124 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT process data object entry methods. +*/ + +/****************************************************************************/ + +#include + +#include "pdo_entry.h" + +/****************************************************************************/ + +/** PDO entry constructor. + */ +void ec_pdo_entry_init( + ec_pdo_entry_t *entry /**< PDO entry. */ + ) +{ + entry->name = NULL; +} + +/****************************************************************************/ + +/** PDO entry copy constructor. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_entry_init_copy( + ec_pdo_entry_t *entry, /**< PDO entry. */ + const ec_pdo_entry_t *other /**< PDO entry to copy from. */ + ) +{ + entry->index = other->index; + entry->subindex = other->subindex; + entry->name = NULL; + entry->bit_length = other->bit_length; + + return ec_pdo_entry_set_name(entry, other->name); +} + +/****************************************************************************/ + +/** PDO entry destructor. + */ +void ec_pdo_entry_clear(ec_pdo_entry_t *entry /**< PDO entry. */) +{ + if (entry->name) + kfree(entry->name); +} + +/****************************************************************************/ + +/** Set PDO entry name. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_pdo_entry_set_name( + ec_pdo_entry_t *entry, /**< PDO entry. */ + const char *name /**< New name. */ + ) +{ + unsigned int len; + + if (entry->name && name && !strcmp(entry->name, name)) + return 0; + + if (entry->name) + kfree(entry->name); + + if (name && (len = strlen(name))) { + if (!(entry->name = (char *) kmalloc(len + 1, GFP_KERNEL))) { + EC_ERR("Failed to allocate PDO entry name.\n"); + return -ENOMEM; + } + memcpy(entry->name, name, len + 1); + } else { + entry->name = NULL; + } + + return 0; +} + +/****************************************************************************/ + +/** Compares two PDO entries. + * + * \retval 1 The entries are equal. + * \retval 0 The entries differ. + */ +int ec_pdo_entry_equal( + const ec_pdo_entry_t *entry1, /**< First PDO entry. */ + const ec_pdo_entry_t *entry2 /**< Second PDO entry. */ + ) +{ + return entry1->index == entry2->index + && entry1->subindex == entry2->subindex + && entry1->bit_length == entry2->bit_length; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/pdo_entry.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/pdo_entry.h @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT Process data object structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_PDO_ENTRY_H__ +#define __EC_PDO_ENTRY_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** PDO entry description. + */ +typedef struct { + struct list_head list; /**< list item */ + uint16_t index; /**< PDO entry index */ + uint8_t subindex; /**< PDO entry subindex */ + char *name; /**< entry name */ + uint8_t bit_length; /**< entry length in bit */ +} ec_pdo_entry_t; + +/****************************************************************************/ + +void ec_pdo_entry_init(ec_pdo_entry_t *); +int ec_pdo_entry_init_copy(ec_pdo_entry_t *, const ec_pdo_entry_t *); +void ec_pdo_entry_clear(ec_pdo_entry_t *); +int ec_pdo_entry_set_name(ec_pdo_entry_t *, const char *); +int ec_pdo_entry_equal(const ec_pdo_entry_t *, const ec_pdo_entry_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/pdo_list.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/pdo_list.c @@ -0,0 +1,338 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT PDO list methods. +*/ + +/****************************************************************************/ + +#include + +#include "globals.h" +#include "pdo.h" +#include "slave_config.h" +#include "master.h" + +#include "pdo_list.h" + +/****************************************************************************/ + +/** PDO list constructor. + */ +void ec_pdo_list_init( + ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + INIT_LIST_HEAD(&pl->list); +} + +/****************************************************************************/ + +/** PDO list destructor. + */ +void ec_pdo_list_clear(ec_pdo_list_t *pl /**< PDO list. */) +{ + ec_pdo_list_clear_pdos(pl); +} + +/****************************************************************************/ + +/** Clears the list of mapped PDOs. + */ +void ec_pdo_list_clear_pdos(ec_pdo_list_t *pl /**< PDO list. */) +{ + ec_pdo_t *pdo, *next; + + list_for_each_entry_safe(pdo, next, &pl->list, list) { + list_del_init(&pdo->list); + ec_pdo_clear(pdo); + kfree(pdo); + } +} + +/****************************************************************************/ + +/** Calculates the total size of the mapped PDO entries. + * + * \retval Data size in byte. + */ +uint16_t ec_pdo_list_total_size( + const ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + unsigned int bit_size; + const ec_pdo_t *pdo; + const ec_pdo_entry_t *pdo_entry; + uint16_t byte_size; + + bit_size = 0; + list_for_each_entry(pdo, &pl->list, list) { + list_for_each_entry(pdo_entry, &pdo->entries, list) { + bit_size += pdo_entry->bit_length; + } + } + + if (bit_size % 8) // round up to full bytes + byte_size = bit_size / 8 + 1; + else + byte_size = bit_size / 8; + + return byte_size; +} + +/****************************************************************************/ + +/** Add a new PDO to the list. + * + * \return Pointer to new PDO, otherwise an ERR_PTR() code. + */ +ec_pdo_t *ec_pdo_list_add_pdo( + ec_pdo_list_t *pl, /**< PDO list. */ + uint16_t index /**< PDO index. */ + ) +{ + ec_pdo_t *pdo; + + if (!(pdo = (ec_pdo_t *) kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate memory for PDO.\n"); + return ERR_PTR(-ENOMEM); + } + + ec_pdo_init(pdo); + pdo->index = index; + list_add_tail(&pdo->list, &pl->list); + return pdo; +} + +/****************************************************************************/ + +/** Add the copy of an existing PDO to the list. + * + * \return 0 on success, else < 0 + */ +int ec_pdo_list_add_pdo_copy( + ec_pdo_list_t *pl, /**< PDO list. */ + const ec_pdo_t *pdo /**< PDO to add. */ + ) +{ + ec_pdo_t *mapped_pdo; + int ret; + + // PDO already mapped? + list_for_each_entry(mapped_pdo, &pl->list, list) { + if (mapped_pdo->index != pdo->index) continue; + EC_ERR("PDO 0x%04X is already mapped!\n", pdo->index); + return -EEXIST; + } + + if (!(mapped_pdo = kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_ERR("Failed to allocate PDO memory.\n"); + return -ENOMEM; + } + + ret = ec_pdo_init_copy(mapped_pdo, pdo); + if (ret < 0) { + kfree(mapped_pdo); + return ret; + } + + list_add_tail(&mapped_pdo->list, &pl->list); + return 0; +} + +/****************************************************************************/ + +/** Makes a deep copy of another PDO list. + * + * \return 0 on success, else < 0 + */ +int ec_pdo_list_copy( + ec_pdo_list_t *pl, /**< PDO list. */ + const ec_pdo_list_t *other /**< PDO list to copy from. */ + ) +{ + ec_pdo_t *other_pdo; + int ret; + + ec_pdo_list_clear_pdos(pl); + + // PDO already mapped? + list_for_each_entry(other_pdo, &other->list, list) { + ret = ec_pdo_list_add_pdo_copy(pl, other_pdo); + if (ret) + return ret; + } + + return 0; +} + +/****************************************************************************/ + +/** Compares two PDO lists. + * + * Only the list is compared, not the PDO entries (i. e. the PDO + * mapping). + * + * \retval 1 The given PDO lists are equal. + * \retval 0 The given PDO lists differ. + */ +int ec_pdo_list_equal( + const ec_pdo_list_t *pl1, /**< First list. */ + const ec_pdo_list_t *pl2 /**< Second list. */ + ) +{ + const struct list_head *h1, *h2, *l1, *l2; + const ec_pdo_t *p1, *p2; + + h1 = l1 = &pl1->list; + h2 = l2 = &pl2->list; + + while (1) { + l1 = l1->next; + l2 = l2->next; + + if ((l1 == h1) ^ (l2 == h2)) // unequal lengths + return 0; + if (l1 == h1) // both finished + break; + + p1 = list_entry(l1, ec_pdo_t, list); + p2 = list_entry(l2, ec_pdo_t, list); + + if (p1->index != p2->index) + return 0; + } + + return 1; +} + +/****************************************************************************/ + +/** Finds a PDO with the given index. + * + * \return Search result, or NULL. + */ +ec_pdo_t *ec_pdo_list_find_pdo( + const ec_pdo_list_t *pl, /**< PDO list. */ + uint16_t index /**< PDO index. */ + ) +{ + ec_pdo_t *pdo; + + list_for_each_entry(pdo, &pl->list, list) { + if (pdo->index != index) + continue; + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a PDO with the given index and returns a const pointer. + * + * \return Search result, or NULL. + */ +const ec_pdo_t *ec_pdo_list_find_pdo_const( + const ec_pdo_list_t *pl, /**< PDO list. */ + uint16_t index /**< PDO index. */ + ) +{ + const ec_pdo_t *pdo; + + list_for_each_entry(pdo, &pl->list, list) { + if (pdo->index != index) + continue; + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a PDO via its position in the list. + * + * Const version. + * + * \return Zero on success, otherwise a negative error code. + */ +const ec_pdo_t *ec_pdo_list_find_pdo_by_pos_const( + const ec_pdo_list_t *pl, /**< PDO list. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_pdo_t *pdo; + + list_for_each_entry(pdo, &pl->list, list) { + if (pos--) + continue; + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of PDOs in the list. + * + * \return Number of PDOs. + */ +unsigned int ec_pdo_list_count( + const ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + const ec_pdo_t *pdo; + unsigned int num = 0; + + list_for_each_entry(pdo, &pl->list, list) { + num++; + } + + return num; +} + +/****************************************************************************/ + +/** Outputs the PDOs in the list. + */ +void ec_pdo_list_print( + const ec_pdo_list_t *pl /**< PDO list. */ + ) +{ + const ec_pdo_t *pdo; + + if (list_empty(&pl->list)) { + printk(KERN_CONT "(none)"); + } else { + list_for_each_entry(pdo, &pl->list, list) { + printk(KERN_CONT "0x%04X", pdo->index); + if (pdo->list.next != &pl->list) + printk(KERN_CONT " "); + } + } +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/pdo_list.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/pdo_list.h @@ -0,0 +1,71 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT PDO list structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_PDO_LIST_H__ +#define __EC_PDO_LIST_H__ + +#include + +#include "globals.h" +#include "pdo.h" + +/****************************************************************************/ + +/** EtherCAT PDO list. + */ +typedef struct { + struct list_head list; /**< List of PDOs. */ +} ec_pdo_list_t; + +/****************************************************************************/ + +void ec_pdo_list_init(ec_pdo_list_t *); +void ec_pdo_list_clear(ec_pdo_list_t *); + +void ec_pdo_list_clear_pdos(ec_pdo_list_t *); + +ec_pdo_t *ec_pdo_list_add_pdo(ec_pdo_list_t *, uint16_t); +int ec_pdo_list_add_pdo_copy(ec_pdo_list_t *, const ec_pdo_t *); + +int ec_pdo_list_copy(ec_pdo_list_t *, const ec_pdo_list_t *); + +uint16_t ec_pdo_list_total_size(const ec_pdo_list_t *); +int ec_pdo_list_equal(const ec_pdo_list_t *, const ec_pdo_list_t *); + +ec_pdo_t *ec_pdo_list_find_pdo(const ec_pdo_list_t *, uint16_t); +const ec_pdo_t *ec_pdo_list_find_pdo_const(const ec_pdo_list_t *, + uint16_t); +const ec_pdo_t *ec_pdo_list_find_pdo_by_pos_const( + const ec_pdo_list_t *, unsigned int); +unsigned int ec_pdo_list_count(const ec_pdo_list_t *); + +void ec_pdo_list_print(const ec_pdo_list_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/reg_request.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/reg_request.c @@ -0,0 +1,125 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Register request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "reg_request.h" + +/****************************************************************************/ + +/** Register request constructor. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_reg_request_init( + ec_reg_request_t *reg, /**< Register request. */ + size_t size /**< Memory size. */ + ) +{ + if (!(reg->data = (uint8_t *) kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of register memory.\n", size); + return -ENOMEM; + } + + INIT_LIST_HEAD(®->list); + reg->mem_size = size; + memset(reg->data, 0x00, size); + reg->dir = EC_DIR_INVALID; + reg->address = 0; + reg->transfer_size = 0; + reg->state = EC_INT_REQUEST_INIT; + reg->ring_position = 0; + return 0; +} + +/****************************************************************************/ + +/** Register request destructor. + */ +void ec_reg_request_clear( + ec_reg_request_t *reg /**< Register request. */ + ) +{ + if (reg->data) { + kfree(reg->data); + } +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +uint8_t *ecrt_reg_request_data(const ec_reg_request_t *reg) +{ + return reg->data; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_reg_request_state(const ec_reg_request_t *reg) +{ + return ec_request_state_translation_table[reg->state]; +} + +/****************************************************************************/ + +int ecrt_reg_request_write(ec_reg_request_t *reg, uint16_t address, + size_t size) +{ + reg->dir = EC_DIR_OUTPUT; + reg->address = address; + reg->transfer_size = min(size, reg->mem_size); + reg->state = EC_INT_REQUEST_QUEUED; + return 0; +} + +/****************************************************************************/ + +int ecrt_reg_request_read(ec_reg_request_t *reg, uint16_t address, + size_t size) +{ + reg->dir = EC_DIR_INPUT; + reg->address = address; + reg->transfer_size = min(size, reg->mem_size); + reg->state = EC_INT_REQUEST_QUEUED; + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_reg_request_data); +EXPORT_SYMBOL(ecrt_reg_request_state); +EXPORT_SYMBOL(ecrt_reg_request_write); +EXPORT_SYMBOL(ecrt_reg_request_read); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/reg_request.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/reg_request.h @@ -0,0 +1,59 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT register request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_REG_REQUEST_H__ +#define __EC_REG_REQUEST_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** Register request. + */ +struct ec_reg_request { + struct list_head list; /**< List item. */ + size_t mem_size; /**< Size of data memory. */ + uint8_t *data; /**< Pointer to data memory. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means writing to the + slave, EC_DIR_INPUT means reading from the slave. */ + uint16_t address; /**< Register address. */ + size_t transfer_size; /**< Size of the data to transfer. */ + ec_internal_request_state_t state; /**< Request state. */ + uint16_t ring_position; /**< Ring position for emergency requests. */ +}; + +/****************************************************************************/ + +int ec_reg_request_init(ec_reg_request_t *, size_t); +void ec_reg_request_clear(ec_reg_request_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/rt_locks.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/rt_locks.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Abstract locks for realtime part of interface. +*/ + +/****************************************************************************/ + +#ifndef __EC_LOCKS_H__ +#define __EC_LOCKS_H__ + +#include "globals.h" +#include + +#include + +/****************************************************************************/ + +#ifdef EC_USE_RTMUTEX + +#include + +typedef struct rt_mutex ec_lock_t; + +static inline void ec_lock_init(ec_lock_t *sem) { rt_mutex_init(sem); } +static inline void ec_lock_down(ec_lock_t *sem) { rt_mutex_lock(sem); } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 34) +static inline int ec_lock_down_interruptible(ec_lock_t *sem) { + return rt_mutex_lock_interruptible(sem); +} +#else +static inline int ec_lock_down_interruptible(ec_lock_t *sem) { + return rt_mutex_lock_interruptible(sem, 1); +} +#endif +static inline void ec_lock_up(ec_lock_t *sem) { rt_mutex_unlock(sem); } + +#else + +typedef struct semaphore ec_lock_t; + +static inline void ec_lock_init(ec_lock_t *sem) { sema_init(sem, 1); } +static inline void ec_lock_down(ec_lock_t *sem) { down(sem); } +static inline int ec_lock_down_interruptible(ec_lock_t *sem) { + return down_interruptible(sem); +} +static inline void ec_lock_up(ec_lock_t *sem) { up(sem); } + +#endif + +/****************************************************************************/ + +#endif + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/rtdm.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/rtdm.c @@ -0,0 +1,259 @@ +/***************************************************************************** + * + * Copyright (C) 2009-2010 Moehwald GmbH B. Benner + * 2011 IgH Andreas Stewering-Bone + * 2012 Florian Pose + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +/** \file + * RTDM interface. + */ + +#include +#include +#include + + +#include "master.h" +#include "ioctl.h" +#include "rtdm.h" +#include "rtdm_details.h" + +/* include last because it does some redefinitions */ +#include + +/** Set to 1 to enable device operations debugging. + */ +#define DEBUG 0 + +/****************************************************************************/ + +static int ec_rtdm_open(struct rtdm_dev_context *, rtdm_user_info_t *, int); +static int ec_rtdm_close(struct rtdm_dev_context *, rtdm_user_info_t *); +static int ec_rtdm_ioctl_nrt_handler(struct rtdm_dev_context *, + rtdm_user_info_t *, unsigned int, void __user *); +static int ec_rtdm_ioctl_rt_handler(struct rtdm_dev_context *, + rtdm_user_info_t *, unsigned int, void __user *); + +/****************************************************************************/ + +/** Initialize an RTDM device. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_rtdm_dev_init( + ec_rtdm_dev_t *rtdm_dev, /**< EtherCAT RTDM device. */ + ec_master_t *master /**< EtherCAT master. */ + ) +{ + int ret; + + rtdm_dev->master = master; + + rtdm_dev->dev = kzalloc(sizeof(struct rtdm_device), GFP_KERNEL); + if (!rtdm_dev->dev) { + EC_MASTER_ERR(master, "Failed to reserve memory for RTDM device.\n"); + return -ENOMEM; + } + + rtdm_dev->dev->struct_version = RTDM_DEVICE_STRUCT_VER; + rtdm_dev->dev->device_flags = RTDM_NAMED_DEVICE; + rtdm_dev->dev->context_size = sizeof(ec_rtdm_context_t); + snprintf(rtdm_dev->dev->device_name, RTDM_MAX_DEVNAME_LEN, + "EtherCAT%u", master->index); + rtdm_dev->dev->open_nrt = ec_rtdm_open; + rtdm_dev->dev->ops.close_nrt = ec_rtdm_close; + rtdm_dev->dev->ops.ioctl_rt = ec_rtdm_ioctl_rt_handler; + rtdm_dev->dev->ops.ioctl_nrt = ec_rtdm_ioctl_nrt_handler; + rtdm_dev->dev->device_class = RTDM_CLASS_EXPERIMENTAL; + rtdm_dev->dev->device_sub_class = 222; + rtdm_dev->dev->driver_name = "EtherCAT"; + rtdm_dev->dev->driver_version = RTDM_DRIVER_VER(1, 0, 2); + rtdm_dev->dev->peripheral_name = rtdm_dev->dev->device_name; + rtdm_dev->dev->provider_name = "EtherLab Community"; + rtdm_dev->dev->proc_name = rtdm_dev->dev->device_name; + rtdm_dev->dev->device_data = rtdm_dev; /* pointer to parent */ + + EC_MASTER_INFO(master, "Registering RTDM device %s.\n", + rtdm_dev->dev->driver_name); + ret = rtdm_dev_register(rtdm_dev->dev); + if (ret) { + EC_MASTER_ERR(master, "Initialization of RTDM interface failed" + " (return value %i).\n", ret); + kfree(rtdm_dev->dev); + } + + return ret; +} + +/****************************************************************************/ + +/** Clear an RTDM device. + */ +void ec_rtdm_dev_clear( + ec_rtdm_dev_t *rtdm_dev /**< EtherCAT RTDM device. */ + ) +{ + int ret; + + EC_MASTER_INFO(rtdm_dev->master, "Unregistering RTDM device %s.\n", + rtdm_dev->dev->driver_name); + ret = rtdm_dev_unregister(rtdm_dev->dev, 1000 /* poll delay [ms] */); + if (ret < 0) { + EC_MASTER_WARN(rtdm_dev->master, + "Failed to unregister RTDM device (code %i).\n", ret); + } + + kfree(rtdm_dev->dev); +} + +/****************************************************************************/ + +/** Driver open. + * + * \return Always zero (success). + */ +static int ec_rtdm_open( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info, /**< User data. */ + int oflags /**< Open flags. */ + ) +{ + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; +#if DEBUG + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; +#endif + + ctx->user_fd = user_info; + ctx->ioctl_ctx.writable = oflags & O_WRONLY || oflags & O_RDWR; + ctx->ioctl_ctx.requested = 0; + ctx->ioctl_ctx.process_data = NULL; + ctx->ioctl_ctx.process_data_size = 0; + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s opened.\n", + context->device->device_name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Driver close. + * + * \return Always zero (success). + */ +static int ec_rtdm_close( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info /**< User data. */ + ) +{ + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; + + if (ctx->ioctl_ctx.requested) { + ecrt_release_master(rtdm_dev->master); + } + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s closed.\n", + context->device->device_name); +#endif + return 0; +} + +/****************************************************************************/ + +/** Driver ioctl. + * + * \return ioctl() return code. + */ +static int ec_rtdm_ioctl_nrt_handler( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info, /**< User data. */ + unsigned int request, /**< Request. */ + void __user *arg /**< Argument. */ + ) +{ + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "ioctl(request = %u, ctl = %02x)" + " on RTDM device %s.\n", request, _IOC_NR(request), + context->device->device_name); +#endif + return ec_ioctl_rtdm_nrt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); +} + +/****************************************************************************/ + +static int ec_rtdm_ioctl_rt_handler( + struct rtdm_dev_context *context, /**< Context. */ + rtdm_user_info_t *user_info, /**< User data. */ + unsigned int request, /**< Request. */ + void __user *arg /**< Argument. */ + ) +{ + int result; + ec_rtdm_context_t *ctx = (ec_rtdm_context_t *) context->dev_private; + ec_rtdm_dev_t *rtdm_dev = (ec_rtdm_dev_t *) context->device->device_data; + +#if DEBUG + EC_MASTER_INFO(rtdm_dev->master, "ioctl(request = %u, ctl = %02x)" + " on RTDM device %s.\n", request, _IOC_NR(request), + context->device->device_name); +#endif + result = + ec_ioctl_rtdm_rt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); + + if (result == -ENOTTY) { + /* Try again with nrt ioctl handler above in secondary mode. */ + return -ENOSYS; + } + return result; +} + +/****************************************************************************/ + +/** Memory-map process data to user space. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_rtdm_mmap( + ec_ioctl_context_t *ioctl_ctx, /**< Context. */ + void **user_address /**< Userspace address. */ + ) +{ + ec_rtdm_context_t *ctx = + container_of(ioctl_ctx, ec_rtdm_context_t, ioctl_ctx); + int ret; + + ret = rtdm_mmap_to_user(ctx->user_fd, + ioctl_ctx->process_data, ioctl_ctx->process_data_size, + PROT_READ | PROT_WRITE, + user_address, + NULL, NULL); + if (ret < 0) { + return ret; + } + + return 0; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/rtdm.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/rtdm.h @@ -0,0 +1,50 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Florian Pose + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +/** \file + * RTDM interface. + */ + +#ifndef __EC_RTDM_H__ +#define __EC_RTDM_H__ + +#include "../include/ecrt.h" /* ec_master_t */ + +/****************************************************************************/ + +struct rtdm_device; + +/****************************************************************************/ + +/** EtherCAT RTDM device. + */ +typedef struct ec_rtdm_dev { + ec_master_t *master; /**< Master pointer. */ + struct rtdm_device *dev; /**< RTDM device. */ +} ec_rtdm_dev_t; + +/****************************************************************************/ + +int ec_rtdm_dev_init(ec_rtdm_dev_t *, ec_master_t *); +void ec_rtdm_dev_clear(ec_rtdm_dev_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/rtdm_details.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/rtdm_details.h @@ -0,0 +1,60 @@ +/***************************************************************************** + * + * Copyright (C) 2024 Bjarne von Horn + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +#ifndef __EC_RTDM_DETAILS_H__ +#define __EC_RTDM_DETAILS_H__ + +#include "../config.h" +#include "ioctl.h" + +#include + +#ifdef EC_RTDM_XENOMAI_V3 + +#include +#define EC_RTDM_USERFD_T struct rtdm_fd + +#else // EC_RTDM_XENOMAI_V3 + +#include + +#define EC_RTDM_USERFD_T rtdm_user_info_t + +#endif // EC_RTDM_XENOMAI_V3 + +/****************************************************************************/ + +/** Context structure for an open RTDM file handle. + */ +typedef struct ec_rtdm_context { + EC_RTDM_USERFD_T *user_fd; /**< RTDM user data. */ + ec_ioctl_context_t ioctl_ctx; /**< Context structure. */ +} ec_rtdm_context_t; + +/****************************************************************************/ + +static inline EC_RTDM_USERFD_T *ec_ioctl_to_rtdm(ec_ioctl_context_t *ctx) +{ + return container_of(ctx, ec_rtdm_context_t, ioctl_ctx)->user_fd; +} + +/****************************************************************************/ + +#endif // __EC_RTDM_DETAILS_H__ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/rtdm_xenomai_v3.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/rtdm_xenomai_v3.c @@ -0,0 +1,193 @@ +/***************************************************************************** + * + * Copyright (C) 2009-2010 Moehwald GmbH B. Benner + * 2011 IgH Andreas Stewering-Bone + * 2012 Florian Pose + * + * This file is part of the IgH EtherCAT master. + * + * The IgH EtherCAT master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; version 2 of the License. + * + * The IgH EtherCAT master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT master. If not, see . + * + ****************************************************************************/ + +/** \file + * RTDM interface. + */ + +#include +#include +#include + +#include "master.h" +#include "ioctl.h" +#include "rtdm.h" +#include "rtdm_details.h" + +/** Set to 1 to enable device operations debugging. + */ +#define DEBUG_RTDM 0 + +/****************************************************************************/ + +static int ec_rtdm_open(struct rtdm_fd *fd, int oflags) +{ + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); +#if DEBUG_RTDM + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; +#endif + + ctx->user_fd = fd; + + ctx->ioctl_ctx.writable = oflags & O_WRONLY || oflags & O_RDWR; + ctx->ioctl_ctx.requested = 0; + ctx->ioctl_ctx.process_data = NULL; + ctx->ioctl_ctx.process_data_size = 0; + +#if DEBUG_RTDM + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s opened.\n", + dev->name); +#endif + + return 0; +} + +/****************************************************************************/ + +static void ec_rtdm_close(struct rtdm_fd *fd) +{ + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; + + if (ctx->ioctl_ctx.requested) + ecrt_release_master(rtdm_dev->master); + + if (ctx->ioctl_ctx.process_data) + vfree(ctx->ioctl_ctx.process_data); + +#if DEBUG_RTDM + EC_MASTER_INFO(rtdm_dev->master, "RTDM device %s closed.\n", + dev->name); +#endif +} + +/****************************************************************************/ + +static int ec_rtdm_ioctl_rt_handler(struct rtdm_fd *fd, unsigned int request, + void __user *arg) +{ + int result; + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; + + result = + ec_ioctl_rtdm_rt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); + + if (result == -ENOTTY) + /* Try again with nrt ioctl handler below in secondary mode. */ + return -ENOSYS; + + return result; +} + +/****************************************************************************/ + +static int ec_rtdm_ioctl_nrt_handler(struct rtdm_fd *fd, unsigned int request, + void __user *arg) +{ + struct ec_rtdm_context *ctx = rtdm_fd_to_private(fd); + struct rtdm_device *dev = rtdm_fd_device(fd); + ec_rtdm_dev_t *rtdm_dev = dev->device_data; + + return ec_ioctl_rtdm_nrt(rtdm_dev->master, &ctx->ioctl_ctx, request, arg); +} + +/****************************************************************************/ + +static int ec_rtdm_mmap(struct rtdm_fd *fd, struct vm_area_struct *vma) +{ + struct ec_rtdm_context *ctx = + (struct ec_rtdm_context *) rtdm_fd_to_private(fd); + return rtdm_mmap_kmem(vma, (void *)ctx->ioctl_ctx.process_data); +} + +/****************************************************************************/ + +static struct rtdm_driver ec_rtdm_driver = { + .profile_info = RTDM_PROFILE_INFO(ec_rtdm, + RTDM_CLASS_EXPERIMENTAL, + 222, + 0), + .device_flags = RTDM_NAMED_DEVICE, + .device_count = EC_MAX_MASTERS, + .context_size = sizeof(struct ec_rtdm_context), + .ops = { + .open = ec_rtdm_open, + .close = ec_rtdm_close, + .ioctl_rt = ec_rtdm_ioctl_rt_handler, + .ioctl_nrt = ec_rtdm_ioctl_nrt_handler, + .mmap = ec_rtdm_mmap, + }, +}; + +/****************************************************************************/ + +int ec_rtdm_dev_init(ec_rtdm_dev_t *rtdm_dev, ec_master_t *master) +{ + struct rtdm_device *dev; + int ret; + + rtdm_dev->master = master; + + rtdm_dev->dev = kzalloc(sizeof(struct rtdm_device), GFP_KERNEL); + if (!rtdm_dev->dev) { + EC_MASTER_ERR(master, + "Failed to reserve memory for RTDM device.\n"); + return -ENOMEM; + } + + dev = rtdm_dev->dev; + + dev->driver = &ec_rtdm_driver; + dev->device_data = rtdm_dev; + dev->label = "EtherCAT%u"; + dev->minor = master->index; + + ret = rtdm_dev_register(dev); + if (ret) { + EC_MASTER_ERR(master, "Initialization of RTDM interface failed" + " (return value %i).\n", ret); + kfree(dev); + return ret; + } + + EC_MASTER_INFO(master, "Registered RTDM device %s.\n", dev->name); + + return 0; +} + +/****************************************************************************/ + +void ec_rtdm_dev_clear(ec_rtdm_dev_t *rtdm_dev) +{ + rtdm_dev_unregister(rtdm_dev->dev); + + EC_MASTER_INFO(rtdm_dev->master, "Unregistered RTDM device %s.\n", + rtdm_dev->dev->name); + + kfree(rtdm_dev->dev); +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sdo.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sdo.c @@ -0,0 +1,124 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + CANopen SDO functions. +*/ + +/****************************************************************************/ + +#include + +#include "master.h" + +#include "sdo.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sdo_init( + ec_sdo_t *sdo, /**< SDO. */ + ec_slave_t *slave, /**< Parent slave. */ + uint16_t index /**< SDO index. */ + ) +{ + sdo->slave = slave; + sdo->index = index; + sdo->object_code = 0x00; + sdo->name = NULL; + sdo->max_subindex = 0; + INIT_LIST_HEAD(&sdo->entries); +} + +/****************************************************************************/ + +/** SDO destructor. + * + * Clears and frees an SDO object. + */ +void ec_sdo_clear( + ec_sdo_t *sdo /**< SDO. */ + ) +{ + ec_sdo_entry_t *entry, *next; + + // free all entries + list_for_each_entry_safe(entry, next, &sdo->entries, list) { + list_del(&entry->list); + ec_sdo_entry_clear(entry); + kfree(entry); + } + + if (sdo->name) + kfree(sdo->name); +} + +/****************************************************************************/ + +/** Get an SDO entry from an SDO via its subindex. + * + * \retval >0 Pointer to the requested SDO entry. + * \retval NULL SDO entry not found. + */ +ec_sdo_entry_t *ec_sdo_get_entry( + ec_sdo_t *sdo, /**< SDO. */ + uint8_t subindex /**< Entry subindex. */ + ) +{ + ec_sdo_entry_t *entry; + + list_for_each_entry(entry, &sdo->entries, list) { + if (entry->subindex != subindex) + continue; + return entry; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get an SDO entry from an SDO via its subindex. + * + * const version. + * + * \retval >0 Pointer to the requested SDO entry. + * \retval NULL SDO entry not found. + */ +const ec_sdo_entry_t *ec_sdo_get_entry_const( + const ec_sdo_t *sdo, /**< SDO. */ + uint8_t subindex /**< Entry subindex. */ + ) +{ + const ec_sdo_entry_t *entry; + + list_for_each_entry(entry, &sdo->entries, list) { + if (entry->subindex != subindex) + continue; + return entry; + } + + return NULL; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sdo.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sdo.h @@ -0,0 +1,61 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CANopen SDO structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SDO_H__ +#define __EC_SDO_H__ + +#include + +#include "globals.h" +#include "sdo_entry.h" + +/****************************************************************************/ + +/** CANopen SDO. + */ +struct ec_sdo { + struct list_head list; /**< List item. */ + ec_slave_t *slave; /**< Parent slave. */ + uint16_t index; /**< SDO index. */ + uint8_t object_code; /**< Object code. */ + char *name; /**< SDO name. */ + uint8_t max_subindex; /**< Maximum subindex. */ + struct list_head entries; /**< List of entries. */ +}; + +/****************************************************************************/ + +void ec_sdo_init(ec_sdo_t *, ec_slave_t *, uint16_t); +void ec_sdo_clear(ec_sdo_t *); + +ec_sdo_entry_t *ec_sdo_get_entry(ec_sdo_t *, uint8_t); +const ec_sdo_entry_t *ec_sdo_get_entry_const(const ec_sdo_t *, uint8_t); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sdo_entry.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sdo_entry.c @@ -0,0 +1,69 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + CANopen over EtherCAT SDO entry functions. +*/ + +/****************************************************************************/ + +#include + +#include "sdo_entry.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sdo_entry_init( + ec_sdo_entry_t *entry, /**< SDO entry. */ + ec_sdo_t *sdo, /**< Parent SDO. */ + uint8_t subindex /**< Subindex. */ + ) +{ + entry->sdo = sdo; + entry->subindex = subindex; + entry->data_type = 0x0000; + entry->bit_length = 0; + entry->read_access[EC_SDO_ENTRY_ACCESS_PREOP] = 0; + entry->read_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = 0; + entry->read_access[EC_SDO_ENTRY_ACCESS_OP] = 0; + entry->write_access[EC_SDO_ENTRY_ACCESS_PREOP] = 0; + entry->write_access[EC_SDO_ENTRY_ACCESS_SAFEOP] = 0; + entry->write_access[EC_SDO_ENTRY_ACCESS_OP] = 0; + entry->description = NULL; +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_sdo_entry_clear( + ec_sdo_entry_t *entry /**< SDO entry. */ + ) +{ + + if (entry->description) + kfree(entry->description); +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sdo_entry.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sdo_entry.h @@ -0,0 +1,64 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CANopen SDO entry structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SDO_ENTRY_H__ +#define __EC_SDO_ENTRY_H__ + +#include +#include + +#include "globals.h" + +/****************************************************************************/ + +struct ec_sdo; +typedef struct ec_sdo ec_sdo_t; /**< \see ec_sdo. */ + +/****************************************************************************/ + +/** CANopen SDO entry. + */ +typedef struct { + struct list_head list; /**< List item. */ + ec_sdo_t *sdo; /**< Parent SDO. */ + uint8_t subindex; /**< Subindex. */ + uint16_t data_type; /**< Data type. */ + uint16_t bit_length; /**< Data size in bit. */ + uint8_t read_access[EC_SDO_ENTRY_ACCESS_COUNT]; /**< Read access. */ + uint8_t write_access[EC_SDO_ENTRY_ACCESS_COUNT]; /**< Write access. */ + char *description; /**< Description. */ +} ec_sdo_entry_t; + +/****************************************************************************/ + +void ec_sdo_entry_init(ec_sdo_entry_t *, ec_sdo_t *, uint8_t); +void ec_sdo_entry_clear(ec_sdo_entry_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sdo_request.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sdo_request.c @@ -0,0 +1,256 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Canopen over EtherCAT SDO request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "sdo_request.h" + +/****************************************************************************/ + +/** Default timeout in ms to wait for SDO transfer responses. + */ +#define EC_SDO_REQUEST_RESPONSE_TIMEOUT 1000 + +/****************************************************************************/ + +void ec_sdo_request_clear_data(ec_sdo_request_t *); + +/****************************************************************************/ + +/** SDO request constructor. + */ +void ec_sdo_request_init( + ec_sdo_request_t *req /**< SDO request. */ + ) +{ + req->complete_access = 0; + req->data = NULL; + req->mem_size = 0; + req->data_size = 0; + req->issue_timeout = 0; // no timeout + req->response_timeout = EC_SDO_REQUEST_RESPONSE_TIMEOUT; + req->dir = EC_DIR_INVALID; + req->state = EC_INT_REQUEST_INIT; + req->jiffies_start = 0U; + req->jiffies_sent = 0U; + req->errno = 0; + req->abort_code = 0x00000000; +} + +/****************************************************************************/ + +/** SDO request destructor. + */ +void ec_sdo_request_clear( + ec_sdo_request_t *req /**< SDO request. */ + ) +{ + ec_sdo_request_clear_data(req); +} + +/****************************************************************************/ + +/** Copy another SDO request. + * + * \attention Only the index subindex and data are copied. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_sdo_request_copy( + ec_sdo_request_t *req, /**< SDO request. */ + const ec_sdo_request_t *other /**< Other SDO request to copy from. */ + ) +{ + req->complete_access = other->complete_access; + req->index = other->index; + req->subindex = other->subindex; + return ec_sdo_request_copy_data(req, other->data, other->data_size); +} + +/****************************************************************************/ + +/** SDO request destructor. + */ +void ec_sdo_request_clear_data( + ec_sdo_request_t *req /**< SDO request. */ + ) +{ + if (req->data) { + kfree(req->data); + req->data = NULL; + } + + req->mem_size = 0; + req->data_size = 0; +} + +/****************************************************************************/ + +/** Pre-allocates the data memory. + * + * If the \a mem_size is already bigger than \a size, nothing is done. + * + * \return 0 on success, otherwise -ENOMEM. + */ +int ec_sdo_request_alloc( + ec_sdo_request_t *req, /**< SDO request. */ + size_t size /**< Data size to allocate. */ + ) +{ + if (size <= req->mem_size) + return 0; + + ec_sdo_request_clear_data(req); + + if (!(req->data = (uint8_t *) kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of SDO memory.\n", size); + return -ENOMEM; + } + + req->mem_size = size; + req->data_size = 0; + return 0; +} + +/****************************************************************************/ + +/** Copies SDO data from an external source. + * + * If the \a mem_size is to small, new memory is allocated. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_sdo_request_copy_data( + ec_sdo_request_t *req, /**< SDO request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + int ret = ec_sdo_request_alloc(req, size); + if (ret < 0) + return ret; + + memcpy(req->data, source, size); + req->data_size = size; + return 0; +} + +/****************************************************************************/ + +/** Checks, if the timeout was exceeded. + * + * \return non-zero if the timeout was exceeded, else zero. + */ +int ec_sdo_request_timed_out(const ec_sdo_request_t *req /**< SDO request. */) +{ + return req->issue_timeout + && jiffies - req->jiffies_start > HZ * req->issue_timeout / 1000; +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +int ecrt_sdo_request_index(ec_sdo_request_t *req, uint16_t index, + uint8_t subindex) +{ + req->index = index; + req->subindex = subindex; + return 0; +} + +/****************************************************************************/ + +int ecrt_sdo_request_timeout(ec_sdo_request_t *req, uint32_t timeout) +{ + req->issue_timeout = timeout; + return 0; +} + +/****************************************************************************/ + +uint8_t *ecrt_sdo_request_data(const ec_sdo_request_t *req) +{ + return req->data; +} + +/****************************************************************************/ + +size_t ecrt_sdo_request_data_size(const ec_sdo_request_t *req) +{ + return req->data_size; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_sdo_request_state(const ec_sdo_request_t *req) +{ + return ec_request_state_translation_table[req->state]; +} + +/****************************************************************************/ + +int ecrt_sdo_request_read(ec_sdo_request_t *req) +{ + req->dir = EC_DIR_INPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->errno = 0; + req->abort_code = 0x00000000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +int ecrt_sdo_request_write(ec_sdo_request_t *req) +{ + req->dir = EC_DIR_OUTPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->errno = 0; + req->abort_code = 0x00000000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_sdo_request_index); +EXPORT_SYMBOL(ecrt_sdo_request_timeout); +EXPORT_SYMBOL(ecrt_sdo_request_data); +EXPORT_SYMBOL(ecrt_sdo_request_data_size); +EXPORT_SYMBOL(ecrt_sdo_request_state); +EXPORT_SYMBOL(ecrt_sdo_request_read); +EXPORT_SYMBOL(ecrt_sdo_request_write); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sdo_request.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sdo_request.h @@ -0,0 +1,75 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT CANopen SDO request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SDO_REQUEST_H__ +#define __EC_SDO_REQUEST_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** CANopen SDO request. + */ +struct ec_sdo_request { + struct list_head list; /**< List item. */ + uint16_t index; /**< SDO index. */ + uint8_t subindex; /**< SDO subindex. */ + uint8_t *data; /**< Pointer to SDO data. */ + size_t mem_size; /**< Size of SDO data memory. */ + size_t data_size; /**< Size of SDO data. */ + uint8_t complete_access; /**< SDO shall be transferred completely. */ + uint32_t issue_timeout; /**< Maximum time in ms, the processing of the + request may take. */ + uint32_t response_timeout; /**< Maximum time in ms, the transfer is + retried, if the slave does not respond. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means downloading to + the slave, EC_DIR_INPUT means uploading from the + slave. */ + ec_internal_request_state_t state; /**< SDO request state. */ + unsigned long jiffies_start; /**< Jiffies, when the request was issued. */ + unsigned long jiffies_sent; /**< Jiffies, when the upload/download + request was sent. */ + int errno; /**< Error number. */ + uint32_t abort_code; /**< SDO request abort code. Zero on success. */ +}; + +/****************************************************************************/ + +void ec_sdo_request_init(ec_sdo_request_t *); +void ec_sdo_request_clear(ec_sdo_request_t *); + +int ec_sdo_request_copy(ec_sdo_request_t *, const ec_sdo_request_t *); +int ec_sdo_request_alloc(ec_sdo_request_t *, size_t); +int ec_sdo_request_copy_data(ec_sdo_request_t *, const uint8_t *, size_t); +int ec_sdo_request_timed_out(const ec_sdo_request_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/slave.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/slave.c @@ -0,0 +1,1010 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave methods. +*/ + +/****************************************************************************/ + +#include +#include + +#include "globals.h" +#include "datagram.h" +#include "master.h" +#include "slave_config.h" + +#include "slave.h" + +/****************************************************************************/ + +extern const ec_code_msg_t al_status_messages[]; + +/****************************************************************************/ + +// prototypes for private methods +char *ec_slave_sii_string(const ec_slave_t *, unsigned int); +void ec_slave_find_names_for_pdo(ec_slave_t *, ec_pdo_t *); +unsigned int ec_slave_get_previous_port(const ec_slave_t *, unsigned int); +unsigned int ec_slave_get_next_port(const ec_slave_t *, unsigned int); +uint32_t ec_slave_calc_rtt_sum(const ec_slave_t *); +ec_slave_t *ec_slave_find_next_dc_slave(ec_slave_t *); + +/****************************************************************************/ + +/** + Slave constructor. + \return 0 in case of success, else < 0 +*/ + +void ec_slave_init( + ec_slave_t *slave, /**< EtherCAT slave */ + ec_master_t *master, /**< EtherCAT master */ + ec_device_index_t dev_idx, /**< Device index. */ + uint16_t ring_position, /**< ring position */ + uint16_t station_address /**< station address to configure */ + ) +{ + unsigned int i; + + slave->master = master; + slave->device_index = dev_idx; + slave->ring_position = ring_position; + slave->station_address = station_address; + slave->effective_alias = 0x0000; + + slave->config = NULL; + slave->requested_state = EC_SLAVE_STATE_PREOP; + slave->current_state = EC_SLAVE_STATE_UNKNOWN; + slave->error_flag = 0; + slave->force_config = 0; + slave->configured_rx_mailbox_offset = 0x0000; + slave->configured_rx_mailbox_size = 0x0000; + slave->configured_tx_mailbox_offset = 0x0000; + slave->configured_tx_mailbox_size = 0x0000; + + slave->base_type = 0; + slave->base_revision = 0; + slave->base_build = 0; + slave->base_fmmu_count = 0; + slave->base_sync_count = 0; + + for (i = 0; i < EC_MAX_PORTS; i++) { + slave->ports[i].desc = EC_PORT_NOT_IMPLEMENTED; + + slave->ports[i].link.link_up = 0; + slave->ports[i].link.loop_closed = 0; + slave->ports[i].link.signal_detected = 0; + slave->sii.physical_layer[i] = 0xFF; + + slave->ports[i].receive_time = 0U; + + slave->ports[i].next_slave = NULL; + slave->ports[i].delay_to_next_dc = 0U; + } + + slave->base_fmmu_bit_operation = 0; + slave->base_dc_supported = 0; + slave->base_dc_range = EC_DC_32; + slave->has_dc_system_time = 0; + slave->transmission_delay = 0U; + + slave->sii_words = NULL; + slave->sii_nwords = 0; + + slave->sii.alias = 0x0000; + slave->sii.vendor_id = 0x00000000; + slave->sii.product_code = 0x00000000; + slave->sii.revision_number = 0x00000000; + slave->sii.serial_number = 0x00000000; + slave->sii.boot_rx_mailbox_offset = 0x0000; + slave->sii.boot_rx_mailbox_size = 0x0000; + slave->sii.boot_tx_mailbox_offset = 0x0000; + slave->sii.boot_tx_mailbox_size = 0x0000; + slave->sii.std_rx_mailbox_offset = 0x0000; + slave->sii.std_rx_mailbox_size = 0x0000; + slave->sii.std_tx_mailbox_offset = 0x0000; + slave->sii.std_tx_mailbox_size = 0x0000; + slave->sii.mailbox_protocols = 0; + + slave->sii.strings = NULL; + slave->sii.string_count = 0; + + slave->sii.has_general = 0; + slave->sii.group = NULL; + slave->sii.image = NULL; + slave->sii.order = NULL; + slave->sii.name = NULL; + memset(&slave->sii.coe_details, 0x00, sizeof(ec_sii_coe_details_t)); + memset(&slave->sii.general_flags, 0x00, sizeof(ec_sii_general_flags_t)); + slave->sii.current_on_ebus = 0; + + slave->sii.syncs = NULL; + slave->sii.sync_count = 0; + + INIT_LIST_HEAD(&slave->sii.pdos); + + INIT_LIST_HEAD(&slave->sdo_dictionary); + + slave->sdo_dictionary_fetched = 0; + slave->jiffies_preop = 0; + + INIT_LIST_HEAD(&slave->sdo_requests); + INIT_LIST_HEAD(&slave->reg_requests); + INIT_LIST_HEAD(&slave->foe_requests); + INIT_LIST_HEAD(&slave->soe_requests); + INIT_LIST_HEAD(&slave->eoe_requests); + + // create state machine object + ec_fsm_slave_init(&slave->fsm, slave); +} + +/****************************************************************************/ + +/** + Slave destructor. + Clears and frees a slave object. +*/ + +void ec_slave_clear(ec_slave_t *slave /**< EtherCAT slave */) +{ + ec_sdo_t *sdo, *next_sdo; + unsigned int i; + ec_pdo_t *pdo, *next_pdo; + + // abort all pending requests + + while (!list_empty(&slave->sdo_requests)) { + ec_sdo_request_t *request = + list_entry(slave->sdo_requests.next, ec_sdo_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding SDO request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } + + while (!list_empty(&slave->reg_requests)) { + ec_reg_request_t *reg = + list_entry(slave->reg_requests.next, ec_reg_request_t, list); + list_del_init(®->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding register request," + " slave about to be deleted.\n"); + reg->state = EC_INT_REQUEST_FAILURE; + } + + while (!list_empty(&slave->foe_requests)) { + ec_foe_request_t *request = + list_entry(slave->foe_requests.next, ec_foe_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding FoE request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } + + while (!list_empty(&slave->soe_requests)) { + ec_soe_request_t *request = + list_entry(slave->soe_requests.next, ec_soe_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding SoE request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } + +#ifdef EC_EOE + while (!list_empty(&slave->eoe_requests)) { + ec_eoe_request_t *request = + list_entry(slave->eoe_requests.next, ec_eoe_request_t, list); + list_del_init(&request->list); // dequeue + EC_SLAVE_WARN(slave, "Discarding EoE request," + " slave about to be deleted.\n"); + request->state = EC_INT_REQUEST_FAILURE; + } +#endif + + wake_up_all(&slave->master->request_queue); + + if (slave->config) { + ec_slave_config_detach(slave->config); + } + + // free all SDOs + list_for_each_entry_safe(sdo, next_sdo, &slave->sdo_dictionary, list) { + list_del(&sdo->list); + ec_sdo_clear(sdo); + kfree(sdo); + } + + // free all strings + if (slave->sii.strings) { + for (i = 0; i < slave->sii.string_count; i++) + kfree(slave->sii.strings[i]); + kfree(slave->sii.strings); + } + + // free all sync managers + ec_slave_clear_sync_managers(slave); + + // free all SII PDOs + list_for_each_entry_safe(pdo, next_pdo, &slave->sii.pdos, list) { + list_del(&pdo->list); + ec_pdo_clear(pdo); + kfree(pdo); + } + + if (slave->sii_words) { + kfree(slave->sii_words); + } + + ec_fsm_slave_clear(&slave->fsm); +} + +/****************************************************************************/ + +/** Clear the sync manager array. + */ +void ec_slave_clear_sync_managers(ec_slave_t *slave /**< EtherCAT slave. */) +{ + unsigned int i; + + if (slave->sii.syncs) { + for (i = 0; i < slave->sii.sync_count; i++) { + ec_sync_clear(&slave->sii.syncs[i]); + } + kfree(slave->sii.syncs); + slave->sii.syncs = NULL; + } +} + +/****************************************************************************/ + +/** + * Sets the application state of a slave. + */ + +void ec_slave_set_state(ec_slave_t *slave, /**< EtherCAT slave */ + ec_slave_state_t new_state /**< new application state */ + ) +{ + if (new_state != slave->current_state) { + if (slave->master->debug_level) { + char old_state[EC_STATE_STRING_SIZE], + cur_state[EC_STATE_STRING_SIZE]; + ec_state_string(slave->current_state, old_state, 0); + ec_state_string(new_state, cur_state, 0); + EC_SLAVE_DBG(slave, 0, "%s -> %s.\n", old_state, cur_state); + } + slave->current_state = new_state; + } +} + +/****************************************************************************/ + +/** + * Request a slave state and resets the error flag. + */ + +void ec_slave_request_state(ec_slave_t *slave, /**< EtherCAT slave */ + ec_slave_state_t state /**< new state */ + ) +{ + slave->requested_state = state; + slave->error_flag = 0; +} + +/****************************************************************************/ + +/** + Fetches data from a STRING category. + \todo range checking + \return 0 in case of success, else < 0 +*/ + +int ec_slave_fetch_sii_strings( + ec_slave_t *slave, /**< EtherCAT slave */ + const uint8_t *data, /**< category data */ + size_t data_size /**< number of bytes */ + ) +{ + int i, err; + size_t size; + off_t offset; + + slave->sii.string_count = data[0]; + + if (slave->sii.string_count) { + if (!(slave->sii.strings = + kmalloc(sizeof(char *) * slave->sii.string_count, + GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate string array memory.\n"); + err = -ENOMEM; + goto out_zero; + } + + offset = 1; + for (i = 0; i < slave->sii.string_count; i++) { + size = data[offset]; + // allocate memory for string structure and data at a single blow + if (!(slave->sii.strings[i] = + kmalloc(sizeof(char) * size + 1, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate string memory.\n"); + err = -ENOMEM; + goto out_free; + } + memcpy(slave->sii.strings[i], data + offset + 1, size); + slave->sii.strings[i][size] = 0x00; // append binary zero + offset += 1 + size; + } + } + + return 0; + +out_free: + for (i--; i >= 0; i--) + kfree(slave->sii.strings[i]); + kfree(slave->sii.strings); + slave->sii.strings = NULL; +out_zero: + slave->sii.string_count = 0; + return err; +} + +/****************************************************************************/ + +/** + Fetches data from a GENERAL category. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_fetch_sii_general( + ec_slave_t *slave, /**< EtherCAT slave */ + const uint8_t *data, /**< category data */ + size_t data_size /**< size in bytes */ + ) +{ + unsigned int i; + uint8_t flags; + + if (data_size != 32) { + EC_SLAVE_ERR(slave, "Wrong size of general category (%zu/32).\n", + data_size); + return -EINVAL; + } + + slave->sii.group = ec_slave_sii_string(slave, data[0]); + slave->sii.image = ec_slave_sii_string(slave, data[1]); + slave->sii.order = ec_slave_sii_string(slave, data[2]); + slave->sii.name = ec_slave_sii_string(slave, data[3]); + + for (i = 0; i < 4; i++) + slave->sii.physical_layer[i] = + (data[4] & (0x03 << (i * 2))) >> (i * 2); + + // read CoE details + flags = EC_READ_U8(data + 5); + slave->sii.coe_details.enable_sdo = (flags >> 0) & 0x01; + slave->sii.coe_details.enable_sdo_info = (flags >> 1) & 0x01; + slave->sii.coe_details.enable_pdo_assign = (flags >> 2) & 0x01; + slave->sii.coe_details.enable_pdo_configuration = (flags >> 3) & 0x01; + slave->sii.coe_details.enable_upload_at_startup = (flags >> 4) & 0x01; + slave->sii.coe_details.enable_sdo_complete_access = (flags >> 5) & 0x01; + + // read general flags + flags = EC_READ_U8(data + 0x000B); + slave->sii.general_flags.enable_safeop = (flags >> 0) & 0x01; + slave->sii.general_flags.enable_not_lrw = (flags >> 1) & 0x01; + + slave->sii.current_on_ebus = EC_READ_S16(data + 0x0C); + slave->sii.has_general = 1; + return 0; +} + +/****************************************************************************/ + +/** Fetches data from a SYNC MANAGER category. + * + * Appends the sync managers described in the category to the existing ones. + * + * \return 0 in case of success, else < 0 + */ +int ec_slave_fetch_sii_syncs( + ec_slave_t *slave, /**< EtherCAT slave. */ + const uint8_t *data, /**< Category data. */ + size_t data_size /**< Number of bytes. */ + ) +{ + unsigned int i, count, total_count; + ec_sync_t *sync; + size_t memsize; + ec_sync_t *syncs; + uint8_t index; + + // one sync manager struct is 4 words long + if (data_size % 8) { + EC_SLAVE_ERR(slave, "Invalid SII sync manager category size %zu.\n", + data_size); + return -EINVAL; + } + + count = data_size / 8; + + if (count) { + total_count = count + slave->sii.sync_count; + if (total_count > EC_MAX_SYNC_MANAGERS) { + EC_SLAVE_ERR(slave, "Exceeded maximum number of" + " sync managers!\n"); + return -EOVERFLOW; + } + memsize = sizeof(ec_sync_t) * total_count; + if (!(syncs = kmalloc(memsize, GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate %zu bytes" + " for sync managers.\n", memsize); + return -ENOMEM; + } + + for (i = 0; i < slave->sii.sync_count; i++) + ec_sync_init_copy(syncs + i, slave->sii.syncs + i); + + // initialize new sync managers + for (i = 0; i < count; i++, data += 8) { + index = i + slave->sii.sync_count; + sync = &syncs[index]; + + ec_sync_init(sync, slave); + sync->physical_start_address = EC_READ_U16(data); + sync->default_length = EC_READ_U16(data + 2); + sync->control_register = EC_READ_U8(data + 4); + sync->enable = EC_READ_U8(data + 6); + } + + if (slave->sii.syncs) + kfree(slave->sii.syncs); + slave->sii.syncs = syncs; + slave->sii.sync_count = total_count; + } + + return 0; +} + +/****************************************************************************/ + +/** + Fetches data from a [RT]xPDO category. + \return 0 in case of success, else < 0 +*/ + +int ec_slave_fetch_sii_pdos( + ec_slave_t *slave, /**< EtherCAT slave */ + const uint8_t *data, /**< category data */ + size_t data_size, /**< number of bytes */ + ec_direction_t dir /**< PDO direction. */ + ) +{ + int ret; + ec_pdo_t *pdo; + ec_pdo_entry_t *entry; + unsigned int entry_count, i; + + while (data_size >= 8) { + if (!(pdo = kmalloc(sizeof(ec_pdo_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate PDO memory.\n"); + return -ENOMEM; + } + + ec_pdo_init(pdo); + pdo->index = EC_READ_U16(data); + entry_count = EC_READ_U8(data + 2); + pdo->sync_index = EC_READ_U8(data + 3); + ret = ec_pdo_set_name(pdo, + ec_slave_sii_string(slave, EC_READ_U8(data + 5))); + if (ret) { + ec_pdo_clear(pdo); + kfree(pdo); + return ret; + } + list_add_tail(&pdo->list, &slave->sii.pdos); + + data_size -= 8; + data += 8; + + for (i = 0; i < entry_count; i++) { + if (!(entry = kmalloc(sizeof(ec_pdo_entry_t), GFP_KERNEL))) { + EC_SLAVE_ERR(slave, "Failed to allocate PDO entry memory.\n"); + return -ENOMEM; + } + + ec_pdo_entry_init(entry); + entry->index = EC_READ_U16(data); + entry->subindex = EC_READ_U8(data + 2); + ret = ec_pdo_entry_set_name(entry, + ec_slave_sii_string(slave, EC_READ_U8(data + 3))); + if (ret) { + ec_pdo_entry_clear(entry); + kfree(entry); + return ret; + } + entry->bit_length = EC_READ_U8(data + 5); + list_add_tail(&entry->list, &pdo->entries); + + data_size -= 8; + data += 8; + } + + // if sync manager index is positive, the PDO is mapped by default + if (pdo->sync_index >= 0) { + ec_sync_t *sync; + + if (!(sync = ec_slave_get_sync(slave, pdo->sync_index))) { + EC_SLAVE_ERR(slave, "Invalid SM index %i for PDO 0x%04X.", + pdo->sync_index, pdo->index); + return -ENOENT; + } + + ret = ec_pdo_list_add_pdo_copy(&sync->pdos, pdo); + if (ret) + return ret; + } + } + + return 0; +} + +/****************************************************************************/ + +/** + Searches the string list for an index. + \return 0 in case of success, else < 0 +*/ + +char *ec_slave_sii_string( + const ec_slave_t *slave, /**< EtherCAT slave */ + unsigned int index /**< string index */ + ) +{ + if (!index--) + return NULL; + + if (index >= slave->sii.string_count) { + EC_SLAVE_DBG(slave, 1, "String %u not found.\n", index); + return NULL; + } + + return slave->sii.strings[index]; +} + +/****************************************************************************/ + +/** Get the sync manager given an index. + * + * \return pointer to sync manager, or NULL. + */ +ec_sync_t *ec_slave_get_sync( + ec_slave_t *slave, /**< EtherCAT slave. */ + uint8_t sync_index /**< Sync manager index. */ + ) +{ + if (sync_index < slave->sii.sync_count) { + return &slave->sii.syncs[sync_index]; + } else { + return NULL; + } +} + +/****************************************************************************/ + +/** + Counts the total number of SDOs and entries in the dictionary. +*/ + +void ec_slave_sdo_dict_info(const ec_slave_t *slave, /**< EtherCAT slave */ + unsigned int *sdo_count, /**< number of SDOs */ + unsigned int *entry_count /**< total number of + entries */ + ) +{ + unsigned int sdos = 0, entries = 0; + ec_sdo_t *sdo; + ec_sdo_entry_t *entry; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + sdos++; + list_for_each_entry(entry, &sdo->entries, list) { + entries++; + } + } + + *sdo_count = sdos; + *entry_count = entries; +} + +/****************************************************************************/ + +/** + * Get an SDO from the dictionary. + * \returns The desired SDO, or NULL. + */ + +ec_sdo_t *ec_slave_get_sdo( + ec_slave_t *slave, /**< EtherCAT slave */ + uint16_t index /**< SDO index */ + ) +{ + ec_sdo_t *sdo; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo->index != index) + continue; + return sdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** + * Get an SDO from the dictionary. + * + * const version. + * + * \returns The desired SDO, or NULL. + */ + +const ec_sdo_t *ec_slave_get_sdo_const( + const ec_slave_t *slave, /**< EtherCAT slave */ + uint16_t index /**< SDO index */ + ) +{ + const ec_sdo_t *sdo; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo->index != index) + continue; + return sdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get an SDO from the dictionary, given its position in the list. + * \returns The desired SDO, or NULL. + */ + +const ec_sdo_t *ec_slave_get_sdo_by_pos_const( + const ec_slave_t *slave, /**< EtherCAT slave. */ + uint16_t sdo_position /**< SDO list position. */ + ) +{ + const ec_sdo_t *sdo; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo_position--) + continue; + return sdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of SDOs in the dictionary. + * \returns SDO count. + */ + +uint16_t ec_slave_sdo_count( + const ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + const ec_sdo_t *sdo; + uint16_t count = 0; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds a mapped PDO. + * \returns The desired PDO object, or NULL. + */ +const ec_pdo_t *ec_slave_find_pdo( + const ec_slave_t *slave, /**< Slave. */ + uint16_t index /**< PDO index to find. */ + ) +{ + unsigned int i; + const ec_sync_t *sync; + const ec_pdo_t *pdo; + + for (i = 0; i < slave->sii.sync_count; i++) { + sync = &slave->sii.syncs[i]; + + if (!(pdo = ec_pdo_list_find_pdo_const(&sync->pdos, index))) + continue; + + return pdo; + } + + return NULL; +} + +/****************************************************************************/ + +/** Find name for a PDO and its entries. + */ +void ec_slave_find_names_for_pdo( + ec_slave_t *slave, + ec_pdo_t *pdo + ) +{ + const ec_sdo_t *sdo; + ec_pdo_entry_t *pdo_entry; + const ec_sdo_entry_t *sdo_entry; + + list_for_each_entry(sdo, &slave->sdo_dictionary, list) { + if (sdo->index == pdo->index) { + ec_pdo_set_name(pdo, sdo->name); + } else { + list_for_each_entry(pdo_entry, &pdo->entries, list) { + if (sdo->index == pdo_entry->index) { + sdo_entry = ec_sdo_get_entry_const( + sdo, pdo_entry->subindex); + if (sdo_entry) { + ec_pdo_entry_set_name(pdo_entry, + sdo_entry->description); + } + } + } + } + } +} + +/****************************************************************************/ + +/** Attach PDO names. + */ +void ec_slave_attach_pdo_names( + ec_slave_t *slave + ) +{ + unsigned int i; + ec_sync_t *sync; + ec_pdo_t *pdo; + + for (i = 0; i < slave->sii.sync_count; i++) { + sync = slave->sii.syncs + i; + list_for_each_entry(pdo, &sync->pdos.list, list) { + ec_slave_find_names_for_pdo(slave, pdo); + } + } +} + +/****************************************************************************/ + +/** Returns the previous connected port of a given port. + * + * \return Port index. + */ +unsigned int ec_slave_get_previous_port( + const ec_slave_t *slave, /**< EtherCAT slave. */ + unsigned int port_index /**< Port index. */ + ) +{ + static const unsigned int prev_table[EC_MAX_PORTS] = { + 2, 3, 1, 0 + }; + + if (port_index >= EC_MAX_PORTS) { + EC_SLAVE_WARN(slave, "%s(port_index=%u): Invalid port index!\n", + __func__, port_index); + } + + do { + port_index = prev_table[port_index]; + if (slave->ports[port_index].next_slave) { + return port_index; + } + } while (port_index); + + return 0; +} + +/****************************************************************************/ + +/** Returns the next connected port of a given port. + * + * \return Port index. + */ +unsigned int ec_slave_get_next_port( + const ec_slave_t *slave, /**< EtherCAT slave. */ + unsigned int port_index /**< Port index. */ + ) +{ + static const unsigned int next_table[EC_MAX_PORTS] = { + 3, 2, 0, 1 + }; + + if (port_index >= EC_MAX_PORTS) { + EC_SLAVE_WARN(slave, "%s(port_index=%u): Invalid port index!\n", + __func__, port_index); + } + + do { + port_index = next_table[port_index]; + if (slave->ports[port_index].next_slave) { + return port_index; + } + } while (port_index); + + return 0; +} + +/****************************************************************************/ + +/** Calculates the sum of round-trip-times of connected ports 1-3. + * + * \return Round-trip-time in ns. + */ +uint32_t ec_slave_calc_rtt_sum( + const ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + uint32_t rtt_sum = 0, rtt; + unsigned int port_index = ec_slave_get_next_port(slave, 0); + + while (port_index != 0) { + unsigned int prev_index = + ec_slave_get_previous_port(slave, port_index); + + rtt = slave->ports[port_index].receive_time - + slave->ports[prev_index].receive_time; + rtt_sum += rtt; + port_index = ec_slave_get_next_port(slave, port_index); + } + + return rtt_sum; +} + +/****************************************************************************/ + +/** Finds the next slave supporting DC delay measurement. + * + * \return Next DC slave, or NULL. + */ +ec_slave_t *ec_slave_find_next_dc_slave( + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + unsigned int port_index; + ec_slave_t *dc_slave = NULL; + + if (slave->base_dc_supported) { + dc_slave = slave; + } else { + port_index = ec_slave_get_next_port(slave, 0); + + while (port_index != 0) { + ec_slave_t *next = slave->ports[port_index].next_slave; + + if (next) { + dc_slave = ec_slave_find_next_dc_slave(next); + + if (dc_slave) { + break; + } + } + port_index = ec_slave_get_next_port(slave, port_index); + } + } + + return dc_slave; +} + +/****************************************************************************/ + +/** Calculates the port transmission delays. + */ +void ec_slave_calc_port_delays( + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + unsigned int port_index; + ec_slave_t *next_slave, *next_dc; + uint32_t rtt, next_rtt_sum; + + if (!slave->base_dc_supported) + return; + + port_index = ec_slave_get_next_port(slave, 0); + + while (port_index != 0) { + next_slave = slave->ports[port_index].next_slave; + next_dc = ec_slave_find_next_dc_slave(next_slave); + + if (next_dc) { + unsigned int prev_port = + ec_slave_get_previous_port(slave, port_index); + + rtt = slave->ports[port_index].receive_time - + slave->ports[prev_port].receive_time; + next_rtt_sum = ec_slave_calc_rtt_sum(next_dc); + + slave->ports[port_index].delay_to_next_dc = + (rtt - next_rtt_sum) / 2; // FIXME + next_dc->ports[0].delay_to_next_dc = + (rtt - next_rtt_sum) / 2; + +#if 0 + EC_SLAVE_DBG(slave, 1, "delay %u:%u rtt=%u" + " next_rtt_sum=%u delay=%u\n", + slave->ring_position, port_index, rtt, next_rtt_sum, + slave->ports[port_index].delay_to_next_dc); +#endif + } + + port_index = ec_slave_get_next_port(slave, port_index); + } +} + +/****************************************************************************/ + +/** Recursively calculates transmission delays. + */ +void ec_slave_calc_transmission_delays_rec( + ec_slave_t *slave, /**< Current slave. */ + uint32_t *delay /**< Sum of delays. */ + ) +{ + unsigned int i; + ec_slave_t *next_dc; + + EC_SLAVE_DBG(slave, 1, "%s(delay = %u ns)\n", __func__, *delay); + + slave->transmission_delay = *delay; + + i = ec_slave_get_next_port(slave, 0); + + while (i != 0) { + ec_slave_port_t *port = &slave->ports[i]; + next_dc = ec_slave_find_next_dc_slave(port->next_slave); + if (next_dc) { + *delay = *delay + port->delay_to_next_dc; +#if 0 + EC_SLAVE_DBG(slave, 1, "%u:%u %u\n", + slave->ring_position, i, *delay); +#endif + ec_slave_calc_transmission_delays_rec(next_dc, delay); + } + + i = ec_slave_get_next_port(slave, i); + } + + *delay = *delay + slave->ports[0].delay_to_next_dc; +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/slave.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/slave.h @@ -0,0 +1,266 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2012 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SLAVE_H__ +#define __EC_SLAVE_H__ + +#include +#include + +#include "globals.h" +#include "datagram.h" +#include "pdo.h" +#include "sync.h" +#include "sdo.h" +#include "fsm_slave.h" + +/****************************************************************************/ + +/** Convenience macro for printing slave-specific information to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_INFO(slave, fmt, args...) \ + printk(KERN_INFO "EtherCAT %u-%u: " fmt, slave->master->index, \ + slave->ring_position, ##args) + +/** Convenience macro for printing slave-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_ERR(slave, fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR %u-%u: " fmt, slave->master->index, \ + slave->ring_position, ##args) + +/** Convenience macro for printing slave-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_WARN(slave, fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING %u-%u: " fmt, \ + slave->master->index, slave->ring_position, ##args) + +/** Convenience macro for printing slave-specific debug messages to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT -: ", where INDEX is the master index and + * POSITION is the slave's ring position. + * + * \param slave EtherCAT slave + * \param level Debug level. Master's debug level must be >= \a level for + * output. + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_SLAVE_DBG(slave, level, fmt, args...) \ + do { \ + if (slave->master->debug_level >= level) { \ + printk(KERN_DEBUG "EtherCAT DEBUG %u-%u: " fmt, \ + slave->master->index, slave->ring_position, ##args); \ + } \ + } while (0) + +/****************************************************************************/ + +/** Slave port. + */ +typedef struct { + ec_slave_port_desc_t desc; /**< Port descriptors. */ + ec_slave_port_link_t link; /**< Port link status. */ + ec_slave_t *next_slave; /**< Connected slaves. */ + uint32_t receive_time; /**< Port receive times for delay + measurement. */ + uint32_t delay_to_next_dc; /**< Delay to next slave with DC support behind + this port [ns]. */ +} ec_slave_port_t; + +/****************************************************************************/ + +/** Slave information interface data. + */ +typedef struct { + // Non-category data + uint16_t alias; /**< Configured station alias. */ + uint32_t vendor_id; /**< Vendor ID. */ + uint32_t product_code; /**< Vendor-specific product code. */ + uint32_t revision_number; /**< Revision number. */ + uint32_t serial_number; /**< Serial number. */ + uint16_t boot_rx_mailbox_offset; /**< Bootstrap receive mailbox address. */ + uint16_t boot_rx_mailbox_size; /**< Bootstrap receive mailbox size. */ + uint16_t boot_tx_mailbox_offset; /**< Bootstrap transmit mailbox address. */ + uint16_t boot_tx_mailbox_size; /**< Bootstrap transmit mailbox size. */ + uint16_t std_rx_mailbox_offset; /**< Standard receive mailbox address. */ + uint16_t std_rx_mailbox_size; /**< Standard receive mailbox size. */ + uint16_t std_tx_mailbox_offset; /**< Standard transmit mailbox address. */ + uint16_t std_tx_mailbox_size; /**< Standard transmit mailbox size. */ + uint16_t mailbox_protocols; /**< Supported mailbox protocols. */ + + // Strings + char **strings; /**< Strings in SII categories. */ + unsigned int string_count; /**< Number of SII strings. */ + + // General + unsigned int has_general; /**< General category present. */ + char *group; /**< Group name. */ + char *image; /**< Image name. */ + char *order; /**< Order number. */ + char *name; /**< Slave name. */ + uint8_t physical_layer[EC_MAX_PORTS]; /**< Port media. */ + ec_sii_coe_details_t coe_details; /**< CoE detail flags. */ + ec_sii_general_flags_t general_flags; /**< General flags. */ + int16_t current_on_ebus; /**< Power consumption in mA. */ + + // SyncM + ec_sync_t *syncs; /**< SYNC MANAGER categories. */ + unsigned int sync_count; /**< Number of sync managers. */ + + // [RT]XPDO + struct list_head pdos; /**< SII [RT]XPDO categories. */ +} ec_sii_t; + +/****************************************************************************/ + +/** EtherCAT slave. + */ +struct ec_slave +{ + ec_master_t *master; /**< Master owning the slave. */ + ec_device_index_t device_index; /**< Index of device the slave responds + on. */ + + // addresses + uint16_t ring_position; /**< Ring position. */ + uint16_t station_address; /**< Configured station address. */ + uint16_t effective_alias; /**< Effective alias address. */ + + ec_slave_port_t ports[EC_MAX_PORTS]; /**< Ports. */ + + // configuration + ec_slave_config_t *config; /**< Current configuration. */ + ec_slave_state_t requested_state; /**< Requested application state. */ + ec_slave_state_t current_state; /**< Current application state. */ + unsigned int error_flag; /**< Stop processing after an error. */ + unsigned int force_config; /**< Force (re-)configuration. */ + uint16_t configured_rx_mailbox_offset; /**< Configured receive mailbox + offset. */ + uint16_t configured_rx_mailbox_size; /**< Configured receive mailbox size. + */ + uint16_t configured_tx_mailbox_offset; /**< Configured send mailbox + offset. */ + uint16_t configured_tx_mailbox_size; /**< Configured send mailbox size. */ + + // base data + uint8_t base_type; /**< Slave type. */ + uint8_t base_revision; /**< Revision. */ + uint16_t base_build; /**< Build number. */ + uint8_t base_fmmu_count; /**< Number of supported FMMUs. */ + uint8_t base_sync_count; /**< Number of supported sync managers. */ + uint8_t base_fmmu_bit_operation; /**< FMMU bit operation is supported. */ + uint8_t base_dc_supported; /**< Distributed clocks are supported. */ + ec_slave_dc_range_t base_dc_range; /**< DC range. */ + uint8_t has_dc_system_time; /**< The slave supports the DC system time + register. Otherwise it can only be used for + delay measurement. */ + uint32_t transmission_delay; /**< DC system time transmission delay + (offset from reference clock). */ + + // SII + uint16_t *sii_words; /**< Complete SII image. */ + size_t sii_nwords; /**< Size of the SII contents in words. */ + + // Slave information interface + ec_sii_t sii; /**< Extracted SII data. */ + + struct list_head sdo_dictionary; /**< SDO dictionary list */ + uint8_t sdo_dictionary_fetched; /**< Dictionary has been fetched. */ + unsigned long jiffies_preop; /**< Time, the slave went to PREOP. */ + + struct list_head sdo_requests; /**< SDO access requests. */ + struct list_head reg_requests; /**< Register access requests. */ + struct list_head foe_requests; /**< FoE requests. */ + struct list_head soe_requests; /**< SoE requests. */ + struct list_head eoe_requests; /**< EoE set IP parameter requests. */ + + ec_fsm_slave_t fsm; /**< Slave state machine. */ +}; + +/****************************************************************************/ + +// slave construction/destruction +void ec_slave_init(ec_slave_t *, ec_master_t *, ec_device_index_t, + uint16_t, uint16_t); +void ec_slave_clear(ec_slave_t *); + +void ec_slave_clear_sync_managers(ec_slave_t *); + +void ec_slave_request_state(ec_slave_t *, ec_slave_state_t); +void ec_slave_set_state(ec_slave_t *, ec_slave_state_t); + +// SII categories +int ec_slave_fetch_sii_strings(ec_slave_t *, const uint8_t *, size_t); +int ec_slave_fetch_sii_general(ec_slave_t *, const uint8_t *, size_t); +int ec_slave_fetch_sii_syncs(ec_slave_t *, const uint8_t *, size_t); +int ec_slave_fetch_sii_pdos(ec_slave_t *, const uint8_t *, size_t, + ec_direction_t); + +// misc. +ec_sync_t *ec_slave_get_sync(ec_slave_t *, uint8_t); + +void ec_slave_sdo_dict_info(const ec_slave_t *, + unsigned int *, unsigned int *); +ec_sdo_t *ec_slave_get_sdo(ec_slave_t *, uint16_t); +const ec_sdo_t *ec_slave_get_sdo_const(const ec_slave_t *, uint16_t); +const ec_sdo_t *ec_slave_get_sdo_by_pos_const(const ec_slave_t *, uint16_t); +uint16_t ec_slave_sdo_count(const ec_slave_t *); +const ec_pdo_t *ec_slave_find_pdo(const ec_slave_t *, uint16_t); +void ec_slave_attach_pdo_names(ec_slave_t *); + +void ec_slave_calc_port_delays(ec_slave_t *); +void ec_slave_calc_transmission_delays_rec(ec_slave_t *, uint32_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/slave_config.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/slave_config.c @@ -0,0 +1,1652 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * vim: expandtab + * + ****************************************************************************/ + +/** + \file + EtherCAT slave configuration methods. +*/ + +/****************************************************************************/ + +#include "slave_config.h" + +#include "globals.h" +#include "master.h" +#include "voe_handler.h" +#include "flag.h" +#include "ioctl.h" + +#ifdef EC_EOE +#include "eoe_request.h" +#endif + +#include +#include + +/****************************************************************************/ + +// prototypes for private methods +int ec_slave_config_prepare_fmmu(ec_slave_config_t *, ec_domain_t *, uint8_t, + ec_direction_t); +void ec_slave_config_load_default_mapping(const ec_slave_config_t *, + ec_pdo_t *); + +/****************************************************************************/ + +/** EtherCAT application-layer transition timeout. + */ +typedef struct { + struct list_head list; + ec_slave_state_t from; + ec_slave_state_t to; + unsigned int timeout_ms; +} ec_al_timeout_t; + +/****************************************************************************/ + +/** Slave configuration constructor. + * + * See ecrt_master_slave_config() for the usage of the \a alias and \a + * position parameters. + */ +void ec_slave_config_init( + ec_slave_config_t *sc, /**< Slave configuration. */ + ec_master_t *master, /**< EtherCAT master. */ + uint16_t alias, /**< Slave alias. */ + uint16_t position, /**< Slave position. */ + uint32_t vendor_id, /**< Expected vendor ID. */ + uint32_t product_code /**< Expected product code. */ + ) +{ + unsigned int i; + + sc->master = master; + + sc->alias = alias; + sc->position = position; + sc->vendor_id = vendor_id; + sc->product_code = product_code; + sc->watchdog_divider = 0; // use default + sc->watchdog_intervals = 0; // use default + + sc->slave = NULL; + + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) + ec_sync_config_init(&sc->sync_configs[i]); + + sc->used_fmmus = 0; + sc->dc_assign_activate = 0x0000; + sc->dc_sync[0].cycle_time = 0U; + sc->dc_sync[1].cycle_time = 0; + sc->dc_sync[0].shift_time = 0U; + sc->dc_sync[1].shift_time = 0; + + INIT_LIST_HEAD(&sc->sdo_configs); + INIT_LIST_HEAD(&sc->sdo_requests); + INIT_LIST_HEAD(&sc->soe_requests); + INIT_LIST_HEAD(&sc->reg_requests); + INIT_LIST_HEAD(&sc->voe_handlers); + INIT_LIST_HEAD(&sc->soe_configs); + INIT_LIST_HEAD(&sc->flags); + INIT_LIST_HEAD(&sc->al_timeouts); + +#ifdef EC_EOE + ec_eoe_request_init(&sc->eoe_ip_param_request); +#endif + + ec_coe_emerg_ring_init(&sc->emerg_ring, sc); +} + +/****************************************************************************/ + +/** Slave configuration destructor. + * + * Clears and frees a slave configuration object. + */ +void ec_slave_config_clear( + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + unsigned int i; + ec_sdo_request_t *req, *next_req; + ec_voe_handler_t *voe, *next_voe; + ec_reg_request_t *reg, *next_reg; + ec_soe_request_t *soe, *next_soe; + ec_flag_t *flag, *next_flag; + ec_al_timeout_t *timeout, *next_timeout; + + ec_slave_config_detach(sc); + + // Free sync managers + for (i = 0; i < EC_MAX_SYNC_MANAGERS; i++) + ec_sync_config_clear(&sc->sync_configs[i]); + + // free all SDO configurations + list_for_each_entry_safe(req, next_req, &sc->sdo_configs, list) { + list_del(&req->list); + ec_sdo_request_clear(req); + kfree(req); + } + + // free all SDO requests + list_for_each_entry_safe(req, next_req, &sc->sdo_requests, list) { + list_del(&req->list); + ec_sdo_request_clear(req); + kfree(req); + } + + // free all SoE requests + list_for_each_entry_safe(soe, next_soe, &sc->soe_requests, list) { + list_del(&soe->list); + ec_soe_request_clear(soe); + kfree(soe); + } + + // free all register requests + list_for_each_entry_safe(reg, next_reg, &sc->reg_requests, list) { + list_del(®->list); + ec_reg_request_clear(reg); + kfree(reg); + } + + // free all VoE handlers + list_for_each_entry_safe(voe, next_voe, &sc->voe_handlers, list) { + list_del(&voe->list); + ec_voe_handler_clear(voe); + kfree(voe); + } + + // free all SoE configurations + list_for_each_entry_safe(soe, next_soe, &sc->soe_configs, list) { + list_del(&soe->list); + ec_soe_request_clear(soe); + kfree(soe); + } + + // free all flags + list_for_each_entry_safe(flag, next_flag, &sc->flags, list) { + list_del(&flag->list); + ec_flag_clear(flag); + kfree(flag); + } + + // free all AL timeouts + list_for_each_entry_safe(timeout, next_timeout, &sc->al_timeouts, list) { + list_del(&timeout->list); + kfree(timeout); + } + + ec_coe_emerg_ring_clear(&sc->emerg_ring); +} + +/****************************************************************************/ + +/** Prepares an FMMU configuration. + * + * Configuration data for the FMMU is saved in the slave config structure and + * is written to the slave during the configuration. The FMMU configuration + * is done in a way, that the complete data range of the corresponding sync + * manager is covered. Seperate FMMUs are configured for each domain. If the + * FMMU configuration is already prepared, the function does nothing and + * returns with success. + * + * \retval >=0 Success, logical offset byte address. + * \retval <0 Error code. + */ +int ec_slave_config_prepare_fmmu( + ec_slave_config_t *sc, /**< Slave configuration. */ + ec_domain_t *domain, /**< Domain. */ + uint8_t sync_index, /**< Sync manager index. */ + ec_direction_t dir /**< PDO direction. */ + ) +{ + unsigned int i; + ec_fmmu_config_t *fmmu; + + // FMMU configuration already prepared? + for (i = 0; i < sc->used_fmmus; i++) { + fmmu = &sc->fmmu_configs[i]; + if (fmmu->domain == domain && fmmu->sync_index == sync_index) + return fmmu->logical_start_address; + } + + if (sc->used_fmmus == EC_MAX_FMMUS) { + EC_CONFIG_ERR(sc, "FMMU limit reached!\n"); + return -EOVERFLOW; + } + + fmmu = &sc->fmmu_configs[sc->used_fmmus++]; + + down(&sc->master->master_sem); + ec_fmmu_config_init(fmmu, sc, domain, sync_index, dir); + up(&sc->master->master_sem); + + return fmmu->logical_start_address; +} + +/****************************************************************************/ + +/** Attaches the configuration to the addressed slave object. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_slave_config_attach( + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + ec_slave_t *slave; + + if (sc->slave) + return 0; // already attached + + if (!(slave = ec_master_find_slave( + sc->master, sc->alias, sc->position))) { + EC_CONFIG_DBG(sc, 1, "Failed to find slave for configuration.\n"); + return -ENOENT; + } + + if (slave->config) { + EC_CONFIG_DBG(sc, 1, "Failed to attach configuration. Slave %u" + " already has a configuration!\n", slave->ring_position); + return -EEXIST; + } + + if ( +#ifdef EC_IDENT_WILDCARDS + sc->vendor_id != 0xffffffff && +#endif + slave->sii.vendor_id != sc->vendor_id + ) { + EC_CONFIG_DBG(sc, 1, "Slave %u has no matching vendor ID (0x%08X)" + " for configuration (0x%08X).\n", + slave->ring_position, slave->sii.vendor_id, sc->vendor_id); + return -EINVAL; + } + + if ( +#ifdef EC_IDENT_WILDCARDS + sc->product_code != 0xffffffff && +#endif + slave->sii.product_code != sc->product_code + ) { + EC_CONFIG_DBG(sc, 1, "Slave %u has no matching product code (0x%08X)" + " for configuration (0x%08X).\n", + slave->ring_position, slave->sii.product_code, + sc->product_code); + return -EINVAL; + } + + // attach slave + slave->config = sc; + sc->slave = slave; + + EC_CONFIG_DBG(sc, 1, "Attached slave %u.\n", slave->ring_position); + return 0; +} + +/****************************************************************************/ + +/** Detaches the configuration from a slave object. + */ +void ec_slave_config_detach( + ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + if (sc->slave) { + ec_reg_request_t *reg; + + sc->slave->config = NULL; + + // invalidate processing register request + list_for_each_entry(reg, &sc->reg_requests, list) { + if (sc->slave->fsm.reg_request == reg) { + sc->slave->fsm.reg_request = NULL; + break; + } + } + + sc->slave = NULL; + } +} + +/****************************************************************************/ + +/** Loads the default PDO assignment from the slave object. + */ +void ec_slave_config_load_default_sync_config(ec_slave_config_t *sc) +{ + uint8_t sync_index; + ec_sync_config_t *sync_config; + const ec_sync_t *sync; + + if (!sc->slave) + return; + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) { + sync_config = &sc->sync_configs[sync_index]; + if ((sync = ec_slave_get_sync(sc->slave, sync_index))) { + sync_config->dir = ec_sync_default_direction(sync); + if (sync_config->dir == EC_DIR_INVALID) + EC_SLAVE_WARN(sc->slave, + "SM%u has an invalid direction field!\n", sync_index); + ec_pdo_list_copy(&sync_config->pdos, &sync->pdos); + } + } +} + +/****************************************************************************/ + +/** Loads the default mapping for a PDO from the slave object. + */ +void ec_slave_config_load_default_mapping( + const ec_slave_config_t *sc, + ec_pdo_t *pdo + ) +{ + unsigned int i; + const ec_sync_t *sync; + const ec_pdo_t *default_pdo; + + if (!sc->slave) + return; + + EC_CONFIG_DBG(sc, 1, "Loading default mapping for PDO 0x%04X.\n", + pdo->index); + + // find PDO in any sync manager (it could be reassigned later) + for (i = 0; i < sc->slave->sii.sync_count; i++) { + sync = &sc->slave->sii.syncs[i]; + + list_for_each_entry(default_pdo, &sync->pdos.list, list) { + if (default_pdo->index != pdo->index) + continue; + + if (default_pdo->name) { + EC_CONFIG_DBG(sc, 1, "Found PDO name \"%s\".\n", + default_pdo->name); + + // take PDO name from assigned one + ec_pdo_set_name(pdo, default_pdo->name); + } + + // copy entries (= default PDO mapping) + if (ec_pdo_copy_entries(pdo, default_pdo)) + return; + + if (sc->master->debug_level) { + const ec_pdo_entry_t *entry; + list_for_each_entry(entry, &pdo->entries, list) { + EC_CONFIG_DBG(sc, 1, "Entry 0x%04X:%02X.\n", + entry->index, entry->subindex); + } + } + + return; + } + } + + EC_CONFIG_DBG(sc, 1, "No default mapping found.\n"); +} + +/****************************************************************************/ + +/** Get the number of SDO configurations. + * + * \return Number of SDO configurations. + */ +unsigned int ec_slave_config_sdo_count( + const ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + const ec_sdo_request_t *req; + unsigned int count = 0; + + list_for_each_entry(req, &sc->sdo_configs, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds an SDO configuration via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_sdo_request_t *ec_slave_config_get_sdo_by_pos_const( + const ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_sdo_request_t *req; + + list_for_each_entry(req, &sc->sdo_configs, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of IDN configurations. + * + * \return Number of SDO configurations. + */ +unsigned int ec_slave_config_idn_count( + const ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + const ec_soe_request_t *req; + unsigned int count = 0; + + list_for_each_entry(req, &sc->soe_configs, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds an IDN configuration via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_soe_request_t *ec_slave_config_get_idn_by_pos_const( + const ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_soe_request_t *req; + + list_for_each_entry(req, &sc->soe_configs, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Get the number of feature flags. + * + * \return Number of feature flags. + */ +unsigned int ec_slave_config_flag_count( + const ec_slave_config_t *sc /**< Slave configuration. */ + ) +{ + const ec_flag_t *flag; + unsigned int count = 0; + + list_for_each_entry(flag, &sc->flags, list) { + count++; + } + + return count; +} + +/****************************************************************************/ + +/** Finds a flag via its position in the list. + * + * Const version. + * + * \return Search result, or NULL. + */ +const ec_flag_t *ec_slave_config_get_flag_by_pos_const( + const ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + const ec_flag_t *flag; + + list_for_each_entry(flag, &sc->flags, list) { + if (pos--) + continue; + return flag; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a CoE SDO request via its position in the list. + * + * \return Search result, or NULL. + */ +ec_sdo_request_t *ec_slave_config_find_sdo_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_sdo_request_t *req; + + list_for_each_entry(req, &sc->sdo_requests, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a SoE request via its position in the list. + * + * \return Search result, or NULL. + */ +ec_soe_request_t *ec_slave_config_find_soe_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_soe_request_t *req; + + list_for_each_entry(req, &sc->soe_requests, list) { + if (pos--) + continue; + return req; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a register handler via its position in the list. + * + * \return Search result, or NULL. + */ +ec_reg_request_t *ec_slave_config_find_reg_request( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_reg_request_t *reg; + + list_for_each_entry(reg, &sc->reg_requests, list) { + if (pos--) + continue; + return reg; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a VoE handler via its position in the list. + * + * \return Search result, or NULL. + */ +ec_voe_handler_t *ec_slave_config_find_voe_handler( + ec_slave_config_t *sc, /**< Slave configuration. */ + unsigned int pos /**< Position in the list. */ + ) +{ + ec_voe_handler_t *voe; + + list_for_each_entry(voe, &sc->voe_handlers, list) { + if (pos--) + continue; + return voe; + } + + return NULL; +} + +/****************************************************************************/ + +/** Finds a flag. + * + * \return Search result, or NULL. + */ +ec_flag_t *ec_slave_config_find_flag( + ec_slave_config_t *sc, /**< Slave configuration. */ + const char *key /**< Flag key. */ + ) +{ + if (sc) { + ec_flag_t *flag; + list_for_each_entry(flag, &sc->flags, list) { + if (!strcmp(flag->key, key)) { + return flag; + } + } + } + + return NULL; +} + +/****************************************************************************/ + +/** Return an AL state timeout. + * + * \return Search result, or 0. + */ +unsigned int ec_slave_config_al_timeout(const ec_slave_config_t *sc, + ec_slave_state_t from, ec_slave_state_t to) +{ + ec_al_timeout_t *timeout; + + list_for_each_entry(timeout, &sc->al_timeouts, list) { + if (timeout->from == from && timeout->to == to) { + return timeout->timeout_ms; + } + } + + return 0; +} + +/***************************************************************************** + * Application interface + ****************************************************************************/ + +int ecrt_slave_config_sync_manager(ec_slave_config_t *sc, uint8_t sync_index, + ec_direction_t dir, ec_watchdog_mode_t watchdog_mode) +{ + ec_sync_config_t *sync_config; + + EC_CONFIG_DBG(sc, 1, "ecrt_slave_config_sync_manager(sc = 0x%p," + " sync_index = %u, dir = %i, watchdog_mode = %i)\n", + sc, sync_index, dir, watchdog_mode); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", sync_index); + return -ENOENT; + } + + if (dir != EC_DIR_OUTPUT && dir != EC_DIR_INPUT) { + EC_CONFIG_ERR(sc, "Invalid direction %u!\n", (unsigned int) dir); + return -EINVAL; + } + + sync_config = &sc->sync_configs[sync_index]; + sync_config->dir = dir; + sync_config->watchdog_mode = watchdog_mode; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_watchdog(ec_slave_config_t *sc, + uint16_t divider, uint16_t intervals) +{ + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, divider = %u, intervals = %u)\n", + __func__, sc, divider, intervals); + + sc->watchdog_divider = divider; + sc->watchdog_intervals = intervals; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_assign_add(ec_slave_config_t *sc, + uint8_t sync_index, uint16_t pdo_index) +{ + ec_pdo_t *pdo; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, sync_index = %u, " + "pdo_index = 0x%04X)\n", __func__, sc, sync_index, pdo_index); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", sync_index); + return -EINVAL; + } + + down(&sc->master->master_sem); + + pdo = ec_pdo_list_add_pdo(&sc->sync_configs[sync_index].pdos, pdo_index); + if (IS_ERR(pdo)) { + up(&sc->master->master_sem); + return PTR_ERR(pdo); + } + pdo->sync_index = sync_index; + + ec_slave_config_load_default_mapping(sc, pdo); + + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_assign_clear(ec_slave_config_t *sc, + uint8_t sync_index) +{ + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, sync_index = %u)\n", + __func__, sc, sync_index); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", sync_index); + return -EINVAL; + } + + down(&sc->master->master_sem); + ec_pdo_list_clear_pdos(&sc->sync_configs[sync_index].pdos); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_mapping_add(ec_slave_config_t *sc, + uint16_t pdo_index, uint16_t entry_index, uint8_t entry_subindex, + uint8_t entry_bit_length) +{ + uint8_t sync_index; + ec_pdo_t *pdo = NULL; + ec_pdo_entry_t *entry; + int retval = 0; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, " + "pdo_index = 0x%04X, entry_index = 0x%04X, " + "entry_subindex = 0x%02X, entry_bit_length = %u)\n", + __func__, sc, pdo_index, entry_index, entry_subindex, + entry_bit_length); + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) + if ((pdo = ec_pdo_list_find_pdo( + &sc->sync_configs[sync_index].pdos, pdo_index))) + break; + + if (pdo) { + down(&sc->master->master_sem); + entry = ec_pdo_add_entry(pdo, entry_index, entry_subindex, + entry_bit_length); + up(&sc->master->master_sem); + if (IS_ERR(entry)) + retval = PTR_ERR(entry); + } else { + EC_CONFIG_ERR(sc, "PDO 0x%04X is not assigned.\n", pdo_index); + retval = -ENOENT; + } + + return retval; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdo_mapping_clear(ec_slave_config_t *sc, + uint16_t pdo_index) +{ + uint8_t sync_index; + ec_pdo_t *pdo = NULL; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, pdo_index = 0x%04X)\n", + __func__, sc, pdo_index); + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) + if ((pdo = ec_pdo_list_find_pdo( + &sc->sync_configs[sync_index].pdos, pdo_index))) + break; + + if (pdo) { + down(&sc->master->master_sem); + ec_pdo_clear_entries(pdo); + up(&sc->master->master_sem); + } else { + EC_CONFIG_WARN(sc, "PDO 0x%04X is not assigned.\n", pdo_index); + } + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_pdos(ec_slave_config_t *sc, + unsigned int n_syncs, const ec_sync_info_t syncs[]) +{ + int ret; + unsigned int i, j, k; + const ec_sync_info_t *sync_info; + const ec_pdo_info_t *pdo_info; + const ec_pdo_entry_info_t *entry_info; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, n_syncs = %u, syncs = 0x%p)\n", + __func__, sc, n_syncs, syncs); + + if (!syncs) + return 0; + + for (i = 0; i < n_syncs; i++) { + sync_info = &syncs[i]; + + if (sync_info->index == (uint8_t) EC_END) + break; + + if (sync_info->index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid sync manager index %u!\n", + sync_info->index); + return -ENOENT; + } + + ret = ecrt_slave_config_sync_manager(sc, sync_info->index, + sync_info->dir, sync_info->watchdog_mode); + if (ret) + return ret; + + ecrt_slave_config_pdo_assign_clear(sc, sync_info->index); + + if (sync_info->n_pdos && sync_info->pdos) { + + for (j = 0; j < sync_info->n_pdos; j++) { + pdo_info = &sync_info->pdos[j]; + + ret = ecrt_slave_config_pdo_assign_add( + sc, sync_info->index, pdo_info->index); + if (ret) + return ret; + + ecrt_slave_config_pdo_mapping_clear(sc, pdo_info->index); + + if (pdo_info->n_entries && pdo_info->entries) { + for (k = 0; k < pdo_info->n_entries; k++) { + entry_info = &pdo_info->entries[k]; + + ret = ecrt_slave_config_pdo_mapping_add(sc, + pdo_info->index, entry_info->index, + entry_info->subindex, + entry_info->bit_length); + if (ret) + return ret; + } + } + } + } + } + + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_reg_pdo_entry( + ec_slave_config_t *sc, + uint16_t index, + uint8_t subindex, + ec_domain_t *domain, + unsigned int *bit_position + ) +{ + uint8_t sync_index; + const ec_sync_config_t *sync_config; + unsigned int bit_offset, bit_pos; + ec_pdo_t *pdo; + ec_pdo_entry_t *entry; + int sync_offset; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, domain = 0x%p, bit_position = 0x%p)\n", + __func__, sc, index, subindex, domain, bit_position); + + for (sync_index = 0; sync_index < EC_MAX_SYNC_MANAGERS; sync_index++) { + sync_config = &sc->sync_configs[sync_index]; + bit_offset = 0; + + list_for_each_entry(pdo, &sync_config->pdos.list, list) { + list_for_each_entry(entry, &pdo->entries, list) { + if (entry->index != index || entry->subindex != subindex) { + bit_offset += entry->bit_length; + } else { + bit_pos = bit_offset % 8; + if (bit_position) { + *bit_position = bit_pos; + } else if (bit_pos) { + EC_CONFIG_ERR(sc, "PDO entry 0x%04X:%02X does" + " not byte-align.\n", index, subindex); + return -EFAULT; + } + + sync_offset = ec_slave_config_prepare_fmmu( + sc, domain, sync_index, sync_config->dir); + if (sync_offset < 0) + return sync_offset; + + return sync_offset + bit_offset / 8; + } + } + } + } + + EC_CONFIG_ERR(sc, "PDO entry 0x%04X:%02X is not mapped.\n", + index, subindex); + return -ENOENT; +} + +/****************************************************************************/ + +int ecrt_slave_config_reg_pdo_entry_pos( + ec_slave_config_t *sc, + uint8_t sync_index, + unsigned int pdo_pos, + unsigned int entry_pos, + ec_domain_t *domain, + unsigned int *bit_position + ) +{ + const ec_sync_config_t *sync_config; + unsigned int bit_offset, pp, ep; + ec_pdo_t *pdo; + ec_pdo_entry_t *entry; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, sync_index = %u, pdo_pos = %u," + " entry_pos = %u, domain = 0x%p, bit_position = 0x%p)\n", + __func__, sc, sync_index, pdo_pos, entry_pos, + domain, bit_position); + + if (sync_index >= EC_MAX_SYNC_MANAGERS) { + EC_CONFIG_ERR(sc, "Invalid syncmanager position %u.\n", sync_index); + return -EINVAL; + } + + sync_config = &sc->sync_configs[sync_index]; + bit_offset = 0; + pp = 0; + + list_for_each_entry(pdo, &sync_config->pdos.list, list) { + ep = 0; + list_for_each_entry(entry, &pdo->entries, list) { + if (pp != pdo_pos || ep != entry_pos) { + bit_offset += entry->bit_length; + } else { + unsigned int bit_pos = bit_offset % 8; + int sync_offset; + + if (bit_position) { + *bit_position = bit_pos; + } else if (bit_pos) { + EC_CONFIG_ERR(sc, "PDO entry 0x%04X:%02X does" + " not byte-align.\n", + pdo->index, entry->subindex); + return -EFAULT; + } + + sync_offset = ec_slave_config_prepare_fmmu( + sc, domain, sync_index, sync_config->dir); + if (sync_offset < 0) + return sync_offset; + + return sync_offset + bit_offset / 8; + } + ep++; + } + pp++; + } + + EC_CONFIG_ERR(sc, "PDO entry specification %u/%u/%u out of range.\n", + sync_index, pdo_pos, entry_pos); + return -ENOENT; +} + +/****************************************************************************/ + +int ecrt_slave_config_dc(ec_slave_config_t *sc, uint16_t assign_activate, + uint32_t sync0_cycle_time, int32_t sync0_shift_time, + uint32_t sync1_cycle_time, int32_t sync1_shift_time) +{ + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, assign_activate = 0x%04X," + " sync0_cycle = %u, sync0_shift = %i," + " sync1_cycle = %u, sync1_shift = %i\n", + __func__, sc, assign_activate, sync0_cycle_time, sync0_shift_time, + sync1_cycle_time, sync1_shift_time); + + sc->dc_assign_activate = assign_activate; + sc->dc_sync[0].cycle_time = sync0_cycle_time; + sc->dc_sync[0].shift_time = sync0_shift_time; + sc->dc_sync[1].cycle_time = sync1_cycle_time; + sc->dc_sync[1].shift_time = sync1_shift_time; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, const uint8_t *data, size_t size) +{ + ec_slave_t *slave = sc->slave; + ec_sdo_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, data = 0x%p, size = %zu)\n", + __func__, sc, index, subindex, data, size); + + if (slave && !(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_CONFIG_WARN(sc, "Attached slave does not support CoE!\n"); + } + + if (!(req = (ec_sdo_request_t *) + kmalloc(sizeof(ec_sdo_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " SDO configuration!\n"); + return -ENOMEM; + } + + ec_sdo_request_init(req); + ecrt_sdo_request_index(req, index, subindex); + + ret = ec_sdo_request_copy_data(req, data, size); + if (ret < 0) { + ec_sdo_request_clear(req); + kfree(req); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->sdo_configs); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo8(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, uint8_t value) +{ + uint8_t data[1]; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, value = %u)\n", + __func__, sc, index, subindex, (unsigned int) value); + + EC_WRITE_U8(data, value); + return ecrt_slave_config_sdo(sc, index, subindex, data, 1); +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo16(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, uint16_t value) +{ + uint8_t data[2]; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, value = %u)\n", + __func__, sc, index, subindex, value); + + EC_WRITE_U16(data, value); + return ecrt_slave_config_sdo(sc, index, subindex, data, 2); +} + +/****************************************************************************/ + +int ecrt_slave_config_sdo32(ec_slave_config_t *sc, uint16_t index, + uint8_t subindex, uint32_t value) +{ + uint8_t data[4]; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "subindex = 0x%02X, value = %u)\n", + __func__, sc, index, subindex, value); + + EC_WRITE_U32(data, value); + return ecrt_slave_config_sdo(sc, index, subindex, data, 4); +} + +/****************************************************************************/ + +int ecrt_slave_config_complete_sdo(ec_slave_config_t *sc, uint16_t index, + const uint8_t *data, size_t size) +{ + ec_slave_t *slave = sc->slave; + ec_sdo_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, index = 0x%04X, " + "data = 0x%p, size = %zu)\n", __func__, sc, index, data, size); + + if (slave && !(slave->sii.mailbox_protocols & EC_MBOX_COE)) { + EC_CONFIG_WARN(sc, "Attached slave does not support CoE!\n"); + } + + if (!(req = (ec_sdo_request_t *) + kmalloc(sizeof(ec_sdo_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " SDO configuration!\n"); + return -ENOMEM; + } + + ec_sdo_request_init(req); + ecrt_sdo_request_index(req, index, 0); + req->complete_access = 1; + + ret = ec_sdo_request_copy_data(req, data, size); + if (ret < 0) { + ec_sdo_request_clear(req); + kfree(req); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->sdo_configs); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_size(ec_slave_config_t *sc, size_t elements) +{ + return ec_coe_emerg_ring_size(&sc->emerg_ring, elements); +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_pop(ec_slave_config_t *sc, uint8_t *target) +{ + return ec_coe_emerg_ring_pop(&sc->emerg_ring, target); +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_clear(ec_slave_config_t *sc) +{ + return ec_coe_emerg_ring_clear_ring(&sc->emerg_ring); +} + +/****************************************************************************/ + +int ecrt_slave_config_emerg_overruns(const ec_slave_config_t *sc) +{ + return ec_coe_emerg_ring_overruns(&sc->emerg_ring); +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_sdo_request(), but with ERR_PTR() return + * value. + */ +ec_sdo_request_t *ecrt_slave_config_create_sdo_request_err( + ec_slave_config_t *sc, uint16_t index, uint8_t subindex, size_t size) +{ + ec_sdo_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, " + "index = 0x%04X, subindex = 0x%02X, size = %zu)\n", + __func__, sc, index, subindex, size); + + if (!(req = (ec_sdo_request_t *) + kmalloc(sizeof(ec_sdo_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate SDO request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ec_sdo_request_init(req); + ecrt_sdo_request_index(req, index, subindex); + + ret = ec_sdo_request_alloc(req, size); + if (ret < 0) { + ec_sdo_request_clear(req); + kfree(req); + return ERR_PTR(ret); + } + + // prepare data for optional writing + memset(req->data, 0x00, size); + req->data_size = size; + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->sdo_requests); + up(&sc->master->master_sem); + + return req; +} + +/****************************************************************************/ + +ec_sdo_request_t *ecrt_slave_config_create_sdo_request( + ec_slave_config_t *sc, uint16_t index, uint8_t subindex, size_t size) +{ + ec_sdo_request_t *s = ecrt_slave_config_create_sdo_request_err(sc, index, + subindex, size); + return IS_ERR(s) ? NULL : s; +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_soe_request(), but with ERR_PTR() return + * value. + */ +ec_soe_request_t *ecrt_slave_config_create_soe_request_err( + ec_slave_config_t *sc, uint8_t drive_no, uint16_t idn, size_t size) +{ + ec_soe_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, " + "drive_no = 0x%02X, idn = 0x%04X, size = %zu)\n", + __func__, sc, drive_no, idn, size); + + if (!(req = (ec_soe_request_t *) + kmalloc(sizeof(ec_soe_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate IDN request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ec_soe_request_init(req); + ecrt_soe_request_idn(req, drive_no, idn); + + ret = ec_soe_request_alloc(req, size); + if (ret < 0) { + ec_soe_request_clear(req); + kfree(req); + return ERR_PTR(ret); + } + + // prepare data for optional writing + memset(req->data, 0x00, size); + req->data_size = size; + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->soe_requests); + up(&sc->master->master_sem); + + return req; +} + +/****************************************************************************/ + +ec_soe_request_t *ecrt_slave_config_create_soe_request( + ec_slave_config_t *sc, uint8_t drive_no, uint16_t idn, size_t size) +{ + ec_soe_request_t *req = ecrt_slave_config_create_soe_request_err(sc, + drive_no, idn, size); + return IS_ERR(req) ? NULL : req; +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_reg_request(), but with ERR_PTR() return + * value. + */ +ec_reg_request_t *ecrt_slave_config_create_reg_request_err( + ec_slave_config_t *sc, size_t size) +{ + ec_reg_request_t *reg; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, size = %zu)\n", + __func__, sc, size); + + if (!(reg = (ec_reg_request_t *) + kmalloc(sizeof(ec_reg_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate register request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ret = ec_reg_request_init(reg, size); + if (ret) { + kfree(reg); + return ERR_PTR(ret); + } + + down(&sc->master->master_sem); + list_add_tail(®->list, &sc->reg_requests); + up(&sc->master->master_sem); + + return reg; +} + +/****************************************************************************/ + +ec_reg_request_t *ecrt_slave_config_create_reg_request( + ec_slave_config_t *sc, size_t size) +{ + ec_reg_request_t *reg = + ecrt_slave_config_create_reg_request_err(sc, size); + return IS_ERR(reg) ? NULL : reg; +} + +/****************************************************************************/ + +/** Same as ecrt_slave_config_create_voe_handler(), but with ERR_PTR() return + * value. + */ +ec_voe_handler_t *ecrt_slave_config_create_voe_handler_err( + ec_slave_config_t *sc, size_t size) +{ + ec_voe_handler_t *voe; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, size = %zu)\n", __func__, sc, size); + + if (!(voe = (ec_voe_handler_t *) + kmalloc(sizeof(ec_voe_handler_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate VoE request memory!\n"); + return ERR_PTR(-ENOMEM); + } + + ret = ec_voe_handler_init(voe, sc, size); + if (ret < 0) { + kfree(voe); + return ERR_PTR(ret); + } + + down(&sc->master->master_sem); + list_add_tail(&voe->list, &sc->voe_handlers); + up(&sc->master->master_sem); + + return voe; +} + +/****************************************************************************/ + +ec_voe_handler_t *ecrt_slave_config_create_voe_handler( + ec_slave_config_t *sc, size_t size) +{ + ec_voe_handler_t *voe = ecrt_slave_config_create_voe_handler_err(sc, + size); + return IS_ERR(voe) ? NULL : voe; +} + +/****************************************************************************/ + +int ecrt_slave_config_state(const ec_slave_config_t *sc, + ec_slave_config_state_t *state) +{ + const ec_slave_t *slave = sc->slave; + + state->online = slave ? 1 : 0; + if (state->online) { + state->operational = + slave->current_state == EC_SLAVE_STATE_OP && !slave->force_config; + state->al_state = slave->current_state; + } else { + state->operational = 0; + state->al_state = EC_SLAVE_STATE_UNKNOWN; + } + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_idn(ec_slave_config_t *sc, uint8_t drive_no, + uint16_t idn, ec_al_state_t state, const uint8_t *data, + size_t size) +{ + ec_slave_t *slave = sc->slave; + ec_soe_request_t *req; + int ret; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, drive_no = %u, idn = 0x%04X, " + "state = %u, data = 0x%p, size = %zu)\n", + __func__, sc, drive_no, idn, state, data, size); + + if (drive_no > 7) { + EC_CONFIG_ERR(sc, "Invalid drive number %u!\n", + (unsigned int) drive_no); + return -EINVAL; + } + + if (state != EC_AL_STATE_PREOP && state != EC_AL_STATE_SAFEOP) { + EC_CONFIG_ERR(sc, "AL state for IDN config" + " must be PREOP or SAFEOP!\n"); + return -EINVAL; + } + + if (slave && !(slave->sii.mailbox_protocols & EC_MBOX_SOE)) { + EC_CONFIG_WARN(sc, "Attached slave does not support SoE!\n"); + } + + if (!(req = (ec_soe_request_t *) + kmalloc(sizeof(ec_soe_request_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " IDN configuration!\n"); + return -ENOMEM; + } + + ec_soe_request_init(req); + ec_soe_request_set_drive_no(req, drive_no); + ec_soe_request_set_idn(req, idn); + req->al_state = state; + + ret = ec_soe_request_copy_data(req, data, size); + if (ret < 0) { + ec_soe_request_clear(req); + kfree(req); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&req->list, &sc->soe_configs); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_flag(ec_slave_config_t *sc, const char *key, + int32_t value) +{ + ec_flag_t *flag; + + EC_CONFIG_DBG(sc, 1, "%s(sc = 0x%p, key = %s, value = %i)\n", + __func__, sc, key, value); + + + flag = ec_slave_config_find_flag(sc, key); + if (flag) { + flag->value = value; // overwrite value + } + else { // new flag + int ret; + + if (!(flag = (ec_flag_t *) kmalloc(sizeof(ec_flag_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for flag!\n"); + return -ENOMEM; + } + + ret = ec_flag_init(flag, key, value); + if (ret) { + kfree(flag); + return ret; + } + + down(&sc->master->master_sem); + list_add_tail(&flag->list, &sc->flags); + up(&sc->master->master_sem); + } + return 0; +} + +/****************************************************************************/ + +#ifdef EC_EOE + +int ecrt_slave_config_eoe_mac_address(ec_slave_config_t *sc, + const unsigned char *mac_address) +{ + memcpy(sc->eoe_ip_param_request.mac_address, mac_address, EC_ETH_ALEN); + sc->eoe_ip_param_request.mac_address_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_ip_address(ec_slave_config_t *sc, + struct in_addr ip_address) +{ + sc->eoe_ip_param_request.ip_address = ip_address; + sc->eoe_ip_param_request.ip_address_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_subnet_mask(ec_slave_config_t *sc, + struct in_addr subnet_mask) +{ + sc->eoe_ip_param_request.subnet_mask = subnet_mask; + sc->eoe_ip_param_request.subnet_mask_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_default_gateway(ec_slave_config_t *sc, + struct in_addr gateway_address) +{ + sc->eoe_ip_param_request.gateway = gateway_address; + sc->eoe_ip_param_request.gateway_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_dns_address(ec_slave_config_t *sc, + struct in_addr dns_address) +{ + sc->eoe_ip_param_request.dns = dns_address; + sc->eoe_ip_param_request.dns_included = 1; + return 0; +} + +/****************************************************************************/ + +int ecrt_slave_config_eoe_hostname(ec_slave_config_t *sc, + const char *name) +{ + strncpy(sc->eoe_ip_param_request.name, name, EC_MAX_HOSTNAME_SIZE - 1); + sc->eoe_ip_param_request.name_included = 1; + return 0; +} + +#endif + +/****************************************************************************/ + +int ecrt_slave_config_state_timeout(ec_slave_config_t *sc, + ec_al_state_t from, ec_al_state_t to, unsigned int timeout_ms) +{ + ec_al_timeout_t *timeout; + ec_slave_state_t from_state, to_state; + + if (from != EC_AL_STATE_INIT && from != EC_AL_STATE_PREOP && + from != EC_AL_STATE_SAFEOP && from != EC_AL_STATE_OP) { + EC_CONFIG_ERR(sc, "Invalid from state %i.\n", from); + return -EINVAL; + } + if (to != EC_AL_STATE_INIT && to != EC_AL_STATE_PREOP && + to != EC_AL_STATE_SAFEOP && to != EC_AL_STATE_OP) { + EC_CONFIG_ERR(sc, "Invalid to state %i.\n", to); + return -EINVAL; + } + + from_state = (ec_slave_state_t) from; + to_state = (ec_slave_state_t) to; + + /* try to find an already configured timeout. */ + list_for_each_entry(timeout, &sc->al_timeouts, list) { + if (timeout->from == from_state && timeout->to == to_state) { + if (timeout_ms == 0) { + // delete configured value + list_del(&timeout->list); + kfree(timeout); + return 0; + } + timeout->timeout_ms = timeout_ms; + return 0; + } + } + + if (timeout_ms == 0) { + return 0; + } + + /* no timeout found. create one. */ + if (!(timeout = (ec_al_timeout_t *) + kmalloc(sizeof(ec_al_timeout_t), GFP_KERNEL))) { + EC_CONFIG_ERR(sc, "Failed to allocate memory for" + " AL timeout configuration!\n"); + return -ENOMEM; + } + + timeout->from = from_state; + timeout->to = to_state; + timeout->timeout_ms = timeout_ms; + + down(&sc->master->master_sem); + list_add_tail(&timeout->list, &sc->al_timeouts); + up(&sc->master->master_sem); + return 0; +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_slave_config_sync_manager); +EXPORT_SYMBOL(ecrt_slave_config_watchdog); +EXPORT_SYMBOL(ecrt_slave_config_pdo_assign_add); +EXPORT_SYMBOL(ecrt_slave_config_pdo_assign_clear); +EXPORT_SYMBOL(ecrt_slave_config_pdo_mapping_add); +EXPORT_SYMBOL(ecrt_slave_config_pdo_mapping_clear); +EXPORT_SYMBOL(ecrt_slave_config_pdos); +EXPORT_SYMBOL(ecrt_slave_config_reg_pdo_entry); +EXPORT_SYMBOL(ecrt_slave_config_reg_pdo_entry_pos); +EXPORT_SYMBOL(ecrt_slave_config_dc); +EXPORT_SYMBOL(ecrt_slave_config_sdo); +EXPORT_SYMBOL(ecrt_slave_config_sdo8); +EXPORT_SYMBOL(ecrt_slave_config_sdo16); +EXPORT_SYMBOL(ecrt_slave_config_sdo32); +EXPORT_SYMBOL(ecrt_slave_config_complete_sdo); +EXPORT_SYMBOL(ecrt_slave_config_emerg_size); +EXPORT_SYMBOL(ecrt_slave_config_emerg_pop); +EXPORT_SYMBOL(ecrt_slave_config_emerg_clear); +EXPORT_SYMBOL(ecrt_slave_config_emerg_overruns); +EXPORT_SYMBOL(ecrt_slave_config_create_sdo_request); +EXPORT_SYMBOL(ecrt_slave_config_create_soe_request); +EXPORT_SYMBOL(ecrt_slave_config_create_voe_handler); +EXPORT_SYMBOL(ecrt_slave_config_create_reg_request); +EXPORT_SYMBOL(ecrt_slave_config_state); +EXPORT_SYMBOL(ecrt_slave_config_idn); +EXPORT_SYMBOL(ecrt_slave_config_flag); +#ifdef EOE +EXPORT_SYMBOL(ecrt_slave_config_eoe_mac_address); +EXPORT_SYMBOL(ecrt_slave_config_eoe_ip_address); +EXPORT_SYMBOL(ecrt_slave_config_eoe_subnet_mask); +EXPORT_SYMBOL(ecrt_slave_config_eoe_default_gateway); +EXPORT_SYMBOL(ecrt_slave_config_eoe_dns_address); +EXPORT_SYMBOL(ecrt_slave_config_eoe_hostname); +#endif +EXPORT_SYMBOL(ecrt_slave_config_state_timeout); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/slave_config.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/slave_config.h @@ -0,0 +1,196 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2024 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT slave configuration structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SLAVE_CONFIG_H__ +#define __EC_SLAVE_CONFIG_H__ + +#include + +#include "globals.h" +#include "slave.h" +#include "sync_config.h" +#include "fmmu_config.h" +#include "coe_emerg_ring.h" +#include "flag.h" + +/****************************************************************************/ + +/** Convenience macro for printing configuration-specific information to + * syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_INFO(sc, fmt, args...) \ + printk(KERN_INFO "EtherCAT %u %u:%u: " fmt, sc->master->index, \ + sc->alias, sc->position, ##args) + +/** Convenience macro for printing configuration-specific errors to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_ERR(sc, fmt, args...) \ + printk(KERN_ERR "EtherCAT ERROR %u %u:%u: " fmt, sc->master->index, \ + sc->alias, sc->position, ##args) + +/** Convenience macro for printing configuration-specific warnings to syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_WARN(sc, fmt, args...) \ + printk(KERN_WARNING "EtherCAT WARNING %u %u:%u: " fmt, \ + sc->master->index, sc->alias, sc->position, ##args) + +/** Convenience macro for printing configuration-specific debug messages to + * syslog. + * + * This will print the message in \a fmt with a prefixed + * "EtherCAT :: ", where INDEX is the master index + * and ALIAS and POSITION identify the configuration. + * + * \param sc EtherCAT slave configuration + * \param level Debug level. Master's debug level must be >= \a level for + * output. + * \param fmt format string (like in printf()) + * \param args arguments (optional) + */ +#define EC_CONFIG_DBG(sc, level, fmt, args...) \ + do { \ + if (sc->master->debug_level >= level) { \ + printk(KERN_DEBUG "EtherCAT DEBUG %u %u:%u: " fmt, \ + sc->master->index, sc->alias, sc->position, ##args); \ + } \ + } while (0) + +/****************************************************************************/ + +/** EtherCAT slave configuration. + */ +struct ec_slave_config { + struct list_head list; /**< List item. */ + ec_master_t *master; /**< Master owning the slave configuration. */ + + uint16_t alias; /**< Slave alias. */ + uint16_t position; /**< Index after alias. If alias is zero, this is the + ring position. */ + uint32_t vendor_id; /**< Slave vendor ID. */ + uint32_t product_code; /**< Slave product code. */ + + uint16_t watchdog_divider; /**< Watchdog divider as a number of 40ns + intervals (see spec. reg. 0x0400). */ + uint16_t watchdog_intervals; /**< Process data watchdog intervals (see + spec. reg. 0x0420). */ + + ec_slave_t *slave; /**< Slave pointer. This is \a NULL, if the slave is + offline. */ + + ec_sync_config_t sync_configs[EC_MAX_SYNC_MANAGERS]; /**< Sync manager + configurations. */ + ec_fmmu_config_t fmmu_configs[EC_MAX_FMMUS]; /**< FMMU configurations. */ + uint8_t used_fmmus; /**< Number of FMMUs used. */ + uint16_t dc_assign_activate; /**< Vendor-specific AssignActivate word. */ + ec_sync_signal_t dc_sync[EC_SYNC_SIGNAL_COUNT]; /**< DC sync signals. */ + + struct list_head sdo_configs; /**< List of SDO configurations. */ + struct list_head sdo_requests; /**< List of SDO requests. */ + struct list_head soe_requests; /**< List of SoE requests. */ + struct list_head voe_handlers; /**< List of VoE handlers. */ + struct list_head reg_requests; /**< List of register requests. */ + struct list_head soe_configs; /**< List of SoE configurations. */ + struct list_head flags; /**< List of feature flags. */ + struct list_head al_timeouts; /**< List of specific AL state timeouts. */ + +#ifdef EC_EOE + ec_eoe_request_t eoe_ip_param_request; /**< EoE IP parameters. */ +#endif + + ec_coe_emerg_ring_t emerg_ring; /**< CoE emergency ring buffer. */ +}; + +/****************************************************************************/ + +void ec_slave_config_init(ec_slave_config_t *, ec_master_t *, uint16_t, + uint16_t, uint32_t, uint32_t); +void ec_slave_config_clear(ec_slave_config_t *); + +int ec_slave_config_attach(ec_slave_config_t *); +void ec_slave_config_detach(ec_slave_config_t *); + +void ec_slave_config_load_default_sync_config(ec_slave_config_t *); + +unsigned int ec_slave_config_sdo_count(const ec_slave_config_t *); +const ec_sdo_request_t *ec_slave_config_get_sdo_by_pos_const( + const ec_slave_config_t *, unsigned int); +unsigned int ec_slave_config_idn_count(const ec_slave_config_t *); +const ec_soe_request_t *ec_slave_config_get_idn_by_pos_const( + const ec_slave_config_t *, unsigned int); +unsigned int ec_slave_config_flag_count(const ec_slave_config_t *); +const ec_flag_t *ec_slave_config_get_flag_by_pos_const( + const ec_slave_config_t *, unsigned int); +ec_sdo_request_t *ec_slave_config_find_sdo_request(ec_slave_config_t *, + unsigned int); +ec_soe_request_t *ec_slave_config_find_soe_request(ec_slave_config_t *, + unsigned int); +ec_reg_request_t *ec_slave_config_find_reg_request(ec_slave_config_t *, + unsigned int); +ec_voe_handler_t *ec_slave_config_find_voe_handler(ec_slave_config_t *, + unsigned int); +ec_flag_t *ec_slave_config_find_flag(ec_slave_config_t *, const char *); + +ec_sdo_request_t *ecrt_slave_config_create_sdo_request_err( + ec_slave_config_t *, uint16_t, uint8_t, size_t); +ec_soe_request_t *ecrt_slave_config_create_soe_request_err( + ec_slave_config_t *, uint8_t, uint16_t, size_t); +ec_voe_handler_t *ecrt_slave_config_create_voe_handler_err( + ec_slave_config_t *, size_t); +ec_reg_request_t *ecrt_slave_config_create_reg_request_err( + ec_slave_config_t *, size_t); + +unsigned int ec_slave_config_al_timeout(const ec_slave_config_t *, + ec_slave_state_t, ec_slave_state_t); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/soe_errors.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/soe_errors.c @@ -0,0 +1,88 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT SoE errors. +*/ + +/****************************************************************************/ + +#include "globals.h" + +/****************************************************************************/ + +/** SoE error codes. + */ +const ec_code_msg_t soe_error_codes[] = { + {0x1001, "No IDN"}, + {0x1009, "Invalid access to element 1"}, + {0x2001, "No name"}, + {0x2002, "Name transmission too short"}, + {0x2003, "Name transmission too long"}, + {0x2004, "Name cannot be changed, read only"}, + {0x2005, "Name is write protected at this time"}, + {0x3002, "Attribute transmission too short"}, + {0x3003, "Attribute transmission too long"}, + {0x3004, "Attribute cannot be changed, read only"}, + {0x3005, "Attribute is write protected at this time"}, + {0x4001, "No unit"}, + {0x4002, "Unit transmission too short"}, + {0x4003, "Unit transmission too long"}, + {0x4004, "Unit cannot be changed, read only"}, + {0x4005, "Unit is write proteced at this time"}, + {0x5001, "No minimum input value"}, + {0x5002, "Minimum input value transmission too short"}, + {0x5003, "Minimum input value transmission too long"}, + {0x5004, "Minimum input value cannot be changed, read only"}, + {0x5005, "Minimum input value is write protected at this time"}, + {0x6001, "No maximum input value"}, + {0x6002, "Maximum input value transmission too short"}, + {0x6003, "Maximum input value transmission too long"}, + {0x6004, "Maximum input value cannot be changed, read only"}, + {0x6005, "Maximum input value is write protected at this time"}, + {0x7002, "Operation data value transmission too short"}, + {0x7003, "Operation data value transmission too long"}, + {0x7004, "Operation data value cannot be changed, read only"}, + {0x7005, "Operation data value is write protected at this time"}, + {0x7006, "Operation data value is smaller than the minimum input value"}, + {0x7007, "Operation data value is greater than the minimum input value"}, + {0x7008, "Invalid operation data"}, + {0x7009, "Operation data is write protected by a password"}, + {0x700A, "Operation data is write protected"}, + {0x700B, "Invalid indirect addressing"}, + {0x700C, "Operation data is write protected due to other settings"}, + {0x700D, "Reserved"}, + {0x7010, "Procedure command already active"}, + {0x7011, "Procedure command not interruptible"}, + {0x7012, "Procedure command is at this time not executable"}, + {0x7013, "Procedure command not executable"}, + {0x7014, "No data state"}, + {0x8001, "No default value"}, + {0x8002, "Default value transmission too long"}, + {0x8004, "Default value cannot be changed, read only"}, + {0x800A, "Invalid drive number"}, + {0x800B, "General error"}, + {0x800C, "No element addressed"}, + {} +}; + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/soe_request.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/soe_request.c @@ -0,0 +1,333 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2023 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Sercos-over-EtherCAT request functions. + */ + +/****************************************************************************/ + +#include +#include +#include + +#include "soe_request.h" + +/****************************************************************************/ + +/** Default timeout in ms to wait for SoE responses. + */ +#define EC_SOE_REQUEST_RESPONSE_TIMEOUT 1000 + +/****************************************************************************/ + +void ec_soe_request_clear_data(ec_soe_request_t *); + +/****************************************************************************/ + +/** SoE request constructor. + */ +void ec_soe_request_init( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + INIT_LIST_HEAD(&req->list); + req->drive_no = 0x00; + req->idn = 0x0000; + req->al_state = EC_AL_STATE_INIT; + req->data = NULL; + req->mem_size = 0; + req->data_size = 0; + req->issue_timeout = 0; // no timeout + req->dir = EC_DIR_INVALID; + req->state = EC_INT_REQUEST_INIT; + req->jiffies_start = 0U; + req->jiffies_sent = 0U; + req->error_code = 0x0000; +} + +/****************************************************************************/ + +/** SoE request destructor. + */ +void ec_soe_request_clear( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + ec_soe_request_clear_data(req); +} + +/****************************************************************************/ + +/** Copy another SoE request. + * + * \return Zero on success, otherwise a negative error code. + */ +int ec_soe_request_copy( + ec_soe_request_t *req, /**< SoE request. */ + const ec_soe_request_t *other /**< Other SoE request to copy from. */ + ) +{ + req->drive_no = other->drive_no; + req->idn = other->idn; + req->al_state = other->al_state; + return ec_soe_request_copy_data(req, other->data, other->data_size); +} + +/****************************************************************************/ + +/** Set drive number. + */ +void ec_soe_request_set_drive_no( + ec_soe_request_t *req, /**< SoE request. */ + uint8_t drive_no /** Drive Number. */ + ) +{ + req->drive_no = drive_no; +} + +/****************************************************************************/ + +/** Set IDN. + */ +void ec_soe_request_set_idn( + ec_soe_request_t *req, /**< SoE request. */ + uint16_t idn /** IDN. */ + ) +{ + req->idn = idn; +} + +/****************************************************************************/ + +/** Free allocated memory. + */ +void ec_soe_request_clear_data( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + if (req->data) { + kfree(req->data); + req->data = NULL; + } + + req->mem_size = 0; + req->data_size = 0; +} + +/****************************************************************************/ + +/** Pre-allocates the data memory. + * + * If the \a mem_size is already bigger than \a size, nothing is done. + * + * \return 0 on success, otherwise -ENOMEM. + */ +int ec_soe_request_alloc( + ec_soe_request_t *req, /**< SoE request. */ + size_t size /**< Data size to allocate. */ + ) +{ + if (size <= req->mem_size) + return 0; + + ec_soe_request_clear_data(req); + + if (!(req->data = (uint8_t *) kmalloc(size, GFP_KERNEL))) { + EC_ERR("Failed to allocate %zu bytes of SoE memory.\n", size); + return -ENOMEM; + } + + req->mem_size = size; + req->data_size = 0; + return 0; +} + +/****************************************************************************/ + +/** Copies SoE data from an external source. + * + * If the \a mem_size is to small, new memory is allocated. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_soe_request_copy_data( + ec_soe_request_t *req, /**< SoE request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + int ret = ec_soe_request_alloc(req, size); + if (ret < 0) + return ret; + + memcpy(req->data, source, size); + req->data_size = size; + return 0; +} + +/****************************************************************************/ + +/** Copies SoE data from an external source. + * + * If the \a mem_size is to small, new memory is allocated. + * + * \retval 0 Success. + * \retval <0 Error code. + */ +int ec_soe_request_append_data( + ec_soe_request_t *req, /**< SoE request. */ + const uint8_t *source, /**< Source data. */ + size_t size /**< Number of bytes in \a source. */ + ) +{ + if (req->data_size + size > req->mem_size) { + size_t new_size = req->mem_size ? req->mem_size * 2 : size; + uint8_t *new_data = (uint8_t *) kmalloc(new_size, GFP_KERNEL); + if (!new_data) { + EC_ERR("Failed to allocate %zu bytes of SoE memory.\n", + new_size); + return -ENOMEM; + } + memcpy(new_data, req->data, req->data_size); + kfree(req->data); + req->data = new_data; + req->mem_size = new_size; + } + + memcpy(req->data + req->data_size, source, size); + req->data_size += size; + return 0; +} + +/****************************************************************************/ + +/** Request a read operation. + */ +int ec_soe_request_read( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + req->dir = EC_DIR_INPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->error_code = 0x0000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +/** Request a write operation. + */ +int ec_soe_request_write( + ec_soe_request_t *req /**< SoE request. */ + ) +{ + req->dir = EC_DIR_OUTPUT; + req->state = EC_INT_REQUEST_QUEUED; + req->error_code = 0x0000; + req->jiffies_start = jiffies; + return 0; +} + +/****************************************************************************/ + +/** Checks, if the timeout was exceeded. + * + * \return non-zero if the timeout was exceeded, else zero. + */ +int ec_soe_request_timed_out(const ec_soe_request_t *req /**< SDO request. */) +{ + return req->issue_timeout + && jiffies - req->jiffies_start > HZ * req->issue_timeout / 1000; +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +int ecrt_soe_request_idn(ec_soe_request_t *req, uint8_t drive_no, + uint16_t idn) +{ + req->drive_no = drive_no; + req->idn = idn; + return 0; +} + +/****************************************************************************/ + +int ecrt_soe_request_timeout(ec_soe_request_t *req, uint32_t timeout) +{ + req->issue_timeout = timeout; + return 0; +} + +/****************************************************************************/ + +uint8_t *ecrt_soe_request_data(const ec_soe_request_t *req) +{ + return req->data; +} + +/****************************************************************************/ + +size_t ecrt_soe_request_data_size(const ec_soe_request_t *req) +{ + return req->data_size; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_soe_request_state(const ec_soe_request_t *req) +{ + return ec_request_state_translation_table[req->state]; +} + +/****************************************************************************/ + +int ecrt_soe_request_read(ec_soe_request_t *req) +{ + return ec_soe_request_read(req); +} + +/****************************************************************************/ + +int ecrt_soe_request_write(ec_soe_request_t *req) +{ + return ec_soe_request_write(req); +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_soe_request_idn); +EXPORT_SYMBOL(ecrt_soe_request_timeout); +EXPORT_SYMBOL(ecrt_soe_request_data); +EXPORT_SYMBOL(ecrt_soe_request_data_size); +EXPORT_SYMBOL(ecrt_soe_request_state); +EXPORT_SYMBOL(ecrt_soe_request_read); +EXPORT_SYMBOL(ecrt_soe_request_write); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/soe_request.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/soe_request.h @@ -0,0 +1,76 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + EtherCAT SoE request structure. +*/ + +/****************************************************************************/ + +#ifndef __EC_SOE_REQUEST_H__ +#define __EC_SOE_REQUEST_H__ + +#include + +#include "globals.h" + +/****************************************************************************/ + +/** Sercos-over-EtherCAT request. + */ +struct ec_soe_request { + struct list_head list; /**< List item. */ + uint8_t drive_no; /**< Drive number. */ + uint16_t idn; /**< Sercos ID-Number. */ + ec_al_state_t al_state; /**< AL state (only valid for IDN config). */ + uint8_t *data; /**< Pointer to SDO data. */ + size_t mem_size; /**< Size of SDO data memory. */ + size_t data_size; /**< Size of SDO data. */ + uint32_t issue_timeout; /**< Maximum time in ms, the processing of the + request may take. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means writing to the + slave, EC_DIR_INPUT means reading from the slave. */ + ec_internal_request_state_t state; /**< Request state. */ + unsigned long jiffies_start; /**< Jiffies, when the request was issued. */ + unsigned long jiffies_sent; /**< Jiffies, when the upload/download + request was sent. */ + uint16_t error_code; /**< SoE error code. */ +}; + +/****************************************************************************/ + +void ec_soe_request_init(ec_soe_request_t *); +void ec_soe_request_clear(ec_soe_request_t *); + +int ec_soe_request_copy(ec_soe_request_t *, const ec_soe_request_t *); +void ec_soe_request_set_drive_no(ec_soe_request_t *, uint8_t); +void ec_soe_request_set_idn(ec_soe_request_t *, uint16_t); +int ec_soe_request_alloc(ec_soe_request_t *, size_t); +int ec_soe_request_copy_data(ec_soe_request_t *, const uint8_t *, size_t); +int ec_soe_request_append_data(ec_soe_request_t *, const uint8_t *, size_t); +int ec_soe_request_read(ec_soe_request_t *); +int ec_soe_request_write(ec_soe_request_t *); +int ec_soe_request_timed_out(const ec_soe_request_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sync.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sync.c @@ -0,0 +1,170 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager methods. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "slave.h" +#include "master.h" +#include "pdo.h" +#include "sync.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sync_init( + ec_sync_t *sync, /**< EtherCAT sync manager. */ + ec_slave_t *slave /**< EtherCAT slave. */ + ) +{ + sync->slave = slave; + sync->physical_start_address = 0x0000; + sync->default_length = 0x0000; + sync->control_register = 0x00; + sync->enable = 0x00; + ec_pdo_list_init(&sync->pdos); +} + +/****************************************************************************/ + +/** Copy constructor. + */ +void ec_sync_init_copy( + ec_sync_t *sync, /**< EtherCAT sync manager. */ + const ec_sync_t *other /**< Sync manager to copy from. */ + ) +{ + sync->slave = other->slave; + sync->physical_start_address = other->physical_start_address; + sync->default_length = other->default_length; + sync->control_register = other->control_register; + sync->enable = other->enable; + ec_pdo_list_init(&sync->pdos); + ec_pdo_list_copy(&sync->pdos, &other->pdos); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_sync_clear( + ec_sync_t *sync /**< EtherCAT sync manager. */ + ) +{ + ec_pdo_list_clear(&sync->pdos); +} + +/****************************************************************************/ + +/** Initializes a sync manager configuration page. + * + * The referenced memory (\a data) must be at least \a EC_SYNC_SIZE bytes. + */ +void ec_sync_page( + const ec_sync_t *sync, /**< Sync manager. */ + uint8_t sync_index, /**< Index of the sync manager. */ + uint16_t data_size, /**< Data size. */ + const ec_sync_config_t *sync_config, /**< Configuration. */ + uint8_t pdo_xfer, /**< Non-zero, if PDOs will be transferred via this + sync manager. */ + uint8_t *data /**> Configuration memory. */ + ) +{ + // enable only if (SII enable is set or PDO xfer) + // and size is > 0 and SM is not virtual + uint16_t enable = ((sync->enable & 0x01) || pdo_xfer) + && data_size + && ((sync->enable & 0x04) == 0); + uint8_t control = sync->control_register; + + if (sync_config) { + + switch (sync_config->dir) { + case EC_DIR_OUTPUT: + case EC_DIR_INPUT: + EC_WRITE_BIT(&control, 2, + sync_config->dir == EC_DIR_OUTPUT ? 1 : 0); + EC_WRITE_BIT(&control, 3, 0); + break; + default: + break; + } + + switch (sync_config->watchdog_mode) { + case EC_WD_ENABLE: + case EC_WD_DISABLE: + EC_WRITE_BIT(&control, 6, + sync_config->watchdog_mode == EC_WD_ENABLE); + break; + default: + break; + } + } + + EC_SLAVE_DBG(sync->slave, 1, "SM%u: Addr 0x%04X, Size %3u," + " Ctrl 0x%02X, En %u\n", + sync_index, sync->physical_start_address, + data_size, control, enable); + + EC_WRITE_U16(data, sync->physical_start_address); + EC_WRITE_U16(data + 2, data_size); + EC_WRITE_U8 (data + 4, control); + EC_WRITE_U8 (data + 5, 0x00); // status byte (read only) + EC_WRITE_U16(data + 6, enable); +} + +/****************************************************************************/ + +/** Adds a PDO to the list of known mapped PDOs. + * + * \return 0 on success, else < 0 + */ +int ec_sync_add_pdo( + ec_sync_t *sync, /**< EtherCAT sync manager. */ + const ec_pdo_t *pdo /**< PDO to map. */ + ) +{ + return ec_pdo_list_add_pdo_copy(&sync->pdos, pdo); +} + +/****************************************************************************/ + +/** Determines the default direction from the control register. + * + * \return Direction. + */ +ec_direction_t ec_sync_default_direction( + const ec_sync_t *sync /**< EtherCAT sync manager. */ + ) +{ + switch ((sync->control_register & 0x0C) >> 2) { + case 0x0: return EC_DIR_INPUT; + case 0x1: return EC_DIR_OUTPUT; + default: return EC_DIR_INVALID; + } +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sync.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sync.h @@ -0,0 +1,60 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager. + */ + +/****************************************************************************/ + +#ifndef __EC_SYNC_H__ +#define __EC_SYNC_H__ + +#include "globals.h" +#include "pdo_list.h" +#include "sync_config.h" + +/****************************************************************************/ + +/** Sync manager. + */ +typedef struct { + ec_slave_t *slave; /**< Slave, the sync manager belongs to. */ + uint16_t physical_start_address; /**< Physical start address. */ + uint16_t default_length; /**< Data length in bytes. */ + uint8_t control_register; /**< Control register value. */ + uint8_t enable; /**< Enable bit. */ + ec_pdo_list_t pdos; /**< Current PDO assignment. */ +} ec_sync_t; + +/****************************************************************************/ + +void ec_sync_init(ec_sync_t *, ec_slave_t *); +void ec_sync_init_copy(ec_sync_t *, const ec_sync_t *); +void ec_sync_clear(ec_sync_t *); +void ec_sync_page(const ec_sync_t *, uint8_t, uint16_t, + const ec_sync_config_t *, uint8_t, uint8_t *); +int ec_sync_add_pdo(ec_sync_t *, const ec_pdo_t *); +ec_direction_t ec_sync_default_direction(const ec_sync_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sync_config.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sync_config.c @@ -0,0 +1,55 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager configuration methods. + */ + +/****************************************************************************/ + +#include "globals.h" +#include "sync_config.h" + +/****************************************************************************/ + +/** Constructor. + */ +void ec_sync_config_init( + ec_sync_config_t *sync_config /**< Sync manager configuration. */ + ) +{ + sync_config->dir = EC_DIR_INVALID; + sync_config->watchdog_mode = EC_WD_DEFAULT; + ec_pdo_list_init(&sync_config->pdos); +} + +/****************************************************************************/ + +/** Destructor. + */ +void ec_sync_config_clear( + ec_sync_config_t *sync_config /**< Sync manager configuration. */ + ) +{ + ec_pdo_list_clear(&sync_config->pdos); +} + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/sync_config.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/sync_config.h @@ -0,0 +1,51 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * EtherCAT sync manager. + */ + +/****************************************************************************/ + +#ifndef __EC_SYNC_CONFIG_H__ +#define __EC_SYNC_CONFIG_H__ + +#include "globals.h" +#include "pdo_list.h" + +/****************************************************************************/ + +/** Sync manager configuration. + */ +typedef struct { + ec_direction_t dir; /**< Sync manager direction. */ + ec_watchdog_mode_t watchdog_mode; /**< Watchdog mode. */ + ec_pdo_list_t pdos; /**< Current PDO assignment. */ +} ec_sync_config_t; + +/****************************************************************************/ + +void ec_sync_config_init(ec_sync_config_t *); +void ec_sync_config_clear(ec_sync_config_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/voe_handler.c +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/voe_handler.c @@ -0,0 +1,553 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** \file + * Vendor specific over EtherCAT protocol handler functions. + */ + +/****************************************************************************/ + +#include + +#include "master.h" +#include "slave_config.h" +#include "mailbox.h" +#include "voe_handler.h" + +/** VoE header size. + */ +#define EC_VOE_HEADER_SIZE 6 + +/** VoE response timeout in [ms]. + */ +#define EC_VOE_RESPONSE_TIMEOUT 500 + +/****************************************************************************/ + +void ec_voe_handler_state_write_start(ec_voe_handler_t *); +void ec_voe_handler_state_write_response(ec_voe_handler_t *); + +void ec_voe_handler_state_read_start(ec_voe_handler_t *); +void ec_voe_handler_state_read_check(ec_voe_handler_t *); +void ec_voe_handler_state_read_response(ec_voe_handler_t *); + +void ec_voe_handler_state_read_nosync_start(ec_voe_handler_t *); +void ec_voe_handler_state_read_nosync_response(ec_voe_handler_t *); + +void ec_voe_handler_state_end(ec_voe_handler_t *); +void ec_voe_handler_state_error(ec_voe_handler_t *); + +/****************************************************************************/ + +/** VoE handler constructor. + * + * \return Return value of ec_datagram_prealloc(). + */ +int ec_voe_handler_init( + ec_voe_handler_t *voe, /**< VoE handler. */ + ec_slave_config_t *sc, /**< Parent slave configuration. */ + size_t size /**< Size of memory to reserve. */ + ) +{ + voe->config = sc; + voe->vendor_id = 0x00000000; + voe->vendor_type = 0x0000; + voe->data_size = 0; + voe->dir = EC_DIR_INVALID; + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_INIT; + + ec_datagram_init(&voe->datagram); + return ec_datagram_prealloc(&voe->datagram, + size + EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE); +} + +/****************************************************************************/ + +/** VoE handler destructor. + */ +void ec_voe_handler_clear( + ec_voe_handler_t *voe /**< VoE handler. */ + ) +{ + ec_datagram_clear(&voe->datagram); +} + +/****************************************************************************/ + +/** Get usable memory size. + * + * \return Memory size. + */ +size_t ec_voe_handler_mem_size( + const ec_voe_handler_t *voe /**< VoE handler. */ + ) +{ + if (voe->datagram.mem_size >= EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE) + return voe->datagram.mem_size - + (EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE); + else + return 0; +} + +/***************************************************************************** + * Application interface. + ****************************************************************************/ + +int ecrt_voe_handler_send_header(ec_voe_handler_t *voe, uint32_t vendor_id, + uint16_t vendor_type) +{ + voe->vendor_id = vendor_id; + voe->vendor_type = vendor_type; + return 0; +} + +/****************************************************************************/ + +int ecrt_voe_handler_received_header(const ec_voe_handler_t *voe, + uint32_t *vendor_id, uint16_t *vendor_type) +{ + uint8_t *header = voe->datagram.data + EC_MBOX_HEADER_SIZE; + + if (vendor_id) + *vendor_id = EC_READ_U32(header); + if (vendor_type) + *vendor_type = EC_READ_U16(header + 4); + return 0; +} + +/****************************************************************************/ + +uint8_t *ecrt_voe_handler_data(const ec_voe_handler_t *voe) +{ + return voe->datagram.data + EC_MBOX_HEADER_SIZE + EC_VOE_HEADER_SIZE; +} + +/****************************************************************************/ + +size_t ecrt_voe_handler_data_size(const ec_voe_handler_t *voe) +{ + return voe->data_size; +} + +/****************************************************************************/ + +int ecrt_voe_handler_read(ec_voe_handler_t *voe) +{ + voe->dir = EC_DIR_INPUT; + voe->state = ec_voe_handler_state_read_start; + voe->request_state = EC_INT_REQUEST_BUSY; + return 0; +} + +/****************************************************************************/ + +int ecrt_voe_handler_read_nosync(ec_voe_handler_t *voe) +{ + voe->dir = EC_DIR_INPUT; + voe->state = ec_voe_handler_state_read_nosync_start; + voe->request_state = EC_INT_REQUEST_BUSY; + return 0; +} + +/****************************************************************************/ + +int ecrt_voe_handler_write(ec_voe_handler_t *voe, size_t size) +{ + voe->dir = EC_DIR_OUTPUT; + voe->data_size = size; + voe->state = ec_voe_handler_state_write_start; + voe->request_state = EC_INT_REQUEST_BUSY; + return 0; +} + +/****************************************************************************/ + +ec_request_state_t ecrt_voe_handler_execute(ec_voe_handler_t *voe) +{ + if (voe->config->slave) { // FIXME locking? + voe->state(voe); + if (voe->request_state == EC_INT_REQUEST_BUSY) { + ec_master_queue_datagram(voe->config->master, &voe->datagram); + } + } else { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + } + + return ec_request_state_translation_table[voe->request_state]; +} + +/***************************************************************************** + * State functions. + ****************************************************************************/ + +/** Start writing VoE data. + */ +void ec_voe_handler_state_write_start(ec_voe_handler_t *voe) +{ + ec_slave_t *slave = voe->config->slave; + uint8_t *data; + + if (slave->master->debug_level) { + EC_SLAVE_DBG(slave, 0, "Writing %zu bytes of VoE data.\n", + voe->data_size); + ec_print_data(ecrt_voe_handler_data(voe), voe->data_size); + } + + if (!(slave->sii.mailbox_protocols & EC_MBOX_VOE)) { + EC_SLAVE_ERR(slave, "Slave does not support VoE!\n"); + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + data = ec_slave_mbox_prepare_send(slave, &voe->datagram, + EC_MBOX_TYPE_VOE, EC_VOE_HEADER_SIZE + voe->data_size); + if (IS_ERR(data)) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + EC_WRITE_U32(data, voe->vendor_id); + EC_WRITE_U16(data + 4, voe->vendor_type); + /* data already in datagram */ + + voe->retries = EC_FSM_RETRIES; + voe->jiffies_start = jiffies; + voe->state = ec_voe_handler_state_write_response; +} + +/****************************************************************************/ + +/** Wait for the mailbox response. + */ +void ec_voe_handler_state_write_response(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE write request datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + if (!datagram->working_counter) { + unsigned long diff_ms = + (jiffies - voe->jiffies_start) * 1000 / HZ; + if (diff_ms < EC_VOE_RESPONSE_TIMEOUT) { + EC_SLAVE_DBG(slave, 1, "Slave did not respond to" + " VoE write request. Retrying after %lu ms...\n", + diff_ms); + // no response; send request datagram again + return; + } + } + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Reception of VoE write request failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + EC_CONFIG_DBG(voe->config, 1, "VoE write request successful.\n"); + + voe->request_state = EC_INT_REQUEST_SUCCESS; + voe->state = ec_voe_handler_state_end; +} + +/****************************************************************************/ + +/** Start reading VoE data. + */ +void ec_voe_handler_state_read_start(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + EC_SLAVE_DBG(slave, 1, "Reading VoE data.\n"); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_VOE)) { + EC_SLAVE_ERR(slave, "Slave does not support VoE!\n"); + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + + voe->jiffies_start = jiffies; + voe->retries = EC_FSM_RETRIES; + voe->state = ec_voe_handler_state_read_check; +} + +/****************************************************************************/ + +/** Check for new data in the mailbox. + */ +void ec_voe_handler_state_read_check(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE mailbox check datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Reception of VoE mailbox check" + " datagram failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + if (!ec_slave_mbox_check(datagram)) { + unsigned long diff_ms = + (datagram->jiffies_received - voe->jiffies_start) * 1000 / HZ; + if (diff_ms >= EC_VOE_RESPONSE_TIMEOUT) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Timeout while waiting for VoE data.\n"); + return; + } + + ec_slave_mbox_prepare_check(slave, datagram); // can not fail. + voe->retries = EC_FSM_RETRIES; + return; + } + + // Fetch response + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + voe->retries = EC_FSM_RETRIES; + voe->state = ec_voe_handler_state_read_response; +} + +/****************************************************************************/ + +/** Read the pending mailbox data. + */ +void ec_voe_handler_state_read_response(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + ec_master_t *master = voe->config->master; + uint8_t *data, mbox_prot; + size_t rec_size; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE read datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter != 1) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Reception of VoE read response failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + data = ec_slave_mbox_fetch(slave, datagram, &mbox_prot, &rec_size); + if (IS_ERR(data)) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_VOE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_WARN(slave, "Received mailbox protocol 0x%02X" + " as response.\n", mbox_prot); + ec_print_data(data, rec_size); + return; + } + + if (rec_size < EC_VOE_HEADER_SIZE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Received VoE header is" + " incomplete (%zu bytes)!\n", rec_size); + return; + } + + if (master->debug_level) { + EC_CONFIG_DBG(voe->config, 0, "VoE data:\n"); + ec_print_data(data, rec_size); + } + + voe->data_size = rec_size - EC_VOE_HEADER_SIZE; + voe->request_state = EC_INT_REQUEST_SUCCESS; + voe->state = ec_voe_handler_state_end; // success +} + +/****************************************************************************/ + +/** Start reading VoE data without sending a sync message before. + */ +void ec_voe_handler_state_read_nosync_start(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + + EC_SLAVE_DBG(slave, 1, "Reading VoE data.\n"); + + if (!(slave->sii.mailbox_protocols & EC_MBOX_VOE)) { + EC_SLAVE_ERR(slave, "Slave does not support VoE!\n"); + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + ec_slave_mbox_prepare_fetch(slave, datagram); // can not fail. + + voe->jiffies_start = jiffies; + voe->retries = EC_FSM_RETRIES; + voe->state = ec_voe_handler_state_read_nosync_response; +} + +/****************************************************************************/ + +/** Read the pending mailbox data without sending a sync message before. This + * might lead to an empty reponse from the client. + */ +void ec_voe_handler_state_read_nosync_response(ec_voe_handler_t *voe) +{ + ec_datagram_t *datagram = &voe->datagram; + ec_slave_t *slave = voe->config->slave; + ec_master_t *master = voe->config->master; + uint8_t *data, mbox_prot; + size_t rec_size; + + if (datagram->state == EC_DATAGRAM_TIMED_OUT && voe->retries--) + return; + + if (datagram->state != EC_DATAGRAM_RECEIVED) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Failed to receive VoE read datagram: "); + ec_datagram_print_state(datagram); + return; + } + + if (datagram->working_counter == 0) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_DBG(slave, 1, "Slave did not send VoE data.\n"); + return; + } + + if (datagram->working_counter != 1) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_WARN(slave, "Reception of VoE read response failed: "); + ec_datagram_print_wc_error(datagram); + return; + } + + if (!(data = ec_slave_mbox_fetch(slave, datagram, + &mbox_prot, &rec_size))) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + return; + } + + if (mbox_prot != EC_MBOX_TYPE_VOE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_WARN(slave, "Received mailbox protocol 0x%02X" + " as response.\n", mbox_prot); + ec_print_data(data, rec_size); + return; + } + + if (rec_size < EC_VOE_HEADER_SIZE) { + voe->state = ec_voe_handler_state_error; + voe->request_state = EC_INT_REQUEST_FAILURE; + EC_SLAVE_ERR(slave, "Received VoE header is" + " incomplete (%zu bytes)!\n", rec_size); + return; + } + + if (master->debug_level) { + EC_CONFIG_DBG(voe->config, 1, "VoE data:\n"); + ec_print_data(data, rec_size); + } + + voe->data_size = rec_size - EC_VOE_HEADER_SIZE; + voe->request_state = EC_INT_REQUEST_SUCCESS; + voe->state = ec_voe_handler_state_end; // success +} + +/****************************************************************************/ + +/** Successful termination state function. + */ +void ec_voe_handler_state_end(ec_voe_handler_t *voe) +{ +} + +/****************************************************************************/ + +/** Failure termination state function. + */ +void ec_voe_handler_state_error(ec_voe_handler_t *voe) +{ +} + +/****************************************************************************/ + +/** \cond */ + +EXPORT_SYMBOL(ecrt_voe_handler_send_header); +EXPORT_SYMBOL(ecrt_voe_handler_received_header); +EXPORT_SYMBOL(ecrt_voe_handler_data); +EXPORT_SYMBOL(ecrt_voe_handler_data_size); +EXPORT_SYMBOL(ecrt_voe_handler_read); +EXPORT_SYMBOL(ecrt_voe_handler_write); +EXPORT_SYMBOL(ecrt_voe_handler_execute); + +/** \endcond */ + +/****************************************************************************/ --- linux-nvidia-7.0.0.orig/ubuntu/igh-ecat/master/voe_handler.h +++ linux-nvidia-7.0.0/ubuntu/igh-ecat/master/voe_handler.h @@ -0,0 +1,65 @@ +/***************************************************************************** + * + * Copyright (C) 2006-2008 Florian Pose, Ingenieurgemeinschaft IgH + * + * This file is part of the IgH EtherCAT Master. + * + * The IgH EtherCAT Master is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * The IgH EtherCAT Master is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the IgH EtherCAT Master; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + ****************************************************************************/ + +/** + \file + Vendor specific over EtherCAT protocol handler. +*/ + +/****************************************************************************/ + +#ifndef __EC_VOE_HANDLER_H__ +#define __EC_VOE_HANDLER_H__ + +#include + +#include "globals.h" +#include "datagram.h" + +/****************************************************************************/ + +/** Vendor specific over EtherCAT handler. + */ +struct ec_voe_handler { + struct list_head list; /**< List item. */ + ec_slave_config_t *config; /**< Parent slave configuration. */ + ec_datagram_t datagram; /**< State machine datagram. */ + uint32_t vendor_id; /**< Vendor ID for the header. */ + uint16_t vendor_type; /**< Vendor type for the header. */ + size_t data_size; /**< Size of VoE data. */ + ec_direction_t dir; /**< Direction. EC_DIR_OUTPUT means writing to + the slave, EC_DIR_INPUT means reading from the + slave. */ + void (*state)(ec_voe_handler_t *); /**< State function */ + ec_internal_request_state_t request_state; /**< Handler state. */ + unsigned int retries; /**< retries upon datagram timeout */ + unsigned long jiffies_start; /**< Timestamp for timeout calculation. */ +}; + +/****************************************************************************/ + +int ec_voe_handler_init(ec_voe_handler_t *, ec_slave_config_t *, size_t); +void ec_voe_handler_clear(ec_voe_handler_t *); +size_t ec_voe_handler_mem_size(const ec_voe_handler_t *); + +/****************************************************************************/ + +#endif --- linux-nvidia-7.0.0.orig/ubuntu/include/Kbuild +++ linux-nvidia-7.0.0/ubuntu/include/Kbuild @@ -0,0 +1,2 @@ + + --- linux-nvidia-7.0.0.orig/ubuntu/include/README +++ linux-nvidia-7.0.0/ubuntu/include/README @@ -0,0 +1,4 @@ +Only use this directory for things which need to share their headers with +other parts of the kernel or other modules in ubuntu/ + +Otherwise, keep them local to the module directory. --- linux-nvidia-7.0.0.orig/ubuntu/ubuntu-host/Kconfig +++ linux-nvidia-7.0.0/ubuntu/ubuntu-host/Kconfig @@ -0,0 +1,5 @@ +config UBUNTU_HOST + tristate "proc dir for exporting host data to containers" + help + Creates an ubuntu-host directory in proc for providing data from + Ubuntu hosts to containers. --- linux-nvidia-7.0.0.orig/ubuntu/ubuntu-host/Makefile +++ linux-nvidia-7.0.0/ubuntu/ubuntu-host/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_UBUNTU_HOST) += ubuntu-host.o --- linux-nvidia-7.0.0.orig/ubuntu/ubuntu-host/ubuntu-host.c +++ linux-nvidia-7.0.0/ubuntu/ubuntu-host/ubuntu-host.c @@ -0,0 +1,68 @@ +#include +#include +#include +#include +#include + +#define PROC_DIR "ubuntu-host" + +#define ESM_TOKEN_FILE "esm-token" +#define ESM_TOKEN_MAX_SIZE 64 + +static struct proc_dir_entry *proc_dir; +static char esm_token_buffer[ESM_TOKEN_MAX_SIZE]; + +static ssize_t esm_token_read(struct file *f, char __user *buf, size_t len, + loff_t *off) +{ + return simple_read_from_buffer(buf, len, off, esm_token_buffer, + strlen(esm_token_buffer)); +} + +static ssize_t esm_token_write(struct file *f, const char __user *buf, + size_t len, loff_t *off) +{ + ssize_t ret; + + if (len >= ESM_TOKEN_MAX_SIZE - 1) + return -EINVAL; + + ret = simple_write_to_buffer(esm_token_buffer, ESM_TOKEN_MAX_SIZE - 1, + off, buf, len); + if (ret >= 0) + esm_token_buffer[ret] = '\0'; + + return ret; +} + +static const struct proc_ops esm_token_fops = { + .proc_read = esm_token_read, + .proc_write = esm_token_write, +}; + +static void ubuntu_host_cleanup(void) +{ + remove_proc_entry(ESM_TOKEN_FILE, proc_dir); + proc_remove(proc_dir); +} + +static int __init ubuntu_host_init(void) +{ + proc_dir = proc_mkdir(PROC_DIR, NULL); + if (!proc_dir) { + pr_err("Failed to create ubuntu-host dir\n"); + return -ENOMEM; + } + + if (!proc_create_data(ESM_TOKEN_FILE, 0644, proc_dir, &esm_token_fops, NULL)) { + pr_err("Failed to create esm-tokan file\n"); + ubuntu_host_cleanup(); + return -ENOMEM; + } + + return 0; +} + +module_init(ubuntu_host_init); +module_exit(ubuntu_host_cleanup); +MODULE_LICENSE("GPL");